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Commit | Line | Data |
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abfa3df3 JC |
1 | /* |
2 | * The Marvell camera core. This device appears in a number of settings, | |
3 | * so it needs platform-specific support outside of the core. | |
4 | * | |
5 | * Copyright 2011 Jonathan Corbet corbet@lwn.net | |
6 | */ | |
7 | #include <linux/kernel.h> | |
8 | #include <linux/module.h> | |
9 | #include <linux/fs.h> | |
abfa3df3 JC |
10 | #include <linux/mm.h> |
11 | #include <linux/i2c.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/spinlock.h> | |
abfa3df3 | 14 | #include <linux/slab.h> |
abfa3df3 JC |
15 | #include <linux/device.h> |
16 | #include <linux/wait.h> | |
17 | #include <linux/list.h> | |
18 | #include <linux/dma-mapping.h> | |
19 | #include <linux/delay.h> | |
abfa3df3 | 20 | #include <linux/vmalloc.h> |
abfa3df3 | 21 | #include <linux/io.h> |
05fed816 | 22 | #include <linux/clk.h> |
362d45b2 JC |
23 | #include <linux/videodev2.h> |
24 | #include <media/v4l2-device.h> | |
25 | #include <media/v4l2-ioctl.h> | |
593403c5 | 26 | #include <media/v4l2-ctrls.h> |
87d18430 | 27 | #include <media/v4l2-event.h> |
b5dcee22 | 28 | #include <media/i2c/ov7670.h> |
362d45b2 | 29 | #include <media/videobuf2-vmalloc.h> |
a9b36e85 | 30 | #include <media/videobuf2-dma-contig.h> |
cbc4f3a2 | 31 | #include <media/videobuf2-dma-sg.h> |
abfa3df3 JC |
32 | |
33 | #include "mcam-core.h" | |
34 | ||
7498469f | 35 | #ifdef MCAM_MODE_VMALLOC |
abfa3df3 JC |
36 | /* |
37 | * Internal DMA buffer management. Since the controller cannot do S/G I/O, | |
38 | * we must have physically contiguous buffers to bring frames into. | |
39 | * These parameters control how many buffers we use, whether we | |
40 | * allocate them at load time (better chance of success, but nails down | |
41 | * memory) or when somebody tries to use the camera (riskier), and, | |
42 | * for load-time allocation, how big they should be. | |
43 | * | |
44 | * The controller can cycle through three buffers. We could use | |
45 | * more by flipping pointers around, but it probably makes little | |
46 | * sense. | |
47 | */ | |
48 | ||
90ab5ee9 | 49 | static bool alloc_bufs_at_read; |
abfa3df3 JC |
50 | module_param(alloc_bufs_at_read, bool, 0444); |
51 | MODULE_PARM_DESC(alloc_bufs_at_read, | |
52 | "Non-zero value causes DMA buffers to be allocated when the " | |
53 | "video capture device is read, rather than at module load " | |
54 | "time. This saves memory, but decreases the chances of " | |
a9b36e85 JC |
55 | "successfully getting those buffers. This parameter is " |
56 | "only used in the vmalloc buffer mode"); | |
abfa3df3 JC |
57 | |
58 | static int n_dma_bufs = 3; | |
59 | module_param(n_dma_bufs, uint, 0644); | |
60 | MODULE_PARM_DESC(n_dma_bufs, | |
61 | "The number of DMA buffers to allocate. Can be either two " | |
62 | "(saves memory, makes timing tighter) or three."); | |
63 | ||
64 | static int dma_buf_size = VGA_WIDTH * VGA_HEIGHT * 2; /* Worst case */ | |
65 | module_param(dma_buf_size, uint, 0444); | |
66 | MODULE_PARM_DESC(dma_buf_size, | |
67 | "The size of the allocated DMA buffers. If actual operating " | |
68 | "parameters require larger buffers, an attempt to reallocate " | |
69 | "will be made."); | |
7498469f | 70 | #else /* MCAM_MODE_VMALLOC */ |
a7459a9d | 71 | static const bool alloc_bufs_at_read; |
7498469f JC |
72 | static const int n_dma_bufs = 3; /* Used by S/G_PARM */ |
73 | #endif /* MCAM_MODE_VMALLOC */ | |
abfa3df3 | 74 | |
90ab5ee9 | 75 | static bool flip; |
abfa3df3 JC |
76 | module_param(flip, bool, 0444); |
77 | MODULE_PARM_DESC(flip, | |
78 | "If set, the sensor will be instructed to flip the image " | |
79 | "vertically."); | |
80 | ||
a9b36e85 JC |
81 | static int buffer_mode = -1; |
82 | module_param(buffer_mode, int, 0444); | |
83 | MODULE_PARM_DESC(buffer_mode, | |
84 | "Set the buffer mode to be used; default is to go with what " | |
85 | "the platform driver asks for. Set to 0 for vmalloc, 1 for " | |
86 | "DMA contiguous."); | |
87 | ||
abfa3df3 JC |
88 | /* |
89 | * Status flags. Always manipulated with bit operations. | |
90 | */ | |
91 | #define CF_BUF0_VALID 0 /* Buffers valid - first three */ | |
92 | #define CF_BUF1_VALID 1 | |
93 | #define CF_BUF2_VALID 2 | |
94 | #define CF_DMA_ACTIVE 3 /* A frame is incoming */ | |
95 | #define CF_CONFIG_NEEDED 4 /* Must configure hardware */ | |
a9b36e85 | 96 | #define CF_SINGLE_BUFFER 5 /* Running with a single buffer */ |
cbc4f3a2 | 97 | #define CF_SG_RESTART 6 /* SG restart needed */ |
0a0b3fb4 LY |
98 | #define CF_FRAME_SOF0 7 /* Frame 0 started */ |
99 | #define CF_FRAME_SOF1 8 | |
100 | #define CF_FRAME_SOF2 9 | |
abfa3df3 JC |
101 | |
102 | #define sensor_call(cam, o, f, args...) \ | |
103 | v4l2_subdev_call(cam->sensor, o, f, ##args) | |
104 | ||
105 | static struct mcam_format_struct { | |
106 | __u8 *desc; | |
107 | __u32 pixelformat; | |
108 | int bpp; /* Bytes per pixel */ | |
ad6ac452 | 109 | bool planar; |
27ffaeb0 | 110 | u32 mbus_code; |
abfa3df3 JC |
111 | } mcam_formats[] = { |
112 | { | |
113 | .desc = "YUYV 4:2:2", | |
114 | .pixelformat = V4L2_PIX_FMT_YUYV, | |
27ffaeb0 | 115 | .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, |
abfa3df3 | 116 | .bpp = 2, |
ad6ac452 LY |
117 | .planar = false, |
118 | }, | |
119 | { | |
2a700d8e HV |
120 | .desc = "YVYU 4:2:2", |
121 | .pixelformat = V4L2_PIX_FMT_YVYU, | |
27ffaeb0 | 122 | .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, |
ad6ac452 LY |
123 | .bpp = 2, |
124 | .planar = false, | |
125 | }, | |
ad6ac452 LY |
126 | { |
127 | .desc = "YUV 4:2:0 PLANAR", | |
128 | .pixelformat = V4L2_PIX_FMT_YUV420, | |
27ffaeb0 | 129 | .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, |
47ba7dba | 130 | .bpp = 1, |
ad6ac452 LY |
131 | .planar = true, |
132 | }, | |
133 | { | |
134 | .desc = "YVU 4:2:0 PLANAR", | |
135 | .pixelformat = V4L2_PIX_FMT_YVU420, | |
27ffaeb0 | 136 | .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, |
47ba7dba | 137 | .bpp = 1, |
ad6ac452 | 138 | .planar = true, |
abfa3df3 JC |
139 | }, |
140 | { | |
ccf509f8 HV |
141 | .desc = "XRGB 444", |
142 | .pixelformat = V4L2_PIX_FMT_XRGB444, | |
27ffaeb0 | 143 | .mbus_code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE, |
abfa3df3 | 144 | .bpp = 2, |
ad6ac452 | 145 | .planar = false, |
abfa3df3 JC |
146 | }, |
147 | { | |
148 | .desc = "RGB 565", | |
149 | .pixelformat = V4L2_PIX_FMT_RGB565, | |
27ffaeb0 | 150 | .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE, |
abfa3df3 | 151 | .bpp = 2, |
ad6ac452 | 152 | .planar = false, |
abfa3df3 JC |
153 | }, |
154 | { | |
155 | .desc = "Raw RGB Bayer", | |
156 | .pixelformat = V4L2_PIX_FMT_SBGGR8, | |
27ffaeb0 | 157 | .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, |
ad6ac452 LY |
158 | .bpp = 1, |
159 | .planar = false, | |
abfa3df3 JC |
160 | }, |
161 | }; | |
162 | #define N_MCAM_FMTS ARRAY_SIZE(mcam_formats) | |
163 | ||
164 | static struct mcam_format_struct *mcam_find_format(u32 pixelformat) | |
165 | { | |
166 | unsigned i; | |
167 | ||
168 | for (i = 0; i < N_MCAM_FMTS; i++) | |
169 | if (mcam_formats[i].pixelformat == pixelformat) | |
170 | return mcam_formats + i; | |
171 | /* Not found? Then return the first format. */ | |
172 | return mcam_formats; | |
173 | } | |
174 | ||
175 | /* | |
d43dae75 | 176 | * The default format we use until somebody says otherwise. |
abfa3df3 | 177 | */ |
d43dae75 JC |
178 | static const struct v4l2_pix_format mcam_def_pix_format = { |
179 | .width = VGA_WIDTH, | |
180 | .height = VGA_HEIGHT, | |
181 | .pixelformat = V4L2_PIX_FMT_YUYV, | |
182 | .field = V4L2_FIELD_NONE, | |
183 | .bytesperline = VGA_WIDTH*2, | |
184 | .sizeimage = VGA_WIDTH*VGA_HEIGHT*2, | |
2e6e6095 | 185 | .colorspace = V4L2_COLORSPACE_SRGB, |
d43dae75 | 186 | }; |
abfa3df3 | 187 | |
27ffaeb0 | 188 | static const u32 mcam_def_mbus_code = MEDIA_BUS_FMT_YUYV8_2X8; |
abfa3df3 | 189 | |
abfa3df3 | 190 | |
cbc4f3a2 JC |
191 | /* |
192 | * The two-word DMA descriptor format used by the Armada 610 and like. There | |
193 | * Is a three-word format as well (set C1_DESC_3WORD) where the third | |
194 | * word is a pointer to the next descriptor, but we don't use it. Two-word | |
195 | * descriptors have to be contiguous in memory. | |
196 | */ | |
197 | struct mcam_dma_desc { | |
198 | u32 dma_addr; | |
199 | u32 segment_len; | |
200 | }; | |
201 | ||
b5210fd2 JC |
202 | /* |
203 | * Our buffer type for working with videobuf2. Note that the vb2 | |
2d700715 | 204 | * developers have decreed that struct vb2_v4l2_buffer must be at the |
b5210fd2 JC |
205 | * beginning of this structure. |
206 | */ | |
207 | struct mcam_vb_buffer { | |
2d700715 | 208 | struct vb2_v4l2_buffer vb_buf; |
b5210fd2 | 209 | struct list_head queue; |
cbc4f3a2 JC |
210 | struct mcam_dma_desc *dma_desc; /* Descriptor virtual address */ |
211 | dma_addr_t dma_desc_pa; /* Descriptor physical address */ | |
212 | int dma_desc_nent; /* Number of mapped descriptors */ | |
b5210fd2 JC |
213 | }; |
214 | ||
2d700715 | 215 | static inline struct mcam_vb_buffer *vb_to_mvb(struct vb2_v4l2_buffer *vb) |
b5210fd2 JC |
216 | { |
217 | return container_of(vb, struct mcam_vb_buffer, vb_buf); | |
218 | } | |
219 | ||
d43dae75 JC |
220 | /* |
221 | * Hand a completed buffer back to user space. | |
222 | */ | |
223 | static void mcam_buffer_done(struct mcam_camera *cam, int frame, | |
2d700715 | 224 | struct vb2_v4l2_buffer *vbuf) |
d43dae75 | 225 | { |
2d700715 JS |
226 | vbuf->vb2_buf.planes[0].bytesused = cam->pix_format.sizeimage; |
227 | vbuf->sequence = cam->buf_seq[frame]; | |
228 | vbuf->field = V4L2_FIELD_NONE; | |
d6dd645e | 229 | vbuf->vb2_buf.timestamp = ktime_get_ns(); |
2d700715 JS |
230 | vb2_set_plane_payload(&vbuf->vb2_buf, 0, cam->pix_format.sizeimage); |
231 | vb2_buffer_done(&vbuf->vb2_buf, VB2_BUF_STATE_DONE); | |
d43dae75 JC |
232 | } |
233 | ||
234 | ||
abfa3df3 JC |
235 | |
236 | /* | |
67a8dbbc | 237 | * Debugging and related. |
abfa3df3 JC |
238 | */ |
239 | #define cam_err(cam, fmt, arg...) \ | |
240 | dev_err((cam)->dev, fmt, ##arg); | |
241 | #define cam_warn(cam, fmt, arg...) \ | |
242 | dev_warn((cam)->dev, fmt, ##arg); | |
243 | #define cam_dbg(cam, fmt, arg...) \ | |
244 | dev_dbg((cam)->dev, fmt, ##arg); | |
245 | ||
246 | ||
d43dae75 JC |
247 | /* |
248 | * Flag manipulation helpers | |
249 | */ | |
250 | static void mcam_reset_buffers(struct mcam_camera *cam) | |
251 | { | |
252 | int i; | |
253 | ||
254 | cam->next_buf = -1; | |
0a0b3fb4 | 255 | for (i = 0; i < cam->nbufs; i++) { |
d43dae75 | 256 | clear_bit(i, &cam->flags); |
0a0b3fb4 LY |
257 | clear_bit(CF_FRAME_SOF0 + i, &cam->flags); |
258 | } | |
d43dae75 JC |
259 | } |
260 | ||
261 | static inline int mcam_needs_config(struct mcam_camera *cam) | |
262 | { | |
263 | return test_bit(CF_CONFIG_NEEDED, &cam->flags); | |
264 | } | |
265 | ||
266 | static void mcam_set_config_needed(struct mcam_camera *cam, int needed) | |
267 | { | |
268 | if (needed) | |
269 | set_bit(CF_CONFIG_NEEDED, &cam->flags); | |
270 | else | |
271 | clear_bit(CF_CONFIG_NEEDED, &cam->flags); | |
272 | } | |
abfa3df3 JC |
273 | |
274 | /* ------------------------------------------------------------------- */ | |
275 | /* | |
d43dae75 JC |
276 | * Make the controller start grabbing images. Everything must |
277 | * be set up before doing this. | |
abfa3df3 | 278 | */ |
d43dae75 JC |
279 | static void mcam_ctlr_start(struct mcam_camera *cam) |
280 | { | |
281 | /* set_bit performs a read, so no other barrier should be | |
282 | needed here */ | |
283 | mcam_reg_set_bit(cam, REG_CTRL0, C0_ENABLE); | |
284 | } | |
285 | ||
286 | static void mcam_ctlr_stop(struct mcam_camera *cam) | |
287 | { | |
288 | mcam_reg_clear_bit(cam, REG_CTRL0, C0_ENABLE); | |
289 | } | |
290 | ||
05fed816 LY |
291 | static void mcam_enable_mipi(struct mcam_camera *mcam) |
292 | { | |
293 | /* Using MIPI mode and enable MIPI */ | |
294 | cam_dbg(mcam, "camera: DPHY3=0x%x, DPHY5=0x%x, DPHY6=0x%x\n", | |
295 | mcam->dphy[0], mcam->dphy[1], mcam->dphy[2]); | |
296 | mcam_reg_write(mcam, REG_CSI2_DPHY3, mcam->dphy[0]); | |
297 | mcam_reg_write(mcam, REG_CSI2_DPHY5, mcam->dphy[1]); | |
298 | mcam_reg_write(mcam, REG_CSI2_DPHY6, mcam->dphy[2]); | |
299 | ||
300 | if (!mcam->mipi_enabled) { | |
301 | if (mcam->lane > 4 || mcam->lane <= 0) { | |
302 | cam_warn(mcam, "lane number error\n"); | |
303 | mcam->lane = 1; /* set the default value */ | |
304 | } | |
305 | /* | |
306 | * 0x41 actives 1 lane | |
307 | * 0x43 actives 2 lanes | |
308 | * 0x45 actives 3 lanes (never happen) | |
309 | * 0x47 actives 4 lanes | |
310 | */ | |
311 | mcam_reg_write(mcam, REG_CSI2_CTRL0, | |
312 | CSI2_C0_MIPI_EN | CSI2_C0_ACT_LANE(mcam->lane)); | |
313 | mcam_reg_write(mcam, REG_CLKCTRL, | |
314 | (mcam->mclk_src << 29) | mcam->mclk_div); | |
315 | ||
316 | mcam->mipi_enabled = true; | |
317 | } | |
318 | } | |
319 | ||
320 | static void mcam_disable_mipi(struct mcam_camera *mcam) | |
321 | { | |
322 | /* Using Parallel mode or disable MIPI */ | |
323 | mcam_reg_write(mcam, REG_CSI2_CTRL0, 0x0); | |
324 | mcam_reg_write(mcam, REG_CSI2_DPHY3, 0x0); | |
325 | mcam_reg_write(mcam, REG_CSI2_DPHY5, 0x0); | |
326 | mcam_reg_write(mcam, REG_CSI2_DPHY6, 0x0); | |
327 | mcam->mipi_enabled = false; | |
328 | } | |
329 | ||
6eb40d59 HV |
330 | static bool mcam_fmt_is_planar(__u32 pfmt) |
331 | { | |
332 | struct mcam_format_struct *f; | |
333 | ||
334 | f = mcam_find_format(pfmt); | |
335 | return f->planar; | |
336 | } | |
337 | ||
338 | static void mcam_write_yuv_bases(struct mcam_camera *cam, | |
339 | unsigned frame, dma_addr_t base) | |
340 | { | |
341 | struct v4l2_pix_format *fmt = &cam->pix_format; | |
342 | u32 pixel_count = fmt->width * fmt->height; | |
343 | dma_addr_t y, u = 0, v = 0; | |
344 | ||
345 | y = base; | |
346 | ||
347 | switch (fmt->pixelformat) { | |
6eb40d59 HV |
348 | case V4L2_PIX_FMT_YUV420: |
349 | u = y + pixel_count; | |
350 | v = u + pixel_count / 4; | |
351 | break; | |
352 | case V4L2_PIX_FMT_YVU420: | |
353 | v = y + pixel_count; | |
354 | u = v + pixel_count / 4; | |
355 | break; | |
356 | default: | |
357 | break; | |
358 | } | |
359 | ||
360 | mcam_reg_write(cam, REG_Y0BAR + frame * 4, y); | |
361 | if (mcam_fmt_is_planar(fmt->pixelformat)) { | |
362 | mcam_reg_write(cam, REG_U0BAR + frame * 4, u); | |
363 | mcam_reg_write(cam, REG_V0BAR + frame * 4, v); | |
364 | } | |
365 | } | |
366 | ||
d43dae75 | 367 | /* ------------------------------------------------------------------- */ |
7498469f JC |
368 | |
369 | #ifdef MCAM_MODE_VMALLOC | |
d43dae75 JC |
370 | /* |
371 | * Code specific to the vmalloc buffer mode. | |
372 | */ | |
373 | ||
374 | /* | |
375 | * Allocate in-kernel DMA buffers for vmalloc mode. | |
376 | */ | |
377 | static int mcam_alloc_dma_bufs(struct mcam_camera *cam, int loadtime) | |
378 | { | |
379 | int i; | |
380 | ||
381 | mcam_set_config_needed(cam, 1); | |
382 | if (loadtime) | |
383 | cam->dma_buf_size = dma_buf_size; | |
384 | else | |
385 | cam->dma_buf_size = cam->pix_format.sizeimage; | |
386 | if (n_dma_bufs > 3) | |
387 | n_dma_bufs = 3; | |
388 | ||
389 | cam->nbufs = 0; | |
390 | for (i = 0; i < n_dma_bufs; i++) { | |
391 | cam->dma_bufs[i] = dma_alloc_coherent(cam->dev, | |
392 | cam->dma_buf_size, cam->dma_handles + i, | |
393 | GFP_KERNEL); | |
394 | if (cam->dma_bufs[i] == NULL) { | |
395 | cam_warn(cam, "Failed to allocate DMA buffer\n"); | |
396 | break; | |
397 | } | |
398 | (cam->nbufs)++; | |
399 | } | |
400 | ||
401 | switch (cam->nbufs) { | |
402 | case 1: | |
403 | dma_free_coherent(cam->dev, cam->dma_buf_size, | |
404 | cam->dma_bufs[0], cam->dma_handles[0]); | |
405 | cam->nbufs = 0; | |
406 | case 0: | |
407 | cam_err(cam, "Insufficient DMA buffers, cannot operate\n"); | |
408 | return -ENOMEM; | |
409 | ||
410 | case 2: | |
411 | if (n_dma_bufs > 2) | |
412 | cam_warn(cam, "Will limp along with only 2 buffers\n"); | |
413 | break; | |
414 | } | |
415 | return 0; | |
416 | } | |
417 | ||
418 | static void mcam_free_dma_bufs(struct mcam_camera *cam) | |
419 | { | |
420 | int i; | |
421 | ||
422 | for (i = 0; i < cam->nbufs; i++) { | |
423 | dma_free_coherent(cam->dev, cam->dma_buf_size, | |
424 | cam->dma_bufs[i], cam->dma_handles[i]); | |
425 | cam->dma_bufs[i] = NULL; | |
426 | } | |
427 | cam->nbufs = 0; | |
428 | } | |
429 | ||
abfa3df3 JC |
430 | |
431 | /* | |
a9b36e85 | 432 | * Set up DMA buffers when operating in vmalloc mode |
abfa3df3 | 433 | */ |
a9b36e85 | 434 | static void mcam_ctlr_dma_vmalloc(struct mcam_camera *cam) |
abfa3df3 JC |
435 | { |
436 | /* | |
6eb40d59 | 437 | * Store the first two YUV buffers. Then either |
abfa3df3 JC |
438 | * set the third if it exists, or tell the controller |
439 | * to just use two. | |
440 | */ | |
6eb40d59 HV |
441 | mcam_write_yuv_bases(cam, 0, cam->dma_handles[0]); |
442 | mcam_write_yuv_bases(cam, 1, cam->dma_handles[1]); | |
abfa3df3 | 443 | if (cam->nbufs > 2) { |
6eb40d59 | 444 | mcam_write_yuv_bases(cam, 2, cam->dma_handles[2]); |
abfa3df3 JC |
445 | mcam_reg_clear_bit(cam, REG_CTRL1, C1_TWOBUFS); |
446 | } else | |
447 | mcam_reg_set_bit(cam, REG_CTRL1, C1_TWOBUFS); | |
7486af1a | 448 | if (cam->chip_id == MCAM_CAFE) |
67a8dbbc | 449 | mcam_reg_write(cam, REG_UBAR, 0); /* 32 bits only */ |
abfa3df3 JC |
450 | } |
451 | ||
d43dae75 JC |
452 | /* |
453 | * Copy data out to user space in the vmalloc case | |
454 | */ | |
455 | static void mcam_frame_tasklet(unsigned long data) | |
456 | { | |
457 | struct mcam_camera *cam = (struct mcam_camera *) data; | |
458 | int i; | |
459 | unsigned long flags; | |
460 | struct mcam_vb_buffer *buf; | |
461 | ||
462 | spin_lock_irqsave(&cam->dev_lock, flags); | |
463 | for (i = 0; i < cam->nbufs; i++) { | |
464 | int bufno = cam->next_buf; | |
465 | ||
466 | if (cam->state != S_STREAMING || bufno < 0) | |
467 | break; /* I/O got stopped */ | |
468 | if (++(cam->next_buf) >= cam->nbufs) | |
469 | cam->next_buf = 0; | |
470 | if (!test_bit(bufno, &cam->flags)) | |
471 | continue; | |
472 | if (list_empty(&cam->buffers)) { | |
f698957a | 473 | cam->frame_state.singles++; |
d43dae75 JC |
474 | break; /* Leave it valid, hope for better later */ |
475 | } | |
f698957a | 476 | cam->frame_state.delivered++; |
d43dae75 JC |
477 | clear_bit(bufno, &cam->flags); |
478 | buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer, | |
479 | queue); | |
480 | list_del_init(&buf->queue); | |
481 | /* | |
482 | * Drop the lock during the big copy. This *should* be safe... | |
483 | */ | |
484 | spin_unlock_irqrestore(&cam->dev_lock, flags); | |
2d700715 JS |
485 | memcpy(vb2_plane_vaddr(&buf->vb_buf.vb2_buf, 0), |
486 | cam->dma_bufs[bufno], | |
d43dae75 JC |
487 | cam->pix_format.sizeimage); |
488 | mcam_buffer_done(cam, bufno, &buf->vb_buf); | |
489 | spin_lock_irqsave(&cam->dev_lock, flags); | |
490 | } | |
491 | spin_unlock_irqrestore(&cam->dev_lock, flags); | |
492 | } | |
493 | ||
494 | ||
7498469f JC |
495 | /* |
496 | * Make sure our allocated buffers are up to the task. | |
497 | */ | |
498 | static int mcam_check_dma_buffers(struct mcam_camera *cam) | |
499 | { | |
500 | if (cam->nbufs > 0 && cam->dma_buf_size < cam->pix_format.sizeimage) | |
501 | mcam_free_dma_bufs(cam); | |
502 | if (cam->nbufs == 0) | |
503 | return mcam_alloc_dma_bufs(cam, 0); | |
504 | return 0; | |
505 | } | |
506 | ||
507 | static void mcam_vmalloc_done(struct mcam_camera *cam, int frame) | |
508 | { | |
509 | tasklet_schedule(&cam->s_tasklet); | |
510 | } | |
511 | ||
512 | #else /* MCAM_MODE_VMALLOC */ | |
513 | ||
514 | static inline int mcam_alloc_dma_bufs(struct mcam_camera *cam, int loadtime) | |
515 | { | |
516 | return 0; | |
517 | } | |
518 | ||
519 | static inline void mcam_free_dma_bufs(struct mcam_camera *cam) | |
520 | { | |
521 | return; | |
522 | } | |
523 | ||
524 | static inline int mcam_check_dma_buffers(struct mcam_camera *cam) | |
525 | { | |
526 | return 0; | |
527 | } | |
528 | ||
529 | ||
530 | ||
531 | #endif /* MCAM_MODE_VMALLOC */ | |
532 | ||
533 | ||
534 | #ifdef MCAM_MODE_DMA_CONTIG | |
d43dae75 JC |
535 | /* ---------------------------------------------------------------------- */ |
536 | /* | |
537 | * DMA-contiguous code. | |
538 | */ | |
ad6ac452 | 539 | |
a9b36e85 JC |
540 | /* |
541 | * Set up a contiguous buffer for the given frame. Here also is where | |
542 | * the underrun strategy is set: if there is no buffer available, reuse | |
543 | * the buffer from the other BAR and set the CF_SINGLE_BUFFER flag to | |
544 | * keep the interrupt handler from giving that buffer back to user | |
545 | * space. In this way, we always have a buffer to DMA to and don't | |
546 | * have to try to play games stopping and restarting the controller. | |
547 | */ | |
548 | static void mcam_set_contig_buffer(struct mcam_camera *cam, int frame) | |
549 | { | |
550 | struct mcam_vb_buffer *buf; | |
ad6ac452 | 551 | dma_addr_t dma_handle; |
2d700715 | 552 | struct vb2_v4l2_buffer *vb; |
ad6ac452 | 553 | |
a9b36e85 JC |
554 | /* |
555 | * If there are no available buffers, go into single mode | |
556 | */ | |
557 | if (list_empty(&cam->buffers)) { | |
558 | buf = cam->vb_bufs[frame ^ 0x1]; | |
a9b36e85 | 559 | set_bit(CF_SINGLE_BUFFER, &cam->flags); |
f698957a | 560 | cam->frame_state.singles++; |
1d3953fb LY |
561 | } else { |
562 | /* | |
563 | * OK, we have a buffer we can use. | |
564 | */ | |
565 | buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer, | |
566 | queue); | |
567 | list_del_init(&buf->queue); | |
568 | clear_bit(CF_SINGLE_BUFFER, &cam->flags); | |
a9b36e85 | 569 | } |
1d3953fb LY |
570 | |
571 | cam->vb_bufs[frame] = buf; | |
ad6ac452 LY |
572 | vb = &buf->vb_buf; |
573 | ||
2d700715 | 574 | dma_handle = vb2_dma_contig_plane_dma_addr(&vb->vb2_buf, 0); |
6eb40d59 | 575 | mcam_write_yuv_bases(cam, frame, dma_handle); |
a9b36e85 JC |
576 | } |
577 | ||
cbc4f3a2 JC |
578 | /* |
579 | * Initial B_DMA_contig setup. | |
580 | */ | |
a9b36e85 JC |
581 | static void mcam_ctlr_dma_contig(struct mcam_camera *cam) |
582 | { | |
583 | mcam_reg_set_bit(cam, REG_CTRL1, C1_TWOBUFS); | |
584 | cam->nbufs = 2; | |
585 | mcam_set_contig_buffer(cam, 0); | |
586 | mcam_set_contig_buffer(cam, 1); | |
587 | } | |
588 | ||
d43dae75 JC |
589 | /* |
590 | * Frame completion handling. | |
591 | */ | |
592 | static void mcam_dma_contig_done(struct mcam_camera *cam, int frame) | |
593 | { | |
594 | struct mcam_vb_buffer *buf = cam->vb_bufs[frame]; | |
595 | ||
596 | if (!test_bit(CF_SINGLE_BUFFER, &cam->flags)) { | |
f698957a | 597 | cam->frame_state.delivered++; |
ca657b28 | 598 | cam->vb_bufs[frame] = NULL; |
d43dae75 JC |
599 | mcam_buffer_done(cam, frame, &buf->vb_buf); |
600 | } | |
601 | mcam_set_contig_buffer(cam, frame); | |
602 | } | |
603 | ||
7498469f | 604 | #endif /* MCAM_MODE_DMA_CONTIG */ |
d43dae75 | 605 | |
7498469f | 606 | #ifdef MCAM_MODE_DMA_SG |
d43dae75 JC |
607 | /* ---------------------------------------------------------------------- */ |
608 | /* | |
609 | * Scatter/gather-specific code. | |
610 | */ | |
a9b36e85 | 611 | |
cbc4f3a2 JC |
612 | /* |
613 | * Set up the next buffer for S/G I/O; caller should be sure that | |
614 | * the controller is stopped and a buffer is available. | |
615 | */ | |
616 | static void mcam_sg_next_buffer(struct mcam_camera *cam) | |
a9b36e85 | 617 | { |
cbc4f3a2 JC |
618 | struct mcam_vb_buffer *buf; |
619 | ||
620 | buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer, queue); | |
621 | list_del_init(&buf->queue); | |
121bbe25 JC |
622 | /* |
623 | * Very Bad Not Good Things happen if you don't clear | |
624 | * C1_DESC_ENA before making any descriptor changes. | |
625 | */ | |
626 | mcam_reg_clear_bit(cam, REG_CTRL1, C1_DESC_ENA); | |
cbc4f3a2 JC |
627 | mcam_reg_write(cam, REG_DMA_DESC_Y, buf->dma_desc_pa); |
628 | mcam_reg_write(cam, REG_DESC_LEN_Y, | |
629 | buf->dma_desc_nent*sizeof(struct mcam_dma_desc)); | |
630 | mcam_reg_write(cam, REG_DESC_LEN_U, 0); | |
631 | mcam_reg_write(cam, REG_DESC_LEN_V, 0); | |
121bbe25 | 632 | mcam_reg_set_bit(cam, REG_CTRL1, C1_DESC_ENA); |
cbc4f3a2 | 633 | cam->vb_bufs[0] = buf; |
a9b36e85 JC |
634 | } |
635 | ||
cbc4f3a2 JC |
636 | /* |
637 | * Initial B_DMA_sg setup | |
638 | */ | |
639 | static void mcam_ctlr_dma_sg(struct mcam_camera *cam) | |
640 | { | |
bb0a896e JC |
641 | /* |
642 | * The list-empty condition can hit us at resume time | |
643 | * if the buffer list was empty when the system was suspended. | |
644 | */ | |
645 | if (list_empty(&cam->buffers)) { | |
646 | set_bit(CF_SG_RESTART, &cam->flags); | |
647 | return; | |
648 | } | |
649 | ||
cbc4f3a2 JC |
650 | mcam_reg_clear_bit(cam, REG_CTRL1, C1_DESC_3WORD); |
651 | mcam_sg_next_buffer(cam); | |
cbc4f3a2 JC |
652 | cam->nbufs = 3; |
653 | } | |
654 | ||
d43dae75 | 655 | |
cbc4f3a2 | 656 | /* |
d43dae75 JC |
657 | * Frame completion with S/G is trickier. We can't muck with |
658 | * a descriptor chain on the fly, since the controller buffers it | |
659 | * internally. So we have to actually stop and restart; Marvell | |
660 | * says this is the way to do it. | |
661 | * | |
662 | * Of course, stopping is easier said than done; experience shows | |
663 | * that the controller can start a frame *after* C0_ENABLE has been | |
664 | * cleared. So when running in S/G mode, the controller is "stopped" | |
665 | * on receipt of the start-of-frame interrupt. That means we can | |
666 | * safely change the DMA descriptor array here and restart things | |
667 | * (assuming there's another buffer waiting to go). | |
668 | */ | |
669 | static void mcam_dma_sg_done(struct mcam_camera *cam, int frame) | |
670 | { | |
671 | struct mcam_vb_buffer *buf = cam->vb_bufs[0]; | |
672 | ||
49df19eb JC |
673 | /* |
674 | * If we're no longer supposed to be streaming, don't do anything. | |
675 | */ | |
676 | if (cam->state != S_STREAMING) | |
677 | return; | |
d43dae75 JC |
678 | /* |
679 | * If we have another buffer available, put it in and | |
680 | * restart the engine. | |
681 | */ | |
682 | if (!list_empty(&cam->buffers)) { | |
683 | mcam_sg_next_buffer(cam); | |
d43dae75 JC |
684 | mcam_ctlr_start(cam); |
685 | /* | |
686 | * Otherwise set CF_SG_RESTART and the controller will | |
687 | * be restarted once another buffer shows up. | |
688 | */ | |
689 | } else { | |
690 | set_bit(CF_SG_RESTART, &cam->flags); | |
f698957a | 691 | cam->frame_state.singles++; |
bb0a896e | 692 | cam->vb_bufs[0] = NULL; |
d43dae75 JC |
693 | } |
694 | /* | |
695 | * Now we can give the completed frame back to user space. | |
696 | */ | |
f698957a | 697 | cam->frame_state.delivered++; |
d43dae75 JC |
698 | mcam_buffer_done(cam, frame, &buf->vb_buf); |
699 | } | |
700 | ||
701 | ||
702 | /* | |
703 | * Scatter/gather mode requires stopping the controller between | |
704 | * frames so we can put in a new DMA descriptor array. If no new | |
705 | * buffer exists at frame completion, the controller is left stopped; | |
706 | * this function is charged with gettig things going again. | |
707 | */ | |
708 | static void mcam_sg_restart(struct mcam_camera *cam) | |
709 | { | |
710 | mcam_ctlr_dma_sg(cam); | |
711 | mcam_ctlr_start(cam); | |
712 | clear_bit(CF_SG_RESTART, &cam->flags); | |
713 | } | |
714 | ||
7498469f JC |
715 | #else /* MCAM_MODE_DMA_SG */ |
716 | ||
717 | static inline void mcam_sg_restart(struct mcam_camera *cam) | |
718 | { | |
719 | return; | |
720 | } | |
721 | ||
722 | #endif /* MCAM_MODE_DMA_SG */ | |
d43dae75 JC |
723 | |
724 | /* ---------------------------------------------------------------------- */ | |
725 | /* | |
726 | * Buffer-mode-independent controller code. | |
727 | */ | |
728 | ||
729 | /* | |
730 | * Image format setup | |
cbc4f3a2 | 731 | */ |
abfa3df3 JC |
732 | static void mcam_ctlr_image(struct mcam_camera *cam) |
733 | { | |
abfa3df3 | 734 | struct v4l2_pix_format *fmt = &cam->pix_format; |
ad6ac452 LY |
735 | u32 widthy = 0, widthuv = 0, imgsz_h, imgsz_w; |
736 | ||
737 | cam_dbg(cam, "camera: bytesperline = %d; height = %d\n", | |
738 | fmt->bytesperline, fmt->sizeimage / fmt->bytesperline); | |
739 | imgsz_h = (fmt->height << IMGSZ_V_SHIFT) & IMGSZ_V_MASK; | |
740 | imgsz_w = (fmt->width * 2) & IMGSZ_H_MASK; | |
741 | ||
742 | switch (fmt->pixelformat) { | |
743 | case V4L2_PIX_FMT_YUYV: | |
2a700d8e | 744 | case V4L2_PIX_FMT_YVYU: |
ad6ac452 LY |
745 | widthy = fmt->width * 2; |
746 | widthuv = 0; | |
747 | break; | |
ad6ac452 LY |
748 | case V4L2_PIX_FMT_YUV420: |
749 | case V4L2_PIX_FMT_YVU420: | |
750 | widthy = fmt->width; | |
751 | widthuv = fmt->width / 2; | |
752 | break; | |
753 | default: | |
754 | widthy = fmt->bytesperline; | |
755 | widthuv = 0; | |
47ba7dba | 756 | break; |
ad6ac452 LY |
757 | } |
758 | ||
759 | mcam_reg_write_mask(cam, REG_IMGPITCH, widthuv << 16 | widthy, | |
760 | IMGP_YP_MASK | IMGP_UVP_MASK); | |
761 | mcam_reg_write(cam, REG_IMGSIZE, imgsz_h | imgsz_w); | |
762 | mcam_reg_write(cam, REG_IMGOFFSET, 0x0); | |
abfa3df3 | 763 | |
abfa3df3 JC |
764 | /* |
765 | * Tell the controller about the image format we are using. | |
766 | */ | |
ad6ac452 | 767 | switch (fmt->pixelformat) { |
ad6ac452 LY |
768 | case V4L2_PIX_FMT_YUV420: |
769 | case V4L2_PIX_FMT_YVU420: | |
770 | mcam_reg_write_mask(cam, REG_CTRL0, | |
2a700d8e | 771 | C0_DF_YUV | C0_YUV_420PL | C0_YUVE_VYUY, C0_DF_MASK); |
ad6ac452 | 772 | break; |
abfa3df3 | 773 | case V4L2_PIX_FMT_YUYV: |
ad6ac452 | 774 | mcam_reg_write_mask(cam, REG_CTRL0, |
2a700d8e | 775 | C0_DF_YUV | C0_YUV_PACKED | C0_YUVE_NOSWAP, C0_DF_MASK); |
ad6ac452 | 776 | break; |
2a700d8e | 777 | case V4L2_PIX_FMT_YVYU: |
ad6ac452 | 778 | mcam_reg_write_mask(cam, REG_CTRL0, |
2a700d8e | 779 | C0_DF_YUV | C0_YUV_PACKED | C0_YUVE_SWAP24, C0_DF_MASK); |
ad6ac452 | 780 | break; |
ccf509f8 | 781 | case V4L2_PIX_FMT_XRGB444: |
ad6ac452 | 782 | mcam_reg_write_mask(cam, REG_CTRL0, |
ccf509f8 | 783 | C0_DF_RGB | C0_RGBF_444 | C0_RGB4_XBGR, C0_DF_MASK); |
ad6ac452 | 784 | break; |
abfa3df3 | 785 | case V4L2_PIX_FMT_RGB565: |
ad6ac452 LY |
786 | mcam_reg_write_mask(cam, REG_CTRL0, |
787 | C0_DF_RGB | C0_RGBF_565 | C0_RGB5_BGGR, C0_DF_MASK); | |
788 | break; | |
8380b7e4 HV |
789 | case V4L2_PIX_FMT_SBGGR8: |
790 | mcam_reg_write_mask(cam, REG_CTRL0, | |
791 | C0_DF_RGB | C0_RGB5_GRBG, C0_DF_MASK); | |
792 | break; | |
abfa3df3 | 793 | default: |
ad6ac452 LY |
794 | cam_err(cam, "camera: unknown format: %#x\n", fmt->pixelformat); |
795 | break; | |
abfa3df3 | 796 | } |
ad6ac452 | 797 | |
abfa3df3 JC |
798 | /* |
799 | * Make sure it knows we want to use hsync/vsync. | |
800 | */ | |
ad6ac452 | 801 | mcam_reg_write_mask(cam, REG_CTRL0, C0_SIF_HVSYNC, C0_SIFM_MASK); |
05fed816 LY |
802 | /* |
803 | * This field controls the generation of EOF(DVP only) | |
804 | */ | |
805 | if (cam->bus_type != V4L2_MBUS_CSI2) | |
806 | mcam_reg_set_bit(cam, REG_CTRL0, | |
807 | C0_EOF_VSYNC | C0_VEDGE_CTRL); | |
abfa3df3 JC |
808 | } |
809 | ||
810 | ||
811 | /* | |
812 | * Configure the controller for operation; caller holds the | |
813 | * device mutex. | |
814 | */ | |
815 | static int mcam_ctlr_configure(struct mcam_camera *cam) | |
816 | { | |
817 | unsigned long flags; | |
818 | ||
819 | spin_lock_irqsave(&cam->dev_lock, flags); | |
bb0a896e | 820 | clear_bit(CF_SG_RESTART, &cam->flags); |
7498469f | 821 | cam->dma_setup(cam); |
abfa3df3 JC |
822 | mcam_ctlr_image(cam); |
823 | mcam_set_config_needed(cam, 0); | |
824 | spin_unlock_irqrestore(&cam->dev_lock, flags); | |
825 | return 0; | |
826 | } | |
827 | ||
828 | static void mcam_ctlr_irq_enable(struct mcam_camera *cam) | |
829 | { | |
830 | /* | |
831 | * Clear any pending interrupts, since we do not | |
832 | * expect to have I/O active prior to enabling. | |
833 | */ | |
834 | mcam_reg_write(cam, REG_IRQSTAT, FRAMEIRQS); | |
835 | mcam_reg_set_bit(cam, REG_IRQMASK, FRAMEIRQS); | |
836 | } | |
837 | ||
838 | static void mcam_ctlr_irq_disable(struct mcam_camera *cam) | |
839 | { | |
840 | mcam_reg_clear_bit(cam, REG_IRQMASK, FRAMEIRQS); | |
841 | } | |
842 | ||
abfa3df3 | 843 | |
cbc4f3a2 | 844 | |
abfa3df3 JC |
845 | static void mcam_ctlr_init(struct mcam_camera *cam) |
846 | { | |
847 | unsigned long flags; | |
848 | ||
849 | spin_lock_irqsave(&cam->dev_lock, flags); | |
850 | /* | |
851 | * Make sure it's not powered down. | |
852 | */ | |
853 | mcam_reg_clear_bit(cam, REG_CTRL1, C1_PWRDWN); | |
854 | /* | |
855 | * Turn off the enable bit. It sure should be off anyway, | |
856 | * but it's good to be sure. | |
857 | */ | |
858 | mcam_reg_clear_bit(cam, REG_CTRL0, C0_ENABLE); | |
859 | /* | |
860 | * Clock the sensor appropriately. Controller clock should | |
861 | * be 48MHz, sensor "typical" value is half that. | |
862 | */ | |
863 | mcam_reg_write_mask(cam, REG_CLKCTRL, 2, CLK_DIV_MASK); | |
864 | spin_unlock_irqrestore(&cam->dev_lock, flags); | |
865 | } | |
866 | ||
867 | ||
868 | /* | |
869 | * Stop the controller, and don't return until we're really sure that no | |
870 | * further DMA is going on. | |
871 | */ | |
872 | static void mcam_ctlr_stop_dma(struct mcam_camera *cam) | |
873 | { | |
874 | unsigned long flags; | |
875 | ||
876 | /* | |
877 | * Theory: stop the camera controller (whether it is operating | |
878 | * or not). Delay briefly just in case we race with the SOF | |
879 | * interrupt, then wait until no DMA is active. | |
880 | */ | |
881 | spin_lock_irqsave(&cam->dev_lock, flags); | |
cbc4f3a2 | 882 | clear_bit(CF_SG_RESTART, &cam->flags); |
abfa3df3 | 883 | mcam_ctlr_stop(cam); |
cbc4f3a2 | 884 | cam->state = S_IDLE; |
abfa3df3 | 885 | spin_unlock_irqrestore(&cam->dev_lock, flags); |
482d35c4 JC |
886 | /* |
887 | * This is a brutally long sleep, but experience shows that | |
888 | * it can take the controller a while to get the message that | |
889 | * it needs to stop grabbing frames. In particular, we can | |
890 | * sometimes (on mmp) get a frame at the end WITHOUT the | |
891 | * start-of-frame indication. | |
892 | */ | |
893 | msleep(150); | |
abfa3df3 JC |
894 | if (test_bit(CF_DMA_ACTIVE, &cam->flags)) |
895 | cam_err(cam, "Timeout waiting for DMA to end\n"); | |
896 | /* This would be bad news - what now? */ | |
897 | spin_lock_irqsave(&cam->dev_lock, flags); | |
abfa3df3 JC |
898 | mcam_ctlr_irq_disable(cam); |
899 | spin_unlock_irqrestore(&cam->dev_lock, flags); | |
900 | } | |
901 | ||
902 | /* | |
903 | * Power up and down. | |
904 | */ | |
05fed816 | 905 | static int mcam_ctlr_power_up(struct mcam_camera *cam) |
abfa3df3 JC |
906 | { |
907 | unsigned long flags; | |
05fed816 | 908 | int ret; |
abfa3df3 JC |
909 | |
910 | spin_lock_irqsave(&cam->dev_lock, flags); | |
05fed816 LY |
911 | ret = cam->plat_power_up(cam); |
912 | if (ret) { | |
913 | spin_unlock_irqrestore(&cam->dev_lock, flags); | |
914 | return ret; | |
915 | } | |
67a8dbbc | 916 | mcam_reg_clear_bit(cam, REG_CTRL1, C1_PWRDWN); |
abfa3df3 JC |
917 | spin_unlock_irqrestore(&cam->dev_lock, flags); |
918 | msleep(5); /* Just to be sure */ | |
05fed816 | 919 | return 0; |
abfa3df3 JC |
920 | } |
921 | ||
922 | static void mcam_ctlr_power_down(struct mcam_camera *cam) | |
923 | { | |
924 | unsigned long flags; | |
925 | ||
926 | spin_lock_irqsave(&cam->dev_lock, flags); | |
67a8dbbc JC |
927 | /* |
928 | * School of hard knocks department: be sure we do any register | |
929 | * twiddling on the controller *before* calling the platform | |
930 | * power down routine. | |
931 | */ | |
abfa3df3 | 932 | mcam_reg_set_bit(cam, REG_CTRL1, C1_PWRDWN); |
67a8dbbc | 933 | cam->plat_power_down(cam); |
abfa3df3 JC |
934 | spin_unlock_irqrestore(&cam->dev_lock, flags); |
935 | } | |
936 | ||
937 | /* -------------------------------------------------------------------- */ | |
938 | /* | |
939 | * Communications with the sensor. | |
940 | */ | |
941 | ||
942 | static int __mcam_cam_reset(struct mcam_camera *cam) | |
943 | { | |
944 | return sensor_call(cam, core, reset, 0); | |
945 | } | |
946 | ||
947 | /* | |
948 | * We have found the sensor on the i2c. Let's try to have a | |
949 | * conversation. | |
950 | */ | |
951 | static int mcam_cam_init(struct mcam_camera *cam) | |
952 | { | |
abfa3df3 JC |
953 | int ret; |
954 | ||
abfa3df3 JC |
955 | if (cam->state != S_NOTREADY) |
956 | cam_warn(cam, "Cam init with device in funky state %d", | |
957 | cam->state); | |
958 | ret = __mcam_cam_reset(cam); | |
7486af1a | 959 | /* Get/set parameters? */ |
d43dae75 | 960 | cam->state = S_IDLE; |
d43dae75 | 961 | mcam_ctlr_power_down(cam); |
d43dae75 | 962 | return ret; |
abfa3df3 JC |
963 | } |
964 | ||
d43dae75 JC |
965 | /* |
966 | * Configure the sensor to match the parameters we have. Caller should | |
967 | * hold s_mutex | |
968 | */ | |
969 | static int mcam_cam_set_flip(struct mcam_camera *cam) | |
abfa3df3 | 970 | { |
d43dae75 | 971 | struct v4l2_control ctrl; |
abfa3df3 | 972 | |
d43dae75 JC |
973 | memset(&ctrl, 0, sizeof(ctrl)); |
974 | ctrl.id = V4L2_CID_VFLIP; | |
975 | ctrl.value = flip; | |
976 | return sensor_call(cam, core, s_ctrl, &ctrl); | |
abfa3df3 JC |
977 | } |
978 | ||
979 | ||
d43dae75 JC |
980 | static int mcam_cam_configure(struct mcam_camera *cam) |
981 | { | |
ebf984bb HV |
982 | struct v4l2_subdev_format format = { |
983 | .which = V4L2_SUBDEV_FORMAT_ACTIVE, | |
984 | }; | |
d43dae75 | 985 | int ret; |
abfa3df3 | 986 | |
ebf984bb | 987 | v4l2_fill_mbus_format(&format.format, &cam->pix_format, cam->mbus_code); |
d43dae75 JC |
988 | ret = sensor_call(cam, core, init, 0); |
989 | if (ret == 0) | |
ebf984bb | 990 | ret = sensor_call(cam, pad, set_fmt, NULL, &format); |
d43dae75 JC |
991 | /* |
992 | * OV7670 does weird things if flip is set *before* format... | |
993 | */ | |
994 | ret += mcam_cam_set_flip(cam); | |
995 | return ret; | |
996 | } | |
abfa3df3 JC |
997 | |
998 | /* | |
999 | * Get everything ready, and start grabbing frames. | |
1000 | */ | |
a9b36e85 | 1001 | static int mcam_read_setup(struct mcam_camera *cam) |
abfa3df3 JC |
1002 | { |
1003 | int ret; | |
1004 | unsigned long flags; | |
1005 | ||
1006 | /* | |
1007 | * Configuration. If we still don't have DMA buffers, | |
1008 | * make one last, desperate attempt. | |
1009 | */ | |
a9b36e85 JC |
1010 | if (cam->buffer_mode == B_vmalloc && cam->nbufs == 0 && |
1011 | mcam_alloc_dma_bufs(cam, 0)) | |
1012 | return -ENOMEM; | |
abfa3df3 JC |
1013 | |
1014 | if (mcam_needs_config(cam)) { | |
1015 | mcam_cam_configure(cam); | |
1016 | ret = mcam_ctlr_configure(cam); | |
1017 | if (ret) | |
1018 | return ret; | |
1019 | } | |
1020 | ||
1021 | /* | |
1022 | * Turn it loose. | |
1023 | */ | |
1024 | spin_lock_irqsave(&cam->dev_lock, flags); | |
482d35c4 | 1025 | clear_bit(CF_DMA_ACTIVE, &cam->flags); |
abfa3df3 | 1026 | mcam_reset_buffers(cam); |
05fed816 LY |
1027 | /* |
1028 | * Update CSI2_DPHY value | |
1029 | */ | |
1030 | if (cam->calc_dphy) | |
1031 | cam->calc_dphy(cam); | |
1032 | cam_dbg(cam, "camera: DPHY sets: dphy3=0x%x, dphy5=0x%x, dphy6=0x%x\n", | |
1033 | cam->dphy[0], cam->dphy[1], cam->dphy[2]); | |
1034 | if (cam->bus_type == V4L2_MBUS_CSI2) | |
1035 | mcam_enable_mipi(cam); | |
1036 | else | |
1037 | mcam_disable_mipi(cam); | |
abfa3df3 | 1038 | mcam_ctlr_irq_enable(cam); |
a9b36e85 | 1039 | cam->state = S_STREAMING; |
bb0a896e JC |
1040 | if (!test_bit(CF_SG_RESTART, &cam->flags)) |
1041 | mcam_ctlr_start(cam); | |
abfa3df3 JC |
1042 | spin_unlock_irqrestore(&cam->dev_lock, flags); |
1043 | return 0; | |
1044 | } | |
1045 | ||
b5210fd2 JC |
1046 | /* ----------------------------------------------------------------------- */ |
1047 | /* | |
1048 | * Videobuf2 interface code. | |
1049 | */ | |
abfa3df3 | 1050 | |
fc714e70 | 1051 | static int mcam_vb_queue_setup(struct vb2_queue *vq, |
df9ecb0c | 1052 | unsigned int *nbufs, |
035aa147 | 1053 | unsigned int *num_planes, unsigned int sizes[], |
36c0f8b3 | 1054 | struct device *alloc_devs[]) |
abfa3df3 | 1055 | { |
b5210fd2 | 1056 | struct mcam_camera *cam = vb2_get_drv_priv(vq); |
cbc4f3a2 | 1057 | int minbufs = (cam->buffer_mode == B_DMA_contig) ? 3 : 2; |
df9ecb0c | 1058 | unsigned size = cam->pix_format.sizeimage; |
b5210fd2 | 1059 | |
cbc4f3a2 JC |
1060 | if (*nbufs < minbufs) |
1061 | *nbufs = minbufs; | |
df9ecb0c HV |
1062 | |
1063 | if (*num_planes) | |
1064 | return sizes[0] < size ? -EINVAL : 0; | |
1065 | sizes[0] = size; | |
1066 | *num_planes = 1; /* Someday we have to support planar formats... */ | |
b5210fd2 JC |
1067 | return 0; |
1068 | } | |
1069 | ||
cbc4f3a2 | 1070 | |
b5210fd2 JC |
1071 | static void mcam_vb_buf_queue(struct vb2_buffer *vb) |
1072 | { | |
2d700715 JS |
1073 | struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); |
1074 | struct mcam_vb_buffer *mvb = vb_to_mvb(vbuf); | |
b5210fd2 JC |
1075 | struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue); |
1076 | unsigned long flags; | |
a9b36e85 | 1077 | int start; |
b5210fd2 JC |
1078 | |
1079 | spin_lock_irqsave(&cam->dev_lock, flags); | |
a9b36e85 JC |
1080 | start = (cam->state == S_BUFWAIT) && !list_empty(&cam->buffers); |
1081 | list_add(&mvb->queue, &cam->buffers); | |
49df19eb | 1082 | if (cam->state == S_STREAMING && test_bit(CF_SG_RESTART, &cam->flags)) |
cbc4f3a2 | 1083 | mcam_sg_restart(cam); |
b5210fd2 | 1084 | spin_unlock_irqrestore(&cam->dev_lock, flags); |
a9b36e85 JC |
1085 | if (start) |
1086 | mcam_read_setup(cam); | |
b5210fd2 JC |
1087 | } |
1088 | ||
ca657b28 HV |
1089 | static void mcam_vb_requeue_bufs(struct vb2_queue *vq, |
1090 | enum vb2_buffer_state state) | |
1091 | { | |
1092 | struct mcam_camera *cam = vb2_get_drv_priv(vq); | |
1093 | struct mcam_vb_buffer *buf, *node; | |
1094 | unsigned long flags; | |
1095 | unsigned i; | |
1096 | ||
1097 | spin_lock_irqsave(&cam->dev_lock, flags); | |
1098 | list_for_each_entry_safe(buf, node, &cam->buffers, queue) { | |
2d700715 | 1099 | vb2_buffer_done(&buf->vb_buf.vb2_buf, state); |
ca657b28 HV |
1100 | list_del(&buf->queue); |
1101 | } | |
1102 | for (i = 0; i < MAX_DMA_BUFS; i++) { | |
1103 | buf = cam->vb_bufs[i]; | |
1104 | ||
1105 | if (buf) { | |
2d700715 | 1106 | vb2_buffer_done(&buf->vb_buf.vb2_buf, state); |
ca657b28 HV |
1107 | cam->vb_bufs[i] = NULL; |
1108 | } | |
1109 | } | |
1110 | spin_unlock_irqrestore(&cam->dev_lock, flags); | |
1111 | } | |
1112 | ||
b5210fd2 JC |
1113 | /* |
1114 | * These need to be called with the mutex held from vb2 | |
1115 | */ | |
bd323e28 | 1116 | static int mcam_vb_start_streaming(struct vb2_queue *vq, unsigned int count) |
b5210fd2 JC |
1117 | { |
1118 | struct mcam_camera *cam = vb2_get_drv_priv(vq); | |
0a0b3fb4 | 1119 | unsigned int frame; |
ca657b28 | 1120 | int ret; |
abfa3df3 | 1121 | |
bd323e28 | 1122 | if (cam->state != S_IDLE) { |
ca657b28 | 1123 | mcam_vb_requeue_bufs(vq, VB2_BUF_STATE_QUEUED); |
a9b36e85 | 1124 | return -EINVAL; |
bd323e28 | 1125 | } |
949bd408 HV |
1126 | cam->frame_state.frames = 0; |
1127 | cam->frame_state.singles = 0; | |
1128 | cam->frame_state.delivered = 0; | |
a9b36e85 JC |
1129 | cam->sequence = 0; |
1130 | /* | |
1131 | * Videobuf2 sneakily hoards all the buffers and won't | |
1132 | * give them to us until *after* streaming starts. But | |
1133 | * we can't actually start streaming until we have a | |
1134 | * destination. So go into a wait state and hope they | |
1135 | * give us buffers soon. | |
1136 | */ | |
1137 | if (cam->buffer_mode != B_vmalloc && list_empty(&cam->buffers)) { | |
1138 | cam->state = S_BUFWAIT; | |
1139 | return 0; | |
abfa3df3 | 1140 | } |
0a0b3fb4 LY |
1141 | |
1142 | /* | |
1143 | * Ensure clear the left over frame flags | |
1144 | * before every really start streaming | |
1145 | */ | |
1146 | for (frame = 0; frame < cam->nbufs; frame++) | |
1147 | clear_bit(CF_FRAME_SOF0 + frame, &cam->flags); | |
1148 | ||
ca657b28 HV |
1149 | ret = mcam_read_setup(cam); |
1150 | if (ret) | |
1151 | mcam_vb_requeue_bufs(vq, VB2_BUF_STATE_QUEUED); | |
1152 | return ret; | |
b5210fd2 JC |
1153 | } |
1154 | ||
e37559b2 | 1155 | static void mcam_vb_stop_streaming(struct vb2_queue *vq) |
b5210fd2 JC |
1156 | { |
1157 | struct mcam_camera *cam = vb2_get_drv_priv(vq); | |
b5210fd2 | 1158 | |
949bd408 HV |
1159 | cam_dbg(cam, "stop_streaming: %d frames, %d singles, %d delivered\n", |
1160 | cam->frame_state.frames, cam->frame_state.singles, | |
1161 | cam->frame_state.delivered); | |
a9b36e85 JC |
1162 | if (cam->state == S_BUFWAIT) { |
1163 | /* They never gave us buffers */ | |
1164 | cam->state = S_IDLE; | |
e37559b2 | 1165 | return; |
a9b36e85 | 1166 | } |
b5210fd2 | 1167 | if (cam->state != S_STREAMING) |
e37559b2 | 1168 | return; |
b5210fd2 | 1169 | mcam_ctlr_stop_dma(cam); |
7c269f45 LY |
1170 | /* |
1171 | * Reset the CCIC PHY after stopping streaming, | |
1172 | * otherwise, the CCIC may be unstable. | |
1173 | */ | |
1174 | if (cam->ctlr_reset) | |
1175 | cam->ctlr_reset(cam); | |
abfa3df3 | 1176 | /* |
b5210fd2 JC |
1177 | * VB2 reclaims the buffers, so we need to forget |
1178 | * about them. | |
abfa3df3 | 1179 | */ |
ca657b28 | 1180 | mcam_vb_requeue_bufs(vq, VB2_BUF_STATE_ERROR); |
abfa3df3 JC |
1181 | } |
1182 | ||
1183 | ||
b5210fd2 JC |
1184 | static const struct vb2_ops mcam_vb2_ops = { |
1185 | .queue_setup = mcam_vb_queue_setup, | |
b5210fd2 JC |
1186 | .buf_queue = mcam_vb_buf_queue, |
1187 | .start_streaming = mcam_vb_start_streaming, | |
1188 | .stop_streaming = mcam_vb_stop_streaming, | |
519694f9 PL |
1189 | .wait_prepare = vb2_ops_wait_prepare, |
1190 | .wait_finish = vb2_ops_wait_finish, | |
b5210fd2 | 1191 | }; |
abfa3df3 | 1192 | |
7498469f JC |
1193 | |
1194 | #ifdef MCAM_MODE_DMA_SG | |
cbc4f3a2 | 1195 | /* |
d43dae75 JC |
1196 | * Scatter/gather mode uses all of the above functions plus a |
1197 | * few extras to deal with DMA mapping. | |
cbc4f3a2 | 1198 | */ |
d43dae75 JC |
1199 | static int mcam_vb_sg_buf_init(struct vb2_buffer *vb) |
1200 | { | |
2d700715 JS |
1201 | struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); |
1202 | struct mcam_vb_buffer *mvb = vb_to_mvb(vbuf); | |
d43dae75 JC |
1203 | struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue); |
1204 | int ndesc = cam->pix_format.sizeimage/PAGE_SIZE + 1; | |
1205 | ||
1206 | mvb->dma_desc = dma_alloc_coherent(cam->dev, | |
1207 | ndesc * sizeof(struct mcam_dma_desc), | |
1208 | &mvb->dma_desc_pa, GFP_KERNEL); | |
1209 | if (mvb->dma_desc == NULL) { | |
1210 | cam_err(cam, "Unable to get DMA descriptor array\n"); | |
1211 | return -ENOMEM; | |
1212 | } | |
1213 | return 0; | |
1214 | } | |
1215 | ||
1216 | static int mcam_vb_sg_buf_prepare(struct vb2_buffer *vb) | |
1217 | { | |
2d700715 JS |
1218 | struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); |
1219 | struct mcam_vb_buffer *mvb = vb_to_mvb(vbuf); | |
22301247 | 1220 | struct sg_table *sg_table = vb2_dma_sg_plane_desc(vb, 0); |
d43dae75 JC |
1221 | struct mcam_dma_desc *desc = mvb->dma_desc; |
1222 | struct scatterlist *sg; | |
1223 | int i; | |
1224 | ||
d790b7ed | 1225 | for_each_sg(sg_table->sgl, sg, sg_table->nents, i) { |
d43dae75 JC |
1226 | desc->dma_addr = sg_dma_address(sg); |
1227 | desc->segment_len = sg_dma_len(sg); | |
1228 | desc++; | |
1229 | } | |
1230 | return 0; | |
1231 | } | |
1232 | ||
d43dae75 JC |
1233 | static void mcam_vb_sg_buf_cleanup(struct vb2_buffer *vb) |
1234 | { | |
2d700715 | 1235 | struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); |
d43dae75 | 1236 | struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue); |
2d700715 | 1237 | struct mcam_vb_buffer *mvb = vb_to_mvb(vbuf); |
d43dae75 JC |
1238 | int ndesc = cam->pix_format.sizeimage/PAGE_SIZE + 1; |
1239 | ||
1240 | dma_free_coherent(cam->dev, ndesc * sizeof(struct mcam_dma_desc), | |
1241 | mvb->dma_desc, mvb->dma_desc_pa); | |
1242 | } | |
1243 | ||
1244 | ||
cbc4f3a2 JC |
1245 | static const struct vb2_ops mcam_vb2_sg_ops = { |
1246 | .queue_setup = mcam_vb_queue_setup, | |
1247 | .buf_init = mcam_vb_sg_buf_init, | |
1248 | .buf_prepare = mcam_vb_sg_buf_prepare, | |
1249 | .buf_queue = mcam_vb_buf_queue, | |
cbc4f3a2 JC |
1250 | .buf_cleanup = mcam_vb_sg_buf_cleanup, |
1251 | .start_streaming = mcam_vb_start_streaming, | |
1252 | .stop_streaming = mcam_vb_stop_streaming, | |
519694f9 PL |
1253 | .wait_prepare = vb2_ops_wait_prepare, |
1254 | .wait_finish = vb2_ops_wait_finish, | |
cbc4f3a2 JC |
1255 | }; |
1256 | ||
7498469f JC |
1257 | #endif /* MCAM_MODE_DMA_SG */ |
1258 | ||
b5210fd2 JC |
1259 | static int mcam_setup_vb2(struct mcam_camera *cam) |
1260 | { | |
1261 | struct vb2_queue *vq = &cam->vb_queue; | |
abfa3df3 | 1262 | |
b5210fd2 JC |
1263 | memset(vq, 0, sizeof(*vq)); |
1264 | vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; | |
b5210fd2 | 1265 | vq->drv_priv = cam; |
519694f9 | 1266 | vq->lock = &cam->s_mutex; |
17d3675a | 1267 | vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; |
ca16a64b HV |
1268 | vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ; |
1269 | vq->buf_struct_size = sizeof(struct mcam_vb_buffer); | |
1ad70ced | 1270 | vq->dev = cam->dev; |
cbc4f3a2 JC |
1271 | INIT_LIST_HEAD(&cam->buffers); |
1272 | switch (cam->buffer_mode) { | |
1273 | case B_DMA_contig: | |
7498469f | 1274 | #ifdef MCAM_MODE_DMA_CONTIG |
cbc4f3a2 | 1275 | vq->ops = &mcam_vb2_ops; |
a9b36e85 | 1276 | vq->mem_ops = &vb2_dma_contig_memops; |
7498469f JC |
1277 | cam->dma_setup = mcam_ctlr_dma_contig; |
1278 | cam->frame_complete = mcam_dma_contig_done; | |
1279 | #endif | |
cbc4f3a2 JC |
1280 | break; |
1281 | case B_DMA_sg: | |
7498469f | 1282 | #ifdef MCAM_MODE_DMA_SG |
cbc4f3a2 JC |
1283 | vq->ops = &mcam_vb2_sg_ops; |
1284 | vq->mem_ops = &vb2_dma_sg_memops; | |
7498469f JC |
1285 | cam->dma_setup = mcam_ctlr_dma_sg; |
1286 | cam->frame_complete = mcam_dma_sg_done; | |
1287 | #endif | |
cbc4f3a2 JC |
1288 | break; |
1289 | case B_vmalloc: | |
7498469f JC |
1290 | #ifdef MCAM_MODE_VMALLOC |
1291 | tasklet_init(&cam->s_tasklet, mcam_frame_tasklet, | |
1292 | (unsigned long) cam); | |
cbc4f3a2 | 1293 | vq->ops = &mcam_vb2_ops; |
a9b36e85 | 1294 | vq->mem_ops = &vb2_vmalloc_memops; |
7498469f JC |
1295 | cam->dma_setup = mcam_ctlr_dma_vmalloc; |
1296 | cam->frame_complete = mcam_vmalloc_done; | |
1297 | #endif | |
cbc4f3a2 JC |
1298 | break; |
1299 | } | |
b5210fd2 JC |
1300 | return vb2_queue_init(vq); |
1301 | } | |
1302 | ||
abfa3df3 | 1303 | |
d43dae75 | 1304 | /* ---------------------------------------------------------------------- */ |
abfa3df3 | 1305 | /* |
d43dae75 | 1306 | * The long list of V4L2 ioctl() operations. |
abfa3df3 JC |
1307 | */ |
1308 | ||
abfa3df3 JC |
1309 | static int mcam_vidioc_querycap(struct file *file, void *priv, |
1310 | struct v4l2_capability *cap) | |
1311 | { | |
44fbcb10 | 1312 | struct mcam_camera *cam = video_drvdata(file); |
b7b68393 | 1313 | |
abfa3df3 JC |
1314 | strcpy(cap->driver, "marvell_ccic"); |
1315 | strcpy(cap->card, "marvell_ccic"); | |
b7b68393 | 1316 | strlcpy(cap->bus_info, cam->bus_info, sizeof(cap->bus_info)); |
a020c747 | 1317 | cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | |
abfa3df3 | 1318 | V4L2_CAP_READWRITE | V4L2_CAP_STREAMING; |
a020c747 | 1319 | cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; |
abfa3df3 JC |
1320 | return 0; |
1321 | } | |
1322 | ||
1323 | ||
abfa3df3 JC |
1324 | static int mcam_vidioc_enum_fmt_vid_cap(struct file *filp, |
1325 | void *priv, struct v4l2_fmtdesc *fmt) | |
1326 | { | |
1327 | if (fmt->index >= N_MCAM_FMTS) | |
1328 | return -EINVAL; | |
1329 | strlcpy(fmt->description, mcam_formats[fmt->index].desc, | |
1330 | sizeof(fmt->description)); | |
1331 | fmt->pixelformat = mcam_formats[fmt->index].pixelformat; | |
1332 | return 0; | |
1333 | } | |
1334 | ||
1335 | static int mcam_vidioc_try_fmt_vid_cap(struct file *filp, void *priv, | |
1336 | struct v4l2_format *fmt) | |
1337 | { | |
44fbcb10 | 1338 | struct mcam_camera *cam = video_drvdata(filp); |
abfa3df3 JC |
1339 | struct mcam_format_struct *f; |
1340 | struct v4l2_pix_format *pix = &fmt->fmt.pix; | |
5eab4983 HV |
1341 | struct v4l2_subdev_pad_config pad_cfg; |
1342 | struct v4l2_subdev_format format = { | |
1343 | .which = V4L2_SUBDEV_FORMAT_TRY, | |
1344 | }; | |
abfa3df3 JC |
1345 | int ret; |
1346 | ||
1347 | f = mcam_find_format(pix->pixelformat); | |
1348 | pix->pixelformat = f->pixelformat; | |
5eab4983 HV |
1349 | v4l2_fill_mbus_format(&format.format, pix, f->mbus_code); |
1350 | ret = sensor_call(cam, pad, set_fmt, &pad_cfg, &format); | |
1351 | v4l2_fill_pix_format(pix, &format.format); | |
47ba7dba | 1352 | pix->bytesperline = pix->width * f->bpp; |
ad6ac452 LY |
1353 | switch (f->pixelformat) { |
1354 | case V4L2_PIX_FMT_YUV420: | |
1355 | case V4L2_PIX_FMT_YVU420: | |
47ba7dba | 1356 | pix->sizeimage = pix->height * pix->bytesperline * 3 / 2; |
ad6ac452 LY |
1357 | break; |
1358 | default: | |
47ba7dba | 1359 | pix->sizeimage = pix->height * pix->bytesperline; |
ad6ac452 LY |
1360 | break; |
1361 | } | |
2e6e6095 | 1362 | pix->colorspace = V4L2_COLORSPACE_SRGB; |
abfa3df3 JC |
1363 | return ret; |
1364 | } | |
1365 | ||
1366 | static int mcam_vidioc_s_fmt_vid_cap(struct file *filp, void *priv, | |
1367 | struct v4l2_format *fmt) | |
1368 | { | |
44fbcb10 | 1369 | struct mcam_camera *cam = video_drvdata(filp); |
abfa3df3 JC |
1370 | struct mcam_format_struct *f; |
1371 | int ret; | |
1372 | ||
1373 | /* | |
1374 | * Can't do anything if the device is not idle | |
1375 | * Also can't if there are streaming buffers in place. | |
1376 | */ | |
e198d0ff | 1377 | if (cam->state != S_IDLE || vb2_is_busy(&cam->vb_queue)) |
abfa3df3 JC |
1378 | return -EBUSY; |
1379 | ||
1380 | f = mcam_find_format(fmt->fmt.pix.pixelformat); | |
1381 | ||
1382 | /* | |
1383 | * See if the formatting works in principle. | |
1384 | */ | |
1385 | ret = mcam_vidioc_try_fmt_vid_cap(filp, priv, fmt); | |
1386 | if (ret) | |
1387 | return ret; | |
1388 | /* | |
1389 | * Now we start to change things for real, so let's do it | |
1390 | * under lock. | |
1391 | */ | |
abfa3df3 JC |
1392 | cam->pix_format = fmt->fmt.pix; |
1393 | cam->mbus_code = f->mbus_code; | |
1394 | ||
1395 | /* | |
1396 | * Make sure we have appropriate DMA buffers. | |
1397 | */ | |
a9b36e85 | 1398 | if (cam->buffer_mode == B_vmalloc) { |
7498469f JC |
1399 | ret = mcam_check_dma_buffers(cam); |
1400 | if (ret) | |
1401 | goto out; | |
abfa3df3 | 1402 | } |
a9b36e85 | 1403 | mcam_set_config_needed(cam, 1); |
abfa3df3 | 1404 | out: |
abfa3df3 JC |
1405 | return ret; |
1406 | } | |
1407 | ||
1408 | /* | |
1409 | * Return our stored notion of how the camera is/should be configured. | |
1410 | * The V4l2 spec wants us to be smarter, and actually get this from | |
1411 | * the camera (and not mess with it at open time). Someday. | |
1412 | */ | |
1413 | static int mcam_vidioc_g_fmt_vid_cap(struct file *filp, void *priv, | |
1414 | struct v4l2_format *f) | |
1415 | { | |
44fbcb10 | 1416 | struct mcam_camera *cam = video_drvdata(filp); |
abfa3df3 JC |
1417 | |
1418 | f->fmt.pix = cam->pix_format; | |
1419 | return 0; | |
1420 | } | |
1421 | ||
1422 | /* | |
1423 | * We only have one input - the sensor - so minimize the nonsense here. | |
1424 | */ | |
1425 | static int mcam_vidioc_enum_input(struct file *filp, void *priv, | |
1426 | struct v4l2_input *input) | |
1427 | { | |
1428 | if (input->index != 0) | |
1429 | return -EINVAL; | |
1430 | ||
1431 | input->type = V4L2_INPUT_TYPE_CAMERA; | |
abfa3df3 JC |
1432 | strcpy(input->name, "Camera"); |
1433 | return 0; | |
1434 | } | |
1435 | ||
1436 | static int mcam_vidioc_g_input(struct file *filp, void *priv, unsigned int *i) | |
1437 | { | |
1438 | *i = 0; | |
1439 | return 0; | |
1440 | } | |
1441 | ||
1442 | static int mcam_vidioc_s_input(struct file *filp, void *priv, unsigned int i) | |
1443 | { | |
1444 | if (i != 0) | |
1445 | return -EINVAL; | |
1446 | return 0; | |
1447 | } | |
1448 | ||
abfa3df3 JC |
1449 | /* |
1450 | * G/S_PARM. Most of this is done by the sensor, but we are | |
1451 | * the level which controls the number of read buffers. | |
1452 | */ | |
1453 | static int mcam_vidioc_g_parm(struct file *filp, void *priv, | |
1454 | struct v4l2_streamparm *parms) | |
1455 | { | |
44fbcb10 | 1456 | struct mcam_camera *cam = video_drvdata(filp); |
abfa3df3 JC |
1457 | int ret; |
1458 | ||
abfa3df3 | 1459 | ret = sensor_call(cam, video, g_parm, parms); |
abfa3df3 JC |
1460 | parms->parm.capture.readbuffers = n_dma_bufs; |
1461 | return ret; | |
1462 | } | |
1463 | ||
1464 | static int mcam_vidioc_s_parm(struct file *filp, void *priv, | |
1465 | struct v4l2_streamparm *parms) | |
1466 | { | |
44fbcb10 | 1467 | struct mcam_camera *cam = video_drvdata(filp); |
abfa3df3 JC |
1468 | int ret; |
1469 | ||
abfa3df3 | 1470 | ret = sensor_call(cam, video, s_parm, parms); |
abfa3df3 JC |
1471 | parms->parm.capture.readbuffers = n_dma_bufs; |
1472 | return ret; | |
1473 | } | |
1474 | ||
abfa3df3 JC |
1475 | static int mcam_vidioc_enum_framesizes(struct file *filp, void *priv, |
1476 | struct v4l2_frmsizeenum *sizes) | |
1477 | { | |
44fbcb10 | 1478 | struct mcam_camera *cam = video_drvdata(filp); |
17bef885 HV |
1479 | struct mcam_format_struct *f; |
1480 | struct v4l2_subdev_frame_size_enum fse = { | |
1481 | .index = sizes->index, | |
1482 | .which = V4L2_SUBDEV_FORMAT_ACTIVE, | |
1483 | }; | |
abfa3df3 JC |
1484 | int ret; |
1485 | ||
17bef885 HV |
1486 | f = mcam_find_format(sizes->pixel_format); |
1487 | if (f->pixelformat != sizes->pixel_format) | |
1488 | return -EINVAL; | |
1489 | fse.code = f->mbus_code; | |
17bef885 | 1490 | ret = sensor_call(cam, pad, enum_frame_size, NULL, &fse); |
17bef885 HV |
1491 | if (ret) |
1492 | return ret; | |
1493 | if (fse.min_width == fse.max_width && | |
1494 | fse.min_height == fse.max_height) { | |
1495 | sizes->type = V4L2_FRMSIZE_TYPE_DISCRETE; | |
1496 | sizes->discrete.width = fse.min_width; | |
1497 | sizes->discrete.height = fse.min_height; | |
1498 | return 0; | |
1499 | } | |
1500 | sizes->type = V4L2_FRMSIZE_TYPE_CONTINUOUS; | |
1501 | sizes->stepwise.min_width = fse.min_width; | |
1502 | sizes->stepwise.max_width = fse.max_width; | |
1503 | sizes->stepwise.min_height = fse.min_height; | |
1504 | sizes->stepwise.max_height = fse.max_height; | |
1505 | sizes->stepwise.step_width = 1; | |
1506 | sizes->stepwise.step_height = 1; | |
1507 | return 0; | |
abfa3df3 JC |
1508 | } |
1509 | ||
1510 | static int mcam_vidioc_enum_frameintervals(struct file *filp, void *priv, | |
1511 | struct v4l2_frmivalenum *interval) | |
1512 | { | |
44fbcb10 | 1513 | struct mcam_camera *cam = video_drvdata(filp); |
17bef885 HV |
1514 | struct mcam_format_struct *f; |
1515 | struct v4l2_subdev_frame_interval_enum fie = { | |
1516 | .index = interval->index, | |
1517 | .width = interval->width, | |
1518 | .height = interval->height, | |
1519 | .which = V4L2_SUBDEV_FORMAT_ACTIVE, | |
1520 | }; | |
abfa3df3 JC |
1521 | int ret; |
1522 | ||
17bef885 HV |
1523 | f = mcam_find_format(interval->pixel_format); |
1524 | if (f->pixelformat != interval->pixel_format) | |
1525 | return -EINVAL; | |
1526 | fie.code = f->mbus_code; | |
17bef885 | 1527 | ret = sensor_call(cam, pad, enum_frame_interval, NULL, &fie); |
17bef885 HV |
1528 | if (ret) |
1529 | return ret; | |
1530 | interval->type = V4L2_FRMIVAL_TYPE_DISCRETE; | |
1531 | interval->discrete = fie.interval; | |
1532 | return 0; | |
abfa3df3 JC |
1533 | } |
1534 | ||
1535 | #ifdef CONFIG_VIDEO_ADV_DEBUG | |
1536 | static int mcam_vidioc_g_register(struct file *file, void *priv, | |
1537 | struct v4l2_dbg_register *reg) | |
1538 | { | |
44fbcb10 | 1539 | struct mcam_camera *cam = video_drvdata(file); |
abfa3df3 | 1540 | |
4e032f3f HV |
1541 | if (reg->reg > cam->regs_size - 4) |
1542 | return -EINVAL; | |
7486af1a HV |
1543 | reg->val = mcam_reg_read(cam, reg->reg); |
1544 | reg->size = 4; | |
1545 | return 0; | |
abfa3df3 JC |
1546 | } |
1547 | ||
1548 | static int mcam_vidioc_s_register(struct file *file, void *priv, | |
977ba3b1 | 1549 | const struct v4l2_dbg_register *reg) |
abfa3df3 | 1550 | { |
44fbcb10 | 1551 | struct mcam_camera *cam = video_drvdata(file); |
abfa3df3 | 1552 | |
4e032f3f HV |
1553 | if (reg->reg > cam->regs_size - 4) |
1554 | return -EINVAL; | |
7486af1a HV |
1555 | mcam_reg_write(cam, reg->reg, reg->val); |
1556 | return 0; | |
abfa3df3 JC |
1557 | } |
1558 | #endif | |
1559 | ||
abfa3df3 JC |
1560 | static const struct v4l2_ioctl_ops mcam_v4l_ioctl_ops = { |
1561 | .vidioc_querycap = mcam_vidioc_querycap, | |
1562 | .vidioc_enum_fmt_vid_cap = mcam_vidioc_enum_fmt_vid_cap, | |
1563 | .vidioc_try_fmt_vid_cap = mcam_vidioc_try_fmt_vid_cap, | |
1564 | .vidioc_s_fmt_vid_cap = mcam_vidioc_s_fmt_vid_cap, | |
1565 | .vidioc_g_fmt_vid_cap = mcam_vidioc_g_fmt_vid_cap, | |
1566 | .vidioc_enum_input = mcam_vidioc_enum_input, | |
1567 | .vidioc_g_input = mcam_vidioc_g_input, | |
1568 | .vidioc_s_input = mcam_vidioc_s_input, | |
949bd408 | 1569 | .vidioc_reqbufs = vb2_ioctl_reqbufs, |
e198d0ff | 1570 | .vidioc_create_bufs = vb2_ioctl_create_bufs, |
949bd408 HV |
1571 | .vidioc_querybuf = vb2_ioctl_querybuf, |
1572 | .vidioc_qbuf = vb2_ioctl_qbuf, | |
1573 | .vidioc_dqbuf = vb2_ioctl_dqbuf, | |
ca16a64b | 1574 | .vidioc_expbuf = vb2_ioctl_expbuf, |
949bd408 HV |
1575 | .vidioc_streamon = vb2_ioctl_streamon, |
1576 | .vidioc_streamoff = vb2_ioctl_streamoff, | |
abfa3df3 JC |
1577 | .vidioc_g_parm = mcam_vidioc_g_parm, |
1578 | .vidioc_s_parm = mcam_vidioc_s_parm, | |
1579 | .vidioc_enum_framesizes = mcam_vidioc_enum_framesizes, | |
1580 | .vidioc_enum_frameintervals = mcam_vidioc_enum_frameintervals, | |
87d18430 HV |
1581 | .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, |
1582 | .vidioc_unsubscribe_event = v4l2_event_unsubscribe, | |
abfa3df3 JC |
1583 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
1584 | .vidioc_g_register = mcam_vidioc_g_register, | |
1585 | .vidioc_s_register = mcam_vidioc_s_register, | |
1586 | #endif | |
1587 | }; | |
1588 | ||
abfa3df3 JC |
1589 | /* ---------------------------------------------------------------------- */ |
1590 | /* | |
d43dae75 | 1591 | * Our various file operations. |
abfa3df3 | 1592 | */ |
d43dae75 JC |
1593 | static int mcam_v4l_open(struct file *filp) |
1594 | { | |
1595 | struct mcam_camera *cam = video_drvdata(filp); | |
949bd408 | 1596 | int ret; |
abfa3df3 | 1597 | |
d43dae75 | 1598 | mutex_lock(&cam->s_mutex); |
949bd408 HV |
1599 | ret = v4l2_fh_open(filp); |
1600 | if (ret) | |
1601 | goto out; | |
1602 | if (v4l2_fh_is_singular_file(filp)) { | |
05fed816 LY |
1603 | ret = mcam_ctlr_power_up(cam); |
1604 | if (ret) | |
1605 | goto out; | |
d43dae75 JC |
1606 | __mcam_cam_reset(cam); |
1607 | mcam_set_config_needed(cam, 1); | |
1608 | } | |
d43dae75 JC |
1609 | out: |
1610 | mutex_unlock(&cam->s_mutex); | |
44fbcb10 HV |
1611 | if (ret) |
1612 | v4l2_fh_release(filp); | |
d43dae75 | 1613 | return ret; |
a9b36e85 | 1614 | } |
abfa3df3 | 1615 | |
abfa3df3 | 1616 | |
d43dae75 JC |
1617 | static int mcam_v4l_release(struct file *filp) |
1618 | { | |
44fbcb10 | 1619 | struct mcam_camera *cam = video_drvdata(filp); |
949bd408 | 1620 | bool last_open; |
b5210fd2 | 1621 | |
d43dae75 | 1622 | mutex_lock(&cam->s_mutex); |
949bd408 HV |
1623 | last_open = v4l2_fh_is_singular_file(filp); |
1624 | _vb2_fop_release(filp, NULL); | |
1625 | if (last_open) { | |
05fed816 | 1626 | mcam_disable_mipi(cam); |
d43dae75 JC |
1627 | mcam_ctlr_power_down(cam); |
1628 | if (cam->buffer_mode == B_vmalloc && alloc_bufs_at_read) | |
1629 | mcam_free_dma_bufs(cam); | |
1630 | } | |
05fed816 | 1631 | |
d43dae75 JC |
1632 | mutex_unlock(&cam->s_mutex); |
1633 | return 0; | |
abfa3df3 JC |
1634 | } |
1635 | ||
d43dae75 JC |
1636 | static const struct v4l2_file_operations mcam_v4l_fops = { |
1637 | .owner = THIS_MODULE, | |
1638 | .open = mcam_v4l_open, | |
1639 | .release = mcam_v4l_release, | |
949bd408 HV |
1640 | .read = vb2_fop_read, |
1641 | .poll = vb2_fop_poll, | |
1642 | .mmap = vb2_fop_mmap, | |
d43dae75 JC |
1643 | .unlocked_ioctl = video_ioctl2, |
1644 | }; | |
1645 | ||
1646 | ||
1647 | /* | |
1648 | * This template device holds all of those v4l2 methods; we | |
1649 | * clone it for specific real devices. | |
1650 | */ | |
1651 | static struct video_device mcam_v4l_template = { | |
1652 | .name = "mcam", | |
d43dae75 JC |
1653 | .fops = &mcam_v4l_fops, |
1654 | .ioctl_ops = &mcam_v4l_ioctl_ops, | |
1655 | .release = video_device_release_empty, | |
1656 | }; | |
1657 | ||
1658 | /* ---------------------------------------------------------------------- */ | |
1659 | /* | |
1660 | * Interrupt handler stuff | |
1661 | */ | |
abfa3df3 JC |
1662 | static void mcam_frame_complete(struct mcam_camera *cam, int frame) |
1663 | { | |
1664 | /* | |
1665 | * Basic frame housekeeping. | |
1666 | */ | |
abfa3df3 JC |
1667 | set_bit(frame, &cam->flags); |
1668 | clear_bit(CF_DMA_ACTIVE, &cam->flags); | |
a9b36e85 | 1669 | cam->next_buf = frame; |
53423429 | 1670 | cam->buf_seq[frame] = cam->sequence++; |
f698957a | 1671 | cam->frame_state.frames++; |
abfa3df3 | 1672 | /* |
cbc4f3a2 | 1673 | * "This should never happen" |
abfa3df3 | 1674 | */ |
cbc4f3a2 JC |
1675 | if (cam->state != S_STREAMING) |
1676 | return; | |
1677 | /* | |
1678 | * Process the frame and set up the next one. | |
1679 | */ | |
7498469f | 1680 | cam->frame_complete(cam, frame); |
abfa3df3 JC |
1681 | } |
1682 | ||
1683 | ||
d43dae75 JC |
1684 | /* |
1685 | * The interrupt handler; this needs to be called from the | |
1686 | * platform irq handler with the lock held. | |
1687 | */ | |
abfa3df3 JC |
1688 | int mccic_irq(struct mcam_camera *cam, unsigned int irqs) |
1689 | { | |
1690 | unsigned int frame, handled = 0; | |
1691 | ||
1692 | mcam_reg_write(cam, REG_IRQSTAT, FRAMEIRQS); /* Clear'em all */ | |
1693 | /* | |
1694 | * Handle any frame completions. There really should | |
1695 | * not be more than one of these, or we have fallen | |
1696 | * far behind. | |
cbc4f3a2 JC |
1697 | * |
1698 | * When running in S/G mode, the frame number lacks any | |
1699 | * real meaning - there's only one descriptor array - but | |
1700 | * the controller still picks a different one to signal | |
1701 | * each time. | |
abfa3df3 JC |
1702 | */ |
1703 | for (frame = 0; frame < cam->nbufs; frame++) | |
0a0b3fb4 LY |
1704 | if (irqs & (IRQ_EOF0 << frame) && |
1705 | test_bit(CF_FRAME_SOF0 + frame, &cam->flags)) { | |
abfa3df3 JC |
1706 | mcam_frame_complete(cam, frame); |
1707 | handled = 1; | |
0a0b3fb4 | 1708 | clear_bit(CF_FRAME_SOF0 + frame, &cam->flags); |
f2354dd1 JC |
1709 | if (cam->buffer_mode == B_DMA_sg) |
1710 | break; | |
abfa3df3 JC |
1711 | } |
1712 | /* | |
1713 | * If a frame starts, note that we have DMA active. This | |
1714 | * code assumes that we won't get multiple frame interrupts | |
1715 | * at once; may want to rethink that. | |
1716 | */ | |
0a0b3fb4 LY |
1717 | for (frame = 0; frame < cam->nbufs; frame++) { |
1718 | if (irqs & (IRQ_SOF0 << frame)) { | |
1719 | set_bit(CF_FRAME_SOF0 + frame, &cam->flags); | |
1720 | handled = IRQ_HANDLED; | |
1721 | } | |
1722 | } | |
1723 | ||
1724 | if (handled == IRQ_HANDLED) { | |
abfa3df3 | 1725 | set_bit(CF_DMA_ACTIVE, &cam->flags); |
cbc4f3a2 JC |
1726 | if (cam->buffer_mode == B_DMA_sg) |
1727 | mcam_ctlr_stop(cam); | |
abfa3df3 JC |
1728 | } |
1729 | return handled; | |
1730 | } | |
1731 | ||
d43dae75 | 1732 | /* ---------------------------------------------------------------------- */ |
abfa3df3 JC |
1733 | /* |
1734 | * Registration and such. | |
1735 | */ | |
abfa3df3 | 1736 | static struct ov7670_config sensor_cfg = { |
abfa3df3 JC |
1737 | /* |
1738 | * Exclude QCIF mode, because it only captures a tiny portion | |
1739 | * of the sensor FOV | |
1740 | */ | |
1741 | .min_width = 320, | |
1742 | .min_height = 240, | |
1743 | }; | |
1744 | ||
1745 | ||
1746 | int mccic_register(struct mcam_camera *cam) | |
1747 | { | |
1748 | struct i2c_board_info ov7670_info = { | |
1749 | .type = "ov7670", | |
1c68f889 | 1750 | .addr = 0x42 >> 1, |
abfa3df3 JC |
1751 | .platform_data = &sensor_cfg, |
1752 | }; | |
1753 | int ret; | |
1754 | ||
7498469f JC |
1755 | /* |
1756 | * Validate the requested buffer mode. | |
1757 | */ | |
1758 | if (buffer_mode >= 0) | |
1759 | cam->buffer_mode = buffer_mode; | |
1760 | if (cam->buffer_mode == B_DMA_sg && | |
7486af1a | 1761 | cam->chip_id == MCAM_CAFE) { |
7498469f JC |
1762 | printk(KERN_ERR "marvell-cam: Cafe can't do S/G I/O, " |
1763 | "attempting vmalloc mode instead\n"); | |
1764 | cam->buffer_mode = B_vmalloc; | |
1765 | } | |
1766 | if (!mcam_buffer_mode_supported(cam->buffer_mode)) { | |
1767 | printk(KERN_ERR "marvell-cam: buffer mode %d unsupported\n", | |
1768 | cam->buffer_mode); | |
1769 | return -EINVAL; | |
1770 | } | |
abfa3df3 JC |
1771 | /* |
1772 | * Register with V4L | |
1773 | */ | |
1774 | ret = v4l2_device_register(cam->dev, &cam->v4l2_dev); | |
1775 | if (ret) | |
1776 | return ret; | |
1777 | ||
1778 | mutex_init(&cam->s_mutex); | |
1779 | cam->state = S_NOTREADY; | |
1780 | mcam_set_config_needed(cam, 1); | |
abfa3df3 JC |
1781 | cam->pix_format = mcam_def_pix_format; |
1782 | cam->mbus_code = mcam_def_mbus_code; | |
abfa3df3 JC |
1783 | mcam_ctlr_init(cam); |
1784 | ||
1e4cbe67 HV |
1785 | /* |
1786 | * Get the v4l2 setup done. | |
1787 | */ | |
1788 | ret = v4l2_ctrl_handler_init(&cam->ctrl_handler, 10); | |
1789 | if (ret) | |
1790 | goto out_unregister; | |
1791 | cam->v4l2_dev.ctrl_handler = &cam->ctrl_handler; | |
1792 | ||
abfa3df3 JC |
1793 | /* |
1794 | * Try to find the sensor. | |
1795 | */ | |
2164b5af JC |
1796 | sensor_cfg.clock_speed = cam->clock_speed; |
1797 | sensor_cfg.use_smbus = cam->use_smbus; | |
abfa3df3 JC |
1798 | cam->sensor_addr = ov7670_info.addr; |
1799 | cam->sensor = v4l2_i2c_new_subdev_board(&cam->v4l2_dev, | |
595a93a4 | 1800 | cam->i2c_adapter, &ov7670_info, NULL); |
abfa3df3 JC |
1801 | if (cam->sensor == NULL) { |
1802 | ret = -ENODEV; | |
1803 | goto out_unregister; | |
1804 | } | |
1805 | ||
1806 | ret = mcam_cam_init(cam); | |
1807 | if (ret) | |
1808 | goto out_unregister; | |
593403c5 | 1809 | |
949bd408 HV |
1810 | ret = mcam_setup_vb2(cam); |
1811 | if (ret) | |
1812 | goto out_unregister; | |
1813 | ||
abfa3df3 JC |
1814 | mutex_lock(&cam->s_mutex); |
1815 | cam->vdev = mcam_v4l_template; | |
abfa3df3 | 1816 | cam->vdev.v4l2_dev = &cam->v4l2_dev; |
949bd408 HV |
1817 | cam->vdev.lock = &cam->s_mutex; |
1818 | cam->vdev.queue = &cam->vb_queue; | |
593403c5 | 1819 | video_set_drvdata(&cam->vdev, cam); |
abfa3df3 | 1820 | ret = video_register_device(&cam->vdev, VFL_TYPE_GRABBER, -1); |
949bd408 HV |
1821 | if (ret) { |
1822 | mutex_unlock(&cam->s_mutex); | |
1823 | goto out_unregister; | |
1824 | } | |
abfa3df3 JC |
1825 | |
1826 | /* | |
1827 | * If so requested, try to get our DMA buffers now. | |
1828 | */ | |
a9b36e85 | 1829 | if (cam->buffer_mode == B_vmalloc && !alloc_bufs_at_read) { |
abfa3df3 JC |
1830 | if (mcam_alloc_dma_bufs(cam, 1)) |
1831 | cam_warn(cam, "Unable to alloc DMA buffers at load" | |
1832 | " will try again later."); | |
1833 | } | |
1834 | ||
abfa3df3 | 1835 | mutex_unlock(&cam->s_mutex); |
949bd408 HV |
1836 | return 0; |
1837 | ||
abfa3df3 | 1838 | out_unregister: |
1e4cbe67 | 1839 | v4l2_ctrl_handler_free(&cam->ctrl_handler); |
abfa3df3 JC |
1840 | v4l2_device_unregister(&cam->v4l2_dev); |
1841 | return ret; | |
1842 | } | |
1843 | ||
1844 | ||
1845 | void mccic_shutdown(struct mcam_camera *cam) | |
1846 | { | |
67a8dbbc JC |
1847 | /* |
1848 | * If we have no users (and we really, really should have no | |
1849 | * users) the device will already be powered down. Trying to | |
1850 | * take it down again will wedge the machine, which is frowned | |
1851 | * upon. | |
1852 | */ | |
949bd408 | 1853 | if (!list_empty(&cam->vdev.fh_list)) { |
abfa3df3 | 1854 | cam_warn(cam, "Removing a device with users!\n"); |
67a8dbbc JC |
1855 | mcam_ctlr_power_down(cam); |
1856 | } | |
a9b36e85 JC |
1857 | if (cam->buffer_mode == B_vmalloc) |
1858 | mcam_free_dma_bufs(cam); | |
abfa3df3 | 1859 | video_unregister_device(&cam->vdev); |
593403c5 | 1860 | v4l2_ctrl_handler_free(&cam->ctrl_handler); |
abfa3df3 JC |
1861 | v4l2_device_unregister(&cam->v4l2_dev); |
1862 | } | |
1863 | ||
1864 | /* | |
1865 | * Power management | |
1866 | */ | |
1867 | #ifdef CONFIG_PM | |
1868 | ||
1869 | void mccic_suspend(struct mcam_camera *cam) | |
1870 | { | |
bb0a896e | 1871 | mutex_lock(&cam->s_mutex); |
949bd408 | 1872 | if (!list_empty(&cam->vdev.fh_list)) { |
bb0a896e | 1873 | enum mcam_state cstate = cam->state; |
abfa3df3 | 1874 | |
bb0a896e JC |
1875 | mcam_ctlr_stop_dma(cam); |
1876 | mcam_ctlr_power_down(cam); | |
1877 | cam->state = cstate; | |
1878 | } | |
1879 | mutex_unlock(&cam->s_mutex); | |
abfa3df3 JC |
1880 | } |
1881 | ||
1882 | int mccic_resume(struct mcam_camera *cam) | |
1883 | { | |
1884 | int ret = 0; | |
1885 | ||
1886 | mutex_lock(&cam->s_mutex); | |
949bd408 | 1887 | if (!list_empty(&cam->vdev.fh_list)) { |
05fed816 LY |
1888 | ret = mcam_ctlr_power_up(cam); |
1889 | if (ret) { | |
1890 | mutex_unlock(&cam->s_mutex); | |
1891 | return ret; | |
1892 | } | |
abfa3df3 JC |
1893 | __mcam_cam_reset(cam); |
1894 | } else { | |
1895 | mcam_ctlr_power_down(cam); | |
1896 | } | |
1897 | mutex_unlock(&cam->s_mutex); | |
1898 | ||
1899 | set_bit(CF_CONFIG_NEEDED, &cam->flags); | |
bb0a896e JC |
1900 | if (cam->state == S_STREAMING) { |
1901 | /* | |
1902 | * If there was a buffer in the DMA engine at suspend | |
1903 | * time, put it back on the queue or we'll forget about it. | |
1904 | */ | |
1905 | if (cam->buffer_mode == B_DMA_sg && cam->vb_bufs[0]) | |
1906 | list_add(&cam->vb_bufs[0]->queue, &cam->buffers); | |
a9b36e85 | 1907 | ret = mcam_read_setup(cam); |
bb0a896e | 1908 | } |
abfa3df3 JC |
1909 | return ret; |
1910 | } | |
1911 | #endif /* CONFIG_PM */ |