[mirror_ubuntu-focal-kernel.git] / drivers / media / platform / marvell-ccic / mcam-core.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Marvell camera core structures.
 *
 * Copyright 2011 Jonathan Corbet corbet@lwn.net
 */
#ifndef _MCAM_CORE_H
#define _MCAM_CORE_H

#include <linux/list.h>
#include <media/v4l2-common.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-dev.h>
#include <media/videobuf2-v4l2.h>

/*
 * Create our own symbols for the supported buffer modes, but, for now,
 * base them entirely on which videobuf2 options have been selected.
 */
#if IS_ENABLED(CONFIG_VIDEOBUF2_VMALLOC)
#define MCAM_MODE_VMALLOC 1
#endif

#if IS_ENABLED(CONFIG_VIDEOBUF2_DMA_CONTIG)
#define MCAM_MODE_DMA_CONTIG 1
#endif

#if IS_ENABLED(CONFIG_VIDEOBUF2_DMA_SG)
#define MCAM_MODE_DMA_SG 1
#endif

#if !defined(MCAM_MODE_VMALLOC) && !defined(MCAM_MODE_DMA_CONTIG) && \
	!defined(MCAM_MODE_DMA_SG)
#error One of the videobuf buffer modes must be selected in the config
#endif


enum mcam_state {
	S_NOTREADY,	/* Not yet initialized */
	S_IDLE,		/* Just hanging around */
	S_FLAKED,	/* Some sort of problem */
	S_STREAMING,	/* Streaming data */
	S_BUFWAIT	/* streaming requested but no buffers yet */
};
#define MAX_DMA_BUFS 3

/*
 * Different platforms work best with different buffer modes, so we
 * let the platform pick.
 */
enum mcam_buffer_mode {
	B_vmalloc = 0,
	B_DMA_contig = 1,
	B_DMA_sg = 2
};

enum mcam_chip_id {
	MCAM_CAFE,
	MCAM_ARMADA610,
};

/*
 * Is a given buffer mode supported by the current kernel configuration?
 */
static inline int mcam_buffer_mode_supported(enum mcam_buffer_mode mode)
{
	switch (mode) {
#ifdef MCAM_MODE_VMALLOC
	case B_vmalloc:
#endif
#ifdef MCAM_MODE_DMA_CONTIG
	case B_DMA_contig:
#endif
#ifdef MCAM_MODE_DMA_SG
	case B_DMA_sg:
#endif
		return 1;
	default:
		return 0;
	}
}

/*
 * Basic frame states
 */
struct mcam_frame_state {
	unsigned int frames;
	unsigned int singles;
	unsigned int delivered;
};

#define NR_MCAM_CLK 3

/*
 * A description of one of our devices.
 * Locking: controlled by s_mutex.  Certain fields, however, require
 *          the dev_lock spinlock; they are marked as such by comments.
 *          dev_lock is also required for access to device registers.
 */
struct mcam_camera {
	/*
	 * These fields should be set by the platform code prior to
	 * calling mcam_register().
	 */
	struct i2c_adapter *i2c_adapter;
	unsigned char __iomem *regs;
	unsigned regs_size; /* size in bytes of the register space */
	spinlock_t dev_lock;
	struct device *dev; /* For messages, dma alloc */
	enum mcam_chip_id chip_id;
	short int clock_speed;	/* Sensor clock speed, default 30 */
	short int use_smbus;	/* SMBUS or straight I2c? */
	enum mcam_buffer_mode buffer_mode;

	int mclk_min;	/* The minimal value of mclk */
	int mclk_src;	/* which clock source the mclk derives from */
	int mclk_div;	/* Clock Divider Value for MCLK */

	int ccic_id;
	enum v4l2_mbus_type bus_type;
	/* MIPI support */
	/* The dphy config value, allocated in board file
	 * dphy[0]: DPHY3
	 * dphy[1]: DPHY5
	 * dphy[2]: DPHY6
	 */
	int *dphy;
	bool mipi_enabled;	/* flag whether mipi is enabled already */
	int lane;			/* lane number */

	/* clock tree support */
	struct clk *clk[NR_MCAM_CLK];

	/*
	 * Callbacks from the core to the platform code.
	 */
	int (*plat_power_up) (struct mcam_camera *cam);
	void (*plat_power_down) (struct mcam_camera *cam);
	void (*calc_dphy) (struct mcam_camera *cam);
	void (*ctlr_reset) (struct mcam_camera *cam);

	/*
	 * Everything below here is private to the mcam core and
	 * should not be touched by the platform code.
	 */
	struct v4l2_device v4l2_dev;
	struct v4l2_ctrl_handler ctrl_handler;
	enum mcam_state state;
	unsigned long flags;		/* Buffer status, mainly (dev_lock) */

	struct mcam_frame_state frame_state;	/* Frame state counter */
	/*
	 * Subsystem structures.
	 */
	struct video_device vdev;
	struct v4l2_subdev *sensor;
	unsigned short sensor_addr;

	/* Videobuf2 stuff */
	struct vb2_queue vb_queue;
	struct list_head buffers;	/* Available frames */

	unsigned int nbufs;		/* How many are alloc'd */
	int next_buf;			/* Next to consume (dev_lock) */

	char bus_info[32];		/* querycap bus_info */

	/* DMA buffers - vmalloc mode */
#ifdef MCAM_MODE_VMALLOC
	unsigned int dma_buf_size;	/* allocated size */
	void *dma_bufs[MAX_DMA_BUFS];	/* Internal buffer addresses */
	dma_addr_t dma_handles[MAX_DMA_BUFS]; /* Buffer bus addresses */
	struct tasklet_struct s_tasklet;
#endif
	unsigned int sequence;		/* Frame sequence number */
	unsigned int buf_seq[MAX_DMA_BUFS]; /* Sequence for individual bufs */

	/* DMA buffers - DMA modes */
	struct mcam_vb_buffer *vb_bufs[MAX_DMA_BUFS];

	/* Mode-specific ops, set at open time */
	void (*dma_setup)(struct mcam_camera *cam);
	void (*frame_complete)(struct mcam_camera *cam, int frame);

	/* Current operating parameters */
	struct v4l2_pix_format pix_format;
	u32 mbus_code;

	/* Locks */
	struct mutex s_mutex; /* Access to this structure */
};


/*
 * Register I/O functions.  These are here because the platform code
 * may legitimately need to mess with the register space.
 */
/*
 * Device register I/O
 */
static inline void mcam_reg_write(struct mcam_camera *cam, unsigned int reg,
		unsigned int val)
{
	iowrite32(val, cam->regs + reg);
}

static inline unsigned int mcam_reg_read(struct mcam_camera *cam,
		unsigned int reg)
{
	return ioread32(cam->regs + reg);
}


static inline void mcam_reg_write_mask(struct mcam_camera *cam, unsigned int reg,
		unsigned int val, unsigned int mask)
{
	unsigned int v = mcam_reg_read(cam, reg);

	v = (v & ~mask) | (val & mask);
	mcam_reg_write(cam, reg, v);
}

static inline void mcam_reg_clear_bit(struct mcam_camera *cam,
		unsigned int reg, unsigned int val)
{
	mcam_reg_write_mask(cam, reg, 0, val);
}

static inline void mcam_reg_set_bit(struct mcam_camera *cam,
		unsigned int reg, unsigned int val)
{
	mcam_reg_write_mask(cam, reg, val, val);
}

/*
 * Functions for use by platform code.
 */
int mccic_register(struct mcam_camera *cam);
int mccic_irq(struct mcam_camera *cam, unsigned int irqs);
void mccic_shutdown(struct mcam_camera *cam);
#ifdef CONFIG_PM
void mccic_suspend(struct mcam_camera *cam);
int mccic_resume(struct mcam_camera *cam);
#endif

/*
 * Register definitions for the m88alp01 camera interface.  Offsets in bytes
 * as given in the spec.
 */
#define REG_Y0BAR	0x00
#define REG_Y1BAR	0x04
#define REG_Y2BAR	0x08
#define REG_U0BAR	0x0c
#define REG_U1BAR	0x10
#define REG_U2BAR	0x14
#define REG_V0BAR	0x18
#define REG_V1BAR	0x1C
#define REG_V2BAR	0x20

/*
 * register definitions for MIPI support
 */
#define REG_CSI2_CTRL0	0x100
#define   CSI2_C0_MIPI_EN (0x1 << 0)
#define   CSI2_C0_ACT_LANE(n) ((n-1) << 1)
#define REG_CSI2_DPHY3	0x12c
#define REG_CSI2_DPHY5	0x134
#define REG_CSI2_DPHY6	0x138

/* ... */

#define REG_IMGPITCH	0x24	/* Image pitch register */
#define   IMGP_YP_SHFT	  2		/* Y pitch params */
#define   IMGP_YP_MASK	  0x00003ffc	/* Y pitch field */
#define	  IMGP_UVP_SHFT	  18		/* UV pitch (planar) */
#define   IMGP_UVP_MASK   0x3ffc0000
#define REG_IRQSTATRAW	0x28	/* RAW IRQ Status */
#define   IRQ_EOF0	  0x00000001	/* End of frame 0 */
#define   IRQ_EOF1	  0x00000002	/* End of frame 1 */
#define   IRQ_EOF2	  0x00000004	/* End of frame 2 */
#define   IRQ_SOF0	  0x00000008	/* Start of frame 0 */
#define   IRQ_SOF1	  0x00000010	/* Start of frame 1 */
#define   IRQ_SOF2	  0x00000020	/* Start of frame 2 */
#define   IRQ_OVERFLOW	  0x00000040	/* FIFO overflow */
#define   IRQ_TWSIW	  0x00010000	/* TWSI (smbus) write */
#define   IRQ_TWSIR	  0x00020000	/* TWSI read */
#define   IRQ_TWSIE	  0x00040000	/* TWSI error */
#define   TWSIIRQS (IRQ_TWSIW|IRQ_TWSIR|IRQ_TWSIE)
#define   FRAMEIRQS (IRQ_EOF0|IRQ_EOF1|IRQ_EOF2|IRQ_SOF0|IRQ_SOF1|IRQ_SOF2)
#define   ALLIRQS (TWSIIRQS|FRAMEIRQS|IRQ_OVERFLOW)
#define REG_IRQMASK	0x2c	/* IRQ mask - same bits as IRQSTAT */
#define REG_IRQSTAT	0x30	/* IRQ status / clear */

#define REG_IMGSIZE	0x34	/* Image size */
#define  IMGSZ_V_MASK	  0x1fff0000
#define  IMGSZ_V_SHIFT	  16
#define	 IMGSZ_H_MASK	  0x00003fff
#define REG_IMGOFFSET	0x38	/* IMage offset */

#define REG_CTRL0	0x3c	/* Control 0 */
#define   C0_ENABLE	  0x00000001	/* Makes the whole thing go */

/* Mask for all the format bits */
#define   C0_DF_MASK	  0x00fffffc    /* Bits 2-23 */

/* RGB ordering */
#define	  C0_RGB4_RGBX	  0x00000000
#define	  C0_RGB4_XRGB	  0x00000004
#define	  C0_RGB4_BGRX	  0x00000008
#define	  C0_RGB4_XBGR	  0x0000000c
#define	  C0_RGB5_RGGB	  0x00000000
#define	  C0_RGB5_GRBG	  0x00000004
#define	  C0_RGB5_GBRG	  0x00000008
#define	  C0_RGB5_BGGR	  0x0000000c

/* Spec has two fields for DIN and DOUT, but they must match, so
   combine them here. */
#define	  C0_DF_YUV	  0x00000000	/* Data is YUV	    */
#define	  C0_DF_RGB	  0x000000a0	/* ... RGB		    */
#define	  C0_DF_BAYER	  0x00000140	/* ... Bayer		    */
/* 8-8-8 must be missing from the below - ask */
#define	  C0_RGBF_565	  0x00000000
#define	  C0_RGBF_444	  0x00000800
#define	  C0_RGB_BGR	  0x00001000	/* Blue comes first */
#define	  C0_YUV_PLANAR	  0x00000000	/* YUV 422 planar format */
#define	  C0_YUV_PACKED	  0x00008000	/* YUV 422 packed	*/
#define	  C0_YUV_420PL	  0x0000a000	/* YUV 420 planar	*/
/* Think that 420 packed must be 111 - ask */
#define	  C0_YUVE_YUYV	  0x00000000	/* Y1CbY0Cr		*/
#define	  C0_YUVE_YVYU	  0x00010000	/* Y1CrY0Cb		*/
#define	  C0_YUVE_VYUY	  0x00020000	/* CrY1CbY0		*/
#define	  C0_YUVE_UYVY	  0x00030000	/* CbY1CrY0		*/
#define	  C0_YUVE_NOSWAP  0x00000000	/* no bytes swapping	*/
#define	  C0_YUVE_SWAP13  0x00010000	/* swap byte 1 and 3	*/
#define	  C0_YUVE_SWAP24  0x00020000	/* swap byte 2 and 4	*/
#define	  C0_YUVE_SWAP1324 0x00030000	/* swap bytes 1&3 and 2&4 */
/* Bayer bits 18,19 if needed */
#define	  C0_EOF_VSYNC	  0x00400000	/* Generate EOF by VSYNC */
#define	  C0_VEDGE_CTRL   0x00800000	/* Detect falling edge of VSYNC */
#define	  C0_HPOL_LOW	  0x01000000	/* HSYNC polarity active low */
#define	  C0_VPOL_LOW	  0x02000000	/* VSYNC polarity active low */
#define	  C0_VCLK_LOW	  0x04000000	/* VCLK on falling edge */
#define	  C0_DOWNSCALE	  0x08000000	/* Enable downscaler */
/* SIFMODE */
#define	  C0_SIF_HVSYNC	  0x00000000	/* Use H/VSYNC */
#define	  C0_SOF_NOSYNC	  0x40000000	/* Use inband active signaling */
#define	  C0_SIFM_MASK	  0xc0000000	/* SIF mode bits */

/* Bits below C1_444ALPHA are not present in Cafe */
#define REG_CTRL1	0x40	/* Control 1 */
#define	  C1_CLKGATE	  0x00000001	/* Sensor clock gate */
#define   C1_DESC_ENA	  0x00000100	/* DMA descriptor enable */
#define   C1_DESC_3WORD   0x00000200	/* Three-word descriptors used */
#define	  C1_444ALPHA	  0x00f00000	/* Alpha field in RGB444 */
#define	  C1_ALPHA_SHFT	  20
#define	  C1_DMAB32	  0x00000000	/* 32-byte DMA burst */
#define	  C1_DMAB16	  0x02000000	/* 16-byte DMA burst */
#define	  C1_DMAB64	  0x04000000	/* 64-byte DMA burst */
#define	  C1_DMAB_MASK	  0x06000000
#define	  C1_TWOBUFS	  0x08000000	/* Use only two DMA buffers */
#define	  C1_PWRDWN	  0x10000000	/* Power down */

#define REG_CLKCTRL	0x88	/* Clock control */
#define	  CLK_DIV_MASK	  0x0000ffff	/* Upper bits RW "reserved" */

/* This appears to be a Cafe-only register */
#define REG_UBAR	0xc4	/* Upper base address register */

/* Armada 610 DMA descriptor registers */
#define	REG_DMA_DESC_Y	0x200
#define	REG_DMA_DESC_U	0x204
#define	REG_DMA_DESC_V	0x208
#define REG_DESC_LEN_Y	0x20c	/* Lengths are in bytes */
#define	REG_DESC_LEN_U	0x210
#define REG_DESC_LEN_V	0x214

/*
 * Useful stuff that probably belongs somewhere global.
 */
#define VGA_WIDTH	640
#define VGA_HEIGHT	480

#endif /* _MCAM_CORE_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
abfa3df3 JC	2	/*
	3	* Marvell camera core structures.
	4	*
	5	* Copyright 2011 Jonathan Corbet corbet@lwn.net
	6	*/
b5210fd2 JC	7	#ifndef _MCAM_CORE_H
	8	#define _MCAM_CORE_H
	9
	10	#include <linux/list.h>
	11	#include <media/v4l2-common.h>
593403c5	12	#include <media/v4l2-ctrls.h>
b5210fd2	13	#include <media/v4l2-dev.h>
c139990e	14	#include <media/videobuf2-v4l2.h>
abfa3df3	15
7498469f JC	16	/*
	17	* Create our own symbols for the supported buffer modes, but, for now,
	18	* base them entirely on which videobuf2 options have been selected.
	19	*/
f1c16adc	20	#if IS_ENABLED(CONFIG_VIDEOBUF2_VMALLOC)
7498469f JC	21	#define MCAM_MODE_VMALLOC 1
	22	#endif
	23
f1c16adc	24	#if IS_ENABLED(CONFIG_VIDEOBUF2_DMA_CONTIG)
7498469f JC	25	#define MCAM_MODE_DMA_CONTIG 1
	26	#endif
	27
f1c16adc	28	#if IS_ENABLED(CONFIG_VIDEOBUF2_DMA_SG)
7498469f JC	29	#define MCAM_MODE_DMA_SG 1
	30	#endif
	31
	32	#if !defined(MCAM_MODE_VMALLOC) && !defined(MCAM_MODE_DMA_CONTIG) && \
	33	!defined(MCAM_MODE_DMA_SG)
	34	#error One of the videobuf buffer modes must be selected in the config
	35	#endif
	36
abfa3df3 JC	37
	38	enum mcam_state {
	39	S_NOTREADY, /* Not yet initialized */
	40	S_IDLE, /* Just hanging around */
	41	S_FLAKED, /* Some sort of problem */
a9b36e85 JC	42	S_STREAMING, /* Streaming data */
a9b36e85 JC	43	S_BUFWAIT /* streaming requested but no buffers yet */
abfa3df3 JC	44	};
	45	#define MAX_DMA_BUFS 3
	46
a9b36e85 JC	47	/*
	48	* Different platforms work best with different buffer modes, so we
	49	* let the platform pick.
	50	*/
	51	enum mcam_buffer_mode {
	52	B_vmalloc = 0,
7498469f JC	53	B_DMA_contig = 1,
7498469f JC	54	B_DMA_sg = 2
a9b36e85 JC	55	};
a9b36e85 JC	56
7486af1a HV	57	enum mcam_chip_id {
	58	MCAM_CAFE,
	59	MCAM_ARMADA610,
	60	};
	61
7498469f JC	62	/*
	63	* Is a given buffer mode supported by the current kernel configuration?
	64	*/
	65	static inline int mcam_buffer_mode_supported(enum mcam_buffer_mode mode)
	66	{
	67	switch (mode) {
	68	#ifdef MCAM_MODE_VMALLOC
	69	case B_vmalloc:
	70	#endif
	71	#ifdef MCAM_MODE_DMA_CONTIG
	72	case B_DMA_contig:
	73	#endif
	74	#ifdef MCAM_MODE_DMA_SG
	75	case B_DMA_sg:
	76	#endif
	77	return 1;
	78	default:
	79	return 0;
	80	}
	81	}
	82
f698957a LY	83	/*
	84	* Basic frame states
	85	*/
	86	struct mcam_frame_state {
	87	unsigned int frames;
	88	unsigned int singles;
	89	unsigned int delivered;
	90	};
7498469f	91
0e394f44 LY	92	#define NR_MCAM_CLK 3
0e394f44 LY	93
abfa3df3 JC	94	/*
	95	* A description of one of our devices.
	96	* Locking: controlled by s_mutex. Certain fields, however, require
	97	* the dev_lock spinlock; they are marked as such by comments.
	98	* dev_lock is also required for access to device registers.
	99	*/
	100	struct mcam_camera {
	101	/*
	102	* These fields should be set by the platform code prior to
	103	* calling mcam_register().
	104	*/
595a93a4	105	struct i2c_adapter *i2c_adapter;
abfa3df3	106	unsigned char __iomem *regs;
4e032f3f	107	unsigned regs_size; /* size in bytes of the register space */
abfa3df3 JC	108	spinlock_t dev_lock;
abfa3df3 JC	109	struct device dev; / For messages, dma alloc */
7486af1a	110	enum mcam_chip_id chip_id;
2164b5af JC	111	short int clock_speed; /* Sensor clock speed, default 30 */
2164b5af JC	112	short int use_smbus; /* SMBUS or straight I2c? */
a9b36e85	113	enum mcam_buffer_mode buffer_mode;
05fed816 LY	114
	115	int mclk_min; /* The minimal value of mclk */
	116	int mclk_src; /* which clock source the mclk derives from */
	117	int mclk_div; /* Clock Divider Value for MCLK */
	118
7c269f45	119	int ccic_id;
05fed816 LY	120	enum v4l2_mbus_type bus_type;
	121	/* MIPI support */
	122	/* The dphy config value, allocated in board file
	123	* dphy[0]: DPHY3
	124	* dphy[1]: DPHY5
	125	* dphy[2]: DPHY6
	126	*/
	127	int *dphy;
	128	bool mipi_enabled; /* flag whether mipi is enabled already */
	129	int lane; /* lane number */
	130
0e394f44 LY	131	/* clock tree support */
	132	struct clk *clk[NR_MCAM_CLK];
	133
abfa3df3 JC	134	/*
	135	* Callbacks from the core to the platform code.
	136	*/
05fed816	137	int (plat_power_up) (struct mcam_camera cam);
abfa3df3	138	void (plat_power_down) (struct mcam_camera cam);
05fed816	139	void (calc_dphy) (struct mcam_camera cam);
7c269f45	140	void (ctlr_reset) (struct mcam_camera cam);
abfa3df3 JC	141
	142	/*
	143	* Everything below here is private to the mcam core and
	144	* should not be touched by the platform code.
	145	*/
	146	struct v4l2_device v4l2_dev;
593403c5	147	struct v4l2_ctrl_handler ctrl_handler;
abfa3df3 JC	148	enum mcam_state state;
abfa3df3 JC	149	unsigned long flags; /* Buffer status, mainly (dev_lock) */
abfa3df3	150
f698957a	151	struct mcam_frame_state frame_state; /* Frame state counter */
abfa3df3 JC	152	/*
	153	* Subsystem structures.
	154	*/
	155	struct video_device vdev;
	156	struct v4l2_subdev *sensor;
	157	unsigned short sensor_addr;
	158
b5210fd2 JC	159	/* Videobuf2 stuff */
	160	struct vb2_queue vb_queue;
	161	struct list_head buffers; /* Available frames */
	162
abfa3df3 JC	163	unsigned int nbufs; /* How many are alloc'd */
abfa3df3 JC	164	int next_buf; /* Next to consume (dev_lock) */
7498469f	165
b7b68393 HV	166	char bus_info[32]; /* querycap bus_info */
b7b68393 HV	167
7498469f JC	168	/* DMA buffers - vmalloc mode */
7498469f JC	169	#ifdef MCAM_MODE_VMALLOC
abfa3df3 JC	170	unsigned int dma_buf_size; /* allocated size */
	171	void dma_bufs[MAX_DMA_BUFS]; / Internal buffer addresses */
	172	dma_addr_t dma_handles[MAX_DMA_BUFS]; /* Buffer bus addresses */
7498469f JC	173	struct tasklet_struct s_tasklet;
7498469f JC	174	#endif
abfa3df3	175	unsigned int sequence; /* Frame sequence number */
b5210fd2	176	unsigned int buf_seq[MAX_DMA_BUFS]; /* Sequence for individual bufs */
abfa3df3	177
7498469f	178	/* DMA buffers - DMA modes */
a9b36e85	179	struct mcam_vb_buffer *vb_bufs[MAX_DMA_BUFS];
a9b36e85	180
7498469f JC	181	/* Mode-specific ops, set at open time */
	182	void (dma_setup)(struct mcam_camera cam);
	183	void (frame_complete)(struct mcam_camera cam, int frame);
abfa3df3 JC	184
abfa3df3 JC	185	/* Current operating parameters */
abfa3df3	186	struct v4l2_pix_format pix_format;
27ffaeb0	187	u32 mbus_code;
abfa3df3 JC	188
	189	/* Locks */
	190	struct mutex s_mutex; /* Access to this structure */
abfa3df3 JC	191	};
	192
	193
	194	/*
	195	* Register I/O functions. These are here because the platform code
	196	* may legitimately need to mess with the register space.
	197	*/
	198	/*
	199	* Device register I/O
	200	*/
	201	static inline void mcam_reg_write(struct mcam_camera *cam, unsigned int reg,
	202	unsigned int val)
	203	{
	204	iowrite32(val, cam->regs + reg);
	205	}
	206
	207	static inline unsigned int mcam_reg_read(struct mcam_camera *cam,
	208	unsigned int reg)
	209	{
	210	return ioread32(cam->regs + reg);
	211	}
	212
	213
	214	static inline void mcam_reg_write_mask(struct mcam_camera *cam, unsigned int reg,
	215	unsigned int val, unsigned int mask)
	216	{
	217	unsigned int v = mcam_reg_read(cam, reg);
	218
	219	v = (v & ~mask) \| (val & mask);
	220	mcam_reg_write(cam, reg, v);
	221	}
	222
	223	static inline void mcam_reg_clear_bit(struct mcam_camera *cam,
	224	unsigned int reg, unsigned int val)
	225	{
	226	mcam_reg_write_mask(cam, reg, 0, val);
	227	}
	228
	229	static inline void mcam_reg_set_bit(struct mcam_camera *cam,
	230	unsigned int reg, unsigned int val)
	231	{
	232	mcam_reg_write_mask(cam, reg, val, val);
	233	}
	234
	235	/*
	236	* Functions for use by platform code.
	237	*/
	238	int mccic_register(struct mcam_camera *cam);
	239	int mccic_irq(struct mcam_camera *cam, unsigned int irqs);
	240	void mccic_shutdown(struct mcam_camera *cam);
	241	#ifdef CONFIG_PM
	242	void mccic_suspend(struct mcam_camera *cam);
	243	int mccic_resume(struct mcam_camera *cam);
	244	#endif
	245
	246	/*
	247	* Register definitions for the m88alp01 camera interface. Offsets in bytes
	248	* as given in the spec.
	249	*/
	250	#define REG_Y0BAR 0x00
	251	#define REG_Y1BAR 0x04
	252	#define REG_Y2BAR 0x08
ad6ac452 LY	253	#define REG_U0BAR 0x0c
	254	#define REG_U1BAR 0x10
	255	#define REG_U2BAR 0x14
	256	#define REG_V0BAR 0x18
	257	#define REG_V1BAR 0x1C
	258	#define REG_V2BAR 0x20
05fed816 LY	259
	260	/*
	261	* register definitions for MIPI support
	262	*/
	263	#define REG_CSI2_CTRL0 0x100
	264	#define CSI2_C0_MIPI_EN (0x1 << 0)
	265	#define CSI2_C0_ACT_LANE(n) ((n-1) << 1)
	266	#define REG_CSI2_DPHY3 0x12c
	267	#define REG_CSI2_DPHY5 0x134
	268	#define REG_CSI2_DPHY6 0x138
	269
abfa3df3 JC	270	/* ... */
	271
	272	#define REG_IMGPITCH 0x24 /* Image pitch register */
	273	#define IMGP_YP_SHFT 2 /* Y pitch params */
	274	#define IMGP_YP_MASK 0x00003ffc /* Y pitch field */
	275	#define IMGP_UVP_SHFT 18 /* UV pitch (planar) */
	276	#define IMGP_UVP_MASK 0x3ffc0000
	277	#define REG_IRQSTATRAW 0x28 /* RAW IRQ Status */
	278	#define IRQ_EOF0 0x00000001 /* End of frame 0 */
	279	#define IRQ_EOF1 0x00000002 /* End of frame 1 */
	280	#define IRQ_EOF2 0x00000004 /* End of frame 2 */
	281	#define IRQ_SOF0 0x00000008 /* Start of frame 0 */
	282	#define IRQ_SOF1 0x00000010 /* Start of frame 1 */
	283	#define IRQ_SOF2 0x00000020 /* Start of frame 2 */
	284	#define IRQ_OVERFLOW 0x00000040 /* FIFO overflow */
	285	#define IRQ_TWSIW 0x00010000 /* TWSI (smbus) write */
	286	#define IRQ_TWSIR 0x00020000 /* TWSI read */
	287	#define IRQ_TWSIE 0x00040000 /* TWSI error */
	288	#define TWSIIRQS (IRQ_TWSIW\|IRQ_TWSIR\|IRQ_TWSIE)
	289	#define FRAMEIRQS (IRQ_EOF0\|IRQ_EOF1\|IRQ_EOF2\|IRQ_SOF0\|IRQ_SOF1\|IRQ_SOF2)
	290	#define ALLIRQS (TWSIIRQS\|FRAMEIRQS\|IRQ_OVERFLOW)
	291	#define REG_IRQMASK 0x2c /* IRQ mask - same bits as IRQSTAT */
	292	#define REG_IRQSTAT 0x30 /* IRQ status / clear */
	293
	294	#define REG_IMGSIZE 0x34 /* Image size */
	295	#define IMGSZ_V_MASK 0x1fff0000
	296	#define IMGSZ_V_SHIFT 16
	297	#define IMGSZ_H_MASK 0x00003fff
	298	#define REG_IMGOFFSET 0x38 /* IMage offset */
	299
	300	#define REG_CTRL0 0x3c /* Control 0 */
	301	#define C0_ENABLE 0x00000001 /* Makes the whole thing go */
	302
	303	/* Mask for all the format bits */
	304	#define C0_DF_MASK 0x00fffffc /* Bits 2-23 */
	305
	306	/* RGB ordering */
	307	#define C0_RGB4_RGBX 0x00000000
	308	#define C0_RGB4_XRGB 0x00000004
	309	#define C0_RGB4_BGRX 0x00000008
	310	#define C0_RGB4_XBGR 0x0000000c
	311	#define C0_RGB5_RGGB 0x00000000
	312	#define C0_RGB5_GRBG 0x00000004
	313	#define C0_RGB5_GBRG 0x00000008
	314	#define C0_RGB5_BGGR 0x0000000c
	315
	316	/* Spec has two fields for DIN and DOUT, but they must match, so
	317	combine them here. */
	318	#define C0_DF_YUV 0x00000000 /* Data is YUV */
	319	#define C0_DF_RGB 0x000000a0 /* ... RGB */
	320	#define C0_DF_BAYER 0x00000140 /* ... Bayer */
	321	/* 8-8-8 must be missing from the below - ask */
	322	#define C0_RGBF_565 0x00000000
	323	#define C0_RGBF_444 0x00000800
	324	#define C0_RGB_BGR 0x00001000 /* Blue comes first */
	325	#define C0_YUV_PLANAR 0x00000000 /* YUV 422 planar format */
	326	#define C0_YUV_PACKED 0x00008000 /* YUV 422 packed */
	327	#define C0_YUV_420PL 0x0000a000 /* YUV 420 planar */
	328	/* Think that 420 packed must be 111 - ask */
	329	#define C0_YUVE_YUYV 0x00000000 /* Y1CbY0Cr */
	330	#define C0_YUVE_YVYU 0x00010000 /* Y1CrY0Cb */
	331	#define C0_YUVE_VYUY 0x00020000 /* CrY1CbY0 */
	332	#define C0_YUVE_UYVY 0x00030000 /* CbY1CrY0 */
2a700d8e HV	333	#define C0_YUVE_NOSWAP 0x00000000 /* no bytes swapping */
	334	#define C0_YUVE_SWAP13 0x00010000 /* swap byte 1 and 3 */
	335	#define C0_YUVE_SWAP24 0x00020000 /* swap byte 2 and 4 */
	336	#define C0_YUVE_SWAP1324 0x00030000 /* swap bytes 1&3 and 2&4 */
abfa3df3	337	/* Bayer bits 18,19 if needed */
05fed816 LY	338	#define C0_EOF_VSYNC 0x00400000 /* Generate EOF by VSYNC */
05fed816 LY	339	#define C0_VEDGE_CTRL 0x00800000 /* Detect falling edge of VSYNC */
abfa3df3 JC	340	#define C0_HPOL_LOW 0x01000000 /* HSYNC polarity active low */
	341	#define C0_VPOL_LOW 0x02000000 /* VSYNC polarity active low */
	342	#define C0_VCLK_LOW 0x04000000 /* VCLK on falling edge */
	343	#define C0_DOWNSCALE 0x08000000 /* Enable downscaler */
05fed816	344	/* SIFMODE */
abfa3df3	345	#define C0_SIF_HVSYNC 0x00000000 /* Use H/VSYNC */
05fed816 LY	346	#define C0_SOF_NOSYNC 0x40000000 /* Use inband active signaling */
05fed816 LY	347	#define C0_SIFM_MASK 0xc0000000 /* SIF mode bits */
abfa3df3	348
cbc4f3a2	349	/* Bits below C1_444ALPHA are not present in Cafe */
abfa3df3	350	#define REG_CTRL1 0x40 /* Control 1 */
cbc4f3a2 JC	351	#define C1_CLKGATE 0x00000001 /* Sensor clock gate */
	352	#define C1_DESC_ENA 0x00000100 /* DMA descriptor enable */
	353	#define C1_DESC_3WORD 0x00000200 /* Three-word descriptors used */
abfa3df3 JC	354	#define C1_444ALPHA 0x00f00000 /* Alpha field in RGB444 */
	355	#define C1_ALPHA_SHFT 20
	356	#define C1_DMAB32 0x00000000 /* 32-byte DMA burst */
	357	#define C1_DMAB16 0x02000000 /* 16-byte DMA burst */
	358	#define C1_DMAB64 0x04000000 /* 64-byte DMA burst */
	359	#define C1_DMAB_MASK 0x06000000
	360	#define C1_TWOBUFS 0x08000000 /* Use only two DMA buffers */
	361	#define C1_PWRDWN 0x10000000 /* Power down */
	362
	363	#define REG_CLKCTRL 0x88 /* Clock control */
	364	#define CLK_DIV_MASK 0x0000ffff /* Upper bits RW "reserved" */
	365
f8ff6a96	366	/* This appears to be a Cafe-only register */
abfa3df3 JC	367	#define REG_UBAR 0xc4 /* Upper base address register */
abfa3df3 JC	368
cbc4f3a2 JC	369	/* Armada 610 DMA descriptor registers */
	370	#define REG_DMA_DESC_Y 0x200
	371	#define REG_DMA_DESC_U 0x204
	372	#define REG_DMA_DESC_V 0x208
	373	#define REG_DESC_LEN_Y 0x20c /* Lengths are in bytes */
	374	#define REG_DESC_LEN_U 0x210
	375	#define REG_DESC_LEN_V 0x214
	376
abfa3df3 JC	377	/*
	378	* Useful stuff that probably belongs somewhere global.
	379	*/
	380	#define VGA_WIDTH 640
	381	#define VGA_HEIGHT 480
b5210fd2 JC	382
b5210fd2 JC	383	#endif /* _MCAM_CORE_H */