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448de7e7
SA		 1/*
2 * isp.c
3 *
4 * TI OMAP3 ISP - Core
5 *
6 * Copyright (C) 2006-2010 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments, Inc.
8 *
9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 * Sakari Ailus <sakari.ailus@iki.fi>
11 *
12 * Contributors:
13 * Laurent Pinchart <laurent.pinchart@ideasonboard.com>
14 * Sakari Ailus <sakari.ailus@iki.fi>
15 * David Cohen <dacohen@gmail.com>
16 * Stanimir Varbanov <svarbanov@mm-sol.com>
17 * Vimarsh Zutshi <vimarsh.zutshi@gmail.com>
18 * Tuukka Toivonen <tuukkat76@gmail.com>
19 * Sergio Aguirre <saaguirre@ti.com>
20 * Antti Koskipaa <akoskipa@gmail.com>
21 * Ivan T. Ivanov <iivanov@mm-sol.com>
22 * RaniSuneela <r-m@ti.com>
23 * Atanas Filipov <afilipov@mm-sol.com>
24 * Gjorgji Rosikopulos <grosikopulos@mm-sol.com>
25 * Hiroshi DOYU <hiroshi.doyu@nokia.com>
26 * Nayden Kanchev <nkanchev@mm-sol.com>
27 * Phil Carmody <ext-phil.2.carmody@nokia.com>
28 * Artem Bityutskiy <artem.bityutskiy@nokia.com>
29 * Dominic Curran <dcurran@ti.com>
30 * Ilkka Myllyperkio <ilkka.myllyperkio@sofica.fi>
31 * Pallavi Kulkarni <p-kulkarni@ti.com>
32 * Vaibhav Hiremath <hvaibhav@ti.com>
33 * Mohit Jalori <mjalori@ti.com>
34 * Sameer Venkatraman <sameerv@ti.com>
35 * Senthilvadivu Guruswamy <svadivu@ti.com>
36 * Thara Gopinath <thara@ti.com>
37 * Toni Leinonen <toni.leinonen@nokia.com>
38 * Troy Laramy <t-laramy@ti.com>
39 *
40 * This program is free software; you can redistribute it and/or modify
41 * it under the terms of the GNU General Public License version 2 as
42 * published by the Free Software Foundation.
43 *
44 * This program is distributed in the hope that it will be useful, but
45 * WITHOUT ANY WARRANTY; without even the implied warranty of
46 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
47 * General Public License for more details.
48 *
49 * You should have received a copy of the GNU General Public License
50 * along with this program; if not, write to the Free Software
51 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
52 * 02110-1301 USA
53 */
54
55#include <asm/cacheflush.h>
56
57#include <linux/clk.h>
58#include <linux/delay.h>
59#include <linux/device.h>
60#include <linux/dma-mapping.h>
61#include <linux/i2c.h>
62#include <linux/interrupt.h>
63#include <linux/module.h>
c8d35c84 64#include <linux/omap-iommu.h>
448de7e7
SA		 65#include <linux/platform_device.h>
66#include <linux/regulator/consumer.h>
67#include <linux/slab.h>
68#include <linux/sched.h>
69#include <linux/vmalloc.h>
70
71#include <media/v4l2-common.h>
72#include <media/v4l2-device.h>
73
74#include "isp.h"
75#include "ispreg.h"
76#include "ispccdc.h"
77#include "isppreview.h"
78#include "ispresizer.h"
79#include "ispcsi2.h"
80#include "ispccp2.h"
81#include "isph3a.h"
82#include "isphist.h"
83
84static unsigned int autoidle;
85module_param(autoidle, int, 0444);
86MODULE_PARM_DESC(autoidle, "Enable OMAP3ISP AUTOIDLE support");
87
88static void isp_save_ctx(struct isp_device *isp);
89
90static void isp_restore_ctx(struct isp_device *isp);
91
92static const struct isp_res_mapping isp_res_maps[] = {
93 {
94 .isp_rev = ISP_REVISION_2_0,
95 .map = 1 << OMAP3_ISP_IOMEM_MAIN |
96 1 << OMAP3_ISP_IOMEM_CCP2 |
97 1 << OMAP3_ISP_IOMEM_CCDC |
98 1 << OMAP3_ISP_IOMEM_HIST |
99 1 << OMAP3_ISP_IOMEM_H3A |
100 1 << OMAP3_ISP_IOMEM_PREV |
101 1 << OMAP3_ISP_IOMEM_RESZ |
102 1 << OMAP3_ISP_IOMEM_SBL |
103 1 << OMAP3_ISP_IOMEM_CSI2A_REGS1 |
c19d19eb
SA		 104 1 << OMAP3_ISP_IOMEM_CSIPHY2 |
105 1 << OMAP3_ISP_IOMEM_343X_CONTROL_CSIRXFE,
448de7e7
SA		 106 },
107 {
108 .isp_rev = ISP_REVISION_15_0,
109 .map = 1 << OMAP3_ISP_IOMEM_MAIN |
110 1 << OMAP3_ISP_IOMEM_CCP2 |
111 1 << OMAP3_ISP_IOMEM_CCDC |
112 1 << OMAP3_ISP_IOMEM_HIST |
113 1 << OMAP3_ISP_IOMEM_H3A |
114 1 << OMAP3_ISP_IOMEM_PREV |
115 1 << OMAP3_ISP_IOMEM_RESZ |
116 1 << OMAP3_ISP_IOMEM_SBL |
117 1 << OMAP3_ISP_IOMEM_CSI2A_REGS1 |
118 1 << OMAP3_ISP_IOMEM_CSIPHY2 |
119 1 << OMAP3_ISP_IOMEM_CSI2A_REGS2 |
120 1 << OMAP3_ISP_IOMEM_CSI2C_REGS1 |
121 1 << OMAP3_ISP_IOMEM_CSIPHY1 |
c19d19eb
SA		 122 1 << OMAP3_ISP_IOMEM_CSI2C_REGS2 |
123 1 << OMAP3_ISP_IOMEM_3630_CONTROL_CAMERA_PHY_CTRL,
448de7e7
SA		 124 },
125};
126
127/* Structure for saving/restoring ISP module registers */
128static struct isp_reg isp_reg_list[] = {
129 {OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG, 0},
130 {OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, 0},
131 {OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL, 0},
132 {0, ISP_TOK_TERM, 0}
133};
134
135/*
136 * omap3isp_flush - Post pending L3 bus writes by doing a register readback
137 * @isp: OMAP3 ISP device
138 *
139 * In order to force posting of pending writes, we need to write and
140 * readback the same register, in this case the revision register.
141 *
142 * See this link for reference:
143 * http://www.mail-archive.com/linux-omap@vger.kernel.org/msg08149.html
144 */
145void omap3isp_flush(struct isp_device *isp)
146{
147 isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION);
148 isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION);
149}
150
151/*
152 * isp_enable_interrupts - Enable ISP interrupts.
153 * @isp: OMAP3 ISP device
154 */
155static void isp_enable_interrupts(struct isp_device *isp)
156{
157 static const u32 irq = IRQ0ENABLE_CSIA_IRQ
158 | IRQ0ENABLE_CSIB_IRQ
159 | IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ
160 | IRQ0ENABLE_CCDC_LSC_DONE_IRQ
161 | IRQ0ENABLE_CCDC_VD0_IRQ
162 | IRQ0ENABLE_CCDC_VD1_IRQ
163 | IRQ0ENABLE_HS_VS_IRQ
164 | IRQ0ENABLE_HIST_DONE_IRQ
165 | IRQ0ENABLE_H3A_AWB_DONE_IRQ
166 | IRQ0ENABLE_H3A_AF_DONE_IRQ
167 | IRQ0ENABLE_PRV_DONE_IRQ
168 | IRQ0ENABLE_RSZ_DONE_IRQ;
169
170 isp_reg_writel(isp, irq, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
171 isp_reg_writel(isp, irq, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE);
172}
173
174/*
175 * isp_disable_interrupts - Disable ISP interrupts.
176 * @isp: OMAP3 ISP device
177 */
178static void isp_disable_interrupts(struct isp_device *isp)
179{
180 isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE);
181}
182
183/**
184 * isp_set_xclk - Configures the specified cam_xclk to the desired frequency.
185 * @isp: OMAP3 ISP device
186 * @xclk: Desired frequency of the clock in Hz. 0 = stable low, 1 is stable high
187 * @xclksel: XCLK to configure (0 = A, 1 = B).
188 *
189 * Configures the specified MCLK divisor in the ISP timing control register
190 * (TCTRL_CTRL) to generate the desired xclk clock value.
191 *
192 * Divisor = cam_mclk_hz / xclk
193 *
194 * Returns the final frequency that is actually being generated
195 **/
196static u32 isp_set_xclk(struct isp_device *isp, u32 xclk, u8 xclksel)
197{
198 u32 divisor;
199 u32 currentxclk;
200 unsigned long mclk_hz;
201
202 if (!omap3isp_get(isp))
203 return 0;
204
205 mclk_hz = clk_get_rate(isp->clock[ISP_CLK_CAM_MCLK]);
206
207 if (xclk >= mclk_hz) {
208 divisor = ISPTCTRL_CTRL_DIV_BYPASS;
209 currentxclk = mclk_hz;
210 } else if (xclk >= 2) {
211 divisor = mclk_hz / xclk;
212 if (divisor >= ISPTCTRL_CTRL_DIV_BYPASS)
213 divisor = ISPTCTRL_CTRL_DIV_BYPASS - 1;
214 currentxclk = mclk_hz / divisor;
215 } else {
216 divisor = xclk;
217 currentxclk = 0;
218 }
219
220 switch (xclksel) {
7c2c8f42 221 case ISP_XCLK_A:
448de7e7
SA		 222 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL,
223 ISPTCTRL_CTRL_DIVA_MASK,
224 divisor << ISPTCTRL_CTRL_DIVA_SHIFT);
225 dev_dbg(isp->dev, "isp_set_xclk(): cam_xclka set to %d Hz\n",
226 currentxclk);
227 break;
7c2c8f42 228 case ISP_XCLK_B:
448de7e7
SA		 229 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL,
230 ISPTCTRL_CTRL_DIVB_MASK,
231 divisor << ISPTCTRL_CTRL_DIVB_SHIFT);
232 dev_dbg(isp->dev, "isp_set_xclk(): cam_xclkb set to %d Hz\n",
233 currentxclk);
234 break;
7c2c8f42 235 case ISP_XCLK_NONE:
448de7e7
SA		 236 default:
237 omap3isp_put(isp);
238 dev_dbg(isp->dev, "ISP_ERR: isp_set_xclk(): Invalid requested "
239 "xclk. Must be 0 (A) or 1 (B).\n");
240 return -EINVAL;
241 }
242
243 /* Do we go from stable whatever to clock? */
7c2c8f42 244 if (divisor >= 2 && isp->xclk_divisor[xclksel - 1] < 2)
448de7e7
SA		 245 omap3isp_get(isp);
246 /* Stopping the clock. */
7c2c8f42 247 else if (divisor < 2 && isp->xclk_divisor[xclksel - 1] >= 2)
448de7e7
SA		 248 omap3isp_put(isp);
249
7c2c8f42 250 isp->xclk_divisor[xclksel - 1] = divisor;
448de7e7
SA		 251
252 omap3isp_put(isp);
253
254 return currentxclk;
255}
256
257/*
96d62ae2 258 * isp_core_init - ISP core settings
448de7e7
SA		 259 * @isp: OMAP3 ISP device
260 * @idle: Consider idle state.
261 *
96d62ae2
LP		 262 * Set the power settings for the ISP and SBL bus and cConfigure the HS/VS
263 * interrupt source.
264 *
265 * We need to configure the HS/VS interrupt source before interrupts get
266 * enabled, as the sensor might be free-running and the ISP default setting
267 * (HS edge) would put an unnecessary burden on the CPU.
448de7e7 268 */
96d62ae2 269static void isp_core_init(struct isp_device *isp, int idle)
448de7e7
SA		 270{
271 isp_reg_writel(isp,
272 ((idle ? ISP_SYSCONFIG_MIDLEMODE_SMARTSTANDBY :
273 ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY) <<
274 ISP_SYSCONFIG_MIDLEMODE_SHIFT) |
275 ((isp->revision == ISP_REVISION_15_0) ?
276 ISP_SYSCONFIG_AUTOIDLE : 0),
277 OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG);
278
96d62ae2
LP		 279 isp_reg_writel(isp,
280 (isp->autoidle ? ISPCTRL_SBL_AUTOIDLE : 0) |
281 ISPCTRL_SYNC_DETECT_VSRISE,
282 OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
448de7e7
SA		 283}
284
285/*
286 * Configure the bridge and lane shifter. Valid inputs are
287 *
288 * CCDC_INPUT_PARALLEL: Parallel interface
289 * CCDC_INPUT_CSI2A: CSI2a receiver
290 * CCDC_INPUT_CCP2B: CCP2b receiver
291 * CCDC_INPUT_CSI2C: CSI2c receiver
292 *
293 * The bridge and lane shifter are configured according to the selected input
294 * and the ISP platform data.
295 */
296void omap3isp_configure_bridge(struct isp_device *isp,
297 enum ccdc_input_entity input,
c09af044 298 const struct isp_parallel_platform_data *pdata,
c51364ca 299 unsigned int shift, unsigned int bridge)
448de7e7
SA		 300{
301 u32 ispctrl_val;
302
303 ispctrl_val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
304 ispctrl_val &= ~ISPCTRL_SHIFT_MASK;
305 ispctrl_val &= ~ISPCTRL_PAR_CLK_POL_INV;
306 ispctrl_val &= ~ISPCTRL_PAR_SER_CLK_SEL_MASK;
307 ispctrl_val &= ~ISPCTRL_PAR_BRIDGE_MASK;
c51364ca 308 ispctrl_val |= bridge;
448de7e7
SA		 309
310 switch (input) {
311 case CCDC_INPUT_PARALLEL:
312 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_PARALLEL;
448de7e7 313 ispctrl_val |= pdata->clk_pol << ISPCTRL_PAR_CLK_POL_SHIFT;
c09af044 314 shift += pdata->data_lane_shift * 2;
448de7e7
SA		 315 break;
316
317 case CCDC_INPUT_CSI2A:
318 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIA;
319 break;
320
321 case CCDC_INPUT_CCP2B:
322 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIB;
323 break;
324
325 case CCDC_INPUT_CSI2C:
326 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIC;
327 break;
328
329 default:
330 return;
331 }
332
c09af044
MJ		 333 ispctrl_val |= ((shift/2) << ISPCTRL_SHIFT_SHIFT) & ISPCTRL_SHIFT_MASK;
334
448de7e7
SA		 335 isp_reg_writel(isp, ispctrl_val, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
336}
337
448de7e7
SA		 338void omap3isp_hist_dma_done(struct isp_device *isp)
339{
340 if (omap3isp_ccdc_busy(&isp->isp_ccdc) ||
341 omap3isp_stat_pcr_busy(&isp->isp_hist)) {
342 /* Histogram cannot be enabled in this frame anymore */
343 atomic_set(&isp->isp_hist.buf_err, 1);
344 dev_dbg(isp->dev, "hist: Out of synchronization with "
345 "CCDC. Ignoring next buffer.\n");
346 }
347}
348
349static inline void isp_isr_dbg(struct isp_device *isp, u32 irqstatus)
350{
351 static const char *name[] = {
352 "CSIA_IRQ",
353 "res1",
354 "res2",
355 "CSIB_LCM_IRQ",
356 "CSIB_IRQ",
357 "res5",
358 "res6",
359 "res7",
360 "CCDC_VD0_IRQ",
361 "CCDC_VD1_IRQ",
362 "CCDC_VD2_IRQ",
363 "CCDC_ERR_IRQ",
364 "H3A_AF_DONE_IRQ",
365 "H3A_AWB_DONE_IRQ",
366 "res14",
367 "res15",
368 "HIST_DONE_IRQ",
369 "CCDC_LSC_DONE",
370 "CCDC_LSC_PREFETCH_COMPLETED",
371 "CCDC_LSC_PREFETCH_ERROR",
372 "PRV_DONE_IRQ",
373 "CBUFF_IRQ",
374 "res22",
375 "res23",
376 "RSZ_DONE_IRQ",
377 "OVF_IRQ",
378 "res26",
379 "res27",
380 "MMU_ERR_IRQ",
381 "OCP_ERR_IRQ",
382 "SEC_ERR_IRQ",
383 "HS_VS_IRQ",
384 };
385 int i;
386
6c20c635 387 dev_dbg(isp->dev, "ISP IRQ: ");
448de7e7
SA		 388
389 for (i = 0; i < ARRAY_SIZE(name); i++) {
390 if ((1 << i) & irqstatus)
391 printk(KERN_CONT "%s ", name[i]);
392 }
393 printk(KERN_CONT "\n");
394}
395
396static void isp_isr_sbl(struct isp_device *isp)
397{
398 struct device *dev = isp->dev;
875e2e3e 399 struct isp_pipeline *pipe;
448de7e7
SA		 400 u32 sbl_pcr;
401
402 /*
403 * Handle shared buffer logic overflows for video buffers.
404 * ISPSBL_PCR_CCDCPRV_2_RSZ_OVF can be safely ignored.
405 */
406 sbl_pcr = isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_PCR);
407 isp_reg_writel(isp, sbl_pcr, OMAP3_ISP_IOMEM_SBL, ISPSBL_PCR);
408 sbl_pcr &= ~ISPSBL_PCR_CCDCPRV_2_RSZ_OVF;
409
410 if (sbl_pcr)
411 dev_dbg(dev, "SBL overflow (PCR = 0x%08x)\n", sbl_pcr);
412
875e2e3e
LP		 413 if (sbl_pcr & ISPSBL_PCR_CSIB_WBL_OVF) {
414 pipe = to_isp_pipeline(&isp->isp_ccp2.subdev.entity);
415 if (pipe != NULL)
416 pipe->error = true;
417 }
418
419 if (sbl_pcr & ISPSBL_PCR_CSIA_WBL_OVF) {
420 pipe = to_isp_pipeline(&isp->isp_csi2a.subdev.entity);
421 if (pipe != NULL)
422 pipe->error = true;
423 }
424
425 if (sbl_pcr & ISPSBL_PCR_CCDC_WBL_OVF) {
426 pipe = to_isp_pipeline(&isp->isp_ccdc.subdev.entity);
427 if (pipe != NULL)
428 pipe->error = true;
448de7e7
SA		 429 }
430
431 if (sbl_pcr & ISPSBL_PCR_PRV_WBL_OVF) {
875e2e3e
LP		 432 pipe = to_isp_pipeline(&isp->isp_prev.subdev.entity);
433 if (pipe != NULL)
434 pipe->error = true;
448de7e7
SA		 435 }
436
437 if (sbl_pcr & (ISPSBL_PCR_RSZ1_WBL_OVF
438 | ISPSBL_PCR_RSZ2_WBL_OVF
439 | ISPSBL_PCR_RSZ3_WBL_OVF
875e2e3e
LP		 440 | ISPSBL_PCR_RSZ4_WBL_OVF)) {
441 pipe = to_isp_pipeline(&isp->isp_res.subdev.entity);
442 if (pipe != NULL)
443 pipe->error = true;
444 }
448de7e7
SA		 445
446 if (sbl_pcr & ISPSBL_PCR_H3A_AF_WBL_OVF)
447 omap3isp_stat_sbl_overflow(&isp->isp_af);
448
449 if (sbl_pcr & ISPSBL_PCR_H3A_AEAWB_WBL_OVF)
450 omap3isp_stat_sbl_overflow(&isp->isp_aewb);
451}
452
453/*
454 * isp_isr - Interrupt Service Routine for Camera ISP module.
455 * @irq: Not used currently.
456 * @_isp: Pointer to the OMAP3 ISP device
457 *
458 * Handles the corresponding callback if plugged in.
459 *
460 * Returns IRQ_HANDLED when IRQ was correctly handled, or IRQ_NONE when the
461 * IRQ wasn't handled.
462 */
463static irqreturn_t isp_isr(int irq, void *_isp)
464{
465 static const u32 ccdc_events = IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ |
466 IRQ0STATUS_CCDC_LSC_DONE_IRQ |
467 IRQ0STATUS_CCDC_VD0_IRQ |
468 IRQ0STATUS_CCDC_VD1_IRQ |
469 IRQ0STATUS_HS_VS_IRQ;
470 struct isp_device *isp = _isp;
471 u32 irqstatus;
448de7e7
SA		 472
473 irqstatus = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
474 isp_reg_writel(isp, irqstatus, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
475
476 isp_isr_sbl(isp);
477
875e2e3e
LP		 478 if (irqstatus & IRQ0STATUS_CSIA_IRQ)
479 omap3isp_csi2_isr(&isp->isp_csi2a);
448de7e7 480
875e2e3e
LP		 481 if (irqstatus & IRQ0STATUS_CSIB_IRQ)
482 omap3isp_ccp2_isr(&isp->isp_ccp2);
448de7e7
SA		 483
484 if (irqstatus & IRQ0STATUS_CCDC_VD0_IRQ) {
485 if (isp->isp_ccdc.output & CCDC_OUTPUT_PREVIEW)
486 omap3isp_preview_isr_frame_sync(&isp->isp_prev);
487 if (isp->isp_ccdc.output & CCDC_OUTPUT_RESIZER)
488 omap3isp_resizer_isr_frame_sync(&isp->isp_res);
489 omap3isp_stat_isr_frame_sync(&isp->isp_aewb);
490 omap3isp_stat_isr_frame_sync(&isp->isp_af);
491 omap3isp_stat_isr_frame_sync(&isp->isp_hist);
492 }
493
494 if (irqstatus & ccdc_events)
495 omap3isp_ccdc_isr(&isp->isp_ccdc, irqstatus & ccdc_events);
496
497 if (irqstatus & IRQ0STATUS_PRV_DONE_IRQ) {
498 if (isp->isp_prev.output & PREVIEW_OUTPUT_RESIZER)
499 omap3isp_resizer_isr_frame_sync(&isp->isp_res);
500 omap3isp_preview_isr(&isp->isp_prev);
501 }
502
503 if (irqstatus & IRQ0STATUS_RSZ_DONE_IRQ)
504 omap3isp_resizer_isr(&isp->isp_res);
505
506 if (irqstatus & IRQ0STATUS_H3A_AWB_DONE_IRQ)
507 omap3isp_stat_isr(&isp->isp_aewb);
508
509 if (irqstatus & IRQ0STATUS_H3A_AF_DONE_IRQ)
510 omap3isp_stat_isr(&isp->isp_af);
511
512 if (irqstatus & IRQ0STATUS_HIST_DONE_IRQ)
513 omap3isp_stat_isr(&isp->isp_hist);
514
515 omap3isp_flush(isp);
516
517#if defined(DEBUG) && defined(ISP_ISR_DEBUG)
518 isp_isr_dbg(isp, irqstatus);
519#endif
520
521 return IRQ_HANDLED;
522}
523
524/* -----------------------------------------------------------------------------
525 * Pipeline power management
526 *
527 * Entities must be powered up when part of a pipeline that contains at least
528 * one open video device node.
529 *
530 * To achieve this use the entity use_count field to track the number of users.
531 * For entities corresponding to video device nodes the use_count field stores
532 * the users count of the node. For entities corresponding to subdevs the
533 * use_count field stores the total number of users of all video device nodes
534 * in the pipeline.
535 *
536 * The omap3isp_pipeline_pm_use() function must be called in the open() and
537 * close() handlers of video device nodes. It increments or decrements the use
538 * count of all subdev entities in the pipeline.
539 *
540 * To react to link management on powered pipelines, the link setup notification
541 * callback updates the use count of all entities in the source and sink sides
542 * of the link.
543 */
544
545/*
546 * isp_pipeline_pm_use_count - Count the number of users of a pipeline
547 * @entity: The entity
548 *
549 * Return the total number of users of all video device nodes in the pipeline.
550 */
551static int isp_pipeline_pm_use_count(struct media_entity *entity)
552{
553 struct media_entity_graph graph;
554 int use = 0;
555
556 media_entity_graph_walk_start(&graph, entity);
557
558 while ((entity = media_entity_graph_walk_next(&graph))) {
559 if (media_entity_type(entity) == MEDIA_ENT_T_DEVNODE)
560 use += entity->use_count;
561 }
562
563 return use;
564}
565
566/*
567 * isp_pipeline_pm_power_one - Apply power change to an entity
568 * @entity: The entity
569 * @change: Use count change
570 *
571 * Change the entity use count by @change. If the entity is a subdev update its
572 * power state by calling the core::s_power operation when the use count goes
573 * from 0 to != 0 or from != 0 to 0.
574 *
575 * Return 0 on success or a negative error code on failure.
576 */
577static int isp_pipeline_pm_power_one(struct media_entity *entity, int change)
578{
579 struct v4l2_subdev *subdev;
580 int ret;
581
582 subdev = media_entity_type(entity) == MEDIA_ENT_T_V4L2_SUBDEV
583 ? media_entity_to_v4l2_subdev(entity) : NULL;
584
585 if (entity->use_count == 0 && change > 0 && subdev != NULL) {
586 ret = v4l2_subdev_call(subdev, core, s_power, 1);
587 if (ret < 0 && ret != -ENOIOCTLCMD)
588 return ret;
589 }
590
591 entity->use_count += change;
592 WARN_ON(entity->use_count < 0);
593
594 if (entity->use_count == 0 && change < 0 && subdev != NULL)
595 v4l2_subdev_call(subdev, core, s_power, 0);
596
597 return 0;
598}
599
600/*
601 * isp_pipeline_pm_power - Apply power change to all entities in a pipeline
602 * @entity: The entity
603 * @change: Use count change
604 *
605 * Walk the pipeline to update the use count and the power state of all non-node
606 * entities.
607 *
608 * Return 0 on success or a negative error code on failure.
609 */
610static int isp_pipeline_pm_power(struct media_entity *entity, int change)
611{
612 struct media_entity_graph graph;
613 struct media_entity *first = entity;
614 int ret = 0;
615
616 if (!change)
617 return 0;
618
619 media_entity_graph_walk_start(&graph, entity);
620
621 while (!ret && (entity = media_entity_graph_walk_next(&graph)))
622 if (media_entity_type(entity) != MEDIA_ENT_T_DEVNODE)
623 ret = isp_pipeline_pm_power_one(entity, change);
624
625 if (!ret)
626 return 0;
627
628 media_entity_graph_walk_start(&graph, first);
629
630 while ((first = media_entity_graph_walk_next(&graph))
631 && first != entity)
632 if (media_entity_type(first) != MEDIA_ENT_T_DEVNODE)
633 isp_pipeline_pm_power_one(first, -change);
634
635 return ret;
636}
637
638/*
639 * omap3isp_pipeline_pm_use - Update the use count of an entity
640 * @entity: The entity
641 * @use: Use (1) or stop using (0) the entity
642 *
643 * Update the use count of all entities in the pipeline and power entities on or
644 * off accordingly.
645 *
646 * Return 0 on success or a negative error code on failure. Powering entities
647 * off is assumed to never fail. No failure can occur when the use parameter is
648 * set to 0.
649 */
650int omap3isp_pipeline_pm_use(struct media_entity *entity, int use)
651{
652 int change = use ? 1 : -1;
653 int ret;
654
655 mutex_lock(&entity->parent->graph_mutex);
656
657 /* Apply use count to node. */
658 entity->use_count += change;
659 WARN_ON(entity->use_count < 0);
660
661 /* Apply power change to connected non-nodes. */
662 ret = isp_pipeline_pm_power(entity, change);
e2241531
LP		 663 if (ret < 0)
664 entity->use_count -= change;
448de7e7
SA		 665
666 mutex_unlock(&entity->parent->graph_mutex);
667
668 return ret;
669}
670
671/*
672 * isp_pipeline_link_notify - Link management notification callback
673 * @source: Pad at the start of the link
674 * @sink: Pad at the end of the link
675 * @flags: New link flags that will be applied
676 *
677 * React to link management on powered pipelines by updating the use count of
678 * all entities in the source and sink sides of the link. Entities are powered
679 * on or off accordingly.
680 *
681 * Return 0 on success or a negative error code on failure. Powering entities
682 * off is assumed to never fail. This function will not fail for disconnection
683 * events.
684 */
685static int isp_pipeline_link_notify(struct media_pad *source,
686 struct media_pad *sink, u32 flags)
687{
688 int source_use = isp_pipeline_pm_use_count(source->entity);
689 int sink_use = isp_pipeline_pm_use_count(sink->entity);
690 int ret;
691
692 if (!(flags & MEDIA_LNK_FL_ENABLED)) {
693 /* Powering off entities is assumed to never fail. */
694 isp_pipeline_pm_power(source->entity, -sink_use);
695 isp_pipeline_pm_power(sink->entity, -source_use);
696 return 0;
697 }
698
699 ret = isp_pipeline_pm_power(source->entity, sink_use);
700 if (ret < 0)
701 return ret;
702
703 ret = isp_pipeline_pm_power(sink->entity, source_use);
704 if (ret < 0)
705 isp_pipeline_pm_power(source->entity, -sink_use);
706
707 return ret;
708}
709
710/* -----------------------------------------------------------------------------
711 * Pipeline stream management
712 */
713
714/*
715 * isp_pipeline_enable - Enable streaming on a pipeline
716 * @pipe: ISP pipeline
717 * @mode: Stream mode (single shot or continuous)
718 *
719 * Walk the entities chain starting at the pipeline output video node and start
720 * all modules in the chain in the given mode.
721 *
25985edc 722 * Return 0 if successful, or the return value of the failed video::s_stream
448de7e7
SA		 723 * operation otherwise.
724 */
725static int isp_pipeline_enable(struct isp_pipeline *pipe,
726 enum isp_pipeline_stream_state mode)
727{
728 struct isp_device *isp = pipe->output->isp;
729 struct media_entity *entity;
730 struct media_pad *pad;
731 struct v4l2_subdev *subdev;
732 unsigned long flags;
c62e2a19 733 int ret;
448de7e7 734
1567bb7d
LP		 735 /* If the preview engine crashed it might not respond to read/write
736 * operations on the L4 bus. This would result in a bus fault and a
737 * kernel oops. Refuse to start streaming in that case. This check must
738 * be performed before the loop below to avoid starting entities if the
739 * pipeline won't start anyway (those entities would then likely fail to
740 * stop, making the problem worse).
741 */
742 if ((pipe->entities & isp->crashed) &
743 (1U << isp->isp_prev.subdev.entity.id))
744 return -EIO;
745
448de7e7
SA		 746 spin_lock_irqsave(&pipe->lock, flags);
747 pipe->state &= ~(ISP_PIPELINE_IDLE_INPUT | ISP_PIPELINE_IDLE_OUTPUT);
748 spin_unlock_irqrestore(&pipe->lock, flags);
749
750 pipe->do_propagation = false;
751
752 entity = &pipe->output->video.entity;
753 while (1) {
754 pad = &entity->pads[0];
755 if (!(pad->flags & MEDIA_PAD_FL_SINK))
756 break;
757
758 pad = media_entity_remote_source(pad);
759 if (pad == NULL ||
760 media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
761 break;
762
763 entity = pad->entity;
764 subdev = media_entity_to_v4l2_subdev(entity);
765
766 ret = v4l2_subdev_call(subdev, video, s_stream, mode);
767 if (ret < 0 && ret != -ENOIOCTLCMD)
c62e2a19 768 return ret;
448de7e7
SA		 769
770 if (subdev == &isp->isp_ccdc.subdev) {
771 v4l2_subdev_call(&isp->isp_aewb.subdev, video,
772 s_stream, mode);
773 v4l2_subdev_call(&isp->isp_af.subdev, video,
774 s_stream, mode);
775 v4l2_subdev_call(&isp->isp_hist.subdev, video,
776 s_stream, mode);
777 pipe->do_propagation = true;
778 }
779 }
780
c62e2a19 781 return 0;
448de7e7
SA		 782}
783
784static int isp_pipeline_wait_resizer(struct isp_device *isp)
785{
786 return omap3isp_resizer_busy(&isp->isp_res);
787}
788
789static int isp_pipeline_wait_preview(struct isp_device *isp)
790{
791 return omap3isp_preview_busy(&isp->isp_prev);
792}
793
794static int isp_pipeline_wait_ccdc(struct isp_device *isp)
795{
796 return omap3isp_stat_busy(&isp->isp_af)
797 || omap3isp_stat_busy(&isp->isp_aewb)
798 || omap3isp_stat_busy(&isp->isp_hist)
799 || omap3isp_ccdc_busy(&isp->isp_ccdc);
800}
801
802#define ISP_STOP_TIMEOUT msecs_to_jiffies(1000)
803
804static int isp_pipeline_wait(struct isp_device *isp,
805 int(*busy)(struct isp_device *isp))
806{
807 unsigned long timeout = jiffies + ISP_STOP_TIMEOUT;
808
809 while (!time_after(jiffies, timeout)) {
810 if (!busy(isp))
811 return 0;
812 }
813
814 return 1;
815}
816
817/*
818 * isp_pipeline_disable - Disable streaming on a pipeline
819 * @pipe: ISP pipeline
820 *
821 * Walk the entities chain starting at the pipeline output video node and stop
822 * all modules in the chain. Wait synchronously for the modules to be stopped if
823 * necessary.
824 *
825 * Return 0 if all modules have been properly stopped, or -ETIMEDOUT if a module
826 * can't be stopped (in which case a software reset of the ISP is probably
827 * necessary).
828 */
829static int isp_pipeline_disable(struct isp_pipeline *pipe)
830{
831 struct isp_device *isp = pipe->output->isp;
832 struct media_entity *entity;
833 struct media_pad *pad;
834 struct v4l2_subdev *subdev;
835 int failure = 0;
836 int ret;
837
838 /*
839 * We need to stop all the modules after CCDC first or they'll
840 * never stop since they may not get a full frame from CCDC.
841 */
842 entity = &pipe->output->video.entity;
843 while (1) {
844 pad = &entity->pads[0];
845 if (!(pad->flags & MEDIA_PAD_FL_SINK))
846 break;
847
848 pad = media_entity_remote_source(pad);
849 if (pad == NULL ||
850 media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
851 break;
852
853 entity = pad->entity;
854 subdev = media_entity_to_v4l2_subdev(entity);
855
856 if (subdev == &isp->isp_ccdc.subdev) {
857 v4l2_subdev_call(&isp->isp_aewb.subdev,
858 video, s_stream, 0);
859 v4l2_subdev_call(&isp->isp_af.subdev,
860 video, s_stream, 0);
861 v4l2_subdev_call(&isp->isp_hist.subdev,
862 video, s_stream, 0);
863 }
864
865 v4l2_subdev_call(subdev, video, s_stream, 0);
866
867 if (subdev == &isp->isp_res.subdev)
868 ret = isp_pipeline_wait(isp, isp_pipeline_wait_resizer);
869 else if (subdev == &isp->isp_prev.subdev)
870 ret = isp_pipeline_wait(isp, isp_pipeline_wait_preview);
871 else if (subdev == &isp->isp_ccdc.subdev)
872 ret = isp_pipeline_wait(isp, isp_pipeline_wait_ccdc);
873 else
874 ret = 0;
875
876 if (ret) {
877 dev_info(isp->dev, "Unable to stop %s\n", subdev->name);
1567bb7d
LP		 878 /* If the entity failed to stopped, assume it has
879 * crashed. Mark it as such, the ISP will be reset when
880 * applications will release it.
881 */
882 isp->crashed |= 1U << subdev->entity.id;
448de7e7
SA		 883 failure = -ETIMEDOUT;
884 }
885 }
886
887 return failure;
888}
889
890/*
891 * omap3isp_pipeline_set_stream - Enable/disable streaming on a pipeline
892 * @pipe: ISP pipeline
893 * @state: Stream state (stopped, single shot or continuous)
894 *
895 * Set the pipeline to the given stream state. Pipelines can be started in
896 * single-shot or continuous mode.
897 *
25985edc 898 * Return 0 if successful, or the return value of the failed video::s_stream
994d5375
LP		 899 * operation otherwise. The pipeline state is not updated when the operation
900 * fails, except when stopping the pipeline.
448de7e7
SA		 901 */
902int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe,
903 enum isp_pipeline_stream_state state)
904{
905 int ret;
906
907 if (state == ISP_PIPELINE_STREAM_STOPPED)
908 ret = isp_pipeline_disable(pipe);
909 else
910 ret = isp_pipeline_enable(pipe, state);
994d5375
LP		 911
912 if (ret == 0 || state == ISP_PIPELINE_STREAM_STOPPED)
913 pipe->stream_state = state;
448de7e7
SA		 914
915 return ret;
916}
917
918/*
919 * isp_pipeline_resume - Resume streaming on a pipeline
920 * @pipe: ISP pipeline
921 *
922 * Resume video output and input and re-enable pipeline.
923 */
924static void isp_pipeline_resume(struct isp_pipeline *pipe)
925{
926 int singleshot = pipe->stream_state == ISP_PIPELINE_STREAM_SINGLESHOT;
927
928 omap3isp_video_resume(pipe->output, !singleshot);
929 if (singleshot)
930 omap3isp_video_resume(pipe->input, 0);
931 isp_pipeline_enable(pipe, pipe->stream_state);
932}
933
934/*
935 * isp_pipeline_suspend - Suspend streaming on a pipeline
936 * @pipe: ISP pipeline
937 *
938 * Suspend pipeline.
939 */
940static void isp_pipeline_suspend(struct isp_pipeline *pipe)
941{
942 isp_pipeline_disable(pipe);
943}
944
945/*
946 * isp_pipeline_is_last - Verify if entity has an enabled link to the output
947 * video node
948 * @me: ISP module's media entity
949 *
950 * Returns 1 if the entity has an enabled link to the output video node or 0
951 * otherwise. It's true only while pipeline can have no more than one output
952 * node.
953 */
954static int isp_pipeline_is_last(struct media_entity *me)
955{
956 struct isp_pipeline *pipe;
957 struct media_pad *pad;
958
959 if (!me->pipe)
960 return 0;
961 pipe = to_isp_pipeline(me);
962 if (pipe->stream_state == ISP_PIPELINE_STREAM_STOPPED)
963 return 0;
964 pad = media_entity_remote_source(&pipe->output->pad);
965 return pad->entity == me;
966}
967
968/*
969 * isp_suspend_module_pipeline - Suspend pipeline to which belongs the module
970 * @me: ISP module's media entity
971 *
972 * Suspend the whole pipeline if module's entity has an enabled link to the
973 * output video node. It works only while pipeline can have no more than one
974 * output node.
975 */
976static void isp_suspend_module_pipeline(struct media_entity *me)
977{
978 if (isp_pipeline_is_last(me))
979 isp_pipeline_suspend(to_isp_pipeline(me));
980}
981
982/*
983 * isp_resume_module_pipeline - Resume pipeline to which belongs the module
984 * @me: ISP module's media entity
985 *
986 * Resume the whole pipeline if module's entity has an enabled link to the
987 * output video node. It works only while pipeline can have no more than one
988 * output node.
989 */
990static void isp_resume_module_pipeline(struct media_entity *me)
991{
992 if (isp_pipeline_is_last(me))
993 isp_pipeline_resume(to_isp_pipeline(me));
994}
995
996/*
997 * isp_suspend_modules - Suspend ISP submodules.
998 * @isp: OMAP3 ISP device
999 *
1000 * Returns 0 if suspend left in idle state all the submodules properly,
1001 * or returns 1 if a general Reset is required to suspend the submodules.
1002 */
1003static int isp_suspend_modules(struct isp_device *isp)
1004{
1005 unsigned long timeout;
1006
1007 omap3isp_stat_suspend(&isp->isp_aewb);
1008 omap3isp_stat_suspend(&isp->isp_af);
1009 omap3isp_stat_suspend(&isp->isp_hist);
1010 isp_suspend_module_pipeline(&isp->isp_res.subdev.entity);
1011 isp_suspend_module_pipeline(&isp->isp_prev.subdev.entity);
1012 isp_suspend_module_pipeline(&isp->isp_ccdc.subdev.entity);
1013 isp_suspend_module_pipeline(&isp->isp_csi2a.subdev.entity);
1014 isp_suspend_module_pipeline(&isp->isp_ccp2.subdev.entity);
1015
1016 timeout = jiffies + ISP_STOP_TIMEOUT;
1017 while (omap3isp_stat_busy(&isp->isp_af)
1018 || omap3isp_stat_busy(&isp->isp_aewb)
1019 || omap3isp_stat_busy(&isp->isp_hist)
1020 || omap3isp_preview_busy(&isp->isp_prev)
1021 || omap3isp_resizer_busy(&isp->isp_res)
1022 || omap3isp_ccdc_busy(&isp->isp_ccdc)) {
1023 if (time_after(jiffies, timeout)) {
1024 dev_info(isp->dev, "can't stop modules.\n");
1025 return 1;
1026 }
1027 msleep(1);
1028 }
1029
1030 return 0;
1031}
1032
1033/*
1034 * isp_resume_modules - Resume ISP submodules.
1035 * @isp: OMAP3 ISP device
1036 */
1037static void isp_resume_modules(struct isp_device *isp)
1038{
1039 omap3isp_stat_resume(&isp->isp_aewb);
1040 omap3isp_stat_resume(&isp->isp_af);
1041 omap3isp_stat_resume(&isp->isp_hist);
1042 isp_resume_module_pipeline(&isp->isp_res.subdev.entity);
1043 isp_resume_module_pipeline(&isp->isp_prev.subdev.entity);
1044 isp_resume_module_pipeline(&isp->isp_ccdc.subdev.entity);
1045 isp_resume_module_pipeline(&isp->isp_csi2a.subdev.entity);
1046 isp_resume_module_pipeline(&isp->isp_ccp2.subdev.entity);
1047}
1048
1049/*
1050 * isp_reset - Reset ISP with a timeout wait for idle.
1051 * @isp: OMAP3 ISP device
1052 */
1053static int isp_reset(struct isp_device *isp)
1054{
1055 unsigned long timeout = 0;
1056
1057 isp_reg_writel(isp,
1058 isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG)
1059 | ISP_SYSCONFIG_SOFTRESET,
1060 OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG);
1061 while (!(isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN,
1062 ISP_SYSSTATUS) & 0x1)) {
1063 if (timeout++ > 10000) {
1064 dev_alert(isp->dev, "cannot reset ISP\n");
1065 return -ETIMEDOUT;
1066 }
1067 udelay(1);
1068 }
1069
1567bb7d 1070 isp->crashed = 0;
448de7e7
SA		 1071 return 0;
1072}
1073
1074/*
1075 * isp_save_context - Saves the values of the ISP module registers.
1076 * @isp: OMAP3 ISP device
1077 * @reg_list: Structure containing pairs of register address and value to
1078 * modify on OMAP.
1079 */
1080static void
1081isp_save_context(struct isp_device *isp, struct isp_reg *reg_list)
1082{
1083 struct isp_reg *next = reg_list;
1084
1085 for (; next->reg != ISP_TOK_TERM; next++)
1086 next->val = isp_reg_readl(isp, next->mmio_range, next->reg);
1087}
1088
1089/*
1090 * isp_restore_context - Restores the values of the ISP module registers.
1091 * @isp: OMAP3 ISP device
1092 * @reg_list: Structure containing pairs of register address and value to
1093 * modify on OMAP.
1094 */
1095static void
1096isp_restore_context(struct isp_device *isp, struct isp_reg *reg_list)
1097{
1098 struct isp_reg *next = reg_list;
1099
1100 for (; next->reg != ISP_TOK_TERM; next++)
1101 isp_reg_writel(isp, next->val, next->mmio_range, next->reg);
1102}
1103
1104/*
1105 * isp_save_ctx - Saves ISP, CCDC, HIST, H3A, PREV, RESZ & MMU context.
1106 * @isp: OMAP3 ISP device
1107 *
1108 * Routine for saving the context of each module in the ISP.
1109 * CCDC, HIST, H3A, PREV, RESZ and MMU.
1110 */
1111static void isp_save_ctx(struct isp_device *isp)
1112{
1113 isp_save_context(isp, isp_reg_list);
fabdbca8 1114 omap_iommu_save_ctx(isp->dev);
448de7e7
SA		 1115}
1116
1117/*
1118 * isp_restore_ctx - Restores ISP, CCDC, HIST, H3A, PREV, RESZ & MMU context.
1119 * @isp: OMAP3 ISP device
1120 *
1121 * Routine for restoring the context of each module in the ISP.
1122 * CCDC, HIST, H3A, PREV, RESZ and MMU.
1123 */
1124static void isp_restore_ctx(struct isp_device *isp)
1125{
1126 isp_restore_context(isp, isp_reg_list);
fabdbca8 1127 omap_iommu_restore_ctx(isp->dev);
448de7e7
SA		 1128 omap3isp_ccdc_restore_context(isp);
1129 omap3isp_preview_restore_context(isp);
1130}
1131
1132/* -----------------------------------------------------------------------------
1133 * SBL resources management
1134 */
1135#define OMAP3_ISP_SBL_READ (OMAP3_ISP_SBL_CSI1_READ | \
1136 OMAP3_ISP_SBL_CCDC_LSC_READ | \
1137 OMAP3_ISP_SBL_PREVIEW_READ | \
1138 OMAP3_ISP_SBL_RESIZER_READ)
1139#define OMAP3_ISP_SBL_WRITE (OMAP3_ISP_SBL_CSI1_WRITE | \
1140 OMAP3_ISP_SBL_CSI2A_WRITE | \
1141 OMAP3_ISP_SBL_CSI2C_WRITE | \
1142 OMAP3_ISP_SBL_CCDC_WRITE | \
1143 OMAP3_ISP_SBL_PREVIEW_WRITE)
1144
1145void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res)
1146{
1147 u32 sbl = 0;
1148
1149 isp->sbl_resources |= res;
1150
1151 if (isp->sbl_resources & OMAP3_ISP_SBL_CSI1_READ)
1152 sbl |= ISPCTRL_SBL_SHARED_RPORTA;
1153
1154 if (isp->sbl_resources & OMAP3_ISP_SBL_CCDC_LSC_READ)
1155 sbl |= ISPCTRL_SBL_SHARED_RPORTB;
1156
1157 if (isp->sbl_resources & OMAP3_ISP_SBL_CSI2C_WRITE)
1158 sbl |= ISPCTRL_SBL_SHARED_WPORTC;
1159
1160 if (isp->sbl_resources & OMAP3_ISP_SBL_RESIZER_WRITE)
1161 sbl |= ISPCTRL_SBL_WR0_RAM_EN;
1162
1163 if (isp->sbl_resources & OMAP3_ISP_SBL_WRITE)
1164 sbl |= ISPCTRL_SBL_WR1_RAM_EN;
1165
1166 if (isp->sbl_resources & OMAP3_ISP_SBL_READ)
1167 sbl |= ISPCTRL_SBL_RD_RAM_EN;
1168
1169 isp_reg_set(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, sbl);
1170}
1171
1172void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res)
1173{
1174 u32 sbl = 0;
1175
1176 isp->sbl_resources &= ~res;
1177
1178 if (!(isp->sbl_resources & OMAP3_ISP_SBL_CSI1_READ))
1179 sbl |= ISPCTRL_SBL_SHARED_RPORTA;
1180
1181 if (!(isp->sbl_resources & OMAP3_ISP_SBL_CCDC_LSC_READ))
1182 sbl |= ISPCTRL_SBL_SHARED_RPORTB;
1183
1184 if (!(isp->sbl_resources & OMAP3_ISP_SBL_CSI2C_WRITE))
1185 sbl |= ISPCTRL_SBL_SHARED_WPORTC;
1186
1187 if (!(isp->sbl_resources & OMAP3_ISP_SBL_RESIZER_WRITE))
1188 sbl |= ISPCTRL_SBL_WR0_RAM_EN;
1189
1190 if (!(isp->sbl_resources & OMAP3_ISP_SBL_WRITE))
1191 sbl |= ISPCTRL_SBL_WR1_RAM_EN;
1192
1193 if (!(isp->sbl_resources & OMAP3_ISP_SBL_READ))
1194 sbl |= ISPCTRL_SBL_RD_RAM_EN;
1195
1196 isp_reg_clr(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, sbl);
1197}
1198
1199/*
1200 * isp_module_sync_idle - Helper to sync module with its idle state
1201 * @me: ISP submodule's media entity
1202 * @wait: ISP submodule's wait queue for streamoff/interrupt synchronization
1203 * @stopping: flag which tells module wants to stop
1204 *
1205 * This function checks if ISP submodule needs to wait for next interrupt. If
1206 * yes, makes the caller to sleep while waiting for such event.
1207 */
1208int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait,
1209 atomic_t *stopping)
1210{
1211 struct isp_pipeline *pipe = to_isp_pipeline(me);
1212
1213 if (pipe->stream_state == ISP_PIPELINE_STREAM_STOPPED ||
1214 (pipe->stream_state == ISP_PIPELINE_STREAM_SINGLESHOT &&
1215 !isp_pipeline_ready(pipe)))
1216 return 0;
1217
1218 /*
1219 * atomic_set() doesn't include memory barrier on ARM platform for SMP
1220 * scenario. We'll call it here to avoid race conditions.
1221 */
1222 atomic_set(stopping, 1);
1223 smp_mb();
1224
1225 /*
1226 * If module is the last one, it's writing to memory. In this case,
1227 * it's necessary to check if the module is already paused due to
1228 * DMA queue underrun or if it has to wait for next interrupt to be
1229 * idle.
1230 * If it isn't the last one, the function won't sleep but *stopping
1231 * will still be set to warn next submodule caller's interrupt the
1232 * module wants to be idle.
1233 */
1234 if (isp_pipeline_is_last(me)) {
1235 struct isp_video *video = pipe->output;
1236 unsigned long flags;
1237 spin_lock_irqsave(&video->queue->irqlock, flags);
1238 if (video->dmaqueue_flags & ISP_VIDEO_DMAQUEUE_UNDERRUN) {
1239 spin_unlock_irqrestore(&video->queue->irqlock, flags);
1240 atomic_set(stopping, 0);
1241 smp_mb();
1242 return 0;
1243 }
1244 spin_unlock_irqrestore(&video->queue->irqlock, flags);
1245 if (!wait_event_timeout(*wait, !atomic_read(stopping),
1246 msecs_to_jiffies(1000))) {
1247 atomic_set(stopping, 0);
1248 smp_mb();
1249 return -ETIMEDOUT;
1250 }
1251 }
1252
1253 return 0;
1254}
1255
1256/*
1257 * omap3isp_module_sync_is_stopped - Helper to verify if module was stopping
1258 * @wait: ISP submodule's wait queue for streamoff/interrupt synchronization
1259 * @stopping: flag which tells module wants to stop
1260 *
1261 * This function checks if ISP submodule was stopping. In case of yes, it
1262 * notices the caller by setting stopping to 0 and waking up the wait queue.
1263 * Returns 1 if it was stopping or 0 otherwise.
1264 */
1265int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait,
1266 atomic_t *stopping)
1267{
1268 if (atomic_cmpxchg(stopping, 1, 0)) {
1269 wake_up(wait);
1270 return 1;
1271 }
1272
1273 return 0;
1274}
1275
1276/* --------------------------------------------------------------------------
1277 * Clock management
1278 */
1279
1280#define ISPCTRL_CLKS_MASK (ISPCTRL_H3A_CLK_EN | \
1281 ISPCTRL_HIST_CLK_EN | \
1282 ISPCTRL_RSZ_CLK_EN | \
1283 (ISPCTRL_CCDC_CLK_EN | ISPCTRL_CCDC_RAM_EN) | \
1284 (ISPCTRL_PREV_CLK_EN | ISPCTRL_PREV_RAM_EN))
1285
1286static void __isp_subclk_update(struct isp_device *isp)
1287{
1288 u32 clk = 0;
1289
be9a1b98
LP		 1290 /* AEWB and AF share the same clock. */
1291 if (isp->subclk_resources &
1292 (OMAP3_ISP_SUBCLK_AEWB | OMAP3_ISP_SUBCLK_AF))
448de7e7
SA		 1293 clk |= ISPCTRL_H3A_CLK_EN;
1294
1295 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_HIST)
1296 clk |= ISPCTRL_HIST_CLK_EN;
1297
1298 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_RESIZER)
1299 clk |= ISPCTRL_RSZ_CLK_EN;
1300
1301 /* NOTE: For CCDC & Preview submodules, we need to affect internal
25985edc 1302 * RAM as well.
448de7e7
SA		 1303 */
1304 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_CCDC)
1305 clk |= ISPCTRL_CCDC_CLK_EN | ISPCTRL_CCDC_RAM_EN;
1306
1307 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_PREVIEW)
1308 clk |= ISPCTRL_PREV_CLK_EN | ISPCTRL_PREV_RAM_EN;
1309
1310 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL,
1311 ISPCTRL_CLKS_MASK, clk);
1312}
1313
1314void omap3isp_subclk_enable(struct isp_device *isp,
1315 enum isp_subclk_resource res)
1316{
1317 isp->subclk_resources |= res;
1318
1319 __isp_subclk_update(isp);
1320}
1321
1322void omap3isp_subclk_disable(struct isp_device *isp,
1323 enum isp_subclk_resource res)
1324{
1325 isp->subclk_resources &= ~res;
1326
1327 __isp_subclk_update(isp);
1328}
1329
1330/*
1331 * isp_enable_clocks - Enable ISP clocks
1332 * @isp: OMAP3 ISP device
1333 *
b057c3c3
LP		 1334 * Return 0 if successful, or clk_prepare_enable return value if any of them
1335 * fails.
448de7e7
SA		 1336 */
1337static int isp_enable_clocks(struct isp_device *isp)
1338{
1339 int r;
1340 unsigned long rate;
1341 int divisor;
1342
1343 /*
1344 * cam_mclk clock chain:
1345 * dpll4 -> dpll4_m5 -> dpll4_m5x2 -> cam_mclk
1346 *
1347 * In OMAP3630 dpll4_m5x2 != 2 x dpll4_m5 but both are
1348 * set to the same value. Hence the rate set for dpll4_m5
1349 * has to be twice of what is set on OMAP3430 to get
1350 * the required value for cam_mclk
1351 */
d8658bca 1352 divisor = isp->revision == ISP_REVISION_15_0 ? 1 : 2;
448de7e7 1353
b057c3c3 1354 r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_ICK]);
448de7e7 1355 if (r) {
b057c3c3 1356 dev_err(isp->dev, "failed to enable cam_ick clock\n");
448de7e7
SA		 1357 goto out_clk_enable_ick;
1358 }
1359 r = clk_set_rate(isp->clock[ISP_CLK_DPLL4_M5_CK],
1360 CM_CAM_MCLK_HZ/divisor);
1361 if (r) {
1362 dev_err(isp->dev, "clk_set_rate for dpll4_m5_ck failed\n");
1363 goto out_clk_enable_mclk;
1364 }
b057c3c3 1365 r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_MCLK]);
448de7e7 1366 if (r) {
b057c3c3 1367 dev_err(isp->dev, "failed to enable cam_mclk clock\n");
448de7e7
SA		 1368 goto out_clk_enable_mclk;
1369 }
1370 rate = clk_get_rate(isp->clock[ISP_CLK_CAM_MCLK]);
1371 if (rate != CM_CAM_MCLK_HZ)
1372 dev_warn(isp->dev, "unexpected cam_mclk rate:\n"
1373 " expected : %d\n"
1374 " actual : %ld\n", CM_CAM_MCLK_HZ, rate);
b057c3c3 1375 r = clk_prepare_enable(isp->clock[ISP_CLK_CSI2_FCK]);
448de7e7 1376 if (r) {
b057c3c3 1377 dev_err(isp->dev, "failed to enable csi2_fck clock\n");
448de7e7
SA		 1378 goto out_clk_enable_csi2_fclk;
1379 }
1380 return 0;
1381
1382out_clk_enable_csi2_fclk:
b057c3c3 1383 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_MCLK]);
448de7e7 1384out_clk_enable_mclk:
b057c3c3 1385 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_ICK]);
448de7e7
SA		 1386out_clk_enable_ick:
1387 return r;
1388}
1389
1390/*
1391 * isp_disable_clocks - Disable ISP clocks
1392 * @isp: OMAP3 ISP device
1393 */
1394static void isp_disable_clocks(struct isp_device *isp)
1395{
b057c3c3
LP		 1396 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_ICK]);
1397 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_MCLK]);
1398 clk_disable_unprepare(isp->clock[ISP_CLK_CSI2_FCK]);
448de7e7
SA		 1399}
1400
1401static const char *isp_clocks[] = {
1402 "cam_ick",
1403 "cam_mclk",
1404 "dpll4_m5_ck",
1405 "csi2_96m_fck",
1406 "l3_ick",
1407};
1408
1409static void isp_put_clocks(struct isp_device *isp)
1410{
1411 unsigned int i;
1412
1413 for (i = 0; i < ARRAY_SIZE(isp_clocks); ++i) {
1414 if (isp->clock[i]) {
1415 clk_put(isp->clock[i]);
1416 isp->clock[i] = NULL;
1417 }
1418 }
1419}
1420
1421static int isp_get_clocks(struct isp_device *isp)
1422{
1423 struct clk *clk;
1424 unsigned int i;
1425
1426 for (i = 0; i < ARRAY_SIZE(isp_clocks); ++i) {
1427 clk = clk_get(isp->dev, isp_clocks[i]);
1428 if (IS_ERR(clk)) {
1429 dev_err(isp->dev, "clk_get %s failed\n", isp_clocks[i]);
1430 isp_put_clocks(isp);
1431 return PTR_ERR(clk);
1432 }
1433
1434 isp->clock[i] = clk;
1435 }
1436
1437 return 0;
1438}
1439
1440/*
1441 * omap3isp_get - Acquire the ISP resource.
1442 *
1443 * Initializes the clocks for the first acquire.
1444 *
1445 * Increment the reference count on the ISP. If the first reference is taken,
1446 * enable clocks and power-up all submodules.
1447 *
25985edc 1448 * Return a pointer to the ISP device structure, or NULL if an error occurred.
448de7e7 1449 */
96d62ae2 1450static struct isp_device *__omap3isp_get(struct isp_device *isp, bool irq)
448de7e7
SA		 1451{
1452 struct isp_device *__isp = isp;
1453
1454 if (isp == NULL)
1455 return NULL;
1456
1457 mutex_lock(&isp->isp_mutex);
1458 if (isp->ref_count > 0)
1459 goto out;
1460
1461 if (isp_enable_clocks(isp) < 0) {
1462 __isp = NULL;
1463 goto out;
1464 }
1465
1466 /* We don't want to restore context before saving it! */
1467 if (isp->has_context)
1468 isp_restore_ctx(isp);
448de7e7 1469
96d62ae2
LP		 1470 if (irq)
1471 isp_enable_interrupts(isp);
448de7e7
SA		 1472
1473out:
1474 if (__isp != NULL)
1475 isp->ref_count++;
1476 mutex_unlock(&isp->isp_mutex);
1477
1478 return __isp;
1479}
1480
96d62ae2
LP		 1481struct isp_device *omap3isp_get(struct isp_device *isp)
1482{
1483 return __omap3isp_get(isp, true);
1484}
1485
448de7e7
SA		 1486/*
1487 * omap3isp_put - Release the ISP
1488 *
1489 * Decrement the reference count on the ISP. If the last reference is released,
1490 * power-down all submodules, disable clocks and free temporary buffers.
1491 */
1492void omap3isp_put(struct isp_device *isp)
1493{
1494 if (isp == NULL)
1495 return;
1496
1497 mutex_lock(&isp->isp_mutex);
1498 BUG_ON(isp->ref_count == 0);
1499 if (--isp->ref_count == 0) {
1500 isp_disable_interrupts(isp);
96d62ae2 1501 if (isp->domain) {
a32f2f90 1502 isp_save_ctx(isp);
96d62ae2
LP		 1503 isp->has_context = 1;
1504 }
1567bb7d
LP		 1505 /* Reset the ISP if an entity has failed to stop. This is the
1506 * only way to recover from such conditions.
1507 */
1508 if (isp->crashed)
994d5375 1509 isp_reset(isp);
448de7e7
SA		 1510 isp_disable_clocks(isp);
1511 }
1512 mutex_unlock(&isp->isp_mutex);
1513}
1514
1515/* --------------------------------------------------------------------------
1516 * Platform device driver
1517 */
1518
1519/*
1520 * omap3isp_print_status - Prints the values of the ISP Control Module registers
1521 * @isp: OMAP3 ISP device
1522 */
1523#define ISP_PRINT_REGISTER(isp, name)\
1524 dev_dbg(isp->dev, "###ISP " #name "=0x%08x\n", \
1525 isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_##name))
1526#define SBL_PRINT_REGISTER(isp, name)\
1527 dev_dbg(isp->dev, "###SBL " #name "=0x%08x\n", \
1528 isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_##name))
1529
1530void omap3isp_print_status(struct isp_device *isp)
1531{
1532 dev_dbg(isp->dev, "-------------ISP Register dump--------------\n");
1533
1534 ISP_PRINT_REGISTER(isp, SYSCONFIG);
1535 ISP_PRINT_REGISTER(isp, SYSSTATUS);
1536 ISP_PRINT_REGISTER(isp, IRQ0ENABLE);
1537 ISP_PRINT_REGISTER(isp, IRQ0STATUS);
1538 ISP_PRINT_REGISTER(isp, TCTRL_GRESET_LENGTH);
1539 ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_REPLAY);
1540 ISP_PRINT_REGISTER(isp, CTRL);
1541 ISP_PRINT_REGISTER(isp, TCTRL_CTRL);
1542 ISP_PRINT_REGISTER(isp, TCTRL_FRAME);
1543 ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_DELAY);
1544 ISP_PRINT_REGISTER(isp, TCTRL_STRB_DELAY);
1545 ISP_PRINT_REGISTER(isp, TCTRL_SHUT_DELAY);
1546 ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_LENGTH);
1547 ISP_PRINT_REGISTER(isp, TCTRL_STRB_LENGTH);
1548 ISP_PRINT_REGISTER(isp, TCTRL_SHUT_LENGTH);
1549
1550 SBL_PRINT_REGISTER(isp, PCR);
1551 SBL_PRINT_REGISTER(isp, SDR_REQ_EXP);
1552
1553 dev_dbg(isp->dev, "--------------------------------------------\n");
1554}
1555
1556#ifdef CONFIG_PM
1557
1558/*
1559 * Power management support.
1560 *
1561 * As the ISP can't properly handle an input video stream interruption on a non
1562 * frame boundary, the ISP pipelines need to be stopped before sensors get
1563 * suspended. However, as suspending the sensors can require a running clock,
1564 * which can be provided by the ISP, the ISP can't be completely suspended
1565 * before the sensor.
1566 *
1567 * To solve this problem power management support is split into prepare/complete
1568 * and suspend/resume operations. The pipelines are stopped in prepare() and the
1569 * ISP clocks get disabled in suspend(). Similarly, the clocks are reenabled in
1570 * resume(), and the the pipelines are restarted in complete().
1571 *
1572 * TODO: PM dependencies between the ISP and sensors are not modeled explicitly
1573 * yet.
1574 */
1575static int isp_pm_prepare(struct device *dev)
1576{
1577 struct isp_device *isp = dev_get_drvdata(dev);
1578 int reset;
1579
1580 WARN_ON(mutex_is_locked(&isp->isp_mutex));
1581
1582 if (isp->ref_count == 0)
1583 return 0;
1584
1585 reset = isp_suspend_modules(isp);
1586 isp_disable_interrupts(isp);
1587 isp_save_ctx(isp);
1588 if (reset)
1589 isp_reset(isp);
1590
1591 return 0;
1592}
1593
1594static int isp_pm_suspend(struct device *dev)
1595{
1596 struct isp_device *isp = dev_get_drvdata(dev);
1597
1598 WARN_ON(mutex_is_locked(&isp->isp_mutex));
1599
1600 if (isp->ref_count)
1601 isp_disable_clocks(isp);
1602
1603 return 0;
1604}
1605
1606static int isp_pm_resume(struct device *dev)
1607{
1608 struct isp_device *isp = dev_get_drvdata(dev);
1609
1610 if (isp->ref_count == 0)
1611 return 0;
1612
1613 return isp_enable_clocks(isp);
1614}
1615
1616static void isp_pm_complete(struct device *dev)
1617{
1618 struct isp_device *isp = dev_get_drvdata(dev);
1619
1620 if (isp->ref_count == 0)
1621 return;
1622
1623 isp_restore_ctx(isp);
1624 isp_enable_interrupts(isp);
1625 isp_resume_modules(isp);
1626}
1627
1628#else
1629
1630#define isp_pm_prepare NULL
1631#define isp_pm_suspend NULL
1632#define isp_pm_resume NULL
1633#define isp_pm_complete NULL
1634
1635#endif /* CONFIG_PM */
1636
1637static void isp_unregister_entities(struct isp_device *isp)
1638{
1639 omap3isp_csi2_unregister_entities(&isp->isp_csi2a);
1640 omap3isp_ccp2_unregister_entities(&isp->isp_ccp2);
1641 omap3isp_ccdc_unregister_entities(&isp->isp_ccdc);
1642 omap3isp_preview_unregister_entities(&isp->isp_prev);
1643 omap3isp_resizer_unregister_entities(&isp->isp_res);
1644 omap3isp_stat_unregister_entities(&isp->isp_aewb);
1645 omap3isp_stat_unregister_entities(&isp->isp_af);
1646 omap3isp_stat_unregister_entities(&isp->isp_hist);
1647
1648 v4l2_device_unregister(&isp->v4l2_dev);
1649 media_device_unregister(&isp->media_dev);
1650}
1651
1652/*
1653 * isp_register_subdev_group - Register a group of subdevices
1654 * @isp: OMAP3 ISP device
1655 * @board_info: I2C subdevs board information array
1656 *
1657 * Register all I2C subdevices in the board_info array. The array must be
1658 * terminated by a NULL entry, and the first entry must be the sensor.
1659 *
1660 * Return a pointer to the sensor media entity if it has been successfully
1661 * registered, or NULL otherwise.
1662 */
1663static struct v4l2_subdev *
1664isp_register_subdev_group(struct isp_device *isp,
1665 struct isp_subdev_i2c_board_info *board_info)
1666{
1667 struct v4l2_subdev *sensor = NULL;
1668 unsigned int first;
1669
1670 if (board_info->board_info == NULL)
1671 return NULL;
1672
1673 for (first = 1; board_info->board_info; ++board_info, first = 0) {
1674 struct v4l2_subdev *subdev;
1675 struct i2c_adapter *adapter;
1676
1677 adapter = i2c_get_adapter(board_info->i2c_adapter_id);
1678 if (adapter == NULL) {
4feca39b 1679 dev_err(isp->dev, "%s: Unable to get I2C adapter %d for "
448de7e7
SA		 1680 "device %s\n", __func__,
1681 board_info->i2c_adapter_id,
1682 board_info->board_info->type);
1683 continue;
1684 }
1685
1686 subdev = v4l2_i2c_new_subdev_board(&isp->v4l2_dev, adapter,
1687 board_info->board_info, NULL);
1688 if (subdev == NULL) {
4feca39b 1689 dev_err(isp->dev, "%s: Unable to register subdev %s\n",
448de7e7
SA		 1690 __func__, board_info->board_info->type);
1691 continue;
1692 }
1693
1694 if (first)
1695 sensor = subdev;
1696 }
1697
1698 return sensor;
1699}
1700
1701static int isp_register_entities(struct isp_device *isp)
1702{
1703 struct isp_platform_data *pdata = isp->pdata;
1704 struct isp_v4l2_subdevs_group *subdevs;
1705 int ret;
1706
1707 isp->media_dev.dev = isp->dev;
1708 strlcpy(isp->media_dev.model, "TI OMAP3 ISP",
1709 sizeof(isp->media_dev.model));
083eb078 1710 isp->media_dev.hw_revision = isp->revision;
448de7e7
SA		 1711 isp->media_dev.link_notify = isp_pipeline_link_notify;
1712 ret = media_device_register(&isp->media_dev);
1713 if (ret < 0) {
4feca39b 1714 dev_err(isp->dev, "%s: Media device registration failed (%d)\n",
448de7e7
SA		 1715 __func__, ret);
1716 return ret;
1717 }
1718
1719 isp->v4l2_dev.mdev = &isp->media_dev;
1720 ret = v4l2_device_register(isp->dev, &isp->v4l2_dev);
1721 if (ret < 0) {
4feca39b 1722 dev_err(isp->dev, "%s: V4L2 device registration failed (%d)\n",
448de7e7
SA		 1723 __func__, ret);
1724 goto done;
1725 }
1726
1727 /* Register internal entities */
1728 ret = omap3isp_ccp2_register_entities(&isp->isp_ccp2, &isp->v4l2_dev);
1729 if (ret < 0)
1730 goto done;
1731
1732 ret = omap3isp_csi2_register_entities(&isp->isp_csi2a, &isp->v4l2_dev);
1733 if (ret < 0)
1734 goto done;
1735
1736 ret = omap3isp_ccdc_register_entities(&isp->isp_ccdc, &isp->v4l2_dev);
1737 if (ret < 0)
1738 goto done;
1739
1740 ret = omap3isp_preview_register_entities(&isp->isp_prev,
1741 &isp->v4l2_dev);
1742 if (ret < 0)
1743 goto done;
1744
1745 ret = omap3isp_resizer_register_entities(&isp->isp_res, &isp->v4l2_dev);
1746 if (ret < 0)
1747 goto done;
1748
1749 ret = omap3isp_stat_register_entities(&isp->isp_aewb, &isp->v4l2_dev);
1750 if (ret < 0)
1751 goto done;
1752
1753 ret = omap3isp_stat_register_entities(&isp->isp_af, &isp->v4l2_dev);
1754 if (ret < 0)
1755 goto done;
1756
1757 ret = omap3isp_stat_register_entities(&isp->isp_hist, &isp->v4l2_dev);
1758 if (ret < 0)
1759 goto done;
1760
1761 /* Register external entities */
ca4186f0 1762 for (subdevs = pdata->subdevs; subdevs && subdevs->subdevs; ++subdevs) {
448de7e7
SA		 1763 struct v4l2_subdev *sensor;
1764 struct media_entity *input;
1765 unsigned int flags;
1766 unsigned int pad;
aab84f55 1767 unsigned int i;
448de7e7
SA		 1768
1769 sensor = isp_register_subdev_group(isp, subdevs->subdevs);
1770 if (sensor == NULL)
1771 continue;
1772
1773 sensor->host_priv = subdevs;
1774
1775 /* Connect the sensor to the correct interface module. Parallel
1776 * sensors are connected directly to the CCDC, while serial
1777 * sensors are connected to the CSI2a, CCP2b or CSI2c receiver
1778 * through CSIPHY1 or CSIPHY2.
1779 */
1780 switch (subdevs->interface) {
1781 case ISP_INTERFACE_PARALLEL:
1782 input = &isp->isp_ccdc.subdev.entity;
1783 pad = CCDC_PAD_SINK;
1784 flags = 0;
1785 break;
1786
1787 case ISP_INTERFACE_CSI2A_PHY2:
1788 input = &isp->isp_csi2a.subdev.entity;
1789 pad = CSI2_PAD_SINK;
1790 flags = MEDIA_LNK_FL_IMMUTABLE
1791 | MEDIA_LNK_FL_ENABLED;
1792 break;
1793
1794 case ISP_INTERFACE_CCP2B_PHY1:
1795 case ISP_INTERFACE_CCP2B_PHY2:
1796 input = &isp->isp_ccp2.subdev.entity;
1797 pad = CCP2_PAD_SINK;
1798 flags = 0;
1799 break;
1800
1801 case ISP_INTERFACE_CSI2C_PHY1:
1802 input = &isp->isp_csi2c.subdev.entity;
1803 pad = CSI2_PAD_SINK;
1804 flags = MEDIA_LNK_FL_IMMUTABLE
1805 | MEDIA_LNK_FL_ENABLED;
1806 break;
1807
1808 default:
4feca39b
LP		 1809 dev_err(isp->dev, "%s: invalid interface type %u\n",
1810 __func__, subdevs->interface);
448de7e7
SA		 1811 ret = -EINVAL;
1812 goto done;
1813 }
1814
aab84f55
SA		 1815 for (i = 0; i < sensor->entity.num_pads; i++) {
1816 if (sensor->entity.pads[i].flags & MEDIA_PAD_FL_SOURCE)
1817 break;
1818 }
1819 if (i == sensor->entity.num_pads) {
1820 dev_err(isp->dev,
1821 "%s: no source pad in external entity\n",
1822 __func__);
448de7e7
SA		 1823 ret = -EINVAL;
1824 goto done;
1825 }
1826
aab84f55 1827 ret = media_entity_create_link(&sensor->entity, i, input, pad,
448de7e7
SA		 1828 flags);
1829 if (ret < 0)
1830 goto done;
1831 }
1832
1833 ret = v4l2_device_register_subdev_nodes(&isp->v4l2_dev);
1834
1835done:
1836 if (ret < 0)
1837 isp_unregister_entities(isp);
1838
1839 return ret;
1840}
1841
1842static void isp_cleanup_modules(struct isp_device *isp)
1843{
1844 omap3isp_h3a_aewb_cleanup(isp);
1845 omap3isp_h3a_af_cleanup(isp);
1846 omap3isp_hist_cleanup(isp);
1847 omap3isp_resizer_cleanup(isp);
1848 omap3isp_preview_cleanup(isp);
1849 omap3isp_ccdc_cleanup(isp);
1850 omap3isp_ccp2_cleanup(isp);
1851 omap3isp_csi2_cleanup(isp);
1852}
1853
1854static int isp_initialize_modules(struct isp_device *isp)
1855{
1856 int ret;
1857
1858 ret = omap3isp_csiphy_init(isp);
1859 if (ret < 0) {
1860 dev_err(isp->dev, "CSI PHY initialization failed\n");
1861 goto error_csiphy;
1862 }
1863
1864 ret = omap3isp_csi2_init(isp);
1865 if (ret < 0) {
1866 dev_err(isp->dev, "CSI2 initialization failed\n");
1867 goto error_csi2;
1868 }
1869
1870 ret = omap3isp_ccp2_init(isp);
1871 if (ret < 0) {
1872 dev_err(isp->dev, "CCP2 initialization failed\n");
1873 goto error_ccp2;
1874 }
1875
1876 ret = omap3isp_ccdc_init(isp);
1877 if (ret < 0) {
1878 dev_err(isp->dev, "CCDC initialization failed\n");
1879 goto error_ccdc;
1880 }
1881
1882 ret = omap3isp_preview_init(isp);
1883 if (ret < 0) {
1884 dev_err(isp->dev, "Preview initialization failed\n");
1885 goto error_preview;
1886 }
1887
1888 ret = omap3isp_resizer_init(isp);
1889 if (ret < 0) {
1890 dev_err(isp->dev, "Resizer initialization failed\n");
1891 goto error_resizer;
1892 }
1893
1894 ret = omap3isp_hist_init(isp);
1895 if (ret < 0) {
1896 dev_err(isp->dev, "Histogram initialization failed\n");
1897 goto error_hist;
1898 }
1899
1900 ret = omap3isp_h3a_aewb_init(isp);
1901 if (ret < 0) {
1902 dev_err(isp->dev, "H3A AEWB initialization failed\n");
1903 goto error_h3a_aewb;
1904 }
1905
1906 ret = omap3isp_h3a_af_init(isp);
1907 if (ret < 0) {
1908 dev_err(isp->dev, "H3A AF initialization failed\n");
1909 goto error_h3a_af;
1910 }
1911
1912 /* Connect the submodules. */
1913 ret = media_entity_create_link(
1914 &isp->isp_csi2a.subdev.entity, CSI2_PAD_SOURCE,
1915 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SINK, 0);
1916 if (ret < 0)
1917 goto error_link;
1918
1919 ret = media_entity_create_link(
1920 &isp->isp_ccp2.subdev.entity, CCP2_PAD_SOURCE,
1921 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SINK, 0);
1922 if (ret < 0)
1923 goto error_link;
1924
1925 ret = media_entity_create_link(
1926 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1927 &isp->isp_prev.subdev.entity, PREV_PAD_SINK, 0);
1928 if (ret < 0)
1929 goto error_link;
1930
1931 ret = media_entity_create_link(
1932 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_OF,
1933 &isp->isp_res.subdev.entity, RESZ_PAD_SINK, 0);
1934 if (ret < 0)
1935 goto error_link;
1936
1937 ret = media_entity_create_link(
1938 &isp->isp_prev.subdev.entity, PREV_PAD_SOURCE,
1939 &isp->isp_res.subdev.entity, RESZ_PAD_SINK, 0);
1940 if (ret < 0)
1941 goto error_link;
1942
1943 ret = media_entity_create_link(
1944 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1945 &isp->isp_aewb.subdev.entity, 0,
1946 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1947 if (ret < 0)
1948 goto error_link;
1949
1950 ret = media_entity_create_link(
1951 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1952 &isp->isp_af.subdev.entity, 0,
1953 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1954 if (ret < 0)
1955 goto error_link;
1956
1957 ret = media_entity_create_link(
1958 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1959 &isp->isp_hist.subdev.entity, 0,
1960 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1961 if (ret < 0)
1962 goto error_link;
1963
1964 return 0;
1965
1966error_link:
1967 omap3isp_h3a_af_cleanup(isp);
1968error_h3a_af:
1969 omap3isp_h3a_aewb_cleanup(isp);
1970error_h3a_aewb:
1971 omap3isp_hist_cleanup(isp);
1972error_hist:
1973 omap3isp_resizer_cleanup(isp);
1974error_resizer:
1975 omap3isp_preview_cleanup(isp);
1976error_preview:
1977 omap3isp_ccdc_cleanup(isp);
1978error_ccdc:
1979 omap3isp_ccp2_cleanup(isp);
1980error_ccp2:
1981 omap3isp_csi2_cleanup(isp);
1982error_csi2:
1983error_csiphy:
1984 return ret;
1985}
1986
1987/*
1988 * isp_remove - Remove ISP platform device
1989 * @pdev: Pointer to ISP platform device
1990 *
1991 * Always returns 0.
1992 */
4c62e976 1993static int isp_remove(struct platform_device *pdev)
448de7e7
SA		 1994{
1995 struct isp_device *isp = platform_get_drvdata(pdev);
1996 int i;
1997
1998 isp_unregister_entities(isp);
1999 isp_cleanup_modules(isp);
2000
96d62ae2 2001 __omap3isp_get(isp, false);
fabdbca8 2002 iommu_detach_device(isp->domain, &pdev->dev);
f626b52d 2003 iommu_domain_free(isp->domain);
a32f2f90 2004 isp->domain = NULL;
448de7e7
SA		 2005 omap3isp_put(isp);
2006
2007 free_irq(isp->irq_num, isp);
2008 isp_put_clocks(isp);
2009
2010 for (i = 0; i < OMAP3_ISP_IOMEM_LAST; i++) {
2011 if (isp->mmio_base[i]) {
2012 iounmap(isp->mmio_base[i]);
2013 isp->mmio_base[i] = NULL;
2014 }
2015
2016 if (isp->mmio_base_phys[i]) {
2017 release_mem_region(isp->mmio_base_phys[i],
2018 isp->mmio_size[i]);
2019 isp->mmio_base_phys[i] = 0;
2020 }
2021 }
2022
2023 regulator_put(isp->isp_csiphy1.vdd);
2024 regulator_put(isp->isp_csiphy2.vdd);
2025 kfree(isp);
2026
2027 return 0;
2028}
2029
2030static int isp_map_mem_resource(struct platform_device *pdev,
2031 struct isp_device *isp,
2032 enum isp_mem_resources res)
2033{
2034 struct resource *mem;
2035
2036 /* request the mem region for the camera registers */
2037
2038 mem = platform_get_resource(pdev, IORESOURCE_MEM, res);
2039 if (!mem) {
2040 dev_err(isp->dev, "no mem resource?\n");
2041 return -ENODEV;
2042 }
2043
2044 if (!request_mem_region(mem->start, resource_size(mem), pdev->name)) {
2045 dev_err(isp->dev,
2046 "cannot reserve camera register I/O region\n");
2047 return -ENODEV;
2048 }
2049 isp->mmio_base_phys[res] = mem->start;
2050 isp->mmio_size[res] = resource_size(mem);
2051
2052 /* map the region */
2053 isp->mmio_base[res] = ioremap_nocache(isp->mmio_base_phys[res],
2054 isp->mmio_size[res]);
2055 if (!isp->mmio_base[res]) {
2056 dev_err(isp->dev, "cannot map camera register I/O region\n");
2057 return -ENODEV;
2058 }
2059
2060 return 0;
2061}
2062
2063/*
2064 * isp_probe - Probe ISP platform device
2065 * @pdev: Pointer to ISP platform device
2066 *
2067 * Returns 0 if successful,
2068 * -ENOMEM if no memory available,
2069 * -ENODEV if no platform device resources found
2070 * or no space for remapping registers,
2071 * -EINVAL if couldn't install ISR,
2072 * or clk_get return error value.
2073 */
4c62e976 2074static int isp_probe(struct platform_device *pdev)
448de7e7
SA		 2075{
2076 struct isp_platform_data *pdata = pdev->dev.platform_data;
2077 struct isp_device *isp;
2078 int ret;
2079 int i, m;
2080
2081 if (pdata == NULL)
2082 return -EINVAL;
2083
2084 isp = kzalloc(sizeof(*isp), GFP_KERNEL);
2085 if (!isp) {
2086 dev_err(&pdev->dev, "could not allocate memory\n");
2087 return -ENOMEM;
2088 }
2089
2090 isp->autoidle = autoidle;
2091 isp->platform_cb.set_xclk = isp_set_xclk;
448de7e7
SA		 2092
2093 mutex_init(&isp->isp_mutex);
2094 spin_lock_init(&isp->stat_lock);
2095
2096 isp->dev = &pdev->dev;
2097 isp->pdata = pdata;
2098 isp->ref_count = 0;
2099
2100 isp->raw_dmamask = DMA_BIT_MASK(32);
2101 isp->dev->dma_mask = &isp->raw_dmamask;
2102 isp->dev->coherent_dma_mask = DMA_BIT_MASK(32);
2103
2104 platform_set_drvdata(pdev, isp);
2105
2106 /* Regulators */
2107 isp->isp_csiphy1.vdd = regulator_get(&pdev->dev, "VDD_CSIPHY1");
2108 isp->isp_csiphy2.vdd = regulator_get(&pdev->dev, "VDD_CSIPHY2");
2109
d8658bca
LP		 2110 /* Clocks
2111 *
2112 * The ISP clock tree is revision-dependent. We thus need to enable ICLK
2113 * manually to read the revision before calling __omap3isp_get().
2114 */
448de7e7
SA		 2115 ret = isp_map_mem_resource(pdev, isp, OMAP3_ISP_IOMEM_MAIN);
2116 if (ret < 0)
2117 goto error;
2118
2119 ret = isp_get_clocks(isp);
2120 if (ret < 0)
2121 goto error;
2122
d8658bca
LP		 2123 ret = clk_enable(isp->clock[ISP_CLK_CAM_ICK]);
2124 if (ret < 0)
2125 goto error;
2126
2127 isp->revision = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION);
2128 dev_info(isp->dev, "Revision %d.%d found\n",
2129 (isp->revision & 0xf0) >> 4, isp->revision & 0x0f);
2130
2131 clk_disable(isp->clock[ISP_CLK_CAM_ICK]);
2132
0bd0dbee
PST		 2133 if (__omap3isp_get(isp, false) == NULL) {
2134 ret = -ENODEV;
448de7e7 2135 goto error;
0bd0dbee 2136 }
448de7e7
SA		 2137
2138 ret = isp_reset(isp);
2139 if (ret < 0)
2140 goto error_isp;
2141
2142 /* Memory resources */
448de7e7
SA		 2143 for (m = 0; m < ARRAY_SIZE(isp_res_maps); m++)
2144 if (isp->revision == isp_res_maps[m].isp_rev)
2145 break;
2146
2147 if (m == ARRAY_SIZE(isp_res_maps)) {
2148 dev_err(isp->dev, "No resource map found for ISP rev %d.%d\n",
2149 (isp->revision & 0xf0) >> 4, isp->revision & 0xf);
2150 ret = -ENODEV;
2151 goto error_isp;
2152 }
2153
2154 for (i = 1; i < OMAP3_ISP_IOMEM_LAST; i++) {
2155 if (isp_res_maps[m].map & 1 << i) {
2156 ret = isp_map_mem_resource(pdev, isp, i);
2157 if (ret)
2158 goto error_isp;
2159 }
2160 }
2161
905d66c1 2162 isp->domain = iommu_domain_alloc(pdev->dev.bus);
f626b52d
OBC		 2163 if (!isp->domain) {
2164 dev_err(isp->dev, "can't alloc iommu domain\n");
2165 ret = -ENOMEM;
2166 goto error_isp;
2167 }
2168
fabdbca8 2169 ret = iommu_attach_device(isp->domain, &pdev->dev);
f626b52d
OBC		 2170 if (ret) {
2171 dev_err(&pdev->dev, "can't attach iommu device: %d\n", ret);
2172 goto free_domain;
2173 }
2174
448de7e7
SA		 2175 /* Interrupt */
2176 isp->irq_num = platform_get_irq(pdev, 0);
2177 if (isp->irq_num <= 0) {
2178 dev_err(isp->dev, "No IRQ resource\n");
2179 ret = -ENODEV;
f626b52d 2180 goto detach_dev;
448de7e7
SA		 2181 }
2182
2183 if (request_irq(isp->irq_num, isp_isr, IRQF_SHARED, "OMAP3 ISP", isp)) {
2184 dev_err(isp->dev, "Unable to request IRQ\n");
2185 ret = -EINVAL;
f626b52d 2186 goto detach_dev;
448de7e7
SA		 2187 }
2188
2189 /* Entities */
2190 ret = isp_initialize_modules(isp);
2191 if (ret < 0)
2192 goto error_irq;
2193
2194 ret = isp_register_entities(isp);
2195 if (ret < 0)
2196 goto error_modules;
2197
96d62ae2 2198 isp_core_init(isp, 1);
448de7e7
SA		 2199 omap3isp_put(isp);
2200
2201 return 0;
2202
2203error_modules:
2204 isp_cleanup_modules(isp);
2205error_irq:
2206 free_irq(isp->irq_num, isp);
f626b52d 2207detach_dev:
fabdbca8 2208 iommu_detach_device(isp->domain, &pdev->dev);
f626b52d
OBC		 2209free_domain:
2210 iommu_domain_free(isp->domain);
448de7e7 2211error_isp:
448de7e7
SA		 2212 omap3isp_put(isp);
2213error:
2214 isp_put_clocks(isp);
2215
2216 for (i = 0; i < OMAP3_ISP_IOMEM_LAST; i++) {
2217 if (isp->mmio_base[i]) {
2218 iounmap(isp->mmio_base[i]);
2219 isp->mmio_base[i] = NULL;
2220 }
2221
2222 if (isp->mmio_base_phys[i]) {
2223 release_mem_region(isp->mmio_base_phys[i],
2224 isp->mmio_size[i]);
2225 isp->mmio_base_phys[i] = 0;
2226 }
2227 }
2228 regulator_put(isp->isp_csiphy2.vdd);
2229 regulator_put(isp->isp_csiphy1.vdd);
2230 platform_set_drvdata(pdev, NULL);
ed33ac8e
LP		 2231
2232 mutex_destroy(&isp->isp_mutex);
448de7e7
SA		 2233 kfree(isp);
2234
2235 return ret;
2236}
2237
2238static const struct dev_pm_ops omap3isp_pm_ops = {
2239 .prepare = isp_pm_prepare,
2240 .suspend = isp_pm_suspend,
2241 .resume = isp_pm_resume,
2242 .complete = isp_pm_complete,
2243};
2244
2245static struct platform_device_id omap3isp_id_table[] = {
2246 { "omap3isp", 0 },
2247 { },
2248};
2249MODULE_DEVICE_TABLE(platform, omap3isp_id_table);
2250
2251static struct platform_driver omap3isp_driver = {
2252 .probe = isp_probe,
4c62e976 2253 .remove = isp_remove,
448de7e7
SA		 2254 .id_table = omap3isp_id_table,
2255 .driver = {
2256 .owner = THIS_MODULE,
2257 .name = "omap3isp",
2258 .pm = &omap3isp_pm_ops,
2259 },
2260};
2261
1d6629b1 2262module_platform_driver(omap3isp_driver);
448de7e7
SA		 2263
2264MODULE_AUTHOR("Nokia Corporation");
2265MODULE_DESCRIPTION("TI OMAP3 ISP driver");
2266MODULE_LICENSE("GPL");
64dc3c1a 2267MODULE_VERSION(ISP_VIDEO_DRIVER_VERSION);
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