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[media] media: get rid of unused "extra_links" param on media_entity_init()
[mirror_ubuntu-artful-kernel.git] / drivers / media / platform / omap3isp / ispcsi2.c
CommitLineData
121e9f1c
LP		 1/*
2 * ispcsi2.c
3 *
4 * TI OMAP3 ISP - CSI2 module
5 *
6 * Copyright (C) 2010 Nokia Corporation
7 * Copyright (C) 2009 Texas Instruments, Inc.
8 *
9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 * Sakari Ailus <sakari.ailus@iki.fi>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
121e9f1c
LP		 15 */
16#include <linux/delay.h>
17#include <media/v4l2-common.h>
18#include <linux/v4l2-mediabus.h>
19#include <linux/mm.h>
20
21#include "isp.h"
22#include "ispreg.h"
23#include "ispcsi2.h"
24
25/*
26 * csi2_if_enable - Enable CSI2 Receiver interface.
27 * @enable: enable flag
28 *
29 */
30static void csi2_if_enable(struct isp_device *isp,
31 struct isp_csi2_device *csi2, u8 enable)
32{
33 struct isp_csi2_ctrl_cfg *currctrl = &csi2->ctrl;
34
35 isp_reg_clr_set(isp, csi2->regs1, ISPCSI2_CTRL, ISPCSI2_CTRL_IF_EN,
36 enable ? ISPCSI2_CTRL_IF_EN : 0);
37
38 currctrl->if_enable = enable;
39}
40
41/*
42 * csi2_recv_config - CSI2 receiver module configuration.
43 * @currctrl: isp_csi2_ctrl_cfg structure
44 *
45 */
46static void csi2_recv_config(struct isp_device *isp,
47 struct isp_csi2_device *csi2,
48 struct isp_csi2_ctrl_cfg *currctrl)
49{
50 u32 reg;
51
52 reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTRL);
53
54 if (currctrl->frame_mode)
55 reg |= ISPCSI2_CTRL_FRAME;
56 else
57 reg &= ~ISPCSI2_CTRL_FRAME;
58
59 if (currctrl->vp_clk_enable)
60 reg |= ISPCSI2_CTRL_VP_CLK_EN;
61 else
62 reg &= ~ISPCSI2_CTRL_VP_CLK_EN;
63
64 if (currctrl->vp_only_enable)
65 reg |= ISPCSI2_CTRL_VP_ONLY_EN;
66 else
67 reg &= ~ISPCSI2_CTRL_VP_ONLY_EN;
68
69 reg &= ~ISPCSI2_CTRL_VP_OUT_CTRL_MASK;
70 reg |= currctrl->vp_out_ctrl << ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT;
71
72 if (currctrl->ecc_enable)
73 reg |= ISPCSI2_CTRL_ECC_EN;
74 else
75 reg &= ~ISPCSI2_CTRL_ECC_EN;
76
77 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTRL);
78}
79
80static const unsigned int csi2_input_fmts[] = {
27ffaeb0
BB		 81 MEDIA_BUS_FMT_SGRBG10_1X10,
82 MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
83 MEDIA_BUS_FMT_SRGGB10_1X10,
84 MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8,
85 MEDIA_BUS_FMT_SBGGR10_1X10,
86 MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8,
87 MEDIA_BUS_FMT_SGBRG10_1X10,
88 MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8,
89 MEDIA_BUS_FMT_YUYV8_2X8,
121e9f1c
LP		 90};
91
92/* To set the format on the CSI2 requires a mapping function that takes
93 * the following inputs:
73cdc79f 94 * - 3 different formats (at this time)
121e9f1c
LP		 95 * - 2 destinations (mem, vp+mem) (vp only handled separately)
96 * - 2 decompression options (on, off)
97 * - 2 isp revisions (certain format must be handled differently on OMAP3630)
98 * Output should be CSI2 frame format code
99 * Array indices as follows: [format][dest][decompr][is_3630]
100 * Not all combinations are valid. 0 means invalid.
101 */
73cdc79f 102static const u16 __csi2_fmt_map[3][2][2][2] = {
121e9f1c
LP		 103 /* RAW10 formats */
104 {
105 /* Output to memory */
106 {
107 /* No DPCM decompression */
108 { CSI2_PIX_FMT_RAW10_EXP16, CSI2_PIX_FMT_RAW10_EXP16 },
109 /* DPCM decompression */
110 { 0, 0 },
111 },
112 /* Output to both */
113 {
114 /* No DPCM decompression */
115 { CSI2_PIX_FMT_RAW10_EXP16_VP,
116 CSI2_PIX_FMT_RAW10_EXP16_VP },
117 /* DPCM decompression */
118 { 0, 0 },
119 },
120 },
121 /* RAW10 DPCM8 formats */
122 {
123 /* Output to memory */
124 {
125 /* No DPCM decompression */
126 { CSI2_PIX_FMT_RAW8, CSI2_USERDEF_8BIT_DATA1 },
127 /* DPCM decompression */
128 { CSI2_PIX_FMT_RAW8_DPCM10_EXP16,
129 CSI2_USERDEF_8BIT_DATA1_DPCM10 },
130 },
131 /* Output to both */
132 {
133 /* No DPCM decompression */
134 { CSI2_PIX_FMT_RAW8_VP,
135 CSI2_PIX_FMT_RAW8_VP },
136 /* DPCM decompression */
137 { CSI2_PIX_FMT_RAW8_DPCM10_VP,
138 CSI2_USERDEF_8BIT_DATA1_DPCM10_VP },
139 },
140 },
73cdc79f
IP		 141 /* YUYV8 2X8 formats */
142 {
143 /* Output to memory */
144 {
145 /* No DPCM decompression */
146 { CSI2_PIX_FMT_YUV422_8BIT,
147 CSI2_PIX_FMT_YUV422_8BIT },
148 /* DPCM decompression */
149 { 0, 0 },
150 },
151 /* Output to both */
152 {
153 /* No DPCM decompression */
154 { CSI2_PIX_FMT_YUV422_8BIT_VP,
155 CSI2_PIX_FMT_YUV422_8BIT_VP },
156 /* DPCM decompression */
157 { 0, 0 },
158 },
159 },
121e9f1c
LP		 160};
161
162/*
163 * csi2_ctx_map_format - Map CSI2 sink media bus format to CSI2 format ID
164 * @csi2: ISP CSI2 device
165 *
166 * Returns CSI2 physical format id
167 */
168static u16 csi2_ctx_map_format(struct isp_csi2_device *csi2)
169{
170 const struct v4l2_mbus_framefmt *fmt = &csi2->formats[CSI2_PAD_SINK];
171 int fmtidx, destidx, is_3630;
172
173 switch (fmt->code) {
27ffaeb0
BB		 174 case MEDIA_BUS_FMT_SGRBG10_1X10:
175 case MEDIA_BUS_FMT_SRGGB10_1X10:
176 case MEDIA_BUS_FMT_SBGGR10_1X10:
177 case MEDIA_BUS_FMT_SGBRG10_1X10:
121e9f1c
LP		 178 fmtidx = 0;
179 break;
27ffaeb0
BB		 180 case MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8:
181 case MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8:
182 case MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8:
183 case MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8:
121e9f1c
LP		 184 fmtidx = 1;
185 break;
27ffaeb0 186 case MEDIA_BUS_FMT_YUYV8_2X8:
73cdc79f
IP		 187 fmtidx = 2;
188 break;
121e9f1c
LP		 189 default:
190 WARN(1, KERN_ERR "CSI2: pixel format %08x unsupported!\n",
191 fmt->code);
192 return 0;
193 }
194
195 if (!(csi2->output & CSI2_OUTPUT_CCDC) &&
196 !(csi2->output & CSI2_OUTPUT_MEMORY)) {
197 /* Neither output enabled is a valid combination */
198 return CSI2_PIX_FMT_OTHERS;
199 }
200
201 /* If we need to skip frames at the beginning of the stream disable the
202 * video port to avoid sending the skipped frames to the CCDC.
203 */
204 destidx = csi2->frame_skip ? 0 : !!(csi2->output & CSI2_OUTPUT_CCDC);
205 is_3630 = csi2->isp->revision == ISP_REVISION_15_0;
206
207 return __csi2_fmt_map[fmtidx][destidx][csi2->dpcm_decompress][is_3630];
208}
209
210/*
211 * csi2_set_outaddr - Set memory address to save output image
212 * @csi2: Pointer to ISP CSI2a device.
213 * @addr: ISP MMU Mapped 32-bit memory address aligned on 32 byte boundary.
214 *
215 * Sets the memory address where the output will be saved.
216 *
217 * Returns 0 if successful, or -EINVAL if the address is not in the 32 byte
218 * boundary.
219 */
220static void csi2_set_outaddr(struct isp_csi2_device *csi2, u32 addr)
221{
222 struct isp_device *isp = csi2->isp;
223 struct isp_csi2_ctx_cfg *ctx = &csi2->contexts[0];
224
225 ctx->ping_addr = addr;
226 ctx->pong_addr = addr;
227 isp_reg_writel(isp, ctx->ping_addr,
228 csi2->regs1, ISPCSI2_CTX_DAT_PING_ADDR(ctx->ctxnum));
229 isp_reg_writel(isp, ctx->pong_addr,
230 csi2->regs1, ISPCSI2_CTX_DAT_PONG_ADDR(ctx->ctxnum));
231}
232
233/*
234 * is_usr_def_mapping - Checks whether USER_DEF_MAPPING should
235 * be enabled by CSI2.
236 * @format_id: mapped format id
237 *
238 */
239static inline int is_usr_def_mapping(u32 format_id)
240{
241 return (format_id & 0x40) ? 1 : 0;
242}
243
244/*
245 * csi2_ctx_enable - Enable specified CSI2 context
246 * @ctxnum: Context number, valid between 0 and 7 values.
247 * @enable: enable
248 *
249 */
250static void csi2_ctx_enable(struct isp_device *isp,
251 struct isp_csi2_device *csi2, u8 ctxnum, u8 enable)
252{
253 struct isp_csi2_ctx_cfg *ctx = &csi2->contexts[ctxnum];
254 unsigned int skip = 0;
255 u32 reg;
256
257 reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL1(ctxnum));
258
259 if (enable) {
260 if (csi2->frame_skip)
261 skip = csi2->frame_skip;
262 else if (csi2->output & CSI2_OUTPUT_MEMORY)
263 skip = 1;
264
265 reg &= ~ISPCSI2_CTX_CTRL1_COUNT_MASK;
266 reg |= ISPCSI2_CTX_CTRL1_COUNT_UNLOCK
267 | (skip << ISPCSI2_CTX_CTRL1_COUNT_SHIFT)
268 | ISPCSI2_CTX_CTRL1_CTX_EN;
269 } else {
270 reg &= ~ISPCSI2_CTX_CTRL1_CTX_EN;
271 }
272
273 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL1(ctxnum));
274 ctx->enabled = enable;
275}
276
277/*
278 * csi2_ctx_config - CSI2 context configuration.
279 * @ctx: context configuration
280 *
281 */
282static void csi2_ctx_config(struct isp_device *isp,
283 struct isp_csi2_device *csi2,
284 struct isp_csi2_ctx_cfg *ctx)
285{
286 u32 reg;
287
288 /* Set up CSI2_CTx_CTRL1 */
289 reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL1(ctx->ctxnum));
290
291 if (ctx->eof_enabled)
292 reg |= ISPCSI2_CTX_CTRL1_EOF_EN;
293 else
294 reg &= ~ISPCSI2_CTX_CTRL1_EOF_EN;
295
296 if (ctx->eol_enabled)
297 reg |= ISPCSI2_CTX_CTRL1_EOL_EN;
298 else
299 reg &= ~ISPCSI2_CTX_CTRL1_EOL_EN;
300
301 if (ctx->checksum_enabled)
302 reg |= ISPCSI2_CTX_CTRL1_CS_EN;
303 else
304 reg &= ~ISPCSI2_CTX_CTRL1_CS_EN;
305
306 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL1(ctx->ctxnum));
307
308 /* Set up CSI2_CTx_CTRL2 */
309 reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL2(ctx->ctxnum));
310
311 reg &= ~(ISPCSI2_CTX_CTRL2_VIRTUAL_ID_MASK);
312 reg |= ctx->virtual_id << ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT;
313
314 reg &= ~(ISPCSI2_CTX_CTRL2_FORMAT_MASK);
315 reg |= ctx->format_id << ISPCSI2_CTX_CTRL2_FORMAT_SHIFT;
316
317 if (ctx->dpcm_decompress) {
318 if (ctx->dpcm_predictor)
319 reg |= ISPCSI2_CTX_CTRL2_DPCM_PRED;
320 else
321 reg &= ~ISPCSI2_CTX_CTRL2_DPCM_PRED;
322 }
323
324 if (is_usr_def_mapping(ctx->format_id)) {
325 reg &= ~ISPCSI2_CTX_CTRL2_USER_DEF_MAP_MASK;
326 reg |= 2 << ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT;
327 }
328
329 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL2(ctx->ctxnum));
330
331 /* Set up CSI2_CTx_CTRL3 */
332 reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL3(ctx->ctxnum));
333 reg &= ~(ISPCSI2_CTX_CTRL3_ALPHA_MASK);
334 reg |= (ctx->alpha << ISPCSI2_CTX_CTRL3_ALPHA_SHIFT);
335
336 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL3(ctx->ctxnum));
337
338 /* Set up CSI2_CTx_DAT_OFST */
339 reg = isp_reg_readl(isp, csi2->regs1,
340 ISPCSI2_CTX_DAT_OFST(ctx->ctxnum));
341 reg &= ~ISPCSI2_CTX_DAT_OFST_OFST_MASK;
342 reg |= ctx->data_offset << ISPCSI2_CTX_DAT_OFST_OFST_SHIFT;
343 isp_reg_writel(isp, reg, csi2->regs1,
344 ISPCSI2_CTX_DAT_OFST(ctx->ctxnum));
345
346 isp_reg_writel(isp, ctx->ping_addr,
347 csi2->regs1, ISPCSI2_CTX_DAT_PING_ADDR(ctx->ctxnum));
348
349 isp_reg_writel(isp, ctx->pong_addr,
350 csi2->regs1, ISPCSI2_CTX_DAT_PONG_ADDR(ctx->ctxnum));
351}
352
353/*
354 * csi2_timing_config - CSI2 timing configuration.
355 * @timing: csi2_timing_cfg structure
356 */
357static void csi2_timing_config(struct isp_device *isp,
358 struct isp_csi2_device *csi2,
359 struct isp_csi2_timing_cfg *timing)
360{
361 u32 reg;
362
363 reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_TIMING);
364
365 if (timing->force_rx_mode)
366 reg |= ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing->ionum);
367 else
368 reg &= ~ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing->ionum);
369
370 if (timing->stop_state_16x)
371 reg |= ISPCSI2_TIMING_STOP_STATE_X16_IO(timing->ionum);
372 else
373 reg &= ~ISPCSI2_TIMING_STOP_STATE_X16_IO(timing->ionum);
374
375 if (timing->stop_state_4x)
376 reg |= ISPCSI2_TIMING_STOP_STATE_X4_IO(timing->ionum);
377 else
378 reg &= ~ISPCSI2_TIMING_STOP_STATE_X4_IO(timing->ionum);
379
380 reg &= ~ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_MASK(timing->ionum);
381 reg |= timing->stop_state_counter <<
382 ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(timing->ionum);
383
384 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_TIMING);
385}
386
387/*
388 * csi2_irq_ctx_set - Enables CSI2 Context IRQs.
389 * @enable: Enable/disable CSI2 Context interrupts
390 */
391static void csi2_irq_ctx_set(struct isp_device *isp,
392 struct isp_csi2_device *csi2, int enable)
393{
121e9f1c
LP		 394 int i;
395
121e9f1c 396 for (i = 0; i < 8; i++) {
b43883d6 397 isp_reg_writel(isp, ISPCSI2_CTX_IRQSTATUS_FE_IRQ, csi2->regs1,
121e9f1c
LP		 398 ISPCSI2_CTX_IRQSTATUS(i));
399 if (enable)
400 isp_reg_set(isp, csi2->regs1, ISPCSI2_CTX_IRQENABLE(i),
b43883d6 401 ISPCSI2_CTX_IRQSTATUS_FE_IRQ);
121e9f1c
LP		 402 else
403 isp_reg_clr(isp, csi2->regs1, ISPCSI2_CTX_IRQENABLE(i),
b43883d6 404 ISPCSI2_CTX_IRQSTATUS_FE_IRQ);
121e9f1c
LP		 405 }
406}
407
408/*
409 * csi2_irq_complexio1_set - Enables CSI2 ComplexIO IRQs.
410 * @enable: Enable/disable CSI2 ComplexIO #1 interrupts
411 */
412static void csi2_irq_complexio1_set(struct isp_device *isp,
413 struct isp_csi2_device *csi2, int enable)
414{
415 u32 reg;
416 reg = ISPCSI2_PHY_IRQENABLE_STATEALLULPMEXIT |
417 ISPCSI2_PHY_IRQENABLE_STATEALLULPMENTER |
418 ISPCSI2_PHY_IRQENABLE_STATEULPM5 |
419 ISPCSI2_PHY_IRQENABLE_ERRCONTROL5 |
420 ISPCSI2_PHY_IRQENABLE_ERRESC5 |
421 ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS5 |
422 ISPCSI2_PHY_IRQENABLE_ERRSOTHS5 |
423 ISPCSI2_PHY_IRQENABLE_STATEULPM4 |
424 ISPCSI2_PHY_IRQENABLE_ERRCONTROL4 |
425 ISPCSI2_PHY_IRQENABLE_ERRESC4 |
426 ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS4 |
427 ISPCSI2_PHY_IRQENABLE_ERRSOTHS4 |
428 ISPCSI2_PHY_IRQENABLE_STATEULPM3 |
429 ISPCSI2_PHY_IRQENABLE_ERRCONTROL3 |
430 ISPCSI2_PHY_IRQENABLE_ERRESC3 |
431 ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS3 |
432 ISPCSI2_PHY_IRQENABLE_ERRSOTHS3 |
433 ISPCSI2_PHY_IRQENABLE_STATEULPM2 |
434 ISPCSI2_PHY_IRQENABLE_ERRCONTROL2 |
435 ISPCSI2_PHY_IRQENABLE_ERRESC2 |
436 ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS2 |
437 ISPCSI2_PHY_IRQENABLE_ERRSOTHS2 |
438 ISPCSI2_PHY_IRQENABLE_STATEULPM1 |
439 ISPCSI2_PHY_IRQENABLE_ERRCONTROL1 |
440 ISPCSI2_PHY_IRQENABLE_ERRESC1 |
441 ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS1 |
442 ISPCSI2_PHY_IRQENABLE_ERRSOTHS1;
443 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_PHY_IRQSTATUS);
444 if (enable)
445 reg |= isp_reg_readl(isp, csi2->regs1, ISPCSI2_PHY_IRQENABLE);
446 else
447 reg = 0;
448 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_PHY_IRQENABLE);
449}
450
451/*
452 * csi2_irq_status_set - Enables CSI2 Status IRQs.
453 * @enable: Enable/disable CSI2 Status interrupts
454 */
455static void csi2_irq_status_set(struct isp_device *isp,
456 struct isp_csi2_device *csi2, int enable)
457{
458 u32 reg;
459 reg = ISPCSI2_IRQSTATUS_OCP_ERR_IRQ |
460 ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ |
461 ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ |
462 ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ |
463 ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ |
464 ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ |
465 ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ |
466 ISPCSI2_IRQSTATUS_CONTEXT(0);
467 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_IRQSTATUS);
468 if (enable)
469 reg |= isp_reg_readl(isp, csi2->regs1, ISPCSI2_IRQENABLE);
470 else
471 reg = 0;
472
473 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_IRQENABLE);
474}
475
476/*
477 * omap3isp_csi2_reset - Resets the CSI2 module.
478 *
479 * Must be called with the phy lock held.
480 *
481 * Returns 0 if successful, or -EBUSY if power command didn't respond.
482 */
483int omap3isp_csi2_reset(struct isp_csi2_device *csi2)
484{
485 struct isp_device *isp = csi2->isp;
486 u8 soft_reset_retries = 0;
487 u32 reg;
488 int i;
489
490 if (!csi2->available)
491 return -ENODEV;
492
493 if (csi2->phy->phy_in_use)
494 return -EBUSY;
495
496 isp_reg_set(isp, csi2->regs1, ISPCSI2_SYSCONFIG,
497 ISPCSI2_SYSCONFIG_SOFT_RESET);
498
499 do {
500 reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_SYSSTATUS) &
501 ISPCSI2_SYSSTATUS_RESET_DONE;
502 if (reg == ISPCSI2_SYSSTATUS_RESET_DONE)
503 break;
504 soft_reset_retries++;
505 if (soft_reset_retries < 5)
506 udelay(100);
507 } while (soft_reset_retries < 5);
508
509 if (soft_reset_retries == 5) {
4feca39b 510 dev_err(isp->dev, "CSI2: Soft reset try count exceeded!\n");
121e9f1c
LP		 511 return -EBUSY;
512 }
513
514 if (isp->revision == ISP_REVISION_15_0)
515 isp_reg_set(isp, csi2->regs1, ISPCSI2_PHY_CFG,
516 ISPCSI2_PHY_CFG_RESET_CTRL);
517
518 i = 100;
519 do {
520 reg = isp_reg_readl(isp, csi2->phy->phy_regs, ISPCSIPHY_REG1)
521 & ISPCSIPHY_REG1_RESET_DONE_CTRLCLK;
522 if (reg == ISPCSIPHY_REG1_RESET_DONE_CTRLCLK)
523 break;
524 udelay(100);
525 } while (--i > 0);
526
527 if (i == 0) {
4feca39b
LP		 528 dev_err(isp->dev,
529 "CSI2: Reset for CSI2_96M_FCLK domain Failed!\n");
121e9f1c
LP		 530 return -EBUSY;
531 }
532
533 if (isp->autoidle)
534 isp_reg_clr_set(isp, csi2->regs1, ISPCSI2_SYSCONFIG,
535 ISPCSI2_SYSCONFIG_MSTANDBY_MODE_MASK |
536 ISPCSI2_SYSCONFIG_AUTO_IDLE,
537 ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SMART |
538 ((isp->revision == ISP_REVISION_15_0) ?
539 ISPCSI2_SYSCONFIG_AUTO_IDLE : 0));
540 else
541 isp_reg_clr_set(isp, csi2->regs1, ISPCSI2_SYSCONFIG,
542 ISPCSI2_SYSCONFIG_MSTANDBY_MODE_MASK |
543 ISPCSI2_SYSCONFIG_AUTO_IDLE,
544 ISPCSI2_SYSCONFIG_MSTANDBY_MODE_NO);
545
546 return 0;
547}
548
549static int csi2_configure(struct isp_csi2_device *csi2)
550{
6387b752 551 struct isp_pipeline *pipe = to_isp_pipeline(&csi2->subdev.entity);
68908747 552 const struct isp_bus_cfg *buscfg;
121e9f1c
LP		 553 struct isp_device *isp = csi2->isp;
554 struct isp_csi2_timing_cfg *timing = &csi2->timing[0];
555 struct v4l2_subdev *sensor;
556 struct media_pad *pad;
557
558 /*
559 * CSI2 fields that can be updated while the context has
560 * been enabled or the interface has been enabled are not
561 * updated dynamically currently. So we do not allow to
562 * reconfigure if either has been enabled
563 */
564 if (csi2->contexts[0].enabled || csi2->ctrl.if_enable)
565 return -EBUSY;
566
1bddf1b3 567 pad = media_entity_remote_pad(&csi2->pads[CSI2_PAD_SINK]);
121e9f1c 568 sensor = media_entity_to_v4l2_subdev(pad->entity);
68908747 569 buscfg = sensor->host_priv;
121e9f1c
LP		 570
571 csi2->frame_skip = 0;
572 v4l2_subdev_call(sensor, sensor, g_skip_frames, &csi2->frame_skip);
573
6387b752
SA		 574 csi2->ctrl.vp_out_ctrl =
575 clamp_t(unsigned int, pipe->l3_ick / pipe->external_rate - 1,
576 1, 3);
577 dev_dbg(isp->dev, "%s: l3_ick %lu, external_rate %u, vp_out_ctrl %u\n",
578 __func__, pipe->l3_ick, pipe->external_rate,
579 csi2->ctrl.vp_out_ctrl);
121e9f1c 580 csi2->ctrl.frame_mode = ISP_CSI2_FRAME_IMMEDIATE;
68908747 581 csi2->ctrl.ecc_enable = buscfg->bus.csi2.crc;
121e9f1c
LP		 582
583 timing->ionum = 1;
584 timing->force_rx_mode = 1;
585 timing->stop_state_16x = 1;
586 timing->stop_state_4x = 1;
587 timing->stop_state_counter = 0x1FF;
588
589 /*
590 * The CSI2 receiver can't do any format conversion except DPCM
591 * decompression, so every set_format call configures both pads
592 * and enables DPCM decompression as a special case:
593 */
594 if (csi2->formats[CSI2_PAD_SINK].code !=
595 csi2->formats[CSI2_PAD_SOURCE].code)
596 csi2->dpcm_decompress = true;
597 else
598 csi2->dpcm_decompress = false;
599
600 csi2->contexts[0].format_id = csi2_ctx_map_format(csi2);
601
602 if (csi2->video_out.bpl_padding == 0)
603 csi2->contexts[0].data_offset = 0;
604 else
605 csi2->contexts[0].data_offset = csi2->video_out.bpl_value;
606
607 /*
608 * Enable end of frame and end of line signals generation for
609 * context 0. These signals are generated from CSI2 receiver to
610 * qualify the last pixel of a frame and the last pixel of a line.
611 * Without enabling the signals CSI2 receiver writes data to memory
612 * beyond buffer size and/or data line offset is not handled correctly.
613 */
614 csi2->contexts[0].eof_enabled = 1;
615 csi2->contexts[0].eol_enabled = 1;
616
617 csi2_irq_complexio1_set(isp, csi2, 1);
618 csi2_irq_ctx_set(isp, csi2, 1);
619 csi2_irq_status_set(isp, csi2, 1);
620
621 /* Set configuration (timings, format and links) */
622 csi2_timing_config(isp, csi2, timing);
623 csi2_recv_config(isp, csi2, &csi2->ctrl);
624 csi2_ctx_config(isp, csi2, &csi2->contexts[0]);
625
626 return 0;
627}
628
629/*
630 * csi2_print_status - Prints CSI2 debug information.
631 */
632#define CSI2_PRINT_REGISTER(isp, regs, name)\
633 dev_dbg(isp->dev, "###CSI2 " #name "=0x%08x\n", \
634 isp_reg_readl(isp, regs, ISPCSI2_##name))
635
636static void csi2_print_status(struct isp_csi2_device *csi2)
637{
638 struct isp_device *isp = csi2->isp;
639
640 if (!csi2->available)
641 return;
642
643 dev_dbg(isp->dev, "-------------CSI2 Register dump-------------\n");
644
645 CSI2_PRINT_REGISTER(isp, csi2->regs1, SYSCONFIG);
646 CSI2_PRINT_REGISTER(isp, csi2->regs1, SYSSTATUS);
647 CSI2_PRINT_REGISTER(isp, csi2->regs1, IRQENABLE);
648 CSI2_PRINT_REGISTER(isp, csi2->regs1, IRQSTATUS);
649 CSI2_PRINT_REGISTER(isp, csi2->regs1, CTRL);
650 CSI2_PRINT_REGISTER(isp, csi2->regs1, DBG_H);
651 CSI2_PRINT_REGISTER(isp, csi2->regs1, GNQ);
652 CSI2_PRINT_REGISTER(isp, csi2->regs1, PHY_CFG);
653 CSI2_PRINT_REGISTER(isp, csi2->regs1, PHY_IRQSTATUS);
654 CSI2_PRINT_REGISTER(isp, csi2->regs1, SHORT_PACKET);
655 CSI2_PRINT_REGISTER(isp, csi2->regs1, PHY_IRQENABLE);
656 CSI2_PRINT_REGISTER(isp, csi2->regs1, DBG_P);
657 CSI2_PRINT_REGISTER(isp, csi2->regs1, TIMING);
658 CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_CTRL1(0));
659 CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_CTRL2(0));
660 CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_DAT_OFST(0));
661 CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_DAT_PING_ADDR(0));
662 CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_DAT_PONG_ADDR(0));
663 CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_IRQENABLE(0));
664 CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_IRQSTATUS(0));
665 CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_CTRL3(0));
666
667 dev_dbg(isp->dev, "--------------------------------------------\n");
668}
669
670/* -----------------------------------------------------------------------------
671 * Interrupt handling
672 */
673
674/*
675 * csi2_isr_buffer - Does buffer handling at end-of-frame
676 * when writing to memory.
677 */
678static void csi2_isr_buffer(struct isp_csi2_device *csi2)
679{
680 struct isp_device *isp = csi2->isp;
681 struct isp_buffer *buffer;
682
683 csi2_ctx_enable(isp, csi2, 0, 0);
684
875e2e3e 685 buffer = omap3isp_video_buffer_next(&csi2->video_out);
121e9f1c
LP		 686
687 /*
688 * Let video queue operation restart engine if there is an underrun
689 * condition.
690 */
691 if (buffer == NULL)
692 return;
693
21d8582d 694 csi2_set_outaddr(csi2, buffer->dma);
121e9f1c
LP		 695 csi2_ctx_enable(isp, csi2, 0, 1);
696}
697
698static void csi2_isr_ctx(struct isp_csi2_device *csi2,
699 struct isp_csi2_ctx_cfg *ctx)
700{
701 struct isp_device *isp = csi2->isp;
702 unsigned int n = ctx->ctxnum;
703 u32 status;
704
705 status = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_IRQSTATUS(n));
706 isp_reg_writel(isp, status, csi2->regs1, ISPCSI2_CTX_IRQSTATUS(n));
707
121e9f1c
LP		 708 if (!(status & ISPCSI2_CTX_IRQSTATUS_FE_IRQ))
709 return;
710
711 /* Skip interrupts until we reach the frame skip count. The CSI2 will be
712 * automatically disabled, as the frame skip count has been programmed
713 * in the CSI2_CTx_CTRL1::COUNT field, so reenable it.
714 *
715 * It would have been nice to rely on the FRAME_NUMBER interrupt instead
716 * but it turned out that the interrupt is only generated when the CSI2
717 * writes to memory (the CSI2_CTx_CTRL1::COUNT field is decreased
718 * correctly and reaches 0 when data is forwarded to the video port only
719 * but no interrupt arrives). Maybe a CSI2 hardware bug.
720 */
721 if (csi2->frame_skip) {
722 csi2->frame_skip--;
723 if (csi2->frame_skip == 0) {
724 ctx->format_id = csi2_ctx_map_format(csi2);
725 csi2_ctx_config(isp, csi2, ctx);
726 csi2_ctx_enable(isp, csi2, n, 1);
727 }
728 return;
729 }
730
731 if (csi2->output & CSI2_OUTPUT_MEMORY)
732 csi2_isr_buffer(csi2);
733}
734
735/*
736 * omap3isp_csi2_isr - CSI2 interrupt handling.
121e9f1c 737 */
875e2e3e 738void omap3isp_csi2_isr(struct isp_csi2_device *csi2)
121e9f1c 739{
875e2e3e 740 struct isp_pipeline *pipe = to_isp_pipeline(&csi2->subdev.entity);
121e9f1c
LP		 741 u32 csi2_irqstatus, cpxio1_irqstatus;
742 struct isp_device *isp = csi2->isp;
121e9f1c
LP		 743
744 if (!csi2->available)
875e2e3e 745 return;
121e9f1c
LP		 746
747 csi2_irqstatus = isp_reg_readl(isp, csi2->regs1, ISPCSI2_IRQSTATUS);
748 isp_reg_writel(isp, csi2_irqstatus, csi2->regs1, ISPCSI2_IRQSTATUS);
749
750 /* Failure Cases */
751 if (csi2_irqstatus & ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ) {
752 cpxio1_irqstatus = isp_reg_readl(isp, csi2->regs1,
753 ISPCSI2_PHY_IRQSTATUS);
754 isp_reg_writel(isp, cpxio1_irqstatus,
755 csi2->regs1, ISPCSI2_PHY_IRQSTATUS);
756 dev_dbg(isp->dev, "CSI2: ComplexIO Error IRQ "
757 "%x\n", cpxio1_irqstatus);
875e2e3e 758 pipe->error = true;
121e9f1c
LP		 759 }
760
761 if (csi2_irqstatus & (ISPCSI2_IRQSTATUS_OCP_ERR_IRQ |
762 ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ |
763 ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ |
764 ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ |
765 ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ)) {
766 dev_dbg(isp->dev, "CSI2 Err:"
767 " OCP:%d,"
768 " Short_pack:%d,"
769 " ECC:%d,"
770 " CPXIO2:%d,"
771 " FIFO_OVF:%d,"
772 "\n",
773 (csi2_irqstatus &
774 ISPCSI2_IRQSTATUS_OCP_ERR_IRQ) ? 1 : 0,
775 (csi2_irqstatus &
776 ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ) ? 1 : 0,
777 (csi2_irqstatus &
778 ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ) ? 1 : 0,
779 (csi2_irqstatus &
780 ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ) ? 1 : 0,
781 (csi2_irqstatus &
782 ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ) ? 1 : 0);
875e2e3e 783 pipe->error = true;
121e9f1c
LP		 784 }
785
786 if (omap3isp_module_sync_is_stopping(&csi2->wait, &csi2->stopping))
875e2e3e 787 return;
121e9f1c
LP		 788
789 /* Successful cases */
790 if (csi2_irqstatus & ISPCSI2_IRQSTATUS_CONTEXT(0))
791 csi2_isr_ctx(csi2, &csi2->contexts[0]);
792
793 if (csi2_irqstatus & ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ)
794 dev_dbg(isp->dev, "CSI2: ECC correction done\n");
121e9f1c
LP		 795}
796
797/* -----------------------------------------------------------------------------
798 * ISP video operations
799 */
800
801/*
802 * csi2_queue - Queues the first buffer when using memory output
803 * @video: The video node
804 * @buffer: buffer to queue
805 */
806static int csi2_queue(struct isp_video *video, struct isp_buffer *buffer)
807{
808 struct isp_device *isp = video->isp;
809 struct isp_csi2_device *csi2 = &isp->isp_csi2a;
810
21d8582d 811 csi2_set_outaddr(csi2, buffer->dma);
121e9f1c
LP		 812
813 /*
814 * If streaming was enabled before there was a buffer queued
815 * or underrun happened in the ISR, the hardware was not enabled
816 * and DMA queue flag ISP_VIDEO_DMAQUEUE_UNDERRUN is still set.
817 * Enable it now.
818 */
819 if (csi2->video_out.dmaqueue_flags & ISP_VIDEO_DMAQUEUE_UNDERRUN) {
820 /* Enable / disable context 0 and IRQs */
821 csi2_if_enable(isp, csi2, 1);
822 csi2_ctx_enable(isp, csi2, 0, 1);
823 isp_video_dmaqueue_flags_clr(&csi2->video_out);
824 }
825
826 return 0;
827}
828
829static const struct isp_video_operations csi2_ispvideo_ops = {
830 .queue = csi2_queue,
831};
832
833/* -----------------------------------------------------------------------------
834 * V4L2 subdev operations
835 */
836
837static struct v4l2_mbus_framefmt *
f7234138 838__csi2_get_format(struct isp_csi2_device *csi2, struct v4l2_subdev_pad_config *cfg,
121e9f1c
LP		 839 unsigned int pad, enum v4l2_subdev_format_whence which)
840{
841 if (which == V4L2_SUBDEV_FORMAT_TRY)
f7234138 842 return v4l2_subdev_get_try_format(&csi2->subdev, cfg, pad);
121e9f1c
LP		 843 else
844 return &csi2->formats[pad];
845}
846
847static void
f7234138 848csi2_try_format(struct isp_csi2_device *csi2, struct v4l2_subdev_pad_config *cfg,
121e9f1c
LP		 849 unsigned int pad, struct v4l2_mbus_framefmt *fmt,
850 enum v4l2_subdev_format_whence which)
851{
27ffaeb0 852 u32 pixelcode;
121e9f1c
LP		 853 struct v4l2_mbus_framefmt *format;
854 const struct isp_format_info *info;
855 unsigned int i;
856
857 switch (pad) {
858 case CSI2_PAD_SINK:
859 /* Clamp the width and height to valid range (1-8191). */
860 for (i = 0; i < ARRAY_SIZE(csi2_input_fmts); i++) {
861 if (fmt->code == csi2_input_fmts[i])
862 break;
863 }
864
865 /* If not found, use SGRBG10 as default */
866 if (i >= ARRAY_SIZE(csi2_input_fmts))
27ffaeb0 867 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
121e9f1c
LP		 868
869 fmt->width = clamp_t(u32, fmt->width, 1, 8191);
870 fmt->height = clamp_t(u32, fmt->height, 1, 8191);
871 break;
872
873 case CSI2_PAD_SOURCE:
874 /* Source format same as sink format, except for DPCM
875 * compression.
876 */
877 pixelcode = fmt->code;
f7234138 878 format = __csi2_get_format(csi2, cfg, CSI2_PAD_SINK, which);
121e9f1c
LP		 879 memcpy(fmt, format, sizeof(*fmt));
880
881 /*
882 * Only Allow DPCM decompression, and check that the
883 * pattern is preserved
884 */
885 info = omap3isp_video_format_info(fmt->code);
886 if (info->uncompressed == pixelcode)
887 fmt->code = pixelcode;
888 break;
889 }
890
891 /* RGB, non-interlaced */
892 fmt->colorspace = V4L2_COLORSPACE_SRGB;
893 fmt->field = V4L2_FIELD_NONE;
894}
895
896/*
897 * csi2_enum_mbus_code - Handle pixel format enumeration
898 * @sd : pointer to v4l2 subdev structure
f7234138 899 * @cfg: V4L2 subdev pad configuration
121e9f1c
LP		 900 * @code : pointer to v4l2_subdev_mbus_code_enum structure
901 * return -EINVAL or zero on success
902 */
903static int csi2_enum_mbus_code(struct v4l2_subdev *sd,
f7234138 904 struct v4l2_subdev_pad_config *cfg,
121e9f1c
LP		 905 struct v4l2_subdev_mbus_code_enum *code)
906{
907 struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
908 struct v4l2_mbus_framefmt *format;
909 const struct isp_format_info *info;
910
911 if (code->pad == CSI2_PAD_SINK) {
912 if (code->index >= ARRAY_SIZE(csi2_input_fmts))
913 return -EINVAL;
914
915 code->code = csi2_input_fmts[code->index];
916 } else {
f7234138 917 format = __csi2_get_format(csi2, cfg, CSI2_PAD_SINK,
3f1ccf16 918 code->which);
121e9f1c
LP		 919 switch (code->index) {
920 case 0:
921 /* Passthrough sink pad code */
922 code->code = format->code;
923 break;
924 case 1:
925 /* Uncompressed code */
926 info = omap3isp_video_format_info(format->code);
927 if (info->uncompressed == format->code)
928 return -EINVAL;
929
930 code->code = info->uncompressed;
931 break;
932 default:
933 return -EINVAL;
934 }
935 }
936
937 return 0;
938}
939
940static int csi2_enum_frame_size(struct v4l2_subdev *sd,
f7234138 941 struct v4l2_subdev_pad_config *cfg,
121e9f1c
LP		 942 struct v4l2_subdev_frame_size_enum *fse)
943{
944 struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
945 struct v4l2_mbus_framefmt format;
946
947 if (fse->index != 0)
948 return -EINVAL;
949
950 format.code = fse->code;
951 format.width = 1;
952 format.height = 1;
5778e749 953 csi2_try_format(csi2, cfg, fse->pad, &format, fse->which);
121e9f1c
LP		 954 fse->min_width = format.width;
955 fse->min_height = format.height;
956
957 if (format.code != fse->code)
958 return -EINVAL;
959
960 format.code = fse->code;
961 format.width = -1;
962 format.height = -1;
5778e749 963 csi2_try_format(csi2, cfg, fse->pad, &format, fse->which);
121e9f1c
LP		 964 fse->max_width = format.width;
965 fse->max_height = format.height;
966
967 return 0;
968}
969
970/*
971 * csi2_get_format - Handle get format by pads subdev method
972 * @sd : pointer to v4l2 subdev structure
f7234138 973 * @cfg: V4L2 subdev pad configuration
121e9f1c 974 * @fmt: pointer to v4l2 subdev format structure
25985edc 975 * return -EINVAL or zero on success
121e9f1c 976 */
f7234138 977static int csi2_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
121e9f1c
LP		 978 struct v4l2_subdev_format *fmt)
979{
980 struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
981 struct v4l2_mbus_framefmt *format;
982
f7234138 983 format = __csi2_get_format(csi2, cfg, fmt->pad, fmt->which);
121e9f1c
LP		 984 if (format == NULL)
985 return -EINVAL;
986
987 fmt->format = *format;
988 return 0;
989}
990
991/*
992 * csi2_set_format - Handle set format by pads subdev method
993 * @sd : pointer to v4l2 subdev structure
f7234138 994 * @cfg: V4L2 subdev pad configuration
121e9f1c
LP		 995 * @fmt: pointer to v4l2 subdev format structure
996 * return -EINVAL or zero on success
997 */
f7234138 998static int csi2_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
121e9f1c
LP		 999 struct v4l2_subdev_format *fmt)
1000{
1001 struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
1002 struct v4l2_mbus_framefmt *format;
1003
f7234138 1004 format = __csi2_get_format(csi2, cfg, fmt->pad, fmt->which);
121e9f1c
LP		 1005 if (format == NULL)
1006 return -EINVAL;
1007
f7234138 1008 csi2_try_format(csi2, cfg, fmt->pad, &fmt->format, fmt->which);
121e9f1c
LP		 1009 *format = fmt->format;
1010
1011 /* Propagate the format from sink to source */
1012 if (fmt->pad == CSI2_PAD_SINK) {
f7234138 1013 format = __csi2_get_format(csi2, cfg, CSI2_PAD_SOURCE,
121e9f1c
LP		 1014 fmt->which);
1015 *format = fmt->format;
f7234138 1016 csi2_try_format(csi2, cfg, CSI2_PAD_SOURCE, format, fmt->which);
121e9f1c
LP		 1017 }
1018
1019 return 0;
1020}
1021
1022/*
1023 * csi2_init_formats - Initialize formats on all pads
1024 * @sd: ISP CSI2 V4L2 subdevice
1025 * @fh: V4L2 subdev file handle
1026 *
1027 * Initialize all pad formats with default values. If fh is not NULL, try
1028 * formats are initialized on the file handle. Otherwise active formats are
1029 * initialized on the device.
1030 */
1031static int csi2_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1032{
1033 struct v4l2_subdev_format format;
1034
1035 memset(&format, 0, sizeof(format));
1036 format.pad = CSI2_PAD_SINK;
1037 format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
27ffaeb0 1038 format.format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
121e9f1c
LP		 1039 format.format.width = 4096;
1040 format.format.height = 4096;
f7234138 1041 csi2_set_format(sd, fh ? fh->pad : NULL, &format);
121e9f1c
LP		 1042
1043 return 0;
1044}
1045
1046/*
1047 * csi2_set_stream - Enable/Disable streaming on the CSI2 module
1048 * @sd: ISP CSI2 V4L2 subdevice
1049 * @enable: ISP pipeline stream state
1050 *
1051 * Return 0 on success or a negative error code otherwise.
1052 */
1053static int csi2_set_stream(struct v4l2_subdev *sd, int enable)
1054{
1055 struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
1056 struct isp_device *isp = csi2->isp;
121e9f1c
LP		 1057 struct isp_video *video_out = &csi2->video_out;
1058
1059 switch (enable) {
1060 case ISP_PIPELINE_STREAM_CONTINUOUS:
1061 if (omap3isp_csiphy_acquire(csi2->phy) < 0)
1062 return -ENODEV;
121e9f1c
LP		 1063 if (csi2->output & CSI2_OUTPUT_MEMORY)
1064 omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_CSI2A_WRITE);
1065 csi2_configure(csi2);
1066 csi2_print_status(csi2);
1067
1068 /*
1069 * When outputting to memory with no buffer available, let the
1070 * buffer queue handler start the hardware. A DMA queue flag
1071 * ISP_VIDEO_DMAQUEUE_QUEUED will be set as soon as there is
1072 * a buffer available.
1073 */
1074 if (csi2->output & CSI2_OUTPUT_MEMORY &&
1075 !(video_out->dmaqueue_flags & ISP_VIDEO_DMAQUEUE_QUEUED))
1076 break;
1077 /* Enable context 0 and IRQs */
1078 atomic_set(&csi2->stopping, 0);
1079 csi2_ctx_enable(isp, csi2, 0, 1);
1080 csi2_if_enable(isp, csi2, 1);
1081 isp_video_dmaqueue_flags_clr(video_out);
1082 break;
1083
1084 case ISP_PIPELINE_STREAM_STOPPED:
1085 if (csi2->state == ISP_PIPELINE_STREAM_STOPPED)
1086 return 0;
1087 if (omap3isp_module_sync_idle(&sd->entity, &csi2->wait,
1088 &csi2->stopping))
1089 dev_dbg(isp->dev, "%s: module stop timeout.\n",
1090 sd->name);
1091 csi2_ctx_enable(isp, csi2, 0, 0);
1092 csi2_if_enable(isp, csi2, 0);
1093 csi2_irq_ctx_set(isp, csi2, 0);
1094 omap3isp_csiphy_release(csi2->phy);
1095 isp_video_dmaqueue_flags_clr(video_out);
1096 omap3isp_sbl_disable(isp, OMAP3_ISP_SBL_CSI2A_WRITE);
1097 break;
1098 }
1099
1100 csi2->state = enable;
1101 return 0;
1102}
1103
1104/* subdev video operations */
1105static const struct v4l2_subdev_video_ops csi2_video_ops = {
1106 .s_stream = csi2_set_stream,
1107};
1108
1109/* subdev pad operations */
1110static const struct v4l2_subdev_pad_ops csi2_pad_ops = {
1111 .enum_mbus_code = csi2_enum_mbus_code,
1112 .enum_frame_size = csi2_enum_frame_size,
1113 .get_fmt = csi2_get_format,
1114 .set_fmt = csi2_set_format,
1115};
1116
1117/* subdev operations */
1118static const struct v4l2_subdev_ops csi2_ops = {
1119 .video = &csi2_video_ops,
1120 .pad = &csi2_pad_ops,
1121};
1122
1123/* subdev internal operations */
1124static const struct v4l2_subdev_internal_ops csi2_internal_ops = {
1125 .open = csi2_init_formats,
1126};
1127
1128/* -----------------------------------------------------------------------------
1129 * Media entity operations
1130 */
1131
1132/*
1133 * csi2_link_setup - Setup CSI2 connections.
1134 * @entity : Pointer to media entity structure
1135 * @local : Pointer to local pad array
1136 * @remote : Pointer to remote pad array
1137 * @flags : Link flags
1138 * return -EINVAL or zero on success
1139 */
1140static int csi2_link_setup(struct media_entity *entity,
1141 const struct media_pad *local,
1142 const struct media_pad *remote, u32 flags)
1143{
1144 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
1145 struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
1146 struct isp_csi2_ctrl_cfg *ctrl = &csi2->ctrl;
1147
1148 /*
1149 * The ISP core doesn't support pipelines with multiple video outputs.
1150 * Revisit this when it will be implemented, and return -EBUSY for now.
1151 */
1152
1153 switch (local->index | media_entity_type(remote->entity)) {
1154 case CSI2_PAD_SOURCE | MEDIA_ENT_T_DEVNODE:
1155 if (flags & MEDIA_LNK_FL_ENABLED) {
1156 if (csi2->output & ~CSI2_OUTPUT_MEMORY)
1157 return -EBUSY;
1158 csi2->output |= CSI2_OUTPUT_MEMORY;
1159 } else {
1160 csi2->output &= ~CSI2_OUTPUT_MEMORY;
1161 }
1162 break;
1163
1164 case CSI2_PAD_SOURCE | MEDIA_ENT_T_V4L2_SUBDEV:
1165 if (flags & MEDIA_LNK_FL_ENABLED) {
1166 if (csi2->output & ~CSI2_OUTPUT_CCDC)
1167 return -EBUSY;
1168 csi2->output |= CSI2_OUTPUT_CCDC;
1169 } else {
1170 csi2->output &= ~CSI2_OUTPUT_CCDC;
1171 }
1172 break;
1173
1174 default:
1175 /* Link from camera to CSI2 is fixed... */
1176 return -EINVAL;
1177 }
1178
1179 ctrl->vp_only_enable =
1180 (csi2->output & CSI2_OUTPUT_MEMORY) ? false : true;
1181 ctrl->vp_clk_enable = !!(csi2->output & CSI2_OUTPUT_CCDC);
1182
1183 return 0;
1184}
1185
1186/* media operations */
1187static const struct media_entity_operations csi2_media_ops = {
1188 .link_setup = csi2_link_setup,
20d4ab7b 1189 .link_validate = v4l2_subdev_link_validate,
121e9f1c
LP		 1190};
1191
39099d09
LP		 1192void omap3isp_csi2_unregister_entities(struct isp_csi2_device *csi2)
1193{
1194 v4l2_device_unregister_subdev(&csi2->subdev);
1195 omap3isp_video_unregister(&csi2->video_out);
1196}
1197
1198int omap3isp_csi2_register_entities(struct isp_csi2_device *csi2,
1199 struct v4l2_device *vdev)
1200{
1201 int ret;
1202
1203 /* Register the subdev and video nodes. */
1204 ret = v4l2_device_register_subdev(vdev, &csi2->subdev);
1205 if (ret < 0)
1206 goto error;
1207
1208 ret = omap3isp_video_register(&csi2->video_out, vdev);
1209 if (ret < 0)
1210 goto error;
1211
1212 return 0;
1213
1214error:
1215 omap3isp_csi2_unregister_entities(csi2);
1216 return ret;
1217}
1218
1219/* -----------------------------------------------------------------------------
1220 * ISP CSI2 initialisation and cleanup
1221 */
1222
121e9f1c
LP		 1223/*
1224 * csi2_init_entities - Initialize subdev and media entity.
1225 * @csi2: Pointer to csi2 structure.
1226 * return -ENOMEM or zero on success
1227 */
1228static int csi2_init_entities(struct isp_csi2_device *csi2)
1229{
1230 struct v4l2_subdev *sd = &csi2->subdev;
1231 struct media_pad *pads = csi2->pads;
1232 struct media_entity *me = &sd->entity;
1233 int ret;
1234
1235 v4l2_subdev_init(sd, &csi2_ops);
1236 sd->internal_ops = &csi2_internal_ops;
1237 strlcpy(sd->name, "OMAP3 ISP CSI2a", sizeof(sd->name));
1238
1239 sd->grp_id = 1 << 16; /* group ID for isp subdevs */
1240 v4l2_set_subdevdata(sd, csi2);
1241 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1242
1243 pads[CSI2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
8dad936a
SA		 1244 pads[CSI2_PAD_SINK].flags = MEDIA_PAD_FL_SINK
1245 | MEDIA_PAD_FL_MUST_CONNECT;
121e9f1c
LP		 1246
1247 me->ops = &csi2_media_ops;
18095107 1248 ret = media_entity_init(me, CSI2_PADS_NUM, pads);
121e9f1c
LP		 1249 if (ret < 0)
1250 return ret;
1251
1252 csi2_init_formats(sd, NULL);
1253
1254 /* Video device node */
1255 csi2->video_out.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1256 csi2->video_out.ops = &csi2_ispvideo_ops;
1257 csi2->video_out.bpl_alignment = 32;
1258 csi2->video_out.bpl_zero_padding = 1;
1259 csi2->video_out.bpl_max = 0x1ffe0;
1260 csi2->video_out.isp = csi2->isp;
1261 csi2->video_out.capture_mem = PAGE_ALIGN(4096 * 4096) * 3;
1262
1263 ret = omap3isp_video_init(&csi2->video_out, "CSI2a");
1264 if (ret < 0)
9b6390bd 1265 goto error_video;
121e9f1c
LP		 1266
1267 /* Connect the CSI2 subdev to the video node. */
1268 ret = media_entity_create_link(&csi2->subdev.entity, CSI2_PAD_SOURCE,
1269 &csi2->video_out.video.entity, 0, 0);
1270 if (ret < 0)
9b6390bd 1271 goto error_link;
121e9f1c
LP		 1272
1273 return 0;
9b6390bd
LP		 1274
1275error_link:
1276 omap3isp_video_cleanup(&csi2->video_out);
1277error_video:
1278 media_entity_cleanup(&csi2->subdev.entity);
1279 return ret;
121e9f1c
LP		 1280}
1281
121e9f1c
LP		 1282/*
1283 * omap3isp_csi2_init - Routine for module driver init
1284 */
1285int omap3isp_csi2_init(struct isp_device *isp)
1286{
1287 struct isp_csi2_device *csi2a = &isp->isp_csi2a;
1288 struct isp_csi2_device *csi2c = &isp->isp_csi2c;
1289 int ret;
1290
1291 csi2a->isp = isp;
1292 csi2a->available = 1;
1293 csi2a->regs1 = OMAP3_ISP_IOMEM_CSI2A_REGS1;
1294 csi2a->regs2 = OMAP3_ISP_IOMEM_CSI2A_REGS2;
1295 csi2a->phy = &isp->isp_csiphy2;
1296 csi2a->state = ISP_PIPELINE_STREAM_STOPPED;
1297 init_waitqueue_head(&csi2a->wait);
1298
1299 ret = csi2_init_entities(csi2a);
1300 if (ret < 0)
9b6390bd 1301 return ret;
121e9f1c
LP		 1302
1303 if (isp->revision == ISP_REVISION_15_0) {
1304 csi2c->isp = isp;
1305 csi2c->available = 1;
1306 csi2c->regs1 = OMAP3_ISP_IOMEM_CSI2C_REGS1;
1307 csi2c->regs2 = OMAP3_ISP_IOMEM_CSI2C_REGS2;
1308 csi2c->phy = &isp->isp_csiphy1;
1309 csi2c->state = ISP_PIPELINE_STREAM_STOPPED;
1310 init_waitqueue_head(&csi2c->wait);
1311 }
1312
1313 return 0;
121e9f1c 1314}
39099d09
LP		 1315
1316/*
1317 * omap3isp_csi2_cleanup - Routine for module driver cleanup
1318 */
1319void omap3isp_csi2_cleanup(struct isp_device *isp)
1320{
1321 struct isp_csi2_device *csi2a = &isp->isp_csi2a;
1322
1323 omap3isp_video_cleanup(&csi2a->video_out);
1324 media_entity_cleanup(&csi2a->subdev.entity);
1325}
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