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[mirror_ubuntu-hirsute-kernel.git] / drivers / media / platform / omap3isp / ispcsi2.c
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d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
121e9f1c
LP		 2/*
3 * ispcsi2.c
4 *
5 * TI OMAP3 ISP - CSI2 module
6 *
7 * Copyright (C) 2010 Nokia Corporation
8 * Copyright (C) 2009 Texas Instruments, Inc.
9 *
10 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
11 * Sakari Ailus <sakari.ailus@iki.fi>
121e9f1c
LP		 12 */
13#include <linux/delay.h>
14#include <media/v4l2-common.h>
15#include <linux/v4l2-mediabus.h>
16#include <linux/mm.h>
17
18#include "isp.h"
19#include "ispreg.h"
20#include "ispcsi2.h"
21
22/*
23 * csi2_if_enable - Enable CSI2 Receiver interface.
24 * @enable: enable flag
25 *
26 */
27static void csi2_if_enable(struct isp_device *isp,
28 struct isp_csi2_device *csi2, u8 enable)
29{
30 struct isp_csi2_ctrl_cfg *currctrl = &csi2->ctrl;
31
32 isp_reg_clr_set(isp, csi2->regs1, ISPCSI2_CTRL, ISPCSI2_CTRL_IF_EN,
33 enable ? ISPCSI2_CTRL_IF_EN : 0);
34
35 currctrl->if_enable = enable;
36}
37
38/*
39 * csi2_recv_config - CSI2 receiver module configuration.
40 * @currctrl: isp_csi2_ctrl_cfg structure
41 *
42 */
43static void csi2_recv_config(struct isp_device *isp,
44 struct isp_csi2_device *csi2,
45 struct isp_csi2_ctrl_cfg *currctrl)
46{
47 u32 reg;
48
49 reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTRL);
50
51 if (currctrl->frame_mode)
52 reg |= ISPCSI2_CTRL_FRAME;
53 else
54 reg &= ~ISPCSI2_CTRL_FRAME;
55
56 if (currctrl->vp_clk_enable)
57 reg |= ISPCSI2_CTRL_VP_CLK_EN;
58 else
59 reg &= ~ISPCSI2_CTRL_VP_CLK_EN;
60
61 if (currctrl->vp_only_enable)
62 reg |= ISPCSI2_CTRL_VP_ONLY_EN;
63 else
64 reg &= ~ISPCSI2_CTRL_VP_ONLY_EN;
65
66 reg &= ~ISPCSI2_CTRL_VP_OUT_CTRL_MASK;
67 reg |= currctrl->vp_out_ctrl << ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT;
68
69 if (currctrl->ecc_enable)
70 reg |= ISPCSI2_CTRL_ECC_EN;
71 else
72 reg &= ~ISPCSI2_CTRL_ECC_EN;
73
74 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTRL);
75}
76
77static const unsigned int csi2_input_fmts[] = {
27ffaeb0
BB		 78 MEDIA_BUS_FMT_SGRBG10_1X10,
79 MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
80 MEDIA_BUS_FMT_SRGGB10_1X10,
81 MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8,
82 MEDIA_BUS_FMT_SBGGR10_1X10,
83 MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8,
84 MEDIA_BUS_FMT_SGBRG10_1X10,
85 MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8,
86 MEDIA_BUS_FMT_YUYV8_2X8,
121e9f1c
LP		 87};
88
89/* To set the format on the CSI2 requires a mapping function that takes
90 * the following inputs:
73cdc79f 91 * - 3 different formats (at this time)
121e9f1c
LP		 92 * - 2 destinations (mem, vp+mem) (vp only handled separately)
93 * - 2 decompression options (on, off)
94 * - 2 isp revisions (certain format must be handled differently on OMAP3630)
95 * Output should be CSI2 frame format code
96 * Array indices as follows: [format][dest][decompr][is_3630]
97 * Not all combinations are valid. 0 means invalid.
98 */
73cdc79f 99static const u16 __csi2_fmt_map[3][2][2][2] = {
121e9f1c
LP		 100 /* RAW10 formats */
101 {
102 /* Output to memory */
103 {
104 /* No DPCM decompression */
105 { CSI2_PIX_FMT_RAW10_EXP16, CSI2_PIX_FMT_RAW10_EXP16 },
106 /* DPCM decompression */
107 { 0, 0 },
108 },
109 /* Output to both */
110 {
111 /* No DPCM decompression */
112 { CSI2_PIX_FMT_RAW10_EXP16_VP,
113 CSI2_PIX_FMT_RAW10_EXP16_VP },
114 /* DPCM decompression */
115 { 0, 0 },
116 },
117 },
118 /* RAW10 DPCM8 formats */
119 {
120 /* Output to memory */
121 {
122 /* No DPCM decompression */
123 { CSI2_PIX_FMT_RAW8, CSI2_USERDEF_8BIT_DATA1 },
124 /* DPCM decompression */
125 { CSI2_PIX_FMT_RAW8_DPCM10_EXP16,
126 CSI2_USERDEF_8BIT_DATA1_DPCM10 },
127 },
128 /* Output to both */
129 {
130 /* No DPCM decompression */
131 { CSI2_PIX_FMT_RAW8_VP,
132 CSI2_PIX_FMT_RAW8_VP },
133 /* DPCM decompression */
134 { CSI2_PIX_FMT_RAW8_DPCM10_VP,
135 CSI2_USERDEF_8BIT_DATA1_DPCM10_VP },
136 },
137 },
73cdc79f
IP		 138 /* YUYV8 2X8 formats */
139 {
140 /* Output to memory */
141 {
142 /* No DPCM decompression */
143 { CSI2_PIX_FMT_YUV422_8BIT,
144 CSI2_PIX_FMT_YUV422_8BIT },
145 /* DPCM decompression */
146 { 0, 0 },
147 },
148 /* Output to both */
149 {
150 /* No DPCM decompression */
151 { CSI2_PIX_FMT_YUV422_8BIT_VP,
152 CSI2_PIX_FMT_YUV422_8BIT_VP },
153 /* DPCM decompression */
154 { 0, 0 },
155 },
156 },
121e9f1c
LP		 157};
158
159/*
160 * csi2_ctx_map_format - Map CSI2 sink media bus format to CSI2 format ID
161 * @csi2: ISP CSI2 device
162 *
163 * Returns CSI2 physical format id
164 */
165static u16 csi2_ctx_map_format(struct isp_csi2_device *csi2)
166{
167 const struct v4l2_mbus_framefmt *fmt = &csi2->formats[CSI2_PAD_SINK];
168 int fmtidx, destidx, is_3630;
169
170 switch (fmt->code) {
27ffaeb0
BB		 171 case MEDIA_BUS_FMT_SGRBG10_1X10:
172 case MEDIA_BUS_FMT_SRGGB10_1X10:
173 case MEDIA_BUS_FMT_SBGGR10_1X10:
174 case MEDIA_BUS_FMT_SGBRG10_1X10:
121e9f1c
LP		 175 fmtidx = 0;
176 break;
27ffaeb0
BB		 177 case MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8:
178 case MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8:
179 case MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8:
180 case MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8:
121e9f1c
LP		 181 fmtidx = 1;
182 break;
27ffaeb0 183 case MEDIA_BUS_FMT_YUYV8_2X8:
73cdc79f
IP		 184 fmtidx = 2;
185 break;
121e9f1c
LP		 186 default:
187 WARN(1, KERN_ERR "CSI2: pixel format %08x unsupported!\n",
188 fmt->code);
189 return 0;
190 }
191
192 if (!(csi2->output & CSI2_OUTPUT_CCDC) &&
193 !(csi2->output & CSI2_OUTPUT_MEMORY)) {
194 /* Neither output enabled is a valid combination */
195 return CSI2_PIX_FMT_OTHERS;
196 }
197
198 /* If we need to skip frames at the beginning of the stream disable the
199 * video port to avoid sending the skipped frames to the CCDC.
200 */
201 destidx = csi2->frame_skip ? 0 : !!(csi2->output & CSI2_OUTPUT_CCDC);
202 is_3630 = csi2->isp->revision == ISP_REVISION_15_0;
203
204 return __csi2_fmt_map[fmtidx][destidx][csi2->dpcm_decompress][is_3630];
205}
206
207/*
208 * csi2_set_outaddr - Set memory address to save output image
209 * @csi2: Pointer to ISP CSI2a device.
210 * @addr: ISP MMU Mapped 32-bit memory address aligned on 32 byte boundary.
211 *
212 * Sets the memory address where the output will be saved.
213 *
214 * Returns 0 if successful, or -EINVAL if the address is not in the 32 byte
215 * boundary.
216 */
217static void csi2_set_outaddr(struct isp_csi2_device *csi2, u32 addr)
218{
219 struct isp_device *isp = csi2->isp;
220 struct isp_csi2_ctx_cfg *ctx = &csi2->contexts[0];
221
222 ctx->ping_addr = addr;
223 ctx->pong_addr = addr;
224 isp_reg_writel(isp, ctx->ping_addr,
225 csi2->regs1, ISPCSI2_CTX_DAT_PING_ADDR(ctx->ctxnum));
226 isp_reg_writel(isp, ctx->pong_addr,
227 csi2->regs1, ISPCSI2_CTX_DAT_PONG_ADDR(ctx->ctxnum));
228}
229
230/*
231 * is_usr_def_mapping - Checks whether USER_DEF_MAPPING should
232 * be enabled by CSI2.
233 * @format_id: mapped format id
234 *
235 */
236static inline int is_usr_def_mapping(u32 format_id)
237{
238 return (format_id & 0x40) ? 1 : 0;
239}
240
241/*
242 * csi2_ctx_enable - Enable specified CSI2 context
243 * @ctxnum: Context number, valid between 0 and 7 values.
244 * @enable: enable
245 *
246 */
247static void csi2_ctx_enable(struct isp_device *isp,
248 struct isp_csi2_device *csi2, u8 ctxnum, u8 enable)
249{
250 struct isp_csi2_ctx_cfg *ctx = &csi2->contexts[ctxnum];
251 unsigned int skip = 0;
252 u32 reg;
253
254 reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL1(ctxnum));
255
256 if (enable) {
257 if (csi2->frame_skip)
258 skip = csi2->frame_skip;
259 else if (csi2->output & CSI2_OUTPUT_MEMORY)
260 skip = 1;
261
262 reg &= ~ISPCSI2_CTX_CTRL1_COUNT_MASK;
263 reg |= ISPCSI2_CTX_CTRL1_COUNT_UNLOCK
264 | (skip << ISPCSI2_CTX_CTRL1_COUNT_SHIFT)
265 | ISPCSI2_CTX_CTRL1_CTX_EN;
266 } else {
267 reg &= ~ISPCSI2_CTX_CTRL1_CTX_EN;
268 }
269
270 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL1(ctxnum));
271 ctx->enabled = enable;
272}
273
274/*
275 * csi2_ctx_config - CSI2 context configuration.
276 * @ctx: context configuration
277 *
278 */
279static void csi2_ctx_config(struct isp_device *isp,
280 struct isp_csi2_device *csi2,
281 struct isp_csi2_ctx_cfg *ctx)
282{
283 u32 reg;
284
285 /* Set up CSI2_CTx_CTRL1 */
286 reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL1(ctx->ctxnum));
287
288 if (ctx->eof_enabled)
289 reg |= ISPCSI2_CTX_CTRL1_EOF_EN;
290 else
291 reg &= ~ISPCSI2_CTX_CTRL1_EOF_EN;
292
293 if (ctx->eol_enabled)
294 reg |= ISPCSI2_CTX_CTRL1_EOL_EN;
295 else
296 reg &= ~ISPCSI2_CTX_CTRL1_EOL_EN;
297
298 if (ctx->checksum_enabled)
299 reg |= ISPCSI2_CTX_CTRL1_CS_EN;
300 else
301 reg &= ~ISPCSI2_CTX_CTRL1_CS_EN;
302
303 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL1(ctx->ctxnum));
304
305 /* Set up CSI2_CTx_CTRL2 */
306 reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL2(ctx->ctxnum));
307
308 reg &= ~(ISPCSI2_CTX_CTRL2_VIRTUAL_ID_MASK);
309 reg |= ctx->virtual_id << ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT;
310
311 reg &= ~(ISPCSI2_CTX_CTRL2_FORMAT_MASK);
312 reg |= ctx->format_id << ISPCSI2_CTX_CTRL2_FORMAT_SHIFT;
313
314 if (ctx->dpcm_decompress) {
315 if (ctx->dpcm_predictor)
316 reg |= ISPCSI2_CTX_CTRL2_DPCM_PRED;
317 else
318 reg &= ~ISPCSI2_CTX_CTRL2_DPCM_PRED;
319 }
320
321 if (is_usr_def_mapping(ctx->format_id)) {
322 reg &= ~ISPCSI2_CTX_CTRL2_USER_DEF_MAP_MASK;
323 reg |= 2 << ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT;
324 }
325
326 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL2(ctx->ctxnum));
327
328 /* Set up CSI2_CTx_CTRL3 */
329 reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL3(ctx->ctxnum));
330 reg &= ~(ISPCSI2_CTX_CTRL3_ALPHA_MASK);
331 reg |= (ctx->alpha << ISPCSI2_CTX_CTRL3_ALPHA_SHIFT);
332
333 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL3(ctx->ctxnum));
334
335 /* Set up CSI2_CTx_DAT_OFST */
336 reg = isp_reg_readl(isp, csi2->regs1,
337 ISPCSI2_CTX_DAT_OFST(ctx->ctxnum));
338 reg &= ~ISPCSI2_CTX_DAT_OFST_OFST_MASK;
339 reg |= ctx->data_offset << ISPCSI2_CTX_DAT_OFST_OFST_SHIFT;
340 isp_reg_writel(isp, reg, csi2->regs1,
341 ISPCSI2_CTX_DAT_OFST(ctx->ctxnum));
342
343 isp_reg_writel(isp, ctx->ping_addr,
344 csi2->regs1, ISPCSI2_CTX_DAT_PING_ADDR(ctx->ctxnum));
345
346 isp_reg_writel(isp, ctx->pong_addr,
347 csi2->regs1, ISPCSI2_CTX_DAT_PONG_ADDR(ctx->ctxnum));
348}
349
350/*
351 * csi2_timing_config - CSI2 timing configuration.
352 * @timing: csi2_timing_cfg structure
353 */
354static void csi2_timing_config(struct isp_device *isp,
355 struct isp_csi2_device *csi2,
356 struct isp_csi2_timing_cfg *timing)
357{
358 u32 reg;
359
360 reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_TIMING);
361
362 if (timing->force_rx_mode)
363 reg |= ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing->ionum);
364 else
365 reg &= ~ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing->ionum);
366
367 if (timing->stop_state_16x)
368 reg |= ISPCSI2_TIMING_STOP_STATE_X16_IO(timing->ionum);
369 else
370 reg &= ~ISPCSI2_TIMING_STOP_STATE_X16_IO(timing->ionum);
371
372 if (timing->stop_state_4x)
373 reg |= ISPCSI2_TIMING_STOP_STATE_X4_IO(timing->ionum);
374 else
375 reg &= ~ISPCSI2_TIMING_STOP_STATE_X4_IO(timing->ionum);
376
377 reg &= ~ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_MASK(timing->ionum);
378 reg |= timing->stop_state_counter <<
379 ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(timing->ionum);
380
381 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_TIMING);
382}
383
384/*
385 * csi2_irq_ctx_set - Enables CSI2 Context IRQs.
386 * @enable: Enable/disable CSI2 Context interrupts
387 */
388static void csi2_irq_ctx_set(struct isp_device *isp,
389 struct isp_csi2_device *csi2, int enable)
390{
121e9f1c
LP		 391 int i;
392
121e9f1c 393 for (i = 0; i < 8; i++) {
b43883d6 394 isp_reg_writel(isp, ISPCSI2_CTX_IRQSTATUS_FE_IRQ, csi2->regs1,
121e9f1c
LP		 395 ISPCSI2_CTX_IRQSTATUS(i));
396 if (enable)
397 isp_reg_set(isp, csi2->regs1, ISPCSI2_CTX_IRQENABLE(i),
b43883d6 398 ISPCSI2_CTX_IRQSTATUS_FE_IRQ);
121e9f1c
LP		 399 else
400 isp_reg_clr(isp, csi2->regs1, ISPCSI2_CTX_IRQENABLE(i),
b43883d6 401 ISPCSI2_CTX_IRQSTATUS_FE_IRQ);
121e9f1c
LP		 402 }
403}
404
405/*
406 * csi2_irq_complexio1_set - Enables CSI2 ComplexIO IRQs.
407 * @enable: Enable/disable CSI2 ComplexIO #1 interrupts
408 */
409static void csi2_irq_complexio1_set(struct isp_device *isp,
410 struct isp_csi2_device *csi2, int enable)
411{
412 u32 reg;
413 reg = ISPCSI2_PHY_IRQENABLE_STATEALLULPMEXIT |
414 ISPCSI2_PHY_IRQENABLE_STATEALLULPMENTER |
415 ISPCSI2_PHY_IRQENABLE_STATEULPM5 |
416 ISPCSI2_PHY_IRQENABLE_ERRCONTROL5 |
417 ISPCSI2_PHY_IRQENABLE_ERRESC5 |
418 ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS5 |
419 ISPCSI2_PHY_IRQENABLE_ERRSOTHS5 |
420 ISPCSI2_PHY_IRQENABLE_STATEULPM4 |
421 ISPCSI2_PHY_IRQENABLE_ERRCONTROL4 |
422 ISPCSI2_PHY_IRQENABLE_ERRESC4 |
423 ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS4 |
424 ISPCSI2_PHY_IRQENABLE_ERRSOTHS4 |
425 ISPCSI2_PHY_IRQENABLE_STATEULPM3 |
426 ISPCSI2_PHY_IRQENABLE_ERRCONTROL3 |
427 ISPCSI2_PHY_IRQENABLE_ERRESC3 |
428 ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS3 |
429 ISPCSI2_PHY_IRQENABLE_ERRSOTHS3 |
430 ISPCSI2_PHY_IRQENABLE_STATEULPM2 |
431 ISPCSI2_PHY_IRQENABLE_ERRCONTROL2 |
432 ISPCSI2_PHY_IRQENABLE_ERRESC2 |
433 ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS2 |
434 ISPCSI2_PHY_IRQENABLE_ERRSOTHS2 |
435 ISPCSI2_PHY_IRQENABLE_STATEULPM1 |
436 ISPCSI2_PHY_IRQENABLE_ERRCONTROL1 |
437 ISPCSI2_PHY_IRQENABLE_ERRESC1 |
438 ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS1 |
439 ISPCSI2_PHY_IRQENABLE_ERRSOTHS1;
440 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_PHY_IRQSTATUS);
441 if (enable)
442 reg |= isp_reg_readl(isp, csi2->regs1, ISPCSI2_PHY_IRQENABLE);
443 else
444 reg = 0;
445 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_PHY_IRQENABLE);
446}
447
448/*
449 * csi2_irq_status_set - Enables CSI2 Status IRQs.
450 * @enable: Enable/disable CSI2 Status interrupts
451 */
452static void csi2_irq_status_set(struct isp_device *isp,
453 struct isp_csi2_device *csi2, int enable)
454{
455 u32 reg;
456 reg = ISPCSI2_IRQSTATUS_OCP_ERR_IRQ |
457 ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ |
458 ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ |
459 ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ |
460 ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ |
461 ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ |
462 ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ |
463 ISPCSI2_IRQSTATUS_CONTEXT(0);
464 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_IRQSTATUS);
465 if (enable)
466 reg |= isp_reg_readl(isp, csi2->regs1, ISPCSI2_IRQENABLE);
467 else
468 reg = 0;
469
470 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_IRQENABLE);
471}
472
473/*
474 * omap3isp_csi2_reset - Resets the CSI2 module.
475 *
476 * Must be called with the phy lock held.
477 *
478 * Returns 0 if successful, or -EBUSY if power command didn't respond.
479 */
480int omap3isp_csi2_reset(struct isp_csi2_device *csi2)
481{
482 struct isp_device *isp = csi2->isp;
483 u8 soft_reset_retries = 0;
484 u32 reg;
485 int i;
486
487 if (!csi2->available)
488 return -ENODEV;
489
7e1db599 490 if (csi2->phy->entity)
121e9f1c
LP		 491 return -EBUSY;
492
493 isp_reg_set(isp, csi2->regs1, ISPCSI2_SYSCONFIG,
494 ISPCSI2_SYSCONFIG_SOFT_RESET);
495
496 do {
497 reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_SYSSTATUS) &
498 ISPCSI2_SYSSTATUS_RESET_DONE;
499 if (reg == ISPCSI2_SYSSTATUS_RESET_DONE)
500 break;
501 soft_reset_retries++;
502 if (soft_reset_retries < 5)
503 udelay(100);
504 } while (soft_reset_retries < 5);
505
506 if (soft_reset_retries == 5) {
4feca39b 507 dev_err(isp->dev, "CSI2: Soft reset try count exceeded!\n");
121e9f1c
LP		 508 return -EBUSY;
509 }
510
511 if (isp->revision == ISP_REVISION_15_0)
512 isp_reg_set(isp, csi2->regs1, ISPCSI2_PHY_CFG,
513 ISPCSI2_PHY_CFG_RESET_CTRL);
514
515 i = 100;
516 do {
517 reg = isp_reg_readl(isp, csi2->phy->phy_regs, ISPCSIPHY_REG1)
518 & ISPCSIPHY_REG1_RESET_DONE_CTRLCLK;
519 if (reg == ISPCSIPHY_REG1_RESET_DONE_CTRLCLK)
520 break;
521 udelay(100);
522 } while (--i > 0);
523
524 if (i == 0) {
4feca39b
LP		 525 dev_err(isp->dev,
526 "CSI2: Reset for CSI2_96M_FCLK domain Failed!\n");
121e9f1c
LP		 527 return -EBUSY;
528 }
529
530 if (isp->autoidle)
531 isp_reg_clr_set(isp, csi2->regs1, ISPCSI2_SYSCONFIG,
532 ISPCSI2_SYSCONFIG_MSTANDBY_MODE_MASK |
533 ISPCSI2_SYSCONFIG_AUTO_IDLE,
534 ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SMART |
535 ((isp->revision == ISP_REVISION_15_0) ?
536 ISPCSI2_SYSCONFIG_AUTO_IDLE : 0));
537 else
538 isp_reg_clr_set(isp, csi2->regs1, ISPCSI2_SYSCONFIG,
539 ISPCSI2_SYSCONFIG_MSTANDBY_MODE_MASK |
540 ISPCSI2_SYSCONFIG_AUTO_IDLE,
541 ISPCSI2_SYSCONFIG_MSTANDBY_MODE_NO);
542
543 return 0;
544}
545
546static int csi2_configure(struct isp_csi2_device *csi2)
547{
6387b752 548 struct isp_pipeline *pipe = to_isp_pipeline(&csi2->subdev.entity);
68908747 549 const struct isp_bus_cfg *buscfg;
121e9f1c
LP		 550 struct isp_device *isp = csi2->isp;
551 struct isp_csi2_timing_cfg *timing = &csi2->timing[0];
552 struct v4l2_subdev *sensor;
553 struct media_pad *pad;
554
555 /*
556 * CSI2 fields that can be updated while the context has
557 * been enabled or the interface has been enabled are not
558 * updated dynamically currently. So we do not allow to
559 * reconfigure if either has been enabled
560 */
561 if (csi2->contexts[0].enabled || csi2->ctrl.if_enable)
562 return -EBUSY;
563
1bddf1b3 564 pad = media_entity_remote_pad(&csi2->pads[CSI2_PAD_SINK]);
121e9f1c 565 sensor = media_entity_to_v4l2_subdev(pad->entity);
02b1ce92 566 buscfg = v4l2_subdev_to_bus_cfg(pipe->external);
121e9f1c
LP		 567
568 csi2->frame_skip = 0;
569 v4l2_subdev_call(sensor, sensor, g_skip_frames, &csi2->frame_skip);
570
6387b752
SA		 571 csi2->ctrl.vp_out_ctrl =
572 clamp_t(unsigned int, pipe->l3_ick / pipe->external_rate - 1,
573 1, 3);
574 dev_dbg(isp->dev, "%s: l3_ick %lu, external_rate %u, vp_out_ctrl %u\n",
575 __func__, pipe->l3_ick, pipe->external_rate,
576 csi2->ctrl.vp_out_ctrl);
121e9f1c 577 csi2->ctrl.frame_mode = ISP_CSI2_FRAME_IMMEDIATE;
68908747 578 csi2->ctrl.ecc_enable = buscfg->bus.csi2.crc;
121e9f1c
LP		 579
580 timing->ionum = 1;
581 timing->force_rx_mode = 1;
582 timing->stop_state_16x = 1;
583 timing->stop_state_4x = 1;
584 timing->stop_state_counter = 0x1FF;
585
586 /*
587 * The CSI2 receiver can't do any format conversion except DPCM
588 * decompression, so every set_format call configures both pads
589 * and enables DPCM decompression as a special case:
590 */
591 if (csi2->formats[CSI2_PAD_SINK].code !=
592 csi2->formats[CSI2_PAD_SOURCE].code)
593 csi2->dpcm_decompress = true;
594 else
595 csi2->dpcm_decompress = false;
596
597 csi2->contexts[0].format_id = csi2_ctx_map_format(csi2);
598
599 if (csi2->video_out.bpl_padding == 0)
600 csi2->contexts[0].data_offset = 0;
601 else
602 csi2->contexts[0].data_offset = csi2->video_out.bpl_value;
603
604 /*
605 * Enable end of frame and end of line signals generation for
606 * context 0. These signals are generated from CSI2 receiver to
607 * qualify the last pixel of a frame and the last pixel of a line.
608 * Without enabling the signals CSI2 receiver writes data to memory
609 * beyond buffer size and/or data line offset is not handled correctly.
610 */
611 csi2->contexts[0].eof_enabled = 1;
612 csi2->contexts[0].eol_enabled = 1;
613
614 csi2_irq_complexio1_set(isp, csi2, 1);
615 csi2_irq_ctx_set(isp, csi2, 1);
616 csi2_irq_status_set(isp, csi2, 1);
617
618 /* Set configuration (timings, format and links) */
619 csi2_timing_config(isp, csi2, timing);
620 csi2_recv_config(isp, csi2, &csi2->ctrl);
621 csi2_ctx_config(isp, csi2, &csi2->contexts[0]);
622
623 return 0;
624}
625
626/*
627 * csi2_print_status - Prints CSI2 debug information.
628 */
629#define CSI2_PRINT_REGISTER(isp, regs, name)\
630 dev_dbg(isp->dev, "###CSI2 " #name "=0x%08x\n", \
631 isp_reg_readl(isp, regs, ISPCSI2_##name))
632
633static void csi2_print_status(struct isp_csi2_device *csi2)
634{
635 struct isp_device *isp = csi2->isp;
636
637 if (!csi2->available)
638 return;
639
640 dev_dbg(isp->dev, "-------------CSI2 Register dump-------------\n");
641
642 CSI2_PRINT_REGISTER(isp, csi2->regs1, SYSCONFIG);
643 CSI2_PRINT_REGISTER(isp, csi2->regs1, SYSSTATUS);
644 CSI2_PRINT_REGISTER(isp, csi2->regs1, IRQENABLE);
645 CSI2_PRINT_REGISTER(isp, csi2->regs1, IRQSTATUS);
646 CSI2_PRINT_REGISTER(isp, csi2->regs1, CTRL);
647 CSI2_PRINT_REGISTER(isp, csi2->regs1, DBG_H);
648 CSI2_PRINT_REGISTER(isp, csi2->regs1, GNQ);
649 CSI2_PRINT_REGISTER(isp, csi2->regs1, PHY_CFG);
650 CSI2_PRINT_REGISTER(isp, csi2->regs1, PHY_IRQSTATUS);
651 CSI2_PRINT_REGISTER(isp, csi2->regs1, SHORT_PACKET);
652 CSI2_PRINT_REGISTER(isp, csi2->regs1, PHY_IRQENABLE);
653 CSI2_PRINT_REGISTER(isp, csi2->regs1, DBG_P);
654 CSI2_PRINT_REGISTER(isp, csi2->regs1, TIMING);
655 CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_CTRL1(0));
656 CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_CTRL2(0));
657 CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_DAT_OFST(0));
658 CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_DAT_PING_ADDR(0));
659 CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_DAT_PONG_ADDR(0));
660 CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_IRQENABLE(0));
661 CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_IRQSTATUS(0));
662 CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_CTRL3(0));
663
664 dev_dbg(isp->dev, "--------------------------------------------\n");
665}
666
667/* -----------------------------------------------------------------------------
668 * Interrupt handling
669 */
670
671/*
672 * csi2_isr_buffer - Does buffer handling at end-of-frame
673 * when writing to memory.
674 */
675static void csi2_isr_buffer(struct isp_csi2_device *csi2)
676{
677 struct isp_device *isp = csi2->isp;
678 struct isp_buffer *buffer;
679
680 csi2_ctx_enable(isp, csi2, 0, 0);
681
875e2e3e 682 buffer = omap3isp_video_buffer_next(&csi2->video_out);
121e9f1c
LP		 683
684 /*
685 * Let video queue operation restart engine if there is an underrun
686 * condition.
687 */
688 if (buffer == NULL)
689 return;
690
21d8582d 691 csi2_set_outaddr(csi2, buffer->dma);
121e9f1c
LP		 692 csi2_ctx_enable(isp, csi2, 0, 1);
693}
694
695static void csi2_isr_ctx(struct isp_csi2_device *csi2,
696 struct isp_csi2_ctx_cfg *ctx)
697{
698 struct isp_device *isp = csi2->isp;
699 unsigned int n = ctx->ctxnum;
700 u32 status;
701
702 status = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_IRQSTATUS(n));
703 isp_reg_writel(isp, status, csi2->regs1, ISPCSI2_CTX_IRQSTATUS(n));
704
121e9f1c
LP		 705 if (!(status & ISPCSI2_CTX_IRQSTATUS_FE_IRQ))
706 return;
707
708 /* Skip interrupts until we reach the frame skip count. The CSI2 will be
709 * automatically disabled, as the frame skip count has been programmed
8b72c18d 710 * in the CSI2_CTx_CTRL1::COUNT field, so re-enable it.
121e9f1c
LP		 711 *
712 * It would have been nice to rely on the FRAME_NUMBER interrupt instead
713 * but it turned out that the interrupt is only generated when the CSI2
714 * writes to memory (the CSI2_CTx_CTRL1::COUNT field is decreased
715 * correctly and reaches 0 when data is forwarded to the video port only
716 * but no interrupt arrives). Maybe a CSI2 hardware bug.
717 */
718 if (csi2->frame_skip) {
719 csi2->frame_skip--;
720 if (csi2->frame_skip == 0) {
721 ctx->format_id = csi2_ctx_map_format(csi2);
722 csi2_ctx_config(isp, csi2, ctx);
723 csi2_ctx_enable(isp, csi2, n, 1);
724 }
725 return;
726 }
727
728 if (csi2->output & CSI2_OUTPUT_MEMORY)
729 csi2_isr_buffer(csi2);
730}
731
732/*
733 * omap3isp_csi2_isr - CSI2 interrupt handling.
121e9f1c 734 */
875e2e3e 735void omap3isp_csi2_isr(struct isp_csi2_device *csi2)
121e9f1c 736{
875e2e3e 737 struct isp_pipeline *pipe = to_isp_pipeline(&csi2->subdev.entity);
121e9f1c
LP		 738 u32 csi2_irqstatus, cpxio1_irqstatus;
739 struct isp_device *isp = csi2->isp;
121e9f1c
LP		 740
741 if (!csi2->available)
875e2e3e 742 return;
121e9f1c
LP		 743
744 csi2_irqstatus = isp_reg_readl(isp, csi2->regs1, ISPCSI2_IRQSTATUS);
745 isp_reg_writel(isp, csi2_irqstatus, csi2->regs1, ISPCSI2_IRQSTATUS);
746
747 /* Failure Cases */
748 if (csi2_irqstatus & ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ) {
749 cpxio1_irqstatus = isp_reg_readl(isp, csi2->regs1,
750 ISPCSI2_PHY_IRQSTATUS);
751 isp_reg_writel(isp, cpxio1_irqstatus,
752 csi2->regs1, ISPCSI2_PHY_IRQSTATUS);
d26da990
MCC		 753 dev_dbg(isp->dev, "CSI2: ComplexIO Error IRQ %x\n",
754 cpxio1_irqstatus);
875e2e3e 755 pipe->error = true;
121e9f1c
LP		 756 }
757
758 if (csi2_irqstatus & (ISPCSI2_IRQSTATUS_OCP_ERR_IRQ |
759 ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ |
760 ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ |
761 ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ |
762 ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ)) {
d26da990
MCC		 763 dev_dbg(isp->dev,
764 "CSI2 Err: OCP:%d, Short_pack:%d, ECC:%d, CPXIO2:%d, FIFO_OVF:%d,\n",
121e9f1c
LP		 765 (csi2_irqstatus &
766 ISPCSI2_IRQSTATUS_OCP_ERR_IRQ) ? 1 : 0,
767 (csi2_irqstatus &
768 ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ) ? 1 : 0,
769 (csi2_irqstatus &
770 ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ) ? 1 : 0,
771 (csi2_irqstatus &
772 ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ) ? 1 : 0,
773 (csi2_irqstatus &
774 ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ) ? 1 : 0);
875e2e3e 775 pipe->error = true;
121e9f1c
LP		 776 }
777
778 if (omap3isp_module_sync_is_stopping(&csi2->wait, &csi2->stopping))
875e2e3e 779 return;
121e9f1c
LP		 780
781 /* Successful cases */
782 if (csi2_irqstatus & ISPCSI2_IRQSTATUS_CONTEXT(0))
783 csi2_isr_ctx(csi2, &csi2->contexts[0]);
784
785 if (csi2_irqstatus & ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ)
786 dev_dbg(isp->dev, "CSI2: ECC correction done\n");
121e9f1c
LP		 787}
788
789/* -----------------------------------------------------------------------------
790 * ISP video operations
791 */
792
793/*
794 * csi2_queue - Queues the first buffer when using memory output
795 * @video: The video node
796 * @buffer: buffer to queue
797 */
798static int csi2_queue(struct isp_video *video, struct isp_buffer *buffer)
799{
800 struct isp_device *isp = video->isp;
801 struct isp_csi2_device *csi2 = &isp->isp_csi2a;
802
21d8582d 803 csi2_set_outaddr(csi2, buffer->dma);
121e9f1c
LP		 804
805 /*
806 * If streaming was enabled before there was a buffer queued
807 * or underrun happened in the ISR, the hardware was not enabled
808 * and DMA queue flag ISP_VIDEO_DMAQUEUE_UNDERRUN is still set.
809 * Enable it now.
810 */
811 if (csi2->video_out.dmaqueue_flags & ISP_VIDEO_DMAQUEUE_UNDERRUN) {
812 /* Enable / disable context 0 and IRQs */
813 csi2_if_enable(isp, csi2, 1);
814 csi2_ctx_enable(isp, csi2, 0, 1);
815 isp_video_dmaqueue_flags_clr(&csi2->video_out);
816 }
817
818 return 0;
819}
820
821static const struct isp_video_operations csi2_ispvideo_ops = {
822 .queue = csi2_queue,
823};
824
825/* -----------------------------------------------------------------------------
826 * V4L2 subdev operations
827 */
828
829static struct v4l2_mbus_framefmt *
f7234138 830__csi2_get_format(struct isp_csi2_device *csi2, struct v4l2_subdev_pad_config *cfg,
121e9f1c
LP		 831 unsigned int pad, enum v4l2_subdev_format_whence which)
832{
833 if (which == V4L2_SUBDEV_FORMAT_TRY)
f7234138 834 return v4l2_subdev_get_try_format(&csi2->subdev, cfg, pad);
121e9f1c
LP		 835 else
836 return &csi2->formats[pad];
837}
838
839static void
f7234138 840csi2_try_format(struct isp_csi2_device *csi2, struct v4l2_subdev_pad_config *cfg,
121e9f1c
LP		 841 unsigned int pad, struct v4l2_mbus_framefmt *fmt,
842 enum v4l2_subdev_format_whence which)
843{
27ffaeb0 844 u32 pixelcode;
121e9f1c
LP		 845 struct v4l2_mbus_framefmt *format;
846 const struct isp_format_info *info;
847 unsigned int i;
848
849 switch (pad) {
850 case CSI2_PAD_SINK:
851 /* Clamp the width and height to valid range (1-8191). */
852 for (i = 0; i < ARRAY_SIZE(csi2_input_fmts); i++) {
853 if (fmt->code == csi2_input_fmts[i])
854 break;
855 }
856
857 /* If not found, use SGRBG10 as default */
858 if (i >= ARRAY_SIZE(csi2_input_fmts))
27ffaeb0 859 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
121e9f1c
LP		 860
861 fmt->width = clamp_t(u32, fmt->width, 1, 8191);
862 fmt->height = clamp_t(u32, fmt->height, 1, 8191);
863 break;
864
865 case CSI2_PAD_SOURCE:
866 /* Source format same as sink format, except for DPCM
867 * compression.
868 */
869 pixelcode = fmt->code;
f7234138 870 format = __csi2_get_format(csi2, cfg, CSI2_PAD_SINK, which);
121e9f1c
LP		 871 memcpy(fmt, format, sizeof(*fmt));
872
873 /*
874 * Only Allow DPCM decompression, and check that the
875 * pattern is preserved
876 */
877 info = omap3isp_video_format_info(fmt->code);
878 if (info->uncompressed == pixelcode)
879 fmt->code = pixelcode;
880 break;
881 }
882
883 /* RGB, non-interlaced */
884 fmt->colorspace = V4L2_COLORSPACE_SRGB;
885 fmt->field = V4L2_FIELD_NONE;
886}
887
888/*
889 * csi2_enum_mbus_code - Handle pixel format enumeration
890 * @sd : pointer to v4l2 subdev structure
f7234138 891 * @cfg: V4L2 subdev pad configuration
121e9f1c
LP		 892 * @code : pointer to v4l2_subdev_mbus_code_enum structure
893 * return -EINVAL or zero on success
894 */
895static int csi2_enum_mbus_code(struct v4l2_subdev *sd,
f7234138 896 struct v4l2_subdev_pad_config *cfg,
121e9f1c
LP		 897 struct v4l2_subdev_mbus_code_enum *code)
898{
899 struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
900 struct v4l2_mbus_framefmt *format;
901 const struct isp_format_info *info;
902
903 if (code->pad == CSI2_PAD_SINK) {
904 if (code->index >= ARRAY_SIZE(csi2_input_fmts))
905 return -EINVAL;
906
907 code->code = csi2_input_fmts[code->index];
908 } else {
f7234138 909 format = __csi2_get_format(csi2, cfg, CSI2_PAD_SINK,
3f1ccf16 910 code->which);
121e9f1c
LP		 911 switch (code->index) {
912 case 0:
913 /* Passthrough sink pad code */
914 code->code = format->code;
915 break;
916 case 1:
917 /* Uncompressed code */
918 info = omap3isp_video_format_info(format->code);
919 if (info->uncompressed == format->code)
920 return -EINVAL;
921
922 code->code = info->uncompressed;
923 break;
924 default:
925 return -EINVAL;
926 }
927 }
928
929 return 0;
930}
931
932static int csi2_enum_frame_size(struct v4l2_subdev *sd,
f7234138 933 struct v4l2_subdev_pad_config *cfg,
121e9f1c
LP		 934 struct v4l2_subdev_frame_size_enum *fse)
935{
936 struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
937 struct v4l2_mbus_framefmt format;
938
939 if (fse->index != 0)
940 return -EINVAL;
941
942 format.code = fse->code;
943 format.width = 1;
944 format.height = 1;
5778e749 945 csi2_try_format(csi2, cfg, fse->pad, &format, fse->which);
121e9f1c
LP		 946 fse->min_width = format.width;
947 fse->min_height = format.height;
948
949 if (format.code != fse->code)
950 return -EINVAL;
951
952 format.code = fse->code;
953 format.width = -1;
954 format.height = -1;
5778e749 955 csi2_try_format(csi2, cfg, fse->pad, &format, fse->which);
121e9f1c
LP		 956 fse->max_width = format.width;
957 fse->max_height = format.height;
958
959 return 0;
960}
961
962/*
963 * csi2_get_format - Handle get format by pads subdev method
964 * @sd : pointer to v4l2 subdev structure
f7234138 965 * @cfg: V4L2 subdev pad configuration
121e9f1c 966 * @fmt: pointer to v4l2 subdev format structure
25985edc 967 * return -EINVAL or zero on success
121e9f1c 968 */
f7234138 969static int csi2_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
121e9f1c
LP		 970 struct v4l2_subdev_format *fmt)
971{
972 struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
973 struct v4l2_mbus_framefmt *format;
974
f7234138 975 format = __csi2_get_format(csi2, cfg, fmt->pad, fmt->which);
121e9f1c
LP		 976 if (format == NULL)
977 return -EINVAL;
978
979 fmt->format = *format;
980 return 0;
981}
982
983/*
984 * csi2_set_format - Handle set format by pads subdev method
985 * @sd : pointer to v4l2 subdev structure
f7234138 986 * @cfg: V4L2 subdev pad configuration
121e9f1c
LP		 987 * @fmt: pointer to v4l2 subdev format structure
988 * return -EINVAL or zero on success
989 */
f7234138 990static int csi2_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
121e9f1c
LP		 991 struct v4l2_subdev_format *fmt)
992{
993 struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
994 struct v4l2_mbus_framefmt *format;
995
f7234138 996 format = __csi2_get_format(csi2, cfg, fmt->pad, fmt->which);
121e9f1c
LP		 997 if (format == NULL)
998 return -EINVAL;
999
f7234138 1000 csi2_try_format(csi2, cfg, fmt->pad, &fmt->format, fmt->which);
121e9f1c
LP		 1001 *format = fmt->format;
1002
1003 /* Propagate the format from sink to source */
1004 if (fmt->pad == CSI2_PAD_SINK) {
f7234138 1005 format = __csi2_get_format(csi2, cfg, CSI2_PAD_SOURCE,
121e9f1c
LP		 1006 fmt->which);
1007 *format = fmt->format;
f7234138 1008 csi2_try_format(csi2, cfg, CSI2_PAD_SOURCE, format, fmt->which);
121e9f1c
LP		 1009 }
1010
1011 return 0;
1012}
1013
1014/*
1015 * csi2_init_formats - Initialize formats on all pads
1016 * @sd: ISP CSI2 V4L2 subdevice
1017 * @fh: V4L2 subdev file handle
1018 *
1019 * Initialize all pad formats with default values. If fh is not NULL, try
1020 * formats are initialized on the file handle. Otherwise active formats are
1021 * initialized on the device.
1022 */
1023static int csi2_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1024{
1025 struct v4l2_subdev_format format;
1026
1027 memset(&format, 0, sizeof(format));
1028 format.pad = CSI2_PAD_SINK;
1029 format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
27ffaeb0 1030 format.format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
121e9f1c
LP		 1031 format.format.width = 4096;
1032 format.format.height = 4096;
f7234138 1033 csi2_set_format(sd, fh ? fh->pad : NULL, &format);
121e9f1c
LP		 1034
1035 return 0;
1036}
1037
1038/*
1039 * csi2_set_stream - Enable/Disable streaming on the CSI2 module
1040 * @sd: ISP CSI2 V4L2 subdevice
1041 * @enable: ISP pipeline stream state
1042 *
1043 * Return 0 on success or a negative error code otherwise.
1044 */
1045static int csi2_set_stream(struct v4l2_subdev *sd, int enable)
1046{
1047 struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
1048 struct isp_device *isp = csi2->isp;
121e9f1c
LP		 1049 struct isp_video *video_out = &csi2->video_out;
1050
1051 switch (enable) {
1052 case ISP_PIPELINE_STREAM_CONTINUOUS:
7e1db599 1053 if (omap3isp_csiphy_acquire(csi2->phy, &sd->entity) < 0)
121e9f1c 1054 return -ENODEV;
121e9f1c
LP		 1055 if (csi2->output & CSI2_OUTPUT_MEMORY)
1056 omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_CSI2A_WRITE);
1057 csi2_configure(csi2);
1058 csi2_print_status(csi2);
1059
1060 /*
1061 * When outputting to memory with no buffer available, let the
1062 * buffer queue handler start the hardware. A DMA queue flag
1063 * ISP_VIDEO_DMAQUEUE_QUEUED will be set as soon as there is
1064 * a buffer available.
1065 */
1066 if (csi2->output & CSI2_OUTPUT_MEMORY &&
1067 !(video_out->dmaqueue_flags & ISP_VIDEO_DMAQUEUE_QUEUED))
1068 break;
1069 /* Enable context 0 and IRQs */
1070 atomic_set(&csi2->stopping, 0);
1071 csi2_ctx_enable(isp, csi2, 0, 1);
1072 csi2_if_enable(isp, csi2, 1);
1073 isp_video_dmaqueue_flags_clr(video_out);
1074 break;
1075
1076 case ISP_PIPELINE_STREAM_STOPPED:
1077 if (csi2->state == ISP_PIPELINE_STREAM_STOPPED)
1078 return 0;
1079 if (omap3isp_module_sync_idle(&sd->entity, &csi2->wait,
1080 &csi2->stopping))
1081 dev_dbg(isp->dev, "%s: module stop timeout.\n",
1082 sd->name);
1083 csi2_ctx_enable(isp, csi2, 0, 0);
1084 csi2_if_enable(isp, csi2, 0);
1085 csi2_irq_ctx_set(isp, csi2, 0);
1086 omap3isp_csiphy_release(csi2->phy);
1087 isp_video_dmaqueue_flags_clr(video_out);
1088 omap3isp_sbl_disable(isp, OMAP3_ISP_SBL_CSI2A_WRITE);
1089 break;
1090 }
1091
1092 csi2->state = enable;
1093 return 0;
1094}
1095
1096/* subdev video operations */
1097static const struct v4l2_subdev_video_ops csi2_video_ops = {
1098 .s_stream = csi2_set_stream,
1099};
1100
1101/* subdev pad operations */
1102static const struct v4l2_subdev_pad_ops csi2_pad_ops = {
1103 .enum_mbus_code = csi2_enum_mbus_code,
1104 .enum_frame_size = csi2_enum_frame_size,
1105 .get_fmt = csi2_get_format,
1106 .set_fmt = csi2_set_format,
1107};
1108
1109/* subdev operations */
1110static const struct v4l2_subdev_ops csi2_ops = {
1111 .video = &csi2_video_ops,
1112 .pad = &csi2_pad_ops,
1113};
1114
1115/* subdev internal operations */
1116static const struct v4l2_subdev_internal_ops csi2_internal_ops = {
1117 .open = csi2_init_formats,
1118};
1119
1120/* -----------------------------------------------------------------------------
1121 * Media entity operations
1122 */
1123
1124/*
1125 * csi2_link_setup - Setup CSI2 connections.
1126 * @entity : Pointer to media entity structure
1127 * @local : Pointer to local pad array
1128 * @remote : Pointer to remote pad array
1129 * @flags : Link flags
1130 * return -EINVAL or zero on success
1131 */
1132static int csi2_link_setup(struct media_entity *entity,
1133 const struct media_pad *local,
1134 const struct media_pad *remote, u32 flags)
1135{
1136 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
1137 struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
1138 struct isp_csi2_ctrl_cfg *ctrl = &csi2->ctrl;
829de29b 1139 unsigned int index = local->index;
121e9f1c
LP		 1140
1141 /*
1142 * The ISP core doesn't support pipelines with multiple video outputs.
1143 * Revisit this when it will be implemented, and return -EBUSY for now.
1144 */
1145
59ecd59d
MCC		 1146 /* FIXME: this is actually a hack! */
1147 if (is_media_entity_v4l2_subdev(remote->entity))
1148 index |= 2 << 16;
1149
1150 switch (index) {
1151 case CSI2_PAD_SOURCE:
121e9f1c
LP		 1152 if (flags & MEDIA_LNK_FL_ENABLED) {
1153 if (csi2->output & ~CSI2_OUTPUT_MEMORY)
1154 return -EBUSY;
1155 csi2->output |= CSI2_OUTPUT_MEMORY;
1156 } else {
1157 csi2->output &= ~CSI2_OUTPUT_MEMORY;
1158 }
1159 break;
1160
59ecd59d 1161 case CSI2_PAD_SOURCE | 2 << 16:
121e9f1c
LP		 1162 if (flags & MEDIA_LNK_FL_ENABLED) {
1163 if (csi2->output & ~CSI2_OUTPUT_CCDC)
1164 return -EBUSY;
1165 csi2->output |= CSI2_OUTPUT_CCDC;
1166 } else {
1167 csi2->output &= ~CSI2_OUTPUT_CCDC;
1168 }
1169 break;
1170
1171 default:
1172 /* Link from camera to CSI2 is fixed... */
1173 return -EINVAL;
1174 }
1175
1176 ctrl->vp_only_enable =
1177 (csi2->output & CSI2_OUTPUT_MEMORY) ? false : true;
1178 ctrl->vp_clk_enable = !!(csi2->output & CSI2_OUTPUT_CCDC);
1179
1180 return 0;
1181}
1182
1183/* media operations */
1184static const struct media_entity_operations csi2_media_ops = {
1185 .link_setup = csi2_link_setup,
20d4ab7b 1186 .link_validate = v4l2_subdev_link_validate,
121e9f1c
LP		 1187};
1188
39099d09
LP		 1189void omap3isp_csi2_unregister_entities(struct isp_csi2_device *csi2)
1190{
1191 v4l2_device_unregister_subdev(&csi2->subdev);
1192 omap3isp_video_unregister(&csi2->video_out);
1193}
1194
1195int omap3isp_csi2_register_entities(struct isp_csi2_device *csi2,
1196 struct v4l2_device *vdev)
1197{
1198 int ret;
1199
1200 /* Register the subdev and video nodes. */
1201 ret = v4l2_device_register_subdev(vdev, &csi2->subdev);
1202 if (ret < 0)
1203 goto error;
1204
1205 ret = omap3isp_video_register(&csi2->video_out, vdev);
1206 if (ret < 0)
1207 goto error;
1208
1209 return 0;
1210
1211error:
1212 omap3isp_csi2_unregister_entities(csi2);
1213 return ret;
1214}
1215
1216/* -----------------------------------------------------------------------------
1217 * ISP CSI2 initialisation and cleanup
1218 */
1219
121e9f1c
LP		 1220/*
1221 * csi2_init_entities - Initialize subdev and media entity.
1222 * @csi2: Pointer to csi2 structure.
1223 * return -ENOMEM or zero on success
1224 */
1225static int csi2_init_entities(struct isp_csi2_device *csi2)
1226{
1227 struct v4l2_subdev *sd = &csi2->subdev;
1228 struct media_pad *pads = csi2->pads;
1229 struct media_entity *me = &sd->entity;
1230 int ret;
1231
1232 v4l2_subdev_init(sd, &csi2_ops);
1233 sd->internal_ops = &csi2_internal_ops;
c0decac1 1234 strscpy(sd->name, "OMAP3 ISP CSI2a", sizeof(sd->name));
121e9f1c
LP		 1235
1236 sd->grp_id = 1 << 16; /* group ID for isp subdevs */
1237 v4l2_set_subdevdata(sd, csi2);
1238 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1239
1240 pads[CSI2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
8dad936a
SA		 1241 pads[CSI2_PAD_SINK].flags = MEDIA_PAD_FL_SINK
1242 | MEDIA_PAD_FL_MUST_CONNECT;
121e9f1c
LP		 1243
1244 me->ops = &csi2_media_ops;
ab22e77c 1245 ret = media_entity_pads_init(me, CSI2_PADS_NUM, pads);
121e9f1c
LP		 1246 if (ret < 0)
1247 return ret;
1248
1249 csi2_init_formats(sd, NULL);
1250
1251 /* Video device node */
1252 csi2->video_out.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1253 csi2->video_out.ops = &csi2_ispvideo_ops;
1254 csi2->video_out.bpl_alignment = 32;
1255 csi2->video_out.bpl_zero_padding = 1;
1256 csi2->video_out.bpl_max = 0x1ffe0;
1257 csi2->video_out.isp = csi2->isp;
1258 csi2->video_out.capture_mem = PAGE_ALIGN(4096 * 4096) * 3;
1259
1260 ret = omap3isp_video_init(&csi2->video_out, "CSI2a");
1261 if (ret < 0)
9b6390bd 1262 goto error_video;
121e9f1c 1263
121e9f1c 1264 return 0;
9b6390bd 1265
9b6390bd
LP		 1266error_video:
1267 media_entity_cleanup(&csi2->subdev.entity);
1268 return ret;
121e9f1c
LP		 1269}
1270
121e9f1c
LP		 1271/*
1272 * omap3isp_csi2_init - Routine for module driver init
1273 */
1274int omap3isp_csi2_init(struct isp_device *isp)
1275{
1276 struct isp_csi2_device *csi2a = &isp->isp_csi2a;
1277 struct isp_csi2_device *csi2c = &isp->isp_csi2c;
1278 int ret;
1279
1280 csi2a->isp = isp;
1281 csi2a->available = 1;
1282 csi2a->regs1 = OMAP3_ISP_IOMEM_CSI2A_REGS1;
1283 csi2a->regs2 = OMAP3_ISP_IOMEM_CSI2A_REGS2;
1284 csi2a->phy = &isp->isp_csiphy2;
1285 csi2a->state = ISP_PIPELINE_STREAM_STOPPED;
1286 init_waitqueue_head(&csi2a->wait);
1287
1288 ret = csi2_init_entities(csi2a);
1289 if (ret < 0)
9b6390bd 1290 return ret;
121e9f1c
LP		 1291
1292 if (isp->revision == ISP_REVISION_15_0) {
1293 csi2c->isp = isp;
1294 csi2c->available = 1;
1295 csi2c->regs1 = OMAP3_ISP_IOMEM_CSI2C_REGS1;
1296 csi2c->regs2 = OMAP3_ISP_IOMEM_CSI2C_REGS2;
1297 csi2c->phy = &isp->isp_csiphy1;
1298 csi2c->state = ISP_PIPELINE_STREAM_STOPPED;
1299 init_waitqueue_head(&csi2c->wait);
1300 }
1301
1302 return 0;
121e9f1c 1303}
39099d09
LP		 1304
1305/*
1306 * omap3isp_csi2_cleanup - Routine for module driver cleanup
1307 */
1308void omap3isp_csi2_cleanup(struct isp_device *isp)
1309{
1310 struct isp_csi2_device *csi2a = &isp->isp_csi2a;
1311
1312 omap3isp_video_cleanup(&csi2a->video_out);
1313 media_entity_cleanup(&csi2a->subdev.entity);
1314}
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