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[mirror_ubuntu-zesty-kernel.git] / drivers / media / platform / s5p-fimc / fimc-capture.c
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5f3cc447 1/*
3a3f9449 2 * Samsung S5P/EXYNOS4 SoC series camera interface (camera capture) driver
5f3cc447 3 *
0c9204d3
SN
4 * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
5 * Sylwester Nawrocki <s.nawrocki@samsung.com>
5f3cc447
SN
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/kernel.h>
5f3cc447
SN
14#include <linux/types.h>
15#include <linux/errno.h>
16#include <linux/bug.h>
17#include <linux/interrupt.h>
18#include <linux/device.h>
e9e21083 19#include <linux/pm_runtime.h>
5f3cc447
SN
20#include <linux/list.h>
21#include <linux/slab.h>
5f3cc447
SN
22
23#include <linux/videodev2.h>
24#include <media/v4l2-device.h>
25#include <media/v4l2-ioctl.h>
26#include <media/v4l2-mem2mem.h>
2dab38e2
SN
27#include <media/videobuf2-core.h>
28#include <media/videobuf2-dma-contig.h>
5f3cc447 29
131b6c61 30#include "fimc-mdevice.h"
5f3cc447 31#include "fimc-core.h"
c83a1ff0 32#include "fimc-reg.h"
5f3cc447 33
bb7c276e 34static int fimc_capture_hw_init(struct fimc_dev *fimc)
9e803a04
SN
35{
36 struct fimc_ctx *ctx = fimc->vid_cap.ctx;
0f735f52 37 struct fimc_pipeline *p = &fimc->pipeline;
9e803a04
SN
38 struct fimc_sensor_info *sensor;
39 unsigned long flags;
40 int ret = 0;
41
0f735f52 42 if (p->subdevs[IDX_SENSOR] == NULL || ctx == NULL)
9e803a04
SN
43 return -ENXIO;
44 if (ctx->s_frame.fmt == NULL)
45 return -EINVAL;
46
0f735f52 47 sensor = v4l2_get_subdev_hostdata(p->subdevs[IDX_SENSOR]);
9e803a04
SN
48
49 spin_lock_irqsave(&fimc->slock, flags);
50 fimc_prepare_dma_offset(ctx, &ctx->d_frame);
51 fimc_set_yuv_order(ctx);
52
6612a082
SN
53 fimc_hw_set_camera_polarity(fimc, &sensor->pdata);
54 fimc_hw_set_camera_type(fimc, &sensor->pdata);
55 fimc_hw_set_camera_source(fimc, &sensor->pdata);
9e803a04
SN
56 fimc_hw_set_camera_offset(fimc, &ctx->s_frame);
57
58 ret = fimc_set_scaler_info(ctx);
59 if (!ret) {
60 fimc_hw_set_input_path(ctx);
61 fimc_hw_set_prescaler(ctx);
62 fimc_hw_set_mainscaler(ctx);
63 fimc_hw_set_target_format(ctx);
64 fimc_hw_set_rotation(ctx);
9448ab7d 65 fimc_hw_set_effect(ctx);
9e803a04
SN
66 fimc_hw_set_output_path(ctx);
67 fimc_hw_set_out_dma(ctx);
dafb9c70
SN
68 if (fimc->variant->has_alpha)
69 fimc_hw_set_rgb_alpha(ctx);
237e0265 70 clear_bit(ST_CAPT_APPLY_CFG, &fimc->state);
9e803a04
SN
71 }
72 spin_unlock_irqrestore(&fimc->slock, flags);
73 return ret;
74}
75
bb7c276e
SN
76/*
77 * Reinitialize the driver so it is ready to start the streaming again.
78 * Set fimc->state to indicate stream off and the hardware shut down state.
79 * If not suspending (@suspend is false), return any buffers to videobuf2.
80 * Otherwise put any owned buffers onto the pending buffers queue, so they
81 * can be re-spun when the device is being resumed. Also perform FIMC
82 * software reset and disable streaming on the whole pipeline if required.
83 */
3e4748d8 84static int fimc_capture_state_cleanup(struct fimc_dev *fimc, bool suspend)
5f3cc447 85{
bd323e28 86 struct fimc_vid_cap *cap = &fimc->vid_cap;
2dab38e2 87 struct fimc_vid_buffer *buf;
bd323e28 88 unsigned long flags;
3e4748d8 89 bool streaming;
5f3cc447
SN
90
91 spin_lock_irqsave(&fimc->slock, flags);
3e4748d8 92 streaming = fimc->state & (1 << ST_CAPT_ISP_STREAM);
5f3cc447 93
3e4748d8
SN
94 fimc->state &= ~(1 << ST_CAPT_RUN | 1 << ST_CAPT_SHUT |
95 1 << ST_CAPT_STREAM | 1 << ST_CAPT_ISP_STREAM);
aa333122
SN
96 if (suspend)
97 fimc->state |= (1 << ST_CAPT_SUSPENDED);
98 else
3e4748d8 99 fimc->state &= ~(1 << ST_CAPT_PEND | 1 << ST_CAPT_SUSPENDED);
2dab38e2 100
3e4748d8
SN
101 /* Release unused buffers */
102 while (!suspend && !list_empty(&cap->pending_buf_q)) {
0295202c 103 buf = fimc_pending_queue_pop(cap);
2dab38e2
SN
104 vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
105 }
3e4748d8 106 /* If suspending put unused buffers onto pending queue */
2dab38e2 107 while (!list_empty(&cap->active_buf_q)) {
0295202c 108 buf = fimc_active_queue_pop(cap);
3e4748d8
SN
109 if (suspend)
110 fimc_pending_queue_add(cap, buf);
111 else
112 vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
2dab38e2 113 }
2c1bb62e
SN
114
115 fimc_hw_reset(fimc);
116 cap->buf_index = 0;
117
5f3cc447 118 spin_unlock_irqrestore(&fimc->slock, flags);
4db5e27e 119
3e4748d8 120 if (streaming)
b9ee31e6
SN
121 return fimc_pipeline_call(fimc, set_stream,
122 &fimc->pipeline, 0);
4db5e27e
SN
123 else
124 return 0;
bd323e28
MS
125}
126
3e4748d8 127static int fimc_stop_capture(struct fimc_dev *fimc, bool suspend)
bd323e28 128{
bd323e28
MS
129 unsigned long flags;
130
131 if (!fimc_capture_active(fimc))
132 return 0;
133
134 spin_lock_irqsave(&fimc->slock, flags);
135 set_bit(ST_CAPT_SHUT, &fimc->state);
136 fimc_deactivate_capture(fimc);
137 spin_unlock_irqrestore(&fimc->slock, flags);
138
139 wait_event_timeout(fimc->irq_queue,
140 !test_bit(ST_CAPT_SHUT, &fimc->state),
3e4748d8 141 (2*HZ/10)); /* 200 ms */
5f3cc447 142
3e4748d8 143 return fimc_capture_state_cleanup(fimc, suspend);
5f3cc447
SN
144}
145
237e0265
SN
146/**
147 * fimc_capture_config_update - apply the camera interface configuration
148 *
149 * To be called from within the interrupt handler with fimc.slock
150 * spinlock held. It updates the camera pixel crop, rotation and
151 * image flip in H/W.
152 */
97d97422 153static int fimc_capture_config_update(struct fimc_ctx *ctx)
237e0265
SN
154{
155 struct fimc_dev *fimc = ctx->fimc_dev;
156 int ret;
157
237e0265 158 fimc_hw_set_camera_offset(fimc, &ctx->s_frame);
efb13c3d 159
237e0265 160 ret = fimc_set_scaler_info(ctx);
efb13c3d
SN
161 if (ret)
162 return ret;
163
164 fimc_hw_set_prescaler(ctx);
165 fimc_hw_set_mainscaler(ctx);
166 fimc_hw_set_target_format(ctx);
167 fimc_hw_set_rotation(ctx);
9448ab7d 168 fimc_hw_set_effect(ctx);
efb13c3d
SN
169 fimc_prepare_dma_offset(ctx, &ctx->d_frame);
170 fimc_hw_set_out_dma(ctx);
171 if (fimc->variant->has_alpha)
172 fimc_hw_set_rgb_alpha(ctx);
173
174 clear_bit(ST_CAPT_APPLY_CFG, &fimc->state);
237e0265
SN
175 return ret;
176}
bd323e28 177
97d97422
SN
178void fimc_capture_irq_handler(struct fimc_dev *fimc, int deq_buf)
179{
14783d25 180 struct v4l2_subdev *csis = fimc->pipeline.subdevs[IDX_CSIS];
97d97422 181 struct fimc_vid_cap *cap = &fimc->vid_cap;
14783d25 182 struct fimc_frame *f = &cap->ctx->d_frame;
97d97422
SN
183 struct fimc_vid_buffer *v_buf;
184 struct timeval *tv;
185 struct timespec ts;
186
187 if (test_and_clear_bit(ST_CAPT_SHUT, &fimc->state)) {
188 wake_up(&fimc->irq_queue);
189 goto done;
190 }
191
192 if (!list_empty(&cap->active_buf_q) &&
193 test_bit(ST_CAPT_RUN, &fimc->state) && deq_buf) {
194 ktime_get_real_ts(&ts);
195
196 v_buf = fimc_active_queue_pop(cap);
197
198 tv = &v_buf->vb.v4l2_buf.timestamp;
199 tv->tv_sec = ts.tv_sec;
200 tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC;
201 v_buf->vb.v4l2_buf.sequence = cap->frame_count++;
202
203 vb2_buffer_done(&v_buf->vb, VB2_BUF_STATE_DONE);
204 }
205
206 if (!list_empty(&cap->pending_buf_q)) {
207
208 v_buf = fimc_pending_queue_pop(cap);
209 fimc_hw_set_output_addr(fimc, &v_buf->paddr, cap->buf_index);
210 v_buf->index = cap->buf_index;
211
212 /* Move the buffer to the capture active queue */
213 fimc_active_queue_add(cap, v_buf);
214
215 dbg("next frame: %d, done frame: %d",
216 fimc_hw_get_frame_index(fimc), v_buf->index);
217
218 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
219 cap->buf_index = 0;
220 }
14783d25
SN
221 /*
222 * Set up a buffer at MIPI-CSIS if current image format
223 * requires the frame embedded data capture.
224 */
225 if (f->fmt->mdataplanes && !list_empty(&cap->active_buf_q)) {
226 unsigned int plane = ffs(f->fmt->mdataplanes) - 1;
227 unsigned int size = f->payload[plane];
228 s32 index = fimc_hw_get_frame_index(fimc);
229 void *vaddr;
230
231 list_for_each_entry(v_buf, &cap->active_buf_q, list) {
232 if (v_buf->index != index)
233 continue;
234 vaddr = vb2_plane_vaddr(&v_buf->vb, plane);
235 v4l2_subdev_call(csis, video, s_rx_buffer,
236 vaddr, &size);
237 break;
238 }
239 }
97d97422
SN
240
241 if (cap->active_buf_cnt == 0) {
242 if (deq_buf)
243 clear_bit(ST_CAPT_RUN, &fimc->state);
244
245 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
246 cap->buf_index = 0;
247 } else {
248 set_bit(ST_CAPT_RUN, &fimc->state);
249 }
250
bb7c276e
SN
251 if (test_bit(ST_CAPT_APPLY_CFG, &fimc->state))
252 fimc_capture_config_update(cap->ctx);
97d97422
SN
253done:
254 if (cap->active_buf_cnt == 1) {
255 fimc_deactivate_capture(fimc);
256 clear_bit(ST_CAPT_STREAM, &fimc->state);
257 }
258
259 dbg("frame: %d, active_buf_cnt: %d",
260 fimc_hw_get_frame_index(fimc), cap->active_buf_cnt);
261}
262
263
bd323e28 264static int start_streaming(struct vb2_queue *q, unsigned int count)
2dab38e2
SN
265{
266 struct fimc_ctx *ctx = q->drv_priv;
267 struct fimc_dev *fimc = ctx->fimc_dev;
9e803a04 268 struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
bd323e28 269 int min_bufs;
2dab38e2
SN
270 int ret;
271
9e803a04 272 vid_cap->frame_count = 0;
8ec737ff 273
bb7c276e
SN
274 ret = fimc_capture_hw_init(fimc);
275 if (ret) {
276 fimc_capture_state_cleanup(fimc, false);
277 return ret;
278 }
2dab38e2 279
2dab38e2
SN
280 set_bit(ST_CAPT_PEND, &fimc->state);
281
bd323e28
MS
282 min_bufs = fimc->vid_cap.reqbufs_count > 1 ? 2 : 1;
283
4db5e27e
SN
284 if (vid_cap->active_buf_cnt >= min_bufs &&
285 !test_and_set_bit(ST_CAPT_STREAM, &fimc->state)) {
bd323e28
MS
286 fimc_activate_capture(ctx);
287
4db5e27e 288 if (!test_and_set_bit(ST_CAPT_ISP_STREAM, &fimc->state))
b9ee31e6
SN
289 fimc_pipeline_call(fimc, set_stream,
290 &fimc->pipeline, 1);
4db5e27e
SN
291 }
292
2dab38e2
SN
293 return 0;
294}
295
296static int stop_streaming(struct vb2_queue *q)
297{
298 struct fimc_ctx *ctx = q->drv_priv;
299 struct fimc_dev *fimc = ctx->fimc_dev;
2dab38e2 300
4ecbf5d1 301 if (!fimc_capture_active(fimc))
2dab38e2 302 return -EINVAL;
2dab38e2 303
3e4748d8 304 return fimc_stop_capture(fimc, false);
2dab38e2
SN
305}
306
e9e21083
SN
307int fimc_capture_suspend(struct fimc_dev *fimc)
308{
3e4748d8
SN
309 bool suspend = fimc_capture_busy(fimc);
310
311 int ret = fimc_stop_capture(fimc, suspend);
312 if (ret)
313 return ret;
b9ee31e6 314 return fimc_pipeline_call(fimc, close, &fimc->pipeline);
e9e21083
SN
315}
316
3e4748d8
SN
317static void buffer_queue(struct vb2_buffer *vb);
318
e9e21083
SN
319int fimc_capture_resume(struct fimc_dev *fimc)
320{
3e4748d8
SN
321 struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
322 struct fimc_vid_buffer *buf;
323 int i;
324
325 if (!test_and_clear_bit(ST_CAPT_SUSPENDED, &fimc->state))
326 return 0;
327
328 INIT_LIST_HEAD(&fimc->vid_cap.active_buf_q);
329 vid_cap->buf_index = 0;
b9ee31e6
SN
330 fimc_pipeline_call(fimc, open, &fimc->pipeline,
331 &vid_cap->vfd.entity, false);
bb7c276e 332 fimc_capture_hw_init(fimc);
3e4748d8
SN
333
334 clear_bit(ST_CAPT_SUSPENDED, &fimc->state);
335
336 for (i = 0; i < vid_cap->reqbufs_count; i++) {
337 if (list_empty(&vid_cap->pending_buf_q))
338 break;
339 buf = fimc_pending_queue_pop(vid_cap);
340 buffer_queue(&buf->vb);
341 }
e9e21083 342 return 0;
3e4748d8 343
e9e21083
SN
344}
345
63746be5 346static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *pfmt,
fc714e70
GL
347 unsigned int *num_buffers, unsigned int *num_planes,
348 unsigned int sizes[], void *allocators[])
2dab38e2 349{
63746be5 350 const struct v4l2_pix_format_mplane *pixm = NULL;
2dab38e2 351 struct fimc_ctx *ctx = vq->drv_priv;
63746be5
SN
352 struct fimc_frame *frame = &ctx->d_frame;
353 struct fimc_fmt *fmt = frame->fmt;
354 unsigned long wh;
ef7af59b 355 int i;
2dab38e2 356
63746be5
SN
357 if (pfmt) {
358 pixm = &pfmt->fmt.pix_mp;
359 fmt = fimc_find_format(&pixm->pixelformat, NULL,
360 FMT_FLAGS_CAM | FMT_FLAGS_M2M, -1);
361 wh = pixm->width * pixm->height;
362 } else {
363 wh = frame->f_width * frame->f_height;
364 }
365
366 if (fmt == NULL)
2dab38e2
SN
367 return -EINVAL;
368
ef7af59b 369 *num_planes = fmt->memplanes;
2dab38e2 370
ef7af59b 371 for (i = 0; i < fmt->memplanes; i++) {
63746be5
SN
372 unsigned int size = (wh * fmt->depth[i]) / 8;
373 if (pixm)
374 sizes[i] = max(size, pixm->plane_fmt[i].sizeimage);
14783d25
SN
375 else if (fimc_fmt_is_user_defined(fmt->color))
376 sizes[i] = frame->payload[i];
63746be5 377 else
d547ab66
SN
378 sizes[i] = max_t(u32, size, frame->payload[i]);
379
ef7af59b
SN
380 allocators[i] = ctx->fimc_dev->alloc_ctx;
381 }
2dab38e2 382
ef7af59b 383 return 0;
2dab38e2
SN
384}
385
2dab38e2
SN
386static int buffer_prepare(struct vb2_buffer *vb)
387{
388 struct vb2_queue *vq = vb->vb2_queue;
389 struct fimc_ctx *ctx = vq->drv_priv;
2dab38e2
SN
390 int i;
391
4db5e27e 392 if (ctx->d_frame.fmt == NULL)
ef7af59b 393 return -EINVAL;
2dab38e2 394
ef7af59b 395 for (i = 0; i < ctx->d_frame.fmt->memplanes; i++) {
4db5e27e 396 unsigned long size = ctx->d_frame.payload[i];
2dab38e2
SN
397
398 if (vb2_plane_size(vb, i) < size) {
31d34d9b 399 v4l2_err(&ctx->fimc_dev->vid_cap.vfd,
30c9939d 400 "User buffer too small (%ld < %ld)\n",
2dab38e2
SN
401 vb2_plane_size(vb, i), size);
402 return -EINVAL;
403 }
2dab38e2
SN
404 vb2_set_plane_payload(vb, i, size);
405 }
406
407 return 0;
408}
409
410static void buffer_queue(struct vb2_buffer *vb)
411{
2dab38e2
SN
412 struct fimc_vid_buffer *buf
413 = container_of(vb, struct fimc_vid_buffer, vb);
4db5e27e
SN
414 struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
415 struct fimc_dev *fimc = ctx->fimc_dev;
2dab38e2
SN
416 struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
417 unsigned long flags;
8ec737ff 418 int min_bufs;
2dab38e2
SN
419
420 spin_lock_irqsave(&fimc->slock, flags);
8ec737ff
SK
421 fimc_prepare_addr(ctx, &buf->vb, &ctx->d_frame, &buf->paddr);
422
3e4748d8
SN
423 if (!test_bit(ST_CAPT_SUSPENDED, &fimc->state) &&
424 !test_bit(ST_CAPT_STREAM, &fimc->state) &&
425 vid_cap->active_buf_cnt < FIMC_MAX_OUT_BUFS) {
8ec737ff
SK
426 /* Setup the buffer directly for processing. */
427 int buf_id = (vid_cap->reqbufs_count == 1) ? -1 :
428 vid_cap->buf_index;
2dab38e2 429
8ec737ff
SK
430 fimc_hw_set_output_addr(fimc, &buf->paddr, buf_id);
431 buf->index = vid_cap->buf_index;
0295202c 432 fimc_active_queue_add(vid_cap, buf);
2dab38e2 433
8ec737ff
SK
434 if (++vid_cap->buf_index >= FIMC_MAX_OUT_BUFS)
435 vid_cap->buf_index = 0;
436 } else {
437 fimc_pending_queue_add(vid_cap, buf);
2dab38e2 438 }
8ec737ff
SK
439
440 min_bufs = vid_cap->reqbufs_count > 1 ? 2 : 1;
441
4db5e27e 442
bd323e28
MS
443 if (vb2_is_streaming(&vid_cap->vbq) &&
444 vid_cap->active_buf_cnt >= min_bufs &&
4db5e27e 445 !test_and_set_bit(ST_CAPT_STREAM, &fimc->state)) {
8ec737ff 446 fimc_activate_capture(ctx);
4db5e27e 447 spin_unlock_irqrestore(&fimc->slock, flags);
8ec737ff 448
4db5e27e 449 if (!test_and_set_bit(ST_CAPT_ISP_STREAM, &fimc->state))
b9ee31e6
SN
450 fimc_pipeline_call(fimc, set_stream,
451 &fimc->pipeline, 1);
4db5e27e
SN
452 return;
453 }
2dab38e2
SN
454 spin_unlock_irqrestore(&fimc->slock, flags);
455}
456
457static void fimc_lock(struct vb2_queue *vq)
458{
459 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
460 mutex_lock(&ctx->fimc_dev->lock);
461}
462
463static void fimc_unlock(struct vb2_queue *vq)
464{
465 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
466 mutex_unlock(&ctx->fimc_dev->lock);
467}
468
469static struct vb2_ops fimc_capture_qops = {
470 .queue_setup = queue_setup,
471 .buf_prepare = buffer_prepare,
472 .buf_queue = buffer_queue,
2dab38e2
SN
473 .wait_prepare = fimc_unlock,
474 .wait_finish = fimc_lock,
475 .start_streaming = start_streaming,
476 .stop_streaming = stop_streaming,
477};
478
131b6c61
SN
479/**
480 * fimc_capture_ctrls_create - initialize the control handler
481 * Initialize the capture video node control handler and fill it
482 * with the FIMC controls. Inherit any sensor's controls if the
483 * 'user_subdev_api' flag is false (default behaviour).
484 * This function need to be called with the graph mutex held.
485 */
486int fimc_capture_ctrls_create(struct fimc_dev *fimc)
487{
488 struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
489 int ret;
490
491 if (WARN_ON(vid_cap->ctx == NULL))
492 return -ENXIO;
9448ab7d 493 if (vid_cap->ctx->ctrls.ready)
131b6c61
SN
494 return 0;
495
496 ret = fimc_ctrls_create(vid_cap->ctx);
9448ab7d 497 if (ret || vid_cap->user_subdev_api || !vid_cap->ctx->ctrls.ready)
131b6c61
SN
498 return ret;
499
9448ab7d 500 return v4l2_ctrl_add_handler(&vid_cap->ctx->ctrls.handler,
34a6b7d0 501 fimc->pipeline.subdevs[IDX_SENSOR]->ctrl_handler, NULL);
131b6c61
SN
502}
503
237e0265
SN
504static int fimc_capture_set_default_format(struct fimc_dev *fimc);
505
5f3cc447
SN
506static int fimc_capture_open(struct file *file)
507{
508 struct fimc_dev *fimc = video_drvdata(file);
c2d430af 509 int ret = -EBUSY;
5f3cc447
SN
510
511 dbg("pid: %d, state: 0x%lx", task_pid_nr(current), fimc->state);
512
c2d430af
SN
513 if (mutex_lock_interruptible(&fimc->lock))
514 return -ERESTARTSYS;
515
5f3cc447 516 if (fimc_m2m_active(fimc))
c2d430af 517 goto unlock;
5f3cc447 518
3e4748d8 519 set_bit(ST_CAPT_BUSY, &fimc->state);
e3fc82e8
SN
520 ret = pm_runtime_get_sync(&fimc->pdev->dev);
521 if (ret < 0)
c2d430af 522 goto unlock;
4db5e27e 523
e3fc82e8 524 ret = v4l2_fh_open(file);
c2d430af
SN
525 if (ret) {
526 pm_runtime_put(&fimc->pdev->dev);
527 goto unlock;
528 }
e3fc82e8 529
c2d430af 530 if (++fimc->vid_cap.refcnt == 1) {
b9ee31e6
SN
531 ret = fimc_pipeline_call(fimc, open, &fimc->pipeline,
532 &fimc->vid_cap.vfd.entity, true);
e3fc82e8 533
c2d430af
SN
534 if (!ret && !fimc->vid_cap.user_subdev_api)
535 ret = fimc_capture_set_default_format(fimc);
536
537 if (!ret)
538 ret = fimc_capture_ctrls_create(fimc);
e3fc82e8 539
c2d430af
SN
540 if (ret < 0) {
541 clear_bit(ST_CAPT_BUSY, &fimc->state);
542 pm_runtime_put_sync(&fimc->pdev->dev);
543 fimc->vid_cap.refcnt--;
544 v4l2_fh_release(file);
545 }
546 }
547unlock:
548 mutex_unlock(&fimc->lock);
131b6c61 549 return ret;
5f3cc447
SN
550}
551
552static int fimc_capture_close(struct file *file)
553{
554 struct fimc_dev *fimc = video_drvdata(file);
c2d430af 555 int ret;
5f3cc447 556
5f3cc447
SN
557 dbg("pid: %d, state: 0x%lx", task_pid_nr(current), fimc->state);
558
ba6b372c 559 mutex_lock(&fimc->lock);
c2d430af 560
5f3cc447 561 if (--fimc->vid_cap.refcnt == 0) {
3e4748d8
SN
562 clear_bit(ST_CAPT_BUSY, &fimc->state);
563 fimc_stop_capture(fimc, false);
b9ee31e6 564 fimc_pipeline_call(fimc, close, &fimc->pipeline);
3e4748d8 565 clear_bit(ST_CAPT_SUSPENDED, &fimc->state);
5f3cc447
SN
566 }
567
e9e21083
SN
568 pm_runtime_put(&fimc->pdev->dev);
569
3e4748d8
SN
570 if (fimc->vid_cap.refcnt == 0) {
571 vb2_queue_release(&fimc->vid_cap.vbq);
572 fimc_ctrls_delete(fimc->vid_cap.ctx);
573 }
c2d430af
SN
574
575 ret = v4l2_fh_release(file);
576
577 mutex_unlock(&fimc->lock);
578 return ret;
5f3cc447
SN
579}
580
581static unsigned int fimc_capture_poll(struct file *file,
582 struct poll_table_struct *wait)
583{
e578588e 584 struct fimc_dev *fimc = video_drvdata(file);
c2d430af 585 int ret;
5f3cc447 586
c2d430af
SN
587 if (mutex_lock_interruptible(&fimc->lock))
588 return POLL_ERR;
589
590 ret = vb2_poll(&fimc->vid_cap.vbq, file, wait);
591 mutex_unlock(&fimc->lock);
592
593 return ret;
5f3cc447
SN
594}
595
596static int fimc_capture_mmap(struct file *file, struct vm_area_struct *vma)
597{
e578588e 598 struct fimc_dev *fimc = video_drvdata(file);
c2d430af
SN
599 int ret;
600
601 if (mutex_lock_interruptible(&fimc->lock))
602 return -ERESTARTSYS;
5f3cc447 603
c2d430af
SN
604 ret = vb2_mmap(&fimc->vid_cap.vbq, vma);
605 mutex_unlock(&fimc->lock);
606
607 return ret;
5f3cc447
SN
608}
609
5f3cc447
SN
610static const struct v4l2_file_operations fimc_capture_fops = {
611 .owner = THIS_MODULE,
612 .open = fimc_capture_open,
613 .release = fimc_capture_close,
614 .poll = fimc_capture_poll,
615 .unlocked_ioctl = video_ioctl2,
616 .mmap = fimc_capture_mmap,
617};
618
237e0265
SN
619/*
620 * Format and crop negotiation helpers
621 */
622
623static struct fimc_fmt *fimc_capture_try_format(struct fimc_ctx *ctx,
624 u32 *width, u32 *height,
625 u32 *code, u32 *fourcc, int pad)
626{
627 bool rotation = ctx->rotation == 90 || ctx->rotation == 270;
628 struct fimc_dev *fimc = ctx->fimc_dev;
405f230c
SN
629 const struct fimc_variant *var = fimc->variant;
630 const struct fimc_pix_limit *pl = var->pix_limit;
237e0265
SN
631 struct fimc_frame *dst = &ctx->d_frame;
632 u32 depth, min_w, max_w, min_h, align_h = 3;
633 u32 mask = FMT_FLAGS_CAM;
634 struct fimc_fmt *ffmt;
635
14783d25 636 /* Conversion from/to JPEG or User Defined format is not supported */
237e0265 637 if (code && ctx->s_frame.fmt && pad == FIMC_SD_PAD_SOURCE &&
14783d25
SN
638 fimc_fmt_is_user_defined(ctx->s_frame.fmt->color))
639 *code = ctx->s_frame.fmt->mbus_code;
237e0265
SN
640
641 if (fourcc && *fourcc != V4L2_PIX_FMT_JPEG && pad != FIMC_SD_PAD_SINK)
642 mask |= FMT_FLAGS_M2M;
643
644 ffmt = fimc_find_format(fourcc, code, mask, 0);
645 if (WARN_ON(!ffmt))
646 return NULL;
647 if (code)
648 *code = ffmt->mbus_code;
649 if (fourcc)
650 *fourcc = ffmt->fourcc;
651
652 if (pad == FIMC_SD_PAD_SINK) {
14783d25 653 max_w = fimc_fmt_is_user_defined(ffmt->color) ?
237e0265
SN
654 pl->scaler_dis_w : pl->scaler_en_w;
655 /* Apply the camera input interface pixel constraints */
656 v4l_bound_align_image(width, max_t(u32, *width, 32), max_w, 4,
657 height, max_t(u32, *height, 32),
658 FIMC_CAMIF_MAX_HEIGHT,
14783d25
SN
659 fimc_fmt_is_user_defined(ffmt->color) ?
660 3 : 1,
237e0265
SN
661 0);
662 return ffmt;
663 }
664 /* Can't scale or crop in transparent (JPEG) transfer mode */
14783d25 665 if (fimc_fmt_is_user_defined(ffmt->color)) {
237e0265
SN
666 *width = ctx->s_frame.f_width;
667 *height = ctx->s_frame.f_height;
668 return ffmt;
669 }
670 /* Apply the scaler and the output DMA constraints */
671 max_w = rotation ? pl->out_rot_en_w : pl->out_rot_dis_w;
fed07f84
SN
672 if (ctx->state & FIMC_COMPOSE) {
673 min_w = dst->offs_h + dst->width;
674 min_h = dst->offs_v + dst->height;
675 } else {
676 min_w = var->min_out_pixsize;
677 min_h = var->min_out_pixsize;
678 }
9c63afcb 679 if (var->min_vsize_align == 1 && !rotation)
237e0265
SN
680 align_h = fimc_fmt_is_rgb(ffmt->color) ? 0 : 1;
681
682 depth = fimc_get_format_depth(ffmt);
683 v4l_bound_align_image(width, min_w, max_w,
684 ffs(var->min_out_pixsize) - 1,
685 height, min_h, FIMC_CAMIF_MAX_HEIGHT,
686 align_h,
687 64/(ALIGN(depth, 8)));
688
689 dbg("pad%d: code: 0x%x, %dx%d. dst fmt: %dx%d",
690 pad, code ? *code : 0, *width, *height,
691 dst->f_width, dst->f_height);
692
693 return ffmt;
694}
695
fed07f84
SN
696static void fimc_capture_try_selection(struct fimc_ctx *ctx,
697 struct v4l2_rect *r,
698 int target)
237e0265
SN
699{
700 bool rotate = ctx->rotation == 90 || ctx->rotation == 270;
701 struct fimc_dev *fimc = ctx->fimc_dev;
405f230c
SN
702 const struct fimc_variant *var = fimc->variant;
703 const struct fimc_pix_limit *pl = var->pix_limit;
237e0265
SN
704 struct fimc_frame *sink = &ctx->s_frame;
705 u32 max_w, max_h, min_w = 0, min_h = 0, min_sz;
706 u32 align_sz = 0, align_h = 4;
707 u32 max_sc_h, max_sc_v;
708
709 /* In JPEG transparent transfer mode cropping is not supported */
14783d25 710 if (fimc_fmt_is_user_defined(ctx->d_frame.fmt->color)) {
237e0265
SN
711 r->width = sink->f_width;
712 r->height = sink->f_height;
713 r->left = r->top = 0;
714 return;
715 }
c1334823 716 if (target == V4L2_SEL_TGT_COMPOSE) {
237e0265
SN
717 if (ctx->rotation != 90 && ctx->rotation != 270)
718 align_h = 1;
719 max_sc_h = min(SCALER_MAX_HRATIO, 1 << (ffs(sink->width) - 3));
720 max_sc_v = min(SCALER_MAX_VRATIO, 1 << (ffs(sink->height) - 1));
721 min_sz = var->min_out_pixsize;
722 } else {
723 u32 depth = fimc_get_format_depth(sink->fmt);
724 align_sz = 64/ALIGN(depth, 8);
725 min_sz = var->min_inp_pixsize;
726 min_w = min_h = min_sz;
727 max_sc_h = max_sc_v = 1;
728 }
729 /*
fed07f84 730 * For the compose rectangle the following constraints must be met:
237e0265
SN
731 * - it must fit in the sink pad format rectangle (f_width/f_height);
732 * - maximum downscaling ratio is 64;
733 * - maximum crop size depends if the rotator is used or not;
734 * - the sink pad format width/height must be 4 multiple of the
735 * prescaler ratios determined by sink pad size and source pad crop,
736 * the prescaler ratio is returned by fimc_get_scaler_factor().
737 */
738 max_w = min_t(u32,
739 rotate ? pl->out_rot_en_w : pl->out_rot_dis_w,
740 rotate ? sink->f_height : sink->f_width);
741 max_h = min_t(u32, FIMC_CAMIF_MAX_HEIGHT, sink->f_height);
fed07f84 742
c1334823 743 if (target == V4L2_SEL_TGT_COMPOSE) {
237e0265
SN
744 min_w = min_t(u32, max_w, sink->f_width / max_sc_h);
745 min_h = min_t(u32, max_h, sink->f_height / max_sc_v);
746 if (rotate) {
747 swap(max_sc_h, max_sc_v);
748 swap(min_w, min_h);
749 }
750 }
751 v4l_bound_align_image(&r->width, min_w, max_w, ffs(min_sz) - 1,
752 &r->height, min_h, max_h, align_h,
753 align_sz);
fed07f84 754 /* Adjust left/top if crop/compose rectangle is out of bounds */
237e0265
SN
755 r->left = clamp_t(u32, r->left, 0, sink->f_width - r->width);
756 r->top = clamp_t(u32, r->top, 0, sink->f_height - r->height);
757 r->left = round_down(r->left, var->hor_offs_align);
758
fed07f84
SN
759 dbg("target %#x: (%d,%d)/%dx%d, sink fmt: %dx%d",
760 target, r->left, r->top, r->width, r->height,
237e0265
SN
761 sink->f_width, sink->f_height);
762}
763
764/*
765 * The video node ioctl operations
766 */
5f3cc447
SN
767static int fimc_vidioc_querycap_capture(struct file *file, void *priv,
768 struct v4l2_capability *cap)
769{
e578588e 770 struct fimc_dev *fimc = video_drvdata(file);
5f3cc447
SN
771
772 strncpy(cap->driver, fimc->pdev->name, sizeof(cap->driver) - 1);
773 strncpy(cap->card, fimc->pdev->name, sizeof(cap->card) - 1);
774 cap->bus_info[0] = 0;
8f401543 775 cap->capabilities = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE_MPLANE;
5f3cc447
SN
776
777 return 0;
778}
779
cf52df8a
SN
780static int fimc_cap_enum_fmt_mplane(struct file *file, void *priv,
781 struct v4l2_fmtdesc *f)
782{
783 struct fimc_fmt *fmt;
784
785 fmt = fimc_find_format(NULL, NULL, FMT_FLAGS_CAM | FMT_FLAGS_M2M,
786 f->index);
787 if (!fmt)
788 return -EINVAL;
789 strncpy(f->description, fmt->name, sizeof(f->description) - 1);
790 f->pixelformat = fmt->fourcc;
791 if (fmt->fourcc == V4L2_MBUS_FMT_JPEG_1X8)
792 f->flags |= V4L2_FMT_FLAG_COMPRESSED;
793 return 0;
794}
795
237e0265
SN
796/**
797 * fimc_pipeline_try_format - negotiate and/or set formats at pipeline
798 * elements
799 * @ctx: FIMC capture context
800 * @tfmt: media bus format to try/set on subdevs
801 * @fmt_id: fimc pixel format id corresponding to returned @tfmt (output)
802 * @set: true to set format on subdevs, false to try only
803 */
804static int fimc_pipeline_try_format(struct fimc_ctx *ctx,
805 struct v4l2_mbus_framefmt *tfmt,
806 struct fimc_fmt **fmt_id,
807 bool set)
808{
809 struct fimc_dev *fimc = ctx->fimc_dev;
0f735f52
SN
810 struct v4l2_subdev *sd = fimc->pipeline.subdevs[IDX_SENSOR];
811 struct v4l2_subdev *csis = fimc->pipeline.subdevs[IDX_CSIS];
237e0265
SN
812 struct v4l2_subdev_format sfmt;
813 struct v4l2_mbus_framefmt *mf = &sfmt.format;
814 struct fimc_fmt *ffmt = NULL;
815 int ret, i = 0;
816
817 if (WARN_ON(!sd || !tfmt))
818 return -EINVAL;
5f3cc447 819
237e0265
SN
820 memset(&sfmt, 0, sizeof(sfmt));
821 sfmt.format = *tfmt;
822
823 sfmt.which = set ? V4L2_SUBDEV_FORMAT_ACTIVE : V4L2_SUBDEV_FORMAT_TRY;
824 while (1) {
825 ffmt = fimc_find_format(NULL, mf->code != 0 ? &mf->code : NULL,
826 FMT_FLAGS_CAM, i++);
827 if (ffmt == NULL) {
828 /*
829 * Notify user-space if common pixel code for
830 * host and sensor does not exist.
831 */
832 return -EINVAL;
833 }
834 mf->code = tfmt->code = ffmt->mbus_code;
5f3cc447 835
237e0265
SN
836 ret = v4l2_subdev_call(sd, pad, set_fmt, NULL, &sfmt);
837 if (ret)
838 return ret;
839 if (mf->code != tfmt->code) {
840 mf->code = 0;
841 continue;
842 }
b1aa6089 843 if (mf->width != tfmt->width || mf->height != tfmt->height) {
237e0265
SN
844 u32 fcc = ffmt->fourcc;
845 tfmt->width = mf->width;
846 tfmt->height = mf->height;
847 ffmt = fimc_capture_try_format(ctx,
848 &tfmt->width, &tfmt->height,
849 NULL, &fcc, FIMC_SD_PAD_SOURCE);
850 if (ffmt && ffmt->mbus_code)
851 mf->code = ffmt->mbus_code;
b1aa6089
JL
852 if (mf->width != tfmt->width ||
853 mf->height != tfmt->height)
237e0265
SN
854 continue;
855 tfmt->code = mf->code;
856 }
857 if (csis)
858 ret = v4l2_subdev_call(csis, pad, set_fmt, NULL, &sfmt);
5f3cc447 859
237e0265 860 if (mf->code == tfmt->code &&
b1aa6089 861 mf->width == tfmt->width && mf->height == tfmt->height)
237e0265
SN
862 break;
863 }
5f3cc447 864
237e0265
SN
865 if (fmt_id && ffmt)
866 *fmt_id = ffmt;
867 *tfmt = *mf;
5f3cc447 868
237e0265
SN
869 dbg("code: 0x%x, %dx%d, %p", mf->code, mf->width, mf->height, ffmt);
870 return 0;
871}
5f3cc447 872
14783d25
SN
873/**
874 * fimc_get_sensor_frame_desc - query the sensor for media bus frame parameters
875 * @sensor: pointer to the sensor subdev
876 * @plane_fmt: provides plane sizes corresponding to the frame layout entries
877 * @try: true to set the frame parameters, false to query only
878 *
879 * This function is used by this driver only for compressed/blob data formats.
880 */
881static int fimc_get_sensor_frame_desc(struct v4l2_subdev *sensor,
882 struct v4l2_plane_pix_format *plane_fmt,
883 unsigned int num_planes, bool try)
884{
885 struct v4l2_mbus_frame_desc fd;
886 int i, ret;
1c9f5bd7 887 int pad;
14783d25
SN
888
889 for (i = 0; i < num_planes; i++)
890 fd.entry[i].length = plane_fmt[i].sizeimage;
891
1c9f5bd7 892 pad = sensor->entity.num_pads - 1;
14783d25 893 if (try)
1c9f5bd7 894 ret = v4l2_subdev_call(sensor, pad, set_frame_desc, pad, &fd);
14783d25 895 else
1c9f5bd7 896 ret = v4l2_subdev_call(sensor, pad, get_frame_desc, pad, &fd);
14783d25
SN
897
898 if (ret < 0)
899 return ret;
900
901 if (num_planes != fd.num_entries)
902 return -EINVAL;
903
904 for (i = 0; i < num_planes; i++)
905 plane_fmt[i].sizeimage = fd.entry[i].length;
906
907 if (fd.entry[0].length > FIMC_MAX_JPEG_BUF_SIZE) {
908 v4l2_err(sensor->v4l2_dev, "Unsupported buffer size: %u\n",
909 fd.entry[0].length);
910
911 return -EINVAL;
912 }
913
914 return 0;
915}
916
e578588e
SN
917static int fimc_cap_g_fmt_mplane(struct file *file, void *fh,
918 struct v4l2_format *f)
919{
920 struct fimc_dev *fimc = video_drvdata(file);
921 struct fimc_ctx *ctx = fimc->vid_cap.ctx;
922
e578588e
SN
923 return fimc_fill_format(&ctx->d_frame, f);
924}
925
926static int fimc_cap_try_fmt_mplane(struct file *file, void *fh,
927 struct v4l2_format *f)
928{
237e0265 929 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
e578588e
SN
930 struct fimc_dev *fimc = video_drvdata(file);
931 struct fimc_ctx *ctx = fimc->vid_cap.ctx;
237e0265
SN
932 struct v4l2_mbus_framefmt mf;
933 struct fimc_fmt *ffmt = NULL;
934
14783d25 935 if (fimc_jpeg_fourcc(pix->pixelformat)) {
237e0265
SN
936 fimc_capture_try_format(ctx, &pix->width, &pix->height,
937 NULL, &pix->pixelformat,
938 FIMC_SD_PAD_SINK);
939 ctx->s_frame.f_width = pix->width;
940 ctx->s_frame.f_height = pix->height;
941 }
942 ffmt = fimc_capture_try_format(ctx, &pix->width, &pix->height,
943 NULL, &pix->pixelformat,
944 FIMC_SD_PAD_SOURCE);
945 if (!ffmt)
946 return -EINVAL;
947
948 if (!fimc->vid_cap.user_subdev_api) {
14783d25 949 mf.width = pix->width;
237e0265 950 mf.height = pix->height;
14783d25 951 mf.code = ffmt->mbus_code;
237e0265
SN
952 fimc_md_graph_lock(fimc);
953 fimc_pipeline_try_format(ctx, &mf, &ffmt, false);
954 fimc_md_graph_unlock(fimc);
14783d25
SN
955 pix->width = mf.width;
956 pix->height = mf.height;
237e0265
SN
957 if (ffmt)
958 pix->pixelformat = ffmt->fourcc;
959 }
e578588e 960
237e0265 961 fimc_adjust_mplane_format(ffmt, pix->width, pix->height, pix);
14783d25
SN
962
963 if (ffmt->flags & FMT_FLAGS_COMPRESSED)
964 fimc_get_sensor_frame_desc(fimc->pipeline.subdevs[IDX_SENSOR],
965 pix->plane_fmt, ffmt->memplanes, true);
966
4db5e27e 967 return 0;
e578588e
SN
968}
969
14783d25
SN
970static void fimc_capture_mark_jpeg_xfer(struct fimc_ctx *ctx,
971 enum fimc_color_fmt color)
ee7160e5 972{
14783d25
SN
973 bool jpeg = fimc_fmt_is_user_defined(color);
974
ee7160e5
SN
975 ctx->scaler.enabled = !jpeg;
976 fimc_ctrls_activate(ctx, !jpeg);
977
978 if (jpeg)
979 set_bit(ST_CAPT_JPEG, &ctx->fimc_dev->state);
980 else
981 clear_bit(ST_CAPT_JPEG, &ctx->fimc_dev->state);
982}
983
237e0265 984static int fimc_capture_set_format(struct fimc_dev *fimc, struct v4l2_format *f)
5f3cc447 985{
e578588e 986 struct fimc_ctx *ctx = fimc->vid_cap.ctx;
237e0265
SN
987 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
988 struct v4l2_mbus_framefmt *mf = &fimc->vid_cap.mf;
989 struct fimc_frame *ff = &ctx->d_frame;
990 struct fimc_fmt *s_fmt = NULL;
991 int ret, i;
5f3cc447 992
237e0265 993 if (vb2_is_busy(&fimc->vid_cap.vbq))
ef7af59b 994 return -EBUSY;
5f3cc447 995
237e0265 996 /* Pre-configure format at camera interface input, for JPEG only */
14783d25 997 if (fimc_jpeg_fourcc(pix->pixelformat)) {
237e0265
SN
998 fimc_capture_try_format(ctx, &pix->width, &pix->height,
999 NULL, &pix->pixelformat,
1000 FIMC_SD_PAD_SINK);
1001 ctx->s_frame.f_width = pix->width;
1002 ctx->s_frame.f_height = pix->height;
1003 }
1004 /* Try the format at the scaler and the DMA output */
1005 ff->fmt = fimc_capture_try_format(ctx, &pix->width, &pix->height,
1006 NULL, &pix->pixelformat,
1007 FIMC_SD_PAD_SOURCE);
1008 if (!ff->fmt)
8293ebfc 1009 return -EINVAL;
dafb9c70
SN
1010
1011 /* Update RGB Alpha control state and value range */
1012 fimc_alpha_ctrl_update(ctx);
1013
237e0265
SN
1014 /* Try to match format at the host and the sensor */
1015 if (!fimc->vid_cap.user_subdev_api) {
1016 mf->code = ff->fmt->mbus_code;
1017 mf->width = pix->width;
1018 mf->height = pix->height;
1019
1020 fimc_md_graph_lock(fimc);
1021 ret = fimc_pipeline_try_format(ctx, mf, &s_fmt, true);
1022 fimc_md_graph_unlock(fimc);
1023 if (ret)
1024 return ret;
1025 pix->width = mf->width;
1026 pix->height = mf->height;
1027 }
d547ab66 1028
237e0265 1029 fimc_adjust_mplane_format(ff->fmt, pix->width, pix->height, pix);
14783d25
SN
1030
1031 if (ff->fmt->flags & FMT_FLAGS_COMPRESSED) {
1032 ret = fimc_get_sensor_frame_desc(fimc->pipeline.subdevs[IDX_SENSOR],
1033 pix->plane_fmt, ff->fmt->memplanes,
1034 true);
1035 if (ret < 0)
1036 return ret;
1037 }
1038
1039 for (i = 0; i < ff->fmt->memplanes; i++)
d547ab66 1040 ff->payload[i] = pix->plane_fmt[i].sizeimage;
237e0265
SN
1041
1042 set_frame_bounds(ff, pix->width, pix->height);
1043 /* Reset the composition rectangle if not yet configured */
fed07f84 1044 if (!(ctx->state & FIMC_COMPOSE))
237e0265
SN
1045 set_frame_crop(ff, 0, 0, pix->width, pix->height);
1046
14783d25 1047 fimc_capture_mark_jpeg_xfer(ctx, ff->fmt->color);
ee7160e5 1048
237e0265
SN
1049 /* Reset cropping and set format at the camera interface input */
1050 if (!fimc->vid_cap.user_subdev_api) {
1051 ctx->s_frame.fmt = s_fmt;
1052 set_frame_bounds(&ctx->s_frame, pix->width, pix->height);
1053 set_frame_crop(&ctx->s_frame, 0, 0, pix->width, pix->height);
045030fa 1054 }
ef7af59b 1055
237e0265
SN
1056 return ret;
1057}
5f3cc447 1058
237e0265
SN
1059static int fimc_cap_s_fmt_mplane(struct file *file, void *priv,
1060 struct v4l2_format *f)
1061{
1062 struct fimc_dev *fimc = video_drvdata(file);
5f3cc447 1063
237e0265 1064 return fimc_capture_set_format(fimc, f);
5f3cc447
SN
1065}
1066
1067static int fimc_cap_enum_input(struct file *file, void *priv,
3e002182 1068 struct v4l2_input *i)
5f3cc447 1069{
e578588e 1070 struct fimc_dev *fimc = video_drvdata(file);
0f735f52 1071 struct v4l2_subdev *sd = fimc->pipeline.subdevs[IDX_SENSOR];
5f3cc447 1072
3e002182 1073 if (i->index != 0)
5f3cc447
SN
1074 return -EINVAL;
1075
5f3cc447 1076 i->type = V4L2_INPUT_TYPE_CAMERA;
4db5e27e
SN
1077 if (sd)
1078 strlcpy(i->name, sd->name, sizeof(i->name));
5f3cc447
SN
1079 return 0;
1080}
1081
3e002182 1082static int fimc_cap_s_input(struct file *file, void *priv, unsigned int i)
5f3cc447 1083{
3e002182 1084 return i == 0 ? i : -EINVAL;
5f3cc447
SN
1085}
1086
3e002182 1087static int fimc_cap_g_input(struct file *file, void *priv, unsigned int *i)
5f3cc447 1088{
3e002182 1089 *i = 0;
5f3cc447
SN
1090 return 0;
1091}
1092
237e0265
SN
1093/**
1094 * fimc_pipeline_validate - check for formats inconsistencies
1095 * between source and sink pad of each link
1096 *
1097 * Return 0 if all formats match or -EPIPE otherwise.
1098 */
1099static int fimc_pipeline_validate(struct fimc_dev *fimc)
1100{
1101 struct v4l2_subdev_format sink_fmt, src_fmt;
1102 struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
1103 struct v4l2_subdev *sd;
1104 struct media_pad *pad;
1105 int ret;
1106
1107 /* Start with the video capture node pad */
1108 pad = media_entity_remote_source(&vid_cap->vd_pad);
1109 if (pad == NULL)
1110 return -EPIPE;
1111 /* FIMC.{N} subdevice */
1112 sd = media_entity_to_v4l2_subdev(pad->entity);
1113
1114 while (1) {
1115 /* Retrieve format at the sink pad */
1116 pad = &sd->entity.pads[0];
1117 if (!(pad->flags & MEDIA_PAD_FL_SINK))
1118 break;
1119 /* Don't call FIMC subdev operation to avoid nested locking */
693f5c40 1120 if (sd == &fimc->vid_cap.subdev) {
237e0265
SN
1121 struct fimc_frame *ff = &vid_cap->ctx->s_frame;
1122 sink_fmt.format.width = ff->f_width;
1123 sink_fmt.format.height = ff->f_height;
1124 sink_fmt.format.code = ff->fmt ? ff->fmt->mbus_code : 0;
1125 } else {
1126 sink_fmt.pad = pad->index;
1127 sink_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
1128 ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &sink_fmt);
1129 if (ret < 0 && ret != -ENOIOCTLCMD)
1130 return -EPIPE;
1131 }
1132 /* Retrieve format at the source pad */
1133 pad = media_entity_remote_source(pad);
1134 if (pad == NULL ||
1135 media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
1136 break;
1137
1138 sd = media_entity_to_v4l2_subdev(pad->entity);
1139 src_fmt.pad = pad->index;
1140 src_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
1141 ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &src_fmt);
1142 if (ret < 0 && ret != -ENOIOCTLCMD)
1143 return -EPIPE;
1144
1145 if (src_fmt.format.width != sink_fmt.format.width ||
1146 src_fmt.format.height != sink_fmt.format.height ||
1147 src_fmt.format.code != sink_fmt.format.code)
1148 return -EPIPE;
14783d25
SN
1149
1150 if (sd == fimc->pipeline.subdevs[IDX_SENSOR] &&
1151 fimc_user_defined_mbus_fmt(src_fmt.format.code)) {
1152 struct v4l2_plane_pix_format plane_fmt[FIMC_MAX_PLANES];
1153 struct fimc_frame *frame = &vid_cap->ctx->d_frame;
1154 unsigned int i;
1155
1156 ret = fimc_get_sensor_frame_desc(sd, plane_fmt,
1157 frame->fmt->memplanes,
1158 false);
1159 if (ret < 0)
1160 return -EPIPE;
1161
1162 for (i = 0; i < frame->fmt->memplanes; i++)
1163 if (frame->payload[i] < plane_fmt[i].sizeimage)
1164 return -EPIPE;
1165 }
237e0265
SN
1166 }
1167 return 0;
1168}
1169
5f3cc447 1170static int fimc_cap_streamon(struct file *file, void *priv,
2dab38e2 1171 enum v4l2_buf_type type)
5f3cc447 1172{
e578588e 1173 struct fimc_dev *fimc = video_drvdata(file);
4db5e27e 1174 struct fimc_pipeline *p = &fimc->pipeline;
f676fa06 1175 struct v4l2_subdev *sd = p->subdevs[IDX_SENSOR];
237e0265 1176 int ret;
5f3cc447 1177
4db5e27e 1178 if (fimc_capture_active(fimc))
8293ebfc 1179 return -EBUSY;
5f3cc447 1180
f676fa06 1181 ret = media_entity_pipeline_start(&sd->entity, p->m_pipeline);
a60a2959
SA
1182 if (ret < 0)
1183 return ret;
5f3cc447 1184
237e0265
SN
1185 if (fimc->vid_cap.user_subdev_api) {
1186 ret = fimc_pipeline_validate(fimc);
f676fa06
SK
1187 if (ret < 0) {
1188 media_entity_pipeline_stop(&sd->entity);
237e0265 1189 return ret;
f676fa06 1190 }
237e0265 1191 }
8293ebfc 1192 return vb2_streamon(&fimc->vid_cap.vbq, type);
5f3cc447
SN
1193}
1194
1195static int fimc_cap_streamoff(struct file *file, void *priv,
8293ebfc 1196 enum v4l2_buf_type type)
5f3cc447 1197{
e578588e 1198 struct fimc_dev *fimc = video_drvdata(file);
0f735f52 1199 struct v4l2_subdev *sd = fimc->pipeline.subdevs[IDX_SENSOR];
4db5e27e 1200 int ret;
5f3cc447 1201
4db5e27e
SN
1202 ret = vb2_streamoff(&fimc->vid_cap.vbq, type);
1203 if (ret == 0)
1204 media_entity_pipeline_stop(&sd->entity);
1205 return ret;
5f3cc447
SN
1206}
1207
1208static int fimc_cap_reqbufs(struct file *file, void *priv,
ef7af59b 1209 struct v4l2_requestbuffers *reqbufs)
5f3cc447 1210{
e578588e
SN
1211 struct fimc_dev *fimc = video_drvdata(file);
1212 int ret = vb2_reqbufs(&fimc->vid_cap.vbq, reqbufs);
5f3cc447 1213
5f3cc447 1214 if (!ret)
e578588e 1215 fimc->vid_cap.reqbufs_count = reqbufs->count;
5f3cc447
SN
1216 return ret;
1217}
1218
1219static int fimc_cap_querybuf(struct file *file, void *priv,
1220 struct v4l2_buffer *buf)
1221{
e578588e 1222 struct fimc_dev *fimc = video_drvdata(file);
5f3cc447 1223
e578588e 1224 return vb2_querybuf(&fimc->vid_cap.vbq, buf);
5f3cc447
SN
1225}
1226
1227static int fimc_cap_qbuf(struct file *file, void *priv,
1228 struct v4l2_buffer *buf)
1229{
e578588e
SN
1230 struct fimc_dev *fimc = video_drvdata(file);
1231
1232 return vb2_qbuf(&fimc->vid_cap.vbq, buf);
5f3cc447
SN
1233}
1234
b28d61b6
TS
1235static int fimc_cap_expbuf(struct file *file, void *priv,
1236 struct v4l2_exportbuffer *eb)
1237{
1238 struct fimc_dev *fimc = video_drvdata(file);
1239
1240 return vb2_expbuf(&fimc->vid_cap.vbq, eb);
1241}
1242
5f3cc447
SN
1243static int fimc_cap_dqbuf(struct file *file, void *priv,
1244 struct v4l2_buffer *buf)
1245{
e578588e
SN
1246 struct fimc_dev *fimc = video_drvdata(file);
1247
1248 return vb2_dqbuf(&fimc->vid_cap.vbq, buf, file->f_flags & O_NONBLOCK);
5f3cc447
SN
1249}
1250
3b4c34aa
SN
1251static int fimc_cap_create_bufs(struct file *file, void *priv,
1252 struct v4l2_create_buffers *create)
1253{
1254 struct fimc_dev *fimc = video_drvdata(file);
1255
1256 return vb2_create_bufs(&fimc->vid_cap.vbq, create);
1257}
1258
1259static int fimc_cap_prepare_buf(struct file *file, void *priv,
1260 struct v4l2_buffer *b)
1261{
1262 struct fimc_dev *fimc = video_drvdata(file);
1263
1264 return vb2_prepare_buf(&fimc->vid_cap.vbq, b);
1265}
1266
f9331d11
SN
1267static int fimc_cap_g_selection(struct file *file, void *fh,
1268 struct v4l2_selection *s)
e004e02f 1269{
e578588e 1270 struct fimc_dev *fimc = video_drvdata(file);
f9331d11
SN
1271 struct fimc_ctx *ctx = fimc->vid_cap.ctx;
1272 struct fimc_frame *f = &ctx->s_frame;
e004e02f 1273
f9331d11 1274 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
e004e02f
SN
1275 return -EINVAL;
1276
f9331d11
SN
1277 switch (s->target) {
1278 case V4L2_SEL_TGT_COMPOSE_DEFAULT:
1279 case V4L2_SEL_TGT_COMPOSE_BOUNDS:
1280 f = &ctx->d_frame;
1281 case V4L2_SEL_TGT_CROP_BOUNDS:
1282 case V4L2_SEL_TGT_CROP_DEFAULT:
1283 s->r.left = 0;
1284 s->r.top = 0;
1285 s->r.width = f->o_width;
1286 s->r.height = f->o_height;
1287 return 0;
e004e02f 1288
c1334823 1289 case V4L2_SEL_TGT_COMPOSE:
f9331d11 1290 f = &ctx->d_frame;
c1334823 1291 case V4L2_SEL_TGT_CROP:
f9331d11
SN
1292 s->r.left = f->offs_h;
1293 s->r.top = f->offs_v;
1294 s->r.width = f->width;
1295 s->r.height = f->height;
1296 return 0;
1297 }
1298
1299 return -EINVAL;
e004e02f
SN
1300}
1301
f9331d11 1302/* Return 1 if rectangle a is enclosed in rectangle b, or 0 otherwise. */
7e566be2 1303static int enclosed_rectangle(struct v4l2_rect *a, struct v4l2_rect *b)
e004e02f 1304{
f9331d11
SN
1305 if (a->left < b->left || a->top < b->top)
1306 return 0;
1307 if (a->left + a->width > b->left + b->width)
1308 return 0;
1309 if (a->top + a->height > b->top + b->height)
1310 return 0;
e004e02f 1311
f9331d11 1312 return 1;
e004e02f
SN
1313}
1314
f9331d11
SN
1315static int fimc_cap_s_selection(struct file *file, void *fh,
1316 struct v4l2_selection *s)
5f3cc447 1317{
e578588e
SN
1318 struct fimc_dev *fimc = video_drvdata(file);
1319 struct fimc_ctx *ctx = fimc->vid_cap.ctx;
f9331d11
SN
1320 struct v4l2_rect rect = s->r;
1321 struct fimc_frame *f;
237e0265 1322 unsigned long flags;
f9331d11
SN
1323
1324 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1325 return -EINVAL;
1326
c1334823 1327 if (s->target == V4L2_SEL_TGT_COMPOSE)
f9331d11 1328 f = &ctx->d_frame;
c1334823 1329 else if (s->target == V4L2_SEL_TGT_CROP)
f9331d11 1330 f = &ctx->s_frame;
fed07f84 1331 else
f9331d11 1332 return -EINVAL;
f9331d11 1333
fed07f84 1334 fimc_capture_try_selection(ctx, &rect, s->target);
f9331d11
SN
1335
1336 if (s->flags & V4L2_SEL_FLAG_LE &&
1337 !enclosed_rectangle(&rect, &s->r))
1338 return -ERANGE;
5f3cc447 1339
f9331d11
SN
1340 if (s->flags & V4L2_SEL_FLAG_GE &&
1341 !enclosed_rectangle(&s->r, &rect))
1342 return -ERANGE;
5f3cc447 1343
f9331d11 1344 s->r = rect;
237e0265 1345 spin_lock_irqsave(&fimc->slock, flags);
f9331d11
SN
1346 set_frame_crop(f, s->r.left, s->r.top, s->r.width,
1347 s->r.height);
237e0265 1348 spin_unlock_irqrestore(&fimc->slock, flags);
8293ebfc 1349
f9331d11 1350 set_bit(ST_CAPT_APPLY_CFG, &fimc->state);
8293ebfc 1351 return 0;
5f3cc447
SN
1352}
1353
5f3cc447
SN
1354static const struct v4l2_ioctl_ops fimc_capture_ioctl_ops = {
1355 .vidioc_querycap = fimc_vidioc_querycap_capture,
1356
cf52df8a 1357 .vidioc_enum_fmt_vid_cap_mplane = fimc_cap_enum_fmt_mplane,
e578588e 1358 .vidioc_try_fmt_vid_cap_mplane = fimc_cap_try_fmt_mplane,
ef7af59b 1359 .vidioc_s_fmt_vid_cap_mplane = fimc_cap_s_fmt_mplane,
e578588e 1360 .vidioc_g_fmt_vid_cap_mplane = fimc_cap_g_fmt_mplane,
5f3cc447
SN
1361
1362 .vidioc_reqbufs = fimc_cap_reqbufs,
1363 .vidioc_querybuf = fimc_cap_querybuf,
1364
1365 .vidioc_qbuf = fimc_cap_qbuf,
1366 .vidioc_dqbuf = fimc_cap_dqbuf,
b28d61b6 1367 .vidioc_expbuf = fimc_cap_expbuf,
5f3cc447 1368
3b4c34aa
SN
1369 .vidioc_prepare_buf = fimc_cap_prepare_buf,
1370 .vidioc_create_bufs = fimc_cap_create_bufs,
1371
5f3cc447
SN
1372 .vidioc_streamon = fimc_cap_streamon,
1373 .vidioc_streamoff = fimc_cap_streamoff,
1374
f9331d11
SN
1375 .vidioc_g_selection = fimc_cap_g_selection,
1376 .vidioc_s_selection = fimc_cap_s_selection,
5f3cc447
SN
1377
1378 .vidioc_enum_input = fimc_cap_enum_input,
1379 .vidioc_s_input = fimc_cap_s_input,
1380 .vidioc_g_input = fimc_cap_g_input,
1381};
1382
237e0265 1383/* Capture subdev media entity operations */
d09a7dc8
SN
1384static int fimc_link_setup(struct media_entity *entity,
1385 const struct media_pad *local,
1386 const struct media_pad *remote, u32 flags)
1387{
237e0265
SN
1388 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
1389 struct fimc_dev *fimc = v4l2_get_subdevdata(sd);
1390
1391 if (media_entity_type(remote->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
1392 return -EINVAL;
d09a7dc8
SN
1393
1394 if (WARN_ON(fimc == NULL))
1395 return 0;
1396
1397 dbg("%s --> %s, flags: 0x%x. input: 0x%x",
1398 local->entity->name, remote->entity->name, flags,
1399 fimc->vid_cap.input);
1400
1401 if (flags & MEDIA_LNK_FL_ENABLED) {
1402 if (fimc->vid_cap.input != 0)
1403 return -EBUSY;
1404 fimc->vid_cap.input = sd->grp_id;
1405 return 0;
1406 }
1407
1408 fimc->vid_cap.input = 0;
1409 return 0;
1410}
1411
237e0265 1412static const struct media_entity_operations fimc_sd_media_ops = {
d09a7dc8
SN
1413 .link_setup = fimc_link_setup,
1414};
1415
e1d72f4d
SN
1416/**
1417 * fimc_sensor_notify - v4l2_device notification from a sensor subdev
1418 * @sd: pointer to a subdev generating the notification
1419 * @notification: the notification type, must be S5P_FIMC_TX_END_NOTIFY
1420 * @arg: pointer to an u32 type integer that stores the frame payload value
1421 *
1422 * The End Of Frame notification sent by sensor subdev in its still capture
1423 * mode. If there is only a single VSYNC generated by the sensor at the
1424 * beginning of a frame transmission, FIMC does not issue the LastIrq
1425 * (end of frame) interrupt. And this notification is used to complete the
1426 * frame capture and returning a buffer to user-space. Subdev drivers should
1427 * call this notification from their last 'End of frame capture' interrupt.
1428 */
1429void fimc_sensor_notify(struct v4l2_subdev *sd, unsigned int notification,
1430 void *arg)
1431{
1432 struct fimc_sensor_info *sensor;
1433 struct fimc_vid_buffer *buf;
1434 struct fimc_md *fmd;
1435 struct fimc_dev *fimc;
1436 unsigned long flags;
1437
1438 if (sd == NULL)
1439 return;
1440
1441 sensor = v4l2_get_subdev_hostdata(sd);
1442 fmd = entity_to_fimc_mdev(&sd->entity);
1443
1444 spin_lock_irqsave(&fmd->slock, flags);
1445 fimc = sensor ? sensor->host : NULL;
1446
1447 if (fimc && arg && notification == S5P_FIMC_TX_END_NOTIFY &&
1448 test_bit(ST_CAPT_PEND, &fimc->state)) {
1449 unsigned long irq_flags;
1450 spin_lock_irqsave(&fimc->slock, irq_flags);
1451 if (!list_empty(&fimc->vid_cap.active_buf_q)) {
1452 buf = list_entry(fimc->vid_cap.active_buf_q.next,
1453 struct fimc_vid_buffer, list);
1454 vb2_set_plane_payload(&buf->vb, 0, *((u32 *)arg));
1455 }
97d97422 1456 fimc_capture_irq_handler(fimc, 1);
e1d72f4d
SN
1457 fimc_deactivate_capture(fimc);
1458 spin_unlock_irqrestore(&fimc->slock, irq_flags);
1459 }
1460 spin_unlock_irqrestore(&fmd->slock, flags);
1461}
1462
237e0265
SN
1463static int fimc_subdev_enum_mbus_code(struct v4l2_subdev *sd,
1464 struct v4l2_subdev_fh *fh,
1465 struct v4l2_subdev_mbus_code_enum *code)
1466{
1467 struct fimc_fmt *fmt;
1468
1469 fmt = fimc_find_format(NULL, NULL, FMT_FLAGS_CAM, code->index);
1470 if (!fmt)
1471 return -EINVAL;
1472 code->code = fmt->mbus_code;
1473 return 0;
1474}
1475
1476static int fimc_subdev_get_fmt(struct v4l2_subdev *sd,
1477 struct v4l2_subdev_fh *fh,
1478 struct v4l2_subdev_format *fmt)
1479{
1480 struct fimc_dev *fimc = v4l2_get_subdevdata(sd);
1481 struct fimc_ctx *ctx = fimc->vid_cap.ctx;
1482 struct v4l2_mbus_framefmt *mf;
1483 struct fimc_frame *ff;
1484
1485 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1486 mf = v4l2_subdev_get_try_format(fh, fmt->pad);
1487 fmt->format = *mf;
1488 return 0;
1489 }
1490 mf = &fmt->format;
1491 mf->colorspace = V4L2_COLORSPACE_JPEG;
1492 ff = fmt->pad == FIMC_SD_PAD_SINK ? &ctx->s_frame : &ctx->d_frame;
1493
1494 mutex_lock(&fimc->lock);
1495 /* The pixel code is same on both input and output pad */
1496 if (!WARN_ON(ctx->s_frame.fmt == NULL))
1497 mf->code = ctx->s_frame.fmt->mbus_code;
1498 mf->width = ff->f_width;
1499 mf->height = ff->f_height;
1500 mutex_unlock(&fimc->lock);
1501
1502 return 0;
1503}
1504
1505static int fimc_subdev_set_fmt(struct v4l2_subdev *sd,
1506 struct v4l2_subdev_fh *fh,
1507 struct v4l2_subdev_format *fmt)
1508{
1509 struct fimc_dev *fimc = v4l2_get_subdevdata(sd);
1510 struct v4l2_mbus_framefmt *mf = &fmt->format;
1511 struct fimc_ctx *ctx = fimc->vid_cap.ctx;
1512 struct fimc_frame *ff;
1513 struct fimc_fmt *ffmt;
1514
1515 dbg("pad%d: code: 0x%x, %dx%d",
1516 fmt->pad, mf->code, mf->width, mf->height);
1517
1518 if (fmt->pad == FIMC_SD_PAD_SOURCE &&
1519 vb2_is_busy(&fimc->vid_cap.vbq))
1520 return -EBUSY;
1521
1522 mutex_lock(&fimc->lock);
1523 ffmt = fimc_capture_try_format(ctx, &mf->width, &mf->height,
1524 &mf->code, NULL, fmt->pad);
1525 mutex_unlock(&fimc->lock);
1526 mf->colorspace = V4L2_COLORSPACE_JPEG;
1527
1528 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1529 mf = v4l2_subdev_get_try_format(fh, fmt->pad);
1530 *mf = fmt->format;
1531 return 0;
1532 }
dafb9c70
SN
1533 /* Update RGB Alpha control state and value range */
1534 fimc_alpha_ctrl_update(ctx);
1535
14783d25 1536 fimc_capture_mark_jpeg_xfer(ctx, ffmt->color);
ee7160e5 1537
237e0265
SN
1538 ff = fmt->pad == FIMC_SD_PAD_SINK ?
1539 &ctx->s_frame : &ctx->d_frame;
1540
1541 mutex_lock(&fimc->lock);
1542 set_frame_bounds(ff, mf->width, mf->height);
393a23fc 1543 fimc->vid_cap.mf = *mf;
237e0265
SN
1544 ff->fmt = ffmt;
1545
1546 /* Reset the crop rectangle if required. */
fed07f84 1547 if (!(fmt->pad == FIMC_SD_PAD_SOURCE && (ctx->state & FIMC_COMPOSE)))
237e0265
SN
1548 set_frame_crop(ff, 0, 0, mf->width, mf->height);
1549
1550 if (fmt->pad == FIMC_SD_PAD_SINK)
fed07f84 1551 ctx->state &= ~FIMC_COMPOSE;
237e0265
SN
1552 mutex_unlock(&fimc->lock);
1553 return 0;
1554}
1555
fed07f84
SN
1556static int fimc_subdev_get_selection(struct v4l2_subdev *sd,
1557 struct v4l2_subdev_fh *fh,
1558 struct v4l2_subdev_selection *sel)
237e0265
SN
1559{
1560 struct fimc_dev *fimc = v4l2_get_subdevdata(sd);
1561 struct fimc_ctx *ctx = fimc->vid_cap.ctx;
fed07f84
SN
1562 struct fimc_frame *f = &ctx->s_frame;
1563 struct v4l2_rect *r = &sel->r;
1564 struct v4l2_rect *try_sel;
1565
1566 if (sel->pad != FIMC_SD_PAD_SINK)
1567 return -EINVAL;
1568
1569 mutex_lock(&fimc->lock);
237e0265 1570
fed07f84 1571 switch (sel->target) {
5689b288 1572 case V4L2_SEL_TGT_COMPOSE_BOUNDS:
fed07f84 1573 f = &ctx->d_frame;
5689b288 1574 case V4L2_SEL_TGT_CROP_BOUNDS:
fed07f84
SN
1575 r->width = f->o_width;
1576 r->height = f->o_height;
1577 r->left = 0;
1578 r->top = 0;
1579 mutex_unlock(&fimc->lock);
237e0265 1580 return 0;
fed07f84 1581
5689b288 1582 case V4L2_SEL_TGT_CROP:
fed07f84
SN
1583 try_sel = v4l2_subdev_get_try_crop(fh, sel->pad);
1584 break;
5689b288 1585 case V4L2_SEL_TGT_COMPOSE:
fed07f84
SN
1586 try_sel = v4l2_subdev_get_try_compose(fh, sel->pad);
1587 f = &ctx->d_frame;
1588 break;
1589 default:
1590 mutex_unlock(&fimc->lock);
1591 return -EINVAL;
237e0265 1592 }
237e0265 1593
fed07f84
SN
1594 if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
1595 sel->r = *try_sel;
1596 } else {
1597 r->left = f->offs_h;
1598 r->top = f->offs_v;
1599 r->width = f->width;
1600 r->height = f->height;
1601 }
237e0265 1602
fed07f84
SN
1603 dbg("target %#x: l:%d, t:%d, %dx%d, f_w: %d, f_h: %d",
1604 sel->pad, r->left, r->top, r->width, r->height,
1605 f->f_width, f->f_height);
237e0265 1606
fed07f84 1607 mutex_unlock(&fimc->lock);
237e0265
SN
1608 return 0;
1609}
1610
fed07f84
SN
1611static int fimc_subdev_set_selection(struct v4l2_subdev *sd,
1612 struct v4l2_subdev_fh *fh,
1613 struct v4l2_subdev_selection *sel)
237e0265
SN
1614{
1615 struct fimc_dev *fimc = v4l2_get_subdevdata(sd);
1616 struct fimc_ctx *ctx = fimc->vid_cap.ctx;
fed07f84
SN
1617 struct fimc_frame *f = &ctx->s_frame;
1618 struct v4l2_rect *r = &sel->r;
1619 struct v4l2_rect *try_sel;
237e0265
SN
1620 unsigned long flags;
1621
fed07f84
SN
1622 if (sel->pad != FIMC_SD_PAD_SINK)
1623 return -EINVAL;
237e0265
SN
1624
1625 mutex_lock(&fimc->lock);
c1334823 1626 fimc_capture_try_selection(ctx, r, V4L2_SEL_TGT_CROP);
237e0265 1627
fed07f84 1628 switch (sel->target) {
5689b288 1629 case V4L2_SEL_TGT_COMPOSE_BOUNDS:
fed07f84 1630 f = &ctx->d_frame;
5689b288 1631 case V4L2_SEL_TGT_CROP_BOUNDS:
fed07f84
SN
1632 r->width = f->o_width;
1633 r->height = f->o_height;
1634 r->left = 0;
1635 r->top = 0;
5be4fe63 1636 mutex_unlock(&fimc->lock);
237e0265 1637 return 0;
fed07f84 1638
5689b288 1639 case V4L2_SEL_TGT_CROP:
fed07f84
SN
1640 try_sel = v4l2_subdev_get_try_crop(fh, sel->pad);
1641 break;
5689b288 1642 case V4L2_SEL_TGT_COMPOSE:
fed07f84
SN
1643 try_sel = v4l2_subdev_get_try_compose(fh, sel->pad);
1644 f = &ctx->d_frame;
1645 break;
1646 default:
1647 mutex_unlock(&fimc->lock);
1648 return -EINVAL;
237e0265 1649 }
237e0265 1650
fed07f84
SN
1651 if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
1652 *try_sel = sel->r;
1653 } else {
1654 spin_lock_irqsave(&fimc->slock, flags);
1655 set_frame_crop(f, r->left, r->top, r->width, r->height);
1656 set_bit(ST_CAPT_APPLY_CFG, &fimc->state);
1657 spin_unlock_irqrestore(&fimc->slock, flags);
5689b288 1658 if (sel->target == V4L2_SEL_TGT_COMPOSE)
fed07f84
SN
1659 ctx->state |= FIMC_COMPOSE;
1660 }
237e0265 1661
fed07f84 1662 dbg("target %#x: (%d,%d)/%dx%d", sel->target, r->left, r->top,
237e0265
SN
1663 r->width, r->height);
1664
1665 mutex_unlock(&fimc->lock);
1666 return 0;
1667}
1668
1669static struct v4l2_subdev_pad_ops fimc_subdev_pad_ops = {
1670 .enum_mbus_code = fimc_subdev_enum_mbus_code,
fed07f84
SN
1671 .get_selection = fimc_subdev_get_selection,
1672 .set_selection = fimc_subdev_set_selection,
237e0265
SN
1673 .get_fmt = fimc_subdev_get_fmt,
1674 .set_fmt = fimc_subdev_set_fmt,
237e0265
SN
1675};
1676
1677static struct v4l2_subdev_ops fimc_subdev_ops = {
1678 .pad = &fimc_subdev_pad_ops,
1679};
1680
237e0265
SN
1681/* Set default format at the sensor and host interface */
1682static int fimc_capture_set_default_format(struct fimc_dev *fimc)
1683{
1684 struct v4l2_format fmt = {
1685 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE,
1686 .fmt.pix_mp = {
1687 .width = 640,
1688 .height = 480,
1689 .pixelformat = V4L2_PIX_FMT_YUYV,
1690 .field = V4L2_FIELD_NONE,
1691 .colorspace = V4L2_COLORSPACE_JPEG,
1692 },
1693 };
1694
1695 return fimc_capture_set_format(fimc, &fmt);
1696}
1697
ef7af59b 1698/* fimc->lock must be already initialized */
693f5c40 1699static int fimc_register_capture_device(struct fimc_dev *fimc,
30c9939d 1700 struct v4l2_device *v4l2_dev)
5f3cc447 1701{
31d34d9b 1702 struct video_device *vfd = &fimc->vid_cap.vfd;
5f3cc447
SN
1703 struct fimc_vid_cap *vid_cap;
1704 struct fimc_ctx *ctx;
2dab38e2 1705 struct vb2_queue *q;
30c9939d 1706 int ret = -ENOMEM;
5f3cc447 1707
26ee7f47 1708 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
5f3cc447
SN
1709 if (!ctx)
1710 return -ENOMEM;
1711
1712 ctx->fimc_dev = fimc;
3d112d9a
SN
1713 ctx->in_path = FIMC_IO_CAMERA;
1714 ctx->out_path = FIMC_IO_DMA;
5f3cc447 1715 ctx->state = FIMC_CTX_CAP;
237e0265 1716 ctx->s_frame.fmt = fimc_find_format(NULL, NULL, FMT_FLAGS_CAM, 0);
693f5c40 1717 ctx->d_frame.fmt = ctx->s_frame.fmt;
5f3cc447 1718
31d34d9b 1719 memset(vfd, 0, sizeof(*vfd));
693f5c40 1720 snprintf(vfd->name, sizeof(vfd->name), "fimc.%d.capture", fimc->id);
5f3cc447
SN
1721
1722 vfd->fops = &fimc_capture_fops;
1723 vfd->ioctl_ops = &fimc_capture_ioctl_ops;
574e1717 1724 vfd->v4l2_dev = v4l2_dev;
5f3cc447 1725 vfd->minor = -1;
31d34d9b 1726 vfd->release = video_device_release_empty;
8293ebfc 1727 vfd->lock = &fimc->lock;
c2d430af 1728
5f3cc447
SN
1729 video_set_drvdata(vfd, fimc);
1730
1731 vid_cap = &fimc->vid_cap;
5f3cc447
SN
1732 vid_cap->active_buf_cnt = 0;
1733 vid_cap->reqbufs_count = 0;
1734 vid_cap->refcnt = 0;
5f3cc447
SN
1735
1736 INIT_LIST_HEAD(&vid_cap->pending_buf_q);
1737 INIT_LIST_HEAD(&vid_cap->active_buf_q);
5f3cc447
SN
1738 vid_cap->ctx = ctx;
1739
2dab38e2
SN
1740 q = &fimc->vid_cap.vbq;
1741 memset(q, 0, sizeof(*q));
ef7af59b 1742 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
9bd09fd7 1743 q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
2dab38e2
SN
1744 q->drv_priv = fimc->vid_cap.ctx;
1745 q->ops = &fimc_capture_qops;
1746 q->mem_ops = &vb2_dma_contig_memops;
1747 q->buf_struct_size = sizeof(struct fimc_vid_buffer);
1748
41fd087f
SN
1749 ret = vb2_queue_init(q);
1750 if (ret)
1751 goto err_ent;
5f3cc447 1752
693f5c40
SN
1753 vid_cap->vd_pad.flags = MEDIA_PAD_FL_SINK;
1754 ret = media_entity_init(&vfd->entity, 1, &vid_cap->vd_pad, 0);
574e1717
SN
1755 if (ret)
1756 goto err_ent;
693f5c40
SN
1757
1758 ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
237e0265 1759 if (ret)
693f5c40
SN
1760 goto err_vd;
1761
1762 v4l2_info(v4l2_dev, "Registered %s as /dev/%s\n",
1763 vfd->name, video_device_node_name(vfd));
574e1717 1764
9448ab7d 1765 vfd->ctrl_handler = &ctx->ctrls.handler;
5f3cc447
SN
1766 return 0;
1767
693f5c40 1768err_vd:
237e0265 1769 media_entity_cleanup(&vfd->entity);
574e1717 1770err_ent:
cfd77310 1771 kfree(ctx);
5f3cc447
SN
1772 return ret;
1773}
1774
693f5c40 1775static int fimc_capture_subdev_registered(struct v4l2_subdev *sd)
5f3cc447 1776{
693f5c40
SN
1777 struct fimc_dev *fimc = v4l2_get_subdevdata(sd);
1778 int ret;
5f3cc447 1779
bbc5296f
SN
1780 if (fimc == NULL)
1781 return -ENXIO;
1782
693f5c40
SN
1783 ret = fimc_register_m2m_device(fimc, sd->v4l2_dev);
1784 if (ret)
1785 return ret;
1786
97d66c47
SN
1787 fimc->pipeline_ops = v4l2_get_subdev_hostdata(sd);
1788
693f5c40 1789 ret = fimc_register_capture_device(fimc, sd->v4l2_dev);
97d66c47 1790 if (ret) {
693f5c40 1791 fimc_unregister_m2m_device(fimc);
97d66c47
SN
1792 fimc->pipeline_ops = NULL;
1793 }
693f5c40
SN
1794
1795 return ret;
1796}
1797
1798static void fimc_capture_subdev_unregistered(struct v4l2_subdev *sd)
1799{
1800 struct fimc_dev *fimc = v4l2_get_subdevdata(sd);
1801
1802 if (fimc == NULL)
1803 return;
1804
1805 fimc_unregister_m2m_device(fimc);
1806
31d34d9b
SN
1807 if (video_is_registered(&fimc->vid_cap.vfd)) {
1808 video_unregister_device(&fimc->vid_cap.vfd);
1809 media_entity_cleanup(&fimc->vid_cap.vfd.entity);
97d66c47 1810 fimc->pipeline_ops = NULL;
574e1717
SN
1811 }
1812 kfree(fimc->vid_cap.ctx);
96a85742 1813 fimc->vid_cap.ctx = NULL;
5f3cc447 1814}
693f5c40
SN
1815
1816static const struct v4l2_subdev_internal_ops fimc_capture_sd_internal_ops = {
1817 .registered = fimc_capture_subdev_registered,
1818 .unregistered = fimc_capture_subdev_unregistered,
1819};
1820
1821int fimc_initialize_capture_subdev(struct fimc_dev *fimc)
1822{
1823 struct v4l2_subdev *sd = &fimc->vid_cap.subdev;
1824 int ret;
1825
1826 v4l2_subdev_init(sd, &fimc_subdev_ops);
1827 sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
1828 snprintf(sd->name, sizeof(sd->name), "FIMC.%d", fimc->pdev->id);
1829
1830 fimc->vid_cap.sd_pads[FIMC_SD_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
1831 fimc->vid_cap.sd_pads[FIMC_SD_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
1832 ret = media_entity_init(&sd->entity, FIMC_SD_PADS_NUM,
1833 fimc->vid_cap.sd_pads, 0);
1834 if (ret)
1835 return ret;
1836
1837 sd->entity.ops = &fimc_sd_media_ops;
1838 sd->internal_ops = &fimc_capture_sd_internal_ops;
1839 v4l2_set_subdevdata(sd, fimc);
1840 return 0;
1841}
1842
1843void fimc_unregister_capture_subdev(struct fimc_dev *fimc)
1844{
1845 struct v4l2_subdev *sd = &fimc->vid_cap.subdev;
1846
1847 v4l2_device_unregister_subdev(sd);
1848 media_entity_cleanup(&sd->entity);
1849 v4l2_set_subdevdata(sd, NULL);
1850}