]>
Commit | Line | Data |
---|---|---|
2874c5fd | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
91884734 KD |
2 | /* |
3 | * Samsung S5P G2D - 2D Graphics Accelerator Driver | |
4 | * | |
5 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
6 | * Kamil Debski, <k.debski@samsung.com> | |
91884734 KD |
7 | */ |
8 | ||
9 | /* General Registers */ | |
10 | #define SOFT_RESET_REG 0x0000 /* Software reset reg */ | |
11 | #define INTEN_REG 0x0004 /* Interrupt Enable reg */ | |
12 | #define INTC_PEND_REG 0x000C /* Interrupt Control Pending reg */ | |
13 | #define FIFO_STAT_REG 0x0010 /* Command FIFO Status reg */ | |
14 | #define AXI_ID_MODE_REG 0x0014 /* AXI Read ID Mode reg */ | |
15 | #define CACHECTL_REG 0x0018 /* Cache & Buffer clear reg */ | |
16 | #define AXI_MODE_REG 0x001C /* AXI Mode reg */ | |
17 | ||
18 | /* Command Registers */ | |
19 | #define BITBLT_START_REG 0x0100 /* BitBLT Start reg */ | |
20 | #define BITBLT_COMMAND_REG 0x0104 /* Command reg for BitBLT */ | |
21 | ||
22 | /* Parameter Setting Registers (Rotate & Direction) */ | |
23 | #define ROTATE_REG 0x0200 /* Rotation reg */ | |
24 | #define SRC_MSK_DIRECT_REG 0x0204 /* Src and Mask Direction reg */ | |
25 | #define DST_PAT_DIRECT_REG 0x0208 /* Dest and Pattern Direction reg */ | |
26 | ||
27 | /* Parameter Setting Registers (Src) */ | |
28 | #define SRC_SELECT_REG 0x0300 /* Src Image Selection reg */ | |
29 | #define SRC_BASE_ADDR_REG 0x0304 /* Src Image Base Address reg */ | |
30 | #define SRC_STRIDE_REG 0x0308 /* Src Stride reg */ | |
31 | #define SRC_COLOR_MODE_REG 0x030C /* Src Image Color Mode reg */ | |
32 | #define SRC_LEFT_TOP_REG 0x0310 /* Src Left Top Coordinate reg */ | |
33 | #define SRC_RIGHT_BOTTOM_REG 0x0314 /* Src Right Bottom Coordinate reg */ | |
62ce272d SK |
34 | #define SRC_SCALE_CTRL_REG 0x0328 /* Src Scaling type select */ |
35 | #define SRC_XSCALE_REG 0x032c /* Src X Scaling ratio */ | |
36 | #define SRC_YSCALE_REG 0x0330 /* Src Y Scaling ratio */ | |
91884734 KD |
37 | |
38 | /* Parameter Setting Registers (Dest) */ | |
39 | #define DST_SELECT_REG 0x0400 /* Dest Image Selection reg */ | |
40 | #define DST_BASE_ADDR_REG 0x0404 /* Dest Image Base Address reg */ | |
41 | #define DST_STRIDE_REG 0x0408 /* Dest Stride reg */ | |
42 | #define DST_COLOR_MODE_REG 0x040C /* Dest Image Color Mode reg */ | |
43 | #define DST_LEFT_TOP_REG 0x0410 /* Dest Left Top Coordinate reg */ | |
44 | #define DST_RIGHT_BOTTOM_REG 0x0414 /* Dest Right Bottom Coordinate reg */ | |
45 | ||
46 | /* Parameter Setting Registers (Pattern) */ | |
47 | #define PAT_BASE_ADDR_REG 0x0500 /* Pattern Image Base Address reg */ | |
48 | #define PAT_SIZE_REG 0x0504 /* Pattern Image Size reg */ | |
49 | #define PAT_COLOR_MODE_REG 0x0508 /* Pattern Image Color Mode reg */ | |
50 | #define PAT_OFFSET_REG 0x050C /* Pattern Left Top Coordinate reg */ | |
51 | #define PAT_STRIDE_REG 0x0510 /* Pattern Stride reg */ | |
52 | ||
53 | /* Parameter Setting Registers (Mask) */ | |
54 | #define MASK_BASE_ADDR_REG 0x0520 /* Mask Base Address reg */ | |
55 | #define MASK_STRIDE_REG 0x0524 /* Mask Stride reg */ | |
56 | ||
57 | /* Parameter Setting Registers (Clipping Window) */ | |
58 | #define CW_LT_REG 0x0600 /* LeftTop coordinates of Clip Window */ | |
59 | #define CW_RB_REG 0x0604 /* RightBottom coordinates of Clip | |
60 | Window */ | |
61 | ||
62 | /* Parameter Setting Registers (ROP & Alpha Setting) */ | |
63 | #define THIRD_OPERAND_REG 0x0610 /* Third Operand Selection reg */ | |
64 | #define ROP4_REG 0x0614 /* Raster Operation reg */ | |
65 | #define ALPHA_REG 0x0618 /* Alpha value, Fading offset value */ | |
66 | ||
67 | /* Parameter Setting Registers (Color) */ | |
68 | #define FG_COLOR_REG 0x0700 /* Foreground Color reg */ | |
69 | #define BG_COLOR_REG 0x0704 /* Background Color reg */ | |
70 | #define BS_COLOR_REG 0x0708 /* Blue Screen Color reg */ | |
71 | ||
72 | /* Parameter Setting Registers (Color Key) */ | |
73 | #define SRC_COLORKEY_CTRL_REG 0x0710 /* Src Colorkey control reg */ | |
74 | #define SRC_COLORKEY_DR_MIN_REG 0x0714 /* Src Colorkey Decision Reference | |
75 | Min reg */ | |
76 | #define SRC_COLORKEY_DR_MAX_REG 0x0718 /* Src Colorkey Decision Reference | |
77 | Max reg */ | |
78 | #define DST_COLORKEY_CTRL_REG 0x071C /* Dest Colorkey control reg */ | |
79 | #define DST_COLORKEY_DR_MIN_REG 0x0720 /* Dest Colorkey Decision Reference | |
80 | Min reg */ | |
81 | #define DST_COLORKEY_DR_MAX_REG 0x0724 /* Dest Colorkey Decision Reference | |
82 | Max reg */ | |
83 | ||
84 | /* Color mode values */ | |
85 | ||
86 | #define ORDER_XRGB 0 | |
87 | #define ORDER_RGBX 1 | |
88 | #define ORDER_XBGR 2 | |
89 | #define ORDER_BGRX 3 | |
90 | ||
91 | #define MODE_XRGB_8888 0 | |
92 | #define MODE_ARGB_8888 1 | |
93 | #define MODE_RGB_565 2 | |
94 | #define MODE_XRGB_1555 3 | |
95 | #define MODE_ARGB_1555 4 | |
96 | #define MODE_XRGB_4444 5 | |
97 | #define MODE_ARGB_4444 6 | |
98 | #define MODE_PACKED_RGB_888 7 | |
99 | ||
100 | #define COLOR_MODE(o, m) (((o) << 4) | (m)) | |
101 | ||
102 | /* ROP4 operation values */ | |
103 | #define ROP4_COPY 0xCCCC | |
104 | #define ROP4_INVERT 0x3333 | |
105 | ||
106 | /* Hardware limits */ | |
107 | #define MAX_WIDTH 8000 | |
108 | #define MAX_HEIGHT 8000 | |
109 | ||
110 | #define G2D_TIMEOUT 500 | |
111 | ||
112 | #define DEFAULT_WIDTH 100 | |
113 | #define DEFAULT_HEIGHT 100 | |
114 | ||
62ce272d SK |
115 | #define DEFAULT_SCALE_MODE (2 << 0) |
116 | ||
117 | /* Command mode register values */ | |
118 | #define CMD_V3_ENABLE_STRETCH (1 << 4) |