[mirror_ubuntu-bionic-kernel.git] / drivers / media / platform / s5p-jpeg / jpeg-regs.h

/* linux/drivers/media/platform/s5p-jpeg/jpeg-regs.h
 *
 * Register definition file for Samsung JPEG codec driver
 *
 * Copyright (c) 2011-2013 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Author: Andrzej Pietrasiewicz <andrzej.p@samsung.com>
 * Author: Jacek Anaszewski <j.anaszewski@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef JPEG_REGS_H_
#define JPEG_REGS_H_

/* Register and bit definitions for S5PC210 */

/* JPEG mode register */
#define S5P_JPGMOD			0x00
#define S5P_PROC_MODE_MASK		(0x1 << 3)
#define S5P_PROC_MODE_DECOMPR		(0x1 << 3)
#define S5P_PROC_MODE_COMPR		(0x0 << 3)
#define S5P_SUBSAMPLING_MODE_MASK	0x7
#define S5P_SUBSAMPLING_MODE_444	(0x0 << 0)
#define S5P_SUBSAMPLING_MODE_422	(0x1 << 0)
#define S5P_SUBSAMPLING_MODE_420	(0x2 << 0)
#define S5P_SUBSAMPLING_MODE_GRAY	(0x3 << 0)

/* JPEG operation status register */
#define S5P_JPGOPR			0x04

/* Quantization tables*/
#define S5P_JPG_QTBL			0x08
#define S5P_QT_NUMt_SHIFT(t)		(((t) - 1) << 1)
#define S5P_QT_NUMt_MASK(t)		(0x3 << S5P_QT_NUMt_SHIFT(t))

/* Huffman tables */
#define S5P_JPG_HTBL			0x0c
#define S5P_HT_NUMt_AC_SHIFT(t)		(((t) << 1) - 1)
#define S5P_HT_NUMt_AC_MASK(t)		(0x1 << S5P_HT_NUMt_AC_SHIFT(t))

#define S5P_HT_NUMt_DC_SHIFT(t)		(((t) - 1) << 1)
#define S5P_HT_NUMt_DC_MASK(t)		(0x1 << S5P_HT_NUMt_DC_SHIFT(t))

/* JPEG restart interval register upper byte */
#define S5P_JPGDRI_U			0x10

/* JPEG restart interval register lower byte */
#define S5P_JPGDRI_L			0x14

/* JPEG vertical resolution register upper byte */
#define S5P_JPGY_U			0x18

/* JPEG vertical resolution register lower byte */
#define S5P_JPGY_L			0x1c

/* JPEG horizontal resolution register upper byte */
#define S5P_JPGX_U			0x20

/* JPEG horizontal resolution register lower byte */
#define S5P_JPGX_L			0x24

/* JPEG byte count register upper byte */
#define S5P_JPGCNT_U			0x28

/* JPEG byte count register middle byte */
#define S5P_JPGCNT_M			0x2c

/* JPEG byte count register lower byte */
#define S5P_JPGCNT_L			0x30

/* JPEG interrupt setting register */
#define S5P_JPGINTSE			0x34
#define S5P_RSTm_INT_EN_MASK		(0x1 << 7)
#define S5P_RSTm_INT_EN			(0x1 << 7)
#define S5P_DATA_NUM_INT_EN_MASK	(0x1 << 6)
#define S5P_DATA_NUM_INT_EN		(0x1 << 6)
#define S5P_FINAL_MCU_NUM_INT_EN_MASK	(0x1 << 5)
#define S5P_FINAL_MCU_NUM_INT_EN	(0x1 << 5)

/* JPEG interrupt status register */
#define S5P_JPGINTST			0x38
#define S5P_RESULT_STAT_SHIFT		6
#define S5P_RESULT_STAT_MASK		(0x1 << S5P_RESULT_STAT_SHIFT)
#define S5P_STREAM_STAT_SHIFT		5
#define S5P_STREAM_STAT_MASK		(0x1 << S5P_STREAM_STAT_SHIFT)

/* JPEG command register */
#define S5P_JPGCOM			0x4c
#define S5P_INT_RELEASE			(0x1 << 2)

/* Raw image data r/w address register */
#define S5P_JPG_IMGADR			0x50

/* JPEG file r/w address register */
#define S5P_JPG_JPGADR			0x58

/* Coefficient for RGB-to-YCbCr converter register */
#define S5P_JPG_COEF(n)			(0x5c + (((n) - 1) << 2))
#define S5P_COEFn_SHIFT(j)		((3 - (j)) << 3)
#define S5P_COEFn_MASK(j)		(0xff << S5P_COEFn_SHIFT(j))

/* JPEG color mode register */
#define S5P_JPGCMOD			0x68
#define S5P_MOD_SEL_MASK		(0x7 << 5)
#define S5P_MOD_SEL_422			(0x1 << 5)
#define S5P_MOD_SEL_565			(0x2 << 5)
#define S5P_MODE_Y16_MASK		(0x1 << 1)
#define S5P_MODE_Y16			(0x1 << 1)

/* JPEG clock control register */
#define S5P_JPGCLKCON			0x6c
#define S5P_CLK_DOWN_READY		(0x1 << 1)
#define S5P_POWER_ON			(0x1 << 0)

/* JPEG start register */
#define S5P_JSTART			0x70

/* JPEG SW reset register */
#define S5P_JPG_SW_RESET		0x78

/* JPEG timer setting register */
#define S5P_JPG_TIMER_SE		0x7c
#define S5P_TIMER_INT_EN_MASK		(0x1 << 31)
#define S5P_TIMER_INT_EN		(0x1 << 31)
#define S5P_TIMER_INIT_MASK		0x7fffffff

/* JPEG timer status register */
#define S5P_JPG_TIMER_ST		0x80
#define S5P_TIMER_INT_STAT_SHIFT	31
#define S5P_TIMER_INT_STAT_MASK		(0x1 << S5P_TIMER_INT_STAT_SHIFT)
#define S5P_TIMER_CNT_SHIFT		0
#define S5P_TIMER_CNT_MASK		0x7fffffff

/* JPEG decompression output format register */
#define S5P_JPG_OUTFORM			0x88
#define S5P_DEC_OUT_FORMAT_MASK		(0x1 << 0)
#define S5P_DEC_OUT_FORMAT_422		(0x0 << 0)
#define S5P_DEC_OUT_FORMAT_420		(0x1 << 0)

/* JPEG version register */
#define S5P_JPG_VERSION			0x8c

/* JPEG compressed stream size interrupt setting register */
#define S5P_JPG_ENC_STREAM_INTSE	0x98
#define S5P_ENC_STREAM_INT_MASK		(0x1 << 24)
#define S5P_ENC_STREAM_INT_EN		(0x1 << 24)
#define S5P_ENC_STREAM_BOUND_MASK	0xffffff

/* JPEG compressed stream size interrupt status register */
#define S5P_JPG_ENC_STREAM_INTST	0x9c
#define S5P_ENC_STREAM_INT_STAT_MASK	0x1

/* JPEG quantizer table register */
#define S5P_JPG_QTBL_CONTENT(n)		(0x400 + (n) * 0x100)

/* JPEG DC Huffman table register */
#define S5P_JPG_HDCTBL(n)		(0x800 + (n) * 0x400)

/* JPEG DC Huffman table register */
#define S5P_JPG_HDCTBLG(n)		(0x840 + (n) * 0x400)

/* JPEG AC Huffman table register */
#define S5P_JPG_HACTBL(n)		(0x880 + (n) * 0x400)

/* JPEG AC Huffman table register */
#define S5P_JPG_HACTBLG(n)		(0x8c0 + (n) * 0x400)


/* Register and bit definitions for Exynos 4x12 */

/* JPEG Codec Control Registers */
#define EXYNOS4_JPEG_CNTL_REG		0x00
#define EXYNOS4_INT_EN_REG		0x04
#define EXYNOS4_INT_TIMER_COUNT_REG	0x08
#define EXYNOS4_INT_STATUS_REG		0x0c
#define EXYNOS4_OUT_MEM_BASE_REG		0x10
#define EXYNOS4_JPEG_IMG_SIZE_REG	0x14
#define EXYNOS4_IMG_BA_PLANE_1_REG	0x18
#define EXYNOS4_IMG_SO_PLANE_1_REG	0x1c
#define EXYNOS4_IMG_PO_PLANE_1_REG	0x20
#define EXYNOS4_IMG_BA_PLANE_2_REG	0x24
#define EXYNOS4_IMG_SO_PLANE_2_REG	0x28
#define EXYNOS4_IMG_PO_PLANE_2_REG	0x2c
#define EXYNOS4_IMG_BA_PLANE_3_REG	0x30
#define EXYNOS4_IMG_SO_PLANE_3_REG	0x34
#define EXYNOS4_IMG_PO_PLANE_3_REG	0x38

#define EXYNOS4_TBL_SEL_REG		0x3c

#define EXYNOS4_IMG_FMT_REG		0x40

#define EXYNOS4_BITSTREAM_SIZE_REG	0x44
#define EXYNOS4_PADDING_REG		0x48
#define EXYNOS4_HUFF_CNT_REG		0x4c
#define EXYNOS4_FIFO_STATUS_REG	0x50
#define EXYNOS4_DECODE_XY_SIZE_REG	0x54
#define EXYNOS4_DECODE_IMG_FMT_REG	0x58

#define EXYNOS4_QUAN_TBL_ENTRY_REG	0x100
#define EXYNOS4_HUFF_TBL_ENTRY_REG	0x200


/****************************************************************/
/* Bit definition part						*/
/****************************************************************/

/* JPEG CNTL Register bit */
#define EXYNOS4_ENC_DEC_MODE_MASK	(0xfffffffc << 0)
#define EXYNOS4_DEC_MODE			(1 << 0)
#define EXYNOS4_ENC_MODE			(1 << 1)
#define EXYNOS4_AUTO_RST_MARKER		(1 << 2)
#define EXYNOS4_RST_INTERVAL_SHIFT	3
#define EXYNOS4_RST_INTERVAL(x)		(((x) & 0xffff) \
						<< EXYNOS4_RST_INTERVAL_SHIFT)
#define EXYNOS4_HUF_TBL_EN		(1 << 19)
#define EXYNOS4_HOR_SCALING_SHIFT	20
#define EXYNOS4_HOR_SCALING_MASK		(3 << EXYNOS4_HOR_SCALING_SHIFT)
#define EXYNOS4_HOR_SCALING(x)		(((x) & 0x3) \
						<< EXYNOS4_HOR_SCALING_SHIFT)
#define EXYNOS4_VER_SCALING_SHIFT	22
#define EXYNOS4_VER_SCALING_MASK		(3 << EXYNOS4_VER_SCALING_SHIFT)
#define EXYNOS4_VER_SCALING(x)		(((x) & 0x3) \
						<< EXYNOS4_VER_SCALING_SHIFT)
#define EXYNOS4_PADDING			(1 << 27)
#define EXYNOS4_SYS_INT_EN		(1 << 28)
#define EXYNOS4_SOFT_RESET_HI		(1 << 29)

/* JPEG INT Register bit */
#define EXYNOS4_INT_EN_MASK		(0x1f << 0)
#define EXYNOS4_PROT_ERR_INT_EN		(1 << 0)
#define EXYNOS4_IMG_COMPLETION_INT_EN	(1 << 1)
#define EXYNOS4_DEC_INVALID_FORMAT_EN	(1 << 2)
#define EXYNOS4_MULTI_SCAN_ERROR_EN	(1 << 3)
#define EXYNOS4_FRAME_ERR_EN		(1 << 4)
#define EXYNOS4_INT_EN_ALL		(0x1f << 0)

#define EXYNOS4_MOD_REG_PROC_ENC		(0 << 3)
#define EXYNOS4_MOD_REG_PROC_DEC		(1 << 3)

#define EXYNOS4_MOD_REG_SUBSAMPLE_444	(0 << 0)
#define EXYNOS4_MOD_REG_SUBSAMPLE_422	(1 << 0)
#define EXYNOS4_MOD_REG_SUBSAMPLE_420	(2 << 0)
#define EXYNOS4_MOD_REG_SUBSAMPLE_GRAY	(3 << 0)


/* JPEG IMAGE SIZE Register bit */
#define EXYNOS4_X_SIZE_SHIFT		0
#define EXYNOS4_X_SIZE_MASK		(0xffff << EXYNOS4_X_SIZE_SHIFT)
#define EXYNOS4_X_SIZE(x)		(((x) & 0xffff) << EXYNOS4_X_SIZE_SHIFT)
#define EXYNOS4_Y_SIZE_SHIFT		16
#define EXYNOS4_Y_SIZE_MASK		(0xffff << EXYNOS4_Y_SIZE_SHIFT)
#define EXYNOS4_Y_SIZE(x)		(((x) & 0xffff) << EXYNOS4_Y_SIZE_SHIFT)

/* JPEG IMAGE FORMAT Register bit */
#define EXYNOS4_ENC_IN_FMT_MASK		0xffff0000
#define EXYNOS4_ENC_GRAY_IMG		(0 << 0)
#define EXYNOS4_ENC_RGB_IMG		(1 << 0)
#define EXYNOS4_ENC_YUV_444_IMG		(2 << 0)
#define EXYNOS4_ENC_YUV_422_IMG		(3 << 0)
#define EXYNOS4_ENC_YUV_440_IMG		(4 << 0)

#define EXYNOS4_DEC_GRAY_IMG		(0 << 0)
#define EXYNOS4_DEC_RGB_IMG		(1 << 0)
#define EXYNOS4_DEC_YUV_444_IMG		(2 << 0)
#define EXYNOS4_DEC_YUV_422_IMG		(3 << 0)
#define EXYNOS4_DEC_YUV_420_IMG		(4 << 0)

#define EXYNOS4_GRAY_IMG_IP_SHIFT	3
#define EXYNOS4_GRAY_IMG_IP_MASK		(7 << EXYNOS4_GRAY_IMG_IP_SHIFT)
#define EXYNOS4_GRAY_IMG_IP		(4 << EXYNOS4_GRAY_IMG_IP_SHIFT)

#define EXYNOS4_RGB_IP_SHIFT		6
#define EXYNOS4_RGB_IP_MASK		(7 << EXYNOS4_RGB_IP_SHIFT)
#define EXYNOS4_RGB_IP_RGB_16BIT_IMG	(4 << EXYNOS4_RGB_IP_SHIFT)
#define EXYNOS4_RGB_IP_RGB_32BIT_IMG	(5 << EXYNOS4_RGB_IP_SHIFT)

#define EXYNOS4_YUV_444_IP_SHIFT			9
#define EXYNOS4_YUV_444_IP_MASK			(7 << EXYNOS4_YUV_444_IP_SHIFT)
#define EXYNOS4_YUV_444_IP_YUV_444_2P_IMG	(4 << EXYNOS4_YUV_444_IP_SHIFT)
#define EXYNOS4_YUV_444_IP_YUV_444_3P_IMG	(5 << EXYNOS4_YUV_444_IP_SHIFT)

#define EXYNOS4_YUV_422_IP_SHIFT			12
#define EXYNOS4_YUV_422_IP_MASK			(7 << EXYNOS4_YUV_422_IP_SHIFT)
#define EXYNOS4_YUV_422_IP_YUV_422_1P_IMG	(4 << EXYNOS4_YUV_422_IP_SHIFT)
#define EXYNOS4_YUV_422_IP_YUV_422_2P_IMG	(5 << EXYNOS4_YUV_422_IP_SHIFT)
#define EXYNOS4_YUV_422_IP_YUV_422_3P_IMG	(6 << EXYNOS4_YUV_422_IP_SHIFT)

#define EXYNOS4_YUV_420_IP_SHIFT			15
#define EXYNOS4_YUV_420_IP_MASK			(7 << EXYNOS4_YUV_420_IP_SHIFT)
#define EXYNOS4_YUV_420_IP_YUV_420_2P_IMG	(4 << EXYNOS4_YUV_420_IP_SHIFT)
#define EXYNOS4_YUV_420_IP_YUV_420_3P_IMG	(5 << EXYNOS4_YUV_420_IP_SHIFT)

#define EXYNOS4_ENC_FMT_SHIFT			24
#define EXYNOS4_ENC_FMT_MASK			(3 << EXYNOS4_ENC_FMT_SHIFT)
#define EXYNOS4_ENC_FMT_GRAY			(0 << EXYNOS4_ENC_FMT_SHIFT)
#define EXYNOS4_ENC_FMT_YUV_444			(1 << EXYNOS4_ENC_FMT_SHIFT)
#define EXYNOS4_ENC_FMT_YUV_422			(2 << EXYNOS4_ENC_FMT_SHIFT)
#define EXYNOS4_ENC_FMT_YUV_420			(3 << EXYNOS4_ENC_FMT_SHIFT)

#define EXYNOS4_JPEG_DECODED_IMG_FMT_MASK	0x03

#define EXYNOS4_SWAP_CHROMA_CRCB			(1 << 26)
#define EXYNOS4_SWAP_CHROMA_CBCR			(0 << 26)

/* JPEG HUFF count Register bit */
#define EXYNOS4_HUFF_COUNT_MASK			0xffff

/* JPEG Decoded_img_x_y_size Register bit */
#define EXYNOS4_DECODED_SIZE_MASK		0x0000ffff

/* JPEG Decoded image format Register bit */
#define EXYNOS4_DECODED_IMG_FMT_MASK		0x3

/* JPEG TBL SEL Register bit */
#define EXYNOS4_Q_TBL_COMP1_0		(0 << 0)
#define EXYNOS4_Q_TBL_COMP1_1		(1 << 0)
#define EXYNOS4_Q_TBL_COMP1_2		(2 << 0)
#define EXYNOS4_Q_TBL_COMP1_3		(3 << 0)

#define EXYNOS4_Q_TBL_COMP2_0		(0 << 2)
#define EXYNOS4_Q_TBL_COMP2_1		(1 << 2)
#define EXYNOS4_Q_TBL_COMP2_2		(2 << 2)
#define EXYNOS4_Q_TBL_COMP2_3		(3 << 2)

#define EXYNOS4_Q_TBL_COMP3_0		(0 << 4)
#define EXYNOS4_Q_TBL_COMP3_1		(1 << 4)
#define EXYNOS4_Q_TBL_COMP3_2		(2 << 4)
#define EXYNOS4_Q_TBL_COMP3_3		(3 << 4)

#define EXYNOS4_HUFF_TBL_COMP1_AC_0_DC_0	(0 << 6)
#define EXYNOS4_HUFF_TBL_COMP1_AC_0_DC_1	(1 << 6)
#define EXYNOS4_HUFF_TBL_COMP1_AC_1_DC_0	(2 << 6)
#define EXYNOS4_HUFF_TBL_COMP1_AC_1_DC_1	(3 << 6)

#define EXYNOS4_HUFF_TBL_COMP2_AC_0_DC_0	(0 << 8)
#define EXYNOS4_HUFF_TBL_COMP2_AC_0_DC_1	(1 << 8)
#define EXYNOS4_HUFF_TBL_COMP2_AC_1_DC_0	(2 << 8)
#define EXYNOS4_HUFF_TBL_COMP2_AC_1_DC_1	(3 << 8)

#define EXYNOS4_HUFF_TBL_COMP3_AC_0_DC_0	(0 << 10)
#define EXYNOS4_HUFF_TBL_COMP3_AC_0_DC_1	(1 << 10)
#define EXYNOS4_HUFF_TBL_COMP3_AC_1_DC_0	(2 << 10)
#define EXYNOS4_HUFF_TBL_COMP3_AC_1_DC_1	(3 << 10)

/* JPEG quantizer table register */
#define EXYNOS4_QTBL_CONTENT(n)	(0x100 + (n) * 0x40)

/* JPEG DC luminance (code length) Huffman table register */
#define EXYNOS4_HUFF_TBL_HDCLL	0x200

/* JPEG DC luminance (values) Huffman table register */
#define EXYNOS4_HUFF_TBL_HDCLV	0x210

/* JPEG DC chrominance (code length) Huffman table register */
#define EXYNOS4_HUFF_TBL_HDCCL	0x220

/* JPEG DC chrominance (values) Huffman table register */
#define EXYNOS4_HUFF_TBL_HDCCV	0x230

/* JPEG AC luminance (code length) Huffman table register */
#define EXYNOS4_HUFF_TBL_HACLL	0x240

/* JPEG AC luminance (values) Huffman table register */
#define EXYNOS4_HUFF_TBL_HACLV	0x250

/* JPEG AC chrominance (code length) Huffman table register */
#define EXYNOS4_HUFF_TBL_HACCL	0x300

/* JPEG AC chrominance (values) Huffman table register */
#define EXYNOS4_HUFF_TBL_HACCV	0x310

#endif /* JPEG_REGS_H_ */
Commit	Line	Data
2c3fb08b	1	/* linux/drivers/media/platform/s5p-jpeg/jpeg-regs.h
bb677f3a AP	2	*
	3	* Register definition file for Samsung JPEG codec driver
	4	*
80529ae5	5	* Copyright (c) 2011-2013 Samsung Electronics Co., Ltd.
bb677f3a AP	6	* http://www.samsung.com
	7	*
	8	* Author: Andrzej Pietrasiewicz <andrzej.p@samsung.com>
80529ae5	9	* Author: Jacek Anaszewski <j.anaszewski@samsung.com>
bb677f3a AP	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#ifndef JPEG_REGS_H_
	17	#define JPEG_REGS_H_
	18
80529ae5 JA	19	/* Register and bit definitions for S5PC210 */
80529ae5 JA	20
bb677f3a AP	21	/* JPEG mode register */
	22	#define S5P_JPGMOD 0x00
	23	#define S5P_PROC_MODE_MASK (0x1 << 3)
	24	#define S5P_PROC_MODE_DECOMPR (0x1 << 3)
	25	#define S5P_PROC_MODE_COMPR (0x0 << 3)
	26	#define S5P_SUBSAMPLING_MODE_MASK 0x7
	27	#define S5P_SUBSAMPLING_MODE_444 (0x0 << 0)
	28	#define S5P_SUBSAMPLING_MODE_422 (0x1 << 0)
	29	#define S5P_SUBSAMPLING_MODE_420 (0x2 << 0)
	30	#define S5P_SUBSAMPLING_MODE_GRAY (0x3 << 0)
	31
	32	/* JPEG operation status register */
	33	#define S5P_JPGOPR 0x04
	34
	35	/* Quantization tables*/
	36	#define S5P_JPG_QTBL 0x08
	37	#define S5P_QT_NUMt_SHIFT(t) (((t) - 1) << 1)
	38	#define S5P_QT_NUMt_MASK(t) (0x3 << S5P_QT_NUMt_SHIFT(t))
	39
	40	/* Huffman tables */
	41	#define S5P_JPG_HTBL 0x0c
	42	#define S5P_HT_NUMt_AC_SHIFT(t) (((t) << 1) - 1)
	43	#define S5P_HT_NUMt_AC_MASK(t) (0x1 << S5P_HT_NUMt_AC_SHIFT(t))
	44
	45	#define S5P_HT_NUMt_DC_SHIFT(t) (((t) - 1) << 1)
	46	#define S5P_HT_NUMt_DC_MASK(t) (0x1 << S5P_HT_NUMt_DC_SHIFT(t))
	47
	48	/* JPEG restart interval register upper byte */
	49	#define S5P_JPGDRI_U 0x10
	50
	51	/* JPEG restart interval register lower byte */
	52	#define S5P_JPGDRI_L 0x14
	53
	54	/* JPEG vertical resolution register upper byte */
	55	#define S5P_JPGY_U 0x18
	56
	57	/* JPEG vertical resolution register lower byte */
	58	#define S5P_JPGY_L 0x1c
	59
	60	/* JPEG horizontal resolution register upper byte */
	61	#define S5P_JPGX_U 0x20
	62
	63	/* JPEG horizontal resolution register lower byte */
	64	#define S5P_JPGX_L 0x24
	65
	66	/* JPEG byte count register upper byte */
	67	#define S5P_JPGCNT_U 0x28
	68
	69	/* JPEG byte count register middle byte */
	70	#define S5P_JPGCNT_M 0x2c
	71
	72	/* JPEG byte count register lower byte */
	73	#define S5P_JPGCNT_L 0x30
	74
	75	/* JPEG interrupt setting register */
	76	#define S5P_JPGINTSE 0x34
	77	#define S5P_RSTm_INT_EN_MASK (0x1 << 7)
	78	#define S5P_RSTm_INT_EN (0x1 << 7)
	79	#define S5P_DATA_NUM_INT_EN_MASK (0x1 << 6)
	80	#define S5P_DATA_NUM_INT_EN (0x1 << 6)
	81	#define S5P_FINAL_MCU_NUM_INT_EN_MASK (0x1 << 5)
	82	#define S5P_FINAL_MCU_NUM_INT_EN (0x1 << 5)
	83
	84	/* JPEG interrupt status register */
85	#define S5P_JPGINTST 0x38
86	#define S5P_RESULT_STAT_SHIFT 6
87	#define S5P_RESULT_STAT_MASK (0x1 << S5P_RESULT_STAT_SHIFT)
88	#define S5P_STREAM_STAT_SHIFT 5
89	#define S5P_STREAM_STAT_MASK (0x1 << S5P_STREAM_STAT_SHIFT)
90
91	/* JPEG command register */
92	#define S5P_JPGCOM 0x4c
93	#define S5P_INT_RELEASE (0x1 << 2)
94
95	/* Raw image data r/w address register */
96	#define S5P_JPG_IMGADR 0x50
97
98	/* JPEG file r/w address register */
99	#define S5P_JPG_JPGADR 0x58
100
101	/* Coefficient for RGB-to-YCbCr converter register */
102	#define S5P_JPG_COEF(n) (0x5c + (((n) - 1) << 2))
103	#define S5P_COEFn_SHIFT(j) ((3 - (j)) << 3)
104	#define S5P_COEFn_MASK(j) (0xff << S5P_COEFn_SHIFT(j))
105
106	/* JPEG color mode register */
107	#define S5P_JPGCMOD 0x68
108	#define S5P_MOD_SEL_MASK (0x7 << 5)
109	#define S5P_MOD_SEL_422 (0x1 << 5)
110	#define S5P_MOD_SEL_565 (0x2 << 5)
111	#define S5P_MODE_Y16_MASK (0x1 << 1)
112	#define S5P_MODE_Y16 (0x1 << 1)
113
114	/* JPEG clock control register */
115	#define S5P_JPGCLKCON 0x6c
116	#define S5P_CLK_DOWN_READY (0x1 << 1)
117	#define S5P_POWER_ON (0x1 << 0)
118
119	/* JPEG start register */
120	#define S5P_JSTART 0x70
121
122	/* JPEG SW reset register */
123	#define S5P_JPG_SW_RESET 0x78
124
125	/* JPEG timer setting register */
126	#define S5P_JPG_TIMER_SE 0x7c
127	#define S5P_TIMER_INT_EN_MASK (0x1 << 31)
128	#define S5P_TIMER_INT_EN (0x1 << 31)
129	#define S5P_TIMER_INIT_MASK 0x7fffffff
130
131	/* JPEG timer status register */
132	#define S5P_JPG_TIMER_ST 0x80
133	#define S5P_TIMER_INT_STAT_SHIFT 31
134	#define S5P_TIMER_INT_STAT_MASK (0x1 << S5P_TIMER_INT_STAT_SHIFT)
135	#define S5P_TIMER_CNT_SHIFT 0
136	#define S5P_TIMER_CNT_MASK 0x7fffffff
137
138	/* JPEG decompression output format register */
139	#define S5P_JPG_OUTFORM 0x88
140	#define S5P_DEC_OUT_FORMAT_MASK (0x1 << 0)
141	#define S5P_DEC_OUT_FORMAT_422 (0x0 << 0)
142	#define S5P_DEC_OUT_FORMAT_420 (0x1 << 0)
143
144	/* JPEG version register */
145	#define S5P_JPG_VERSION 0x8c
146
147	/* JPEG compressed stream size interrupt setting register */
148	#define S5P_JPG_ENC_STREAM_INTSE 0x98
149	#define S5P_ENC_STREAM_INT_MASK (0x1 << 24)
150	#define S5P_ENC_STREAM_INT_EN (0x1 << 24)
151	#define S5P_ENC_STREAM_BOUND_MASK 0xffffff
152
153	/* JPEG compressed stream size interrupt status register */
154	#define S5P_JPG_ENC_STREAM_INTST 0x9c
155	#define S5P_ENC_STREAM_INT_STAT_MASK 0x1
156
157	/* JPEG quantizer table register */
158	#define S5P_JPG_QTBL_CONTENT(n) (0x400 + (n) * 0x100)
159
160	/* JPEG DC Huffman table register */
161	#define S5P_JPG_HDCTBL(n) (0x800 + (n) * 0x400)
162
163	/* JPEG DC Huffman table register */
164	#define S5P_JPG_HDCTBLG(n) (0x840 + (n) * 0x400)
165
166	/* JPEG AC Huffman table register */
167	#define S5P_JPG_HACTBL(n) (0x880 + (n) * 0x400)
168
169	/* JPEG AC Huffman table register */
170	#define S5P_JPG_HACTBLG(n) (0x8c0 + (n) * 0x400)
171
80529ae5 JA	172
	173	/* Register and bit definitions for Exynos 4x12 */
	174
	175	/* JPEG Codec Control Registers */
	176	#define EXYNOS4_JPEG_CNTL_REG 0x00
	177	#define EXYNOS4_INT_EN_REG 0x04
	178	#define EXYNOS4_INT_TIMER_COUNT_REG 0x08
	179	#define EXYNOS4_INT_STATUS_REG 0x0c
	180	#define EXYNOS4_OUT_MEM_BASE_REG 0x10
	181	#define EXYNOS4_JPEG_IMG_SIZE_REG 0x14
	182	#define EXYNOS4_IMG_BA_PLANE_1_REG 0x18
	183	#define EXYNOS4_IMG_SO_PLANE_1_REG 0x1c
	184	#define EXYNOS4_IMG_PO_PLANE_1_REG 0x20
	185	#define EXYNOS4_IMG_BA_PLANE_2_REG 0x24
	186	#define EXYNOS4_IMG_SO_PLANE_2_REG 0x28
	187	#define EXYNOS4_IMG_PO_PLANE_2_REG 0x2c
	188	#define EXYNOS4_IMG_BA_PLANE_3_REG 0x30
	189	#define EXYNOS4_IMG_SO_PLANE_3_REG 0x34
	190	#define EXYNOS4_IMG_PO_PLANE_3_REG 0x38
	191
	192	#define EXYNOS4_TBL_SEL_REG 0x3c
	193
	194	#define EXYNOS4_IMG_FMT_REG 0x40
	195
	196	#define EXYNOS4_BITSTREAM_SIZE_REG 0x44
	197	#define EXYNOS4_PADDING_REG 0x48
	198	#define EXYNOS4_HUFF_CNT_REG 0x4c
	199	#define EXYNOS4_FIFO_STATUS_REG 0x50
	200	#define EXYNOS4_DECODE_XY_SIZE_REG 0x54
	201	#define EXYNOS4_DECODE_IMG_FMT_REG 0x58
	202
	203	#define EXYNOS4_QUAN_TBL_ENTRY_REG 0x100
	204	#define EXYNOS4_HUFF_TBL_ENTRY_REG 0x200
	205
	206
	207	/****************************************************************/
	208	/* Bit definition part */
	209	/****************************************************************/
	210
	211	/* JPEG CNTL Register bit */
	212	#define EXYNOS4_ENC_DEC_MODE_MASK (0xfffffffc << 0)
	213	#define EXYNOS4_DEC_MODE (1 << 0)
	214	#define EXYNOS4_ENC_MODE (1 << 1)
	215	#define EXYNOS4_AUTO_RST_MARKER (1 << 2)
	216	#define EXYNOS4_RST_INTERVAL_SHIFT 3
	217	#define EXYNOS4_RST_INTERVAL(x) (((x) & 0xffff) \
	218	<< EXYNOS4_RST_INTERVAL_SHIFT)
	219	#define EXYNOS4_HUF_TBL_EN (1 << 19)
	220	#define EXYNOS4_HOR_SCALING_SHIFT 20
	221	#define EXYNOS4_HOR_SCALING_MASK (3 << EXYNOS4_HOR_SCALING_SHIFT)
	222	#define EXYNOS4_HOR_SCALING(x) (((x) & 0x3) \
	223	<< EXYNOS4_HOR_SCALING_SHIFT)
	224	#define EXYNOS4_VER_SCALING_SHIFT 22
	225	#define EXYNOS4_VER_SCALING_MASK (3 << EXYNOS4_VER_SCALING_SHIFT)
	226	#define EXYNOS4_VER_SCALING(x) (((x) & 0x3) \
	227	<< EXYNOS4_VER_SCALING_SHIFT)
	228	#define EXYNOS4_PADDING (1 << 27)
	229	#define EXYNOS4_SYS_INT_EN (1 << 28)
	230	#define EXYNOS4_SOFT_RESET_HI (1 << 29)
	231
	232	/* JPEG INT Register bit */
	233	#define EXYNOS4_INT_EN_MASK (0x1f << 0)
	234	#define EXYNOS4_PROT_ERR_INT_EN (1 << 0)
	235	#define EXYNOS4_IMG_COMPLETION_INT_EN (1 << 1)
236	#define EXYNOS4_DEC_INVALID_FORMAT_EN (1 << 2)
237	#define EXYNOS4_MULTI_SCAN_ERROR_EN (1 << 3)
238	#define EXYNOS4_FRAME_ERR_EN (1 << 4)
239	#define EXYNOS4_INT_EN_ALL (0x1f << 0)
240
241	#define EXYNOS4_MOD_REG_PROC_ENC (0 << 3)
242	#define EXYNOS4_MOD_REG_PROC_DEC (1 << 3)
243
244	#define EXYNOS4_MOD_REG_SUBSAMPLE_444 (0 << 0)
245	#define EXYNOS4_MOD_REG_SUBSAMPLE_422 (1 << 0)
246	#define EXYNOS4_MOD_REG_SUBSAMPLE_420 (2 << 0)
247	#define EXYNOS4_MOD_REG_SUBSAMPLE_GRAY (3 << 0)
248
249
250	/* JPEG IMAGE SIZE Register bit */
251	#define EXYNOS4_X_SIZE_SHIFT 0
252	#define EXYNOS4_X_SIZE_MASK (0xffff << EXYNOS4_X_SIZE_SHIFT)
253	#define EXYNOS4_X_SIZE(x) (((x) & 0xffff) << EXYNOS4_X_SIZE_SHIFT)
254	#define EXYNOS4_Y_SIZE_SHIFT 16
255	#define EXYNOS4_Y_SIZE_MASK (0xffff << EXYNOS4_Y_SIZE_SHIFT)
256	#define EXYNOS4_Y_SIZE(x) (((x) & 0xffff) << EXYNOS4_Y_SIZE_SHIFT)
257
258	/* JPEG IMAGE FORMAT Register bit */
259	#define EXYNOS4_ENC_IN_FMT_MASK 0xffff0000
260	#define EXYNOS4_ENC_GRAY_IMG (0 << 0)
261	#define EXYNOS4_ENC_RGB_IMG (1 << 0)
262	#define EXYNOS4_ENC_YUV_444_IMG (2 << 0)
263	#define EXYNOS4_ENC_YUV_422_IMG (3 << 0)
264	#define EXYNOS4_ENC_YUV_440_IMG (4 << 0)
265
266	#define EXYNOS4_DEC_GRAY_IMG (0 << 0)
267	#define EXYNOS4_DEC_RGB_IMG (1 << 0)
268	#define EXYNOS4_DEC_YUV_444_IMG (2 << 0)
269	#define EXYNOS4_DEC_YUV_422_IMG (3 << 0)
270	#define EXYNOS4_DEC_YUV_420_IMG (4 << 0)
271
272	#define EXYNOS4_GRAY_IMG_IP_SHIFT 3
273	#define EXYNOS4_GRAY_IMG_IP_MASK (7 << EXYNOS4_GRAY_IMG_IP_SHIFT)
274	#define EXYNOS4_GRAY_IMG_IP (4 << EXYNOS4_GRAY_IMG_IP_SHIFT)
275
276	#define EXYNOS4_RGB_IP_SHIFT 6
277	#define EXYNOS4_RGB_IP_MASK (7 << EXYNOS4_RGB_IP_SHIFT)
278	#define EXYNOS4_RGB_IP_RGB_16BIT_IMG (4 << EXYNOS4_RGB_IP_SHIFT)
279	#define EXYNOS4_RGB_IP_RGB_32BIT_IMG (5 << EXYNOS4_RGB_IP_SHIFT)
280
281	#define EXYNOS4_YUV_444_IP_SHIFT 9
282	#define EXYNOS4_YUV_444_IP_MASK (7 << EXYNOS4_YUV_444_IP_SHIFT)
283	#define EXYNOS4_YUV_444_IP_YUV_444_2P_IMG (4 << EXYNOS4_YUV_444_IP_SHIFT)
284	#define EXYNOS4_YUV_444_IP_YUV_444_3P_IMG (5 << EXYNOS4_YUV_444_IP_SHIFT)
285
286	#define EXYNOS4_YUV_422_IP_SHIFT 12
287	#define EXYNOS4_YUV_422_IP_MASK (7 << EXYNOS4_YUV_422_IP_SHIFT)
288	#define EXYNOS4_YUV_422_IP_YUV_422_1P_IMG (4 << EXYNOS4_YUV_422_IP_SHIFT)
289	#define EXYNOS4_YUV_422_IP_YUV_422_2P_IMG (5 << EXYNOS4_YUV_422_IP_SHIFT)
290	#define EXYNOS4_YUV_422_IP_YUV_422_3P_IMG (6 << EXYNOS4_YUV_422_IP_SHIFT)
291
292	#define EXYNOS4_YUV_420_IP_SHIFT 15
293	#define EXYNOS4_YUV_420_IP_MASK (7 << EXYNOS4_YUV_420_IP_SHIFT)
294	#define EXYNOS4_YUV_420_IP_YUV_420_2P_IMG (4 << EXYNOS4_YUV_420_IP_SHIFT)
295	#define EXYNOS4_YUV_420_IP_YUV_420_3P_IMG (5 << EXYNOS4_YUV_420_IP_SHIFT)
296
297	#define EXYNOS4_ENC_FMT_SHIFT 24
298	#define EXYNOS4_ENC_FMT_MASK (3 << EXYNOS4_ENC_FMT_SHIFT)
299	#define EXYNOS4_ENC_FMT_GRAY (0 << EXYNOS4_ENC_FMT_SHIFT)
300	#define EXYNOS4_ENC_FMT_YUV_444 (1 << EXYNOS4_ENC_FMT_SHIFT)
301	#define EXYNOS4_ENC_FMT_YUV_422 (2 << EXYNOS4_ENC_FMT_SHIFT)
302	#define EXYNOS4_ENC_FMT_YUV_420 (3 << EXYNOS4_ENC_FMT_SHIFT)
303
304	#define EXYNOS4_JPEG_DECODED_IMG_FMT_MASK 0x03
305
306	#define EXYNOS4_SWAP_CHROMA_CRCB (1 << 26)
307	#define EXYNOS4_SWAP_CHROMA_CBCR (0 << 26)
308
309	/* JPEG HUFF count Register bit */
310	#define EXYNOS4_HUFF_COUNT_MASK 0xffff
311
312	/* JPEG Decoded_img_x_y_size Register bit */
313	#define EXYNOS4_DECODED_SIZE_MASK 0x0000ffff
314
315	/* JPEG Decoded image format Register bit */
316	#define EXYNOS4_DECODED_IMG_FMT_MASK 0x3
317
318	/* JPEG TBL SEL Register bit */
319	#define EXYNOS4_Q_TBL_COMP1_0 (0 << 0)
320	#define EXYNOS4_Q_TBL_COMP1_1 (1 << 0)
321	#define EXYNOS4_Q_TBL_COMP1_2 (2 << 0)
322	#define EXYNOS4_Q_TBL_COMP1_3 (3 << 0)
323
324	#define EXYNOS4_Q_TBL_COMP2_0 (0 << 2)
325	#define EXYNOS4_Q_TBL_COMP2_1 (1 << 2)
326	#define EXYNOS4_Q_TBL_COMP2_2 (2 << 2)
327	#define EXYNOS4_Q_TBL_COMP2_3 (3 << 2)
328
329	#define EXYNOS4_Q_TBL_COMP3_0 (0 << 4)
330	#define EXYNOS4_Q_TBL_COMP3_1 (1 << 4)
331	#define EXYNOS4_Q_TBL_COMP3_2 (2 << 4)
332	#define EXYNOS4_Q_TBL_COMP3_3 (3 << 4)
333
334	#define EXYNOS4_HUFF_TBL_COMP1_AC_0_DC_0 (0 << 6)
335	#define EXYNOS4_HUFF_TBL_COMP1_AC_0_DC_1 (1 << 6)
336	#define EXYNOS4_HUFF_TBL_COMP1_AC_1_DC_0 (2 << 6)
337	#define EXYNOS4_HUFF_TBL_COMP1_AC_1_DC_1 (3 << 6)
338
339	#define EXYNOS4_HUFF_TBL_COMP2_AC_0_DC_0 (0 << 8)
340	#define EXYNOS4_HUFF_TBL_COMP2_AC_0_DC_1 (1 << 8)
341	#define EXYNOS4_HUFF_TBL_COMP2_AC_1_DC_0 (2 << 8)
342	#define EXYNOS4_HUFF_TBL_COMP2_AC_1_DC_1 (3 << 8)
343
344	#define EXYNOS4_HUFF_TBL_COMP3_AC_0_DC_0 (0 << 10)
345	#define EXYNOS4_HUFF_TBL_COMP3_AC_0_DC_1 (1 << 10)
346	#define EXYNOS4_HUFF_TBL_COMP3_AC_1_DC_0 (2 << 10)
347	#define EXYNOS4_HUFF_TBL_COMP3_AC_1_DC_1 (3 << 10)
348
349	/* JPEG quantizer table register */
350	#define EXYNOS4_QTBL_CONTENT(n) (0x100 + (n) * 0x40)
351
352	/* JPEG DC luminance (code length) Huffman table register */
353	#define EXYNOS4_HUFF_TBL_HDCLL 0x200
354
355	/* JPEG DC luminance (values) Huffman table register */
356	#define EXYNOS4_HUFF_TBL_HDCLV 0x210
357
358	/* JPEG DC chrominance (code length) Huffman table register */
359	#define EXYNOS4_HUFF_TBL_HDCCL 0x220
360
361	/* JPEG DC chrominance (values) Huffman table register */
362	#define EXYNOS4_HUFF_TBL_HDCCV 0x230
363
364	/* JPEG AC luminance (code length) Huffman table register */
365	#define EXYNOS4_HUFF_TBL_HACLL 0x240
366
367	/* JPEG AC luminance (values) Huffman table register */
368	#define EXYNOS4_HUFF_TBL_HACLV 0x250
369
370	/* JPEG AC chrominance (code length) Huffman table register */
371	#define EXYNOS4_HUFF_TBL_HACCL 0x300
372
373	/* JPEG AC chrominance (values) Huffman table register */
374	#define EXYNOS4_HUFF_TBL_HACCV 0x310
375
bb677f3a AP	376	#endif /* JPEG_REGS_H_ */
bb677f3a AP	377