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af935746 KD |
1 | /* |
2 | * Samsung S5P Multi Format Codec v 5.0 | |
3 | * | |
4 | * This file contains definitions of enums and structs used by the codec | |
5 | * driver. | |
6 | * | |
7 | * Copyright (C) 2011 Samsung Electronics Co., Ltd. | |
8 | * Kamil Debski, <k.debski@samsung.com> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by the | |
12 | * Free Software Foundation; either version 2 of the | |
13 | * License, or (at your option) any later version | |
14 | */ | |
15 | ||
16 | #ifndef S5P_MFC_COMMON_H_ | |
17 | #define S5P_MFC_COMMON_H_ | |
18 | ||
19 | #include "regs-mfc.h" | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/videodev2.h> | |
22 | #include <media/v4l2-ctrls.h> | |
23 | #include <media/v4l2-device.h> | |
24 | #include <media/v4l2-ioctl.h> | |
25 | #include <media/videobuf2-core.h> | |
26 | ||
27 | /* Definitions related to MFC memory */ | |
28 | ||
29 | /* Offset base used to differentiate between CAPTURE and OUTPUT | |
30 | * while mmaping */ | |
31 | #define DST_QUEUE_OFF_BASE (TASK_SIZE / 2) | |
32 | ||
33 | /* Offset used by the hardware to store addresses */ | |
34 | #define MFC_OFFSET_SHIFT 11 | |
35 | ||
36 | #define FIRMWARE_ALIGN 0x20000 /* 128KB */ | |
37 | #define MFC_H264_CTX_BUF_SIZE 0x96000 /* 600KB per H264 instance */ | |
38 | #define MFC_CTX_BUF_SIZE 0x2800 /* 10KB per instance */ | |
39 | #define DESC_BUF_SIZE 0x20000 /* 128KB for DESC buffer */ | |
40 | #define SHARED_BUF_SIZE 0x2000 /* 8KB for shared buffer */ | |
41 | ||
42 | #define DEF_CPB_SIZE 0x40000 /* 512KB */ | |
43 | ||
44 | #define MFC_BANK1_ALLOC_CTX 0 | |
45 | #define MFC_BANK2_ALLOC_CTX 1 | |
46 | ||
47 | #define MFC_BANK1_ALIGN_ORDER 13 | |
48 | #define MFC_BANK2_ALIGN_ORDER 13 | |
49 | #define MFC_BASE_ALIGN_ORDER 17 | |
50 | ||
51 | #include <media/videobuf2-dma-contig.h> | |
52 | ||
53 | static inline dma_addr_t s5p_mfc_mem_cookie(void *a, void *b) | |
54 | { | |
55 | /* Same functionality as the vb2_dma_contig_plane_paddr */ | |
56 | dma_addr_t *paddr = vb2_dma_contig_memops.cookie(b); | |
57 | ||
58 | return *paddr; | |
59 | } | |
60 | ||
61 | /* MFC definitions */ | |
62 | #define MFC_MAX_EXTRA_DPB 5 | |
63 | #define MFC_MAX_BUFFERS 32 | |
64 | #define MFC_NUM_CONTEXTS 4 | |
65 | /* Interrupt timeout */ | |
66 | #define MFC_INT_TIMEOUT 2000 | |
67 | /* Busy wait timeout */ | |
68 | #define MFC_BW_TIMEOUT 500 | |
69 | /* Watchdog interval */ | |
70 | #define MFC_WATCHDOG_INTERVAL 1000 | |
71 | /* After how many executions watchdog should assume lock up */ | |
72 | #define MFC_WATCHDOG_CNT 10 | |
73 | #define MFC_NO_INSTANCE_SET -1 | |
74 | #define MFC_ENC_CAP_PLANE_COUNT 1 | |
75 | #define MFC_ENC_OUT_PLANE_COUNT 2 | |
76 | #define STUFF_BYTE 4 | |
43a1ea1f AK |
77 | #define MFC_MAX_CTRLS 70 |
78 | ||
79 | #define S5P_MFC_CODEC_NONE -1 | |
80 | #define S5P_MFC_CODEC_H264_DEC 0 | |
81 | #define S5P_MFC_CODEC_H264_MVC_DEC 1 | |
82 | #define S5P_MFC_CODEC_VC1_DEC 2 | |
83 | #define S5P_MFC_CODEC_MPEG4_DEC 3 | |
84 | #define S5P_MFC_CODEC_MPEG2_DEC 4 | |
85 | #define S5P_MFC_CODEC_H263_DEC 5 | |
86 | #define S5P_MFC_CODEC_VC1RCV_DEC 6 | |
87 | #define S5P_MFC_CODEC_VP8_DEC 7 | |
88 | ||
89 | #define S5P_MFC_CODEC_H264_ENC 20 | |
90 | #define S5P_MFC_CODEC_H264_MVC_ENC 21 | |
91 | #define S5P_MFC_CODEC_MPEG4_ENC 22 | |
92 | #define S5P_MFC_CODEC_H263_ENC 23 | |
93 | ||
94 | #define S5P_MFC_R2H_CMD_EMPTY 0 | |
95 | #define S5P_MFC_R2H_CMD_SYS_INIT_RET 1 | |
96 | #define S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET 2 | |
97 | #define S5P_MFC_R2H_CMD_SEQ_DONE_RET 3 | |
98 | #define S5P_MFC_R2H_CMD_INIT_BUFFERS_RET 4 | |
99 | #define S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET 6 | |
100 | #define S5P_MFC_R2H_CMD_SLEEP_RET 7 | |
101 | #define S5P_MFC_R2H_CMD_WAKEUP_RET 8 | |
102 | #define S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET 9 | |
103 | #define S5P_MFC_R2H_CMD_DPB_FLUSH_RET 10 | |
104 | #define S5P_MFC_R2H_CMD_NAL_ABORT_RET 11 | |
105 | #define S5P_MFC_R2H_CMD_FW_STATUS_RET 12 | |
106 | #define S5P_MFC_R2H_CMD_FRAME_DONE_RET 13 | |
107 | #define S5P_MFC_R2H_CMD_FIELD_DONE_RET 14 | |
108 | #define S5P_MFC_R2H_CMD_SLICE_DONE_RET 15 | |
109 | #define S5P_MFC_R2H_CMD_ENC_BUFFER_FUL_RET 16 | |
110 | #define S5P_MFC_R2H_CMD_ERR_RET 32 | |
af935746 KD |
111 | |
112 | #define mfc_read(dev, offset) readl(dev->regs_base + (offset)) | |
113 | #define mfc_write(dev, data, offset) writel((data), dev->regs_base + \ | |
114 | (offset)) | |
115 | ||
116 | /** | |
117 | * enum s5p_mfc_fmt_type - type of the pixelformat | |
118 | */ | |
119 | enum s5p_mfc_fmt_type { | |
120 | MFC_FMT_DEC, | |
121 | MFC_FMT_ENC, | |
122 | MFC_FMT_RAW, | |
123 | }; | |
124 | ||
125 | /** | |
126 | * enum s5p_mfc_node_type - The type of an MFC device node. | |
127 | */ | |
128 | enum s5p_mfc_node_type { | |
129 | MFCNODE_INVALID = -1, | |
130 | MFCNODE_DECODER = 0, | |
131 | MFCNODE_ENCODER = 1, | |
132 | }; | |
133 | ||
134 | /** | |
135 | * enum s5p_mfc_inst_type - The type of an MFC instance. | |
136 | */ | |
137 | enum s5p_mfc_inst_type { | |
138 | MFCINST_INVALID, | |
139 | MFCINST_DECODER, | |
140 | MFCINST_ENCODER, | |
141 | }; | |
142 | ||
143 | /** | |
144 | * enum s5p_mfc_inst_state - The state of an MFC instance. | |
145 | */ | |
146 | enum s5p_mfc_inst_state { | |
147 | MFCINST_FREE = 0, | |
148 | MFCINST_INIT = 100, | |
149 | MFCINST_GOT_INST, | |
150 | MFCINST_HEAD_PARSED, | |
151 | MFCINST_BUFS_SET, | |
152 | MFCINST_RUNNING, | |
153 | MFCINST_FINISHING, | |
154 | MFCINST_FINISHED, | |
155 | MFCINST_RETURN_INST, | |
156 | MFCINST_ERROR, | |
157 | MFCINST_ABORT, | |
158 | MFCINST_RES_CHANGE_INIT, | |
159 | MFCINST_RES_CHANGE_FLUSH, | |
160 | MFCINST_RES_CHANGE_END, | |
161 | }; | |
162 | ||
163 | /** | |
164 | * enum s5p_mfc_queue_state - The state of buffer queue. | |
165 | */ | |
166 | enum s5p_mfc_queue_state { | |
167 | QUEUE_FREE, | |
168 | QUEUE_BUFS_REQUESTED, | |
169 | QUEUE_BUFS_QUERIED, | |
170 | QUEUE_BUFS_MMAPED, | |
171 | }; | |
172 | ||
173 | /** | |
174 | * enum s5p_mfc_decode_arg - type of frame decoding | |
175 | */ | |
176 | enum s5p_mfc_decode_arg { | |
177 | MFC_DEC_FRAME, | |
178 | MFC_DEC_LAST_FRAME, | |
179 | MFC_DEC_RES_CHANGE, | |
180 | }; | |
181 | ||
f9f715a9 AH |
182 | #define MFC_BUF_FLAG_USED (1 << 0) |
183 | #define MFC_BUF_FLAG_EOS (1 << 1) | |
184 | ||
af935746 KD |
185 | struct s5p_mfc_ctx; |
186 | ||
187 | /** | |
188 | * struct s5p_mfc_buf - MFC buffer | |
189 | */ | |
190 | struct s5p_mfc_buf { | |
191 | struct list_head list; | |
192 | struct vb2_buffer *b; | |
193 | union { | |
194 | struct { | |
195 | size_t luma; | |
196 | size_t chroma; | |
197 | } raw; | |
198 | size_t stream; | |
199 | } cookie; | |
f9f715a9 | 200 | int flags; |
af935746 KD |
201 | }; |
202 | ||
203 | /** | |
204 | * struct s5p_mfc_pm - power management data structure | |
205 | */ | |
206 | struct s5p_mfc_pm { | |
207 | struct clk *clock; | |
208 | struct clk *clock_gate; | |
209 | atomic_t power; | |
210 | struct device *device; | |
211 | }; | |
212 | ||
213 | /** | |
214 | * struct s5p_mfc_dev - The struct containing driver internal parameters. | |
215 | * | |
216 | * @v4l2_dev: v4l2_device | |
217 | * @vfd_dec: video device for decoding | |
218 | * @vfd_enc: video device for encoding | |
219 | * @plat_dev: platform device | |
220 | * @mem_dev_l: child device of the left memory bank (0) | |
221 | * @mem_dev_r: child device of the right memory bank (1) | |
222 | * @regs_base: base address of the MFC hw registers | |
223 | * @irq: irq resource | |
af935746 KD |
224 | * @dec_ctrl_handler: control framework handler for decoding |
225 | * @enc_ctrl_handler: control framework handler for encoding | |
226 | * @pm: power management control | |
227 | * @num_inst: couter of active MFC instances | |
228 | * @irqlock: lock for operations on videobuf2 queues | |
229 | * @condlock: lock for changing/checking if a context is ready to be | |
230 | * processed | |
231 | * @mfc_mutex: lock for video_device | |
232 | * @int_cond: variable used by the waitqueue | |
233 | * @int_type: type of last interrupt | |
234 | * @int_err: error number for last interrupt | |
235 | * @queue: waitqueue for waiting for completion of device commands | |
236 | * @fw_size: size of firmware | |
237 | * @bank1: address of the beggining of bank 1 memory | |
238 | * @bank2: address of the beggining of bank 2 memory | |
239 | * @hw_lock: used for hardware locking | |
240 | * @ctx: array of driver contexts | |
241 | * @curr_ctx: number of the currently running context | |
242 | * @ctx_work_bits: used to mark which contexts are waiting for hardware | |
243 | * @watchdog_cnt: counter for the watchdog | |
244 | * @watchdog_workqueue: workqueue for the watchdog | |
245 | * @watchdog_work: worker for the watchdog | |
246 | * @alloc_ctx: videobuf2 allocator contexts for two memory banks | |
247 | * @enter_suspend: flag set when entering suspend | |
43a1ea1f AK |
248 | * @warn_start: hardware error code from which warnings start |
249 | * @mfc_ops: ops structure holding HW operation function pointers | |
250 | * @mfc_cmds: cmd structure holding HW commands function pointers | |
af935746 KD |
251 | * |
252 | */ | |
253 | struct s5p_mfc_dev { | |
254 | struct v4l2_device v4l2_dev; | |
255 | struct video_device *vfd_dec; | |
256 | struct video_device *vfd_enc; | |
257 | struct platform_device *plat_dev; | |
258 | struct device *mem_dev_l; | |
259 | struct device *mem_dev_r; | |
260 | void __iomem *regs_base; | |
261 | int irq; | |
af935746 KD |
262 | struct v4l2_ctrl_handler dec_ctrl_handler; |
263 | struct v4l2_ctrl_handler enc_ctrl_handler; | |
264 | struct s5p_mfc_pm pm; | |
265 | int num_inst; | |
266 | spinlock_t irqlock; /* lock when operating on videobuf2 queues */ | |
267 | spinlock_t condlock; /* lock when changing/checking if a context is | |
268 | ready to be processed */ | |
269 | struct mutex mfc_mutex; /* video_device lock */ | |
270 | int int_cond; | |
271 | int int_type; | |
272 | unsigned int int_err; | |
273 | wait_queue_head_t queue; | |
274 | size_t fw_size; | |
275 | size_t bank1; | |
276 | size_t bank2; | |
277 | unsigned long hw_lock; | |
278 | struct s5p_mfc_ctx *ctx[MFC_NUM_CONTEXTS]; | |
279 | int curr_ctx; | |
280 | unsigned long ctx_work_bits; | |
281 | atomic_t watchdog_cnt; | |
282 | struct timer_list watchdog_timer; | |
283 | struct workqueue_struct *watchdog_workqueue; | |
284 | struct work_struct watchdog_work; | |
285 | void *alloc_ctx[2]; | |
286 | unsigned long enter_suspend; | |
43a1ea1f AK |
287 | |
288 | int warn_start; | |
289 | struct s5p_mfc_hw_ops *mfc_ops; | |
290 | struct s5p_mfc_hw_cmds *mfc_cmds; | |
af935746 KD |
291 | }; |
292 | ||
293 | /** | |
294 | * struct s5p_mfc_h264_enc_params - encoding parameters for h264 | |
295 | */ | |
296 | struct s5p_mfc_h264_enc_params { | |
297 | enum v4l2_mpeg_video_h264_profile profile; | |
298 | enum v4l2_mpeg_video_h264_loop_filter_mode loop_filter_mode; | |
299 | s8 loop_filter_alpha; | |
300 | s8 loop_filter_beta; | |
301 | enum v4l2_mpeg_video_h264_entropy_mode entropy_mode; | |
302 | u8 max_ref_pic; | |
303 | u8 num_ref_pic_4p; | |
304 | int _8x8_transform; | |
305 | int rc_mb; | |
306 | int rc_mb_dark; | |
307 | int rc_mb_smooth; | |
308 | int rc_mb_static; | |
309 | int rc_mb_activity; | |
310 | int vui_sar; | |
311 | u8 vui_sar_idc; | |
312 | u16 vui_ext_sar_width; | |
313 | u16 vui_ext_sar_height; | |
314 | int open_gop; | |
315 | u16 open_gop_size; | |
316 | u8 rc_frame_qp; | |
317 | u8 rc_min_qp; | |
318 | u8 rc_max_qp; | |
319 | u8 rc_p_frame_qp; | |
320 | u8 rc_b_frame_qp; | |
321 | enum v4l2_mpeg_video_h264_level level_v4l2; | |
322 | int level; | |
323 | u16 cpb_size; | |
324 | }; | |
325 | ||
326 | /** | |
327 | * struct s5p_mfc_mpeg4_enc_params - encoding parameters for h263 and mpeg4 | |
328 | */ | |
329 | struct s5p_mfc_mpeg4_enc_params { | |
330 | /* MPEG4 Only */ | |
331 | enum v4l2_mpeg_video_mpeg4_profile profile; | |
332 | int quarter_pixel; | |
333 | /* Common for MPEG4, H263 */ | |
334 | u16 vop_time_res; | |
335 | u16 vop_frm_delta; | |
336 | u8 rc_frame_qp; | |
337 | u8 rc_min_qp; | |
338 | u8 rc_max_qp; | |
339 | u8 rc_p_frame_qp; | |
340 | u8 rc_b_frame_qp; | |
341 | enum v4l2_mpeg_video_mpeg4_level level_v4l2; | |
342 | int level; | |
343 | }; | |
344 | ||
345 | /** | |
346 | * struct s5p_mfc_enc_params - general encoding parameters | |
347 | */ | |
348 | struct s5p_mfc_enc_params { | |
349 | u16 width; | |
350 | u16 height; | |
351 | ||
352 | u16 gop_size; | |
353 | enum v4l2_mpeg_video_multi_slice_mode slice_mode; | |
354 | u16 slice_mb; | |
355 | u32 slice_bit; | |
356 | u16 intra_refresh_mb; | |
357 | int pad; | |
358 | u8 pad_luma; | |
359 | u8 pad_cb; | |
360 | u8 pad_cr; | |
361 | int rc_frame; | |
362 | u32 rc_bitrate; | |
363 | u16 rc_reaction_coeff; | |
364 | u16 vbv_size; | |
365 | ||
366 | enum v4l2_mpeg_video_header_mode seq_hdr_mode; | |
367 | enum v4l2_mpeg_mfc51_video_frame_skip_mode frame_skip_mode; | |
368 | int fixed_target_bit; | |
369 | ||
370 | u8 num_b_frame; | |
371 | u32 rc_framerate_num; | |
372 | u32 rc_framerate_denom; | |
373 | int interlace; | |
374 | ||
375 | union { | |
376 | struct s5p_mfc_h264_enc_params h264; | |
377 | struct s5p_mfc_mpeg4_enc_params mpeg4; | |
378 | } codec; | |
379 | ||
380 | }; | |
381 | ||
382 | /** | |
383 | * struct s5p_mfc_codec_ops - codec ops, used by encoding | |
384 | */ | |
385 | struct s5p_mfc_codec_ops { | |
386 | /* initialization routines */ | |
387 | int (*pre_seq_start) (struct s5p_mfc_ctx *ctx); | |
388 | int (*post_seq_start) (struct s5p_mfc_ctx *ctx); | |
389 | /* execution routines */ | |
390 | int (*pre_frame_start) (struct s5p_mfc_ctx *ctx); | |
391 | int (*post_frame_start) (struct s5p_mfc_ctx *ctx); | |
392 | }; | |
393 | ||
394 | #define call_cop(c, op, args...) \ | |
395 | (((c)->c_ops->op) ? \ | |
396 | ((c)->c_ops->op(args)) : 0) | |
397 | ||
398 | /** | |
399 | * struct s5p_mfc_ctx - This struct contains the instance context | |
400 | * | |
401 | * @dev: pointer to the s5p_mfc_dev of the device | |
402 | * @fh: struct v4l2_fh | |
403 | * @num: number of the context that this structure describes | |
404 | * @int_cond: variable used by the waitqueue | |
405 | * @int_type: type of the last interrupt | |
406 | * @int_err: error number received from MFC hw in the interrupt | |
407 | * @queue: waitqueue that can be used to wait for this context to | |
408 | * finish | |
409 | * @src_fmt: source pixelformat information | |
410 | * @dst_fmt: destination pixelformat information | |
411 | * @vq_src: vb2 queue for source buffers | |
412 | * @vq_dst: vb2 queue for destination buffers | |
413 | * @src_queue: driver internal queue for source buffers | |
414 | * @dst_queue: driver internal queue for destination buffers | |
415 | * @src_queue_cnt: number of buffers queued on the source internal queue | |
416 | * @dst_queue_cnt: number of buffers queued on the dest internal queue | |
417 | * @type: type of the instance - decoder or encoder | |
418 | * @state: state of the context | |
419 | * @inst_no: number of hw instance associated with the context | |
420 | * @img_width: width of the image that is decoded or encoded | |
421 | * @img_height: height of the image that is decoded or encoded | |
422 | * @buf_width: width of the buffer for processed image | |
423 | * @buf_height: height of the buffer for processed image | |
424 | * @luma_size: size of a luma plane | |
425 | * @chroma_size: size of a chroma plane | |
426 | * @mv_size: size of a motion vectors buffer | |
427 | * @consumed_stream: number of bytes that have been used so far from the | |
428 | * decoding buffer | |
429 | * @dpb_flush_flag: flag used to indicate that a DPB buffers are being | |
430 | * flushed | |
431 | * @bank1_buf: handle to memory allocated for temporary buffers from | |
432 | * memory bank 1 | |
433 | * @bank1_phys: address of the temporary buffers from memory bank 1 | |
434 | * @bank1_size: size of the memory allocated for temporary buffers from | |
435 | * memory bank 1 | |
436 | * @bank2_buf: handle to memory allocated for temporary buffers from | |
437 | * memory bank 2 | |
438 | * @bank2_phys: address of the temporary buffers from memory bank 2 | |
439 | * @bank2_size: size of the memory allocated for temporary buffers from | |
440 | * memory bank 2 | |
441 | * @capture_state: state of the capture buffers queue | |
442 | * @output_state: state of the output buffers queue | |
443 | * @src_bufs: information on allocated source buffers | |
444 | * @dst_bufs: information on allocated destination buffers | |
445 | * @sequence: counter for the sequence number for v4l2 | |
446 | * @dec_dst_flag: flags for buffers queued in the hardware | |
447 | * @dec_src_buf_size: size of the buffer for source buffers in decoding | |
448 | * @codec_mode: number of codec mode used by MFC hw | |
449 | * @slice_interface: slice interface flag | |
450 | * @loop_filter_mpeg4: loop filter for MPEG4 flag | |
451 | * @display_delay: value of the display delay for H264 | |
452 | * @display_delay_enable: display delay for H264 enable flag | |
453 | * @after_packed_pb: flag used to track buffer when stream is in | |
454 | * Packed PB format | |
455 | * @dpb_count: count of the DPB buffers required by MFC hw | |
456 | * @total_dpb_count: count of DPB buffers with additional buffers | |
457 | * requested by the application | |
458 | * @ctx_buf: handle to the memory associated with this context | |
459 | * @ctx_phys: address of the memory associated with this context | |
460 | * @ctx_size: size of the memory associated with this context | |
461 | * @desc_buf: description buffer for decoding handle | |
462 | * @desc_phys: description buffer for decoding address | |
463 | * @shm_alloc: handle for the shared memory buffer | |
464 | * @shm: virtual address for the shared memory buffer | |
465 | * @shm_ofs: address offset for shared memory | |
466 | * @enc_params: encoding parameters for MFC | |
467 | * @enc_dst_buf_size: size of the buffers for encoder output | |
468 | * @frame_type: used to force the type of the next encoded frame | |
469 | * @ref_queue: list of the reference buffers for encoding | |
470 | * @ref_queue_cnt: number of the buffers in the reference list | |
471 | * @c_ops: ops for encoding | |
472 | * @ctrls: array of controls, used when adding controls to the | |
473 | * v4l2 control framework | |
474 | * @ctrl_handler: handler for v4l2 framework | |
475 | */ | |
476 | struct s5p_mfc_ctx { | |
477 | struct s5p_mfc_dev *dev; | |
478 | struct v4l2_fh fh; | |
479 | ||
480 | int num; | |
481 | ||
482 | int int_cond; | |
483 | int int_type; | |
484 | unsigned int int_err; | |
485 | wait_queue_head_t queue; | |
486 | ||
487 | struct s5p_mfc_fmt *src_fmt; | |
488 | struct s5p_mfc_fmt *dst_fmt; | |
489 | ||
490 | struct vb2_queue vq_src; | |
491 | struct vb2_queue vq_dst; | |
492 | ||
493 | struct list_head src_queue; | |
494 | struct list_head dst_queue; | |
495 | ||
496 | unsigned int src_queue_cnt; | |
497 | unsigned int dst_queue_cnt; | |
498 | ||
499 | enum s5p_mfc_inst_type type; | |
500 | enum s5p_mfc_inst_state state; | |
501 | int inst_no; | |
502 | ||
503 | /* Image parameters */ | |
504 | int img_width; | |
505 | int img_height; | |
506 | int buf_width; | |
507 | int buf_height; | |
508 | ||
509 | int luma_size; | |
510 | int chroma_size; | |
511 | int mv_size; | |
512 | ||
513 | unsigned long consumed_stream; | |
514 | ||
515 | unsigned int dpb_flush_flag; | |
516 | ||
517 | /* Buffers */ | |
518 | void *bank1_buf; | |
519 | size_t bank1_phys; | |
520 | size_t bank1_size; | |
521 | ||
522 | void *bank2_buf; | |
523 | size_t bank2_phys; | |
524 | size_t bank2_size; | |
525 | ||
526 | enum s5p_mfc_queue_state capture_state; | |
527 | enum s5p_mfc_queue_state output_state; | |
528 | ||
529 | struct s5p_mfc_buf src_bufs[MFC_MAX_BUFFERS]; | |
530 | int src_bufs_cnt; | |
531 | struct s5p_mfc_buf dst_bufs[MFC_MAX_BUFFERS]; | |
532 | int dst_bufs_cnt; | |
533 | ||
534 | unsigned int sequence; | |
535 | unsigned long dec_dst_flag; | |
536 | size_t dec_src_buf_size; | |
537 | ||
538 | /* Control values */ | |
539 | int codec_mode; | |
540 | int slice_interface; | |
541 | int loop_filter_mpeg4; | |
542 | int display_delay; | |
543 | int display_delay_enable; | |
544 | int after_packed_pb; | |
545 | ||
546 | int dpb_count; | |
547 | int total_dpb_count; | |
548 | ||
549 | /* Buffers */ | |
550 | void *ctx_buf; | |
551 | size_t ctx_phys; | |
552 | size_t ctx_ofs; | |
553 | size_t ctx_size; | |
554 | ||
555 | void *desc_buf; | |
556 | size_t desc_phys; | |
557 | ||
558 | ||
559 | void *shm_alloc; | |
560 | void *shm; | |
561 | size_t shm_ofs; | |
562 | ||
563 | struct s5p_mfc_enc_params enc_params; | |
564 | ||
565 | size_t enc_dst_buf_size; | |
566 | ||
567 | enum v4l2_mpeg_mfc51_video_force_frame_type force_frame_type; | |
568 | ||
569 | struct list_head ref_queue; | |
570 | unsigned int ref_queue_cnt; | |
571 | ||
572 | struct s5p_mfc_codec_ops *c_ops; | |
573 | ||
574 | struct v4l2_ctrl *ctrls[MFC_MAX_CTRLS]; | |
575 | struct v4l2_ctrl_handler ctrl_handler; | |
576 | }; | |
577 | ||
578 | /* | |
579 | * struct s5p_mfc_fmt - structure used to store information about pixelformats | |
580 | * used by the MFC | |
581 | */ | |
582 | struct s5p_mfc_fmt { | |
583 | char *name; | |
584 | u32 fourcc; | |
585 | u32 codec_mode; | |
586 | enum s5p_mfc_fmt_type type; | |
587 | u32 num_planes; | |
588 | }; | |
589 | ||
590 | /** | |
591 | * struct mfc_control - structure used to store information about MFC controls | |
592 | * it is used to initialize the control framework. | |
593 | */ | |
594 | struct mfc_control { | |
595 | __u32 id; | |
596 | enum v4l2_ctrl_type type; | |
597 | __u8 name[32]; /* Whatever */ | |
598 | __s32 minimum; /* Note signedness */ | |
599 | __s32 maximum; | |
600 | __s32 step; | |
601 | __u32 menu_skip_mask; | |
602 | __s32 default_value; | |
603 | __u32 flags; | |
604 | __u32 reserved[2]; | |
605 | __u8 is_volatile; | |
606 | }; | |
607 | ||
43a1ea1f AK |
608 | /* Macro for making hardware specific calls */ |
609 | #define s5p_mfc_hw_call(f, op, args...) \ | |
610 | ((f && f->op) ? f->op(args) : -ENODEV) | |
af935746 KD |
611 | |
612 | #define fh_to_ctx(__fh) container_of(__fh, struct s5p_mfc_ctx, fh) | |
613 | #define ctrl_to_ctx(__ctrl) \ | |
614 | container_of((__ctrl)->handler, struct s5p_mfc_ctx, ctrl_handler) | |
615 | ||
7fb89eca AH |
616 | void clear_work_bit(struct s5p_mfc_ctx *ctx); |
617 | void set_work_bit(struct s5p_mfc_ctx *ctx); | |
618 | void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx); | |
619 | void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx); | |
620 | ||
af935746 | 621 | #endif /* S5P_MFC_COMMON_H_ */ |