[mirror_ubuntu-kernels.git] / drivers / media / platform / s5p-mfc / s5p_mfc_ctrl.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * linux/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c
 *
 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com/
 */

#include <linux/delay.h>
#include <linux/err.h>
#include <linux/firmware.h>
#include <linux/jiffies.h>
#include <linux/sched.h>
#include "s5p_mfc_cmd.h"
#include "s5p_mfc_common.h"
#include "s5p_mfc_debug.h"
#include "s5p_mfc_intr.h"
#include "s5p_mfc_opr.h"
#include "s5p_mfc_pm.h"
#include "s5p_mfc_ctrl.h"

/* Allocate memory for firmware */
int s5p_mfc_alloc_firmware(struct s5p_mfc_dev *dev)
{
	struct s5p_mfc_priv_buf *fw_buf = &dev->fw_buf;
	int err;

	fw_buf->size = dev->variant->buf_size->fw;

	if (fw_buf->virt) {
		mfc_err("Attempting to allocate firmware when it seems that it is already loaded\n");
		return -ENOMEM;
	}

	err = s5p_mfc_alloc_priv_buf(dev, BANK_L_CTX, &dev->fw_buf);
	if (err) {
		mfc_err("Allocating bitprocessor buffer failed\n");
		return err;
	}

	return 0;
}

/* Load firmware */
int s5p_mfc_load_firmware(struct s5p_mfc_dev *dev)
{
	struct firmware *fw_blob;
	int i, err = -EINVAL;

	/* Firmware has to be present as a separate file or compiled
	 * into kernel. */
	mfc_debug_enter();

	if (dev->fw_get_done)
		return 0;

	for (i = MFC_FW_MAX_VERSIONS - 1; i >= 0; i--) {
		if (!dev->variant->fw_name[i])
			continue;
		err = request_firmware((const struct firmware **)&fw_blob,
				dev->variant->fw_name[i], &dev->plat_dev->dev);
		if (!err) {
			dev->fw_ver = (enum s5p_mfc_fw_ver) i;
			break;
		}
	}

	if (err != 0) {
		mfc_err("Firmware is not present in the /lib/firmware directory nor compiled in kernel\n");
		return -EINVAL;
	}
	if (fw_blob->size > dev->fw_buf.size) {
		mfc_err("MFC firmware is too big to be loaded\n");
		release_firmware(fw_blob);
		return -ENOMEM;
	}
	memcpy(dev->fw_buf.virt, fw_blob->data, fw_blob->size);
	wmb();
	dev->fw_get_done = true;
	release_firmware(fw_blob);
	mfc_debug_leave();
	return 0;
}

/* Release firmware memory */
int s5p_mfc_release_firmware(struct s5p_mfc_dev *dev)
{
	/* Before calling this function one has to make sure
	 * that MFC is no longer processing */
	s5p_mfc_release_priv_buf(dev, &dev->fw_buf);
	dev->fw_get_done = false;
	return 0;
}

static int s5p_mfc_bus_reset(struct s5p_mfc_dev *dev)
{
	unsigned int status;
	unsigned long timeout;

	/* Reset */
	mfc_write(dev, 0x1, S5P_FIMV_MFC_BUS_RESET_CTRL);
	timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT);
	/* Check bus status */
	do {
		if (time_after(jiffies, timeout)) {
			mfc_err("Timeout while resetting MFC.\n");
			return -EIO;
		}
		status = mfc_read(dev, S5P_FIMV_MFC_BUS_RESET_CTRL);
	} while ((status & 0x2) == 0);
	return 0;
}

/* Reset the device */
int s5p_mfc_reset(struct s5p_mfc_dev *dev)
{
	unsigned int mc_status;
	unsigned long timeout;
	int i;

	mfc_debug_enter();

	if (IS_MFCV6_PLUS(dev)) {
		/* Zero Initialization of MFC registers */
		mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD_V6);
		mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD_V6);
		mfc_write(dev, 0, S5P_FIMV_FW_VERSION_V6);

		for (i = 0; i < S5P_FIMV_REG_CLEAR_COUNT_V6; i++)
			mfc_write(dev, 0, S5P_FIMV_REG_CLEAR_BEGIN_V6 + (i*4));

		/* check bus reset control before reset */
		if (dev->risc_on)
			if (s5p_mfc_bus_reset(dev))
				return -EIO;
		/* Reset
		 * set RISC_ON to 0 during power_on & wake_up.
		 * V6 needs RISC_ON set to 0 during reset also.
		 */
		if ((!dev->risc_on) || (!IS_MFCV7_PLUS(dev)))
			mfc_write(dev, 0, S5P_FIMV_RISC_ON_V6);

		mfc_write(dev, 0x1FFF, S5P_FIMV_MFC_RESET_V6);
		mfc_write(dev, 0, S5P_FIMV_MFC_RESET_V6);
	} else {
		/* Stop procedure */
		/*  reset RISC */
		mfc_write(dev, 0x3f6, S5P_FIMV_SW_RESET);
		/*  All reset except for MC */
		mfc_write(dev, 0x3e2, S5P_FIMV_SW_RESET);
		mdelay(10);

		timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT);
		/* Check MC status */
		do {
			if (time_after(jiffies, timeout)) {
				mfc_err("Timeout while resetting MFC\n");
				return -EIO;
			}

			mc_status = mfc_read(dev, S5P_FIMV_MC_STATUS);

		} while (mc_status & 0x3);

		mfc_write(dev, 0x0, S5P_FIMV_SW_RESET);
		mfc_write(dev, 0x3fe, S5P_FIMV_SW_RESET);
	}

	mfc_debug_leave();
	return 0;
}

static inline void s5p_mfc_init_memctrl(struct s5p_mfc_dev *dev)
{
	if (IS_MFCV6_PLUS(dev)) {
		mfc_write(dev, dev->dma_base[BANK_L_CTX],
			  S5P_FIMV_RISC_BASE_ADDRESS_V6);
		mfc_debug(2, "Base Address : %pad\n",
			  &dev->dma_base[BANK_L_CTX]);
	} else {
		mfc_write(dev, dev->dma_base[BANK_L_CTX],
			  S5P_FIMV_MC_DRAMBASE_ADR_A);
		mfc_write(dev, dev->dma_base[BANK_R_CTX],
			  S5P_FIMV_MC_DRAMBASE_ADR_B);
		mfc_debug(2, "Bank1: %pad, Bank2: %pad\n",
			  &dev->dma_base[BANK_L_CTX],
			  &dev->dma_base[BANK_R_CTX]);
	}
}

static inline void s5p_mfc_clear_cmds(struct s5p_mfc_dev *dev)
{
	if (IS_MFCV6_PLUS(dev)) {
		/* Zero initialization should be done before RESET.
		 * Nothing to do here. */
	} else {
		mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH0_INST_ID);
		mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH1_INST_ID);
		mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
		mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD);
	}
}

/* Initialize hardware */
int s5p_mfc_init_hw(struct s5p_mfc_dev *dev)
{
	unsigned int ver;
	int ret;

	mfc_debug_enter();
	if (!dev->fw_buf.virt) {
		mfc_err("Firmware memory is not allocated.\n");
		return -EINVAL;
	}

	/* 0. MFC reset */
	mfc_debug(2, "MFC reset..\n");
	s5p_mfc_clock_on();
	dev->risc_on = 0;
	ret = s5p_mfc_reset(dev);
	if (ret) {
		mfc_err("Failed to reset MFC - timeout\n");
		return ret;
	}
	mfc_debug(2, "Done MFC reset..\n");
	/* 1. Set DRAM base Addr */
	s5p_mfc_init_memctrl(dev);
	/* 2. Initialize registers of channel I/F */
	s5p_mfc_clear_cmds(dev);
	/* 3. Release reset signal to the RISC */
	s5p_mfc_clean_dev_int_flags(dev);
	if (IS_MFCV6_PLUS(dev)) {
		dev->risc_on = 1;
		mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
	}
	else
		mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);

	if (IS_MFCV10(dev))
		mfc_write(dev, 0x0, S5P_FIMV_MFC_CLOCK_OFF_V10);

	mfc_debug(2, "Will now wait for completion of firmware transfer\n");
	if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_FW_STATUS_RET)) {
		mfc_err("Failed to load firmware\n");
		s5p_mfc_reset(dev);
		s5p_mfc_clock_off();
		return -EIO;
	}
	s5p_mfc_clean_dev_int_flags(dev);
	/* 4. Initialize firmware */
	ret = s5p_mfc_hw_call(dev->mfc_cmds, sys_init_cmd, dev);
	if (ret) {
		mfc_err("Failed to send command to MFC - timeout\n");
		s5p_mfc_reset(dev);
		s5p_mfc_clock_off();
		return ret;
	}
	mfc_debug(2, "Ok, now will wait for completion of hardware init\n");
	if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_SYS_INIT_RET)) {
		mfc_err("Failed to init hardware\n");
		s5p_mfc_reset(dev);
		s5p_mfc_clock_off();
		return -EIO;
	}
	dev->int_cond = 0;
	if (dev->int_err != 0 || dev->int_type !=
					S5P_MFC_R2H_CMD_SYS_INIT_RET) {
		/* Failure. */
		mfc_err("Failed to init firmware - error: %d int: %d\n",
						dev->int_err, dev->int_type);
		s5p_mfc_reset(dev);
		s5p_mfc_clock_off();
		return -EIO;
	}
	if (IS_MFCV6_PLUS(dev))
		ver = mfc_read(dev, S5P_FIMV_FW_VERSION_V6);
	else
		ver = mfc_read(dev, S5P_FIMV_FW_VERSION);

	mfc_debug(2, "MFC F/W version : %02xyy, %02xmm, %02xdd\n",
		(ver >> 16) & 0xFF, (ver >> 8) & 0xFF, ver & 0xFF);
	s5p_mfc_clock_off();
	mfc_debug_leave();
	return 0;
}


/* Deinitialize hardware */
void s5p_mfc_deinit_hw(struct s5p_mfc_dev *dev)
{
	s5p_mfc_clock_on();

	s5p_mfc_reset(dev);
	s5p_mfc_hw_call(dev->mfc_ops, release_dev_context_buffer, dev);

	s5p_mfc_clock_off();
}

int s5p_mfc_sleep(struct s5p_mfc_dev *dev)
{
	int ret;

	mfc_debug_enter();
	s5p_mfc_clock_on();
	s5p_mfc_clean_dev_int_flags(dev);
	ret = s5p_mfc_hw_call(dev->mfc_cmds, sleep_cmd, dev);
	if (ret) {
		mfc_err("Failed to send command to MFC - timeout\n");
		return ret;
	}
	if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_SLEEP_RET)) {
		mfc_err("Failed to sleep\n");
		return -EIO;
	}
	s5p_mfc_clock_off();
	dev->int_cond = 0;
	if (dev->int_err != 0 || dev->int_type !=
						S5P_MFC_R2H_CMD_SLEEP_RET) {
		/* Failure. */
		mfc_err("Failed to sleep - error: %d int: %d\n", dev->int_err,
								dev->int_type);
		return -EIO;
	}
	mfc_debug_leave();
	return ret;
}

static int s5p_mfc_v8_wait_wakeup(struct s5p_mfc_dev *dev)
{
	int ret;

	/* Release reset signal to the RISC */
	dev->risc_on = 1;
	mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);

	if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_FW_STATUS_RET)) {
		mfc_err("Failed to reset MFCV8\n");
		return -EIO;
	}
	mfc_debug(2, "Write command to wakeup MFCV8\n");
	ret = s5p_mfc_hw_call(dev->mfc_cmds, wakeup_cmd, dev);
	if (ret) {
		mfc_err("Failed to send command to MFCV8 - timeout\n");
		return ret;
	}

	if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_WAKEUP_RET)) {
		mfc_err("Failed to wakeup MFC\n");
		return -EIO;
	}
	return ret;
}

static int s5p_mfc_wait_wakeup(struct s5p_mfc_dev *dev)
{
	int ret;

	/* Send MFC wakeup command */
	ret = s5p_mfc_hw_call(dev->mfc_cmds, wakeup_cmd, dev);
	if (ret) {
		mfc_err("Failed to send command to MFC - timeout\n");
		return ret;
	}

	/* Release reset signal to the RISC */
	if (IS_MFCV6_PLUS(dev)) {
		dev->risc_on = 1;
		mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
	} else {
		mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
	}

	if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_WAKEUP_RET)) {
		mfc_err("Failed to wakeup MFC\n");
		return -EIO;
	}
	return ret;
}

int s5p_mfc_wakeup(struct s5p_mfc_dev *dev)
{
	int ret;

	mfc_debug_enter();
	/* 0. MFC reset */
	mfc_debug(2, "MFC reset..\n");
	s5p_mfc_clock_on();
	dev->risc_on = 0;
	ret = s5p_mfc_reset(dev);
	if (ret) {
		mfc_err("Failed to reset MFC - timeout\n");
		s5p_mfc_clock_off();
		return ret;
	}
	mfc_debug(2, "Done MFC reset..\n");
	/* 1. Set DRAM base Addr */
	s5p_mfc_init_memctrl(dev);
	/* 2. Initialize registers of channel I/F */
	s5p_mfc_clear_cmds(dev);
	s5p_mfc_clean_dev_int_flags(dev);
	/* 3. Send MFC wakeup command and wait for completion*/
	if (IS_MFCV8_PLUS(dev))
		ret = s5p_mfc_v8_wait_wakeup(dev);
	else
		ret = s5p_mfc_wait_wakeup(dev);

	s5p_mfc_clock_off();
	if (ret)
		return ret;

	dev->int_cond = 0;
	if (dev->int_err != 0 || dev->int_type !=
						S5P_MFC_R2H_CMD_WAKEUP_RET) {
		/* Failure. */
		mfc_err("Failed to wakeup - error: %d int: %d\n", dev->int_err,
								dev->int_type);
		return -EIO;
	}
	mfc_debug_leave();
	return 0;
}

int s5p_mfc_open_mfc_inst(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx)
{
	int ret = 0;

	ret = s5p_mfc_hw_call(dev->mfc_ops, alloc_instance_buffer, ctx);
	if (ret) {
		mfc_err("Failed allocating instance buffer\n");
		goto err;
	}

	if (ctx->type == MFCINST_DECODER) {
		ret = s5p_mfc_hw_call(dev->mfc_ops,
					alloc_dec_temp_buffers, ctx);
		if (ret) {
			mfc_err("Failed allocating temporary buffers\n");
			goto err_free_inst_buf;
		}
	}

	set_work_bit_irqsave(ctx);
	s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
	if (s5p_mfc_wait_for_done_ctx(ctx,
		S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET, 0)) {
		/* Error or timeout */
		mfc_err("Error getting instance from hardware\n");
		ret = -EIO;
		goto err_free_desc_buf;
	}

	mfc_debug(2, "Got instance number: %d\n", ctx->inst_no);
	return ret;

err_free_desc_buf:
	if (ctx->type == MFCINST_DECODER)
		s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer, ctx);
err_free_inst_buf:
	s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx);
err:
	return ret;
}

void s5p_mfc_close_mfc_inst(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx)
{
	ctx->state = MFCINST_RETURN_INST;
	set_work_bit_irqsave(ctx);
	s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
	/* Wait until instance is returned or timeout occurred */
	if (s5p_mfc_wait_for_done_ctx(ctx,
				S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET, 0))
		mfc_err("Err returning instance\n");

	/* Free resources */
	s5p_mfc_hw_call(dev->mfc_ops, release_codec_buffers, ctx);
	s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx);
	if (ctx->type == MFCINST_DECODER)
		s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer, ctx);

	ctx->inst_no = MFC_NO_INSTANCE_SET;
	ctx->state = MFCINST_FREE;
}
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
af935746	2	/*
2c3fb08b	3	* linux/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c
af935746 KD	4	*
	5	* Copyright (c) 2010 Samsung Electronics Co., Ltd.
	6	* http://www.samsung.com/
af935746 KD	7	*/
	8
	9	#include <linux/delay.h>
	10	#include <linux/err.h>
	11	#include <linux/firmware.h>
	12	#include <linux/jiffies.h>
	13	#include <linux/sched.h>
43a1ea1f	14	#include "s5p_mfc_cmd.h"
af935746 KD	15	#include "s5p_mfc_common.h"
	16	#include "s5p_mfc_debug.h"
	17	#include "s5p_mfc_intr.h"
43a1ea1f	18	#include "s5p_mfc_opr.h"
af935746	19	#include "s5p_mfc_pm.h"
b171e3d8	20	#include "s5p_mfc_ctrl.h"
af935746	21
2e731e44 KD	22	/* Allocate memory for firmware */
	23	int s5p_mfc_alloc_firmware(struct s5p_mfc_dev *dev)
	24	{
ba5d4563	25	struct s5p_mfc_priv_buf *fw_buf = &dev->fw_buf;
d1ff4e17	26	int err;
2e731e44	27
ba5d4563	28	fw_buf->size = dev->variant->buf_size->fw;
2e731e44	29
ba5d4563	30	if (fw_buf->virt) {
2e731e44 KD	31	mfc_err("Attempting to allocate firmware when it seems that it is already loaded\n");
	32	return -ENOMEM;
	33	}
	34
5ea289fe	35	err = s5p_mfc_alloc_priv_buf(dev, BANK_L_CTX, &dev->fw_buf);
d1ff4e17	36	if (err) {
2e731e44	37	mfc_err("Allocating bitprocessor buffer failed\n");
d1ff4e17	38	return err;
2e731e44 KD	39	}
2e731e44 KD	40
2e731e44 KD	41	return 0;
2e731e44 KD	42	}
af935746	43
2e731e44 KD	44	/* Load firmware */
2e731e44 KD	45	int s5p_mfc_load_firmware(struct s5p_mfc_dev *dev)
af935746 KD	46	{
af935746 KD	47	struct firmware *fw_blob;
77ba6b73	48	int i, err = -EINVAL;
af935746	49
8b72c18d	50	/* Firmware has to be present as a separate file or compiled
af935746 KD	51	* into kernel. */
af935746 KD	52	mfc_debug_enter();
f96f3cfa	53
f45ce987 SK	54	if (dev->fw_get_done)
	55	return 0;
	56
77ba6b73 AK	57	for (i = MFC_FW_MAX_VERSIONS - 1; i >= 0; i--) {
	58	if (!dev->variant->fw_name[i])
	59	continue;
	60	err = request_firmware((const struct firmware **)&fw_blob,
c8e6f90d	61	dev->variant->fw_name[i], &dev->plat_dev->dev);
77ba6b73 AK	62	if (!err) {
	63	dev->fw_ver = (enum s5p_mfc_fw_ver) i;
	64	break;
	65	}
	66	}
	67
af935746 KD	68	if (err != 0) {
	69	mfc_err("Firmware is not present in the /lib/firmware directory nor compiled in kernel\n");
	70	return -EINVAL;
	71	}
ba5d4563	72	if (fw_blob->size > dev->fw_buf.size) {
af935746 KD	73	mfc_err("MFC firmware is too big to be loaded\n");
	74	release_firmware(fw_blob);
	75	return -ENOMEM;
	76	}
ba5d4563	77	memcpy(dev->fw_buf.virt, fw_blob->data, fw_blob->size);
af935746	78	wmb();
f45ce987	79	dev->fw_get_done = true;
af935746 KD	80	release_firmware(fw_blob);
	81	mfc_debug_leave();
	82	return 0;
	83	}
	84
	85	/* Release firmware memory */
	86	int s5p_mfc_release_firmware(struct s5p_mfc_dev *dev)
	87	{
	88	/* Before calling this function one has to make sure
	89	* that MFC is no longer processing */
d1ff4e17	90	s5p_mfc_release_priv_buf(dev, &dev->fw_buf);
f45ce987	91	dev->fw_get_done = false;
af935746 KD	92	return 0;
	93	}
	94
5932f74a	95	static int s5p_mfc_bus_reset(struct s5p_mfc_dev *dev)
09accdad KA	96	{
	97	unsigned int status;
	98	unsigned long timeout;
	99
	100	/* Reset */
	101	mfc_write(dev, 0x1, S5P_FIMV_MFC_BUS_RESET_CTRL);
	102	timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT);
	103	/* Check bus status */
	104	do {
	105	if (time_after(jiffies, timeout)) {
	106	mfc_err("Timeout while resetting MFC.\n");
	107	return -EIO;
	108	}
	109	status = mfc_read(dev, S5P_FIMV_MFC_BUS_RESET_CTRL);
	110	} while ((status & 0x2) == 0);
	111	return 0;
	112	}
	113
af935746 KD	114	/* Reset the device */
	115	int s5p_mfc_reset(struct s5p_mfc_dev *dev)
	116	{
	117	unsigned int mc_status;
	118	unsigned long timeout;
f96f3cfa	119	int i;
af935746 KD	120
af935746 KD	121	mfc_debug_enter();
af935746	122
722b979e	123	if (IS_MFCV6_PLUS(dev)) {
f96f3cfa JP	124	/* Zero Initialization of MFC registers */
	125	mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD_V6);
	126	mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD_V6);
	127	mfc_write(dev, 0, S5P_FIMV_FW_VERSION_V6);
	128
	129	for (i = 0; i < S5P_FIMV_REG_CLEAR_COUNT_V6; i++)
	130	mfc_write(dev, 0, S5P_FIMV_REG_CLEAR_BEGIN_V6 + (i*4));
	131
09accdad KA	132	/* check bus reset control before reset */
	133	if (dev->risc_on)
	134	if (s5p_mfc_bus_reset(dev))
	135	return -EIO;
d7dce6a3 KA	136	/* Reset
	137	* set RISC_ON to 0 during power_on & wake_up.
	138	* V6 needs RISC_ON set to 0 during reset also.
	139	*/
09accdad	140	if ((!dev->risc_on) \|\| (!IS_MFCV7_PLUS(dev)))
d7dce6a3 KA	141	mfc_write(dev, 0, S5P_FIMV_RISC_ON_V6);
d7dce6a3 KA	142
f96f3cfa JP	143	mfc_write(dev, 0x1FFF, S5P_FIMV_MFC_RESET_V6);
	144	mfc_write(dev, 0, S5P_FIMV_MFC_RESET_V6);
	145	} else {
	146	/* Stop procedure */
	147	/* reset RISC */
	148	mfc_write(dev, 0x3f6, S5P_FIMV_SW_RESET);
	149	/* All reset except for MC */
	150	mfc_write(dev, 0x3e2, S5P_FIMV_SW_RESET);
	151	mdelay(10);
af935746	152
f96f3cfa JP	153	timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT);
	154	/* Check MC status */
	155	do {
	156	if (time_after(jiffies, timeout)) {
	157	mfc_err("Timeout while resetting MFC\n");
	158	return -EIO;
	159	}
	160
	161	mc_status = mfc_read(dev, S5P_FIMV_MC_STATUS);
	162
	163	} while (mc_status & 0x3);
	164
	165	mfc_write(dev, 0x0, S5P_FIMV_SW_RESET);
	166	mfc_write(dev, 0x3fe, S5P_FIMV_SW_RESET);
	167	}
af935746	168
af935746 KD	169	mfc_debug_leave();
	170	return 0;
	171	}
	172
	173	static inline void s5p_mfc_init_memctrl(struct s5p_mfc_dev *dev)
	174	{
722b979e	175	if (IS_MFCV6_PLUS(dev)) {
5ea289fe	176	mfc_write(dev, dev->dma_base[BANK_L_CTX],
0d9e301b MS	177	S5P_FIMV_RISC_BASE_ADDRESS_V6);
0d9e301b MS	178	mfc_debug(2, "Base Address : %pad\n",
5ea289fe	179	&dev->dma_base[BANK_L_CTX]);
f96f3cfa	180	} else {
5ea289fe	181	mfc_write(dev, dev->dma_base[BANK_L_CTX],
0d9e301b	182	S5P_FIMV_MC_DRAMBASE_ADR_A);
5ea289fe	183	mfc_write(dev, dev->dma_base[BANK_R_CTX],
0d9e301b	184	S5P_FIMV_MC_DRAMBASE_ADR_B);
03ce7816	185	mfc_debug(2, "Bank1: %pad, Bank2: %pad\n",
5ea289fe MS	186	&dev->dma_base[BANK_L_CTX],
5ea289fe MS	187	&dev->dma_base[BANK_R_CTX]);
f96f3cfa	188	}
af935746 KD	189	}
	190
	191	static inline void s5p_mfc_clear_cmds(struct s5p_mfc_dev *dev)
	192	{
722b979e	193	if (IS_MFCV6_PLUS(dev)) {
f96f3cfa JP	194	/* Zero initialization should be done before RESET.
	195	* Nothing to do here. */
	196	} else {
	197	mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH0_INST_ID);
	198	mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH1_INST_ID);
	199	mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
	200	mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD);
	201	}
af935746 KD	202	}
	203
	204	/* Initialize hardware */
	205	int s5p_mfc_init_hw(struct s5p_mfc_dev *dev)
	206	{
	207	unsigned int ver;
	208	int ret;
	209
	210	mfc_debug_enter();
ba5d4563	211	if (!dev->fw_buf.virt) {
2e731e44	212	mfc_err("Firmware memory is not allocated.\n");
af935746	213	return -EINVAL;
2e731e44	214	}
af935746 KD	215
	216	/* 0. MFC reset */
	217	mfc_debug(2, "MFC reset..\n");
	218	s5p_mfc_clock_on();
d7dce6a3	219	dev->risc_on = 0;
af935746 KD	220	ret = s5p_mfc_reset(dev);
	221	if (ret) {
	222	mfc_err("Failed to reset MFC - timeout\n");
	223	return ret;
	224	}
	225	mfc_debug(2, "Done MFC reset..\n");
	226	/* 1. Set DRAM base Addr */
	227	s5p_mfc_init_memctrl(dev);
	228	/* 2. Initialize registers of channel I/F */
	229	s5p_mfc_clear_cmds(dev);
	230	/* 3. Release reset signal to the RISC */
	231	s5p_mfc_clean_dev_int_flags(dev);
d7dce6a3 KA	232	if (IS_MFCV6_PLUS(dev)) {
d7dce6a3 KA	233	dev->risc_on = 1;
f96f3cfa	234	mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
d7dce6a3	235	}
f96f3cfa JP	236	else
f96f3cfa JP	237	mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
b1394dc1 SM	238
	239	if (IS_MFCV10(dev))
	240	mfc_write(dev, 0x0, S5P_FIMV_MFC_CLOCK_OFF_V10);
	241
af935746	242	mfc_debug(2, "Will now wait for completion of firmware transfer\n");
43a1ea1f	243	if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_FW_STATUS_RET)) {
af935746 KD	244	mfc_err("Failed to load firmware\n");
	245	s5p_mfc_reset(dev);
	246	s5p_mfc_clock_off();
	247	return -EIO;
	248	}
	249	s5p_mfc_clean_dev_int_flags(dev);
	250	/* 4. Initialize firmware */
43a1ea1f	251	ret = s5p_mfc_hw_call(dev->mfc_cmds, sys_init_cmd, dev);
af935746 KD	252	if (ret) {
	253	mfc_err("Failed to send command to MFC - timeout\n");
	254	s5p_mfc_reset(dev);
	255	s5p_mfc_clock_off();
	256	return ret;
	257	}
e47ccb1d	258	mfc_debug(2, "Ok, now will wait for completion of hardware init\n");
43a1ea1f	259	if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_SYS_INIT_RET)) {
e47ccb1d	260	mfc_err("Failed to init hardware\n");
af935746 KD	261	s5p_mfc_reset(dev);
	262	s5p_mfc_clock_off();
	263	return -EIO;
	264	}
	265	dev->int_cond = 0;
	266	if (dev->int_err != 0 \|\| dev->int_type !=
43a1ea1f	267	S5P_MFC_R2H_CMD_SYS_INIT_RET) {
af935746 KD	268	/* Failure. */
	269	mfc_err("Failed to init firmware - error: %d int: %d\n",
	270	dev->int_err, dev->int_type);
	271	s5p_mfc_reset(dev);
	272	s5p_mfc_clock_off();
	273	return -EIO;
	274	}
722b979e	275	if (IS_MFCV6_PLUS(dev))
f96f3cfa JP	276	ver = mfc_read(dev, S5P_FIMV_FW_VERSION_V6);
	277	else
	278	ver = mfc_read(dev, S5P_FIMV_FW_VERSION);
	279
af935746 KD	280	mfc_debug(2, "MFC F/W version : %02xyy, %02xmm, %02xdd\n",
	281	(ver >> 16) & 0xFF, (ver >> 8) & 0xFF, ver & 0xFF);
	282	s5p_mfc_clock_off();
	283	mfc_debug_leave();
	284	return 0;
	285	}
	286
	287
43a1ea1f AK	288	/* Deinitialize hardware */
	289	void s5p_mfc_deinit_hw(struct s5p_mfc_dev *dev)
	290	{
	291	s5p_mfc_clock_on();
	292
	293	s5p_mfc_reset(dev);
fdd1d4b0	294	s5p_mfc_hw_call(dev->mfc_ops, release_dev_context_buffer, dev);
43a1ea1f AK	295
	296	s5p_mfc_clock_off();
	297	}
	298
af935746 KD	299	int s5p_mfc_sleep(struct s5p_mfc_dev *dev)
	300	{
	301	int ret;
	302
	303	mfc_debug_enter();
	304	s5p_mfc_clock_on();
	305	s5p_mfc_clean_dev_int_flags(dev);
43a1ea1f	306	ret = s5p_mfc_hw_call(dev->mfc_cmds, sleep_cmd, dev);
af935746 KD	307	if (ret) {
	308	mfc_err("Failed to send command to MFC - timeout\n");
	309	return ret;
	310	}
43a1ea1f	311	if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_SLEEP_RET)) {
af935746 KD	312	mfc_err("Failed to sleep\n");
	313	return -EIO;
	314	}
	315	s5p_mfc_clock_off();
	316	dev->int_cond = 0;
	317	if (dev->int_err != 0 \|\| dev->int_type !=
43a1ea1f	318	S5P_MFC_R2H_CMD_SLEEP_RET) {
af935746 KD	319	/* Failure. */
	320	mfc_err("Failed to sleep - error: %d int: %d\n", dev->int_err,
	321	dev->int_type);
	322	return -EIO;
	323	}
	324	mfc_debug_leave();
	325	return ret;
	326	}
	327
773e6352 AM	328	static int s5p_mfc_v8_wait_wakeup(struct s5p_mfc_dev *dev)
	329	{
	330	int ret;
	331
	332	/* Release reset signal to the RISC */
	333	dev->risc_on = 1;
	334	mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
	335
	336	if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_FW_STATUS_RET)) {
	337	mfc_err("Failed to reset MFCV8\n");
	338	return -EIO;
	339	}
	340	mfc_debug(2, "Write command to wakeup MFCV8\n");
	341	ret = s5p_mfc_hw_call(dev->mfc_cmds, wakeup_cmd, dev);
	342	if (ret) {
	343	mfc_err("Failed to send command to MFCV8 - timeout\n");
	344	return ret;
	345	}
	346
	347	if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_WAKEUP_RET)) {
	348	mfc_err("Failed to wakeup MFC\n");
	349	return -EIO;
	350	}
	351	return ret;
	352	}
	353
	354	static int s5p_mfc_wait_wakeup(struct s5p_mfc_dev *dev)
	355	{
	356	int ret;
	357
	358	/* Send MFC wakeup command */
	359	ret = s5p_mfc_hw_call(dev->mfc_cmds, wakeup_cmd, dev);
	360	if (ret) {
	361	mfc_err("Failed to send command to MFC - timeout\n");
	362	return ret;
	363	}
	364
	365	/* Release reset signal to the RISC */
	366	if (IS_MFCV6_PLUS(dev)) {
	367	dev->risc_on = 1;
	368	mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
	369	} else {
	370	mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
	371	}
	372
	373	if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_WAKEUP_RET)) {
	374	mfc_err("Failed to wakeup MFC\n");
	375	return -EIO;
	376	}
	377	return ret;
	378	}
	379
af935746 KD	380	int s5p_mfc_wakeup(struct s5p_mfc_dev *dev)
	381	{
	382	int ret;
	383
	384	mfc_debug_enter();
	385	/* 0. MFC reset */
	386	mfc_debug(2, "MFC reset..\n");
	387	s5p_mfc_clock_on();
d7dce6a3	388	dev->risc_on = 0;
af935746 KD	389	ret = s5p_mfc_reset(dev);
	390	if (ret) {
	391	mfc_err("Failed to reset MFC - timeout\n");
773e6352	392	s5p_mfc_clock_off();
af935746 KD	393	return ret;
	394	}
	395	mfc_debug(2, "Done MFC reset..\n");
	396	/* 1. Set DRAM base Addr */
	397	s5p_mfc_init_memctrl(dev);
	398	/* 2. Initialize registers of channel I/F */
	399	s5p_mfc_clear_cmds(dev);
	400	s5p_mfc_clean_dev_int_flags(dev);
773e6352	401	/* 3. Send MFC wakeup command and wait for completion*/
f1a355bf	402	if (IS_MFCV8_PLUS(dev))
773e6352	403	ret = s5p_mfc_v8_wait_wakeup(dev);
f96f3cfa	404	else
773e6352 AM	405	ret = s5p_mfc_wait_wakeup(dev);
773e6352 AM	406
af935746	407	s5p_mfc_clock_off();
773e6352 AM	408	if (ret)
	409	return ret;
	410
af935746 KD	411	dev->int_cond = 0;
af935746 KD	412	if (dev->int_err != 0 \|\| dev->int_type !=
43a1ea1f	413	S5P_MFC_R2H_CMD_WAKEUP_RET) {
af935746 KD	414	/* Failure. */
	415	mfc_err("Failed to wakeup - error: %d int: %d\n", dev->int_err,
	416	dev->int_type);
	417	return -EIO;
	418	}
	419	mfc_debug_leave();
	420	return 0;
	421	}
	422
818cd91a PO	423	int s5p_mfc_open_mfc_inst(struct s5p_mfc_dev dev, struct s5p_mfc_ctx ctx)
	424	{
	425	int ret = 0;
	426
	427	ret = s5p_mfc_hw_call(dev->mfc_ops, alloc_instance_buffer, ctx);
	428	if (ret) {
	429	mfc_err("Failed allocating instance buffer\n");
	430	goto err;
	431	}
	432
	433	if (ctx->type == MFCINST_DECODER) {
	434	ret = s5p_mfc_hw_call(dev->mfc_ops,
	435	alloc_dec_temp_buffers, ctx);
	436	if (ret) {
	437	mfc_err("Failed allocating temporary buffers\n");
	438	goto err_free_inst_buf;
	439	}
	440	}
	441
	442	set_work_bit_irqsave(ctx);
fdd1d4b0	443	s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
818cd91a PO	444	if (s5p_mfc_wait_for_done_ctx(ctx,
	445	S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET, 0)) {
	446	/* Error or timeout */
	447	mfc_err("Error getting instance from hardware\n");
	448	ret = -EIO;
	449	goto err_free_desc_buf;
	450	}
	451
	452	mfc_debug(2, "Got instance number: %d\n", ctx->inst_no);
	453	return ret;
	454
	455	err_free_desc_buf:
	456	if (ctx->type == MFCINST_DECODER)
fdd1d4b0	457	s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer, ctx);
818cd91a	458	err_free_inst_buf:
fdd1d4b0	459	s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx);
818cd91a PO	460	err:
	461	return ret;
	462	}
	463
	464	void s5p_mfc_close_mfc_inst(struct s5p_mfc_dev dev, struct s5p_mfc_ctx ctx)
	465	{
	466	ctx->state = MFCINST_RETURN_INST;
	467	set_work_bit_irqsave(ctx);
fdd1d4b0	468	s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
818cd91a PO	469	/* Wait until instance is returned or timeout occurred */
	470	if (s5p_mfc_wait_for_done_ctx(ctx,
	471	S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET, 0))
	472	mfc_err("Err returning instance\n");
	473
	474	/* Free resources */
fdd1d4b0 AH	475	s5p_mfc_hw_call(dev->mfc_ops, release_codec_buffers, ctx);
fdd1d4b0 AH	476	s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx);
818cd91a	477	if (ctx->type == MFCINST_DECODER)
fdd1d4b0	478	s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer, ctx);
818cd91a	479
9d87e837	480	ctx->inst_no = MFC_NO_INSTANCE_SET;
818cd91a PO	481	ctx->state = MFCINST_FREE;
818cd91a PO	482	}