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f96f3cfa JP |
1 | /* |
2 | * drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c | |
3 | * | |
4 | * Samsung MFC (Multi Function Codec - FIMV) driver | |
5 | * This file contains hw related functions. | |
6 | * | |
7 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
8 | * http://www.samsung.com/ | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #undef DEBUG | |
16 | ||
17 | #include <linux/delay.h> | |
18 | #include <linux/mm.h> | |
19 | #include <linux/io.h> | |
20 | #include <linux/jiffies.h> | |
21 | #include <linux/firmware.h> | |
22 | #include <linux/err.h> | |
23 | #include <linux/sched.h> | |
24 | #include <linux/dma-mapping.h> | |
25 | ||
26 | #include <asm/cacheflush.h> | |
27 | ||
28 | #include "s5p_mfc_common.h" | |
29 | #include "s5p_mfc_cmd.h" | |
30 | #include "s5p_mfc_intr.h" | |
31 | #include "s5p_mfc_pm.h" | |
32 | #include "s5p_mfc_debug.h" | |
33 | #include "s5p_mfc_opr.h" | |
34 | #include "s5p_mfc_opr_v6.h" | |
35 | ||
36 | /* #define S5P_MFC_DEBUG_REGWRITE */ | |
37 | #ifdef S5P_MFC_DEBUG_REGWRITE | |
38 | #undef writel | |
39 | #define writel(v, r) \ | |
40 | do { \ | |
41 | pr_err("MFCWRITE(%p): %08x\n", r, (unsigned int)v); \ | |
42 | __raw_writel(v, r); \ | |
43 | } while (0) | |
44 | #endif /* S5P_MFC_DEBUG_REGWRITE */ | |
45 | ||
46 | #define READL(offset) readl(dev->regs_base + (offset)) | |
47 | #define WRITEL(data, offset) writel((data), dev->regs_base + (offset)) | |
48 | #define OFFSETA(x) (((x) - dev->port_a) >> S5P_FIMV_MEM_OFFSET) | |
49 | #define OFFSETB(x) (((x) - dev->port_b) >> S5P_FIMV_MEM_OFFSET) | |
50 | ||
51 | /* Allocate temporary buffers for decoding */ | |
52 | int s5p_mfc_alloc_dec_temp_buffers_v6(struct s5p_mfc_ctx *ctx) | |
53 | { | |
54 | /* NOP */ | |
55 | ||
56 | return 0; | |
57 | } | |
58 | ||
59 | /* Release temproary buffers for decoding */ | |
60 | void s5p_mfc_release_dec_desc_buffer_v6(struct s5p_mfc_ctx *ctx) | |
61 | { | |
62 | /* NOP */ | |
63 | } | |
64 | ||
65 | int s5p_mfc_get_dec_status_v6(struct s5p_mfc_dev *dev) | |
66 | { | |
67 | /* NOP */ | |
68 | return -1; | |
69 | } | |
70 | ||
71 | /* Allocate codec buffers */ | |
72 | int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) | |
73 | { | |
74 | struct s5p_mfc_dev *dev = ctx->dev; | |
75 | unsigned int mb_width, mb_height; | |
76 | ||
77 | mb_width = MB_WIDTH(ctx->img_width); | |
78 | mb_height = MB_HEIGHT(ctx->img_height); | |
79 | ||
80 | if (ctx->type == MFCINST_DECODER) { | |
81 | mfc_debug(2, "Luma size:%d Chroma size:%d MV size:%d\n", | |
82 | ctx->luma_size, ctx->chroma_size, ctx->mv_size); | |
83 | mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count); | |
84 | } else if (ctx->type == MFCINST_ENCODER) { | |
85 | ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 * | |
86 | ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V6(mb_width, mb_height), | |
87 | S5P_FIMV_TMV_BUFFER_ALIGN_V6); | |
88 | ctx->luma_dpb_size = ALIGN((mb_width * mb_height) * | |
89 | S5P_FIMV_LUMA_MB_TO_PIXEL_V6, | |
90 | S5P_FIMV_LUMA_DPB_BUFFER_ALIGN_V6); | |
91 | ctx->chroma_dpb_size = ALIGN((mb_width * mb_height) * | |
92 | S5P_FIMV_CHROMA_MB_TO_PIXEL_V6, | |
93 | S5P_FIMV_CHROMA_DPB_BUFFER_ALIGN_V6); | |
94 | ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V6( | |
95 | ctx->img_width, ctx->img_height, | |
96 | mb_width, mb_height), | |
97 | S5P_FIMV_ME_BUFFER_ALIGN_V6); | |
98 | ||
99 | mfc_debug(2, "recon luma size: %d chroma size: %d\n", | |
100 | ctx->luma_dpb_size, ctx->chroma_dpb_size); | |
101 | } else { | |
102 | return -EINVAL; | |
103 | } | |
104 | ||
105 | /* Codecs have different memory requirements */ | |
106 | switch (ctx->codec_mode) { | |
107 | case S5P_MFC_CODEC_H264_DEC: | |
108 | case S5P_MFC_CODEC_H264_MVC_DEC: | |
109 | ctx->scratch_buf_size = | |
110 | S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V6( | |
111 | mb_width, | |
112 | mb_height); | |
113 | ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, | |
114 | S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6); | |
115 | ctx->bank1_size = | |
116 | ctx->scratch_buf_size + | |
117 | (ctx->mv_count * ctx->mv_size); | |
118 | break; | |
119 | case S5P_MFC_CODEC_MPEG4_DEC: | |
120 | ctx->scratch_buf_size = | |
121 | S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V6( | |
122 | mb_width, | |
123 | mb_height); | |
124 | ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, | |
125 | S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6); | |
126 | ctx->bank1_size = ctx->scratch_buf_size; | |
127 | break; | |
128 | case S5P_MFC_CODEC_VC1RCV_DEC: | |
129 | case S5P_MFC_CODEC_VC1_DEC: | |
130 | ctx->scratch_buf_size = | |
131 | S5P_FIMV_SCRATCH_BUF_SIZE_VC1_DEC_V6( | |
132 | mb_width, | |
133 | mb_height); | |
134 | ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, | |
135 | S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6); | |
136 | ctx->bank1_size = ctx->scratch_buf_size; | |
137 | break; | |
138 | case S5P_MFC_CODEC_MPEG2_DEC: | |
139 | ctx->bank1_size = 0; | |
140 | ctx->bank2_size = 0; | |
141 | break; | |
142 | case S5P_MFC_CODEC_H263_DEC: | |
143 | ctx->scratch_buf_size = | |
144 | S5P_FIMV_SCRATCH_BUF_SIZE_H263_DEC_V6( | |
145 | mb_width, | |
146 | mb_height); | |
147 | ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, | |
148 | S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6); | |
149 | ctx->bank1_size = ctx->scratch_buf_size; | |
150 | break; | |
151 | case S5P_MFC_CODEC_VP8_DEC: | |
152 | ctx->scratch_buf_size = | |
153 | S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V6( | |
154 | mb_width, | |
155 | mb_height); | |
156 | ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, | |
157 | S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6); | |
158 | ctx->bank1_size = ctx->scratch_buf_size; | |
159 | break; | |
160 | case S5P_MFC_CODEC_H264_ENC: | |
161 | ctx->scratch_buf_size = | |
162 | S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V6( | |
163 | mb_width, | |
164 | mb_height); | |
165 | ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, | |
166 | S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6); | |
167 | ctx->bank1_size = | |
168 | ctx->scratch_buf_size + ctx->tmv_buffer_size + | |
169 | (ctx->dpb_count * (ctx->luma_dpb_size + | |
170 | ctx->chroma_dpb_size + ctx->me_buffer_size)); | |
171 | ctx->bank2_size = 0; | |
172 | break; | |
173 | case S5P_MFC_CODEC_MPEG4_ENC: | |
174 | case S5P_MFC_CODEC_H263_ENC: | |
175 | ctx->scratch_buf_size = | |
176 | S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_ENC_V6( | |
177 | mb_width, | |
178 | mb_height); | |
179 | ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, | |
180 | S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6); | |
181 | ctx->bank1_size = | |
182 | ctx->scratch_buf_size + ctx->tmv_buffer_size + | |
183 | (ctx->dpb_count * (ctx->luma_dpb_size + | |
184 | ctx->chroma_dpb_size + ctx->me_buffer_size)); | |
185 | ctx->bank2_size = 0; | |
186 | break; | |
187 | default: | |
188 | break; | |
189 | } | |
190 | ||
191 | /* Allocate only if memory from bank 1 is necessary */ | |
192 | if (ctx->bank1_size > 0) { | |
193 | ctx->bank1_buf = vb2_dma_contig_memops.alloc( | |
194 | dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], ctx->bank1_size); | |
195 | if (IS_ERR(ctx->bank1_buf)) { | |
196 | ctx->bank1_buf = 0; | |
197 | pr_err("Buf alloc for decoding failed (port A)\n"); | |
198 | return -ENOMEM; | |
199 | } | |
200 | ctx->bank1_phys = s5p_mfc_mem_cookie( | |
201 | dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], ctx->bank1_buf); | |
202 | BUG_ON(ctx->bank1_phys & ((1 << MFC_BANK1_ALIGN_ORDER) - 1)); | |
203 | } | |
204 | ||
205 | return 0; | |
206 | } | |
207 | ||
208 | /* Release buffers allocated for codec */ | |
209 | void s5p_mfc_release_codec_buffers_v6(struct s5p_mfc_ctx *ctx) | |
210 | { | |
211 | if (ctx->bank1_buf) { | |
212 | vb2_dma_contig_memops.put(ctx->bank1_buf); | |
213 | ctx->bank1_buf = 0; | |
214 | ctx->bank1_phys = 0; | |
215 | ctx->bank1_size = 0; | |
216 | } | |
217 | } | |
218 | ||
219 | /* Allocate memory for instance data buffer */ | |
220 | int s5p_mfc_alloc_instance_buffer_v6(struct s5p_mfc_ctx *ctx) | |
221 | { | |
222 | struct s5p_mfc_dev *dev = ctx->dev; | |
223 | struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv; | |
224 | ||
225 | mfc_debug_enter(); | |
226 | ||
227 | switch (ctx->codec_mode) { | |
228 | case S5P_MFC_CODEC_H264_DEC: | |
229 | case S5P_MFC_CODEC_H264_MVC_DEC: | |
230 | ctx->ctx.size = buf_size->h264_dec_ctx; | |
231 | break; | |
232 | case S5P_MFC_CODEC_MPEG4_DEC: | |
233 | case S5P_MFC_CODEC_H263_DEC: | |
234 | case S5P_MFC_CODEC_VC1RCV_DEC: | |
235 | case S5P_MFC_CODEC_VC1_DEC: | |
236 | case S5P_MFC_CODEC_MPEG2_DEC: | |
237 | case S5P_MFC_CODEC_VP8_DEC: | |
238 | ctx->ctx.size = buf_size->other_dec_ctx; | |
239 | break; | |
240 | case S5P_MFC_CODEC_H264_ENC: | |
241 | ctx->ctx.size = buf_size->h264_enc_ctx; | |
242 | break; | |
243 | case S5P_MFC_CODEC_MPEG4_ENC: | |
244 | case S5P_MFC_CODEC_H263_ENC: | |
245 | ctx->ctx.size = buf_size->other_enc_ctx; | |
246 | break; | |
247 | default: | |
248 | ctx->ctx.size = 0; | |
249 | mfc_err("Codec type(%d) should be checked!\n", ctx->codec_mode); | |
250 | break; | |
251 | } | |
252 | ||
253 | ctx->ctx.alloc = vb2_dma_contig_memops.alloc( | |
254 | dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], ctx->ctx.size); | |
255 | if (IS_ERR(ctx->ctx.alloc)) { | |
256 | mfc_err("Allocating context buffer failed.\n"); | |
257 | return PTR_ERR(ctx->ctx.alloc); | |
258 | } | |
259 | ||
260 | ctx->ctx.dma = s5p_mfc_mem_cookie( | |
261 | dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], ctx->ctx.alloc); | |
262 | ||
263 | ctx->ctx.virt = vb2_dma_contig_memops.vaddr(ctx->ctx.alloc); | |
264 | if (!ctx->ctx.virt) { | |
265 | vb2_dma_contig_memops.put(ctx->ctx.alloc); | |
266 | ctx->ctx.alloc = NULL; | |
267 | ctx->ctx.dma = 0; | |
268 | ctx->ctx.virt = NULL; | |
269 | ||
270 | mfc_err("Remapping context buffer failed.\n"); | |
271 | return -ENOMEM; | |
272 | } | |
273 | ||
274 | memset(ctx->ctx.virt, 0, ctx->ctx.size); | |
275 | wmb(); | |
276 | ||
277 | mfc_debug_leave(); | |
278 | ||
279 | return 0; | |
280 | } | |
281 | ||
282 | /* Release instance buffer */ | |
283 | void s5p_mfc_release_instance_buffer_v6(struct s5p_mfc_ctx *ctx) | |
284 | { | |
285 | mfc_debug_enter(); | |
286 | ||
287 | if (ctx->ctx.alloc) { | |
288 | vb2_dma_contig_memops.put(ctx->ctx.alloc); | |
289 | ctx->ctx.alloc = NULL; | |
290 | ctx->ctx.dma = 0; | |
291 | ctx->ctx.virt = NULL; | |
292 | } | |
293 | ||
294 | mfc_debug_leave(); | |
295 | } | |
296 | ||
297 | /* Allocate context buffers for SYS_INIT */ | |
298 | int s5p_mfc_alloc_dev_context_buffer_v6(struct s5p_mfc_dev *dev) | |
299 | { | |
300 | struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv; | |
301 | ||
302 | mfc_debug_enter(); | |
303 | ||
304 | dev->ctx_buf.alloc = vb2_dma_contig_memops.alloc( | |
305 | dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], buf_size->dev_ctx); | |
306 | if (IS_ERR(dev->ctx_buf.alloc)) { | |
307 | mfc_err("Allocating DESC buffer failed.\n"); | |
308 | return PTR_ERR(dev->ctx_buf.alloc); | |
309 | } | |
310 | ||
311 | dev->ctx_buf.dma = s5p_mfc_mem_cookie( | |
312 | dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], | |
313 | dev->ctx_buf.alloc); | |
314 | ||
315 | dev->ctx_buf.virt = vb2_dma_contig_memops.vaddr(dev->ctx_buf.alloc); | |
316 | if (!dev->ctx_buf.virt) { | |
317 | vb2_dma_contig_memops.put(dev->ctx_buf.alloc); | |
318 | dev->ctx_buf.alloc = NULL; | |
319 | dev->ctx_buf.dma = 0; | |
320 | ||
321 | mfc_err("Remapping DESC buffer failed.\n"); | |
322 | return -ENOMEM; | |
323 | } | |
324 | ||
325 | memset(dev->ctx_buf.virt, 0, buf_size->dev_ctx); | |
326 | wmb(); | |
327 | ||
328 | mfc_debug_leave(); | |
329 | ||
330 | return 0; | |
331 | } | |
332 | ||
333 | /* Release context buffers for SYS_INIT */ | |
334 | void s5p_mfc_release_dev_context_buffer_v6(struct s5p_mfc_dev *dev) | |
335 | { | |
336 | if (dev->ctx_buf.alloc) { | |
337 | vb2_dma_contig_memops.put(dev->ctx_buf.alloc); | |
338 | dev->ctx_buf.alloc = NULL; | |
339 | dev->ctx_buf.dma = 0; | |
340 | dev->ctx_buf.virt = NULL; | |
341 | } | |
342 | } | |
343 | ||
344 | static int calc_plane(int width, int height) | |
345 | { | |
346 | int mbX, mbY; | |
347 | ||
348 | mbX = DIV_ROUND_UP(width, S5P_FIMV_NUM_PIXELS_IN_MB_ROW_V6); | |
349 | mbY = DIV_ROUND_UP(height, S5P_FIMV_NUM_PIXELS_IN_MB_COL_V6); | |
350 | ||
351 | if (width * height < S5P_FIMV_MAX_FRAME_SIZE_V6) | |
352 | mbY = (mbY + 1) / 2 * 2; | |
353 | ||
354 | return (mbX * S5P_FIMV_NUM_PIXELS_IN_MB_COL_V6) * | |
355 | (mbY * S5P_FIMV_NUM_PIXELS_IN_MB_ROW_V6); | |
356 | } | |
357 | ||
358 | void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx) | |
359 | { | |
360 | ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN_V6); | |
361 | ctx->buf_height = ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN_V6); | |
362 | mfc_debug(2, "SEQ Done: Movie dimensions %dx%d,\n" | |
363 | "buffer dimensions: %dx%d\n", ctx->img_width, | |
364 | ctx->img_height, ctx->buf_width, ctx->buf_height); | |
365 | ||
366 | ctx->luma_size = calc_plane(ctx->img_width, ctx->img_height); | |
367 | ctx->chroma_size = calc_plane(ctx->img_width, (ctx->img_height >> 1)); | |
368 | if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || | |
369 | ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) { | |
370 | ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V6(ctx->img_width, | |
371 | ctx->img_height); | |
372 | ctx->mv_size = ALIGN(ctx->mv_size, 16); | |
373 | } else { | |
374 | ctx->mv_size = 0; | |
375 | } | |
376 | } | |
377 | ||
378 | void s5p_mfc_enc_calc_src_size_v6(struct s5p_mfc_ctx *ctx) | |
379 | { | |
380 | unsigned int mb_width, mb_height; | |
381 | ||
382 | mb_width = MB_WIDTH(ctx->img_width); | |
383 | mb_height = MB_HEIGHT(ctx->img_height); | |
384 | ||
385 | ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN_V6); | |
386 | ctx->luma_size = ALIGN((mb_width * mb_height) * 256, 256); | |
387 | ctx->chroma_size = ALIGN((mb_width * mb_height) * 128, 256); | |
388 | } | |
389 | ||
390 | /* Set registers for decoding stream buffer */ | |
391 | int s5p_mfc_set_dec_stream_buffer_v6(struct s5p_mfc_ctx *ctx, int buf_addr, | |
392 | unsigned int start_num_byte, unsigned int strm_size) | |
393 | { | |
394 | struct s5p_mfc_dev *dev = ctx->dev; | |
395 | struct s5p_mfc_buf_size *buf_size = dev->variant->buf_size; | |
396 | ||
397 | mfc_debug_enter(); | |
398 | mfc_debug(2, "inst_no: %d, buf_addr: 0x%08x,\n" | |
399 | "buf_size: 0x%08x (%d)\n", | |
400 | ctx->inst_no, buf_addr, strm_size, strm_size); | |
401 | WRITEL(strm_size, S5P_FIMV_D_STREAM_DATA_SIZE_V6); | |
402 | WRITEL(buf_addr, S5P_FIMV_D_CPB_BUFFER_ADDR_V6); | |
403 | WRITEL(buf_size->cpb, S5P_FIMV_D_CPB_BUFFER_SIZE_V6); | |
404 | WRITEL(start_num_byte, S5P_FIMV_D_CPB_BUFFER_OFFSET_V6); | |
405 | ||
406 | mfc_debug_leave(); | |
407 | return 0; | |
408 | } | |
409 | ||
410 | /* Set decoding frame buffer */ | |
411 | int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx) | |
412 | { | |
413 | unsigned int frame_size, i; | |
414 | unsigned int frame_size_ch, frame_size_mv; | |
415 | struct s5p_mfc_dev *dev = ctx->dev; | |
416 | size_t buf_addr1; | |
417 | int buf_size1; | |
418 | int align_gap; | |
419 | ||
420 | buf_addr1 = ctx->bank1_phys; | |
421 | buf_size1 = ctx->bank1_size; | |
422 | ||
423 | mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1); | |
424 | mfc_debug(2, "Total DPB COUNT: %d\n", ctx->total_dpb_count); | |
425 | mfc_debug(2, "Setting display delay to %d\n", ctx->display_delay); | |
426 | ||
427 | WRITEL(ctx->total_dpb_count, S5P_FIMV_D_NUM_DPB_V6); | |
428 | WRITEL(ctx->luma_size, S5P_FIMV_D_LUMA_DPB_SIZE_V6); | |
429 | WRITEL(ctx->chroma_size, S5P_FIMV_D_CHROMA_DPB_SIZE_V6); | |
430 | ||
431 | WRITEL(buf_addr1, S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V6); | |
432 | WRITEL(ctx->scratch_buf_size, S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V6); | |
433 | buf_addr1 += ctx->scratch_buf_size; | |
434 | buf_size1 -= ctx->scratch_buf_size; | |
435 | ||
436 | if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC || | |
437 | ctx->codec_mode == S5P_FIMV_CODEC_H264_MVC_DEC){ | |
438 | WRITEL(ctx->mv_size, S5P_FIMV_D_MV_BUFFER_SIZE_V6); | |
439 | WRITEL(ctx->mv_count, S5P_FIMV_D_NUM_MV_V6); | |
440 | } | |
441 | ||
442 | frame_size = ctx->luma_size; | |
443 | frame_size_ch = ctx->chroma_size; | |
444 | frame_size_mv = ctx->mv_size; | |
445 | mfc_debug(2, "Frame size: %d ch: %d mv: %d\n", | |
446 | frame_size, frame_size_ch, frame_size_mv); | |
447 | ||
448 | for (i = 0; i < ctx->total_dpb_count; i++) { | |
449 | /* Bank2 */ | |
450 | mfc_debug(2, "Luma %d: %x\n", i, | |
451 | ctx->dst_bufs[i].cookie.raw.luma); | |
452 | WRITEL(ctx->dst_bufs[i].cookie.raw.luma, | |
453 | S5P_FIMV_D_LUMA_DPB_V6 + i * 4); | |
454 | mfc_debug(2, "\tChroma %d: %x\n", i, | |
455 | ctx->dst_bufs[i].cookie.raw.chroma); | |
456 | WRITEL(ctx->dst_bufs[i].cookie.raw.chroma, | |
457 | S5P_FIMV_D_CHROMA_DPB_V6 + i * 4); | |
458 | } | |
459 | if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || | |
460 | ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) { | |
461 | for (i = 0; i < ctx->mv_count; i++) { | |
462 | /* To test alignment */ | |
463 | align_gap = buf_addr1; | |
464 | buf_addr1 = ALIGN(buf_addr1, 16); | |
465 | align_gap = buf_addr1 - align_gap; | |
466 | buf_size1 -= align_gap; | |
467 | ||
468 | mfc_debug(2, "\tBuf1: %x, size: %d\n", | |
469 | buf_addr1, buf_size1); | |
470 | WRITEL(buf_addr1, S5P_FIMV_D_MV_BUFFER_V6 + i * 4); | |
471 | buf_addr1 += frame_size_mv; | |
472 | buf_size1 -= frame_size_mv; | |
473 | } | |
474 | } | |
475 | ||
476 | mfc_debug(2, "Buf1: %u, buf_size1: %d (frames %d)\n", | |
477 | buf_addr1, buf_size1, ctx->total_dpb_count); | |
478 | if (buf_size1 < 0) { | |
479 | mfc_debug(2, "Not enough memory has been allocated.\n"); | |
480 | return -ENOMEM; | |
481 | } | |
482 | ||
483 | WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6); | |
484 | s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, | |
485 | S5P_FIMV_CH_INIT_BUFS_V6, NULL); | |
486 | ||
487 | mfc_debug(2, "After setting buffers.\n"); | |
488 | return 0; | |
489 | } | |
490 | ||
491 | /* Set registers for encoding stream buffer */ | |
492 | int s5p_mfc_set_enc_stream_buffer_v6(struct s5p_mfc_ctx *ctx, | |
493 | unsigned long addr, unsigned int size) | |
494 | { | |
495 | struct s5p_mfc_dev *dev = ctx->dev; | |
496 | ||
497 | WRITEL(addr, S5P_FIMV_E_STREAM_BUFFER_ADDR_V6); /* 16B align */ | |
498 | WRITEL(size, S5P_FIMV_E_STREAM_BUFFER_SIZE_V6); | |
499 | ||
500 | mfc_debug(2, "stream buf addr: 0x%08lx, size: 0x%d", | |
501 | addr, size); | |
502 | ||
503 | return 0; | |
504 | } | |
505 | ||
506 | void s5p_mfc_set_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx, | |
507 | unsigned long y_addr, unsigned long c_addr) | |
508 | { | |
509 | struct s5p_mfc_dev *dev = ctx->dev; | |
510 | ||
511 | WRITEL(y_addr, S5P_FIMV_E_SOURCE_LUMA_ADDR_V6); /* 256B align */ | |
512 | WRITEL(c_addr, S5P_FIMV_E_SOURCE_CHROMA_ADDR_V6); | |
513 | ||
514 | mfc_debug(2, "enc src y buf addr: 0x%08lx", y_addr); | |
515 | mfc_debug(2, "enc src c buf addr: 0x%08lx", c_addr); | |
516 | } | |
517 | ||
518 | void s5p_mfc_get_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx, | |
519 | unsigned long *y_addr, unsigned long *c_addr) | |
520 | { | |
521 | struct s5p_mfc_dev *dev = ctx->dev; | |
522 | unsigned long enc_recon_y_addr, enc_recon_c_addr; | |
523 | ||
524 | *y_addr = READL(S5P_FIMV_E_ENCODED_SOURCE_LUMA_ADDR_V6); | |
525 | *c_addr = READL(S5P_FIMV_E_ENCODED_SOURCE_CHROMA_ADDR_V6); | |
526 | ||
527 | enc_recon_y_addr = READL(S5P_FIMV_E_RECON_LUMA_DPB_ADDR_V6); | |
528 | enc_recon_c_addr = READL(S5P_FIMV_E_RECON_CHROMA_DPB_ADDR_V6); | |
529 | ||
530 | mfc_debug(2, "recon y addr: 0x%08lx", enc_recon_y_addr); | |
531 | mfc_debug(2, "recon c addr: 0x%08lx", enc_recon_c_addr); | |
532 | } | |
533 | ||
534 | /* Set encoding ref & codec buffer */ | |
535 | int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx) | |
536 | { | |
537 | struct s5p_mfc_dev *dev = ctx->dev; | |
538 | size_t buf_addr1, buf_size1; | |
539 | int i; | |
540 | ||
541 | mfc_debug_enter(); | |
542 | ||
543 | buf_addr1 = ctx->bank1_phys; | |
544 | buf_size1 = ctx->bank1_size; | |
545 | ||
546 | mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1); | |
547 | ||
548 | for (i = 0; i < ctx->dpb_count; i++) { | |
549 | WRITEL(buf_addr1, S5P_FIMV_E_LUMA_DPB_V6 + (4 * i)); | |
550 | buf_addr1 += ctx->luma_dpb_size; | |
551 | WRITEL(buf_addr1, S5P_FIMV_E_CHROMA_DPB_V6 + (4 * i)); | |
552 | buf_addr1 += ctx->chroma_dpb_size; | |
553 | WRITEL(buf_addr1, S5P_FIMV_E_ME_BUFFER_V6 + (4 * i)); | |
554 | buf_addr1 += ctx->me_buffer_size; | |
555 | buf_size1 -= (ctx->luma_dpb_size + ctx->chroma_dpb_size + | |
556 | ctx->me_buffer_size); | |
557 | } | |
558 | ||
559 | WRITEL(buf_addr1, S5P_FIMV_E_SCRATCH_BUFFER_ADDR_V6); | |
560 | WRITEL(ctx->scratch_buf_size, S5P_FIMV_E_SCRATCH_BUFFER_SIZE_V6); | |
561 | buf_addr1 += ctx->scratch_buf_size; | |
562 | buf_size1 -= ctx->scratch_buf_size; | |
563 | ||
564 | WRITEL(buf_addr1, S5P_FIMV_E_TMV_BUFFER0_V6); | |
565 | buf_addr1 += ctx->tmv_buffer_size >> 1; | |
566 | WRITEL(buf_addr1, S5P_FIMV_E_TMV_BUFFER1_V6); | |
567 | buf_addr1 += ctx->tmv_buffer_size >> 1; | |
568 | buf_size1 -= ctx->tmv_buffer_size; | |
569 | ||
570 | mfc_debug(2, "Buf1: %u, buf_size1: %d (ref frames %d)\n", | |
571 | buf_addr1, buf_size1, ctx->dpb_count); | |
572 | if (buf_size1 < 0) { | |
573 | mfc_debug(2, "Not enough memory has been allocated.\n"); | |
574 | return -ENOMEM; | |
575 | } | |
576 | ||
577 | WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6); | |
578 | s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, | |
579 | S5P_FIMV_CH_INIT_BUFS_V6, NULL); | |
580 | ||
581 | mfc_debug_leave(); | |
582 | ||
583 | return 0; | |
584 | } | |
585 | ||
586 | static int s5p_mfc_set_slice_mode(struct s5p_mfc_ctx *ctx) | |
587 | { | |
588 | struct s5p_mfc_dev *dev = ctx->dev; | |
589 | ||
590 | /* multi-slice control */ | |
591 | /* multi-slice MB number or bit size */ | |
592 | WRITEL(ctx->slice_mode, S5P_FIMV_E_MSLICE_MODE_V6); | |
593 | if (ctx->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) { | |
594 | WRITEL(ctx->slice_size.mb, S5P_FIMV_E_MSLICE_SIZE_MB_V6); | |
595 | } else if (ctx->slice_mode == | |
596 | V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) { | |
597 | WRITEL(ctx->slice_size.bits, S5P_FIMV_E_MSLICE_SIZE_BITS_V6); | |
598 | } else { | |
599 | WRITEL(0x0, S5P_FIMV_E_MSLICE_SIZE_MB_V6); | |
600 | WRITEL(0x0, S5P_FIMV_E_MSLICE_SIZE_BITS_V6); | |
601 | } | |
602 | ||
603 | return 0; | |
604 | } | |
605 | ||
606 | static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx) | |
607 | { | |
608 | struct s5p_mfc_dev *dev = ctx->dev; | |
609 | struct s5p_mfc_enc_params *p = &ctx->enc_params; | |
610 | unsigned int reg = 0; | |
611 | ||
612 | mfc_debug_enter(); | |
613 | ||
614 | /* width */ | |
615 | WRITEL(ctx->img_width, S5P_FIMV_E_FRAME_WIDTH_V6); /* 16 align */ | |
616 | /* height */ | |
617 | WRITEL(ctx->img_height, S5P_FIMV_E_FRAME_HEIGHT_V6); /* 16 align */ | |
618 | ||
619 | /* cropped width */ | |
620 | WRITEL(ctx->img_width, S5P_FIMV_E_CROPPED_FRAME_WIDTH_V6); | |
621 | /* cropped height */ | |
622 | WRITEL(ctx->img_height, S5P_FIMV_E_CROPPED_FRAME_HEIGHT_V6); | |
623 | /* cropped offset */ | |
624 | WRITEL(0x0, S5P_FIMV_E_FRAME_CROP_OFFSET_V6); | |
625 | ||
626 | /* pictype : IDR period */ | |
627 | reg = 0; | |
628 | reg |= p->gop_size & 0xFFFF; | |
629 | WRITEL(reg, S5P_FIMV_E_GOP_CONFIG_V6); | |
630 | ||
631 | /* multi-slice control */ | |
632 | /* multi-slice MB number or bit size */ | |
633 | ctx->slice_mode = p->slice_mode; | |
634 | reg = 0; | |
635 | if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) { | |
636 | reg |= (0x1 << 3); | |
637 | WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6); | |
638 | ctx->slice_size.mb = p->slice_mb; | |
639 | } else if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) { | |
640 | reg |= (0x1 << 3); | |
641 | WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6); | |
642 | ctx->slice_size.bits = p->slice_bit; | |
643 | } else { | |
644 | reg &= ~(0x1 << 3); | |
645 | WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6); | |
646 | } | |
647 | ||
648 | s5p_mfc_set_slice_mode(ctx); | |
649 | ||
650 | /* cyclic intra refresh */ | |
651 | WRITEL(p->intra_refresh_mb, S5P_FIMV_E_IR_SIZE_V6); | |
652 | reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6); | |
653 | if (p->intra_refresh_mb == 0) | |
654 | reg &= ~(0x1 << 4); | |
655 | else | |
656 | reg |= (0x1 << 4); | |
657 | WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6); | |
658 | ||
659 | /* 'NON_REFERENCE_STORE_ENABLE' for debugging */ | |
660 | reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6); | |
661 | reg &= ~(0x1 << 9); | |
662 | WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6); | |
663 | ||
664 | /* memory structure cur. frame */ | |
665 | if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) { | |
666 | /* 0: Linear, 1: 2D tiled*/ | |
667 | reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6); | |
668 | reg &= ~(0x1 << 7); | |
669 | WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6); | |
670 | /* 0: NV12(CbCr), 1: NV21(CrCb) */ | |
671 | WRITEL(0x0, S5P_FIMV_PIXEL_FORMAT_V6); | |
672 | } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV21M) { | |
673 | /* 0: Linear, 1: 2D tiled*/ | |
674 | reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6); | |
675 | reg &= ~(0x1 << 7); | |
676 | WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6); | |
677 | /* 0: NV12(CbCr), 1: NV21(CrCb) */ | |
678 | WRITEL(0x1, S5P_FIMV_PIXEL_FORMAT_V6); | |
679 | } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16) { | |
680 | /* 0: Linear, 1: 2D tiled*/ | |
681 | reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6); | |
682 | reg |= (0x1 << 7); | |
683 | WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6); | |
684 | /* 0: NV12(CbCr), 1: NV21(CrCb) */ | |
685 | WRITEL(0x0, S5P_FIMV_PIXEL_FORMAT_V6); | |
686 | } | |
687 | ||
688 | /* memory structure recon. frame */ | |
689 | /* 0: Linear, 1: 2D tiled */ | |
690 | reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6); | |
691 | reg |= (0x1 << 8); | |
692 | WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6); | |
693 | ||
694 | /* padding control & value */ | |
695 | WRITEL(0x0, S5P_FIMV_E_PADDING_CTRL_V6); | |
696 | if (p->pad) { | |
697 | reg = 0; | |
698 | /** enable */ | |
699 | reg |= (1 << 31); | |
700 | /** cr value */ | |
701 | reg |= ((p->pad_cr & 0xFF) << 16); | |
702 | /** cb value */ | |
703 | reg |= ((p->pad_cb & 0xFF) << 8); | |
704 | /** y value */ | |
705 | reg |= p->pad_luma & 0xFF; | |
706 | WRITEL(reg, S5P_FIMV_E_PADDING_CTRL_V6); | |
707 | } | |
708 | ||
709 | /* rate control config. */ | |
710 | reg = 0; | |
711 | /* frame-level rate control */ | |
712 | reg |= ((p->rc_frame & 0x1) << 9); | |
713 | WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6); | |
714 | ||
715 | /* bit rate */ | |
716 | if (p->rc_frame) | |
717 | WRITEL(p->rc_bitrate, | |
718 | S5P_FIMV_E_RC_BIT_RATE_V6); | |
719 | else | |
720 | WRITEL(1, S5P_FIMV_E_RC_BIT_RATE_V6); | |
721 | ||
722 | /* reaction coefficient */ | |
723 | if (p->rc_frame) { | |
724 | if (p->rc_reaction_coeff < TIGHT_CBR_MAX) /* tight CBR */ | |
725 | WRITEL(1, S5P_FIMV_E_RC_RPARAM_V6); | |
726 | else /* loose CBR */ | |
727 | WRITEL(2, S5P_FIMV_E_RC_RPARAM_V6); | |
728 | } | |
729 | ||
730 | /* seq header ctrl */ | |
731 | reg = READL(S5P_FIMV_E_ENC_OPTIONS_V6); | |
732 | reg &= ~(0x1 << 2); | |
733 | reg |= ((p->seq_hdr_mode & 0x1) << 2); | |
734 | ||
735 | /* frame skip mode */ | |
736 | reg &= ~(0x3); | |
737 | reg |= (p->frame_skip_mode & 0x3); | |
738 | WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS_V6); | |
739 | ||
740 | /* 'DROP_CONTROL_ENABLE', disable */ | |
741 | reg = READL(S5P_FIMV_E_RC_CONFIG_V6); | |
742 | reg &= ~(0x1 << 10); | |
743 | WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6); | |
744 | ||
745 | /* setting for MV range [16, 256] */ | |
746 | reg = 0; | |
747 | reg &= ~(0x3FFF); | |
748 | reg = 256; | |
749 | WRITEL(reg, S5P_FIMV_E_MV_HOR_RANGE_V6); | |
750 | ||
751 | reg = 0; | |
752 | reg &= ~(0x3FFF); | |
753 | reg = 256; | |
754 | WRITEL(reg, S5P_FIMV_E_MV_VER_RANGE_V6); | |
755 | ||
756 | WRITEL(0x0, S5P_FIMV_E_FRAME_INSERTION_V6); | |
757 | WRITEL(0x0, S5P_FIMV_E_ROI_BUFFER_ADDR_V6); | |
758 | WRITEL(0x0, S5P_FIMV_E_PARAM_CHANGE_V6); | |
759 | WRITEL(0x0, S5P_FIMV_E_RC_ROI_CTRL_V6); | |
760 | WRITEL(0x0, S5P_FIMV_E_PICTURE_TAG_V6); | |
761 | ||
762 | WRITEL(0x0, S5P_FIMV_E_BIT_COUNT_ENABLE_V6); | |
763 | WRITEL(0x0, S5P_FIMV_E_MAX_BIT_COUNT_V6); | |
764 | WRITEL(0x0, S5P_FIMV_E_MIN_BIT_COUNT_V6); | |
765 | ||
766 | WRITEL(0x0, S5P_FIMV_E_METADATA_BUFFER_ADDR_V6); | |
767 | WRITEL(0x0, S5P_FIMV_E_METADATA_BUFFER_SIZE_V6); | |
768 | ||
769 | mfc_debug_leave(); | |
770 | ||
771 | return 0; | |
772 | } | |
773 | ||
774 | static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx) | |
775 | { | |
776 | struct s5p_mfc_dev *dev = ctx->dev; | |
777 | struct s5p_mfc_enc_params *p = &ctx->enc_params; | |
778 | struct s5p_mfc_h264_enc_params *p_h264 = &p->codec.h264; | |
779 | unsigned int reg = 0; | |
780 | int i; | |
781 | ||
782 | mfc_debug_enter(); | |
783 | ||
784 | s5p_mfc_set_enc_params(ctx); | |
785 | ||
786 | /* pictype : number of B */ | |
787 | reg = READL(S5P_FIMV_E_GOP_CONFIG_V6); | |
788 | reg &= ~(0x3 << 16); | |
789 | reg |= ((p->num_b_frame & 0x3) << 16); | |
790 | WRITEL(reg, S5P_FIMV_E_GOP_CONFIG_V6); | |
791 | ||
792 | /* profile & level */ | |
793 | reg = 0; | |
794 | /** level */ | |
795 | reg |= ((p_h264->level & 0xFF) << 8); | |
796 | /** profile - 0 ~ 3 */ | |
797 | reg |= p_h264->profile & 0x3F; | |
798 | WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE_V6); | |
799 | ||
800 | /* rate control config. */ | |
801 | reg = READL(S5P_FIMV_E_RC_CONFIG_V6); | |
802 | /** macroblock level rate control */ | |
803 | reg &= ~(0x1 << 8); | |
804 | reg |= ((p->rc_mb & 0x1) << 8); | |
805 | WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6); | |
806 | /** frame QP */ | |
807 | reg &= ~(0x3F); | |
808 | reg |= p_h264->rc_frame_qp & 0x3F; | |
809 | WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6); | |
810 | ||
811 | /* max & min value of QP */ | |
812 | reg = 0; | |
813 | /** max QP */ | |
814 | reg |= ((p_h264->rc_max_qp & 0x3F) << 8); | |
815 | /** min QP */ | |
816 | reg |= p_h264->rc_min_qp & 0x3F; | |
817 | WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND_V6); | |
818 | ||
819 | /* other QPs */ | |
820 | WRITEL(0x0, S5P_FIMV_E_FIXED_PICTURE_QP_V6); | |
821 | if (!p->rc_frame && !p->rc_mb) { | |
822 | reg = 0; | |
823 | reg |= ((p_h264->rc_b_frame_qp & 0x3F) << 16); | |
824 | reg |= ((p_h264->rc_p_frame_qp & 0x3F) << 8); | |
825 | reg |= p_h264->rc_frame_qp & 0x3F; | |
826 | WRITEL(reg, S5P_FIMV_E_FIXED_PICTURE_QP_V6); | |
827 | } | |
828 | ||
829 | /* frame rate */ | |
830 | if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) { | |
831 | reg = 0; | |
832 | reg |= ((p->rc_framerate_num & 0xFFFF) << 16); | |
833 | reg |= p->rc_framerate_denom & 0xFFFF; | |
834 | WRITEL(reg, S5P_FIMV_E_RC_FRAME_RATE_V6); | |
835 | } | |
836 | ||
837 | /* vbv buffer size */ | |
838 | if (p->frame_skip_mode == | |
839 | V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { | |
840 | WRITEL(p_h264->cpb_size & 0xFFFF, | |
841 | S5P_FIMV_E_VBV_BUFFER_SIZE_V6); | |
842 | ||
843 | if (p->rc_frame) | |
844 | WRITEL(p->vbv_delay, S5P_FIMV_E_VBV_INIT_DELAY_V6); | |
845 | } | |
846 | ||
847 | /* interlace */ | |
848 | reg = 0; | |
849 | reg |= ((p_h264->interlace & 0x1) << 3); | |
850 | WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6); | |
851 | ||
852 | /* height */ | |
853 | if (p_h264->interlace) { | |
854 | WRITEL(ctx->img_height >> 1, | |
855 | S5P_FIMV_E_FRAME_HEIGHT_V6); /* 32 align */ | |
856 | /* cropped height */ | |
857 | WRITEL(ctx->img_height >> 1, | |
858 | S5P_FIMV_E_CROPPED_FRAME_HEIGHT_V6); | |
859 | } | |
860 | ||
861 | /* loop filter ctrl */ | |
862 | reg = READL(S5P_FIMV_E_H264_OPTIONS_V6); | |
863 | reg &= ~(0x3 << 1); | |
864 | reg |= ((p_h264->loop_filter_mode & 0x3) << 1); | |
865 | WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6); | |
866 | ||
867 | /* loopfilter alpha offset */ | |
868 | if (p_h264->loop_filter_alpha < 0) { | |
869 | reg = 0x10; | |
870 | reg |= (0xFF - p_h264->loop_filter_alpha) + 1; | |
871 | } else { | |
872 | reg = 0x00; | |
873 | reg |= (p_h264->loop_filter_alpha & 0xF); | |
874 | } | |
875 | WRITEL(reg, S5P_FIMV_E_H264_LF_ALPHA_OFFSET_V6); | |
876 | ||
877 | /* loopfilter beta offset */ | |
878 | if (p_h264->loop_filter_beta < 0) { | |
879 | reg = 0x10; | |
880 | reg |= (0xFF - p_h264->loop_filter_beta) + 1; | |
881 | } else { | |
882 | reg = 0x00; | |
883 | reg |= (p_h264->loop_filter_beta & 0xF); | |
884 | } | |
885 | WRITEL(reg, S5P_FIMV_E_H264_LF_BETA_OFFSET_V6); | |
886 | ||
887 | /* entropy coding mode */ | |
888 | reg = READL(S5P_FIMV_E_H264_OPTIONS_V6); | |
889 | reg &= ~(0x1); | |
890 | reg |= p_h264->entropy_mode & 0x1; | |
891 | WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6); | |
892 | ||
893 | /* number of ref. picture */ | |
894 | reg = READL(S5P_FIMV_E_H264_OPTIONS_V6); | |
895 | reg &= ~(0x1 << 7); | |
896 | reg |= (((p_h264->num_ref_pic_4p - 1) & 0x1) << 7); | |
897 | WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6); | |
898 | ||
899 | /* 8x8 transform enable */ | |
900 | reg = READL(S5P_FIMV_E_H264_OPTIONS_V6); | |
901 | reg &= ~(0x3 << 12); | |
902 | reg |= ((p_h264->_8x8_transform & 0x3) << 12); | |
903 | WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6); | |
904 | ||
905 | /* macroblock adaptive scaling features */ | |
906 | WRITEL(0x0, S5P_FIMV_E_MB_RC_CONFIG_V6); | |
907 | if (p->rc_mb) { | |
908 | reg = 0; | |
909 | /** dark region */ | |
910 | reg |= ((p_h264->rc_mb_dark & 0x1) << 3); | |
911 | /** smooth region */ | |
912 | reg |= ((p_h264->rc_mb_smooth & 0x1) << 2); | |
913 | /** static region */ | |
914 | reg |= ((p_h264->rc_mb_static & 0x1) << 1); | |
915 | /** high activity region */ | |
916 | reg |= p_h264->rc_mb_activity & 0x1; | |
917 | WRITEL(reg, S5P_FIMV_E_MB_RC_CONFIG_V6); | |
918 | } | |
919 | ||
920 | /* aspect ratio VUI */ | |
921 | reg = READL(S5P_FIMV_E_H264_OPTIONS_V6); | |
922 | reg &= ~(0x1 << 5); | |
923 | reg |= ((p_h264->vui_sar & 0x1) << 5); | |
924 | WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6); | |
925 | ||
926 | WRITEL(0x0, S5P_FIMV_E_ASPECT_RATIO_V6); | |
927 | WRITEL(0x0, S5P_FIMV_E_EXTENDED_SAR_V6); | |
928 | if (p_h264->vui_sar) { | |
929 | /* aspect ration IDC */ | |
930 | reg = 0; | |
931 | reg |= p_h264->vui_sar_idc & 0xFF; | |
932 | WRITEL(reg, S5P_FIMV_E_ASPECT_RATIO_V6); | |
933 | if (p_h264->vui_sar_idc == 0xFF) { | |
934 | /* extended SAR */ | |
935 | reg = 0; | |
936 | reg |= (p_h264->vui_ext_sar_width & 0xFFFF) << 16; | |
937 | reg |= p_h264->vui_ext_sar_height & 0xFFFF; | |
938 | WRITEL(reg, S5P_FIMV_E_EXTENDED_SAR_V6); | |
939 | } | |
940 | } | |
941 | ||
942 | /* intra picture period for H.264 open GOP */ | |
943 | /* control */ | |
944 | reg = READL(S5P_FIMV_E_H264_OPTIONS_V6); | |
945 | reg &= ~(0x1 << 4); | |
946 | reg |= ((p_h264->open_gop & 0x1) << 4); | |
947 | WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6); | |
948 | /* value */ | |
949 | WRITEL(0x0, S5P_FIMV_E_H264_I_PERIOD_V6); | |
950 | if (p_h264->open_gop) { | |
951 | reg = 0; | |
952 | reg |= p_h264->open_gop_size & 0xFFFF; | |
953 | WRITEL(reg, S5P_FIMV_E_H264_I_PERIOD_V6); | |
954 | } | |
955 | ||
956 | /* 'WEIGHTED_BI_PREDICTION' for B is disable */ | |
957 | reg = READL(S5P_FIMV_E_H264_OPTIONS_V6); | |
958 | reg &= ~(0x3 << 9); | |
959 | WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6); | |
960 | ||
961 | /* 'CONSTRAINED_INTRA_PRED_ENABLE' is disable */ | |
962 | reg = READL(S5P_FIMV_E_H264_OPTIONS_V6); | |
963 | reg &= ~(0x1 << 14); | |
964 | WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6); | |
965 | ||
966 | /* ASO */ | |
967 | reg = READL(S5P_FIMV_E_H264_OPTIONS_V6); | |
968 | reg &= ~(0x1 << 6); | |
969 | reg |= ((p_h264->aso & 0x1) << 6); | |
970 | WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6); | |
971 | ||
972 | /* hier qp enable */ | |
973 | reg = READL(S5P_FIMV_E_H264_OPTIONS_V6); | |
974 | reg &= ~(0x1 << 8); | |
975 | reg |= ((p_h264->open_gop & 0x1) << 8); | |
976 | WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6); | |
977 | reg = 0; | |
978 | if (p_h264->hier_qp && p_h264->hier_qp_layer) { | |
979 | reg |= (p_h264->hier_qp_type & 0x1) << 0x3; | |
980 | reg |= p_h264->hier_qp_layer & 0x7; | |
981 | WRITEL(reg, S5P_FIMV_E_H264_NUM_T_LAYER_V6); | |
982 | /* QP value for each layer */ | |
983 | for (i = 0; i < (p_h264->hier_qp_layer & 0x7); i++) | |
984 | WRITEL(p_h264->hier_qp_layer_qp[i], | |
985 | S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER0_V6 + | |
986 | i * 4); | |
987 | } | |
988 | /* number of coding layer should be zero when hierarchical is disable */ | |
989 | WRITEL(reg, S5P_FIMV_E_H264_NUM_T_LAYER_V6); | |
990 | ||
991 | /* frame packing SEI generation */ | |
992 | reg = READL(S5P_FIMV_E_H264_OPTIONS_V6); | |
993 | reg &= ~(0x1 << 25); | |
994 | reg |= ((p_h264->sei_frame_packing & 0x1) << 25); | |
995 | WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_V6); | |
996 | if (p_h264->sei_frame_packing) { | |
997 | reg = 0; | |
998 | /** current frame0 flag */ | |
999 | reg |= ((p_h264->sei_fp_curr_frame_0 & 0x1) << 2); | |
1000 | /** arrangement type */ | |
1001 | reg |= p_h264->sei_fp_arrangement_type & 0x3; | |
1002 | WRITEL(reg, S5P_FIMV_E_H264_FRAME_PACKING_SEI_INFO_V6); | |
1003 | } | |
1004 | ||
1005 | if (p_h264->fmo) { | |
1006 | switch (p_h264->fmo_map_type) { | |
1007 | case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES: | |
1008 | if (p_h264->fmo_slice_grp > 4) | |
1009 | p_h264->fmo_slice_grp = 4; | |
1010 | for (i = 0; i < (p_h264->fmo_slice_grp & 0xF); i++) | |
1011 | WRITEL(p_h264->fmo_run_len[i] - 1, | |
1012 | S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_0_V6 + | |
1013 | i * 4); | |
1014 | break; | |
1015 | case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES: | |
1016 | if (p_h264->fmo_slice_grp > 4) | |
1017 | p_h264->fmo_slice_grp = 4; | |
1018 | break; | |
1019 | case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_RASTER_SCAN: | |
1020 | case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN: | |
1021 | if (p_h264->fmo_slice_grp > 2) | |
1022 | p_h264->fmo_slice_grp = 2; | |
1023 | WRITEL(p_h264->fmo_chg_dir & 0x1, | |
1024 | S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_DIR_V6); | |
1025 | /* the valid range is 0 ~ number of macroblocks -1 */ | |
1026 | WRITEL(p_h264->fmo_chg_rate, | |
1027 | S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_RATE_MINUS1_V6); | |
1028 | break; | |
1029 | default: | |
1030 | mfc_err("Unsupported map type for FMO: %d\n", | |
1031 | p_h264->fmo_map_type); | |
1032 | p_h264->fmo_map_type = 0; | |
1033 | p_h264->fmo_slice_grp = 1; | |
1034 | break; | |
1035 | } | |
1036 | ||
1037 | WRITEL(p_h264->fmo_map_type, | |
1038 | S5P_FIMV_E_H264_FMO_SLICE_GRP_MAP_TYPE_V6); | |
1039 | WRITEL(p_h264->fmo_slice_grp - 1, | |
1040 | S5P_FIMV_E_H264_FMO_NUM_SLICE_GRP_MINUS1_V6); | |
1041 | } else { | |
1042 | WRITEL(0, S5P_FIMV_E_H264_FMO_NUM_SLICE_GRP_MINUS1_V6); | |
1043 | } | |
1044 | ||
1045 | mfc_debug_leave(); | |
1046 | ||
1047 | return 0; | |
1048 | } | |
1049 | ||
1050 | static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx) | |
1051 | { | |
1052 | struct s5p_mfc_dev *dev = ctx->dev; | |
1053 | struct s5p_mfc_enc_params *p = &ctx->enc_params; | |
1054 | struct s5p_mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4; | |
1055 | unsigned int reg = 0; | |
1056 | ||
1057 | mfc_debug_enter(); | |
1058 | ||
1059 | s5p_mfc_set_enc_params(ctx); | |
1060 | ||
1061 | /* pictype : number of B */ | |
1062 | reg = READL(S5P_FIMV_E_GOP_CONFIG_V6); | |
1063 | reg &= ~(0x3 << 16); | |
1064 | reg |= ((p->num_b_frame & 0x3) << 16); | |
1065 | WRITEL(reg, S5P_FIMV_E_GOP_CONFIG_V6); | |
1066 | ||
1067 | /* profile & level */ | |
1068 | reg = 0; | |
1069 | /** level */ | |
1070 | reg |= ((p_mpeg4->level & 0xFF) << 8); | |
1071 | /** profile - 0 ~ 1 */ | |
1072 | reg |= p_mpeg4->profile & 0x3F; | |
1073 | WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE_V6); | |
1074 | ||
1075 | /* rate control config. */ | |
1076 | reg = READL(S5P_FIMV_E_RC_CONFIG_V6); | |
1077 | /** macroblock level rate control */ | |
1078 | reg &= ~(0x1 << 8); | |
1079 | reg |= ((p->rc_mb & 0x1) << 8); | |
1080 | WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6); | |
1081 | /** frame QP */ | |
1082 | reg &= ~(0x3F); | |
1083 | reg |= p_mpeg4->rc_frame_qp & 0x3F; | |
1084 | WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6); | |
1085 | ||
1086 | /* max & min value of QP */ | |
1087 | reg = 0; | |
1088 | /** max QP */ | |
1089 | reg |= ((p_mpeg4->rc_max_qp & 0x3F) << 8); | |
1090 | /** min QP */ | |
1091 | reg |= p_mpeg4->rc_min_qp & 0x3F; | |
1092 | WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND_V6); | |
1093 | ||
1094 | /* other QPs */ | |
1095 | WRITEL(0x0, S5P_FIMV_E_FIXED_PICTURE_QP_V6); | |
1096 | if (!p->rc_frame && !p->rc_mb) { | |
1097 | reg = 0; | |
1098 | reg |= ((p_mpeg4->rc_b_frame_qp & 0x3F) << 16); | |
1099 | reg |= ((p_mpeg4->rc_p_frame_qp & 0x3F) << 8); | |
1100 | reg |= p_mpeg4->rc_frame_qp & 0x3F; | |
1101 | WRITEL(reg, S5P_FIMV_E_FIXED_PICTURE_QP_V6); | |
1102 | } | |
1103 | ||
1104 | /* frame rate */ | |
1105 | if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) { | |
1106 | reg = 0; | |
1107 | reg |= ((p->rc_framerate_num & 0xFFFF) << 16); | |
1108 | reg |= p->rc_framerate_denom & 0xFFFF; | |
1109 | WRITEL(reg, S5P_FIMV_E_RC_FRAME_RATE_V6); | |
1110 | } | |
1111 | ||
1112 | /* vbv buffer size */ | |
1113 | if (p->frame_skip_mode == | |
1114 | V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { | |
1115 | WRITEL(p->vbv_size & 0xFFFF, S5P_FIMV_E_VBV_BUFFER_SIZE_V6); | |
1116 | ||
1117 | if (p->rc_frame) | |
1118 | WRITEL(p->vbv_delay, S5P_FIMV_E_VBV_INIT_DELAY_V6); | |
1119 | } | |
1120 | ||
1121 | /* Disable HEC */ | |
1122 | WRITEL(0x0, S5P_FIMV_E_MPEG4_OPTIONS_V6); | |
1123 | WRITEL(0x0, S5P_FIMV_E_MPEG4_HEC_PERIOD_V6); | |
1124 | ||
1125 | mfc_debug_leave(); | |
1126 | ||
1127 | return 0; | |
1128 | } | |
1129 | ||
1130 | static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx) | |
1131 | { | |
1132 | struct s5p_mfc_dev *dev = ctx->dev; | |
1133 | struct s5p_mfc_enc_params *p = &ctx->enc_params; | |
1134 | struct s5p_mfc_mpeg4_enc_params *p_h263 = &p->codec.mpeg4; | |
1135 | unsigned int reg = 0; | |
1136 | ||
1137 | mfc_debug_enter(); | |
1138 | ||
1139 | s5p_mfc_set_enc_params(ctx); | |
1140 | ||
1141 | /* profile & level */ | |
1142 | reg = 0; | |
1143 | /** profile */ | |
1144 | reg |= (0x1 << 4); | |
1145 | WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE_V6); | |
1146 | ||
1147 | /* rate control config. */ | |
1148 | reg = READL(S5P_FIMV_E_RC_CONFIG_V6); | |
1149 | /** macroblock level rate control */ | |
1150 | reg &= ~(0x1 << 8); | |
1151 | reg |= ((p->rc_mb & 0x1) << 8); | |
1152 | WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6); | |
1153 | /** frame QP */ | |
1154 | reg &= ~(0x3F); | |
1155 | reg |= p_h263->rc_frame_qp & 0x3F; | |
1156 | WRITEL(reg, S5P_FIMV_E_RC_CONFIG_V6); | |
1157 | ||
1158 | /* max & min value of QP */ | |
1159 | reg = 0; | |
1160 | /** max QP */ | |
1161 | reg |= ((p_h263->rc_max_qp & 0x3F) << 8); | |
1162 | /** min QP */ | |
1163 | reg |= p_h263->rc_min_qp & 0x3F; | |
1164 | WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND_V6); | |
1165 | ||
1166 | /* other QPs */ | |
1167 | WRITEL(0x0, S5P_FIMV_E_FIXED_PICTURE_QP_V6); | |
1168 | if (!p->rc_frame && !p->rc_mb) { | |
1169 | reg = 0; | |
1170 | reg |= ((p_h263->rc_b_frame_qp & 0x3F) << 16); | |
1171 | reg |= ((p_h263->rc_p_frame_qp & 0x3F) << 8); | |
1172 | reg |= p_h263->rc_frame_qp & 0x3F; | |
1173 | WRITEL(reg, S5P_FIMV_E_FIXED_PICTURE_QP_V6); | |
1174 | } | |
1175 | ||
1176 | /* frame rate */ | |
1177 | if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) { | |
1178 | reg = 0; | |
1179 | reg |= ((p->rc_framerate_num & 0xFFFF) << 16); | |
1180 | reg |= p->rc_framerate_denom & 0xFFFF; | |
1181 | WRITEL(reg, S5P_FIMV_E_RC_FRAME_RATE_V6); | |
1182 | } | |
1183 | ||
1184 | /* vbv buffer size */ | |
1185 | if (p->frame_skip_mode == | |
1186 | V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { | |
1187 | WRITEL(p->vbv_size & 0xFFFF, S5P_FIMV_E_VBV_BUFFER_SIZE_V6); | |
1188 | ||
1189 | if (p->rc_frame) | |
1190 | WRITEL(p->vbv_delay, S5P_FIMV_E_VBV_INIT_DELAY_V6); | |
1191 | } | |
1192 | ||
1193 | mfc_debug_leave(); | |
1194 | ||
1195 | return 0; | |
1196 | } | |
1197 | ||
1198 | /* Initialize decoding */ | |
1199 | int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx) | |
1200 | { | |
1201 | struct s5p_mfc_dev *dev = ctx->dev; | |
1202 | unsigned int reg = 0; | |
1203 | int fmo_aso_ctrl = 0; | |
1204 | ||
1205 | mfc_debug_enter(); | |
1206 | mfc_debug(2, "InstNo: %d/%d\n", ctx->inst_no, | |
1207 | S5P_FIMV_CH_SEQ_HEADER_V6); | |
1208 | mfc_debug(2, "BUFs: %08x %08x %08x\n", | |
1209 | READL(S5P_FIMV_D_CPB_BUFFER_ADDR_V6), | |
1210 | READL(S5P_FIMV_D_CPB_BUFFER_ADDR_V6), | |
1211 | READL(S5P_FIMV_D_CPB_BUFFER_ADDR_V6)); | |
1212 | ||
1213 | /* FMO_ASO_CTRL - 0: Enable, 1: Disable */ | |
1214 | reg |= (fmo_aso_ctrl << S5P_FIMV_D_OPT_FMO_ASO_CTRL_MASK_V6); | |
1215 | ||
1216 | /* When user sets desplay_delay to 0, | |
1217 | * It works as "display_delay enable" and delay set to 0. | |
1218 | * If user wants display_delay disable, It should be | |
1219 | * set to negative value. */ | |
1220 | if (ctx->display_delay >= 0) { | |
1221 | reg |= (0x1 << S5P_FIMV_D_OPT_DDELAY_EN_SHIFT_V6); | |
1222 | WRITEL(ctx->display_delay, S5P_FIMV_D_DISPLAY_DELAY_V6); | |
1223 | } | |
1224 | /* Setup loop filter, for decoding this is only valid for MPEG4 */ | |
1225 | if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_DEC) { | |
1226 | mfc_debug(2, "Set loop filter to: %d\n", | |
1227 | ctx->loop_filter_mpeg4); | |
1228 | reg |= (ctx->loop_filter_mpeg4 << | |
1229 | S5P_FIMV_D_OPT_LF_CTRL_SHIFT_V6); | |
1230 | } | |
1231 | if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16) | |
1232 | reg |= (0x1 << S5P_FIMV_D_OPT_TILE_MODE_SHIFT_V6); | |
1233 | ||
1234 | WRITEL(reg, S5P_FIMV_D_DEC_OPTIONS_V6); | |
1235 | ||
1236 | /* 0: NV12(CbCr), 1: NV21(CrCb) */ | |
1237 | if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV21M) | |
1238 | WRITEL(0x1, S5P_FIMV_PIXEL_FORMAT_V6); | |
1239 | else | |
1240 | WRITEL(0x0, S5P_FIMV_PIXEL_FORMAT_V6); | |
1241 | ||
1242 | /* sei parse */ | |
1243 | WRITEL(ctx->sei_fp_parse & 0x1, S5P_FIMV_D_SEI_ENABLE_V6); | |
1244 | ||
1245 | WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6); | |
1246 | s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, | |
1247 | S5P_FIMV_CH_SEQ_HEADER_V6, NULL); | |
1248 | ||
1249 | mfc_debug_leave(); | |
1250 | return 0; | |
1251 | } | |
1252 | ||
1253 | static inline void s5p_mfc_set_flush(struct s5p_mfc_ctx *ctx, int flush) | |
1254 | { | |
1255 | struct s5p_mfc_dev *dev = ctx->dev; | |
8f23cc02 AK |
1256 | |
1257 | if (flush) { | |
1258 | dev->curr_ctx = ctx->num; | |
1259 | s5p_mfc_clean_ctx_int_flags(ctx); | |
1260 | WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6); | |
1261 | s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, | |
1262 | S5P_FIMV_H2R_CMD_FLUSH_V6, NULL); | |
1263 | } | |
f96f3cfa JP |
1264 | } |
1265 | ||
1266 | /* Decode a single frame */ | |
1267 | int s5p_mfc_decode_one_frame_v6(struct s5p_mfc_ctx *ctx, | |
1268 | enum s5p_mfc_decode_arg last_frame) | |
1269 | { | |
1270 | struct s5p_mfc_dev *dev = ctx->dev; | |
1271 | ||
1272 | WRITEL(ctx->dec_dst_flag, S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V6); | |
1273 | WRITEL(ctx->slice_interface & 0x1, S5P_FIMV_D_SLICE_IF_ENABLE_V6); | |
1274 | ||
1275 | WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6); | |
1276 | /* Issue different commands to instance basing on whether it | |
1277 | * is the last frame or not. */ | |
1278 | switch (last_frame) { | |
1279 | case 0: | |
1280 | s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, | |
1281 | S5P_FIMV_CH_FRAME_START_V6, NULL); | |
1282 | break; | |
1283 | case 1: | |
1284 | s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, | |
1285 | S5P_FIMV_CH_LAST_FRAME_V6, NULL); | |
1286 | break; | |
1287 | default: | |
1288 | mfc_err("Unsupported last frame arg.\n"); | |
1289 | return -EINVAL; | |
1290 | } | |
1291 | ||
1292 | mfc_debug(2, "Decoding a usual frame.\n"); | |
1293 | return 0; | |
1294 | } | |
1295 | ||
1296 | int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx) | |
1297 | { | |
1298 | struct s5p_mfc_dev *dev = ctx->dev; | |
1299 | ||
1300 | if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC) | |
1301 | s5p_mfc_set_enc_params_h264(ctx); | |
1302 | else if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_ENC) | |
1303 | s5p_mfc_set_enc_params_mpeg4(ctx); | |
1304 | else if (ctx->codec_mode == S5P_MFC_CODEC_H263_ENC) | |
1305 | s5p_mfc_set_enc_params_h263(ctx); | |
1306 | else { | |
1307 | mfc_err("Unknown codec for encoding (%x).\n", | |
1308 | ctx->codec_mode); | |
1309 | return -EINVAL; | |
1310 | } | |
1311 | ||
1312 | WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6); | |
1313 | s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, | |
1314 | S5P_FIMV_CH_SEQ_HEADER_V6, NULL); | |
1315 | ||
1316 | return 0; | |
1317 | } | |
1318 | ||
1319 | int s5p_mfc_h264_set_aso_slice_order_v6(struct s5p_mfc_ctx *ctx) | |
1320 | { | |
1321 | struct s5p_mfc_dev *dev = ctx->dev; | |
1322 | struct s5p_mfc_enc_params *p = &ctx->enc_params; | |
1323 | struct s5p_mfc_h264_enc_params *p_h264 = &p->codec.h264; | |
1324 | int i; | |
1325 | ||
1326 | if (p_h264->aso) { | |
1327 | for (i = 0; i < 8; i++) | |
1328 | WRITEL(p_h264->aso_slice_order[i], | |
1329 | S5P_FIMV_E_H264_ASO_SLICE_ORDER_0_V6 + i * 4); | |
1330 | } | |
1331 | return 0; | |
1332 | } | |
1333 | ||
1334 | /* Encode a single frame */ | |
1335 | int s5p_mfc_encode_one_frame_v6(struct s5p_mfc_ctx *ctx) | |
1336 | { | |
1337 | struct s5p_mfc_dev *dev = ctx->dev; | |
1338 | ||
1339 | mfc_debug(2, "++\n"); | |
1340 | ||
1341 | /* memory structure cur. frame */ | |
1342 | ||
1343 | if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC) | |
1344 | s5p_mfc_h264_set_aso_slice_order_v6(ctx); | |
1345 | ||
1346 | s5p_mfc_set_slice_mode(ctx); | |
1347 | ||
1348 | WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6); | |
1349 | s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, | |
1350 | S5P_FIMV_CH_FRAME_START_V6, NULL); | |
1351 | ||
1352 | mfc_debug(2, "--\n"); | |
1353 | ||
1354 | return 0; | |
1355 | } | |
1356 | ||
1357 | static inline int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev) | |
1358 | { | |
1359 | unsigned long flags; | |
1360 | int new_ctx; | |
1361 | int cnt; | |
1362 | ||
1363 | spin_lock_irqsave(&dev->condlock, flags); | |
1364 | mfc_debug(2, "Previos context: %d (bits %08lx)\n", dev->curr_ctx, | |
1365 | dev->ctx_work_bits); | |
1366 | new_ctx = (dev->curr_ctx + 1) % MFC_NUM_CONTEXTS; | |
1367 | cnt = 0; | |
1368 | while (!test_bit(new_ctx, &dev->ctx_work_bits)) { | |
1369 | new_ctx = (new_ctx + 1) % MFC_NUM_CONTEXTS; | |
1370 | cnt++; | |
1371 | if (cnt > MFC_NUM_CONTEXTS) { | |
1372 | /* No contexts to run */ | |
1373 | spin_unlock_irqrestore(&dev->condlock, flags); | |
1374 | return -EAGAIN; | |
1375 | } | |
1376 | } | |
1377 | spin_unlock_irqrestore(&dev->condlock, flags); | |
1378 | return new_ctx; | |
1379 | } | |
1380 | ||
1381 | static inline void s5p_mfc_run_dec_last_frames(struct s5p_mfc_ctx *ctx) | |
1382 | { | |
1383 | struct s5p_mfc_dev *dev = ctx->dev; | |
1384 | struct s5p_mfc_buf *temp_vb; | |
1385 | unsigned long flags; | |
1386 | ||
1387 | spin_lock_irqsave(&dev->irqlock, flags); | |
1388 | ||
1389 | /* Frames are being decoded */ | |
1390 | if (list_empty(&ctx->src_queue)) { | |
1391 | mfc_debug(2, "No src buffers.\n"); | |
1392 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
1393 | return; | |
1394 | } | |
1395 | /* Get the next source buffer */ | |
1396 | temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); | |
1397 | temp_vb->flags |= MFC_BUF_FLAG_USED; | |
1398 | s5p_mfc_set_dec_stream_buffer_v6(ctx, | |
1399 | vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), 0, 0); | |
1400 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
1401 | ||
1402 | dev->curr_ctx = ctx->num; | |
1403 | s5p_mfc_clean_ctx_int_flags(ctx); | |
1404 | s5p_mfc_decode_one_frame_v6(ctx, 1); | |
1405 | } | |
1406 | ||
1407 | static inline int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx) | |
1408 | { | |
1409 | struct s5p_mfc_dev *dev = ctx->dev; | |
1410 | struct s5p_mfc_buf *temp_vb; | |
1411 | unsigned long flags; | |
1412 | int last_frame = 0; | |
f96f3cfa JP |
1413 | |
1414 | spin_lock_irqsave(&dev->irqlock, flags); | |
1415 | ||
1416 | /* Frames are being decoded */ | |
1417 | if (list_empty(&ctx->src_queue)) { | |
1418 | mfc_debug(2, "No src buffers.\n"); | |
1419 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
1420 | return -EAGAIN; | |
1421 | } | |
1422 | /* Get the next source buffer */ | |
1423 | temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); | |
1424 | temp_vb->flags |= MFC_BUF_FLAG_USED; | |
1425 | s5p_mfc_set_dec_stream_buffer_v6(ctx, | |
1426 | vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), | |
1427 | ctx->consumed_stream, | |
1428 | temp_vb->b->v4l2_planes[0].bytesused); | |
1429 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
1430 | ||
f96f3cfa JP |
1431 | dev->curr_ctx = ctx->num; |
1432 | s5p_mfc_clean_ctx_int_flags(ctx); | |
1433 | if (temp_vb->b->v4l2_planes[0].bytesused == 0) { | |
1434 | last_frame = 1; | |
1435 | mfc_debug(2, "Setting ctx->state to FINISHING\n"); | |
1436 | ctx->state = MFCINST_FINISHING; | |
1437 | } | |
1438 | s5p_mfc_decode_one_frame_v6(ctx, last_frame); | |
1439 | ||
1440 | return 0; | |
1441 | } | |
1442 | ||
1443 | static inline int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx) | |
1444 | { | |
1445 | struct s5p_mfc_dev *dev = ctx->dev; | |
1446 | unsigned long flags; | |
1447 | struct s5p_mfc_buf *dst_mb; | |
1448 | struct s5p_mfc_buf *src_mb; | |
1449 | unsigned long src_y_addr, src_c_addr, dst_addr; | |
1450 | /* | |
1451 | unsigned int src_y_size, src_c_size; | |
1452 | */ | |
1453 | unsigned int dst_size; | |
f96f3cfa JP |
1454 | |
1455 | spin_lock_irqsave(&dev->irqlock, flags); | |
1456 | ||
1457 | if (list_empty(&ctx->src_queue)) { | |
1458 | mfc_debug(2, "no src buffers.\n"); | |
1459 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
1460 | return -EAGAIN; | |
1461 | } | |
1462 | ||
1463 | if (list_empty(&ctx->dst_queue)) { | |
1464 | mfc_debug(2, "no dst buffers.\n"); | |
1465 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
1466 | return -EAGAIN; | |
1467 | } | |
1468 | ||
1469 | src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); | |
1470 | src_mb->flags |= MFC_BUF_FLAG_USED; | |
1471 | src_y_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 0); | |
1472 | src_c_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 1); | |
1473 | ||
1474 | mfc_debug(2, "enc src y addr: 0x%08lx", src_y_addr); | |
1475 | mfc_debug(2, "enc src c addr: 0x%08lx", src_c_addr); | |
1476 | ||
1477 | s5p_mfc_set_enc_frame_buffer_v6(ctx, src_y_addr, src_c_addr); | |
1478 | ||
1479 | dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list); | |
1480 | dst_mb->flags |= MFC_BUF_FLAG_USED; | |
1481 | dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0); | |
1482 | dst_size = vb2_plane_size(dst_mb->b, 0); | |
1483 | ||
1484 | s5p_mfc_set_enc_stream_buffer_v6(ctx, dst_addr, dst_size); | |
1485 | ||
1486 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
1487 | ||
f96f3cfa JP |
1488 | dev->curr_ctx = ctx->num; |
1489 | s5p_mfc_clean_ctx_int_flags(ctx); | |
1490 | s5p_mfc_encode_one_frame_v6(ctx); | |
1491 | ||
1492 | return 0; | |
1493 | } | |
1494 | ||
1495 | static inline void s5p_mfc_run_init_dec(struct s5p_mfc_ctx *ctx) | |
1496 | { | |
1497 | struct s5p_mfc_dev *dev = ctx->dev; | |
1498 | unsigned long flags; | |
1499 | struct s5p_mfc_buf *temp_vb; | |
1500 | ||
1501 | /* Initializing decoding - parsing header */ | |
1502 | spin_lock_irqsave(&dev->irqlock, flags); | |
1503 | mfc_debug(2, "Preparing to init decoding.\n"); | |
1504 | temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); | |
1505 | mfc_debug(2, "Header size: %d\n", temp_vb->b->v4l2_planes[0].bytesused); | |
1506 | s5p_mfc_set_dec_stream_buffer_v6(ctx, | |
1507 | vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), 0, | |
1508 | temp_vb->b->v4l2_planes[0].bytesused); | |
1509 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
1510 | dev->curr_ctx = ctx->num; | |
1511 | s5p_mfc_clean_ctx_int_flags(ctx); | |
1512 | s5p_mfc_init_decode_v6(ctx); | |
1513 | } | |
1514 | ||
1515 | static inline void s5p_mfc_run_init_enc(struct s5p_mfc_ctx *ctx) | |
1516 | { | |
1517 | struct s5p_mfc_dev *dev = ctx->dev; | |
1518 | unsigned long flags; | |
1519 | struct s5p_mfc_buf *dst_mb; | |
1520 | unsigned long dst_addr; | |
1521 | unsigned int dst_size; | |
1522 | ||
1523 | spin_lock_irqsave(&dev->irqlock, flags); | |
1524 | ||
1525 | dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list); | |
1526 | dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0); | |
1527 | dst_size = vb2_plane_size(dst_mb->b, 0); | |
1528 | s5p_mfc_set_enc_stream_buffer_v6(ctx, dst_addr, dst_size); | |
1529 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
1530 | dev->curr_ctx = ctx->num; | |
1531 | s5p_mfc_clean_ctx_int_flags(ctx); | |
1532 | s5p_mfc_init_encode_v6(ctx); | |
1533 | } | |
1534 | ||
1535 | static inline int s5p_mfc_run_init_dec_buffers(struct s5p_mfc_ctx *ctx) | |
1536 | { | |
1537 | struct s5p_mfc_dev *dev = ctx->dev; | |
1538 | int ret; | |
1539 | /* Header was parsed now start processing | |
1540 | * First set the output frame buffers | |
1541 | * s5p_mfc_alloc_dec_buffers(ctx); */ | |
1542 | ||
1543 | if (ctx->capture_state != QUEUE_BUFS_MMAPED) { | |
1544 | mfc_err("It seems that not all destionation buffers were\n" | |
1545 | "mmaped.MFC requires that all destination are mmaped\n" | |
1546 | "before starting processing.\n"); | |
1547 | return -EAGAIN; | |
1548 | } | |
1549 | ||
1550 | dev->curr_ctx = ctx->num; | |
1551 | s5p_mfc_clean_ctx_int_flags(ctx); | |
1552 | ret = s5p_mfc_set_dec_frame_buffer_v6(ctx); | |
1553 | if (ret) { | |
1554 | mfc_err("Failed to alloc frame mem.\n"); | |
1555 | ctx->state = MFCINST_ERROR; | |
1556 | } | |
1557 | return ret; | |
1558 | } | |
1559 | ||
1560 | static inline int s5p_mfc_run_init_enc_buffers(struct s5p_mfc_ctx *ctx) | |
1561 | { | |
1562 | struct s5p_mfc_dev *dev = ctx->dev; | |
1563 | int ret; | |
1564 | ||
1565 | ret = s5p_mfc_alloc_codec_buffers_v6(ctx); | |
1566 | if (ret) { | |
1567 | mfc_err("Failed to allocate encoding buffers.\n"); | |
1568 | return -ENOMEM; | |
1569 | } | |
1570 | ||
1571 | /* Header was generated now starting processing | |
1572 | * First set the reference frame buffers | |
1573 | */ | |
1574 | if (ctx->capture_state != QUEUE_BUFS_REQUESTED) { | |
1575 | mfc_err("It seems that destionation buffers were not\n" | |
1576 | "requested.MFC requires that header should be generated\n" | |
1577 | "before allocating codec buffer.\n"); | |
1578 | return -EAGAIN; | |
1579 | } | |
1580 | ||
1581 | dev->curr_ctx = ctx->num; | |
1582 | s5p_mfc_clean_ctx_int_flags(ctx); | |
1583 | ret = s5p_mfc_set_enc_ref_buffer_v6(ctx); | |
1584 | if (ret) { | |
1585 | mfc_err("Failed to alloc frame mem.\n"); | |
1586 | ctx->state = MFCINST_ERROR; | |
1587 | } | |
1588 | return ret; | |
1589 | } | |
1590 | ||
1591 | /* Try running an operation on hardware */ | |
1592 | void s5p_mfc_try_run_v6(struct s5p_mfc_dev *dev) | |
1593 | { | |
1594 | struct s5p_mfc_ctx *ctx; | |
1595 | int new_ctx; | |
1596 | unsigned int ret = 0; | |
1597 | ||
1598 | mfc_debug(1, "Try run dev: %p\n", dev); | |
1599 | ||
1600 | /* Check whether hardware is not running */ | |
1601 | if (test_and_set_bit(0, &dev->hw_lock) != 0) { | |
1602 | /* This is perfectly ok, the scheduled ctx should wait */ | |
1603 | mfc_debug(1, "Couldn't lock HW.\n"); | |
1604 | return; | |
1605 | } | |
1606 | ||
1607 | /* Choose the context to run */ | |
1608 | new_ctx = s5p_mfc_get_new_ctx(dev); | |
1609 | if (new_ctx < 0) { | |
1610 | /* No contexts to run */ | |
1611 | if (test_and_clear_bit(0, &dev->hw_lock) == 0) { | |
1612 | mfc_err("Failed to unlock hardware.\n"); | |
1613 | return; | |
1614 | } | |
1615 | ||
1616 | mfc_debug(1, "No ctx is scheduled to be run.\n"); | |
1617 | return; | |
1618 | } | |
1619 | ||
1620 | mfc_debug(1, "New context: %d\n", new_ctx); | |
1621 | ctx = dev->ctx[new_ctx]; | |
1622 | mfc_debug(1, "Seting new context to %p\n", ctx); | |
1623 | /* Got context to run in ctx */ | |
1624 | mfc_debug(1, "ctx->dst_queue_cnt=%d ctx->dpb_count=%d ctx->src_queue_cnt=%d\n", | |
1625 | ctx->dst_queue_cnt, ctx->dpb_count, ctx->src_queue_cnt); | |
1626 | mfc_debug(1, "ctx->state=%d\n", ctx->state); | |
1627 | /* Last frame has already been sent to MFC | |
1628 | * Now obtaining frames from MFC buffer */ | |
1629 | ||
1630 | s5p_mfc_clock_on(); | |
1631 | if (ctx->type == MFCINST_DECODER) { | |
1632 | switch (ctx->state) { | |
1633 | case MFCINST_FINISHING: | |
1634 | s5p_mfc_run_dec_last_frames(ctx); | |
1635 | break; | |
1636 | case MFCINST_RUNNING: | |
1637 | ret = s5p_mfc_run_dec_frame(ctx); | |
1638 | break; | |
1639 | case MFCINST_INIT: | |
1640 | s5p_mfc_clean_ctx_int_flags(ctx); | |
1641 | ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd, | |
1642 | ctx); | |
1643 | break; | |
1644 | case MFCINST_RETURN_INST: | |
1645 | s5p_mfc_clean_ctx_int_flags(ctx); | |
1646 | ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd, | |
1647 | ctx); | |
1648 | break; | |
1649 | case MFCINST_GOT_INST: | |
1650 | s5p_mfc_run_init_dec(ctx); | |
1651 | break; | |
1652 | case MFCINST_HEAD_PARSED: | |
1653 | ret = s5p_mfc_run_init_dec_buffers(ctx); | |
1654 | break; | |
8f23cc02 AK |
1655 | case MFCINST_FLUSH: |
1656 | s5p_mfc_set_flush(ctx, ctx->dpb_flush_flag); | |
1657 | break; | |
f96f3cfa JP |
1658 | case MFCINST_RES_CHANGE_INIT: |
1659 | s5p_mfc_run_dec_last_frames(ctx); | |
1660 | break; | |
1661 | case MFCINST_RES_CHANGE_FLUSH: | |
1662 | s5p_mfc_run_dec_last_frames(ctx); | |
1663 | break; | |
1664 | case MFCINST_RES_CHANGE_END: | |
1665 | mfc_debug(2, "Finished remaining frames after resolution change.\n"); | |
1666 | ctx->capture_state = QUEUE_FREE; | |
1667 | mfc_debug(2, "Will re-init the codec`.\n"); | |
1668 | s5p_mfc_run_init_dec(ctx); | |
1669 | break; | |
1670 | default: | |
1671 | ret = -EAGAIN; | |
1672 | } | |
1673 | } else if (ctx->type == MFCINST_ENCODER) { | |
1674 | switch (ctx->state) { | |
1675 | case MFCINST_FINISHING: | |
1676 | case MFCINST_RUNNING: | |
1677 | ret = s5p_mfc_run_enc_frame(ctx); | |
1678 | break; | |
1679 | case MFCINST_INIT: | |
1680 | ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd, | |
1681 | ctx); | |
1682 | break; | |
1683 | case MFCINST_RETURN_INST: | |
1684 | ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd, | |
1685 | ctx); | |
1686 | break; | |
1687 | case MFCINST_GOT_INST: | |
1688 | s5p_mfc_run_init_enc(ctx); | |
1689 | break; | |
1690 | case MFCINST_HEAD_PARSED: /* Only for MFC6.x */ | |
1691 | ret = s5p_mfc_run_init_enc_buffers(ctx); | |
1692 | break; | |
1693 | default: | |
1694 | ret = -EAGAIN; | |
1695 | } | |
1696 | } else { | |
1697 | mfc_err("invalid context type: %d\n", ctx->type); | |
1698 | ret = -EAGAIN; | |
1699 | } | |
1700 | ||
1701 | if (ret) { | |
1702 | /* Free hardware lock */ | |
1703 | if (test_and_clear_bit(0, &dev->hw_lock) == 0) | |
1704 | mfc_err("Failed to unlock hardware.\n"); | |
1705 | ||
1706 | /* This is in deed imporant, as no operation has been | |
1707 | * scheduled, reduce the clock count as no one will | |
1708 | * ever do this, because no interrupt related to this try_run | |
1709 | * will ever come from hardware. */ | |
1710 | s5p_mfc_clock_off(); | |
1711 | } | |
1712 | } | |
1713 | ||
1714 | ||
1715 | void s5p_mfc_cleanup_queue_v6(struct list_head *lh, struct vb2_queue *vq) | |
1716 | { | |
1717 | struct s5p_mfc_buf *b; | |
1718 | int i; | |
1719 | ||
1720 | while (!list_empty(lh)) { | |
1721 | b = list_entry(lh->next, struct s5p_mfc_buf, list); | |
1722 | for (i = 0; i < b->b->num_planes; i++) | |
1723 | vb2_set_plane_payload(b->b, i, 0); | |
1724 | vb2_buffer_done(b->b, VB2_BUF_STATE_ERROR); | |
1725 | list_del(&b->list); | |
1726 | } | |
1727 | } | |
1728 | ||
1729 | void s5p_mfc_clear_int_flags_v6(struct s5p_mfc_dev *dev) | |
1730 | { | |
1731 | mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD_V6); | |
1732 | mfc_write(dev, 0, S5P_FIMV_RISC2HOST_INT_V6); | |
1733 | } | |
1734 | ||
1735 | void s5p_mfc_write_info_v6(struct s5p_mfc_ctx *ctx, unsigned int data, | |
1736 | unsigned int ofs) | |
1737 | { | |
1738 | struct s5p_mfc_dev *dev = ctx->dev; | |
1739 | ||
1740 | s5p_mfc_clock_on(); | |
1741 | WRITEL(data, ofs); | |
1742 | s5p_mfc_clock_off(); | |
1743 | } | |
1744 | ||
1745 | unsigned int s5p_mfc_read_info_v6(struct s5p_mfc_ctx *ctx, unsigned int ofs) | |
1746 | { | |
1747 | struct s5p_mfc_dev *dev = ctx->dev; | |
1748 | int ret; | |
1749 | ||
1750 | s5p_mfc_clock_on(); | |
1751 | ret = READL(ofs); | |
1752 | s5p_mfc_clock_off(); | |
1753 | ||
1754 | return ret; | |
1755 | } | |
1756 | ||
1757 | int s5p_mfc_get_dspl_y_adr_v6(struct s5p_mfc_dev *dev) | |
1758 | { | |
1759 | return mfc_read(dev, S5P_FIMV_D_DISPLAY_LUMA_ADDR_V6); | |
1760 | } | |
1761 | ||
1762 | int s5p_mfc_get_dec_y_adr_v6(struct s5p_mfc_dev *dev) | |
1763 | { | |
d9acbe1a | 1764 | return mfc_read(dev, S5P_FIMV_D_DECODED_LUMA_ADDR_V6); |
f96f3cfa JP |
1765 | } |
1766 | ||
1767 | int s5p_mfc_get_dspl_status_v6(struct s5p_mfc_dev *dev) | |
1768 | { | |
1769 | return mfc_read(dev, S5P_FIMV_D_DISPLAY_STATUS_V6); | |
1770 | } | |
1771 | ||
1772 | int s5p_mfc_get_decoded_status_v6(struct s5p_mfc_dev *dev) | |
1773 | { | |
1774 | return mfc_read(dev, S5P_FIMV_D_DECODED_STATUS_V6); | |
1775 | } | |
1776 | ||
1777 | int s5p_mfc_get_dec_frame_type_v6(struct s5p_mfc_dev *dev) | |
1778 | { | |
1779 | return mfc_read(dev, S5P_FIMV_D_DECODED_FRAME_TYPE_V6) & | |
1780 | S5P_FIMV_DECODE_FRAME_MASK_V6; | |
1781 | } | |
1782 | ||
1783 | int s5p_mfc_get_disp_frame_type_v6(struct s5p_mfc_ctx *ctx) | |
1784 | { | |
1785 | return mfc_read(ctx->dev, S5P_FIMV_D_DISPLAY_FRAME_TYPE_V6) & | |
1786 | S5P_FIMV_DECODE_FRAME_MASK_V6; | |
1787 | } | |
1788 | ||
1789 | int s5p_mfc_get_consumed_stream_v6(struct s5p_mfc_dev *dev) | |
1790 | { | |
1791 | return mfc_read(dev, S5P_FIMV_D_DECODED_NAL_SIZE_V6); | |
1792 | } | |
1793 | ||
1794 | int s5p_mfc_get_int_reason_v6(struct s5p_mfc_dev *dev) | |
1795 | { | |
1796 | return mfc_read(dev, S5P_FIMV_RISC2HOST_CMD_V6) & | |
1797 | S5P_FIMV_RISC2HOST_CMD_MASK; | |
1798 | } | |
1799 | ||
1800 | int s5p_mfc_get_int_err_v6(struct s5p_mfc_dev *dev) | |
1801 | { | |
1802 | return mfc_read(dev, S5P_FIMV_ERROR_CODE_V6); | |
1803 | } | |
1804 | ||
1805 | int s5p_mfc_err_dec_v6(unsigned int err) | |
1806 | { | |
1807 | return (err & S5P_FIMV_ERR_DEC_MASK_V6) >> S5P_FIMV_ERR_DEC_SHIFT_V6; | |
1808 | } | |
1809 | ||
1810 | int s5p_mfc_err_dspl_v6(unsigned int err) | |
1811 | { | |
1812 | return (err & S5P_FIMV_ERR_DSPL_MASK_V6) >> S5P_FIMV_ERR_DSPL_SHIFT_V6; | |
1813 | } | |
1814 | ||
1815 | int s5p_mfc_get_img_width_v6(struct s5p_mfc_dev *dev) | |
1816 | { | |
1817 | return mfc_read(dev, S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V6); | |
1818 | } | |
1819 | ||
1820 | int s5p_mfc_get_img_height_v6(struct s5p_mfc_dev *dev) | |
1821 | { | |
1822 | return mfc_read(dev, S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V6); | |
1823 | } | |
1824 | ||
1825 | int s5p_mfc_get_dpb_count_v6(struct s5p_mfc_dev *dev) | |
1826 | { | |
1827 | return mfc_read(dev, S5P_FIMV_D_MIN_NUM_DPB_V6); | |
1828 | } | |
1829 | ||
1830 | int s5p_mfc_get_mv_count_v6(struct s5p_mfc_dev *dev) | |
1831 | { | |
1832 | return mfc_read(dev, S5P_FIMV_D_MIN_NUM_MV_V6); | |
1833 | } | |
1834 | ||
1835 | int s5p_mfc_get_inst_no_v6(struct s5p_mfc_dev *dev) | |
1836 | { | |
1837 | return mfc_read(dev, S5P_FIMV_RET_INSTANCE_ID_V6); | |
1838 | } | |
1839 | ||
1840 | int s5p_mfc_get_enc_dpb_count_v6(struct s5p_mfc_dev *dev) | |
1841 | { | |
1842 | return mfc_read(dev, S5P_FIMV_E_NUM_DPB_V6); | |
1843 | } | |
1844 | ||
1845 | int s5p_mfc_get_enc_strm_size_v6(struct s5p_mfc_dev *dev) | |
1846 | { | |
1847 | return mfc_read(dev, S5P_FIMV_E_STREAM_SIZE_V6); | |
1848 | } | |
1849 | ||
1850 | int s5p_mfc_get_enc_slice_type_v6(struct s5p_mfc_dev *dev) | |
1851 | { | |
1852 | return mfc_read(dev, S5P_FIMV_E_SLICE_TYPE_V6); | |
1853 | } | |
1854 | ||
1855 | int s5p_mfc_get_enc_pic_count_v6(struct s5p_mfc_dev *dev) | |
1856 | { | |
1857 | return mfc_read(dev, S5P_FIMV_E_PICTURE_COUNT_V6); | |
1858 | } | |
1859 | ||
1860 | int s5p_mfc_get_sei_avail_status_v6(struct s5p_mfc_ctx *ctx) | |
1861 | { | |
1862 | return mfc_read(ctx->dev, S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V6); | |
1863 | } | |
1864 | ||
1865 | int s5p_mfc_get_mvc_num_views_v6(struct s5p_mfc_dev *dev) | |
1866 | { | |
1867 | return mfc_read(dev, S5P_FIMV_D_MVC_NUM_VIEWS_V6); | |
1868 | } | |
1869 | ||
1870 | int s5p_mfc_get_mvc_view_id_v6(struct s5p_mfc_dev *dev) | |
1871 | { | |
1872 | return mfc_read(dev, S5P_FIMV_D_MVC_VIEW_ID_V6); | |
1873 | } | |
1874 | ||
1875 | unsigned int s5p_mfc_get_pic_type_top_v6(struct s5p_mfc_ctx *ctx) | |
1876 | { | |
1877 | return s5p_mfc_read_info_v6(ctx, PIC_TIME_TOP_V6); | |
1878 | } | |
1879 | ||
1880 | unsigned int s5p_mfc_get_pic_type_bot_v6(struct s5p_mfc_ctx *ctx) | |
1881 | { | |
1882 | return s5p_mfc_read_info_v6(ctx, PIC_TIME_BOT_V6); | |
1883 | } | |
1884 | ||
1885 | unsigned int s5p_mfc_get_crop_info_h_v6(struct s5p_mfc_ctx *ctx) | |
1886 | { | |
1887 | return s5p_mfc_read_info_v6(ctx, CROP_INFO_H_V6); | |
1888 | } | |
1889 | ||
1890 | unsigned int s5p_mfc_get_crop_info_v_v6(struct s5p_mfc_ctx *ctx) | |
1891 | { | |
1892 | return s5p_mfc_read_info_v6(ctx, CROP_INFO_V_V6); | |
1893 | } | |
1894 | ||
1895 | /* Initialize opr function pointers for MFC v6 */ | |
1896 | static struct s5p_mfc_hw_ops s5p_mfc_ops_v6 = { | |
1897 | .alloc_dec_temp_buffers = s5p_mfc_alloc_dec_temp_buffers_v6, | |
1898 | .release_dec_desc_buffer = s5p_mfc_release_dec_desc_buffer_v6, | |
1899 | .alloc_codec_buffers = s5p_mfc_alloc_codec_buffers_v6, | |
1900 | .release_codec_buffers = s5p_mfc_release_codec_buffers_v6, | |
1901 | .alloc_instance_buffer = s5p_mfc_alloc_instance_buffer_v6, | |
1902 | .release_instance_buffer = s5p_mfc_release_instance_buffer_v6, | |
1903 | .alloc_dev_context_buffer = | |
1904 | s5p_mfc_alloc_dev_context_buffer_v6, | |
1905 | .release_dev_context_buffer = | |
1906 | s5p_mfc_release_dev_context_buffer_v6, | |
1907 | .dec_calc_dpb_size = s5p_mfc_dec_calc_dpb_size_v6, | |
1908 | .enc_calc_src_size = s5p_mfc_enc_calc_src_size_v6, | |
1909 | .set_dec_stream_buffer = s5p_mfc_set_dec_stream_buffer_v6, | |
1910 | .set_dec_frame_buffer = s5p_mfc_set_dec_frame_buffer_v6, | |
1911 | .set_enc_stream_buffer = s5p_mfc_set_enc_stream_buffer_v6, | |
1912 | .set_enc_frame_buffer = s5p_mfc_set_enc_frame_buffer_v6, | |
1913 | .get_enc_frame_buffer = s5p_mfc_get_enc_frame_buffer_v6, | |
1914 | .set_enc_ref_buffer = s5p_mfc_set_enc_ref_buffer_v6, | |
1915 | .init_decode = s5p_mfc_init_decode_v6, | |
1916 | .init_encode = s5p_mfc_init_encode_v6, | |
1917 | .encode_one_frame = s5p_mfc_encode_one_frame_v6, | |
1918 | .try_run = s5p_mfc_try_run_v6, | |
1919 | .cleanup_queue = s5p_mfc_cleanup_queue_v6, | |
1920 | .clear_int_flags = s5p_mfc_clear_int_flags_v6, | |
1921 | .write_info = s5p_mfc_write_info_v6, | |
1922 | .read_info = s5p_mfc_read_info_v6, | |
1923 | .get_dspl_y_adr = s5p_mfc_get_dspl_y_adr_v6, | |
1924 | .get_dec_y_adr = s5p_mfc_get_dec_y_adr_v6, | |
1925 | .get_dspl_status = s5p_mfc_get_dspl_status_v6, | |
1926 | .get_dec_status = s5p_mfc_get_dec_status_v6, | |
1927 | .get_dec_frame_type = s5p_mfc_get_dec_frame_type_v6, | |
1928 | .get_disp_frame_type = s5p_mfc_get_disp_frame_type_v6, | |
1929 | .get_consumed_stream = s5p_mfc_get_consumed_stream_v6, | |
1930 | .get_int_reason = s5p_mfc_get_int_reason_v6, | |
1931 | .get_int_err = s5p_mfc_get_int_err_v6, | |
1932 | .err_dec = s5p_mfc_err_dec_v6, | |
1933 | .err_dspl = s5p_mfc_err_dspl_v6, | |
1934 | .get_img_width = s5p_mfc_get_img_width_v6, | |
1935 | .get_img_height = s5p_mfc_get_img_height_v6, | |
1936 | .get_dpb_count = s5p_mfc_get_dpb_count_v6, | |
1937 | .get_mv_count = s5p_mfc_get_mv_count_v6, | |
1938 | .get_inst_no = s5p_mfc_get_inst_no_v6, | |
1939 | .get_enc_strm_size = s5p_mfc_get_enc_strm_size_v6, | |
1940 | .get_enc_slice_type = s5p_mfc_get_enc_slice_type_v6, | |
1941 | .get_enc_dpb_count = s5p_mfc_get_enc_dpb_count_v6, | |
1942 | .get_enc_pic_count = s5p_mfc_get_enc_pic_count_v6, | |
1943 | .get_sei_avail_status = s5p_mfc_get_sei_avail_status_v6, | |
1944 | .get_mvc_num_views = s5p_mfc_get_mvc_num_views_v6, | |
1945 | .get_mvc_view_id = s5p_mfc_get_mvc_view_id_v6, | |
1946 | .get_pic_type_top = s5p_mfc_get_pic_type_top_v6, | |
1947 | .get_pic_type_bot = s5p_mfc_get_pic_type_bot_v6, | |
1948 | .get_crop_info_h = s5p_mfc_get_crop_info_h_v6, | |
1949 | .get_crop_info_v = s5p_mfc_get_crop_info_v_v6, | |
1950 | }; | |
1951 | ||
1952 | struct s5p_mfc_hw_ops *s5p_mfc_init_hw_ops_v6(void) | |
1953 | { | |
1954 | return &s5p_mfc_ops_v6; | |
1955 | } |