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3bc43840 GL |
1 | /* |
2 | * V4L2 Driver for PXA camera host | |
3 | * | |
4 | * Copyright (C) 2006, Sascha Hauer, Pengutronix | |
5 | * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
3bc43840 GL |
13 | #include <linux/init.h> |
14 | #include <linux/module.h> | |
7102b773 | 15 | #include <linux/io.h> |
3bc43840 GL |
16 | #include <linux/delay.h> |
17 | #include <linux/dma-mapping.h> | |
8efdb135 | 18 | #include <linux/err.h> |
3bc43840 GL |
19 | #include <linux/errno.h> |
20 | #include <linux/fs.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/mm.h> | |
24 | #include <linux/moduleparam.h> | |
25 | #include <linux/time.h> | |
3bc43840 GL |
26 | #include <linux/device.h> |
27 | #include <linux/platform_device.h> | |
3bc43840 | 28 | #include <linux/clk.h> |
d514edac | 29 | #include <linux/sched.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
3bc43840 GL |
31 | |
32 | #include <media/v4l2-common.h> | |
33 | #include <media/v4l2-dev.h> | |
092d3921 | 34 | #include <media/videobuf-dma-sg.h> |
3bc43840 | 35 | #include <media/soc_camera.h> |
d647f0b7 | 36 | #include <media/drv-intf/soc_mediabus.h> |
e9a1d94f | 37 | #include <media/v4l2-of.h> |
3bc43840 GL |
38 | |
39 | #include <linux/videodev2.h> | |
40 | ||
cfbaf4df | 41 | #include <mach/dma.h> |
a71daaa1 | 42 | #include <linux/platform_data/media/camera-pxa.h> |
3bc43840 | 43 | |
64dc3c1a | 44 | #define PXA_CAM_VERSION "0.0.6" |
3bc43840 GL |
45 | #define PXA_CAM_DRV_NAME "pxa27x-camera" |
46 | ||
5ca11fa3 EM |
47 | /* Camera Interface */ |
48 | #define CICR0 0x0000 | |
49 | #define CICR1 0x0004 | |
50 | #define CICR2 0x0008 | |
51 | #define CICR3 0x000C | |
52 | #define CICR4 0x0010 | |
53 | #define CISR 0x0014 | |
54 | #define CIFR 0x0018 | |
55 | #define CITOR 0x001C | |
56 | #define CIBR0 0x0028 | |
57 | #define CIBR1 0x0030 | |
58 | #define CIBR2 0x0038 | |
59 | ||
60 | #define CICR0_DMAEN (1 << 31) /* DMA request enable */ | |
61 | #define CICR0_PAR_EN (1 << 30) /* Parity enable */ | |
62 | #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */ | |
63 | #define CICR0_ENB (1 << 28) /* Camera interface enable */ | |
64 | #define CICR0_DIS (1 << 27) /* Camera interface disable */ | |
65 | #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */ | |
66 | #define CICR0_TOM (1 << 9) /* Time-out mask */ | |
67 | #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */ | |
68 | #define CICR0_FEM (1 << 7) /* FIFO-empty mask */ | |
69 | #define CICR0_EOLM (1 << 6) /* End-of-line mask */ | |
70 | #define CICR0_PERRM (1 << 5) /* Parity-error mask */ | |
71 | #define CICR0_QDM (1 << 4) /* Quick-disable mask */ | |
72 | #define CICR0_CDM (1 << 3) /* Disable-done mask */ | |
73 | #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */ | |
74 | #define CICR0_EOFM (1 << 1) /* End-of-frame mask */ | |
75 | #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */ | |
76 | ||
77 | #define CICR1_TBIT (1 << 31) /* Transparency bit */ | |
78 | #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */ | |
79 | #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */ | |
80 | #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ | |
81 | #define CICR1_RGB_F (1 << 11) /* RGB format */ | |
82 | #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */ | |
83 | #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */ | |
84 | #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */ | |
85 | #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */ | |
86 | #define CICR1_DW (0x7 << 0) /* Data width mask */ | |
87 | ||
88 | #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock | |
89 | wait count mask */ | |
90 | #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock | |
91 | wait count mask */ | |
92 | #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */ | |
93 | #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | |
94 | wait count mask */ | |
95 | #define CICR2_FSW (0x7 << 0) /* Frame stabilization | |
96 | wait count mask */ | |
97 | ||
98 | #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock | |
99 | wait count mask */ | |
100 | #define CICR3_EFW (0xff << 16) /* End-of-frame line clock | |
101 | wait count mask */ | |
102 | #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */ | |
103 | #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | |
104 | wait count mask */ | |
105 | #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */ | |
106 | ||
107 | #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */ | |
108 | #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */ | |
109 | #define CICR4_PCP (1 << 22) /* Pixel clock polarity */ | |
110 | #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */ | |
111 | #define CICR4_VSP (1 << 20) /* Vertical sync polarity */ | |
112 | #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */ | |
113 | #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */ | |
114 | #define CICR4_DIV (0xff << 0) /* Clock divisor mask */ | |
115 | ||
116 | #define CISR_FTO (1 << 15) /* FIFO time-out */ | |
117 | #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */ | |
118 | #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */ | |
119 | #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */ | |
120 | #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */ | |
121 | #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */ | |
122 | #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */ | |
123 | #define CISR_EOL (1 << 8) /* End of line */ | |
124 | #define CISR_PAR_ERR (1 << 7) /* Parity error */ | |
125 | #define CISR_CQD (1 << 6) /* Camera interface quick disable */ | |
126 | #define CISR_CDD (1 << 5) /* Camera interface disable done */ | |
127 | #define CISR_SOF (1 << 4) /* Start of frame */ | |
128 | #define CISR_EOF (1 << 3) /* End of frame */ | |
129 | #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */ | |
130 | #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */ | |
131 | #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */ | |
132 | ||
133 | #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */ | |
134 | #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */ | |
135 | #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */ | |
136 | #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */ | |
137 | #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */ | |
138 | #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */ | |
139 | #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */ | |
140 | #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */ | |
141 | ||
7102b773 GL |
142 | #define CICR0_SIM_MP (0 << 24) |
143 | #define CICR0_SIM_SP (1 << 24) | |
144 | #define CICR0_SIM_MS (2 << 24) | |
145 | #define CICR0_SIM_EP (3 << 24) | |
146 | #define CICR0_SIM_ES (4 << 24) | |
147 | ||
148 | #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */ | |
149 | #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */ | |
a5462e5b MR |
150 | #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */ |
151 | #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */ | |
152 | #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */ | |
7102b773 GL |
153 | |
154 | #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */ | |
155 | #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */ | |
156 | #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */ | |
157 | #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */ | |
158 | #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */ | |
159 | ||
160 | #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */ | |
161 | #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */ | |
162 | #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */ | |
163 | #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */ | |
164 | ||
3bc43840 GL |
165 | #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \ |
166 | CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \ | |
167 | CICR0_EOFM | CICR0_FOM) | |
168 | ||
3bc43840 GL |
169 | /* |
170 | * Structures | |
171 | */ | |
a5462e5b MR |
172 | enum pxa_camera_active_dma { |
173 | DMA_Y = 0x1, | |
174 | DMA_U = 0x2, | |
175 | DMA_V = 0x4, | |
176 | }; | |
177 | ||
178 | /* descriptor needed for the PXA DMA engine */ | |
179 | struct pxa_cam_dma { | |
180 | dma_addr_t sg_dma; | |
181 | struct pxa_dma_desc *sg_cpu; | |
182 | size_t sg_size; | |
183 | int sglen; | |
184 | }; | |
3bc43840 GL |
185 | |
186 | /* buffer for one video frame */ | |
187 | struct pxa_buffer { | |
188 | /* common v4l buffer stuff -- must be first */ | |
760697be | 189 | struct videobuf_buffer vb; |
27ffaeb0 | 190 | u32 code; |
a5462e5b | 191 | /* our descriptor lists for Y, U and V channels */ |
760697be GL |
192 | struct pxa_cam_dma dmas[3]; |
193 | int inwork; | |
194 | enum pxa_camera_active_dma active_dma; | |
3bc43840 GL |
195 | }; |
196 | ||
3bc43840 | 197 | struct pxa_camera_dev { |
eb6c8558 | 198 | struct soc_camera_host soc_host; |
5d28d525 GL |
199 | /* |
200 | * PXA27x is only supposed to handle one camera on its Quick Capture | |
3bc43840 | 201 | * interface. If anyone ever builds hardware to enable more than |
5d28d525 GL |
202 | * one camera, they will have to modify this driver too |
203 | */ | |
3bc43840 GL |
204 | struct clk *clk; |
205 | ||
206 | unsigned int irq; | |
207 | void __iomem *base; | |
a5462e5b | 208 | |
e7c50688 | 209 | int channels; |
a5462e5b | 210 | unsigned int dma_chans[3]; |
3bc43840 | 211 | |
3bc43840 GL |
212 | struct pxacamera_platform_data *pdata; |
213 | struct resource *res; | |
214 | unsigned long platform_flags; | |
cf34cba7 GL |
215 | unsigned long ciclk; |
216 | unsigned long mclk; | |
217 | u32 mclk_divisor; | |
679419aa | 218 | u16 width_flags; /* max 10 bits */ |
3bc43840 GL |
219 | |
220 | struct list_head capture; | |
221 | ||
222 | spinlock_t lock; | |
223 | ||
3bc43840 | 224 | struct pxa_buffer *active; |
5aa2110f | 225 | struct pxa_dma_desc *sg_tail[3]; |
e623ebe6 | 226 | struct tasklet_struct task_eof; |
3f6ac497 RJ |
227 | |
228 | u32 save_cicr[5]; | |
3bc43840 GL |
229 | }; |
230 | ||
6a6c8786 GL |
231 | struct pxa_cam { |
232 | unsigned long flags; | |
233 | }; | |
234 | ||
3bc43840 GL |
235 | static const char *pxa_cam_driver_description = "PXA_Camera"; |
236 | ||
237 | static unsigned int vid_limit = 16; /* Video memory limit, in Mb */ | |
238 | ||
239 | /* | |
240 | * Videobuf operations | |
241 | */ | |
7102b773 GL |
242 | static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count, |
243 | unsigned int *size) | |
3bc43840 GL |
244 | { |
245 | struct soc_camera_device *icd = vq->priv_data; | |
246 | ||
7dfff953 | 247 | dev_dbg(icd->parent, "count=%d, size=%d\n", *count, *size); |
3bc43840 | 248 | |
2b61d46e | 249 | *size = icd->sizeimage; |
3bc43840 GL |
250 | |
251 | if (0 == *count) | |
252 | *count = 32; | |
dab7e310 AB |
253 | if (*size * *count > vid_limit * 1024 * 1024) |
254 | *count = (vid_limit * 1024 * 1024) / *size; | |
3bc43840 GL |
255 | |
256 | return 0; | |
257 | } | |
258 | ||
259 | static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf) | |
260 | { | |
261 | struct soc_camera_device *icd = vq->priv_data; | |
7dfff953 | 262 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
3bc43840 | 263 | struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb); |
a5462e5b | 264 | int i; |
3bc43840 GL |
265 | |
266 | BUG_ON(in_interrupt()); | |
267 | ||
7dfff953 | 268 | dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
269 | &buf->vb, buf->vb.baddr, buf->vb.bsize); |
270 | ||
5d28d525 GL |
271 | /* |
272 | * This waits until this buffer is out of danger, i.e., until it is no | |
273 | * longer in STATE_QUEUED or STATE_ACTIVE | |
274 | */ | |
0e0809a5 | 275 | videobuf_waiton(vq, &buf->vb, 0, 0); |
3bc43840 | 276 | |
a5462e5b MR |
277 | for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) { |
278 | if (buf->dmas[i].sg_cpu) | |
96c75399 GL |
279 | dma_free_coherent(ici->v4l2_dev.dev, |
280 | buf->dmas[i].sg_size, | |
a5462e5b MR |
281 | buf->dmas[i].sg_cpu, |
282 | buf->dmas[i].sg_dma); | |
283 | buf->dmas[i].sg_cpu = NULL; | |
284 | } | |
8f4895f2 RJ |
285 | videobuf_dma_unmap(vq->dev, dma); |
286 | videobuf_dma_free(dma); | |
3bc43840 GL |
287 | |
288 | buf->vb.state = VIDEOBUF_NEEDS_INIT; | |
289 | } | |
290 | ||
37f5aefd RJ |
291 | static int calculate_dma_sglen(struct scatterlist *sglist, int sglen, |
292 | int sg_first_ofs, int size) | |
293 | { | |
294 | int i, offset, dma_len, xfer_len; | |
295 | struct scatterlist *sg; | |
296 | ||
297 | offset = sg_first_ofs; | |
298 | for_each_sg(sglist, sg, sglen, i) { | |
299 | dma_len = sg_dma_len(sg); | |
300 | ||
301 | /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */ | |
302 | xfer_len = roundup(min(dma_len - offset, size), 8); | |
303 | ||
304 | size = max(0, size - xfer_len); | |
305 | offset = 0; | |
306 | if (size == 0) | |
307 | break; | |
308 | } | |
309 | ||
310 | BUG_ON(size != 0); | |
311 | return i + 1; | |
312 | } | |
313 | ||
314 | /** | |
315 | * pxa_init_dma_channel - init dma descriptors | |
316 | * @pcdev: pxa camera device | |
317 | * @buf: pxa buffer to find pxa dma channel | |
318 | * @dma: dma video buffer | |
319 | * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V') | |
320 | * @cibr: camera Receive Buffer Register | |
321 | * @size: bytes to transfer | |
322 | * @sg_first: first element of sg_list | |
323 | * @sg_first_ofs: offset in first element of sg_list | |
324 | * | |
325 | * Prepares the pxa dma descriptors to transfer one camera channel. | |
326 | * Beware sg_first and sg_first_ofs are both input and output parameters. | |
327 | * | |
328 | * Returns 0 or -ENOMEM if no coherent memory is available | |
329 | */ | |
a5462e5b MR |
330 | static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev, |
331 | struct pxa_buffer *buf, | |
332 | struct videobuf_dmabuf *dma, int channel, | |
37f5aefd RJ |
333 | int cibr, int size, |
334 | struct scatterlist **sg_first, int *sg_first_ofs) | |
a5462e5b MR |
335 | { |
336 | struct pxa_cam_dma *pxa_dma = &buf->dmas[channel]; | |
979ea1dd | 337 | struct device *dev = pcdev->soc_host.v4l2_dev.dev; |
37f5aefd RJ |
338 | struct scatterlist *sg; |
339 | int i, offset, sglen; | |
340 | int dma_len = 0, xfer_len = 0; | |
a5462e5b MR |
341 | |
342 | if (pxa_dma->sg_cpu) | |
979ea1dd | 343 | dma_free_coherent(dev, pxa_dma->sg_size, |
a5462e5b MR |
344 | pxa_dma->sg_cpu, pxa_dma->sg_dma); |
345 | ||
37f5aefd RJ |
346 | sglen = calculate_dma_sglen(*sg_first, dma->sglen, |
347 | *sg_first_ofs, size); | |
348 | ||
a5462e5b | 349 | pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc); |
979ea1dd | 350 | pxa_dma->sg_cpu = dma_alloc_coherent(dev, pxa_dma->sg_size, |
a5462e5b MR |
351 | &pxa_dma->sg_dma, GFP_KERNEL); |
352 | if (!pxa_dma->sg_cpu) | |
353 | return -ENOMEM; | |
354 | ||
355 | pxa_dma->sglen = sglen; | |
37f5aefd | 356 | offset = *sg_first_ofs; |
a5462e5b | 357 | |
979ea1dd | 358 | dev_dbg(dev, "DMA: sg_first=%p, sglen=%d, ofs=%d, dma.desc=%x\n", |
37f5aefd | 359 | *sg_first, sglen, *sg_first_ofs, pxa_dma->sg_dma); |
a5462e5b | 360 | |
37f5aefd RJ |
361 | |
362 | for_each_sg(*sg_first, sg, sglen, i) { | |
363 | dma_len = sg_dma_len(sg); | |
a5462e5b MR |
364 | |
365 | /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */ | |
37f5aefd | 366 | xfer_len = roundup(min(dma_len - offset, size), 8); |
a5462e5b | 367 | |
37f5aefd RJ |
368 | size = max(0, size - xfer_len); |
369 | ||
370 | pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr; | |
371 | pxa_dma->sg_cpu[i].dtadr = sg_dma_address(sg) + offset; | |
a5462e5b MR |
372 | pxa_dma->sg_cpu[i].dcmd = |
373 | DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len; | |
256b0233 RJ |
374 | #ifdef DEBUG |
375 | if (!i) | |
376 | pxa_dma->sg_cpu[i].dcmd |= DCMD_STARTIRQEN; | |
377 | #endif | |
a5462e5b MR |
378 | pxa_dma->sg_cpu[i].ddadr = |
379 | pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc); | |
37f5aefd | 380 | |
979ea1dd | 381 | dev_vdbg(dev, "DMA: desc.%08x->@phys=0x%08x, len=%d\n", |
37f5aefd RJ |
382 | pxa_dma->sg_dma + i * sizeof(struct pxa_dma_desc), |
383 | sg_dma_address(sg) + offset, xfer_len); | |
384 | offset = 0; | |
385 | ||
386 | if (size == 0) | |
387 | break; | |
a5462e5b MR |
388 | } |
389 | ||
256b0233 RJ |
390 | pxa_dma->sg_cpu[sglen].ddadr = DDADR_STOP; |
391 | pxa_dma->sg_cpu[sglen].dcmd = DCMD_FLOWSRC | DCMD_BURST8 | DCMD_ENDIRQEN; | |
a5462e5b | 392 | |
37f5aefd RJ |
393 | /* |
394 | * Handle 1 special case : | |
395 | * - in 3 planes (YUV422P format), we might finish with xfer_len equal | |
396 | * to dma_len (end on PAGE boundary). In this case, the sg element | |
397 | * for next plane should be the next after the last used to store the | |
398 | * last scatter gather RAM page | |
399 | */ | |
400 | if (xfer_len >= dma_len) { | |
401 | *sg_first_ofs = xfer_len - dma_len; | |
402 | *sg_first = sg_next(sg); | |
403 | } else { | |
404 | *sg_first_ofs = xfer_len; | |
405 | *sg_first = sg; | |
406 | } | |
407 | ||
a5462e5b MR |
408 | return 0; |
409 | } | |
410 | ||
256b0233 RJ |
411 | static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev, |
412 | struct pxa_buffer *buf) | |
413 | { | |
414 | buf->active_dma = DMA_Y; | |
415 | if (pcdev->channels == 3) | |
416 | buf->active_dma |= DMA_U | DMA_V; | |
417 | } | |
418 | ||
419 | /* | |
420 | * Please check the DMA prepared buffer structure in : | |
421 | * Documentation/video4linux/pxa_camera.txt | |
422 | * Please check also in pxa_camera_check_link_miss() to understand why DMA chain | |
423 | * modification while DMA chain is running will work anyway. | |
424 | */ | |
7102b773 GL |
425 | static int pxa_videobuf_prepare(struct videobuf_queue *vq, |
426 | struct videobuf_buffer *vb, enum v4l2_field field) | |
3bc43840 GL |
427 | { |
428 | struct soc_camera_device *icd = vq->priv_data; | |
7dfff953 | 429 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
3bc43840 | 430 | struct pxa_camera_dev *pcdev = ici->priv; |
979ea1dd | 431 | struct device *dev = pcdev->soc_host.v4l2_dev.dev; |
3bc43840 | 432 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); |
a5462e5b | 433 | int ret; |
a5462e5b | 434 | int size_y, size_u = 0, size_v = 0; |
3bc43840 | 435 | |
979ea1dd | 436 | dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
437 | vb, vb->baddr, vb->bsize); |
438 | ||
439 | /* Added list head initialization on alloc */ | |
440 | WARN_ON(!list_empty(&vb->queue)); | |
441 | ||
442 | #ifdef DEBUG | |
5d28d525 GL |
443 | /* |
444 | * This can be useful if you want to see if we actually fill | |
445 | * the buffer with something | |
446 | */ | |
3bc43840 GL |
447 | memset((void *)vb->baddr, 0xaa, vb->bsize); |
448 | #endif | |
449 | ||
450 | BUG_ON(NULL == icd->current_fmt); | |
451 | ||
5d28d525 GL |
452 | /* |
453 | * I think, in buf_prepare you only have to protect global data, | |
454 | * the actual buffer is yours | |
455 | */ | |
3bc43840 GL |
456 | buf->inwork = 1; |
457 | ||
760697be | 458 | if (buf->code != icd->current_fmt->code || |
6a6c8786 GL |
459 | vb->width != icd->user_width || |
460 | vb->height != icd->user_height || | |
3bc43840 | 461 | vb->field != field) { |
760697be | 462 | buf->code = icd->current_fmt->code; |
6a6c8786 GL |
463 | vb->width = icd->user_width; |
464 | vb->height = icd->user_height; | |
3bc43840 GL |
465 | vb->field = field; |
466 | vb->state = VIDEOBUF_NEEDS_INIT; | |
467 | } | |
468 | ||
2b61d46e | 469 | vb->size = icd->sizeimage; |
3bc43840 GL |
470 | if (0 != vb->baddr && vb->bsize < vb->size) { |
471 | ret = -EINVAL; | |
472 | goto out; | |
473 | } | |
474 | ||
475 | if (vb->state == VIDEOBUF_NEEDS_INIT) { | |
37f5aefd RJ |
476 | int size = vb->size; |
477 | int next_ofs = 0; | |
3bc43840 | 478 | struct videobuf_dmabuf *dma = videobuf_to_dma(vb); |
37f5aefd | 479 | struct scatterlist *sg; |
3bc43840 GL |
480 | |
481 | ret = videobuf_iolock(vq, vb, NULL); | |
482 | if (ret) | |
8f4895f2 | 483 | goto out; |
3bc43840 | 484 | |
5aa2110f | 485 | if (pcdev->channels == 3) { |
a5462e5b MR |
486 | size_y = size / 2; |
487 | size_u = size_v = size / 4; | |
488 | } else { | |
a5462e5b MR |
489 | size_y = size; |
490 | } | |
491 | ||
37f5aefd | 492 | sg = dma->sglist; |
3bc43840 | 493 | |
37f5aefd RJ |
494 | /* init DMA for Y channel */ |
495 | ret = pxa_init_dma_channel(pcdev, buf, dma, 0, CIBR0, size_y, | |
496 | &sg, &next_ofs); | |
a5462e5b | 497 | if (ret) { |
979ea1dd | 498 | dev_err(dev, "DMA initialization for Y/RGB failed\n"); |
3bc43840 GL |
499 | goto fail; |
500 | } | |
501 | ||
37f5aefd RJ |
502 | /* init DMA for U channel */ |
503 | if (size_u) | |
504 | ret = pxa_init_dma_channel(pcdev, buf, dma, 1, CIBR1, | |
505 | size_u, &sg, &next_ofs); | |
506 | if (ret) { | |
979ea1dd | 507 | dev_err(dev, "DMA initialization for U failed\n"); |
8f4895f2 | 508 | goto fail; |
37f5aefd RJ |
509 | } |
510 | ||
511 | /* init DMA for V channel */ | |
512 | if (size_v) | |
513 | ret = pxa_init_dma_channel(pcdev, buf, dma, 2, CIBR2, | |
514 | size_v, &sg, &next_ofs); | |
515 | if (ret) { | |
979ea1dd | 516 | dev_err(dev, "DMA initialization for V failed\n"); |
8f4895f2 | 517 | goto fail; |
3bc43840 | 518 | } |
3bc43840 GL |
519 | |
520 | vb->state = VIDEOBUF_PREPARED; | |
521 | } | |
522 | ||
523 | buf->inwork = 0; | |
256b0233 | 524 | pxa_videobuf_set_actdma(pcdev, buf); |
3bc43840 GL |
525 | |
526 | return 0; | |
527 | ||
528 | fail: | |
529 | free_buffer(vq, buf); | |
530 | out: | |
531 | buf->inwork = 0; | |
532 | return ret; | |
533 | } | |
534 | ||
256b0233 RJ |
535 | /** |
536 | * pxa_dma_start_channels - start DMA channel for active buffer | |
537 | * @pcdev: pxa camera device | |
538 | * | |
539 | * Initialize DMA channels to the beginning of the active video buffer, and | |
540 | * start these channels. | |
541 | */ | |
542 | static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev) | |
543 | { | |
544 | int i; | |
545 | struct pxa_buffer *active; | |
546 | ||
547 | active = pcdev->active; | |
548 | ||
549 | for (i = 0; i < pcdev->channels; i++) { | |
0166b743 GL |
550 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, |
551 | "%s (channel=%d) ddadr=%08x\n", __func__, | |
256b0233 RJ |
552 | i, active->dmas[i].sg_dma); |
553 | DDADR(pcdev->dma_chans[i]) = active->dmas[i].sg_dma; | |
554 | DCSR(pcdev->dma_chans[i]) = DCSR_RUN; | |
555 | } | |
556 | } | |
557 | ||
558 | static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev) | |
559 | { | |
560 | int i; | |
561 | ||
562 | for (i = 0; i < pcdev->channels; i++) { | |
0166b743 GL |
563 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, |
564 | "%s (channel=%d)\n", __func__, i); | |
256b0233 RJ |
565 | DCSR(pcdev->dma_chans[i]) = 0; |
566 | } | |
567 | } | |
568 | ||
256b0233 RJ |
569 | static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev, |
570 | struct pxa_buffer *buf) | |
571 | { | |
572 | int i; | |
573 | struct pxa_dma_desc *buf_last_desc; | |
574 | ||
575 | for (i = 0; i < pcdev->channels; i++) { | |
576 | buf_last_desc = buf->dmas[i].sg_cpu + buf->dmas[i].sglen; | |
577 | buf_last_desc->ddadr = DDADR_STOP; | |
578 | ||
ae7410e7 GL |
579 | if (pcdev->sg_tail[i]) |
580 | /* Link the new buffer to the old tail */ | |
581 | pcdev->sg_tail[i]->ddadr = buf->dmas[i].sg_dma; | |
256b0233 | 582 | |
ae7410e7 GL |
583 | /* Update the channel tail */ |
584 | pcdev->sg_tail[i] = buf_last_desc; | |
585 | } | |
256b0233 RJ |
586 | } |
587 | ||
588 | /** | |
589 | * pxa_camera_start_capture - start video capturing | |
590 | * @pcdev: camera device | |
591 | * | |
592 | * Launch capturing. DMA channels should not be active yet. They should get | |
593 | * activated at the end of frame interrupt, to capture only whole frames, and | |
594 | * never begin the capture of a partial frame. | |
595 | */ | |
596 | static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev) | |
597 | { | |
a47f6be4 | 598 | unsigned long cicr0; |
256b0233 | 599 | |
979ea1dd | 600 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__); |
e623ebe6 | 601 | __raw_writel(__raw_readl(pcdev->base + CISR), pcdev->base + CISR); |
256b0233 RJ |
602 | /* Enable End-Of-Frame Interrupt */ |
603 | cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB; | |
604 | cicr0 &= ~CICR0_EOFM; | |
605 | __raw_writel(cicr0, pcdev->base + CICR0); | |
606 | } | |
607 | ||
608 | static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev) | |
609 | { | |
610 | unsigned long cicr0; | |
611 | ||
612 | pxa_dma_stop_channels(pcdev); | |
613 | ||
614 | cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB; | |
615 | __raw_writel(cicr0, pcdev->base + CICR0); | |
616 | ||
8c62e221 | 617 | pcdev->active = NULL; |
979ea1dd | 618 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__); |
256b0233 RJ |
619 | } |
620 | ||
2dd54a54 | 621 | /* Called under spinlock_irqsave(&pcdev->lock, ...) */ |
7102b773 GL |
622 | static void pxa_videobuf_queue(struct videobuf_queue *vq, |
623 | struct videobuf_buffer *vb) | |
3bc43840 GL |
624 | { |
625 | struct soc_camera_device *icd = vq->priv_data; | |
7dfff953 | 626 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
3bc43840 GL |
627 | struct pxa_camera_dev *pcdev = ici->priv; |
628 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); | |
3bc43840 | 629 | |
7dfff953 | 630 | dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d active=%p\n", |
0166b743 | 631 | __func__, vb, vb->baddr, vb->bsize, pcdev->active); |
256b0233 | 632 | |
3bc43840 GL |
633 | list_add_tail(&vb->queue, &pcdev->capture); |
634 | ||
635 | vb->state = VIDEOBUF_ACTIVE; | |
256b0233 | 636 | pxa_dma_add_tail_buf(pcdev, buf); |
3bc43840 | 637 | |
256b0233 RJ |
638 | if (!pcdev->active) |
639 | pxa_camera_start_capture(pcdev); | |
3bc43840 GL |
640 | } |
641 | ||
642 | static void pxa_videobuf_release(struct videobuf_queue *vq, | |
643 | struct videobuf_buffer *vb) | |
644 | { | |
645 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); | |
646 | #ifdef DEBUG | |
647 | struct soc_camera_device *icd = vq->priv_data; | |
7dfff953 | 648 | struct device *dev = icd->parent; |
3bc43840 | 649 | |
0166b743 | 650 | dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
651 | vb, vb->baddr, vb->bsize); |
652 | ||
653 | switch (vb->state) { | |
654 | case VIDEOBUF_ACTIVE: | |
0166b743 | 655 | dev_dbg(dev, "%s (active)\n", __func__); |
3bc43840 GL |
656 | break; |
657 | case VIDEOBUF_QUEUED: | |
0166b743 | 658 | dev_dbg(dev, "%s (queued)\n", __func__); |
3bc43840 GL |
659 | break; |
660 | case VIDEOBUF_PREPARED: | |
0166b743 | 661 | dev_dbg(dev, "%s (prepared)\n", __func__); |
3bc43840 GL |
662 | break; |
663 | default: | |
0166b743 | 664 | dev_dbg(dev, "%s (unknown)\n", __func__); |
3bc43840 GL |
665 | break; |
666 | } | |
667 | #endif | |
668 | ||
669 | free_buffer(vq, buf); | |
670 | } | |
671 | ||
a5462e5b MR |
672 | static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev, |
673 | struct videobuf_buffer *vb, | |
674 | struct pxa_buffer *buf) | |
675 | { | |
256b0233 | 676 | int i; |
5ca11fa3 | 677 | |
a5462e5b MR |
678 | /* _init is used to debug races, see comment in pxa_camera_reqbufs() */ |
679 | list_del_init(&vb->queue); | |
680 | vb->state = VIDEOBUF_DONE; | |
8e6057b5 | 681 | v4l2_get_timestamp(&vb->ts); |
a5462e5b MR |
682 | vb->field_count++; |
683 | wake_up(&vb->done); | |
979ea1dd GL |
684 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s dequeud buffer (vb=0x%p)\n", |
685 | __func__, vb); | |
a5462e5b MR |
686 | |
687 | if (list_empty(&pcdev->capture)) { | |
256b0233 | 688 | pxa_camera_stop_capture(pcdev); |
256b0233 RJ |
689 | for (i = 0; i < pcdev->channels; i++) |
690 | pcdev->sg_tail[i] = NULL; | |
a5462e5b MR |
691 | return; |
692 | } | |
693 | ||
694 | pcdev->active = list_entry(pcdev->capture.next, | |
695 | struct pxa_buffer, vb.queue); | |
696 | } | |
697 | ||
256b0233 RJ |
698 | /** |
699 | * pxa_camera_check_link_miss - check missed DMA linking | |
700 | * @pcdev: camera device | |
701 | * | |
702 | * The DMA chaining is done with DMA running. This means a tiny temporal window | |
703 | * remains, where a buffer is queued on the chain, while the chain is already | |
25985edc | 704 | * stopped. This means the tailed buffer would never be transferred by DMA. |
256b0233 RJ |
705 | * This function restarts the capture for this corner case, where : |
706 | * - DADR() == DADDR_STOP | |
707 | * - a videobuffer is queued on the pcdev->capture list | |
708 | * | |
709 | * Please check the "DMA hot chaining timeslice issue" in | |
710 | * Documentation/video4linux/pxa_camera.txt | |
711 | * | |
712 | * Context: should only be called within the dma irq handler | |
713 | */ | |
714 | static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev) | |
715 | { | |
716 | int i, is_dma_stopped = 1; | |
717 | ||
718 | for (i = 0; i < pcdev->channels; i++) | |
719 | if (DDADR(pcdev->dma_chans[i]) != DDADR_STOP) | |
720 | is_dma_stopped = 0; | |
979ea1dd GL |
721 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, |
722 | "%s : top queued buffer=%p, dma_stopped=%d\n", | |
256b0233 RJ |
723 | __func__, pcdev->active, is_dma_stopped); |
724 | if (pcdev->active && is_dma_stopped) | |
725 | pxa_camera_start_capture(pcdev); | |
726 | } | |
727 | ||
a5462e5b MR |
728 | static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev, |
729 | enum pxa_camera_active_dma act_dma) | |
3bc43840 | 730 | { |
979ea1dd | 731 | struct device *dev = pcdev->soc_host.v4l2_dev.dev; |
3bc43840 GL |
732 | struct pxa_buffer *buf; |
733 | unsigned long flags; | |
e7c50688 | 734 | u32 status, camera_status, overrun; |
3bc43840 GL |
735 | struct videobuf_buffer *vb; |
736 | ||
737 | spin_lock_irqsave(&pcdev->lock, flags); | |
738 | ||
a5462e5b | 739 | status = DCSR(channel); |
256b0233 RJ |
740 | DCSR(channel) = status; |
741 | ||
742 | camera_status = __raw_readl(pcdev->base + CISR); | |
743 | overrun = CISR_IFO_0; | |
744 | if (pcdev->channels == 3) | |
745 | overrun |= CISR_IFO_1 | CISR_IFO_2; | |
7102b773 | 746 | |
3bc43840 | 747 | if (status & DCSR_BUSERR) { |
979ea1dd | 748 | dev_err(dev, "DMA Bus Error IRQ!\n"); |
3bc43840 GL |
749 | goto out; |
750 | } | |
751 | ||
256b0233 | 752 | if (!(status & (DCSR_ENDINTR | DCSR_STARTINTR))) { |
979ea1dd GL |
753 | dev_err(dev, "Unknown DMA IRQ source, status: 0x%08x\n", |
754 | status); | |
3bc43840 GL |
755 | goto out; |
756 | } | |
757 | ||
8c62e221 RJ |
758 | /* |
759 | * pcdev->active should not be NULL in DMA irq handler. | |
760 | * | |
761 | * But there is one corner case : if capture was stopped due to an | |
762 | * overrun of channel 1, and at that same channel 2 was completed. | |
763 | * | |
764 | * When handling the overrun in DMA irq for channel 1, we'll stop the | |
765 | * capture and restart it (and thus set pcdev->active to NULL). But the | |
766 | * DMA irq handler will already be pending for channel 2. So on entering | |
767 | * the DMA irq handler for channel 2 there will be no active buffer, yet | |
768 | * that is normal. | |
769 | */ | |
770 | if (!pcdev->active) | |
3bc43840 | 771 | goto out; |
3bc43840 GL |
772 | |
773 | vb = &pcdev->active->vb; | |
774 | buf = container_of(vb, struct pxa_buffer, vb); | |
775 | WARN_ON(buf->inwork || list_empty(&vb->queue)); | |
3bc43840 | 776 | |
979ea1dd | 777 | dev_dbg(dev, "%s channel=%d %s%s(vb=0x%p) dma.desc=%x\n", |
256b0233 RJ |
778 | __func__, channel, status & DCSR_STARTINTR ? "SOF " : "", |
779 | status & DCSR_ENDINTR ? "EOF " : "", vb, DDADR(channel)); | |
780 | ||
781 | if (status & DCSR_ENDINTR) { | |
8c62e221 RJ |
782 | /* |
783 | * It's normal if the last frame creates an overrun, as there | |
784 | * are no more DMA descriptors to fetch from QCI fifos | |
785 | */ | |
786 | if (camera_status & overrun && | |
787 | !list_is_last(pcdev->capture.next, &pcdev->capture)) { | |
979ea1dd | 788 | dev_dbg(dev, "FIFO overrun! CISR: %x\n", |
256b0233 RJ |
789 | camera_status); |
790 | pxa_camera_stop_capture(pcdev); | |
791 | pxa_camera_start_capture(pcdev); | |
792 | goto out; | |
793 | } | |
794 | buf->active_dma &= ~act_dma; | |
795 | if (!buf->active_dma) { | |
796 | pxa_camera_wakeup(pcdev, vb, buf); | |
797 | pxa_camera_check_link_miss(pcdev); | |
798 | } | |
799 | } | |
3bc43840 GL |
800 | |
801 | out: | |
802 | spin_unlock_irqrestore(&pcdev->lock, flags); | |
803 | } | |
804 | ||
a5462e5b MR |
805 | static void pxa_camera_dma_irq_y(int channel, void *data) |
806 | { | |
807 | struct pxa_camera_dev *pcdev = data; | |
808 | pxa_camera_dma_irq(channel, pcdev, DMA_Y); | |
809 | } | |
810 | ||
811 | static void pxa_camera_dma_irq_u(int channel, void *data) | |
812 | { | |
813 | struct pxa_camera_dev *pcdev = data; | |
814 | pxa_camera_dma_irq(channel, pcdev, DMA_U); | |
815 | } | |
816 | ||
817 | static void pxa_camera_dma_irq_v(int channel, void *data) | |
818 | { | |
819 | struct pxa_camera_dev *pcdev = data; | |
820 | pxa_camera_dma_irq(channel, pcdev, DMA_V); | |
821 | } | |
822 | ||
7102b773 | 823 | static struct videobuf_queue_ops pxa_videobuf_ops = { |
3bc43840 GL |
824 | .buf_setup = pxa_videobuf_setup, |
825 | .buf_prepare = pxa_videobuf_prepare, | |
826 | .buf_queue = pxa_videobuf_queue, | |
827 | .buf_release = pxa_videobuf_release, | |
828 | }; | |
829 | ||
a034d1b7 | 830 | static void pxa_camera_init_videobuf(struct videobuf_queue *q, |
092d3921 PZ |
831 | struct soc_camera_device *icd) |
832 | { | |
7dfff953 | 833 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
a034d1b7 MD |
834 | struct pxa_camera_dev *pcdev = ici->priv; |
835 | ||
5d28d525 GL |
836 | /* |
837 | * We must pass NULL as dev pointer, then all pci_* dma operations | |
838 | * transform to normal dma_* ones. | |
839 | */ | |
a034d1b7 | 840 | videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock, |
092d3921 | 841 | V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE, |
47ebe3f9 | 842 | sizeof(struct pxa_buffer), icd, &ici->host_lock); |
092d3921 PZ |
843 | } |
844 | ||
40e2e092 GL |
845 | static u32 mclk_get_divisor(struct platform_device *pdev, |
846 | struct pxa_camera_dev *pcdev) | |
3bc43840 | 847 | { |
cf34cba7 | 848 | unsigned long mclk = pcdev->mclk; |
6a6c8786 | 849 | struct device *dev = &pdev->dev; |
cf34cba7 | 850 | u32 div; |
3bc43840 GL |
851 | unsigned long lcdclk; |
852 | ||
cf34cba7 GL |
853 | lcdclk = clk_get_rate(pcdev->clk); |
854 | pcdev->ciclk = lcdclk; | |
3bc43840 | 855 | |
cf34cba7 GL |
856 | /* mclk <= ciclk / 4 (27.4.2) */ |
857 | if (mclk > lcdclk / 4) { | |
858 | mclk = lcdclk / 4; | |
979ea1dd | 859 | dev_warn(dev, "Limiting master clock to %lu\n", mclk); |
cf34cba7 GL |
860 | } |
861 | ||
862 | /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */ | |
863 | div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1; | |
3bc43840 | 864 | |
cf34cba7 GL |
865 | /* If we're not supplying MCLK, leave it at 0 */ |
866 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
867 | pcdev->mclk = lcdclk / (2 * (div + 1)); | |
3bc43840 | 868 | |
979ea1dd | 869 | dev_dbg(dev, "LCD clock %luHz, target freq %luHz, divisor %u\n", |
40e2e092 | 870 | lcdclk, mclk, div); |
3bc43840 GL |
871 | |
872 | return div; | |
873 | } | |
874 | ||
cf34cba7 GL |
875 | static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev, |
876 | unsigned long pclk) | |
877 | { | |
878 | /* We want a timeout > 1 pixel time, not ">=" */ | |
879 | u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1; | |
880 | ||
881 | __raw_writel(ciclk_per_pixel, pcdev->base + CITOR); | |
882 | } | |
883 | ||
7102b773 | 884 | static void pxa_camera_activate(struct pxa_camera_dev *pcdev) |
3bc43840 | 885 | { |
3bc43840 GL |
886 | u32 cicr4 = 0; |
887 | ||
5ca11fa3 EM |
888 | /* disable all interrupts */ |
889 | __raw_writel(0x3ff, pcdev->base + CICR0); | |
3bc43840 GL |
890 | |
891 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
892 | cicr4 |= CICR4_PCLK_EN; | |
893 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
894 | cicr4 |= CICR4_MCLK_EN; | |
895 | if (pcdev->platform_flags & PXA_CAMERA_PCP) | |
896 | cicr4 |= CICR4_PCP; | |
897 | if (pcdev->platform_flags & PXA_CAMERA_HSP) | |
898 | cicr4 |= CICR4_HSP; | |
899 | if (pcdev->platform_flags & PXA_CAMERA_VSP) | |
900 | cicr4 |= CICR4_VSP; | |
901 | ||
cf34cba7 GL |
902 | __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4); |
903 | ||
904 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
905 | /* Initialise the timeout under the assumption pclk = mclk */ | |
906 | recalculate_fifo_timeout(pcdev, pcdev->mclk); | |
907 | else | |
908 | /* "Safe default" - 13MHz */ | |
909 | recalculate_fifo_timeout(pcdev, 13000000); | |
3bc43840 | 910 | |
91acd962 | 911 | clk_prepare_enable(pcdev->clk); |
3bc43840 GL |
912 | } |
913 | ||
7102b773 | 914 | static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev) |
3bc43840 | 915 | { |
91acd962 | 916 | clk_disable_unprepare(pcdev->clk); |
3bc43840 GL |
917 | } |
918 | ||
e623ebe6 | 919 | static void pxa_camera_eof(unsigned long arg) |
3bc43840 | 920 | { |
e623ebe6 RJ |
921 | struct pxa_camera_dev *pcdev = (struct pxa_camera_dev *)arg; |
922 | unsigned long cifr; | |
256b0233 RJ |
923 | struct pxa_buffer *buf; |
924 | struct videobuf_buffer *vb; | |
3bc43840 | 925 | |
e623ebe6 RJ |
926 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, |
927 | "Camera interrupt status 0x%x\n", | |
928 | __raw_readl(pcdev->base + CISR)); | |
929 | ||
930 | /* Reset the FIFOs */ | |
931 | cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F; | |
932 | __raw_writel(cifr, pcdev->base + CIFR); | |
933 | ||
934 | pcdev->active = list_first_entry(&pcdev->capture, | |
935 | struct pxa_buffer, vb.queue); | |
936 | vb = &pcdev->active->vb; | |
937 | buf = container_of(vb, struct pxa_buffer, vb); | |
938 | pxa_videobuf_set_actdma(pcdev, buf); | |
939 | ||
940 | pxa_dma_start_channels(pcdev); | |
941 | } | |
942 | ||
943 | static irqreturn_t pxa_camera_irq(int irq, void *data) | |
944 | { | |
945 | struct pxa_camera_dev *pcdev = data; | |
946 | unsigned long status, cicr0; | |
947 | ||
5ca11fa3 | 948 | status = __raw_readl(pcdev->base + CISR); |
0166b743 GL |
949 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, |
950 | "Camera interrupt status 0x%lx\n", status); | |
3bc43840 | 951 | |
e7c50688 GL |
952 | if (!status) |
953 | return IRQ_NONE; | |
954 | ||
5ca11fa3 | 955 | __raw_writel(status, pcdev->base + CISR); |
e7c50688 GL |
956 | |
957 | if (status & CISR_EOF) { | |
5ca11fa3 EM |
958 | cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM; |
959 | __raw_writel(cicr0, pcdev->base + CICR0); | |
e623ebe6 | 960 | tasklet_schedule(&pcdev->task_eof); |
e7c50688 GL |
961 | } |
962 | ||
3bc43840 GL |
963 | return IRQ_HANDLED; |
964 | } | |
965 | ||
39b553db GL |
966 | static int pxa_camera_add_device(struct soc_camera_device *icd) |
967 | { | |
968 | dev_info(icd->parent, "PXA Camera driver attached to camera %d\n", | |
969 | icd->devnum); | |
970 | ||
971 | return 0; | |
972 | } | |
973 | ||
974 | static void pxa_camera_remove_device(struct soc_camera_device *icd) | |
975 | { | |
976 | dev_info(icd->parent, "PXA Camera driver detached from camera %d\n", | |
977 | icd->devnum); | |
978 | } | |
979 | ||
1c3bb743 GL |
980 | /* |
981 | * The following two functions absolutely depend on the fact, that | |
982 | * there can be only one camera on PXA quick capture interface | |
dd669e90 | 983 | * Called with .host_lock held |
1c3bb743 | 984 | */ |
39b553db | 985 | static int pxa_camera_clock_start(struct soc_camera_host *ici) |
3bc43840 | 986 | { |
3bc43840 | 987 | struct pxa_camera_dev *pcdev = ici->priv; |
3bc43840 | 988 | |
7102b773 | 989 | pxa_camera_activate(pcdev); |
40e2e092 | 990 | |
40e2e092 | 991 | return 0; |
3bc43840 GL |
992 | } |
993 | ||
dd669e90 | 994 | /* Called with .host_lock held */ |
39b553db | 995 | static void pxa_camera_clock_stop(struct soc_camera_host *ici) |
3bc43840 | 996 | { |
3bc43840 GL |
997 | struct pxa_camera_dev *pcdev = ici->priv; |
998 | ||
3bc43840 | 999 | /* disable capture, disable interrupts */ |
5ca11fa3 | 1000 | __raw_writel(0x3ff, pcdev->base + CICR0); |
a5462e5b | 1001 | |
3bc43840 | 1002 | /* Stop DMA engine */ |
a5462e5b MR |
1003 | DCSR(pcdev->dma_chans[0]) = 0; |
1004 | DCSR(pcdev->dma_chans[1]) = 0; | |
1005 | DCSR(pcdev->dma_chans[2]) = 0; | |
3bc43840 | 1006 | |
7102b773 | 1007 | pxa_camera_deactivate(pcdev); |
3bc43840 GL |
1008 | } |
1009 | ||
ad5f2e85 GL |
1010 | static int test_platform_param(struct pxa_camera_dev *pcdev, |
1011 | unsigned char buswidth, unsigned long *flags) | |
3bc43840 | 1012 | { |
ad5f2e85 GL |
1013 | /* |
1014 | * Platform specified synchronization and pixel clock polarities are | |
1015 | * only a recommendation and are only used during probing. The PXA270 | |
1016 | * quick capture interface supports both. | |
1017 | */ | |
1018 | *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ? | |
679419aa GL |
1019 | V4L2_MBUS_MASTER : V4L2_MBUS_SLAVE) | |
1020 | V4L2_MBUS_HSYNC_ACTIVE_HIGH | | |
1021 | V4L2_MBUS_HSYNC_ACTIVE_LOW | | |
1022 | V4L2_MBUS_VSYNC_ACTIVE_HIGH | | |
1023 | V4L2_MBUS_VSYNC_ACTIVE_LOW | | |
1024 | V4L2_MBUS_DATA_ACTIVE_HIGH | | |
1025 | V4L2_MBUS_PCLK_SAMPLE_RISING | | |
1026 | V4L2_MBUS_PCLK_SAMPLE_FALLING; | |
3bc43840 GL |
1027 | |
1028 | /* If requested data width is supported by the platform, use it */ | |
679419aa GL |
1029 | if ((1 << (buswidth - 1)) & pcdev->width_flags) |
1030 | return 0; | |
ad5f2e85 | 1031 | |
679419aa | 1032 | return -EINVAL; |
ad5f2e85 GL |
1033 | } |
1034 | ||
6a6c8786 GL |
1035 | static void pxa_camera_setup_cicr(struct soc_camera_device *icd, |
1036 | unsigned long flags, __u32 pixfmt) | |
ad5f2e85 | 1037 | { |
7dfff953 | 1038 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
ad5f2e85 | 1039 | struct pxa_camera_dev *pcdev = ici->priv; |
32536108 | 1040 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
6a6c8786 | 1041 | unsigned long dw, bpp; |
32536108 GL |
1042 | u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top; |
1043 | int ret = v4l2_subdev_call(sd, sensor, g_skip_top_lines, &y_skip_top); | |
1044 | ||
1045 | if (ret < 0) | |
1046 | y_skip_top = 0; | |
3bc43840 | 1047 | |
5d28d525 GL |
1048 | /* |
1049 | * Datawidth is now guaranteed to be equal to one of the three values. | |
1050 | * We fix bit-per-pixel equal to data-width... | |
1051 | */ | |
679419aa GL |
1052 | switch (icd->current_fmt->host_fmt->bits_per_sample) { |
1053 | case 10: | |
3bc43840 GL |
1054 | dw = 4; |
1055 | bpp = 0x40; | |
1056 | break; | |
679419aa | 1057 | case 9: |
3bc43840 GL |
1058 | dw = 3; |
1059 | bpp = 0x20; | |
1060 | break; | |
1061 | default: | |
5d28d525 GL |
1062 | /* |
1063 | * Actually it can only be 8 now, | |
1064 | * default is just to silence compiler warnings | |
1065 | */ | |
679419aa | 1066 | case 8: |
3bc43840 GL |
1067 | dw = 2; |
1068 | bpp = 0; | |
1069 | } | |
1070 | ||
1071 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
1072 | cicr4 |= CICR4_PCLK_EN; | |
1073 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
1074 | cicr4 |= CICR4_MCLK_EN; | |
679419aa | 1075 | if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) |
3bc43840 | 1076 | cicr4 |= CICR4_PCP; |
679419aa | 1077 | if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) |
3bc43840 | 1078 | cicr4 |= CICR4_HSP; |
679419aa | 1079 | if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) |
3bc43840 GL |
1080 | cicr4 |= CICR4_VSP; |
1081 | ||
5ca11fa3 | 1082 | cicr0 = __raw_readl(pcdev->base + CICR0); |
3bc43840 | 1083 | if (cicr0 & CICR0_ENB) |
5ca11fa3 | 1084 | __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0); |
a5462e5b | 1085 | |
6a6c8786 | 1086 | cicr1 = CICR1_PPL_VAL(icd->user_width - 1) | bpp | dw; |
a5462e5b MR |
1087 | |
1088 | switch (pixfmt) { | |
1089 | case V4L2_PIX_FMT_YUV422P: | |
e7c50688 | 1090 | pcdev->channels = 3; |
a5462e5b | 1091 | cicr1 |= CICR1_YCBCR_F; |
2a48fc73 RJ |
1092 | /* |
1093 | * Normally, pxa bus wants as input UYVY format. We allow all | |
1094 | * reorderings of the YUV422 format, as no processing is done, | |
1095 | * and the YUV stream is just passed through without any | |
1096 | * transformation. Note that UYVY is the only format that | |
1097 | * should be used if pxa framebuffer Overlay2 is used. | |
1098 | */ | |
1099 | case V4L2_PIX_FMT_UYVY: | |
1100 | case V4L2_PIX_FMT_VYUY: | |
a5462e5b | 1101 | case V4L2_PIX_FMT_YUYV: |
2a48fc73 | 1102 | case V4L2_PIX_FMT_YVYU: |
a5462e5b MR |
1103 | cicr1 |= CICR1_COLOR_SP_VAL(2); |
1104 | break; | |
1105 | case V4L2_PIX_FMT_RGB555: | |
1106 | cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) | | |
1107 | CICR1_TBIT | CICR1_COLOR_SP_VAL(1); | |
1108 | break; | |
1109 | case V4L2_PIX_FMT_RGB565: | |
1110 | cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2); | |
1111 | break; | |
1112 | } | |
1113 | ||
5ca11fa3 | 1114 | cicr2 = 0; |
6a6c8786 | 1115 | cicr3 = CICR3_LPF_VAL(icd->user_height - 1) | |
32536108 | 1116 | CICR3_BFW_VAL(min((u32)255, y_skip_top)); |
cf34cba7 | 1117 | cicr4 |= pcdev->mclk_divisor; |
5ca11fa3 EM |
1118 | |
1119 | __raw_writel(cicr1, pcdev->base + CICR1); | |
1120 | __raw_writel(cicr2, pcdev->base + CICR2); | |
1121 | __raw_writel(cicr3, pcdev->base + CICR3); | |
1122 | __raw_writel(cicr4, pcdev->base + CICR4); | |
3bc43840 GL |
1123 | |
1124 | /* CIF interrupts are not used, only DMA */ | |
5ca11fa3 EM |
1125 | cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ? |
1126 | CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP)); | |
1127 | cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK; | |
1128 | __raw_writel(cicr0, pcdev->base + CICR0); | |
6a6c8786 GL |
1129 | } |
1130 | ||
8843d119 | 1131 | static int pxa_camera_set_bus_param(struct soc_camera_device *icd) |
6a6c8786 | 1132 | { |
679419aa | 1133 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
7dfff953 | 1134 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
6a6c8786 | 1135 | struct pxa_camera_dev *pcdev = ici->priv; |
679419aa | 1136 | struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,}; |
8843d119 | 1137 | u32 pixfmt = icd->current_fmt->host_fmt->fourcc; |
679419aa | 1138 | unsigned long bus_flags, common_flags; |
760697be | 1139 | int ret; |
6a6c8786 GL |
1140 | struct pxa_cam *cam = icd->host_priv; |
1141 | ||
d2dcad49 GL |
1142 | ret = test_platform_param(pcdev, icd->current_fmt->host_fmt->bits_per_sample, |
1143 | &bus_flags); | |
6a6c8786 GL |
1144 | if (ret < 0) |
1145 | return ret; | |
1146 | ||
679419aa GL |
1147 | ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg); |
1148 | if (!ret) { | |
1149 | common_flags = soc_mbus_config_compatible(&cfg, | |
1150 | bus_flags); | |
1151 | if (!common_flags) { | |
1152 | dev_warn(icd->parent, | |
1153 | "Flags incompatible: camera 0x%x, host 0x%lx\n", | |
1154 | cfg.flags, bus_flags); | |
1155 | return -EINVAL; | |
1156 | } | |
1157 | } else if (ret != -ENOIOCTLCMD) { | |
1158 | return ret; | |
1159 | } else { | |
1160 | common_flags = bus_flags; | |
1161 | } | |
6a6c8786 GL |
1162 | |
1163 | pcdev->channels = 1; | |
1164 | ||
1165 | /* Make choises, based on platform preferences */ | |
679419aa GL |
1166 | if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) && |
1167 | (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) { | |
6a6c8786 | 1168 | if (pcdev->platform_flags & PXA_CAMERA_HSP) |
679419aa | 1169 | common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH; |
6a6c8786 | 1170 | else |
679419aa | 1171 | common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW; |
6a6c8786 GL |
1172 | } |
1173 | ||
679419aa GL |
1174 | if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) && |
1175 | (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) { | |
6a6c8786 | 1176 | if (pcdev->platform_flags & PXA_CAMERA_VSP) |
679419aa | 1177 | common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH; |
6a6c8786 | 1178 | else |
679419aa | 1179 | common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW; |
6a6c8786 GL |
1180 | } |
1181 | ||
679419aa GL |
1182 | if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) && |
1183 | (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) { | |
6a6c8786 | 1184 | if (pcdev->platform_flags & PXA_CAMERA_PCP) |
679419aa | 1185 | common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING; |
6a6c8786 | 1186 | else |
679419aa | 1187 | common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING; |
6a6c8786 GL |
1188 | } |
1189 | ||
679419aa GL |
1190 | cfg.flags = common_flags; |
1191 | ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg); | |
1192 | if (ret < 0 && ret != -ENOIOCTLCMD) { | |
1193 | dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n", | |
1194 | common_flags, ret); | |
6a6c8786 | 1195 | return ret; |
679419aa GL |
1196 | } |
1197 | ||
1198 | cam->flags = common_flags; | |
6a6c8786 GL |
1199 | |
1200 | pxa_camera_setup_cicr(icd, common_flags, pixfmt); | |
3bc43840 GL |
1201 | |
1202 | return 0; | |
1203 | } | |
1204 | ||
2a48fc73 RJ |
1205 | static int pxa_camera_try_bus_param(struct soc_camera_device *icd, |
1206 | unsigned char buswidth) | |
ad5f2e85 | 1207 | { |
679419aa | 1208 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
7dfff953 | 1209 | struct soc_camera_host *ici = to_soc_camera_host(icd->parent); |
ad5f2e85 | 1210 | struct pxa_camera_dev *pcdev = ici->priv; |
679419aa GL |
1211 | struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,}; |
1212 | unsigned long bus_flags, common_flags; | |
2a48fc73 | 1213 | int ret = test_platform_param(pcdev, buswidth, &bus_flags); |
ad5f2e85 GL |
1214 | |
1215 | if (ret < 0) | |
1216 | return ret; | |
1217 | ||
679419aa GL |
1218 | ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg); |
1219 | if (!ret) { | |
1220 | common_flags = soc_mbus_config_compatible(&cfg, | |
1221 | bus_flags); | |
1222 | if (!common_flags) { | |
1223 | dev_warn(icd->parent, | |
1224 | "Flags incompatible: camera 0x%x, host 0x%lx\n", | |
1225 | cfg.flags, bus_flags); | |
1226 | return -EINVAL; | |
1227 | } | |
1228 | } else if (ret == -ENOIOCTLCMD) { | |
1229 | ret = 0; | |
1230 | } | |
ad5f2e85 | 1231 | |
679419aa | 1232 | return ret; |
ad5f2e85 GL |
1233 | } |
1234 | ||
760697be | 1235 | static const struct soc_mbus_pixelfmt pxa_camera_formats[] = { |
2a48fc73 | 1236 | { |
760697be GL |
1237 | .fourcc = V4L2_PIX_FMT_YUV422P, |
1238 | .name = "Planar YUV422 16 bit", | |
1239 | .bits_per_sample = 8, | |
1240 | .packing = SOC_MBUS_PACKING_2X8_PADHI, | |
1241 | .order = SOC_MBUS_ORDER_LE, | |
ad3b81fa | 1242 | .layout = SOC_MBUS_LAYOUT_PLANAR_2Y_U_V, |
2a48fc73 RJ |
1243 | }, |
1244 | }; | |
1245 | ||
760697be GL |
1246 | /* This will be corrected as we get more formats */ |
1247 | static bool pxa_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt) | |
ad5f2e85 | 1248 | { |
760697be GL |
1249 | return fmt->packing == SOC_MBUS_PACKING_NONE || |
1250 | (fmt->bits_per_sample == 8 && | |
1251 | fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) || | |
1252 | (fmt->bits_per_sample > 8 && | |
1253 | fmt->packing == SOC_MBUS_PACKING_EXTEND16); | |
2a48fc73 RJ |
1254 | } |
1255 | ||
3805f201 | 1256 | static int pxa_camera_get_formats(struct soc_camera_device *icd, unsigned int idx, |
2a48fc73 RJ |
1257 | struct soc_camera_format_xlate *xlate) |
1258 | { | |
760697be | 1259 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
7dfff953 | 1260 | struct device *dev = icd->parent; |
760697be | 1261 | int formats = 0, ret; |
6a6c8786 | 1262 | struct pxa_cam *cam; |
ebcff5fc HV |
1263 | struct v4l2_subdev_mbus_code_enum code = { |
1264 | .which = V4L2_SUBDEV_FORMAT_ACTIVE, | |
1265 | .index = idx, | |
1266 | }; | |
760697be | 1267 | const struct soc_mbus_pixelfmt *fmt; |
2a48fc73 | 1268 | |
ebcff5fc | 1269 | ret = v4l2_subdev_call(sd, pad, enum_mbus_code, NULL, &code); |
760697be GL |
1270 | if (ret < 0) |
1271 | /* No more formats */ | |
1272 | return 0; | |
2a48fc73 | 1273 | |
ebcff5fc | 1274 | fmt = soc_mbus_get_fmtdesc(code.code); |
760697be | 1275 | if (!fmt) { |
ebcff5fc | 1276 | dev_err(dev, "Invalid format code #%u: %d\n", idx, code.code); |
2a48fc73 | 1277 | return 0; |
760697be | 1278 | } |
3bc43840 | 1279 | |
760697be GL |
1280 | /* This also checks support for the requested bits-per-sample */ |
1281 | ret = pxa_camera_try_bus_param(icd, fmt->bits_per_sample); | |
2a48fc73 RJ |
1282 | if (ret < 0) |
1283 | return 0; | |
1284 | ||
6a6c8786 GL |
1285 | if (!icd->host_priv) { |
1286 | cam = kzalloc(sizeof(*cam), GFP_KERNEL); | |
1287 | if (!cam) | |
1288 | return -ENOMEM; | |
1289 | ||
1290 | icd->host_priv = cam; | |
1291 | } else { | |
1292 | cam = icd->host_priv; | |
1293 | } | |
1294 | ||
ebcff5fc | 1295 | switch (code.code) { |
27ffaeb0 | 1296 | case MEDIA_BUS_FMT_UYVY8_2X8: |
2a48fc73 RJ |
1297 | formats++; |
1298 | if (xlate) { | |
760697be | 1299 | xlate->host_fmt = &pxa_camera_formats[0]; |
ebcff5fc | 1300 | xlate->code = code.code; |
2a48fc73 | 1301 | xlate++; |
760697be | 1302 | dev_dbg(dev, "Providing format %s using code %d\n", |
ebcff5fc | 1303 | pxa_camera_formats[0].name, code.code); |
2a48fc73 | 1304 | } |
27ffaeb0 BB |
1305 | case MEDIA_BUS_FMT_VYUY8_2X8: |
1306 | case MEDIA_BUS_FMT_YUYV8_2X8: | |
1307 | case MEDIA_BUS_FMT_YVYU8_2X8: | |
1308 | case MEDIA_BUS_FMT_RGB565_2X8_LE: | |
1309 | case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE: | |
760697be | 1310 | if (xlate) |
0166b743 | 1311 | dev_dbg(dev, "Providing format %s packed\n", |
760697be | 1312 | fmt->name); |
2a48fc73 RJ |
1313 | break; |
1314 | default: | |
760697be GL |
1315 | if (!pxa_camera_packing_supported(fmt)) |
1316 | return 0; | |
1317 | if (xlate) | |
0166b743 | 1318 | dev_dbg(dev, |
2a48fc73 | 1319 | "Providing format %s in pass-through mode\n", |
760697be GL |
1320 | fmt->name); |
1321 | } | |
1322 | ||
1323 | /* Generic pass-through */ | |
1324 | formats++; | |
1325 | if (xlate) { | |
1326 | xlate->host_fmt = fmt; | |
ebcff5fc | 1327 | xlate->code = code.code; |
760697be | 1328 | xlate++; |
2a48fc73 RJ |
1329 | } |
1330 | ||
1331 | return formats; | |
1332 | } | |
1333 | ||
6a6c8786 GL |
1334 | static void pxa_camera_put_formats(struct soc_camera_device *icd) |
1335 | { | |
1336 | kfree(icd->host_priv); | |
1337 | icd->host_priv = NULL; | |
1338 | } | |
1339 | ||
760697be | 1340 | static int pxa_camera_check_frame(u32 width, u32 height) |
6a6c8786 GL |
1341 | { |
1342 | /* limit to pxa hardware capabilities */ | |
760697be GL |
1343 | return height < 32 || height > 2048 || width < 48 || width > 2048 || |
1344 | (width & 0x01); | |
6a6c8786 GL |
1345 | } |
1346 | ||
09e231b3 | 1347 | static int pxa_camera_set_crop(struct soc_camera_device *icd, |
448a61f0 | 1348 | const struct v4l2_crop *a) |
09e231b3 | 1349 | { |
448a61f0 | 1350 | const struct v4l2_rect *rect = &a->c; |
7dfff953 GL |
1351 | struct device *dev = icd->parent; |
1352 | struct soc_camera_host *ici = to_soc_camera_host(dev); | |
09e231b3 | 1353 | struct pxa_camera_dev *pcdev = ici->priv; |
c9c1f1c0 | 1354 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
09e231b3 GL |
1355 | struct soc_camera_sense sense = { |
1356 | .master_clock = pcdev->mclk, | |
1357 | .pixel_clock_max = pcdev->ciclk / 4, | |
1358 | }; | |
da298c6d HV |
1359 | struct v4l2_subdev_format fmt = { |
1360 | .which = V4L2_SUBDEV_FORMAT_ACTIVE, | |
1361 | }; | |
1362 | struct v4l2_mbus_framefmt *mf = &fmt.format; | |
6a6c8786 | 1363 | struct pxa_cam *cam = icd->host_priv; |
760697be | 1364 | u32 fourcc = icd->current_fmt->host_fmt->fourcc; |
09e231b3 GL |
1365 | int ret; |
1366 | ||
1367 | /* If PCLK is used to latch data from the sensor, check sense */ | |
1368 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
1369 | icd->sense = &sense; | |
1370 | ||
08590b96 | 1371 | ret = v4l2_subdev_call(sd, video, s_crop, a); |
09e231b3 GL |
1372 | |
1373 | icd->sense = NULL; | |
1374 | ||
1375 | if (ret < 0) { | |
0166b743 | 1376 | dev_warn(dev, "Failed to crop to %ux%u@%u:%u\n", |
09e231b3 | 1377 | rect->width, rect->height, rect->left, rect->top); |
6a6c8786 GL |
1378 | return ret; |
1379 | } | |
1380 | ||
da298c6d | 1381 | ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &fmt); |
6a6c8786 GL |
1382 | if (ret < 0) |
1383 | return ret; | |
1384 | ||
da298c6d | 1385 | if (pxa_camera_check_frame(mf->width, mf->height)) { |
6a6c8786 GL |
1386 | /* |
1387 | * Camera cropping produced a frame beyond our capabilities. | |
1388 | * FIXME: just extract a subframe, that we can process. | |
1389 | */ | |
da298c6d HV |
1390 | v4l_bound_align_image(&mf->width, 48, 2048, 1, |
1391 | &mf->height, 32, 2048, 0, | |
760697be | 1392 | fourcc == V4L2_PIX_FMT_YUV422P ? 4 : 0); |
ebf984bb | 1393 | ret = v4l2_subdev_call(sd, pad, set_fmt, NULL, &fmt); |
6a6c8786 GL |
1394 | if (ret < 0) |
1395 | return ret; | |
1396 | ||
da298c6d | 1397 | if (pxa_camera_check_frame(mf->width, mf->height)) { |
7dfff953 | 1398 | dev_warn(icd->parent, |
6a6c8786 GL |
1399 | "Inconsistent state. Use S_FMT to repair\n"); |
1400 | return -EINVAL; | |
1401 | } | |
1402 | } | |
1403 | ||
1404 | if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) { | |
09e231b3 | 1405 | if (sense.pixel_clock > sense.pixel_clock_max) { |
0166b743 | 1406 | dev_err(dev, |
09e231b3 GL |
1407 | "pixel clock %lu set by the camera too high!", |
1408 | sense.pixel_clock); | |
1409 | return -EIO; | |
1410 | } | |
1411 | recalculate_fifo_timeout(pcdev, sense.pixel_clock); | |
1412 | } | |
1413 | ||
da298c6d HV |
1414 | icd->user_width = mf->width; |
1415 | icd->user_height = mf->height; | |
6a6c8786 | 1416 | |
760697be | 1417 | pxa_camera_setup_cicr(icd, cam->flags, fourcc); |
6a6c8786 | 1418 | |
09e231b3 GL |
1419 | return ret; |
1420 | } | |
1421 | ||
d8fac217 | 1422 | static int pxa_camera_set_fmt(struct soc_camera_device *icd, |
09e231b3 | 1423 | struct v4l2_format *f) |
ad5f2e85 | 1424 | { |
7dfff953 GL |
1425 | struct device *dev = icd->parent; |
1426 | struct soc_camera_host *ici = to_soc_camera_host(dev); | |
cf34cba7 | 1427 | struct pxa_camera_dev *pcdev = ici->priv; |
c9c1f1c0 | 1428 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
0ad675eb | 1429 | const struct soc_camera_format_xlate *xlate = NULL; |
cf34cba7 GL |
1430 | struct soc_camera_sense sense = { |
1431 | .master_clock = pcdev->mclk, | |
1432 | .pixel_clock_max = pcdev->ciclk / 4, | |
1433 | }; | |
09e231b3 | 1434 | struct v4l2_pix_format *pix = &f->fmt.pix; |
ebf984bb HV |
1435 | struct v4l2_subdev_format format = { |
1436 | .which = V4L2_SUBDEV_FORMAT_ACTIVE, | |
1437 | }; | |
1438 | struct v4l2_mbus_framefmt *mf = &format.format; | |
0ad675eb | 1439 | int ret; |
25c4d74e | 1440 | |
09e231b3 GL |
1441 | xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); |
1442 | if (!xlate) { | |
0166b743 | 1443 | dev_warn(dev, "Format %x not found\n", pix->pixelformat); |
09e231b3 | 1444 | return -EINVAL; |
0ad675eb | 1445 | } |
2a48fc73 | 1446 | |
cf34cba7 GL |
1447 | /* If PCLK is used to latch data from the sensor, check sense */ |
1448 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
760697be | 1449 | /* The caller holds a mutex. */ |
cf34cba7 GL |
1450 | icd->sense = &sense; |
1451 | ||
ebf984bb HV |
1452 | mf->width = pix->width; |
1453 | mf->height = pix->height; | |
1454 | mf->field = pix->field; | |
1455 | mf->colorspace = pix->colorspace; | |
1456 | mf->code = xlate->code; | |
760697be | 1457 | |
ebf984bb | 1458 | ret = v4l2_subdev_call(sd, pad, set_fmt, NULL, &format); |
760697be | 1459 | |
ebf984bb | 1460 | if (mf->code != xlate->code) |
760697be | 1461 | return -EINVAL; |
2a48fc73 | 1462 | |
cf34cba7 GL |
1463 | icd->sense = NULL; |
1464 | ||
1465 | if (ret < 0) { | |
0166b743 | 1466 | dev_warn(dev, "Failed to configure for format %x\n", |
09e231b3 | 1467 | pix->pixelformat); |
ebf984bb | 1468 | } else if (pxa_camera_check_frame(mf->width, mf->height)) { |
6a6c8786 GL |
1469 | dev_warn(dev, |
1470 | "Camera driver produced an unsupported frame %dx%d\n", | |
ebf984bb | 1471 | mf->width, mf->height); |
6a6c8786 | 1472 | ret = -EINVAL; |
cf34cba7 GL |
1473 | } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) { |
1474 | if (sense.pixel_clock > sense.pixel_clock_max) { | |
0166b743 | 1475 | dev_err(dev, |
cf34cba7 GL |
1476 | "pixel clock %lu set by the camera too high!", |
1477 | sense.pixel_clock); | |
1478 | return -EIO; | |
1479 | } | |
1480 | recalculate_fifo_timeout(pcdev, sense.pixel_clock); | |
1481 | } | |
2a48fc73 | 1482 | |
760697be GL |
1483 | if (ret < 0) |
1484 | return ret; | |
1485 | ||
ebf984bb HV |
1486 | pix->width = mf->width; |
1487 | pix->height = mf->height; | |
1488 | pix->field = mf->field; | |
1489 | pix->colorspace = mf->colorspace; | |
760697be | 1490 | icd->current_fmt = xlate; |
25c4d74e GL |
1491 | |
1492 | return ret; | |
ad5f2e85 GL |
1493 | } |
1494 | ||
d8fac217 GL |
1495 | static int pxa_camera_try_fmt(struct soc_camera_device *icd, |
1496 | struct v4l2_format *f) | |
3bc43840 | 1497 | { |
c9c1f1c0 | 1498 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
2a48fc73 RJ |
1499 | const struct soc_camera_format_xlate *xlate; |
1500 | struct v4l2_pix_format *pix = &f->fmt.pix; | |
5eab4983 HV |
1501 | struct v4l2_subdev_pad_config pad_cfg; |
1502 | struct v4l2_subdev_format format = { | |
1503 | .which = V4L2_SUBDEV_FORMAT_TRY, | |
1504 | }; | |
1505 | struct v4l2_mbus_framefmt *mf = &format.format; | |
2a48fc73 | 1506 | __u32 pixfmt = pix->pixelformat; |
bf507158 | 1507 | int ret; |
a2c8c68c | 1508 | |
2a48fc73 RJ |
1509 | xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); |
1510 | if (!xlate) { | |
7dfff953 | 1511 | dev_warn(icd->parent, "Format %x not found\n", pixfmt); |
25c4d74e | 1512 | return -EINVAL; |
2a48fc73 | 1513 | } |
25c4d74e | 1514 | |
92a8337b | 1515 | /* |
4a6b8df2 TP |
1516 | * Limit to pxa hardware capabilities. YUV422P planar format requires |
1517 | * images size to be a multiple of 16 bytes. If not, zeros will be | |
1518 | * inserted between Y and U planes, and U and V planes, which violates | |
1519 | * the YUV422P standard. | |
92a8337b | 1520 | */ |
4a6b8df2 TP |
1521 | v4l_bound_align_image(&pix->width, 48, 2048, 1, |
1522 | &pix->height, 32, 2048, 0, | |
6a6c8786 | 1523 | pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0); |
92a8337b | 1524 | |
ad5f2e85 | 1525 | /* limit to sensor capabilities */ |
5eab4983 HV |
1526 | mf->width = pix->width; |
1527 | mf->height = pix->height; | |
91401219 | 1528 | /* Only progressive video supported so far */ |
5eab4983 HV |
1529 | mf->field = V4L2_FIELD_NONE; |
1530 | mf->colorspace = pix->colorspace; | |
1531 | mf->code = xlate->code; | |
bf507158 | 1532 | |
5eab4983 | 1533 | ret = v4l2_subdev_call(sd, pad, set_fmt, &pad_cfg, &format); |
760697be GL |
1534 | if (ret < 0) |
1535 | return ret; | |
06daa1af | 1536 | |
5eab4983 HV |
1537 | pix->width = mf->width; |
1538 | pix->height = mf->height; | |
1539 | pix->colorspace = mf->colorspace; | |
760697be | 1540 | |
5eab4983 | 1541 | switch (mf->field) { |
760697be GL |
1542 | case V4L2_FIELD_ANY: |
1543 | case V4L2_FIELD_NONE: | |
1544 | pix->field = V4L2_FIELD_NONE; | |
1545 | break; | |
1546 | default: | |
1547 | /* TODO: support interlaced at least in pass-through mode */ | |
7dfff953 | 1548 | dev_err(icd->parent, "Field type %d unsupported.\n", |
5eab4983 | 1549 | mf->field); |
06daa1af GL |
1550 | return -EINVAL; |
1551 | } | |
1552 | ||
bf507158 | 1553 | return ret; |
3bc43840 GL |
1554 | } |
1555 | ||
57bee29d | 1556 | static int pxa_camera_reqbufs(struct soc_camera_device *icd, |
7102b773 | 1557 | struct v4l2_requestbuffers *p) |
3bc43840 GL |
1558 | { |
1559 | int i; | |
1560 | ||
5d28d525 GL |
1561 | /* |
1562 | * This is for locking debugging only. I removed spinlocks and now I | |
3bc43840 GL |
1563 | * check whether .prepare is ever called on a linked buffer, or whether |
1564 | * a dma IRQ can occur for an in-work or unlinked buffer. Until now | |
5d28d525 GL |
1565 | * it hadn't triggered |
1566 | */ | |
3bc43840 | 1567 | for (i = 0; i < p->count; i++) { |
57bee29d | 1568 | struct pxa_buffer *buf = container_of(icd->vb_vidq.bufs[i], |
3bc43840 GL |
1569 | struct pxa_buffer, vb); |
1570 | buf->inwork = 0; | |
1571 | INIT_LIST_HEAD(&buf->vb.queue); | |
1572 | } | |
1573 | ||
1574 | return 0; | |
1575 | } | |
1576 | ||
7102b773 | 1577 | static unsigned int pxa_camera_poll(struct file *file, poll_table *pt) |
3bc43840 | 1578 | { |
57bee29d | 1579 | struct soc_camera_device *icd = file->private_data; |
3bc43840 GL |
1580 | struct pxa_buffer *buf; |
1581 | ||
57bee29d | 1582 | buf = list_entry(icd->vb_vidq.stream.next, struct pxa_buffer, |
3bc43840 GL |
1583 | vb.stream); |
1584 | ||
1585 | poll_wait(file, &buf->vb.done, pt); | |
1586 | ||
1587 | if (buf->vb.state == VIDEOBUF_DONE || | |
1588 | buf->vb.state == VIDEOBUF_ERROR) | |
1589 | return POLLIN|POLLRDNORM; | |
1590 | ||
1591 | return 0; | |
1592 | } | |
1593 | ||
7102b773 GL |
1594 | static int pxa_camera_querycap(struct soc_camera_host *ici, |
1595 | struct v4l2_capability *cap) | |
3bc43840 GL |
1596 | { |
1597 | /* cap->name is set by the firendly caller:-> */ | |
1598 | strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card)); | |
7d96c3e4 GL |
1599 | cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; |
1600 | cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; | |
3bc43840 GL |
1601 | |
1602 | return 0; | |
1603 | } | |
1604 | ||
7254026c | 1605 | static int pxa_camera_suspend(struct device *dev) |
3f6ac497 | 1606 | { |
7254026c | 1607 | struct soc_camera_host *ici = to_soc_camera_host(dev); |
3f6ac497 RJ |
1608 | struct pxa_camera_dev *pcdev = ici->priv; |
1609 | int i = 0, ret = 0; | |
1610 | ||
5ca11fa3 EM |
1611 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0); |
1612 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1); | |
1613 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2); | |
1614 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3); | |
1615 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4); | |
3f6ac497 | 1616 | |
f7f6ce2d GL |
1617 | if (pcdev->soc_host.icd) { |
1618 | struct v4l2_subdev *sd = soc_camera_to_subdev(pcdev->soc_host.icd); | |
497833c6 GL |
1619 | ret = v4l2_subdev_call(sd, core, s_power, 0); |
1620 | if (ret == -ENOIOCTLCMD) | |
1621 | ret = 0; | |
1622 | } | |
3f6ac497 RJ |
1623 | |
1624 | return ret; | |
1625 | } | |
1626 | ||
7254026c | 1627 | static int pxa_camera_resume(struct device *dev) |
3f6ac497 | 1628 | { |
7254026c | 1629 | struct soc_camera_host *ici = to_soc_camera_host(dev); |
3f6ac497 RJ |
1630 | struct pxa_camera_dev *pcdev = ici->priv; |
1631 | int i = 0, ret = 0; | |
1632 | ||
87f3dd77 EM |
1633 | DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD; |
1634 | DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD; | |
1635 | DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD; | |
3f6ac497 | 1636 | |
5ca11fa3 EM |
1637 | __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0); |
1638 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1); | |
1639 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2); | |
1640 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3); | |
1641 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4); | |
3f6ac497 | 1642 | |
f7f6ce2d GL |
1643 | if (pcdev->soc_host.icd) { |
1644 | struct v4l2_subdev *sd = soc_camera_to_subdev(pcdev->soc_host.icd); | |
497833c6 GL |
1645 | ret = v4l2_subdev_call(sd, core, s_power, 1); |
1646 | if (ret == -ENOIOCTLCMD) | |
1647 | ret = 0; | |
1648 | } | |
3f6ac497 RJ |
1649 | |
1650 | /* Restart frame capture if active buffer exists */ | |
256b0233 RJ |
1651 | if (!ret && pcdev->active) |
1652 | pxa_camera_start_capture(pcdev); | |
3f6ac497 RJ |
1653 | |
1654 | return ret; | |
1655 | } | |
1656 | ||
b8d9904c GL |
1657 | static struct soc_camera_host_ops pxa_soc_camera_host_ops = { |
1658 | .owner = THIS_MODULE, | |
1659 | .add = pxa_camera_add_device, | |
1660 | .remove = pxa_camera_remove_device, | |
39b553db GL |
1661 | .clock_start = pxa_camera_clock_start, |
1662 | .clock_stop = pxa_camera_clock_stop, | |
09e231b3 | 1663 | .set_crop = pxa_camera_set_crop, |
2a48fc73 | 1664 | .get_formats = pxa_camera_get_formats, |
6a6c8786 | 1665 | .put_formats = pxa_camera_put_formats, |
d8fac217 GL |
1666 | .set_fmt = pxa_camera_set_fmt, |
1667 | .try_fmt = pxa_camera_try_fmt, | |
092d3921 | 1668 | .init_videobuf = pxa_camera_init_videobuf, |
b8d9904c GL |
1669 | .reqbufs = pxa_camera_reqbufs, |
1670 | .poll = pxa_camera_poll, | |
1671 | .querycap = pxa_camera_querycap, | |
b8d9904c GL |
1672 | .set_bus_param = pxa_camera_set_bus_param, |
1673 | }; | |
1674 | ||
e9a1d94f RJ |
1675 | static int pxa_camera_pdata_from_dt(struct device *dev, |
1676 | struct pxa_camera_dev *pcdev) | |
1677 | { | |
1678 | u32 mclk_rate; | |
1679 | struct device_node *np = dev->of_node; | |
1680 | struct v4l2_of_endpoint ep; | |
1681 | int err = of_property_read_u32(np, "clock-frequency", | |
1682 | &mclk_rate); | |
1683 | if (!err) { | |
1684 | pcdev->platform_flags |= PXA_CAMERA_MCLK_EN; | |
1685 | pcdev->mclk = mclk_rate; | |
1686 | } | |
1687 | ||
1688 | np = of_graph_get_next_endpoint(np, NULL); | |
1689 | if (!np) { | |
1690 | dev_err(dev, "could not find endpoint\n"); | |
1691 | return -EINVAL; | |
1692 | } | |
1693 | ||
1694 | err = v4l2_of_parse_endpoint(np, &ep); | |
1695 | if (err) { | |
1696 | dev_err(dev, "could not parse endpoint\n"); | |
1697 | goto out; | |
1698 | } | |
1699 | ||
1700 | switch (ep.bus.parallel.bus_width) { | |
1701 | case 4: | |
1702 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_4; | |
1703 | break; | |
1704 | case 5: | |
1705 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_5; | |
1706 | break; | |
1707 | case 8: | |
1708 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_8; | |
1709 | break; | |
1710 | case 9: | |
1711 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_9; | |
1712 | break; | |
1713 | case 10: | |
1714 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10; | |
1715 | break; | |
1716 | default: | |
1717 | break; | |
c611c908 | 1718 | } |
e9a1d94f RJ |
1719 | |
1720 | if (ep.bus.parallel.flags & V4L2_MBUS_MASTER) | |
1721 | pcdev->platform_flags |= PXA_CAMERA_MASTER; | |
1722 | if (ep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) | |
1723 | pcdev->platform_flags |= PXA_CAMERA_HSP; | |
1724 | if (ep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) | |
1725 | pcdev->platform_flags |= PXA_CAMERA_VSP; | |
1726 | if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING) | |
1727 | pcdev->platform_flags |= PXA_CAMERA_PCLK_EN | PXA_CAMERA_PCP; | |
1728 | if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) | |
1729 | pcdev->platform_flags |= PXA_CAMERA_PCLK_EN; | |
1730 | ||
1731 | out: | |
1732 | of_node_put(np); | |
1733 | ||
1734 | return err; | |
1735 | } | |
1736 | ||
4c62e976 | 1737 | static int pxa_camera_probe(struct platform_device *pdev) |
3bc43840 GL |
1738 | { |
1739 | struct pxa_camera_dev *pcdev; | |
1740 | struct resource *res; | |
1741 | void __iomem *base; | |
02da4659 | 1742 | int irq; |
3bc43840 GL |
1743 | int err = 0; |
1744 | ||
1745 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1746 | irq = platform_get_irq(pdev, 0); | |
47de201c JL |
1747 | if (!res || irq < 0) |
1748 | return -ENODEV; | |
3bc43840 | 1749 | |
47de201c | 1750 | pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL); |
3bc43840 | 1751 | if (!pcdev) { |
7102b773 | 1752 | dev_err(&pdev->dev, "Could not allocate pcdev\n"); |
47de201c | 1753 | return -ENOMEM; |
3bc43840 GL |
1754 | } |
1755 | ||
47de201c JL |
1756 | pcdev->clk = devm_clk_get(&pdev->dev, NULL); |
1757 | if (IS_ERR(pcdev->clk)) | |
1758 | return PTR_ERR(pcdev->clk); | |
3bc43840 | 1759 | |
3bc43840 GL |
1760 | pcdev->res = res; |
1761 | ||
1762 | pcdev->pdata = pdev->dev.platform_data; | |
e9a1d94f RJ |
1763 | if (&pdev->dev.of_node && !pcdev->pdata) { |
1764 | err = pxa_camera_pdata_from_dt(&pdev->dev, pcdev); | |
1765 | } else { | |
1766 | pcdev->platform_flags = pcdev->pdata->flags; | |
1767 | pcdev->mclk = pcdev->pdata->mclk_10khz * 10000; | |
1768 | } | |
1769 | if (err < 0) | |
1770 | return err; | |
1771 | ||
ad5f2e85 GL |
1772 | if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 | |
1773 | PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) { | |
5d28d525 GL |
1774 | /* |
1775 | * Platform hasn't set available data widths. This is bad. | |
1776 | * Warn and use a default. | |
1777 | */ | |
3bc43840 GL |
1778 | dev_warn(&pdev->dev, "WARNING! Platform hasn't set available " |
1779 | "data widths, using default 10 bit\n"); | |
1780 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10; | |
1781 | } | |
679419aa GL |
1782 | if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8) |
1783 | pcdev->width_flags = 1 << 7; | |
1784 | if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9) | |
1785 | pcdev->width_flags |= 1 << 8; | |
1786 | if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10) | |
1787 | pcdev->width_flags |= 1 << 9; | |
cf34cba7 | 1788 | if (!pcdev->mclk) { |
3bc43840 | 1789 | dev_warn(&pdev->dev, |
cf34cba7 | 1790 | "mclk == 0! Please, fix your platform data. " |
3bc43840 | 1791 | "Using default 20MHz\n"); |
cf34cba7 | 1792 | pcdev->mclk = 20000000; |
3bc43840 GL |
1793 | } |
1794 | ||
40e2e092 | 1795 | pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev); |
cf34cba7 | 1796 | |
3bc43840 GL |
1797 | INIT_LIST_HEAD(&pcdev->capture); |
1798 | spin_lock_init(&pcdev->lock); | |
1799 | ||
1800 | /* | |
1801 | * Request the regions. | |
1802 | */ | |
8efdb135 SK |
1803 | base = devm_ioremap_resource(&pdev->dev, res); |
1804 | if (IS_ERR(base)) | |
1805 | return PTR_ERR(base); | |
1806 | ||
3bc43840 GL |
1807 | pcdev->irq = irq; |
1808 | pcdev->base = base; | |
3bc43840 GL |
1809 | |
1810 | /* request dma */ | |
de3e3b82 | 1811 | err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH, |
1812 | pxa_camera_dma_irq_y, pcdev); | |
1813 | if (err < 0) { | |
eff505fa | 1814 | dev_err(&pdev->dev, "Can't request DMA for Y\n"); |
47de201c | 1815 | return err; |
3bc43840 | 1816 | } |
de3e3b82 | 1817 | pcdev->dma_chans[0] = err; |
eff505fa | 1818 | dev_dbg(&pdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]); |
a5462e5b | 1819 | |
de3e3b82 | 1820 | err = pxa_request_dma("CI_U", DMA_PRIO_HIGH, |
1821 | pxa_camera_dma_irq_u, pcdev); | |
1822 | if (err < 0) { | |
eff505fa | 1823 | dev_err(&pdev->dev, "Can't request DMA for U\n"); |
a5462e5b MR |
1824 | goto exit_free_dma_y; |
1825 | } | |
de3e3b82 | 1826 | pcdev->dma_chans[1] = err; |
eff505fa | 1827 | dev_dbg(&pdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]); |
a5462e5b | 1828 | |
de3e3b82 | 1829 | err = pxa_request_dma("CI_V", DMA_PRIO_HIGH, |
1830 | pxa_camera_dma_irq_v, pcdev); | |
1831 | if (err < 0) { | |
eff505fa | 1832 | dev_err(&pdev->dev, "Can't request DMA for V\n"); |
a5462e5b MR |
1833 | goto exit_free_dma_u; |
1834 | } | |
de3e3b82 | 1835 | pcdev->dma_chans[2] = err; |
eff505fa | 1836 | dev_dbg(&pdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]); |
3bc43840 | 1837 | |
87f3dd77 EM |
1838 | DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD; |
1839 | DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD; | |
1840 | DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD; | |
3bc43840 GL |
1841 | |
1842 | /* request irq */ | |
47de201c JL |
1843 | err = devm_request_irq(&pdev->dev, pcdev->irq, pxa_camera_irq, 0, |
1844 | PXA_CAM_DRV_NAME, pcdev); | |
3bc43840 | 1845 | if (err) { |
47de201c | 1846 | dev_err(&pdev->dev, "Camera interrupt register failed\n"); |
3bc43840 GL |
1847 | goto exit_free_dma; |
1848 | } | |
1849 | ||
eb6c8558 GL |
1850 | pcdev->soc_host.drv_name = PXA_CAM_DRV_NAME; |
1851 | pcdev->soc_host.ops = &pxa_soc_camera_host_ops; | |
1852 | pcdev->soc_host.priv = pcdev; | |
979ea1dd | 1853 | pcdev->soc_host.v4l2_dev.dev = &pdev->dev; |
eb6c8558 | 1854 | pcdev->soc_host.nr = pdev->id; |
e623ebe6 | 1855 | tasklet_init(&pcdev->task_eof, pxa_camera_eof, (unsigned long)pcdev); |
eff505fa | 1856 | |
eb6c8558 | 1857 | err = soc_camera_host_register(&pcdev->soc_host); |
3bc43840 | 1858 | if (err) |
47de201c | 1859 | goto exit_free_dma; |
3bc43840 GL |
1860 | |
1861 | return 0; | |
1862 | ||
3bc43840 | 1863 | exit_free_dma: |
a5462e5b MR |
1864 | pxa_free_dma(pcdev->dma_chans[2]); |
1865 | exit_free_dma_u: | |
1866 | pxa_free_dma(pcdev->dma_chans[1]); | |
1867 | exit_free_dma_y: | |
1868 | pxa_free_dma(pcdev->dma_chans[0]); | |
3bc43840 GL |
1869 | return err; |
1870 | } | |
1871 | ||
4c62e976 | 1872 | static int pxa_camera_remove(struct platform_device *pdev) |
3bc43840 | 1873 | { |
eff505fa GL |
1874 | struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev); |
1875 | struct pxa_camera_dev *pcdev = container_of(soc_host, | |
1876 | struct pxa_camera_dev, soc_host); | |
3bc43840 | 1877 | |
a5462e5b MR |
1878 | pxa_free_dma(pcdev->dma_chans[0]); |
1879 | pxa_free_dma(pcdev->dma_chans[1]); | |
1880 | pxa_free_dma(pcdev->dma_chans[2]); | |
3bc43840 | 1881 | |
eff505fa | 1882 | soc_camera_host_unregister(soc_host); |
3bc43840 | 1883 | |
7102b773 | 1884 | dev_info(&pdev->dev, "PXA Camera driver unloaded\n"); |
3bc43840 | 1885 | |
3bc43840 GL |
1886 | return 0; |
1887 | } | |
1888 | ||
56a49194 | 1889 | static const struct dev_pm_ops pxa_camera_pm = { |
7254026c GL |
1890 | .suspend = pxa_camera_suspend, |
1891 | .resume = pxa_camera_resume, | |
1892 | }; | |
1893 | ||
e9a1d94f RJ |
1894 | static const struct of_device_id pxa_camera_of_match[] = { |
1895 | { .compatible = "marvell,pxa270-qci", }, | |
1896 | {}, | |
1897 | }; | |
1898 | MODULE_DEVICE_TABLE(of, pxa_camera_of_match); | |
1899 | ||
3bc43840 | 1900 | static struct platform_driver pxa_camera_driver = { |
6003b2ad | 1901 | .driver = { |
3bc43840 | 1902 | .name = PXA_CAM_DRV_NAME, |
7254026c | 1903 | .pm = &pxa_camera_pm, |
e9a1d94f | 1904 | .of_match_table = of_match_ptr(pxa_camera_of_match), |
3bc43840 GL |
1905 | }, |
1906 | .probe = pxa_camera_probe, | |
4c62e976 | 1907 | .remove = pxa_camera_remove, |
3bc43840 GL |
1908 | }; |
1909 | ||
1d6629b1 | 1910 | module_platform_driver(pxa_camera_driver); |
3bc43840 GL |
1911 | |
1912 | MODULE_DESCRIPTION("PXA27x SoC Camera Host driver"); | |
1913 | MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>"); | |
1914 | MODULE_LICENSE("GPL"); | |
64dc3c1a | 1915 | MODULE_VERSION(PXA_CAM_VERSION); |
40e2e092 | 1916 | MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME); |