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44687b2e AT |
1 | /* |
2 | * Scaler library | |
3 | * | |
4 | * Copyright (c) 2013 Texas Instruments Inc. | |
5 | * | |
6 | * David Griego, <dagriego@biglakesoftware.com> | |
7 | * Dale Farnsworth, <dale@farnsworth.org> | |
8 | * Archit Taneja, <archit@ti.com> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License version 2 as published by | |
12 | * the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/err.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/slab.h> | |
19 | ||
20 | #include "sc.h" | |
0df20f96 | 21 | #include "sc_coeff.h" |
44687b2e | 22 | |
44687b2e AT |
23 | void sc_dump_regs(struct sc_data *sc) |
24 | { | |
25 | struct device *dev = &sc->pdev->dev; | |
26 | ||
27 | u32 read_reg(struct sc_data *sc, int offset) | |
28 | { | |
29 | return ioread32(sc->base + offset); | |
30 | } | |
31 | ||
32 | #define DUMPREG(r) dev_dbg(dev, "%-35s %08x\n", #r, read_reg(sc, CFG_##r)) | |
33 | ||
34 | DUMPREG(SC0); | |
35 | DUMPREG(SC1); | |
36 | DUMPREG(SC2); | |
37 | DUMPREG(SC3); | |
38 | DUMPREG(SC4); | |
39 | DUMPREG(SC5); | |
40 | DUMPREG(SC6); | |
41 | DUMPREG(SC8); | |
42 | DUMPREG(SC9); | |
43 | DUMPREG(SC10); | |
44 | DUMPREG(SC11); | |
45 | DUMPREG(SC12); | |
46 | DUMPREG(SC13); | |
47 | DUMPREG(SC17); | |
48 | DUMPREG(SC18); | |
49 | DUMPREG(SC19); | |
50 | DUMPREG(SC20); | |
51 | DUMPREG(SC21); | |
52 | DUMPREG(SC22); | |
53 | DUMPREG(SC23); | |
54 | DUMPREG(SC24); | |
55 | DUMPREG(SC25); | |
56 | ||
57 | #undef DUMPREG | |
58 | } | |
59 | ||
0df20f96 AT |
60 | /* |
61 | * set the horizontal scaler coefficients according to the ratio of output to | |
62 | * input widths, after accounting for up to two levels of decimation | |
63 | */ | |
64 | void sc_set_hs_coeffs(struct sc_data *sc, void *addr, unsigned int src_w, | |
65 | unsigned int dst_w) | |
66 | { | |
67 | int sixteenths; | |
68 | int idx; | |
69 | int i, j; | |
70 | u16 *coeff_h = addr; | |
71 | const u16 *cp; | |
72 | ||
73 | if (dst_w > src_w) { | |
74 | idx = HS_UP_SCALE; | |
75 | } else { | |
76 | if ((dst_w << 1) < src_w) | |
77 | dst_w <<= 1; /* first level decimation */ | |
78 | if ((dst_w << 1) < src_w) | |
79 | dst_w <<= 1; /* second level decimation */ | |
80 | ||
81 | if (dst_w == src_w) { | |
82 | idx = HS_LE_16_16_SCALE; | |
83 | } else { | |
84 | sixteenths = (dst_w << 4) / src_w; | |
85 | if (sixteenths < 8) | |
86 | sixteenths = 8; | |
87 | idx = HS_LT_9_16_SCALE + sixteenths - 8; | |
88 | } | |
89 | } | |
90 | ||
91 | if (idx == sc->hs_index) | |
92 | return; | |
93 | ||
94 | cp = scaler_hs_coeffs[idx]; | |
95 | ||
96 | for (i = 0; i < SC_NUM_PHASES * 2; i++) { | |
97 | for (j = 0; j < SC_H_NUM_TAPS; j++) | |
98 | *coeff_h++ = *cp++; | |
99 | /* | |
100 | * for each phase, the scaler expects space for 8 coefficients | |
101 | * in it's memory. For the horizontal scaler, we copy the first | |
102 | * 7 coefficients and skip the last slot to move to the next | |
103 | * row to hold coefficients for the next phase | |
104 | */ | |
105 | coeff_h += SC_NUM_TAPS_MEM_ALIGN - SC_H_NUM_TAPS; | |
106 | } | |
107 | ||
108 | sc->hs_index = idx; | |
109 | ||
110 | sc->load_coeff_h = true; | |
111 | } | |
112 | ||
113 | /* | |
114 | * set the vertical scaler coefficients according to the ratio of output to | |
115 | * input heights | |
116 | */ | |
117 | void sc_set_vs_coeffs(struct sc_data *sc, void *addr, unsigned int src_h, | |
118 | unsigned int dst_h) | |
119 | { | |
120 | int sixteenths; | |
121 | int idx; | |
122 | int i, j; | |
123 | u16 *coeff_v = addr; | |
124 | const u16 *cp; | |
125 | ||
126 | if (dst_h > src_h) { | |
127 | idx = VS_UP_SCALE; | |
128 | } else if (dst_h == src_h) { | |
129 | idx = VS_1_TO_1_SCALE; | |
130 | } else { | |
131 | sixteenths = (dst_h << 4) / src_h; | |
132 | if (sixteenths < 8) | |
133 | sixteenths = 8; | |
134 | idx = VS_LT_9_16_SCALE + sixteenths - 8; | |
135 | } | |
136 | ||
137 | if (idx == sc->vs_index) | |
138 | return; | |
139 | ||
140 | cp = scaler_vs_coeffs[idx]; | |
141 | ||
142 | for (i = 0; i < SC_NUM_PHASES * 2; i++) { | |
143 | for (j = 0; j < SC_V_NUM_TAPS; j++) | |
144 | *coeff_v++ = *cp++; | |
145 | /* | |
146 | * for the vertical scaler, we copy the first 5 coefficients and | |
147 | * skip the last 3 slots to move to the next row to hold | |
148 | * coefficients for the next phase | |
149 | */ | |
150 | coeff_v += SC_NUM_TAPS_MEM_ALIGN - SC_V_NUM_TAPS; | |
151 | } | |
152 | ||
153 | sc->vs_index = idx; | |
154 | sc->load_coeff_v = true; | |
155 | } | |
156 | ||
bbee8b39 AT |
157 | void sc_config_scaler(struct sc_data *sc, u32 *sc_reg0, u32 *sc_reg8, |
158 | u32 *sc_reg17, unsigned int src_w, unsigned int src_h, | |
159 | unsigned int dst_w, unsigned int dst_h) | |
160 | { | |
161 | struct device *dev = &sc->pdev->dev; | |
162 | u32 val; | |
163 | int dcm_x, dcm_shift; | |
164 | bool use_rav; | |
165 | unsigned long lltmp; | |
166 | u32 lin_acc_inc, lin_acc_inc_u; | |
167 | u32 col_acc_offset; | |
168 | u16 factor = 0; | |
169 | int row_acc_init_rav = 0, row_acc_init_rav_b = 0; | |
170 | u32 row_acc_inc = 0, row_acc_offset = 0, row_acc_offset_b = 0; | |
171 | /* | |
172 | * location of SC register in payload memory with respect to the first | |
173 | * register in the mmr address data block | |
174 | */ | |
175 | u32 *sc_reg9 = sc_reg8 + 1; | |
176 | u32 *sc_reg12 = sc_reg8 + 4; | |
177 | u32 *sc_reg13 = sc_reg8 + 5; | |
178 | u32 *sc_reg24 = sc_reg17 + 7; | |
179 | ||
180 | val = sc_reg0[0]; | |
181 | ||
182 | /* clear all the features(they may get enabled elsewhere later) */ | |
183 | val &= ~(CFG_SELFGEN_FID | CFG_TRIM | CFG_ENABLE_SIN2_VER_INTP | | |
184 | CFG_INTERLACE_I | CFG_DCM_4X | CFG_DCM_2X | CFG_AUTO_HS | | |
185 | CFG_ENABLE_EV | CFG_USE_RAV | CFG_INVT_FID | CFG_SC_BYPASS | | |
186 | CFG_INTERLACE_O | CFG_Y_PK_EN | CFG_HP_BYPASS | CFG_LINEAR); | |
187 | ||
188 | if (src_w == dst_w && src_h == dst_h) { | |
189 | val |= CFG_SC_BYPASS; | |
190 | sc_reg0[0] = val; | |
191 | return; | |
192 | } | |
193 | ||
194 | /* we only support linear scaling for now */ | |
195 | val |= CFG_LINEAR; | |
196 | ||
197 | /* configure horizontal scaler */ | |
198 | ||
199 | /* enable 2X or 4X decimation */ | |
200 | dcm_x = src_w / dst_w; | |
201 | if (dcm_x > 4) { | |
202 | val |= CFG_DCM_4X; | |
203 | dcm_shift = 2; | |
204 | } else if (dcm_x > 2) { | |
205 | val |= CFG_DCM_2X; | |
206 | dcm_shift = 1; | |
207 | } else { | |
208 | dcm_shift = 0; | |
209 | } | |
210 | ||
211 | lltmp = dst_w - 1; | |
212 | lin_acc_inc = div64_u64(((u64)(src_w >> dcm_shift) - 1) << 24, lltmp); | |
213 | lin_acc_inc_u = 0; | |
214 | col_acc_offset = 0; | |
215 | ||
216 | dev_dbg(dev, "hs config: src_w = %d, dst_w = %d, decimation = %s, lin_acc_inc = %08x\n", | |
217 | src_w, dst_w, dcm_shift == 2 ? "4x" : | |
218 | (dcm_shift == 1 ? "2x" : "none"), lin_acc_inc); | |
219 | ||
220 | /* configure vertical scaler */ | |
221 | ||
222 | /* use RAV for vertical scaler if vertical downscaling is > 4x */ | |
223 | if (dst_h < (src_h >> 2)) { | |
224 | use_rav = true; | |
225 | val |= CFG_USE_RAV; | |
226 | } else { | |
227 | use_rav = false; | |
228 | } | |
229 | ||
230 | if (use_rav) { | |
231 | /* use RAV */ | |
232 | factor = (u16) ((dst_h << 10) / src_h); | |
233 | ||
234 | row_acc_init_rav = factor + ((1 + factor) >> 1); | |
235 | if (row_acc_init_rav >= 1024) | |
236 | row_acc_init_rav -= 1024; | |
237 | ||
238 | row_acc_init_rav_b = row_acc_init_rav + | |
239 | (1 + (row_acc_init_rav >> 1)) - | |
240 | (1024 >> 1); | |
241 | ||
242 | if (row_acc_init_rav_b < 0) { | |
243 | row_acc_init_rav_b += row_acc_init_rav; | |
244 | row_acc_init_rav *= 2; | |
245 | } | |
246 | ||
247 | dev_dbg(dev, "vs config(RAV): src_h = %d, dst_h = %d, factor = %d, acc_init = %08x, acc_init_b = %08x\n", | |
248 | src_h, dst_h, factor, row_acc_init_rav, | |
249 | row_acc_init_rav_b); | |
250 | } else { | |
251 | /* use polyphase */ | |
252 | row_acc_inc = ((src_h - 1) << 16) / (dst_h - 1); | |
253 | row_acc_offset = 0; | |
254 | row_acc_offset_b = 0; | |
255 | ||
256 | dev_dbg(dev, "vs config(POLY): src_h = %d, dst_h = %d,row_acc_inc = %08x\n", | |
257 | src_h, dst_h, row_acc_inc); | |
258 | } | |
259 | ||
260 | ||
261 | sc_reg0[0] = val; | |
262 | sc_reg0[1] = row_acc_inc; | |
263 | sc_reg0[2] = row_acc_offset; | |
264 | sc_reg0[3] = row_acc_offset_b; | |
265 | ||
266 | sc_reg0[4] = ((lin_acc_inc_u & CFG_LIN_ACC_INC_U_MASK) << | |
267 | CFG_LIN_ACC_INC_U_SHIFT) | (dst_w << CFG_TAR_W_SHIFT) | | |
268 | (dst_h << CFG_TAR_H_SHIFT); | |
269 | ||
270 | sc_reg0[5] = (src_w << CFG_SRC_W_SHIFT) | (src_h << CFG_SRC_H_SHIFT); | |
271 | ||
272 | sc_reg0[6] = (row_acc_init_rav_b << CFG_ROW_ACC_INIT_RAV_B_SHIFT) | | |
273 | (row_acc_init_rav << CFG_ROW_ACC_INIT_RAV_SHIFT); | |
274 | ||
275 | *sc_reg9 = lin_acc_inc; | |
276 | ||
277 | *sc_reg12 = col_acc_offset << CFG_COL_ACC_OFFSET_SHIFT; | |
278 | ||
279 | *sc_reg13 = factor; | |
280 | ||
281 | *sc_reg24 = (src_w << CFG_ORG_W_SHIFT) | (src_h << CFG_ORG_H_SHIFT); | |
282 | } | |
283 | ||
44687b2e AT |
284 | struct sc_data *sc_create(struct platform_device *pdev) |
285 | { | |
286 | struct sc_data *sc; | |
287 | ||
288 | dev_dbg(&pdev->dev, "sc_create\n"); | |
289 | ||
290 | sc = devm_kzalloc(&pdev->dev, sizeof(*sc), GFP_KERNEL); | |
291 | if (!sc) { | |
292 | dev_err(&pdev->dev, "couldn't alloc sc_data\n"); | |
293 | return ERR_PTR(-ENOMEM); | |
294 | } | |
295 | ||
296 | sc->pdev = pdev; | |
297 | ||
298 | sc->res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sc"); | |
299 | if (!sc->res) { | |
300 | dev_err(&pdev->dev, "missing platform resources data\n"); | |
301 | return ERR_PTR(-ENODEV); | |
302 | } | |
303 | ||
304 | sc->base = devm_ioremap_resource(&pdev->dev, sc->res); | |
305 | if (!sc->base) { | |
306 | dev_err(&pdev->dev, "failed to ioremap\n"); | |
307 | return ERR_PTR(-ENOMEM); | |
308 | } | |
309 | ||
310 | return sc; | |
311 | } |