[mirror_ubuntu-zesty-kernel.git] / drivers / media / platform / vsp1 / vsp1_bru.c

/*
 * vsp1_bru.c  --  R-Car VSP1 Blend ROP Unit
 *
 * Copyright (C) 2013 Renesas Corporation
 *
 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/device.h>
#include <linux/gfp.h>

#include <media/v4l2-subdev.h>

#include "vsp1.h"
#include "vsp1_bru.h"
#include "vsp1_rwpf.h"
#include "vsp1_video.h"

#define BRU_MIN_SIZE				1U
#define BRU_MAX_SIZE				8190U

/* -----------------------------------------------------------------------------
 * Device Access
 */

static inline void vsp1_bru_write(struct vsp1_bru *bru, u32 reg, u32 data)
{
	vsp1_mod_write(&bru->entity, reg, data);
}

/* -----------------------------------------------------------------------------
 * Controls
 */

static int bru_s_ctrl(struct v4l2_ctrl *ctrl)
{
	struct vsp1_bru *bru =
		container_of(ctrl->handler, struct vsp1_bru, ctrls);

	switch (ctrl->id) {
	case V4L2_CID_BG_COLOR:
		bru->bgcolor = ctrl->val;
		break;
	}

	return 0;
}

static const struct v4l2_ctrl_ops bru_ctrl_ops = {
	.s_ctrl = bru_s_ctrl,
};

/* -----------------------------------------------------------------------------
 * V4L2 Subdevice Core Operations
 */

static int bru_s_stream(struct v4l2_subdev *subdev, int enable)
{
	struct vsp1_pipeline *pipe = to_vsp1_pipeline(&subdev->entity);
	struct vsp1_bru *bru = to_bru(subdev);
	struct v4l2_mbus_framefmt *format;
	unsigned int flags;
	unsigned int i;

	if (!enable)
		return 0;

	format = vsp1_entity_get_pad_format(&bru->entity, bru->entity.config,
					    bru->entity.source_pad);

	/* The hardware is extremely flexible but we have no userspace API to
	 * expose all the parameters, nor is it clear whether we would have use
	 * cases for all the supported modes. Let's just harcode the parameters
	 * to sane default values for now.
	 */

	/* Disable dithering and enable color data normalization unless the
	 * format at the pipeline output is premultiplied.
	 */
	flags = pipe->output ? pipe->output->format.flags : 0;
	vsp1_bru_write(bru, VI6_BRU_INCTRL,
		       flags & V4L2_PIX_FMT_FLAG_PREMUL_ALPHA ?
		       0 : VI6_BRU_INCTRL_NRM);

	/* Set the background position to cover the whole output image and
	 * configure its color.
	 */
	vsp1_bru_write(bru, VI6_BRU_VIRRPF_SIZE,
		       (format->width << VI6_BRU_VIRRPF_SIZE_HSIZE_SHIFT) |
		       (format->height << VI6_BRU_VIRRPF_SIZE_VSIZE_SHIFT));
	vsp1_bru_write(bru, VI6_BRU_VIRRPF_LOC, 0);

	vsp1_bru_write(bru, VI6_BRU_VIRRPF_COL, bru->bgcolor |
		       (0xff << VI6_BRU_VIRRPF_COL_A_SHIFT));

	/* Route BRU input 1 as SRC input to the ROP unit and configure the ROP
	 * unit with a NOP operation to make BRU input 1 available as the
	 * Blend/ROP unit B SRC input.
	 */
	vsp1_bru_write(bru, VI6_BRU_ROP, VI6_BRU_ROP_DSTSEL_BRUIN(1) |
		       VI6_BRU_ROP_CROP(VI6_ROP_NOP) |
		       VI6_BRU_ROP_AROP(VI6_ROP_NOP));

	for (i = 0; i < bru->entity.source_pad; ++i) {
		bool premultiplied = false;
		u32 ctrl = 0;

		/* Configure all Blend/ROP units corresponding to an enabled BRU
		 * input for alpha blending. Blend/ROP units corresponding to
		 * disabled BRU inputs are used in ROP NOP mode to ignore the
		 * SRC input.
		 */
		if (bru->inputs[i].rpf) {
			ctrl |= VI6_BRU_CTRL_RBC;

			premultiplied = bru->inputs[i].rpf->format.flags
				      & V4L2_PIX_FMT_FLAG_PREMUL_ALPHA;
		} else {
			ctrl |= VI6_BRU_CTRL_CROP(VI6_ROP_NOP)
			     |  VI6_BRU_CTRL_AROP(VI6_ROP_NOP);
		}

		/* Select the virtual RPF as the Blend/ROP unit A DST input to
		 * serve as a background color.
		 */
		if (i == 0)
			ctrl |= VI6_BRU_CTRL_DSTSEL_VRPF;

		/* Route BRU inputs 0 to 3 as SRC inputs to Blend/ROP units A to
		 * D in that order. The Blend/ROP unit B SRC is hardwired to the
		 * ROP unit output, the corresponding register bits must be set
		 * to 0.
		 */
		if (i != 1)
			ctrl |= VI6_BRU_CTRL_SRCSEL_BRUIN(i);

		vsp1_bru_write(bru, VI6_BRU_CTRL(i), ctrl);

		/* Harcode the blending formula to
		 *
		 *	DSTc = DSTc * (1 - SRCa) + SRCc * SRCa
		 *	DSTa = DSTa * (1 - SRCa) + SRCa
		 *
		 * when the SRC input isn't premultiplied, and to
		 *
		 *	DSTc = DSTc * (1 - SRCa) + SRCc
		 *	DSTa = DSTa * (1 - SRCa) + SRCa
		 *
		 * otherwise.
		 */
		vsp1_bru_write(bru, VI6_BRU_BLD(i),
			       VI6_BRU_BLD_CCMDX_255_SRC_A |
			       (premultiplied ? VI6_BRU_BLD_CCMDY_COEFY :
						VI6_BRU_BLD_CCMDY_SRC_A) |
			       VI6_BRU_BLD_ACMDX_255_SRC_A |
			       VI6_BRU_BLD_ACMDY_COEFY |
			       (0xff << VI6_BRU_BLD_COEFY_SHIFT));
	}

	return 0;
}

/* -----------------------------------------------------------------------------
 * V4L2 Subdevice Pad Operations
 */

/*
 * The BRU can't perform format conversion, all sink and source formats must be
 * identical. We pick the format on the first sink pad (pad 0) and propagate it
 * to all other pads.
 */

static int bru_enum_mbus_code(struct v4l2_subdev *subdev,
			      struct v4l2_subdev_pad_config *cfg,
			      struct v4l2_subdev_mbus_code_enum *code)
{
	static const unsigned int codes[] = {
		MEDIA_BUS_FMT_ARGB8888_1X32,
		MEDIA_BUS_FMT_AYUV8_1X32,
	};
	struct vsp1_bru *bru = to_bru(subdev);

	if (code->pad == BRU_PAD_SINK(0)) {
		if (code->index >= ARRAY_SIZE(codes))
			return -EINVAL;

		code->code = codes[code->index];
	} else {
		struct v4l2_subdev_pad_config *config;
		struct v4l2_mbus_framefmt *format;

		if (code->index)
			return -EINVAL;

		config = vsp1_entity_get_pad_config(&bru->entity, cfg,
						    code->which);
		if (!config)
			return -EINVAL;

		format = vsp1_entity_get_pad_format(&bru->entity, config,
						    BRU_PAD_SINK(0));
		code->code = format->code;
	}

	return 0;
}

static int bru_enum_frame_size(struct v4l2_subdev *subdev,
			       struct v4l2_subdev_pad_config *cfg,
			       struct v4l2_subdev_frame_size_enum *fse)
{
	if (fse->index)
		return -EINVAL;

	if (fse->code != MEDIA_BUS_FMT_ARGB8888_1X32 &&
	    fse->code != MEDIA_BUS_FMT_AYUV8_1X32)
		return -EINVAL;

	fse->min_width = BRU_MIN_SIZE;
	fse->max_width = BRU_MAX_SIZE;
	fse->min_height = BRU_MIN_SIZE;
	fse->max_height = BRU_MAX_SIZE;

	return 0;
}

static struct v4l2_rect *bru_get_compose(struct vsp1_bru *bru,
					 struct v4l2_subdev_pad_config *cfg,
					 unsigned int pad, u32 which)
{
	switch (which) {
	case V4L2_SUBDEV_FORMAT_TRY:
		return v4l2_subdev_get_try_compose(&bru->entity.subdev, cfg,
						   pad);
	case V4L2_SUBDEV_FORMAT_ACTIVE:
		return &bru->inputs[pad].compose;
	default:
		return NULL;
	}
}

static int bru_get_format(struct v4l2_subdev *subdev,
			  struct v4l2_subdev_pad_config *cfg,
			  struct v4l2_subdev_format *fmt)
{
	struct vsp1_bru *bru = to_bru(subdev);
	struct v4l2_subdev_pad_config *config;

	config = vsp1_entity_get_pad_config(&bru->entity, cfg, fmt->which);
	if (!config)
		return -EINVAL;

	fmt->format = *vsp1_entity_get_pad_format(&bru->entity, config,
						  fmt->pad);

	return 0;
}

static void bru_try_format(struct vsp1_bru *bru,
			   struct v4l2_subdev_pad_config *config,
			   unsigned int pad, struct v4l2_mbus_framefmt *fmt)
{
	struct v4l2_mbus_framefmt *format;

	switch (pad) {
	case BRU_PAD_SINK(0):
		/* Default to YUV if the requested format is not supported. */
		if (fmt->code != MEDIA_BUS_FMT_ARGB8888_1X32 &&
		    fmt->code != MEDIA_BUS_FMT_AYUV8_1X32)
			fmt->code = MEDIA_BUS_FMT_AYUV8_1X32;
		break;

	default:
		/* The BRU can't perform format conversion. */
		format = vsp1_entity_get_pad_format(&bru->entity, config,
						    BRU_PAD_SINK(0));
		fmt->code = format->code;
		break;
	}

	fmt->width = clamp(fmt->width, BRU_MIN_SIZE, BRU_MAX_SIZE);
	fmt->height = clamp(fmt->height, BRU_MIN_SIZE, BRU_MAX_SIZE);
	fmt->field = V4L2_FIELD_NONE;
	fmt->colorspace = V4L2_COLORSPACE_SRGB;
}

static int bru_set_format(struct v4l2_subdev *subdev,
			  struct v4l2_subdev_pad_config *cfg,
			  struct v4l2_subdev_format *fmt)
{
	struct vsp1_bru *bru = to_bru(subdev);
	struct v4l2_subdev_pad_config *config;
	struct v4l2_mbus_framefmt *format;

	config = vsp1_entity_get_pad_config(&bru->entity, cfg, fmt->which);
	if (!config)
		return -EINVAL;

	bru_try_format(bru, config, fmt->pad, &fmt->format);

	format = vsp1_entity_get_pad_format(&bru->entity, config, fmt->pad);
	*format = fmt->format;

	/* Reset the compose rectangle */
	if (fmt->pad != bru->entity.source_pad) {
		struct v4l2_rect *compose;

		compose = bru_get_compose(bru, cfg, fmt->pad, fmt->which);
		compose->left = 0;
		compose->top = 0;
		compose->width = format->width;
		compose->height = format->height;
	}

	/* Propagate the format code to all pads */
	if (fmt->pad == BRU_PAD_SINK(0)) {
		unsigned int i;

		for (i = 0; i <= bru->entity.source_pad; ++i) {
			format = vsp1_entity_get_pad_format(&bru->entity,
							    config, i);
			format->code = fmt->format.code;
		}
	}

	return 0;
}

static int bru_get_selection(struct v4l2_subdev *subdev,
			     struct v4l2_subdev_pad_config *cfg,
			     struct v4l2_subdev_selection *sel)
{
	struct vsp1_bru *bru = to_bru(subdev);

	if (sel->pad == bru->entity.source_pad)
		return -EINVAL;

	switch (sel->target) {
	case V4L2_SEL_TGT_COMPOSE_BOUNDS:
		sel->r.left = 0;
		sel->r.top = 0;
		sel->r.width = BRU_MAX_SIZE;
		sel->r.height = BRU_MAX_SIZE;
		return 0;

	case V4L2_SEL_TGT_COMPOSE:
		sel->r = *bru_get_compose(bru, cfg, sel->pad, sel->which);
		return 0;

	default:
		return -EINVAL;
	}
}

static int bru_set_selection(struct v4l2_subdev *subdev,
			     struct v4l2_subdev_pad_config *cfg,
			     struct v4l2_subdev_selection *sel)
{
	struct vsp1_bru *bru = to_bru(subdev);
	struct v4l2_subdev_pad_config *config;
	struct v4l2_mbus_framefmt *format;
	struct v4l2_rect *compose;

	if (sel->pad == bru->entity.source_pad)
		return -EINVAL;

	if (sel->target != V4L2_SEL_TGT_COMPOSE)
		return -EINVAL;

	config = vsp1_entity_get_pad_config(&bru->entity, cfg, sel->which);
	if (!config)
		return -EINVAL;

	/* The compose rectangle top left corner must be inside the output
	 * frame.
	 */
	format = vsp1_entity_get_pad_format(&bru->entity, config,
					    bru->entity.source_pad);
	sel->r.left = clamp_t(unsigned int, sel->r.left, 0, format->width - 1);
	sel->r.top = clamp_t(unsigned int, sel->r.top, 0, format->height - 1);

	/* Scaling isn't supported, the compose rectangle size must be identical
	 * to the sink format size.
	 */
	format = vsp1_entity_get_pad_format(&bru->entity, config, sel->pad);
	sel->r.width = format->width;
	sel->r.height = format->height;

	compose = bru_get_compose(bru, cfg, sel->pad, sel->which);
	*compose = sel->r;

	return 0;
}

/* -----------------------------------------------------------------------------
 * V4L2 Subdevice Operations
 */

static struct v4l2_subdev_video_ops bru_video_ops = {
	.s_stream = bru_s_stream,
};

static struct v4l2_subdev_pad_ops bru_pad_ops = {
	.init_cfg = vsp1_entity_init_cfg,
	.enum_mbus_code = bru_enum_mbus_code,
	.enum_frame_size = bru_enum_frame_size,
	.get_fmt = bru_get_format,
	.set_fmt = bru_set_format,
	.get_selection = bru_get_selection,
	.set_selection = bru_set_selection,
};

static struct v4l2_subdev_ops bru_ops = {
	.video	= &bru_video_ops,
	.pad    = &bru_pad_ops,
};

/* -----------------------------------------------------------------------------
 * Initialization and Cleanup
 */

struct vsp1_bru *vsp1_bru_create(struct vsp1_device *vsp1)
{
	struct vsp1_bru *bru;
	int ret;

	bru = devm_kzalloc(vsp1->dev, sizeof(*bru), GFP_KERNEL);
	if (bru == NULL)
		return ERR_PTR(-ENOMEM);

	bru->entity.type = VSP1_ENTITY_BRU;

	ret = vsp1_entity_init(vsp1, &bru->entity, "bru",
			       vsp1->info->num_bru_inputs + 1, &bru_ops);
	if (ret < 0)
		return ERR_PTR(ret);

	/* Initialize the control handler. */
	v4l2_ctrl_handler_init(&bru->ctrls, 1);
	v4l2_ctrl_new_std(&bru->ctrls, &bru_ctrl_ops, V4L2_CID_BG_COLOR,
			  0, 0xffffff, 1, 0);

	bru->bgcolor = 0;

	bru->entity.subdev.ctrl_handler = &bru->ctrls;

	if (bru->ctrls.error) {
		dev_err(vsp1->dev, "bru: failed to initialize controls\n");
		ret = bru->ctrls.error;
		vsp1_entity_destroy(&bru->entity);
		return ERR_PTR(ret);
	}

	return bru;
}
Commit	Line	Data
629bb6d4 LP	1	/*
	2	* vsp1_bru.c -- R-Car VSP1 Blend ROP Unit
	3	*
	4	* Copyright (C) 2013 Renesas Corporation
	5	*
	6	* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*/
	13
	14	#include <linux/device.h>
	15	#include <linux/gfp.h>
	16
	17	#include <media/v4l2-subdev.h>
	18
	19	#include "vsp1.h"
	20	#include "vsp1_bru.h"
6418b4d6	21	#include "vsp1_rwpf.h"
9d40637a	22	#include "vsp1_video.h"
629bb6d4	23
8cb0b634	24	#define BRU_MIN_SIZE 1U
629bb6d4 LP	25	#define BRU_MAX_SIZE 8190U
	26
	27	/* -----------------------------------------------------------------------------
	28	* Device Access
	29	*/
	30
629bb6d4 LP	31	static inline void vsp1_bru_write(struct vsp1_bru *bru, u32 reg, u32 data)
629bb6d4 LP	32	{
1517b039	33	vsp1_mod_write(&bru->entity, reg, data);
629bb6d4 LP	34	}
629bb6d4 LP	35
a16e2794 LP	36	/* -----------------------------------------------------------------------------
	37	* Controls
	38	*/
	39
	40	static int bru_s_ctrl(struct v4l2_ctrl *ctrl)
	41	{
	42	struct vsp1_bru *bru =
	43	container_of(ctrl->handler, struct vsp1_bru, ctrls);
	44
a16e2794 LP	45	switch (ctrl->id) {
a16e2794 LP	46	case V4L2_CID_BG_COLOR:
f22af945	47	bru->bgcolor = ctrl->val;
a16e2794 LP	48	break;
	49	}
	50
	51	return 0;
	52	}
	53
	54	static const struct v4l2_ctrl_ops bru_ctrl_ops = {
	55	.s_ctrl = bru_s_ctrl,
	56	};
	57
629bb6d4 LP	58	/* -----------------------------------------------------------------------------
	59	* V4L2 Subdevice Core Operations
	60	*/
	61
629bb6d4 LP	62	static int bru_s_stream(struct v4l2_subdev *subdev, int enable)
629bb6d4 LP	63	{
9aca813e	64	struct vsp1_pipeline *pipe = to_vsp1_pipeline(&subdev->entity);
629bb6d4 LP	65	struct vsp1_bru *bru = to_bru(subdev);
629bb6d4 LP	66	struct v4l2_mbus_framefmt *format;
9aca813e	67	unsigned int flags;
629bb6d4	68	unsigned int i;
a16e2794	69
629bb6d4 LP	70	if (!enable)
	71	return 0;
	72
e790c3cb LP	73	format = vsp1_entity_get_pad_format(&bru->entity, bru->entity.config,
e790c3cb LP	74	bru->entity.source_pad);
629bb6d4 LP	75
	76	/* The hardware is extremely flexible but we have no userspace API to
	77	* expose all the parameters, nor is it clear whether we would have use
	78	* cases for all the supported modes. Let's just harcode the parameters
	79	* to sane default values for now.
	80	*/
	81
9aca813e LP	82	/* Disable dithering and enable color data normalization unless the
	83	* format at the pipeline output is premultiplied.
	84	*/
86960eec	85	flags = pipe->output ? pipe->output->format.flags : 0;
9aca813e LP	86	vsp1_bru_write(bru, VI6_BRU_INCTRL,
	87	flags & V4L2_PIX_FMT_FLAG_PREMUL_ALPHA ?
	88	0 : VI6_BRU_INCTRL_NRM);
629bb6d4	89
f22af945 LP	90	/* Set the background position to cover the whole output image and
	91	* configure its color.
	92	*/
629bb6d4 LP	93	vsp1_bru_write(bru, VI6_BRU_VIRRPF_SIZE,
	94	(format->width << VI6_BRU_VIRRPF_SIZE_HSIZE_SHIFT) \|
	95	(format->height << VI6_BRU_VIRRPF_SIZE_VSIZE_SHIFT));
	96	vsp1_bru_write(bru, VI6_BRU_VIRRPF_LOC, 0);
629bb6d4	97
f22af945 LP	98	vsp1_bru_write(bru, VI6_BRU_VIRRPF_COL, bru->bgcolor \|
	99	(0xff << VI6_BRU_VIRRPF_COL_A_SHIFT));
	100
629bb6d4 LP	101	/* Route BRU input 1 as SRC input to the ROP unit and configure the ROP
	102	* unit with a NOP operation to make BRU input 1 available as the
	103	* Blend/ROP unit B SRC input.
	104	*/
	105	vsp1_bru_write(bru, VI6_BRU_ROP, VI6_BRU_ROP_DSTSEL_BRUIN(1) \|
	106	VI6_BRU_ROP_CROP(VI6_ROP_NOP) \|
	107	VI6_BRU_ROP_AROP(VI6_ROP_NOP));
	108
a96c5fa4	109	for (i = 0; i < bru->entity.source_pad; ++i) {
6418b4d6	110	bool premultiplied = false;
629bb6d4 LP	111	u32 ctrl = 0;
	112
	113	/* Configure all Blend/ROP units corresponding to an enabled BRU
	114	* input for alpha blending. Blend/ROP units corresponding to
	115	* disabled BRU inputs are used in ROP NOP mode to ignore the
	116	* SRC input.
	117	*/
6418b4d6	118	if (bru->inputs[i].rpf) {
629bb6d4	119	ctrl \|= VI6_BRU_CTRL_RBC;
6418b4d6	120
86960eec	121	premultiplied = bru->inputs[i].rpf->format.flags
6418b4d6 LP	122	& V4L2_PIX_FMT_FLAG_PREMUL_ALPHA;
6418b4d6 LP	123	} else {
629bb6d4 LP	124	ctrl \|= VI6_BRU_CTRL_CROP(VI6_ROP_NOP)
629bb6d4 LP	125	\| VI6_BRU_CTRL_AROP(VI6_ROP_NOP);
6418b4d6	126	}
629bb6d4 LP	127
	128	/* Select the virtual RPF as the Blend/ROP unit A DST input to
	129	* serve as a background color.
	130	*/
	131	if (i == 0)
	132	ctrl \|= VI6_BRU_CTRL_DSTSEL_VRPF;
	133
	134	/* Route BRU inputs 0 to 3 as SRC inputs to Blend/ROP units A to
	135	* D in that order. The Blend/ROP unit B SRC is hardwired to the
	136	* ROP unit output, the corresponding register bits must be set
	137	* to 0.
	138	*/
	139	if (i != 1)
	140	ctrl \|= VI6_BRU_CTRL_SRCSEL_BRUIN(i);
	141
	142	vsp1_bru_write(bru, VI6_BRU_CTRL(i), ctrl);
	143
	144	/* Harcode the blending formula to
	145	*
	146	* DSTc = DSTc * (1 - SRCa) + SRCc * SRCa
	147	* DSTa = DSTa * (1 - SRCa) + SRCa
6418b4d6 LP	148	*
	149	* when the SRC input isn't premultiplied, and to
	150	*
	151	* DSTc = DSTc * (1 - SRCa) + SRCc
	152	* DSTa = DSTa * (1 - SRCa) + SRCa
	153	*
	154	* otherwise.
629bb6d4 LP	155	*/
	156	vsp1_bru_write(bru, VI6_BRU_BLD(i),
	157	VI6_BRU_BLD_CCMDX_255_SRC_A \|
6418b4d6 LP	158	(premultiplied ? VI6_BRU_BLD_CCMDY_COEFY :
6418b4d6 LP	159	VI6_BRU_BLD_CCMDY_SRC_A) \|
629bb6d4 LP	160	VI6_BRU_BLD_ACMDX_255_SRC_A \|
	161	VI6_BRU_BLD_ACMDY_COEFY \|
	162	(0xff << VI6_BRU_BLD_COEFY_SHIFT));
	163	}
	164
	165	return 0;
	166	}
	167
	168	/* -----------------------------------------------------------------------------
	169	* V4L2 Subdevice Pad Operations
	170	*/
	171
	172	/*
	173	* The BRU can't perform format conversion, all sink and source formats must be
	174	* identical. We pick the format on the first sink pad (pad 0) and propagate it
	175	* to all other pads.
	176	*/
	177
	178	static int bru_enum_mbus_code(struct v4l2_subdev *subdev,
f7234138	179	struct v4l2_subdev_pad_config *cfg,
629bb6d4 LP	180	struct v4l2_subdev_mbus_code_enum *code)
	181	{
	182	static const unsigned int codes[] = {
27ffaeb0 BB	183	MEDIA_BUS_FMT_ARGB8888_1X32,
27ffaeb0 BB	184	MEDIA_BUS_FMT_AYUV8_1X32,
629bb6d4	185	};
3f1ccf16	186	struct vsp1_bru *bru = to_bru(subdev);
629bb6d4 LP	187
	188	if (code->pad == BRU_PAD_SINK(0)) {
	189	if (code->index >= ARRAY_SIZE(codes))
	190	return -EINVAL;
	191
	192	code->code = codes[code->index];
	193	} else {
e790c3cb LP	194	struct v4l2_subdev_pad_config *config;
	195	struct v4l2_mbus_framefmt *format;
	196
629bb6d4 LP	197	if (code->index)
	198	return -EINVAL;
	199
e790c3cb	200	config = vsp1_entity_get_pad_config(&bru->entity, cfg,
1bd0a1bd	201	code->which);
e790c3cb LP	202	if (!config)
	203	return -EINVAL;
	204
	205	format = vsp1_entity_get_pad_format(&bru->entity, config,
	206	BRU_PAD_SINK(0));
629bb6d4 LP	207	code->code = format->code;
	208	}
	209
	210	return 0;
	211	}
	212
	213	static int bru_enum_frame_size(struct v4l2_subdev *subdev,
f7234138	214	struct v4l2_subdev_pad_config *cfg,
629bb6d4 LP	215	struct v4l2_subdev_frame_size_enum *fse)
	216	{
	217	if (fse->index)
	218	return -EINVAL;
	219
27ffaeb0 BB	220	if (fse->code != MEDIA_BUS_FMT_ARGB8888_1X32 &&
27ffaeb0 BB	221	fse->code != MEDIA_BUS_FMT_AYUV8_1X32)
629bb6d4 LP	222	return -EINVAL;
	223
	224	fse->min_width = BRU_MIN_SIZE;
	225	fse->max_width = BRU_MAX_SIZE;
	226	fse->min_height = BRU_MIN_SIZE;
	227	fse->max_height = BRU_MAX_SIZE;
	228
	229	return 0;
	230	}
	231
	232	static struct v4l2_rect bru_get_compose(struct vsp1_bru bru,
f7234138	233	struct v4l2_subdev_pad_config *cfg,
629bb6d4 LP	234	unsigned int pad, u32 which)
	235	{
	236	switch (which) {
	237	case V4L2_SUBDEV_FORMAT_TRY:
21b3d736 LP	238	return v4l2_subdev_get_try_compose(&bru->entity.subdev, cfg,
21b3d736 LP	239	pad);
629bb6d4	240	case V4L2_SUBDEV_FORMAT_ACTIVE:
6418b4d6	241	return &bru->inputs[pad].compose;
629bb6d4 LP	242	default:
	243	return NULL;
	244	}
	245	}
	246
1bd0a1bd LP	247	static int bru_get_format(struct v4l2_subdev *subdev,
1bd0a1bd LP	248	struct v4l2_subdev_pad_config *cfg,
629bb6d4 LP	249	struct v4l2_subdev_format *fmt)
	250	{
	251	struct vsp1_bru *bru = to_bru(subdev);
e790c3cb LP	252	struct v4l2_subdev_pad_config *config;
	253
	254	config = vsp1_entity_get_pad_config(&bru->entity, cfg, fmt->which);
	255	if (!config)
	256	return -EINVAL;
629bb6d4	257
e790c3cb LP	258	fmt->format = *vsp1_entity_get_pad_format(&bru->entity, config,
e790c3cb LP	259	fmt->pad);
629bb6d4 LP	260
	261	return 0;
	262	}
	263
1bd0a1bd	264	static void bru_try_format(struct vsp1_bru *bru,
e790c3cb LP	265	struct v4l2_subdev_pad_config *config,
e790c3cb LP	266	unsigned int pad, struct v4l2_mbus_framefmt *fmt)
629bb6d4 LP	267	{
	268	struct v4l2_mbus_framefmt *format;
	269
	270	switch (pad) {
	271	case BRU_PAD_SINK(0):
	272	/* Default to YUV if the requested format is not supported. */
27ffaeb0 BB	273	if (fmt->code != MEDIA_BUS_FMT_ARGB8888_1X32 &&
	274	fmt->code != MEDIA_BUS_FMT_AYUV8_1X32)
	275	fmt->code = MEDIA_BUS_FMT_AYUV8_1X32;
629bb6d4 LP	276	break;
	277
	278	default:
	279	/* The BRU can't perform format conversion. */
e790c3cb LP	280	format = vsp1_entity_get_pad_format(&bru->entity, config,
e790c3cb LP	281	BRU_PAD_SINK(0));
629bb6d4 LP	282	fmt->code = format->code;
	283	break;
	284	}
	285
	286	fmt->width = clamp(fmt->width, BRU_MIN_SIZE, BRU_MAX_SIZE);
	287	fmt->height = clamp(fmt->height, BRU_MIN_SIZE, BRU_MAX_SIZE);
	288	fmt->field = V4L2_FIELD_NONE;
	289	fmt->colorspace = V4L2_COLORSPACE_SRGB;
	290	}
	291
1bd0a1bd LP	292	static int bru_set_format(struct v4l2_subdev *subdev,
1bd0a1bd LP	293	struct v4l2_subdev_pad_config *cfg,
629bb6d4 LP	294	struct v4l2_subdev_format *fmt)
	295	{
	296	struct vsp1_bru *bru = to_bru(subdev);
e790c3cb	297	struct v4l2_subdev_pad_config *config;
629bb6d4 LP	298	struct v4l2_mbus_framefmt *format;
629bb6d4 LP	299
e790c3cb LP	300	config = vsp1_entity_get_pad_config(&bru->entity, cfg, fmt->which);
	301	if (!config)
	302	return -EINVAL;
	303
	304	bru_try_format(bru, config, fmt->pad, &fmt->format);
629bb6d4	305
e790c3cb	306	format = vsp1_entity_get_pad_format(&bru->entity, config, fmt->pad);
629bb6d4 LP	307	*format = fmt->format;
	308
	309	/* Reset the compose rectangle */
a96c5fa4	310	if (fmt->pad != bru->entity.source_pad) {
629bb6d4 LP	311	struct v4l2_rect *compose;
629bb6d4 LP	312
f7234138	313	compose = bru_get_compose(bru, cfg, fmt->pad, fmt->which);
629bb6d4 LP	314	compose->left = 0;
	315	compose->top = 0;
	316	compose->width = format->width;
	317	compose->height = format->height;
	318	}
	319
	320	/* Propagate the format code to all pads */
	321	if (fmt->pad == BRU_PAD_SINK(0)) {
	322	unsigned int i;
	323
a96c5fa4	324	for (i = 0; i <= bru->entity.source_pad; ++i) {
e790c3cb LP	325	format = vsp1_entity_get_pad_format(&bru->entity,
e790c3cb LP	326	config, i);
629bb6d4 LP	327	format->code = fmt->format.code;
	328	}
	329	}
	330
	331	return 0;
	332	}
	333
	334	static int bru_get_selection(struct v4l2_subdev *subdev,
f7234138	335	struct v4l2_subdev_pad_config *cfg,
629bb6d4 LP	336	struct v4l2_subdev_selection *sel)
	337	{
	338	struct vsp1_bru *bru = to_bru(subdev);
	339
a96c5fa4	340	if (sel->pad == bru->entity.source_pad)
629bb6d4 LP	341	return -EINVAL;
	342
	343	switch (sel->target) {
	344	case V4L2_SEL_TGT_COMPOSE_BOUNDS:
	345	sel->r.left = 0;
	346	sel->r.top = 0;
	347	sel->r.width = BRU_MAX_SIZE;
	348	sel->r.height = BRU_MAX_SIZE;
	349	return 0;
	350
	351	case V4L2_SEL_TGT_COMPOSE:
f7234138	352	sel->r = *bru_get_compose(bru, cfg, sel->pad, sel->which);
629bb6d4 LP	353	return 0;
	354
	355	default:
	356	return -EINVAL;
	357	}
	358	}
	359
	360	static int bru_set_selection(struct v4l2_subdev *subdev,
f7234138	361	struct v4l2_subdev_pad_config *cfg,
629bb6d4 LP	362	struct v4l2_subdev_selection *sel)
	363	{
	364	struct vsp1_bru *bru = to_bru(subdev);
e790c3cb	365	struct v4l2_subdev_pad_config *config;
629bb6d4 LP	366	struct v4l2_mbus_framefmt *format;
	367	struct v4l2_rect *compose;
	368
a96c5fa4	369	if (sel->pad == bru->entity.source_pad)
629bb6d4 LP	370	return -EINVAL;
	371
	372	if (sel->target != V4L2_SEL_TGT_COMPOSE)
	373	return -EINVAL;
	374
e790c3cb LP	375	config = vsp1_entity_get_pad_config(&bru->entity, cfg, sel->which);
	376	if (!config)
	377	return -EINVAL;
	378
629bb6d4 LP	379	/* The compose rectangle top left corner must be inside the output
	380	* frame.
	381	*/
e790c3cb LP	382	format = vsp1_entity_get_pad_format(&bru->entity, config,
e790c3cb LP	383	bru->entity.source_pad);
629bb6d4 LP	384	sel->r.left = clamp_t(unsigned int, sel->r.left, 0, format->width - 1);
	385	sel->r.top = clamp_t(unsigned int, sel->r.top, 0, format->height - 1);
	386
	387	/* Scaling isn't supported, the compose rectangle size must be identical
	388	* to the sink format size.
	389	*/
e790c3cb	390	format = vsp1_entity_get_pad_format(&bru->entity, config, sel->pad);
629bb6d4 LP	391	sel->r.width = format->width;
	392	sel->r.height = format->height;
	393
f7234138	394	compose = bru_get_compose(bru, cfg, sel->pad, sel->which);
629bb6d4 LP	395	*compose = sel->r;
	396
	397	return 0;
	398	}
	399
	400	/* -----------------------------------------------------------------------------
	401	* V4L2 Subdevice Operations
	402	*/
	403
	404	static struct v4l2_subdev_video_ops bru_video_ops = {
	405	.s_stream = bru_s_stream,
	406	};
	407
	408	static struct v4l2_subdev_pad_ops bru_pad_ops = {
0efdf0f5	409	.init_cfg = vsp1_entity_init_cfg,
629bb6d4 LP	410	.enum_mbus_code = bru_enum_mbus_code,
	411	.enum_frame_size = bru_enum_frame_size,
	412	.get_fmt = bru_get_format,
	413	.set_fmt = bru_set_format,
	414	.get_selection = bru_get_selection,
	415	.set_selection = bru_set_selection,
	416	};
	417
	418	static struct v4l2_subdev_ops bru_ops = {
	419	.video = &bru_video_ops,
	420	.pad = &bru_pad_ops,
	421	};
	422
	423	/* -----------------------------------------------------------------------------
	424	* Initialization and Cleanup
	425	*/
	426
	427	struct vsp1_bru vsp1_bru_create(struct vsp1_device vsp1)
	428	{
629bb6d4 LP	429	struct vsp1_bru *bru;
	430	int ret;
	431
	432	bru = devm_kzalloc(vsp1->dev, sizeof(*bru), GFP_KERNEL);
	433	if (bru == NULL)
	434	return ERR_PTR(-ENOMEM);
	435
	436	bru->entity.type = VSP1_ENTITY_BRU;
	437
823329df LP	438	ret = vsp1_entity_init(vsp1, &bru->entity, "bru",
823329df LP	439	vsp1->info->num_bru_inputs + 1, &bru_ops);
629bb6d4 LP	440	if (ret < 0)
	441	return ERR_PTR(ret);
	442
a16e2794 LP	443	/* Initialize the control handler. */
	444	v4l2_ctrl_handler_init(&bru->ctrls, 1);
	445	v4l2_ctrl_new_std(&bru->ctrls, &bru_ctrl_ops, V4L2_CID_BG_COLOR,
	446	0, 0xffffff, 1, 0);
	447
f22af945 LP	448	bru->bgcolor = 0;
f22af945 LP	449
a16e2794 LP	450	bru->entity.subdev.ctrl_handler = &bru->ctrls;
	451
	452	if (bru->ctrls.error) {
	453	dev_err(vsp1->dev, "bru: failed to initialize controls\n");
	454	ret = bru->ctrls.error;
	455	vsp1_entity_destroy(&bru->entity);
	456	return ERR_PTR(ret);
	457	}
	458
629bb6d4 LP	459	return bru;
629bb6d4 LP	460	}