[mirror_ubuntu-zesty-kernel.git] / drivers / media / platform / vsp1 / vsp1_drm.c

/*
 * vsp1_drm.c  --  R-Car VSP1 DRM API
 *
 * Copyright (C) 2015 Renesas Electronics Corporation
 *
 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/device.h>
#include <linux/slab.h>

#include <media/media-entity.h>
#include <media/v4l2-subdev.h>
#include <media/vsp1.h>

#include "vsp1.h"
#include "vsp1_bru.h"
#include "vsp1_dl.h"
#include "vsp1_drm.h"
#include "vsp1_lif.h"
#include "vsp1_pipe.h"
#include "vsp1_rwpf.h"


/* -----------------------------------------------------------------------------
 * Interrupt Handling
 */

void vsp1_drm_display_start(struct vsp1_device *vsp1)
{
	vsp1_dlm_irq_display_start(vsp1->drm->pipe.output->dlm);
}

/* -----------------------------------------------------------------------------
 * DU Driver API
 */

int vsp1_du_init(struct device *dev)
{
	struct vsp1_device *vsp1 = dev_get_drvdata(dev);

	if (!vsp1)
		return -EPROBE_DEFER;

	return 0;
}
EXPORT_SYMBOL_GPL(vsp1_du_init);

/**
 * vsp1_du_setup_lif - Setup the output part of the VSP pipeline
 * @dev: the VSP device
 * @width: output frame width in pixels
 * @height: output frame height in pixels
 *
 * Configure the output part of VSP DRM pipeline for the given frame @width and
 * @height. This sets up formats on the BRU source pad, the WPF0 sink and source
 * pads, and the LIF sink pad.
 *
 * As the media bus code on the BRU source pad is conditioned by the
 * configuration of the BRU sink 0 pad, we also set up the formats on all BRU
 * sinks, even if the configuration will be overwritten later by
 * vsp1_du_setup_rpf(). This ensures that the BRU configuration is set to a well
 * defined state.
 *
 * Return 0 on success or a negative error code on failure.
 */
int vsp1_du_setup_lif(struct device *dev, unsigned int width,
		      unsigned int height)
{
	struct vsp1_device *vsp1 = dev_get_drvdata(dev);
	struct vsp1_pipeline *pipe = &vsp1->drm->pipe;
	struct vsp1_bru *bru = vsp1->bru;
	struct v4l2_subdev_format format;
	unsigned int i;
	int ret;

	dev_dbg(vsp1->dev, "%s: configuring LIF with format %ux%u\n",
		__func__, width, height);

	if (width == 0 || height == 0) {
		/* Zero width or height means the CRTC is being disabled, stop
		 * the pipeline and turn the light off.
		 */
		ret = vsp1_pipeline_stop(pipe);
		if (ret == -ETIMEDOUT)
			dev_err(vsp1->dev, "DRM pipeline stop timeout\n");

		media_entity_pipeline_stop(&pipe->output->entity.subdev.entity);

		for (i = 0; i < bru->entity.source_pad; ++i) {
			bru->inputs[i].rpf = NULL;
			pipe->inputs[i] = NULL;
		}

		pipe->num_inputs = 0;

		vsp1_dlm_reset(pipe->output->dlm);
		vsp1_device_put(vsp1);

		dev_dbg(vsp1->dev, "%s: pipeline disabled\n", __func__);

		return 0;
	}

	/* Configure the format at the BRU sinks and propagate it through the
	 * pipeline.
	 */
	memset(&format, 0, sizeof(format));
	format.which = V4L2_SUBDEV_FORMAT_ACTIVE;

	for (i = 0; i < bru->entity.source_pad; ++i) {
		format.pad = i;

		format.format.width = width;
		format.format.height = height;
		format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32;
		format.format.field = V4L2_FIELD_NONE;

		ret = v4l2_subdev_call(&bru->entity.subdev, pad,
				       set_fmt, NULL, &format);
		if (ret < 0)
			return ret;

		dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on BRU pad %u\n",
			__func__, format.format.width, format.format.height,
			format.format.code, i);
	}

	format.pad = bru->entity.source_pad;
	format.format.width = width;
	format.format.height = height;
	format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32;
	format.format.field = V4L2_FIELD_NONE;

	ret = v4l2_subdev_call(&bru->entity.subdev, pad, set_fmt, NULL,
			       &format);
	if (ret < 0)
		return ret;

	dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on BRU pad %u\n",
		__func__, format.format.width, format.format.height,
		format.format.code, i);

	format.pad = RWPF_PAD_SINK;
	ret = v4l2_subdev_call(&vsp1->wpf[0]->entity.subdev, pad, set_fmt, NULL,
			       &format);
	if (ret < 0)
		return ret;

	dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on WPF0 sink\n",
		__func__, format.format.width, format.format.height,
		format.format.code);

	format.pad = RWPF_PAD_SOURCE;
	ret = v4l2_subdev_call(&vsp1->wpf[0]->entity.subdev, pad, get_fmt, NULL,
			       &format);
	if (ret < 0)
		return ret;

	dev_dbg(vsp1->dev, "%s: got format %ux%u (%x) on WPF0 source\n",
		__func__, format.format.width, format.format.height,
		format.format.code);

	format.pad = LIF_PAD_SINK;
	ret = v4l2_subdev_call(&vsp1->lif->entity.subdev, pad, set_fmt, NULL,
			       &format);
	if (ret < 0)
		return ret;

	dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on LIF sink\n",
		__func__, format.format.width, format.format.height,
		format.format.code);

	/* Verify that the format at the output of the pipeline matches the
	 * requested frame size and media bus code.
	 */
	if (format.format.width != width || format.format.height != height ||
	    format.format.code != MEDIA_BUS_FMT_ARGB8888_1X32) {
		dev_dbg(vsp1->dev, "%s: format mismatch\n", __func__);
		return -EPIPE;
	}

	/* Mark the pipeline as streaming and enable the VSP1. This will store
	 * the pipeline pointer in all entities, which the s_stream handlers
	 * will need. We don't start the entities themselves right at this point
	 * as there's no plane configured yet, so we can't start processing
	 * buffers.
	 */
	ret = vsp1_device_get(vsp1);
	if (ret < 0)
		return ret;

	ret = media_entity_pipeline_start(&pipe->output->entity.subdev.entity,
					  &pipe->pipe);
	if (ret < 0) {
		dev_dbg(vsp1->dev, "%s: pipeline start failed\n", __func__);
		vsp1_device_put(vsp1);
		return ret;
	}

	dev_dbg(vsp1->dev, "%s: pipeline enabled\n", __func__);

	return 0;
}
EXPORT_SYMBOL_GPL(vsp1_du_setup_lif);

/**
 * vsp1_du_atomic_begin - Prepare for an atomic update
 * @dev: the VSP device
 */
void vsp1_du_atomic_begin(struct device *dev)
{
	struct vsp1_device *vsp1 = dev_get_drvdata(dev);
	struct vsp1_pipeline *pipe = &vsp1->drm->pipe;
	unsigned long flags;

	spin_lock_irqsave(&pipe->irqlock, flags);

	vsp1->drm->num_inputs = pipe->num_inputs;

	spin_unlock_irqrestore(&pipe->irqlock, flags);

	/* Prepare the display list. */
	pipe->dl = vsp1_dl_list_get(pipe->output->dlm);
}
EXPORT_SYMBOL_GPL(vsp1_du_atomic_begin);

/**
 * vsp1_du_atomic_update - Setup one RPF input of the VSP pipeline
 * @dev: the VSP device
 * @rpf_index: index of the RPF to setup (0-based)
 * @pixelformat: V4L2 pixel format for the RPF memory input
 * @pitch: number of bytes per line in the image stored in memory
 * @mem: DMA addresses of the memory buffers (one per plane)
 * @src: the source crop rectangle for the RPF
 * @dst: the destination compose rectangle for the BRU input
 *
 * Configure the VSP to perform composition of the image referenced by @mem
 * through RPF @rpf_index, using the @src crop rectangle and the @dst
 * composition rectangle. The Z-order is fixed with RPF 0 at the bottom.
 *
 * Image format as stored in memory is expressed as a V4L2 @pixelformat value.
 * As a special case, setting the pixel format to 0 will disable the RPF. The
 * @pitch, @mem, @src and @dst parameters are ignored in that case. Calling the
 * function on a disabled RPF is allowed.
 *
 * The memory pitch is configurable to allow for padding at end of lines, or
 * simple for images that extend beyond the crop rectangle boundaries. The
 * @pitch value is expressed in bytes and applies to all planes for multiplanar
 * formats.
 *
 * The source memory buffer is referenced by the DMA address of its planes in
 * the @mem array. Up to two planes are supported. The second plane DMA address
 * is ignored for formats using a single plane.
 *
 * This function isn't reentrant, the caller needs to serialize calls.
 *
 * TODO: Implement Z-order control by decoupling the RPF index from the BRU
 * input index.
 *
 * Return 0 on success or a negative error code on failure.
 */
int vsp1_du_atomic_update(struct device *dev, unsigned int rpf_index,
			  u32 pixelformat, unsigned int pitch,
			  dma_addr_t mem[2], const struct v4l2_rect *src,
			  const struct v4l2_rect *dst)
{
	struct vsp1_device *vsp1 = dev_get_drvdata(dev);
	struct vsp1_pipeline *pipe = &vsp1->drm->pipe;
	const struct vsp1_format_info *fmtinfo;
	struct v4l2_subdev_selection sel;
	struct v4l2_subdev_format format;
	struct vsp1_rwpf *rpf;
	unsigned long flags;
	int ret;

	if (rpf_index >= vsp1->info->rpf_count)
		return -EINVAL;

	rpf = vsp1->rpf[rpf_index];

	if (pixelformat == 0) {
		dev_dbg(vsp1->dev, "%s: RPF%u: disable requested\n", __func__,
			rpf_index);

		spin_lock_irqsave(&pipe->irqlock, flags);

		if (pipe->inputs[rpf_index]) {
			/* Remove the RPF from the pipeline if it was previously
			 * enabled.
			 */
			vsp1->bru->inputs[rpf_index].rpf = NULL;
			pipe->inputs[rpf_index] = NULL;

			pipe->num_inputs--;
		}

		spin_unlock_irqrestore(&pipe->irqlock, flags);

		return 0;
	}

	dev_dbg(vsp1->dev,
		"%s: RPF%u: (%u,%u)/%ux%u -> (%u,%u)/%ux%u (%08x), pitch %u dma { %pad, %pad }\n",
		__func__, rpf_index,
		src->left, src->top, src->width, src->height,
		dst->left, dst->top, dst->width, dst->height,
		pixelformat, pitch, &mem[0], &mem[1]);

	/* Set the stride at the RPF input. */
	fmtinfo = vsp1_get_format_info(pixelformat);
	if (!fmtinfo) {
		dev_dbg(vsp1->dev, "Unsupport pixel format %08x for RPF\n",
			pixelformat);
		return -EINVAL;
	}

	rpf->fmtinfo = fmtinfo;
	rpf->format.num_planes = fmtinfo->planes;
	rpf->format.plane_fmt[0].bytesperline = pitch;
	rpf->format.plane_fmt[1].bytesperline = pitch;

	/* Configure the format on the RPF sink pad and propagate it up to the
	 * BRU sink pad.
	 */
	memset(&format, 0, sizeof(format));
	format.which = V4L2_SUBDEV_FORMAT_ACTIVE;
	format.pad = RWPF_PAD_SINK;
	format.format.width = src->width + src->left;
	format.format.height = src->height + src->top;
	format.format.code = fmtinfo->mbus;
	format.format.field = V4L2_FIELD_NONE;

	ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_fmt, NULL,
			       &format);
	if (ret < 0)
		return ret;

	dev_dbg(vsp1->dev,
		"%s: set format %ux%u (%x) on RPF%u sink\n",
		__func__, format.format.width, format.format.height,
		format.format.code, rpf->entity.index);

	memset(&sel, 0, sizeof(sel));
	sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
	sel.pad = RWPF_PAD_SINK;
	sel.target = V4L2_SEL_TGT_CROP;
	sel.r = *src;

	ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_selection, NULL,
			       &sel);
	if (ret < 0)
		return ret;

	dev_dbg(vsp1->dev,
		"%s: set selection (%u,%u)/%ux%u on RPF%u sink\n",
		__func__, sel.r.left, sel.r.top, sel.r.width, sel.r.height,
		rpf->entity.index);

	/* RPF source, hardcode the format to ARGB8888 to turn on format
	 * conversion if needed.
	 */
	format.pad = RWPF_PAD_SOURCE;

	ret = v4l2_subdev_call(&rpf->entity.subdev, pad, get_fmt, NULL,
			       &format);
	if (ret < 0)
		return ret;

	dev_dbg(vsp1->dev,
		"%s: got format %ux%u (%x) on RPF%u source\n",
		__func__, format.format.width, format.format.height,
		format.format.code, rpf->entity.index);

	format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32;

	ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_fmt, NULL,
			       &format);
	if (ret < 0)
		return ret;

	/* BRU sink, propagate the format from the RPF source. */
	format.pad = rpf->entity.index;

	ret = v4l2_subdev_call(&vsp1->bru->entity.subdev, pad, set_fmt, NULL,
			       &format);
	if (ret < 0)
		return ret;

	dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on BRU pad %u\n",
		__func__, format.format.width, format.format.height,
		format.format.code, format.pad);

	sel.pad = rpf->entity.index;
	sel.target = V4L2_SEL_TGT_COMPOSE;
	sel.r = *dst;

	ret = v4l2_subdev_call(&vsp1->bru->entity.subdev, pad, set_selection,
			       NULL, &sel);
	if (ret < 0)
		return ret;

	dev_dbg(vsp1->dev,
		"%s: set selection (%u,%u)/%ux%u on BRU pad %u\n",
		__func__, sel.r.left, sel.r.top, sel.r.width, sel.r.height,
		sel.pad);

	/* Store the BRU input pad number in the RPF. */
	rpf->bru_input = rpf->entity.index;

	/* Cache the memory buffer address but don't apply the values to the
	 * hardware as the crop offsets haven't been computed yet.
	 */
	rpf->mem.addr[0] = mem[0];
	rpf->mem.addr[1] = mem[1];
	rpf->mem.addr[2] = 0;

	spin_lock_irqsave(&pipe->irqlock, flags);

	/* If the RPF was previously stopped set the BRU input to the RPF and
	 * store the RPF in the pipeline inputs array.
	 */
	if (!pipe->inputs[rpf->entity.index]) {
		vsp1->bru->inputs[rpf_index].rpf = rpf;
		pipe->inputs[rpf->entity.index] = rpf;
		pipe->num_inputs++;
	}

	spin_unlock_irqrestore(&pipe->irqlock, flags);

	return 0;
}
EXPORT_SYMBOL_GPL(vsp1_du_atomic_update);

/**
 * vsp1_du_atomic_flush - Commit an atomic update
 * @dev: the VSP device
 */
void vsp1_du_atomic_flush(struct device *dev)
{
	struct vsp1_device *vsp1 = dev_get_drvdata(dev);
	struct vsp1_pipeline *pipe = &vsp1->drm->pipe;
	struct vsp1_entity *entity;
	unsigned long flags;
	bool stop = false;

	list_for_each_entry(entity, &pipe->entities, list_pipe) {
		/* Disconnect unused RPFs from the pipeline. */
		if (entity->type == VSP1_ENTITY_RPF) {
			struct vsp1_rwpf *rpf = to_rwpf(&entity->subdev);

			if (!pipe->inputs[rpf->entity.index]) {
				vsp1_dl_list_write(pipe->dl, entity->route->reg,
						   VI6_DPR_NODE_UNUSED);
				continue;
			}
		}

		vsp1_entity_route_setup(entity, pipe->dl);

		if (entity->ops->configure)
			entity->ops->configure(entity, pipe->dl);

		if (entity->type == VSP1_ENTITY_RPF)
			vsp1_rwpf_set_memory(to_rwpf(&entity->subdev),
					     pipe->dl);
	}

	vsp1_dl_list_commit(pipe->dl);
	pipe->dl = NULL;

	/* Start or stop the pipeline if needed. */
	spin_lock_irqsave(&pipe->irqlock, flags);

	if (!vsp1->drm->num_inputs && pipe->num_inputs) {
		vsp1_write(vsp1, VI6_DISP_IRQ_STA, 0);
		vsp1_write(vsp1, VI6_DISP_IRQ_ENB, VI6_DISP_IRQ_ENB_DSTE);
		vsp1_pipeline_run(pipe);
	} else if (vsp1->drm->num_inputs && !pipe->num_inputs) {
		stop = true;
	}

	spin_unlock_irqrestore(&pipe->irqlock, flags);

	if (stop) {
		vsp1_write(vsp1, VI6_DISP_IRQ_ENB, 0);
		vsp1_pipeline_stop(pipe);
	}
}
EXPORT_SYMBOL_GPL(vsp1_du_atomic_flush);

/* -----------------------------------------------------------------------------
 * Initialization
 */

int vsp1_drm_create_links(struct vsp1_device *vsp1)
{
	const u32 flags = MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE;
	unsigned int i;
	int ret;

	/* VSPD instances require a BRU to perform composition and a LIF to
	 * output to the DU.
	 */
	if (!vsp1->bru || !vsp1->lif)
		return -ENXIO;

	for (i = 0; i < vsp1->info->rpf_count; ++i) {
		struct vsp1_rwpf *rpf = vsp1->rpf[i];

		ret = media_create_pad_link(&rpf->entity.subdev.entity,
					    RWPF_PAD_SOURCE,
					    &vsp1->bru->entity.subdev.entity,
					    i, flags);
		if (ret < 0)
			return ret;

		rpf->entity.sink = &vsp1->bru->entity.subdev.entity;
		rpf->entity.sink_pad = i;
	}

	ret = media_create_pad_link(&vsp1->bru->entity.subdev.entity,
				    vsp1->bru->entity.source_pad,
				    &vsp1->wpf[0]->entity.subdev.entity,
				    RWPF_PAD_SINK, flags);
	if (ret < 0)
		return ret;

	vsp1->bru->entity.sink = &vsp1->wpf[0]->entity.subdev.entity;
	vsp1->bru->entity.sink_pad = RWPF_PAD_SINK;

	ret = media_create_pad_link(&vsp1->wpf[0]->entity.subdev.entity,
				    RWPF_PAD_SOURCE,
				    &vsp1->lif->entity.subdev.entity,
				    LIF_PAD_SINK, flags);
	if (ret < 0)
		return ret;

	return 0;
}

int vsp1_drm_init(struct vsp1_device *vsp1)
{
	struct vsp1_pipeline *pipe;
	unsigned int i;

	vsp1->drm = devm_kzalloc(vsp1->dev, sizeof(*vsp1->drm), GFP_KERNEL);
	if (!vsp1->drm)
		return -ENOMEM;

	pipe = &vsp1->drm->pipe;

	vsp1_pipeline_init(pipe);

	/* The DRM pipeline is static, add entities manually. */
	for (i = 0; i < vsp1->info->rpf_count; ++i) {
		struct vsp1_rwpf *input = vsp1->rpf[i];

		list_add_tail(&input->entity.list_pipe, &pipe->entities);
	}

	list_add_tail(&vsp1->bru->entity.list_pipe, &pipe->entities);
	list_add_tail(&vsp1->wpf[0]->entity.list_pipe, &pipe->entities);
	list_add_tail(&vsp1->lif->entity.list_pipe, &pipe->entities);

	pipe->bru = &vsp1->bru->entity;
	pipe->lif = &vsp1->lif->entity;
	pipe->output = vsp1->wpf[0];

	return 0;
}

void vsp1_drm_cleanup(struct vsp1_device *vsp1)
{
}
Commit	Line	Data
f3af9572 LP	1	/*
	2	* vsp1_drm.c -- R-Car VSP1 DRM API
	3	*
	4	* Copyright (C) 2015 Renesas Electronics Corporation
	5	*
	6	* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*/
	13
	14	#include <linux/device.h>
	15	#include <linux/slab.h>
f3af9572 LP	16
	17	#include <media/media-entity.h>
	18	#include <media/v4l2-subdev.h>
c1741af7	19	#include <media/vsp1.h>
f3af9572 LP	20
	21	#include "vsp1.h"
	22	#include "vsp1_bru.h"
1517b039	23	#include "vsp1_dl.h"
f3af9572 LP	24	#include "vsp1_drm.h"
	25	#include "vsp1_lif.h"
	26	#include "vsp1_pipe.h"
	27	#include "vsp1_rwpf.h"
	28
c2dd2513 LP	29
	30	/* -----------------------------------------------------------------------------
	31	* Interrupt Handling
	32	*/
	33
ef9621bc	34	void vsp1_drm_display_start(struct vsp1_device *vsp1)
c2dd2513	35	{
ef9621bc LP	36	vsp1_dlm_irq_display_start(vsp1->drm->pipe.output->dlm);
ef9621bc LP	37	}
c2dd2513	38
f3af9572 LP	39	/* -----------------------------------------------------------------------------
	40	* DU Driver API
	41	*/
	42
	43	int vsp1_du_init(struct device *dev)
	44	{
	45	struct vsp1_device *vsp1 = dev_get_drvdata(dev);
	46
	47	if (!vsp1)
	48	return -EPROBE_DEFER;
	49
	50	return 0;
	51	}
	52	EXPORT_SYMBOL_GPL(vsp1_du_init);
	53
	54	/**
	55	* vsp1_du_setup_lif - Setup the output part of the VSP pipeline
	56	* @dev: the VSP device
	57	* @width: output frame width in pixels
	58	* @height: output frame height in pixels
	59	*
	60	* Configure the output part of VSP DRM pipeline for the given frame @width and
	61	* @height. This sets up formats on the BRU source pad, the WPF0 sink and source
	62	* pads, and the LIF sink pad.
	63	*
	64	* As the media bus code on the BRU source pad is conditioned by the
	65	* configuration of the BRU sink 0 pad, we also set up the formats on all BRU
	66	* sinks, even if the configuration will be overwritten later by
	67	* vsp1_du_setup_rpf(). This ensures that the BRU configuration is set to a well
	68	* defined state.
	69	*
	70	* Return 0 on success or a negative error code on failure.
	71	*/
	72	int vsp1_du_setup_lif(struct device *dev, unsigned int width,
	73	unsigned int height)
	74	{
	75	struct vsp1_device *vsp1 = dev_get_drvdata(dev);
	76	struct vsp1_pipeline *pipe = &vsp1->drm->pipe;
	77	struct vsp1_bru *bru = vsp1->bru;
	78	struct v4l2_subdev_format format;
	79	unsigned int i;
	80	int ret;
	81
	82	dev_dbg(vsp1->dev, "%s: configuring LIF with format %ux%u\n",
	83	__func__, width, height);
	84
	85	if (width == 0 \|\| height == 0) {
	86	/* Zero width or height means the CRTC is being disabled, stop
	87	* the pipeline and turn the light off.
	88	*/
	89	ret = vsp1_pipeline_stop(pipe);
	90	if (ret == -ETIMEDOUT)
	91	dev_err(vsp1->dev, "DRM pipeline stop timeout\n");
	92
	93	media_entity_pipeline_stop(&pipe->output->entity.subdev.entity);
	94
	95	for (i = 0; i < bru->entity.source_pad; ++i) {
	96	bru->inputs[i].rpf = NULL;
	97	pipe->inputs[i] = NULL;
	98	}
	99
	100	pipe->num_inputs = 0;
	101
ef9621bc	102	vsp1_dlm_reset(pipe->output->dlm);
f3af9572 LP	103	vsp1_device_put(vsp1);
	104
	105	dev_dbg(vsp1->dev, "%s: pipeline disabled\n", __func__);
	106
	107	return 0;
	108	}
	109
	110	/* Configure the format at the BRU sinks and propagate it through the
	111	* pipeline.
	112	*/
	113	memset(&format, 0, sizeof(format));
	114	format.which = V4L2_SUBDEV_FORMAT_ACTIVE;
	115
	116	for (i = 0; i < bru->entity.source_pad; ++i) {
	117	format.pad = i;
	118
	119	format.format.width = width;
	120	format.format.height = height;
	121	format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32;
	122	format.format.field = V4L2_FIELD_NONE;
	123
	124	ret = v4l2_subdev_call(&bru->entity.subdev, pad,
	125	set_fmt, NULL, &format);
	126	if (ret < 0)
	127	return ret;
	128
	129	dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on BRU pad %u\n",
	130	__func__, format.format.width, format.format.height,
	131	format.format.code, i);
	132	}
	133
	134	format.pad = bru->entity.source_pad;
	135	format.format.width = width;
	136	format.format.height = height;
	137	format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32;
	138	format.format.field = V4L2_FIELD_NONE;
	139
	140	ret = v4l2_subdev_call(&bru->entity.subdev, pad, set_fmt, NULL,
	141	&format);
	142	if (ret < 0)
	143	return ret;
	144
	145	dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on BRU pad %u\n",
	146	__func__, format.format.width, format.format.height,
	147	format.format.code, i);
	148
	149	format.pad = RWPF_PAD_SINK;
	150	ret = v4l2_subdev_call(&vsp1->wpf[0]->entity.subdev, pad, set_fmt, NULL,
	151	&format);
	152	if (ret < 0)
	153	return ret;
	154
	155	dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on WPF0 sink\n",
	156	__func__, format.format.width, format.format.height,
	157	format.format.code);
	158
	159	format.pad = RWPF_PAD_SOURCE;
	160	ret = v4l2_subdev_call(&vsp1->wpf[0]->entity.subdev, pad, get_fmt, NULL,
	161	&format);
	162	if (ret < 0)
	163	return ret;
	164
	165	dev_dbg(vsp1->dev, "%s: got format %ux%u (%x) on WPF0 source\n",
	166	__func__, format.format.width, format.format.height,
167	format.format.code);
168
169	format.pad = LIF_PAD_SINK;
170	ret = v4l2_subdev_call(&vsp1->lif->entity.subdev, pad, set_fmt, NULL,
171	&format);
172	if (ret < 0)
173	return ret;
174
175	dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on LIF sink\n",
176	__func__, format.format.width, format.format.height,
177	format.format.code);
178
179	/* Verify that the format at the output of the pipeline matches the
180	* requested frame size and media bus code.
181	*/
182	if (format.format.width != width \|\| format.format.height != height \|\|
183	format.format.code != MEDIA_BUS_FMT_ARGB8888_1X32) {
184	dev_dbg(vsp1->dev, "%s: format mismatch\n", __func__);
185	return -EPIPE;
186	}
187
188	/* Mark the pipeline as streaming and enable the VSP1. This will store
189	* the pipeline pointer in all entities, which the s_stream handlers
190	* will need. We don't start the entities themselves right at this point
191	* as there's no plane configured yet, so we can't start processing
192	* buffers.
193	*/
194	ret = vsp1_device_get(vsp1);
195	if (ret < 0)
196	return ret;
197
198	ret = media_entity_pipeline_start(&pipe->output->entity.subdev.entity,
199	&pipe->pipe);
200	if (ret < 0) {
201	dev_dbg(vsp1->dev, "%s: pipeline start failed\n", __func__);
202	vsp1_device_put(vsp1);
203	return ret;
204	}
205
206	dev_dbg(vsp1->dev, "%s: pipeline enabled\n", __func__);
207
208	return 0;
209	}
210	EXPORT_SYMBOL_GPL(vsp1_du_setup_lif);
211
212	/**
7b4baddc LP	213	* vsp1_du_atomic_begin - Prepare for an atomic update
	214	* @dev: the VSP device
	215	*/
	216	void vsp1_du_atomic_begin(struct device *dev)
	217	{
	218	struct vsp1_device *vsp1 = dev_get_drvdata(dev);
	219	struct vsp1_pipeline *pipe = &vsp1->drm->pipe;
	220	unsigned long flags;
	221
	222	spin_lock_irqsave(&pipe->irqlock, flags);
	223
	224	vsp1->drm->num_inputs = pipe->num_inputs;
7b4baddc LP	225
7b4baddc LP	226	spin_unlock_irqrestore(&pipe->irqlock, flags);
1517b039 TS	227
1517b039 TS	228	/* Prepare the display list. */
ef9621bc	229	pipe->dl = vsp1_dl_list_get(pipe->output->dlm);
7b4baddc LP	230	}
	231	EXPORT_SYMBOL_GPL(vsp1_du_atomic_begin);
	232
	233	/**
	234	* vsp1_du_atomic_update - Setup one RPF input of the VSP pipeline
f3af9572 LP	235	* @dev: the VSP device
	236	* @rpf_index: index of the RPF to setup (0-based)
	237	* @pixelformat: V4L2 pixel format for the RPF memory input
	238	* @pitch: number of bytes per line in the image stored in memory
	239	* @mem: DMA addresses of the memory buffers (one per plane)
	240	* @src: the source crop rectangle for the RPF
	241	* @dst: the destination compose rectangle for the BRU input
	242	*
	243	* Configure the VSP to perform composition of the image referenced by @mem
	244	* through RPF @rpf_index, using the @src crop rectangle and the @dst
	245	* composition rectangle. The Z-order is fixed with RPF 0 at the bottom.
	246	*
	247	* Image format as stored in memory is expressed as a V4L2 @pixelformat value.
	248	* As a special case, setting the pixel format to 0 will disable the RPF. The
	249	* @pitch, @mem, @src and @dst parameters are ignored in that case. Calling the
	250	* function on a disabled RPF is allowed.
	251	*
	252	* The memory pitch is configurable to allow for padding at end of lines, or
	253	* simple for images that extend beyond the crop rectangle boundaries. The
	254	* @pitch value is expressed in bytes and applies to all planes for multiplanar
	255	* formats.
	256	*
	257	* The source memory buffer is referenced by the DMA address of its planes in
	258	* the @mem array. Up to two planes are supported. The second plane DMA address
	259	* is ignored for formats using a single plane.
	260	*
	261	* This function isn't reentrant, the caller needs to serialize calls.
	262	*
	263	* TODO: Implement Z-order control by decoupling the RPF index from the BRU
	264	* input index.
	265	*
	266	* Return 0 on success or a negative error code on failure.
	267	*/
7b4baddc LP	268	int vsp1_du_atomic_update(struct device *dev, unsigned int rpf_index,
	269	u32 pixelformat, unsigned int pitch,
	270	dma_addr_t mem[2], const struct v4l2_rect *src,
	271	const struct v4l2_rect *dst)
f3af9572 LP	272	{
	273	struct vsp1_device *vsp1 = dev_get_drvdata(dev);
	274	struct vsp1_pipeline *pipe = &vsp1->drm->pipe;
	275	const struct vsp1_format_info *fmtinfo;
	276	struct v4l2_subdev_selection sel;
	277	struct v4l2_subdev_format format;
f3af9572 LP	278	struct vsp1_rwpf *rpf;
f3af9572 LP	279	unsigned long flags;
f3af9572 LP	280	int ret;
f3af9572 LP	281
5aa2eb3c	282	if (rpf_index >= vsp1->info->rpf_count)
f3af9572 LP	283	return -EINVAL;
	284
	285	rpf = vsp1->rpf[rpf_index];
	286
	287	if (pixelformat == 0) {
	288	dev_dbg(vsp1->dev, "%s: RPF%u: disable requested\n", __func__,
	289	rpf_index);
	290
	291	spin_lock_irqsave(&pipe->irqlock, flags);
	292
	293	if (pipe->inputs[rpf_index]) {
	294	/* Remove the RPF from the pipeline if it was previously
	295	* enabled.
	296	*/
	297	vsp1->bru->inputs[rpf_index].rpf = NULL;
	298	pipe->inputs[rpf_index] = NULL;
	299
7b4baddc	300	pipe->num_inputs--;
f3af9572 LP	301	}
	302
	303	spin_unlock_irqrestore(&pipe->irqlock, flags);
	304
f3af9572 LP	305	return 0;
	306	}
	307
	308	dev_dbg(vsp1->dev,
	309	"%s: RPF%u: (%u,%u)/%ux%u -> (%u,%u)/%ux%u (%08x), pitch %u dma { %pad, %pad }\n",
	310	__func__, rpf_index,
	311	src->left, src->top, src->width, src->height,
	312	dst->left, dst->top, dst->width, dst->height,
	313	pixelformat, pitch, &mem[0], &mem[1]);
	314
	315	/* Set the stride at the RPF input. */
	316	fmtinfo = vsp1_get_format_info(pixelformat);
	317	if (!fmtinfo) {
	318	dev_dbg(vsp1->dev, "Unsupport pixel format %08x for RPF\n",
	319	pixelformat);
	320	return -EINVAL;
	321	}
	322
	323	rpf->fmtinfo = fmtinfo;
	324	rpf->format.num_planes = fmtinfo->planes;
	325	rpf->format.plane_fmt[0].bytesperline = pitch;
	326	rpf->format.plane_fmt[1].bytesperline = pitch;
	327
	328	/* Configure the format on the RPF sink pad and propagate it up to the
	329	* BRU sink pad.
	330	*/
	331	memset(&format, 0, sizeof(format));
	332	format.which = V4L2_SUBDEV_FORMAT_ACTIVE;
	333	format.pad = RWPF_PAD_SINK;
	334	format.format.width = src->width + src->left;
	335	format.format.height = src->height + src->top;
	336	format.format.code = fmtinfo->mbus;
	337	format.format.field = V4L2_FIELD_NONE;
	338
	339	ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_fmt, NULL,
	340	&format);
	341	if (ret < 0)
	342	return ret;
	343
	344	dev_dbg(vsp1->dev,
	345	"%s: set format %ux%u (%x) on RPF%u sink\n",
	346	__func__, format.format.width, format.format.height,
	347	format.format.code, rpf->entity.index);
	348
	349	memset(&sel, 0, sizeof(sel));
	350	sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
	351	sel.pad = RWPF_PAD_SINK;
	352	sel.target = V4L2_SEL_TGT_CROP;
	353	sel.r = *src;
	354
	355	ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_selection, NULL,
	356	&sel);
	357	if (ret < 0)
	358	return ret;
	359
	360	dev_dbg(vsp1->dev,
	361	"%s: set selection (%u,%u)/%ux%u on RPF%u sink\n",
	362	__func__, sel.r.left, sel.r.top, sel.r.width, sel.r.height,
	363	rpf->entity.index);
	364
	365	/* RPF source, hardcode the format to ARGB8888 to turn on format
	366	* conversion if needed.
	367	*/
	368	format.pad = RWPF_PAD_SOURCE;
369
370	ret = v4l2_subdev_call(&rpf->entity.subdev, pad, get_fmt, NULL,
371	&format);
372	if (ret < 0)
373	return ret;
374
375	dev_dbg(vsp1->dev,
376	"%s: got format %ux%u (%x) on RPF%u source\n",
377	__func__, format.format.width, format.format.height,
378	format.format.code, rpf->entity.index);
379
380	format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32;
381
382	ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_fmt, NULL,
383	&format);
384	if (ret < 0)
385	return ret;
386
387	/* BRU sink, propagate the format from the RPF source. */
388	format.pad = rpf->entity.index;
389
390	ret = v4l2_subdev_call(&vsp1->bru->entity.subdev, pad, set_fmt, NULL,
391	&format);
392	if (ret < 0)
393	return ret;
394
395	dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on BRU pad %u\n",
396	__func__, format.format.width, format.format.height,
397	format.format.code, format.pad);
398
399	sel.pad = rpf->entity.index;
400	sel.target = V4L2_SEL_TGT_COMPOSE;
401	sel.r = *dst;
402
403	ret = v4l2_subdev_call(&vsp1->bru->entity.subdev, pad, set_selection,
404	NULL, &sel);
405	if (ret < 0)
406	return ret;
407
408	dev_dbg(vsp1->dev,
409	"%s: set selection (%u,%u)/%ux%u on BRU pad %u\n",
410	__func__, sel.r.left, sel.r.top, sel.r.width, sel.r.height,
411	sel.pad);
412
b7e5107e LP	413	/* Store the BRU input pad number in the RPF. */
b7e5107e LP	414	rpf->bru_input = rpf->entity.index;
f3af9572	415
351bbf99	416	/* Cache the memory buffer address but don't apply the values to the
4d346be5 LP	417	* hardware as the crop offsets haven't been computed yet.
4d346be5 LP	418	*/
351bbf99 LP	419	rpf->mem.addr[0] = mem[0];
	420	rpf->mem.addr[1] = mem[1];
	421	rpf->mem.addr[2] = 0;
f3af9572 LP	422
	423	spin_lock_irqsave(&pipe->irqlock, flags);
	424
	425	/* If the RPF was previously stopped set the BRU input to the RPF and
	426	* store the RPF in the pipeline inputs array.
	427	*/
	428	if (!pipe->inputs[rpf->entity.index]) {
	429	vsp1->bru->inputs[rpf_index].rpf = rpf;
	430	pipe->inputs[rpf->entity.index] = rpf;
7b4baddc	431	pipe->num_inputs++;
f3af9572 LP	432	}
f3af9572 LP	433
7b4baddc LP	434	spin_unlock_irqrestore(&pipe->irqlock, flags);
	435
	436	return 0;
	437	}
	438	EXPORT_SYMBOL_GPL(vsp1_du_atomic_update);
	439
	440	/**
	441	* vsp1_du_atomic_flush - Commit an atomic update
	442	* @dev: the VSP device
	443	*/
	444	void vsp1_du_atomic_flush(struct device *dev)
	445	{
	446	struct vsp1_device *vsp1 = dev_get_drvdata(dev);
	447	struct vsp1_pipeline *pipe = &vsp1->drm->pipe;
1517b039	448	struct vsp1_entity *entity;
7b4baddc LP	449	unsigned long flags;
	450	bool stop = false;
	451
1517b039 TS	452	list_for_each_entry(entity, &pipe->entities, list_pipe) {
	453	/* Disconnect unused RPFs from the pipeline. */
	454	if (entity->type == VSP1_ENTITY_RPF) {
	455	struct vsp1_rwpf *rpf = to_rwpf(&entity->subdev);
	456
	457	if (!pipe->inputs[rpf->entity.index]) {
5e8dbbf3 LP	458	vsp1_dl_list_write(pipe->dl, entity->route->reg,
5e8dbbf3 LP	459	VI6_DPR_NODE_UNUSED);
1517b039 TS	460	continue;
	461	}
	462	}
	463
5e8dbbf3	464	vsp1_entity_route_setup(entity, pipe->dl);
1517b039	465
7b905f05	466	if (entity->ops->configure)
5e8dbbf3	467	entity->ops->configure(entity, pipe->dl);
351bbf99 LP	468
351bbf99 LP	469	if (entity->type == VSP1_ENTITY_RPF)
5e8dbbf3 LP	470	vsp1_rwpf_set_memory(to_rwpf(&entity->subdev),
5e8dbbf3 LP	471	pipe->dl);
1517b039 TS	472	}
1517b039 TS	473
c2dd2513 LP	474	vsp1_dl_list_commit(pipe->dl);
c2dd2513 LP	475	pipe->dl = NULL;
7b4baddc	476
351bbf99	477	/* Start or stop the pipeline if needed. */
1517b039	478	spin_lock_irqsave(&pipe->irqlock, flags);
7b4baddc	479
1517b039 TS	480	if (!vsp1->drm->num_inputs && pipe->num_inputs) {
	481	vsp1_write(vsp1, VI6_DISP_IRQ_STA, 0);
	482	vsp1_write(vsp1, VI6_DISP_IRQ_ENB, VI6_DISP_IRQ_ENB_DSTE);
	483	vsp1_pipeline_run(pipe);
	484	} else if (vsp1->drm->num_inputs && !pipe->num_inputs) {
7b4baddc	485	stop = true;
1517b039	486	}
f3af9572 LP	487
	488	spin_unlock_irqrestore(&pipe->irqlock, flags);
	489
1517b039 TS	490	if (stop) {
1517b039 TS	491	vsp1_write(vsp1, VI6_DISP_IRQ_ENB, 0);
7b4baddc	492	vsp1_pipeline_stop(pipe);
1517b039	493	}
f3af9572	494	}
7b4baddc	495	EXPORT_SYMBOL_GPL(vsp1_du_atomic_flush);
f3af9572 LP	496
	497	/* -----------------------------------------------------------------------------
	498	* Initialization
	499	*/
	500
	501	int vsp1_drm_create_links(struct vsp1_device *vsp1)
	502	{
	503	const u32 flags = MEDIA_LNK_FL_ENABLED \| MEDIA_LNK_FL_IMMUTABLE;
	504	unsigned int i;
	505	int ret;
	506
	507	/* VSPD instances require a BRU to perform composition and a LIF to
	508	* output to the DU.
	509	*/
	510	if (!vsp1->bru \|\| !vsp1->lif)
	511	return -ENXIO;
	512
5aa2eb3c	513	for (i = 0; i < vsp1->info->rpf_count; ++i) {
f3af9572 LP	514	struct vsp1_rwpf *rpf = vsp1->rpf[i];
	515
	516	ret = media_create_pad_link(&rpf->entity.subdev.entity,
	517	RWPF_PAD_SOURCE,
	518	&vsp1->bru->entity.subdev.entity,
	519	i, flags);
	520	if (ret < 0)
	521	return ret;
	522
	523	rpf->entity.sink = &vsp1->bru->entity.subdev.entity;
	524	rpf->entity.sink_pad = i;
	525	}
	526
	527	ret = media_create_pad_link(&vsp1->bru->entity.subdev.entity,
	528	vsp1->bru->entity.source_pad,
	529	&vsp1->wpf[0]->entity.subdev.entity,
	530	RWPF_PAD_SINK, flags);
	531	if (ret < 0)
	532	return ret;
	533
	534	vsp1->bru->entity.sink = &vsp1->wpf[0]->entity.subdev.entity;
	535	vsp1->bru->entity.sink_pad = RWPF_PAD_SINK;
	536
	537	ret = media_create_pad_link(&vsp1->wpf[0]->entity.subdev.entity,
	538	RWPF_PAD_SOURCE,
	539	&vsp1->lif->entity.subdev.entity,
	540	LIF_PAD_SINK, flags);
	541	if (ret < 0)
	542	return ret;
	543
	544	return 0;
	545	}
	546
	547	int vsp1_drm_init(struct vsp1_device *vsp1)
	548	{
	549	struct vsp1_pipeline *pipe;
	550	unsigned int i;
	551
	552	vsp1->drm = devm_kzalloc(vsp1->dev, sizeof(*vsp1->drm), GFP_KERNEL);
	553	if (!vsp1->drm)
	554	return -ENOMEM;
	555
	556	pipe = &vsp1->drm->pipe;
	557
	558	vsp1_pipeline_init(pipe);
f3af9572 LP	559
f3af9572 LP	560	/* The DRM pipeline is static, add entities manually. */
5aa2eb3c	561	for (i = 0; i < vsp1->info->rpf_count; ++i) {
f3af9572 LP	562	struct vsp1_rwpf *input = vsp1->rpf[i];
	563
	564	list_add_tail(&input->entity.list_pipe, &pipe->entities);
	565	}
	566
	567	list_add_tail(&vsp1->bru->entity.list_pipe, &pipe->entities);
	568	list_add_tail(&vsp1->wpf[0]->entity.list_pipe, &pipe->entities);
	569	list_add_tail(&vsp1->lif->entity.list_pipe, &pipe->entities);
	570
	571	pipe->bru = &vsp1->bru->entity;
	572	pipe->lif = &vsp1->lif->entity;
	573	pipe->output = vsp1->wpf[0];
	574
	575	return 0;
	576	}
1517b039 TS	577
	578	void vsp1_drm_cleanup(struct vsp1_device *vsp1)
	579	{
1517b039	580	}