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12ddbadf BG |
1 | /* |
2 | * Driver for Amlogic Meson IR remote receiver | |
3 | * | |
4 | * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * You should have received a copy of the GNU General Public License | |
11 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
12 | */ | |
13 | ||
14 | #include <linux/device.h> | |
15 | #include <linux/err.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/of_platform.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/spinlock.h> | |
e7a937b5 | 22 | #include <linux/bitfield.h> |
12ddbadf BG |
23 | |
24 | #include <media/rc-core.h> | |
25 | ||
26 | #define DRIVER_NAME "meson-ir" | |
27 | ||
6edf27ee | 28 | /* valid on all Meson platforms */ |
12ddbadf BG |
29 | #define IR_DEC_LDR_ACTIVE 0x00 |
30 | #define IR_DEC_LDR_IDLE 0x04 | |
31 | #define IR_DEC_LDR_REPEAT 0x08 | |
32 | #define IR_DEC_BIT_0 0x0c | |
33 | #define IR_DEC_REG0 0x10 | |
34 | #define IR_DEC_FRAME 0x14 | |
35 | #define IR_DEC_STATUS 0x18 | |
36 | #define IR_DEC_REG1 0x1c | |
6edf27ee NA |
37 | /* only available on Meson 8b and newer */ |
38 | #define IR_DEC_REG2 0x20 | |
12ddbadf | 39 | |
e7a937b5 | 40 | #define REG0_RATE_MASK GENMASK(11, 0) |
12ddbadf | 41 | |
6edf27ee NA |
42 | #define DECODE_MODE_NEC 0x0 |
43 | #define DECODE_MODE_RAW 0x2 | |
44 | ||
45 | /* Meson 6b uses REG1 to configure the mode */ | |
46 | #define REG1_MODE_MASK GENMASK(8, 7) | |
47 | #define REG1_MODE_SHIFT 7 | |
48 | ||
49 | /* Meson 8b / GXBB use REG2 to configure the mode */ | |
50 | #define REG2_MODE_MASK GENMASK(3, 0) | |
51 | #define REG2_MODE_SHIFT 0 | |
12ddbadf | 52 | |
e7a937b5 | 53 | #define REG1_TIME_IV_MASK GENMASK(28, 16) |
12ddbadf | 54 | |
e7a937b5 HK |
55 | #define REG1_IRQSEL_MASK GENMASK(3, 2) |
56 | #define REG1_IRQSEL_NEC_MODE 0 | |
57 | #define REG1_IRQSEL_RISE_FALL 1 | |
58 | #define REG1_IRQSEL_FALL 2 | |
59 | #define REG1_IRQSEL_RISE 3 | |
12ddbadf BG |
60 | |
61 | #define REG1_RESET BIT(0) | |
62 | #define REG1_ENABLE BIT(15) | |
63 | ||
64 | #define STATUS_IR_DEC_IN BIT(8) | |
65 | ||
66 | #define MESON_TRATE 10 /* us */ | |
67 | ||
68 | struct meson_ir { | |
69 | void __iomem *reg; | |
70 | struct rc_dev *rc; | |
12ddbadf BG |
71 | spinlock_t lock; |
72 | }; | |
73 | ||
74 | static void meson_ir_set_mask(struct meson_ir *ir, unsigned int reg, | |
75 | u32 mask, u32 value) | |
76 | { | |
77 | u32 data; | |
78 | ||
79 | data = readl(ir->reg + reg); | |
80 | data &= ~mask; | |
81 | data |= (value & mask); | |
82 | writel(data, ir->reg + reg); | |
83 | } | |
84 | ||
85 | static irqreturn_t meson_ir_irq(int irqno, void *dev_id) | |
86 | { | |
87 | struct meson_ir *ir = dev_id; | |
137edc02 | 88 | u32 duration, status; |
12ddbadf BG |
89 | DEFINE_IR_RAW_EVENT(rawir); |
90 | ||
91 | spin_lock(&ir->lock); | |
92 | ||
137edc02 | 93 | duration = readl_relaxed(ir->reg + IR_DEC_REG1); |
e7a937b5 | 94 | duration = FIELD_GET(REG1_TIME_IV_MASK, duration); |
12ddbadf BG |
95 | rawir.duration = US_TO_NS(duration * MESON_TRATE); |
96 | ||
137edc02 HK |
97 | status = readl_relaxed(ir->reg + IR_DEC_STATUS); |
98 | rawir.pulse = !!(status & STATUS_IR_DEC_IN); | |
12ddbadf | 99 | |
8d7a77ce | 100 | ir_raw_event_store_with_timeout(ir->rc, &rawir); |
12ddbadf BG |
101 | |
102 | spin_unlock(&ir->lock); | |
103 | ||
104 | return IRQ_HANDLED; | |
105 | } | |
106 | ||
107 | static int meson_ir_probe(struct platform_device *pdev) | |
108 | { | |
109 | struct device *dev = &pdev->dev; | |
110 | struct device_node *node = dev->of_node; | |
111 | struct resource *res; | |
112 | const char *map_name; | |
113 | struct meson_ir *ir; | |
1ffc931c | 114 | int irq, ret; |
12ddbadf BG |
115 | |
116 | ir = devm_kzalloc(dev, sizeof(struct meson_ir), GFP_KERNEL); | |
117 | if (!ir) | |
118 | return -ENOMEM; | |
119 | ||
120 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
121 | ir->reg = devm_ioremap_resource(dev, res); | |
122 | if (IS_ERR(ir->reg)) { | |
123 | dev_err(dev, "failed to map registers\n"); | |
124 | return PTR_ERR(ir->reg); | |
125 | } | |
126 | ||
1ffc931c HK |
127 | irq = platform_get_irq(pdev, 0); |
128 | if (irq < 0) { | |
12ddbadf | 129 | dev_err(dev, "no irq resource\n"); |
1ffc931c | 130 | return irq; |
12ddbadf BG |
131 | } |
132 | ||
705aa578 | 133 | ir->rc = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW); |
12ddbadf BG |
134 | if (!ir->rc) { |
135 | dev_err(dev, "failed to allocate rc device\n"); | |
136 | return -ENOMEM; | |
137 | } | |
138 | ||
139 | ir->rc->priv = ir; | |
518f4b26 | 140 | ir->rc->device_name = DRIVER_NAME; |
12ddbadf BG |
141 | ir->rc->input_phys = DRIVER_NAME "/input0"; |
142 | ir->rc->input_id.bustype = BUS_HOST; | |
143 | map_name = of_get_property(node, "linux,rc-map-name", NULL); | |
144 | ir->rc->map_name = map_name ? map_name : RC_MAP_EMPTY; | |
6d741bfe | 145 | ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER; |
12ddbadf BG |
146 | ir->rc->rx_resolution = US_TO_NS(MESON_TRATE); |
147 | ir->rc->timeout = MS_TO_NS(200); | |
148 | ir->rc->driver_name = DRIVER_NAME; | |
149 | ||
150 | spin_lock_init(&ir->lock); | |
151 | platform_set_drvdata(pdev, ir); | |
152 | ||
705aa578 | 153 | ret = devm_rc_register_device(dev, ir->rc); |
12ddbadf BG |
154 | if (ret) { |
155 | dev_err(dev, "failed to register rc device\n"); | |
705aa578 | 156 | return ret; |
12ddbadf BG |
157 | } |
158 | ||
611ee552 | 159 | ret = devm_request_irq(dev, irq, meson_ir_irq, 0, NULL, ir); |
12ddbadf BG |
160 | if (ret) { |
161 | dev_err(dev, "failed to request irq\n"); | |
705aa578 | 162 | return ret; |
12ddbadf BG |
163 | } |
164 | ||
165 | /* Reset the decoder */ | |
166 | meson_ir_set_mask(ir, IR_DEC_REG1, REG1_RESET, REG1_RESET); | |
167 | meson_ir_set_mask(ir, IR_DEC_REG1, REG1_RESET, 0); | |
6edf27ee NA |
168 | |
169 | /* Set general operation mode (= raw/software decoding) */ | |
170 | if (of_device_is_compatible(node, "amlogic,meson6-ir")) | |
171 | meson_ir_set_mask(ir, IR_DEC_REG1, REG1_MODE_MASK, | |
e7a937b5 | 172 | FIELD_PREP(REG1_MODE_MASK, DECODE_MODE_RAW)); |
6edf27ee NA |
173 | else |
174 | meson_ir_set_mask(ir, IR_DEC_REG2, REG2_MODE_MASK, | |
e7a937b5 | 175 | FIELD_PREP(REG2_MODE_MASK, DECODE_MODE_RAW)); |
6edf27ee | 176 | |
12ddbadf BG |
177 | /* Set rate */ |
178 | meson_ir_set_mask(ir, IR_DEC_REG0, REG0_RATE_MASK, MESON_TRATE - 1); | |
179 | /* IRQ on rising and falling edges */ | |
180 | meson_ir_set_mask(ir, IR_DEC_REG1, REG1_IRQSEL_MASK, | |
e7a937b5 | 181 | FIELD_PREP(REG1_IRQSEL_MASK, REG1_IRQSEL_RISE_FALL)); |
12ddbadf BG |
182 | /* Enable the decoder */ |
183 | meson_ir_set_mask(ir, IR_DEC_REG1, REG1_ENABLE, REG1_ENABLE); | |
184 | ||
185 | dev_info(dev, "receiver initialized\n"); | |
186 | ||
187 | return 0; | |
12ddbadf BG |
188 | } |
189 | ||
190 | static int meson_ir_remove(struct platform_device *pdev) | |
191 | { | |
192 | struct meson_ir *ir = platform_get_drvdata(pdev); | |
193 | unsigned long flags; | |
194 | ||
195 | /* Disable the decoder */ | |
196 | spin_lock_irqsave(&ir->lock, flags); | |
197 | meson_ir_set_mask(ir, IR_DEC_REG1, REG1_ENABLE, 0); | |
198 | spin_unlock_irqrestore(&ir->lock, flags); | |
199 | ||
12ddbadf BG |
200 | return 0; |
201 | } | |
202 | ||
2aa1bd1c AD |
203 | static void meson_ir_shutdown(struct platform_device *pdev) |
204 | { | |
205 | struct device *dev = &pdev->dev; | |
206 | struct device_node *node = dev->of_node; | |
207 | struct meson_ir *ir = platform_get_drvdata(pdev); | |
208 | unsigned long flags; | |
209 | ||
210 | spin_lock_irqsave(&ir->lock, flags); | |
211 | ||
212 | /* | |
213 | * Set operation mode to NEC/hardware decoding to give | |
214 | * bootloader a chance to power the system back on | |
215 | */ | |
216 | if (of_device_is_compatible(node, "amlogic,meson6-ir")) | |
217 | meson_ir_set_mask(ir, IR_DEC_REG1, REG1_MODE_MASK, | |
218 | DECODE_MODE_NEC << REG1_MODE_SHIFT); | |
219 | else | |
220 | meson_ir_set_mask(ir, IR_DEC_REG2, REG2_MODE_MASK, | |
221 | DECODE_MODE_NEC << REG2_MODE_SHIFT); | |
222 | ||
223 | /* Set rate to default value */ | |
224 | meson_ir_set_mask(ir, IR_DEC_REG0, REG0_RATE_MASK, 0x13); | |
225 | ||
226 | spin_unlock_irqrestore(&ir->lock, flags); | |
227 | } | |
228 | ||
12ddbadf BG |
229 | static const struct of_device_id meson_ir_match[] = { |
230 | { .compatible = "amlogic,meson6-ir" }, | |
6edf27ee NA |
231 | { .compatible = "amlogic,meson8b-ir" }, |
232 | { .compatible = "amlogic,meson-gxbb-ir" }, | |
12ddbadf BG |
233 | { }, |
234 | }; | |
5bb50fe7 | 235 | MODULE_DEVICE_TABLE(of, meson_ir_match); |
12ddbadf BG |
236 | |
237 | static struct platform_driver meson_ir_driver = { | |
238 | .probe = meson_ir_probe, | |
239 | .remove = meson_ir_remove, | |
2aa1bd1c | 240 | .shutdown = meson_ir_shutdown, |
12ddbadf BG |
241 | .driver = { |
242 | .name = DRIVER_NAME, | |
243 | .of_match_table = meson_ir_match, | |
244 | }, | |
245 | }; | |
246 | ||
247 | module_platform_driver(meson_ir_driver); | |
248 | ||
249 | MODULE_DESCRIPTION("Amlogic Meson IR remote receiver driver"); | |
250 | MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>"); | |
251 | MODULE_LICENSE("GPL v2"); |