[mirror_ubuntu-jammy-kernel.git] / drivers / media / rc / mtk-cir.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Driver for Mediatek IR Receiver Controller
 *
 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
 */

#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/reset.h>
#include <media/rc-core.h>

#define MTK_IR_DEV KBUILD_MODNAME

/* Register to enable PWM and IR */
#define MTK_CONFIG_HIGH_REG       0x0c

/* Bit to enable IR pulse width detection */
#define MTK_PWM_EN		  BIT(13)

/*
 * Register to setting ok count whose unit based on hardware sampling period
 * indicating IR receiving completion and then making IRQ fires
 */
#define MTK_OK_COUNT(x)		  (((x) & GENMASK(23, 16)) << 16)

/* Bit to enable IR hardware function */
#define MTK_IR_EN		  BIT(0)

/* Bit to restart IR receiving */
#define MTK_IRCLR		  BIT(0)

/* Fields containing pulse width data */
#define MTK_WIDTH_MASK		  (GENMASK(7, 0))

/* Bit to enable interrupt */
#define MTK_IRINT_EN		  BIT(0)

/* Bit to clear interrupt status */
#define MTK_IRINT_CLR		  BIT(0)

/* Maximum count of samples */
#define MTK_MAX_SAMPLES		  0xff
/* Indicate the end of IR message */
#define MTK_IR_END(v, p)	  ((v) == MTK_MAX_SAMPLES && (p) == 0)
/* Number of registers to record the pulse width */
#define MTK_CHKDATA_SZ		  17
/* Sample period in ns */
#define MTK_IR_SAMPLE		  46000

enum mtk_fields {
	/* Register to setting software sampling period */
	MTK_CHK_PERIOD,
	/* Register to setting hardware sampling period */
	MTK_HW_PERIOD,
};

enum mtk_regs {
	/* Register to clear state of state machine */
	MTK_IRCLR_REG,
	/* Register containing pulse width data */
	MTK_CHKDATA_REG,
	/* Register to enable IR interrupt */
	MTK_IRINT_EN_REG,
	/* Register to ack IR interrupt */
	MTK_IRINT_CLR_REG
};

static const u32 mt7623_regs[] = {
	[MTK_IRCLR_REG] =	0x20,
	[MTK_CHKDATA_REG] =	0x88,
	[MTK_IRINT_EN_REG] =	0xcc,
	[MTK_IRINT_CLR_REG] =	0xd0,
};

static const u32 mt7622_regs[] = {
	[MTK_IRCLR_REG] =	0x18,
	[MTK_CHKDATA_REG] =	0x30,
	[MTK_IRINT_EN_REG] =	0x1c,
	[MTK_IRINT_CLR_REG] =	0x20,
};

struct mtk_field_type {
	u32 reg;
	u8 offset;
	u32 mask;
};

/*
 * struct mtk_ir_data -	This is the structure holding all differences among
			various hardwares
 * @regs:		The pointer to the array holding registers offset
 * @fields:		The pointer to the array holding fields location
 * @div:		The internal divisor for the based reference clock
 * @ok_count:		The count indicating the completion of IR data
 *			receiving when count is reached
 * @hw_period:		The value indicating the hardware sampling period
 */
struct mtk_ir_data {
	const u32 *regs;
	const struct mtk_field_type *fields;
	u8 div;
	u8 ok_count;
	u32 hw_period;
};

static const struct mtk_field_type mt7623_fields[] = {
	[MTK_CHK_PERIOD] = {0x10, 8, GENMASK(20, 8)},
	[MTK_HW_PERIOD] = {0x10, 0, GENMASK(7, 0)},
};

static const struct mtk_field_type mt7622_fields[] = {
	[MTK_CHK_PERIOD] = {0x24, 0, GENMASK(24, 0)},
	[MTK_HW_PERIOD] = {0x10, 0, GENMASK(24, 0)},
};

/*
 * struct mtk_ir -	This is the main datasructure for holding the state
 *			of the driver
 * @dev:		The device pointer
 * @rc:			The rc instrance
 * @base:		The mapped register i/o base
 * @irq:		The IRQ that we are using
 * @clk:		The clock that IR internal is using
 * @bus:		The clock that software decoder is using
 * @data:		Holding specific data for vaious platform
 */
struct mtk_ir {
	struct device	*dev;
	struct rc_dev	*rc;
	void __iomem	*base;
	int		irq;
	struct clk	*clk;
	struct clk	*bus;
	const struct mtk_ir_data *data;
};

static inline u32 mtk_chkdata_reg(struct mtk_ir *ir, u32 i)
{
	return ir->data->regs[MTK_CHKDATA_REG] + 4 * i;
}

static inline u32 mtk_chk_period(struct mtk_ir *ir)
{
	u32 val;

	/* Period of raw software sampling in ns */
	val = DIV_ROUND_CLOSEST(1000000000ul,
				clk_get_rate(ir->bus) / ir->data->div);

	/*
	 * Period for software decoder used in the
	 * unit of raw software sampling
	 */
	val = DIV_ROUND_CLOSEST(MTK_IR_SAMPLE, val);

	dev_dbg(ir->dev, "@pwm clk  = \t%lu\n",
		clk_get_rate(ir->bus) / ir->data->div);
	dev_dbg(ir->dev, "@chkperiod = %08x\n", val);

	return val;
}

static void mtk_w32_mask(struct mtk_ir *ir, u32 val, u32 mask, unsigned int reg)
{
	u32 tmp;

	tmp = __raw_readl(ir->base + reg);
	tmp = (tmp & ~mask) | val;
	__raw_writel(tmp, ir->base + reg);
}

static void mtk_w32(struct mtk_ir *ir, u32 val, unsigned int reg)
{
	__raw_writel(val, ir->base + reg);
}

static u32 mtk_r32(struct mtk_ir *ir, unsigned int reg)
{
	return __raw_readl(ir->base + reg);
}

static inline void mtk_irq_disable(struct mtk_ir *ir, u32 mask)
{
	u32 val;

	val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]);
	mtk_w32(ir, val & ~mask, ir->data->regs[MTK_IRINT_EN_REG]);
}

static inline void mtk_irq_enable(struct mtk_ir *ir, u32 mask)
{
	u32 val;

	val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]);
	mtk_w32(ir, val | mask, ir->data->regs[MTK_IRINT_EN_REG]);
}

static irqreturn_t mtk_ir_irq(int irqno, void *dev_id)
{
	struct mtk_ir *ir = dev_id;
	u8  wid = 0;
	u32 i, j, val;
	struct ir_raw_event rawir = {};

	/*
	 * Reset decoder state machine explicitly is required
	 * because 1) the longest duration for space MTK IR hardware
	 * could record is not safely long. e.g  12ms if rx resolution
	 * is 46us by default. There is still the risk to satisfying
	 * every decoder to reset themselves through long enough
	 * trailing spaces and 2) the IRQ handler guarantees that
	 * start of IR message is always contained in and starting
	 * from register mtk_chkdata_reg(ir, i).
	 */
	ir_raw_event_reset(ir->rc);

	/* First message must be pulse */
	rawir.pulse = false;

	/* Handle all pulse and space IR controller captures */
	for (i = 0 ; i < MTK_CHKDATA_SZ ; i++) {
		val = mtk_r32(ir, mtk_chkdata_reg(ir, i));
		dev_dbg(ir->dev, "@reg%d=0x%08x\n", i, val);

		for (j = 0 ; j < 4 ; j++) {
			wid = (val & (MTK_WIDTH_MASK << j * 8)) >> j * 8;
			rawir.pulse = !rawir.pulse;
			rawir.duration = wid * (MTK_IR_SAMPLE + 1);
			ir_raw_event_store_with_filter(ir->rc, &rawir);
		}
	}

	/*
	 * The maximum number of edges the IR controller can
	 * hold is MTK_CHKDATA_SZ * 4. So if received IR messages
	 * is over the limit, the last incomplete IR message would
	 * be appended trailing space and still would be sent into
	 * ir-rc-raw to decode. That helps it is possible that it
	 * has enough information to decode a scancode even if the
	 * trailing end of the message is missing.
	 */
	if (!MTK_IR_END(wid, rawir.pulse)) {
		rawir.pulse = false;
		rawir.duration = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1);
		ir_raw_event_store_with_filter(ir->rc, &rawir);
	}

	ir_raw_event_handle(ir->rc);

	/*
	 * Restart controller for the next receive that would
	 * clear up all CHKDATA registers
	 */
	mtk_w32_mask(ir, 0x1, MTK_IRCLR, ir->data->regs[MTK_IRCLR_REG]);

	/* Clear interrupt status */
	mtk_w32_mask(ir, 0x1, MTK_IRINT_CLR,
		     ir->data->regs[MTK_IRINT_CLR_REG]);

	return IRQ_HANDLED;
}

static const struct mtk_ir_data mt7623_data = {
	.regs = mt7623_regs,
	.fields = mt7623_fields,
	.ok_count = 0xf,
	.hw_period = 0xff,
	.div	= 4,
};

static const struct mtk_ir_data mt7622_data = {
	.regs = mt7622_regs,
	.fields = mt7622_fields,
	.ok_count = 0xf,
	.hw_period = 0xffff,
	.div	= 32,
};

static const struct of_device_id mtk_ir_match[] = {
	{ .compatible = "mediatek,mt7623-cir", .data = &mt7623_data},
	{ .compatible = "mediatek,mt7622-cir", .data = &mt7622_data},
	{},
};
MODULE_DEVICE_TABLE(of, mtk_ir_match);

static int mtk_ir_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct device_node *dn = dev->of_node;
	struct resource *res;
	struct mtk_ir *ir;
	u32 val;
	int ret = 0;
	const char *map_name;

	ir = devm_kzalloc(dev, sizeof(struct mtk_ir), GFP_KERNEL);
	if (!ir)
		return -ENOMEM;

	ir->dev = dev;
	ir->data = of_device_get_match_data(dev);

	ir->clk = devm_clk_get(dev, "clk");
	if (IS_ERR(ir->clk)) {
		dev_err(dev, "failed to get a ir clock.\n");
		return PTR_ERR(ir->clk);
	}

	ir->bus = devm_clk_get(dev, "bus");
	if (IS_ERR(ir->bus)) {
		/*
		 * For compatibility with older device trees try unnamed
		 * ir->bus uses the same clock as ir->clock.
		 */
		ir->bus = ir->clk;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	ir->base = devm_ioremap_resource(dev, res);
	if (IS_ERR(ir->base)) {
		dev_err(dev, "failed to map registers\n");
		return PTR_ERR(ir->base);
	}

	ir->rc = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW);
	if (!ir->rc) {
		dev_err(dev, "failed to allocate device\n");
		return -ENOMEM;
	}

	ir->rc->priv = ir;
	ir->rc->device_name = MTK_IR_DEV;
	ir->rc->input_phys = MTK_IR_DEV "/input0";
	ir->rc->input_id.bustype = BUS_HOST;
	ir->rc->input_id.vendor = 0x0001;
	ir->rc->input_id.product = 0x0001;
	ir->rc->input_id.version = 0x0001;
	map_name = of_get_property(dn, "linux,rc-map-name", NULL);
	ir->rc->map_name = map_name ?: RC_MAP_EMPTY;
	ir->rc->dev.parent = dev;
	ir->rc->driver_name = MTK_IR_DEV;
	ir->rc->allowed_protocols = RC_PROTO_BIT_ALL;
	ir->rc->rx_resolution = MTK_IR_SAMPLE;
	ir->rc->timeout = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1);

	ret = devm_rc_register_device(dev, ir->rc);
	if (ret) {
		dev_err(dev, "failed to register rc device\n");
		return ret;
	}

	platform_set_drvdata(pdev, ir);

	ir->irq = platform_get_irq(pdev, 0);
	if (ir->irq < 0) {
		dev_err(dev, "no irq resource\n");
		return -ENODEV;
	}

	if (clk_prepare_enable(ir->clk)) {
		dev_err(dev, "try to enable ir_clk failed\n");
		return -EINVAL;
	}

	if (clk_prepare_enable(ir->bus)) {
		dev_err(dev, "try to enable ir_clk failed\n");
		ret = -EINVAL;
		goto exit_clkdisable_clk;
	}

	/*
	 * Enable interrupt after proper hardware
	 * setup and IRQ handler registration
	 */
	mtk_irq_disable(ir, MTK_IRINT_EN);

	ret = devm_request_irq(dev, ir->irq, mtk_ir_irq, 0, MTK_IR_DEV, ir);
	if (ret) {
		dev_err(dev, "failed request irq\n");
		goto exit_clkdisable_bus;
	}

	/*
	 * Setup software sample period as the reference of software decoder
	 */
	val = (mtk_chk_period(ir) << ir->data->fields[MTK_CHK_PERIOD].offset) &
	       ir->data->fields[MTK_CHK_PERIOD].mask;
	mtk_w32_mask(ir, val, ir->data->fields[MTK_CHK_PERIOD].mask,
		     ir->data->fields[MTK_CHK_PERIOD].reg);

	/*
	 * Setup hardware sampling period used to setup the proper timeout for
	 * indicating end of IR receiving completion
	 */
	val = (ir->data->hw_period << ir->data->fields[MTK_HW_PERIOD].offset) &
	       ir->data->fields[MTK_HW_PERIOD].mask;
	mtk_w32_mask(ir, val, ir->data->fields[MTK_HW_PERIOD].mask,
		     ir->data->fields[MTK_HW_PERIOD].reg);

	/* Enable IR and PWM */
	val = mtk_r32(ir, MTK_CONFIG_HIGH_REG);
	val |= MTK_OK_COUNT(ir->data->ok_count) |  MTK_PWM_EN | MTK_IR_EN;
	mtk_w32(ir, val, MTK_CONFIG_HIGH_REG);

	mtk_irq_enable(ir, MTK_IRINT_EN);

	dev_info(dev, "Initialized MT7623 IR driver, sample period = %dus\n",
		 DIV_ROUND_CLOSEST(MTK_IR_SAMPLE, 1000));

	return 0;

exit_clkdisable_bus:
	clk_disable_unprepare(ir->bus);
exit_clkdisable_clk:
	clk_disable_unprepare(ir->clk);

	return ret;
}

static int mtk_ir_remove(struct platform_device *pdev)
{
	struct mtk_ir *ir = platform_get_drvdata(pdev);

	/*
	 * Avoid contention between remove handler and
	 * IRQ handler so that disabling IR interrupt and
	 * waiting for pending IRQ handler to complete
	 */
	mtk_irq_disable(ir, MTK_IRINT_EN);
	synchronize_irq(ir->irq);

	clk_disable_unprepare(ir->bus);
	clk_disable_unprepare(ir->clk);

	return 0;
}

static struct platform_driver mtk_ir_driver = {
	.probe          = mtk_ir_probe,
	.remove         = mtk_ir_remove,
	.driver = {
		.name = MTK_IR_DEV,
		.of_match_table = mtk_ir_match,
	},
};

module_platform_driver(mtk_ir_driver);

MODULE_DESCRIPTION("Mediatek IR Receiver Controller Driver");
MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
c942fddf	1	// SPDX-License-Identifier: GPL-2.0-or-later
6691e7b9 SW	2	/*
	3	* Driver for Mediatek IR Receiver Controller
	4	*
	5	* Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
6691e7b9 SW	6	*/
	7
	8	#include <linux/clk.h>
	9	#include <linux/interrupt.h>
	10	#include <linux/module.h>
	11	#include <linux/of_platform.h>
	12	#include <linux/reset.h>
	13	#include <media/rc-core.h>
	14
	15	#define MTK_IR_DEV KBUILD_MODNAME
	16
	17	/* Register to enable PWM and IR */
	18	#define MTK_CONFIG_HIGH_REG 0x0c
50c3c1ba SW	19
50c3c1ba SW	20	/* Bit to enable IR pulse width detection */
6691e7b9	21	#define MTK_PWM_EN BIT(13)
6691e7b9	22
50c3c1ba SW	23	/*
	24	* Register to setting ok count whose unit based on hardware sampling period
	25	* indicating IR receiving completion and then making IRQ fires
	26	*/
	27	#define MTK_OK_COUNT(x) (((x) & GENMASK(23, 16)) << 16)
	28
	29	/* Bit to enable IR hardware function */
	30	#define MTK_IR_EN BIT(0)
6691e7b9	31
6691e7b9 SW	32	/* Bit to restart IR receiving */
	33	#define MTK_IRCLR BIT(0)
	34
50c3c1ba	35	/* Fields containing pulse width data */
6691e7b9 SW	36	#define MTK_WIDTH_MASK (GENMASK(7, 0))
6691e7b9 SW	37
6691e7b9 SW	38	/* Bit to enable interrupt */
	39	#define MTK_IRINT_EN BIT(0)
	40
6691e7b9 SW	41	/* Bit to clear interrupt status */
	42	#define MTK_IRINT_CLR BIT(0)
	43
	44	/* Maximum count of samples */
	45	#define MTK_MAX_SAMPLES 0xff
	46	/* Indicate the end of IR message */
	47	#define MTK_IR_END(v, p) ((v) == MTK_MAX_SAMPLES && (p) == 0)
	48	/* Number of registers to record the pulse width */
	49	#define MTK_CHKDATA_SZ 17
6691e7b9	50	/* Sample period in ns */
50c3c1ba SW	51	#define MTK_IR_SAMPLE 46000
	52
	53	enum mtk_fields {
	54	/* Register to setting software sampling period */
	55	MTK_CHK_PERIOD,
	56	/* Register to setting hardware sampling period */
	57	MTK_HW_PERIOD,
	58	};
	59
	60	enum mtk_regs {
	61	/* Register to clear state of state machine */
	62	MTK_IRCLR_REG,
	63	/* Register containing pulse width data */
	64	MTK_CHKDATA_REG,
	65	/* Register to enable IR interrupt */
	66	MTK_IRINT_EN_REG,
	67	/* Register to ack IR interrupt */
	68	MTK_IRINT_CLR_REG
	69	};
	70
	71	static const u32 mt7623_regs[] = {
	72	[MTK_IRCLR_REG] = 0x20,
	73	[MTK_CHKDATA_REG] = 0x88,
	74	[MTK_IRINT_EN_REG] = 0xcc,
	75	[MTK_IRINT_CLR_REG] = 0xd0,
	76	};
	77
58389982 SW	78	static const u32 mt7622_regs[] = {
	79	[MTK_IRCLR_REG] = 0x18,
	80	[MTK_CHKDATA_REG] = 0x30,
	81	[MTK_IRINT_EN_REG] = 0x1c,
	82	[MTK_IRINT_CLR_REG] = 0x20,
	83	};
	84
50c3c1ba SW	85	struct mtk_field_type {
	86	u32 reg;
	87	u8 offset;
	88	u32 mask;
	89	};
	90
	91	/*
	92	* struct mtk_ir_data - This is the structure holding all differences among
	93	various hardwares
	94	* @regs: The pointer to the array holding registers offset
	95	* @fields: The pointer to the array holding fields location
	96	* @div: The internal divisor for the based reference clock
	97	* @ok_count: The count indicating the completion of IR data
	98	* receiving when count is reached
	99	* @hw_period: The value indicating the hardware sampling period
	100	*/
	101	struct mtk_ir_data {
	102	const u32 *regs;
	103	const struct mtk_field_type *fields;
	104	u8 div;
	105	u8 ok_count;
	106	u32 hw_period;
	107	};
	108
	109	static const struct mtk_field_type mt7623_fields[] = {
	110	[MTK_CHK_PERIOD] = {0x10, 8, GENMASK(20, 8)},
	111	[MTK_HW_PERIOD] = {0x10, 0, GENMASK(7, 0)},
	112	};
6691e7b9	113
58389982 SW	114	static const struct mtk_field_type mt7622_fields[] = {
	115	[MTK_CHK_PERIOD] = {0x24, 0, GENMASK(24, 0)},
	116	[MTK_HW_PERIOD] = {0x10, 0, GENMASK(24, 0)},
	117	};
	118
6691e7b9 SW	119	/*
	120	* struct mtk_ir - This is the main datasructure for holding the state
	121	* of the driver
	122	* @dev: The device pointer
	123	* @rc: The rc instrance
6691e7b9	124	* @base: The mapped register i/o base
50c3c1ba SW	125	* @irq: The IRQ that we are using
	126	* @clk: The clock that IR internal is using
	127	* @bus: The clock that software decoder is using
	128	* @data: Holding specific data for vaious platform
6691e7b9 SW	129	*/
	130	struct mtk_ir {
	131	struct device *dev;
	132	struct rc_dev *rc;
	133	void __iomem *base;
	134	int irq;
	135	struct clk *clk;
50c3c1ba SW	136	struct clk *bus;
50c3c1ba SW	137	const struct mtk_ir_data *data;
6691e7b9 SW	138	};
6691e7b9 SW	139
50c3c1ba SW	140	static inline u32 mtk_chkdata_reg(struct mtk_ir *ir, u32 i)
	141	{
	142	return ir->data->regs[MTK_CHKDATA_REG] + 4 * i;
	143	}
	144
	145	static inline u32 mtk_chk_period(struct mtk_ir *ir)
	146	{
	147	u32 val;
	148
	149	/* Period of raw software sampling in ns */
	150	val = DIV_ROUND_CLOSEST(1000000000ul,
	151	clk_get_rate(ir->bus) / ir->data->div);
	152
	153	/*
	154	* Period for software decoder used in the
	155	* unit of raw software sampling
	156	*/
	157	val = DIV_ROUND_CLOSEST(MTK_IR_SAMPLE, val);
	158
	159	dev_dbg(ir->dev, "@pwm clk = \t%lu\n",
	160	clk_get_rate(ir->bus) / ir->data->div);
	161	dev_dbg(ir->dev, "@chkperiod = %08x\n", val);
	162
	163	return val;
	164	}
	165
6691e7b9 SW	166	static void mtk_w32_mask(struct mtk_ir *ir, u32 val, u32 mask, unsigned int reg)
	167	{
	168	u32 tmp;
	169
	170	tmp = __raw_readl(ir->base + reg);
	171	tmp = (tmp & ~mask) \| val;
	172	__raw_writel(tmp, ir->base + reg);
	173	}
	174
	175	static void mtk_w32(struct mtk_ir *ir, u32 val, unsigned int reg)
	176	{
	177	__raw_writel(val, ir->base + reg);
	178	}
	179
	180	static u32 mtk_r32(struct mtk_ir *ir, unsigned int reg)
	181	{
	182	return __raw_readl(ir->base + reg);
	183	}
	184
	185	static inline void mtk_irq_disable(struct mtk_ir *ir, u32 mask)
	186	{
	187	u32 val;
	188
50c3c1ba SW	189	val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]);
50c3c1ba SW	190	mtk_w32(ir, val & ~mask, ir->data->regs[MTK_IRINT_EN_REG]);
6691e7b9 SW	191	}
	192
	193	static inline void mtk_irq_enable(struct mtk_ir *ir, u32 mask)
	194	{
	195	u32 val;
	196
50c3c1ba SW	197	val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]);
50c3c1ba SW	198	mtk_w32(ir, val \| mask, ir->data->regs[MTK_IRINT_EN_REG]);
6691e7b9 SW	199	}
	200
	201	static irqreturn_t mtk_ir_irq(int irqno, void *dev_id)
	202	{
	203	struct mtk_ir *ir = dev_id;
	204	u8 wid = 0;
	205	u32 i, j, val;
183e19f5	206	struct ir_raw_event rawir = {};
6691e7b9 SW	207
	208	/*
	209	* Reset decoder state machine explicitly is required
	210	* because 1) the longest duration for space MTK IR hardware
	211	* could record is not safely long. e.g 12ms if rx resolution
	212	* is 46us by default. There is still the risk to satisfying
	213	* every decoder to reset themselves through long enough
	214	* trailing spaces and 2) the IRQ handler guarantees that
	215	* start of IR message is always contained in and starting
50c3c1ba	216	* from register mtk_chkdata_reg(ir, i).
6691e7b9 SW	217	*/
	218	ir_raw_event_reset(ir->rc);
	219
	220	/* First message must be pulse */
	221	rawir.pulse = false;
	222
	223	/* Handle all pulse and space IR controller captures */
	224	for (i = 0 ; i < MTK_CHKDATA_SZ ; i++) {
50c3c1ba	225	val = mtk_r32(ir, mtk_chkdata_reg(ir, i));
6691e7b9 SW	226	dev_dbg(ir->dev, "@reg%d=0x%08x\n", i, val);
	227
	228	for (j = 0 ; j < 4 ; j++) {
	229	wid = (val & (MTK_WIDTH_MASK << j * 8)) >> j * 8;
	230	rawir.pulse = !rawir.pulse;
	231	rawir.duration = wid * (MTK_IR_SAMPLE + 1);
	232	ir_raw_event_store_with_filter(ir->rc, &rawir);
	233	}
	234	}
	235
	236	/*
	237	* The maximum number of edges the IR controller can
	238	* hold is MTK_CHKDATA_SZ * 4. So if received IR messages
	239	* is over the limit, the last incomplete IR message would
	240	* be appended trailing space and still would be sent into
	241	* ir-rc-raw to decode. That helps it is possible that it
	242	* has enough information to decode a scancode even if the
	243	* trailing end of the message is missing.
	244	*/
	245	if (!MTK_IR_END(wid, rawir.pulse)) {
	246	rawir.pulse = false;
	247	rawir.duration = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1);
	248	ir_raw_event_store_with_filter(ir->rc, &rawir);
	249	}
	250
	251	ir_raw_event_handle(ir->rc);
	252
	253	/*
	254	* Restart controller for the next receive that would
	255	* clear up all CHKDATA registers
	256	*/
50c3c1ba	257	mtk_w32_mask(ir, 0x1, MTK_IRCLR, ir->data->regs[MTK_IRCLR_REG]);
6691e7b9 SW	258
6691e7b9 SW	259	/* Clear interrupt status */
50c3c1ba SW	260	mtk_w32_mask(ir, 0x1, MTK_IRINT_CLR,
50c3c1ba SW	261	ir->data->regs[MTK_IRINT_CLR_REG]);
6691e7b9 SW	262
	263	return IRQ_HANDLED;
	264	}
	265
50c3c1ba SW	266	static const struct mtk_ir_data mt7623_data = {
	267	.regs = mt7623_regs,
	268	.fields = mt7623_fields,
	269	.ok_count = 0xf,
	270	.hw_period = 0xff,
	271	.div = 4,
	272	};
	273
58389982 SW	274	static const struct mtk_ir_data mt7622_data = {
	275	.regs = mt7622_regs,
	276	.fields = mt7622_fields,
	277	.ok_count = 0xf,
	278	.hw_period = 0xffff,
	279	.div = 32,
	280	};
	281
50c3c1ba SW	282	static const struct of_device_id mtk_ir_match[] = {
50c3c1ba SW	283	{ .compatible = "mediatek,mt7623-cir", .data = &mt7623_data},
58389982	284	{ .compatible = "mediatek,mt7622-cir", .data = &mt7622_data},
50c3c1ba SW	285	{},
	286	};
	287	MODULE_DEVICE_TABLE(of, mtk_ir_match);
	288
6691e7b9 SW	289	static int mtk_ir_probe(struct platform_device *pdev)
	290	{
	291	struct device *dev = &pdev->dev;
	292	struct device_node *dn = dev->of_node;
	293	struct resource *res;
	294	struct mtk_ir *ir;
	295	u32 val;
	296	int ret = 0;
	297	const char *map_name;
	298
	299	ir = devm_kzalloc(dev, sizeof(struct mtk_ir), GFP_KERNEL);
	300	if (!ir)
	301	return -ENOMEM;
	302
	303	ir->dev = dev;
5d0af51f	304	ir->data = of_device_get_match_data(dev);
6691e7b9 SW	305
	306	ir->clk = devm_clk_get(dev, "clk");
	307	if (IS_ERR(ir->clk)) {
	308	dev_err(dev, "failed to get a ir clock.\n");
	309	return PTR_ERR(ir->clk);
	310	}
	311
50c3c1ba SW	312	ir->bus = devm_clk_get(dev, "bus");
	313	if (IS_ERR(ir->bus)) {
	314	/*
	315	* For compatibility with older device trees try unnamed
	316	* ir->bus uses the same clock as ir->clock.
	317	*/
	318	ir->bus = ir->clk;
	319	}
	320
6691e7b9 SW	321	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	322	ir->base = devm_ioremap_resource(dev, res);
	323	if (IS_ERR(ir->base)) {
	324	dev_err(dev, "failed to map registers\n");
	325	return PTR_ERR(ir->base);
	326	}
	327
	328	ir->rc = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW);
	329	if (!ir->rc) {
	330	dev_err(dev, "failed to allocate device\n");
	331	return -ENOMEM;
	332	}
	333
	334	ir->rc->priv = ir;
518f4b26	335	ir->rc->device_name = MTK_IR_DEV;
6691e7b9 SW	336	ir->rc->input_phys = MTK_IR_DEV "/input0";
	337	ir->rc->input_id.bustype = BUS_HOST;
	338	ir->rc->input_id.vendor = 0x0001;
	339	ir->rc->input_id.product = 0x0001;
	340	ir->rc->input_id.version = 0x0001;
	341	map_name = of_get_property(dn, "linux,rc-map-name", NULL);
	342	ir->rc->map_name = map_name ?: RC_MAP_EMPTY;
	343	ir->rc->dev.parent = dev;
	344	ir->rc->driver_name = MTK_IR_DEV;
6d741bfe	345	ir->rc->allowed_protocols = RC_PROTO_BIT_ALL;
6691e7b9 SW	346	ir->rc->rx_resolution = MTK_IR_SAMPLE;
	347	ir->rc->timeout = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1);
	348
	349	ret = devm_rc_register_device(dev, ir->rc);
	350	if (ret) {
	351	dev_err(dev, "failed to register rc device\n");
	352	return ret;
	353	}
	354
	355	platform_set_drvdata(pdev, ir);
	356
	357	ir->irq = platform_get_irq(pdev, 0);
	358	if (ir->irq < 0) {
	359	dev_err(dev, "no irq resource\n");
	360	return -ENODEV;
	361	}
	362
6691e7b9	363	if (clk_prepare_enable(ir->clk)) {
50c3c1ba SW	364	dev_err(dev, "try to enable ir_clk failed\n");
	365	return -EINVAL;
	366	}
	367
	368	if (clk_prepare_enable(ir->bus)) {
6691e7b9 SW	369	dev_err(dev, "try to enable ir_clk failed\n");
	370	ret = -EINVAL;
	371	goto exit_clkdisable_clk;
	372	}
	373
50c3c1ba SW	374	/*
	375	* Enable interrupt after proper hardware
	376	* setup and IRQ handler registration
	377	*/
6691e7b9 SW	378	mtk_irq_disable(ir, MTK_IRINT_EN);
	379
	380	ret = devm_request_irq(dev, ir->irq, mtk_ir_irq, 0, MTK_IR_DEV, ir);
	381	if (ret) {
	382	dev_err(dev, "failed request irq\n");
50c3c1ba	383	goto exit_clkdisable_bus;
6691e7b9 SW	384	}
6691e7b9 SW	385
50c3c1ba SW	386	/*
	387	* Setup software sample period as the reference of software decoder
	388	*/
	389	val = (mtk_chk_period(ir) << ir->data->fields[MTK_CHK_PERIOD].offset) &
	390	ir->data->fields[MTK_CHK_PERIOD].mask;
	391	mtk_w32_mask(ir, val, ir->data->fields[MTK_CHK_PERIOD].mask,
	392	ir->data->fields[MTK_CHK_PERIOD].reg);
	393
	394	/*
	395	* Setup hardware sampling period used to setup the proper timeout for
	396	* indicating end of IR receiving completion
	397	*/
	398	val = (ir->data->hw_period << ir->data->fields[MTK_HW_PERIOD].offset) &
	399	ir->data->fields[MTK_HW_PERIOD].mask;
	400	mtk_w32_mask(ir, val, ir->data->fields[MTK_HW_PERIOD].mask,
	401	ir->data->fields[MTK_HW_PERIOD].reg);
	402
6691e7b9 SW	403	/* Enable IR and PWM */
6691e7b9 SW	404	val = mtk_r32(ir, MTK_CONFIG_HIGH_REG);
50c3c1ba	405	val \|= MTK_OK_COUNT(ir->data->ok_count) \| MTK_PWM_EN \| MTK_IR_EN;
6691e7b9 SW	406	mtk_w32(ir, val, MTK_CONFIG_HIGH_REG);
6691e7b9 SW	407
6691e7b9 SW	408	mtk_irq_enable(ir, MTK_IRINT_EN);
6691e7b9 SW	409
50c3c1ba	410	dev_info(dev, "Initialized MT7623 IR driver, sample period = %dus\n",
6691e7b9 SW	411	DIV_ROUND_CLOSEST(MTK_IR_SAMPLE, 1000));
	412
	413	return 0;
	414
50c3c1ba SW	415	exit_clkdisable_bus:
50c3c1ba SW	416	clk_disable_unprepare(ir->bus);
6691e7b9 SW	417	exit_clkdisable_clk:
	418	clk_disable_unprepare(ir->clk);
	419
	420	return ret;
	421	}
	422
	423	static int mtk_ir_remove(struct platform_device *pdev)
	424	{
	425	struct mtk_ir *ir = platform_get_drvdata(pdev);
	426
	427	/*
	428	* Avoid contention between remove handler and
	429	* IRQ handler so that disabling IR interrupt and
	430	* waiting for pending IRQ handler to complete
	431	*/
	432	mtk_irq_disable(ir, MTK_IRINT_EN);
	433	synchronize_irq(ir->irq);
	434
50c3c1ba	435	clk_disable_unprepare(ir->bus);
6691e7b9 SW	436	clk_disable_unprepare(ir->clk);
	437
	438	return 0;
	439	}
	440
6691e7b9 SW	441	static struct platform_driver mtk_ir_driver = {
	442	.probe = mtk_ir_probe,
	443	.remove = mtk_ir_remove,
	444	.driver = {
	445	.name = MTK_IR_DEV,
	446	.of_match_table = mtk_ir_match,
	447	},
	448	};
	449
	450	module_platform_driver(mtk_ir_driver);
	451
	452	MODULE_DESCRIPTION("Mediatek IR Receiver Controller Driver");
	453	MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
	454	MODULE_LICENSE("GPL");