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[media] rc/nuvoton-cir: only warn about unknown chips
[mirror_ubuntu-jammy-kernel.git] / drivers / media / rc / nuvoton-cir.c
CommitLineData
6d2f5c27
JW		 1/*
2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
3 *
4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
5 * Copyright (C) 2009 Nuvoton PS Team
6 *
7 * Special thanks to Nuvoton for providing hardware, spec sheets and
8 * sample code upon which portions of this driver are based. Indirect
9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
10 * modeled after.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
25 * USA
26 */
27
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/pnp.h>
31#include <linux/io.h>
32#include <linux/interrupt.h>
33#include <linux/sched.h>
34#include <linux/slab.h>
6bda9644 35#include <media/rc-core.h>
6d2f5c27
JW		 36#include <linux/pci_ids.h>
37
38#include "nuvoton-cir.h"
39
6d2f5c27
JW		 40/* write val to config reg */
41static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg)
42{
43 outb(reg, nvt->cr_efir);
44 outb(val, nvt->cr_efdr);
45}
46
47/* read val from config reg */
48static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg)
49{
50 outb(reg, nvt->cr_efir);
51 return inb(nvt->cr_efdr);
52}
53
54/* update config register bit without changing other bits */
55static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
56{
57 u8 tmp = nvt_cr_read(nvt, reg) | val;
58 nvt_cr_write(nvt, tmp, reg);
59}
60
61/* clear config register bit without changing other bits */
62static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
63{
64 u8 tmp = nvt_cr_read(nvt, reg) & ~val;
65 nvt_cr_write(nvt, tmp, reg);
66}
67
68/* enter extended function mode */
69static inline void nvt_efm_enable(struct nvt_dev *nvt)
70{
71 /* Enabling Extended Function Mode explicitly requires writing 2x */
72 outb(EFER_EFM_ENABLE, nvt->cr_efir);
73 outb(EFER_EFM_ENABLE, nvt->cr_efir);
74}
75
76/* exit extended function mode */
77static inline void nvt_efm_disable(struct nvt_dev *nvt)
78{
79 outb(EFER_EFM_DISABLE, nvt->cr_efir);
80}
81
82/*
83 * When you want to address a specific logical device, write its logical
84 * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing
85 * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN.
86 */
87static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev)
88{
89 outb(CR_LOGICAL_DEV_SEL, nvt->cr_efir);
90 outb(ldev, nvt->cr_efdr);
91}
92
93/* write val to cir config register */
94static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset)
95{
96 outb(val, nvt->cir_addr + offset);
97}
98
99/* read val from cir config register */
100static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset)
101{
102 u8 val;
103
104 val = inb(nvt->cir_addr + offset);
105
106 return val;
107}
108
109/* write val to cir wake register */
110static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt,
111 u8 val, u8 offset)
112{
113 outb(val, nvt->cir_wake_addr + offset);
114}
115
116/* read val from cir wake config register */
117static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
118{
119 u8 val;
120
121 val = inb(nvt->cir_wake_addr + offset);
122
123 return val;
124}
125
4e6e29ad
JW		 126#define pr_reg(text, ...) \
127 printk(KERN_INFO KBUILD_MODNAME ": " text, ## __VA_ARGS__)
128
6d2f5c27
JW		 129/* dump current cir register contents */
130static void cir_dump_regs(struct nvt_dev *nvt)
131{
132 nvt_efm_enable(nvt);
133 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
134
4e6e29ad
JW		 135 pr_reg("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);
136 pr_reg(" * CR CIR ACTIVE : 0x%x\n",
6d2f5c27 137 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
4e6e29ad 138 pr_reg(" * CR CIR BASE ADDR: 0x%x\n",
6d2f5c27
JW		 139 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
140 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
4e6e29ad 141 pr_reg(" * CR CIR IRQ NUM: 0x%x\n",
6d2f5c27
JW		 142 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
143
144 nvt_efm_disable(nvt);
145
4e6e29ad
JW		 146 pr_reg("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);
147 pr_reg(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
148 pr_reg(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
149 pr_reg(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
150 pr_reg(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
151 pr_reg(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
152 pr_reg(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
153 pr_reg(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
154 pr_reg(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
155 pr_reg(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
156 pr_reg(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
157 pr_reg(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
158 pr_reg(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
159 pr_reg(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
160 pr_reg(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
161 pr_reg(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
162 pr_reg(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
6d2f5c27
JW		 163}
164
165/* dump current cir wake register contents */
166static void cir_wake_dump_regs(struct nvt_dev *nvt)
167{
168 u8 i, fifo_len;
169
170 nvt_efm_enable(nvt);
171 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
172
4e6e29ad 173 pr_reg("%s: Dump CIR WAKE logical device registers:\n",
6d2f5c27 174 NVT_DRIVER_NAME);
4e6e29ad 175 pr_reg(" * CR CIR WAKE ACTIVE : 0x%x\n",
6d2f5c27 176 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
4e6e29ad 177 pr_reg(" * CR CIR WAKE BASE ADDR: 0x%x\n",
6d2f5c27 178 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
4e6e29ad
JW		 179 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
180 pr_reg(" * CR CIR WAKE IRQ NUM: 0x%x\n",
6d2f5c27
JW		 181 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
182
183 nvt_efm_disable(nvt);
184
4e6e29ad
JW		 185 pr_reg("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);
186 pr_reg(" * IRCON: 0x%x\n",
6d2f5c27 187 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
4e6e29ad 188 pr_reg(" * IRSTS: 0x%x\n",
6d2f5c27 189 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
4e6e29ad 190 pr_reg(" * IREN: 0x%x\n",
6d2f5c27 191 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
4e6e29ad 192 pr_reg(" * FIFO CMP DEEP: 0x%x\n",
6d2f5c27 193 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
4e6e29ad 194 pr_reg(" * FIFO CMP TOL: 0x%x\n",
6d2f5c27 195 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
4e6e29ad 196 pr_reg(" * FIFO COUNT: 0x%x\n",
6d2f5c27 197 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
4e6e29ad 198 pr_reg(" * SLCH: 0x%x\n",
6d2f5c27 199 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
4e6e29ad 200 pr_reg(" * SLCL: 0x%x\n",
6d2f5c27 201 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
4e6e29ad 202 pr_reg(" * FIFOCON: 0x%x\n",
6d2f5c27 203 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
4e6e29ad 204 pr_reg(" * SRXFSTS: 0x%x\n",
6d2f5c27 205 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
4e6e29ad 206 pr_reg(" * SAMPLE RX FIFO: 0x%x\n",
6d2f5c27 207 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
4e6e29ad 208 pr_reg(" * WR FIFO DATA: 0x%x\n",
6d2f5c27 209 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
4e6e29ad 210 pr_reg(" * RD FIFO ONLY: 0x%x\n",
6d2f5c27 211 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
4e6e29ad 212 pr_reg(" * RD FIFO ONLY IDX: 0x%x\n",
6d2f5c27 213 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
4e6e29ad 214 pr_reg(" * FIFO IGNORE: 0x%x\n",
6d2f5c27 215 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
4e6e29ad 216 pr_reg(" * IRFSM: 0x%x\n",
6d2f5c27
JW		 217 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
218
219 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
4e6e29ad
JW		 220 pr_reg("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);
221 pr_reg("* Contents = ");
6d2f5c27 222 for (i = 0; i < fifo_len; i++)
4e6e29ad 223 printk(KERN_CONT "%02x ",
6d2f5c27 224 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
4e6e29ad 225 printk(KERN_CONT "\n");
6d2f5c27
JW		 226}
227
228/* detect hardware features */
229static int nvt_hw_detect(struct nvt_dev *nvt)
230{
231 unsigned long flags;
232 u8 chip_major, chip_minor;
233 int ret = 0;
362d3a3a
JW		 234 char chip_id[12];
235 bool chip_unknown = false;
6d2f5c27
JW		 236
237 nvt_efm_enable(nvt);
238
239 /* Check if we're wired for the alternate EFER setup */
240 chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
241 if (chip_major == 0xff) {
242 nvt->cr_efir = CR_EFIR2;
243 nvt->cr_efdr = CR_EFDR2;
244 nvt_efm_enable(nvt);
245 chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
246 }
247
248 chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
6d2f5c27 249
362d3a3a
JW		 250 /* these are the known working chip revisions... */
251 switch (chip_major) {
252 case CHIP_ID_HIGH_667:
253 strcpy(chip_id, "w83667hg\0");
254 if (chip_minor != CHIP_ID_LOW_667)
255 chip_unknown = true;
256 break;
257 case CHIP_ID_HIGH_677B:
258 strcpy(chip_id, "w83677hg\0");
259 if (chip_minor != CHIP_ID_LOW_677B2 &&
260 chip_minor != CHIP_ID_LOW_677B3)
261 chip_unknown = true;
262 break;
263 case CHIP_ID_HIGH_677C:
264 strcpy(chip_id, "w83677hg-c\0");
265 if (chip_minor != CHIP_ID_LOW_677C)
266 chip_unknown = true;
267 break;
268 default:
269 strcpy(chip_id, "w836x7hg\0");
270 chip_unknown = true;
271 break;
5df465df 272 }
6d2f5c27 273
362d3a3a
JW		 274 /* warn, but still let the driver load, if we don't know this chip */
275 if (chip_unknown)
276 nvt_pr(KERN_WARNING, "%s: unknown chip, id: 0x%02x 0x%02x, "
277 "it may not work...", chip_id, chip_major, chip_minor);
278 else
279 nvt_dbg("%s: chip id: 0x%02x 0x%02x",
280 chip_id, chip_major, chip_minor);
281
6d2f5c27
JW		 282 nvt_efm_disable(nvt);
283
284 spin_lock_irqsave(&nvt->nvt_lock, flags);
285 nvt->chip_major = chip_major;
286 nvt->chip_minor = chip_minor;
287 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
288
289 return ret;
290}
291
292static void nvt_cir_ldev_init(struct nvt_dev *nvt)
293{
294 u8 val;
295
296 /* output pin selection (Pin95=CIRRX, Pin96=CIRTX1, WB enabled */
297 val = nvt_cr_read(nvt, CR_OUTPUT_PIN_SEL);
298 val &= OUTPUT_PIN_SEL_MASK;
299 val |= (OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB);
300 nvt_cr_write(nvt, val, CR_OUTPUT_PIN_SEL);
301
302 /* Select CIR logical device and enable */
303 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
304 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
305
306 nvt_cr_write(nvt, nvt->cir_addr >> 8, CR_CIR_BASE_ADDR_HI);
307 nvt_cr_write(nvt, nvt->cir_addr & 0xff, CR_CIR_BASE_ADDR_LO);
308
309 nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
310
311 nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
312 nvt->cir_addr, nvt->cir_irq);
313}
314
315static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt)
316{
317 /* Select ACPI logical device, enable it and CIR Wake */
318 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
319 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
320
321 /* Enable CIR Wake via PSOUT# (Pin60) */
322 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
323
324 /* enable cir interrupt of mouse/keyboard IRQ event */
325 nvt_set_reg_bit(nvt, CIR_INTR_MOUSE_IRQ_BIT, CR_ACPI_IRQ_EVENTS);
326
327 /* enable pme interrupt of cir wakeup event */
328 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
329
330 /* Select CIR Wake logical device and enable */
331 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
332 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
333
334 nvt_cr_write(nvt, nvt->cir_wake_addr >> 8, CR_CIR_BASE_ADDR_HI);
335 nvt_cr_write(nvt, nvt->cir_wake_addr & 0xff, CR_CIR_BASE_ADDR_LO);
336
337 nvt_cr_write(nvt, nvt->cir_wake_irq, CR_CIR_IRQ_RSRC);
338
339 nvt_dbg("CIR Wake initialized, base io port address: 0x%lx, irq: %d",
340 nvt->cir_wake_addr, nvt->cir_wake_irq);
341}
342
343/* clear out the hardware's cir rx fifo */
344static void nvt_clear_cir_fifo(struct nvt_dev *nvt)
345{
346 u8 val;
347
348 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
349 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
350}
351
352/* clear out the hardware's cir wake rx fifo */
353static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt)
354{
355 u8 val;
356
357 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON);
358 nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR,
359 CIR_WAKE_FIFOCON);
360}
361
362/* clear out the hardware's cir tx fifo */
363static void nvt_clear_tx_fifo(struct nvt_dev *nvt)
364{
365 u8 val;
366
367 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
368 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON);
369}
370
fbdc781c
JW		 371/* enable RX Trigger Level Reach and Packet End interrupts */
372static void nvt_set_cir_iren(struct nvt_dev *nvt)
373{
374 u8 iren;
375
376 iren = CIR_IREN_RTR | CIR_IREN_PE;
377 nvt_cir_reg_write(nvt, iren, CIR_IREN);
378}
379
6d2f5c27
JW		 380static void nvt_cir_regs_init(struct nvt_dev *nvt)
381{
382 /* set sample limit count (PE interrupt raised when reached) */
383 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH);
384 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL);
385
386 /* set fifo irq trigger levels */
387 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV |
388 CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON);
389
390 /*
391 * Enable TX and RX, specify carrier on = low, off = high, and set
392 * sample period (currently 50us)
393 */
4e6e29ad
JW		 394 nvt_cir_reg_write(nvt,
395 CIR_IRCON_TXEN | CIR_IRCON_RXEN |
396 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
397 CIR_IRCON);
6d2f5c27
JW		 398
399 /* clear hardware rx and tx fifos */
400 nvt_clear_cir_fifo(nvt);
401 nvt_clear_tx_fifo(nvt);
402
403 /* clear any and all stray interrupts */
404 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
405
fbdc781c
JW		 406 /* and finally, enable interrupts */
407 nvt_set_cir_iren(nvt);
6d2f5c27
JW		 408}
409
410static void nvt_cir_wake_regs_init(struct nvt_dev *nvt)
411{
3198ed16
JW		 412 /* set number of bytes needed for wake from s3 (default 65) */
413 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFO_CMP_BYTES,
414 CIR_WAKE_FIFO_CMP_DEEP);
6d2f5c27
JW		 415
416 /* set tolerance/variance allowed per byte during wake compare */
417 nvt_cir_wake_reg_write(nvt, CIR_WAKE_CMP_TOLERANCE,
418 CIR_WAKE_FIFO_CMP_TOL);
419
420 /* set sample limit count (PE interrupt raised when reached) */
421 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_WAKE_SLCH);
422 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_WAKE_SLCL);
423
424 /* set cir wake fifo rx trigger level (currently 67) */
425 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFOCON_RX_TRIGGER_LEV,
426 CIR_WAKE_FIFOCON);
427
428 /*
429 * Enable TX and RX, specific carrier on = low, off = high, and set
430 * sample period (currently 50us)
431 */
432 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
433 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
434 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
435 CIR_WAKE_IRCON);
436
437 /* clear cir wake rx fifo */
438 nvt_clear_cir_wake_fifo(nvt);
439
440 /* clear any and all stray interrupts */
441 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
442}
443
444static void nvt_enable_wake(struct nvt_dev *nvt)
445{
446 nvt_efm_enable(nvt);
447
448 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
449 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
450 nvt_set_reg_bit(nvt, CIR_INTR_MOUSE_IRQ_BIT, CR_ACPI_IRQ_EVENTS);
451 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
452
453 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
454 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
455
456 nvt_efm_disable(nvt);
457
458 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
459 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
4e6e29ad
JW		 460 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
461 CIR_WAKE_IRCON);
6d2f5c27
JW		 462 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
463 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
464}
465
466/* rx carrier detect only works in learning mode, must be called w/nvt_lock */
467static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt)
468{
469 u32 count, carrier, duration = 0;
470 int i;
471
472 count = nvt_cir_reg_read(nvt, CIR_FCCL) |
473 nvt_cir_reg_read(nvt, CIR_FCCH) << 8;
474
475 for (i = 0; i < nvt->pkts; i++) {
476 if (nvt->buf[i] & BUF_PULSE_BIT)
477 duration += nvt->buf[i] & BUF_LEN_MASK;
478 }
479
480 duration *= SAMPLE_PERIOD;
481
482 if (!count || !duration) {
483 nvt_pr(KERN_NOTICE, "Unable to determine carrier! (c:%u, d:%u)",
484 count, duration);
485 return 0;
486 }
487
b4608fae 488 carrier = MS_TO_NS(count) / duration;
6d2f5c27
JW		 489
490 if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER))
491 nvt_dbg("WTF? Carrier frequency out of range!");
492
493 nvt_dbg("Carrier frequency: %u (count %u, duration %u)",
494 carrier, count, duration);
495
496 return carrier;
497}
498
499/*
500 * set carrier frequency
501 *
502 * set carrier on 2 registers: CP & CC
503 * always set CP as 0x81
504 * set CC by SPEC, CC = 3MHz/carrier - 1
505 */
d8b4b582 506static int nvt_set_tx_carrier(struct rc_dev *dev, u32 carrier)
6d2f5c27 507{
d8b4b582 508 struct nvt_dev *nvt = dev->priv;
6d2f5c27
JW		 509 u16 val;
510
511 nvt_cir_reg_write(nvt, 1, CIR_CP);
512 val = 3000000 / (carrier) - 1;
513 nvt_cir_reg_write(nvt, val & 0xff, CIR_CC);
514
515 nvt_dbg("cp: 0x%x cc: 0x%x\n",
516 nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC));
517
518 return 0;
519}
520
521/*
522 * nvt_tx_ir
523 *
524 * 1) clean TX fifo first (handled by AP)
525 * 2) copy data from user space
526 * 3) disable RX interrupts, enable TX interrupts: TTR & TFU
527 * 4) send 9 packets to TX FIFO to open TTR
528 * in interrupt_handler:
529 * 5) send all data out
530 * go back to write():
531 * 6) disable TX interrupts, re-enable RX interupts
532 *
533 * The key problem of this function is user space data may larger than
534 * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to
535 * buf, and keep current copied data buf num in cur_buf_num. But driver's buf
536 * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to
537 * set TXFCONT as 0xff, until buf_count less than 0xff.
538 */
d8b4b582 539static int nvt_tx_ir(struct rc_dev *dev, int *txbuf, u32 n)
6d2f5c27 540{
d8b4b582 541 struct nvt_dev *nvt = dev->priv;
6d2f5c27
JW		 542 unsigned long flags;
543 size_t cur_count;
544 unsigned int i;
545 u8 iren;
546 int ret;
547
548 spin_lock_irqsave(&nvt->tx.lock, flags);
549
550 if (n >= TX_BUF_LEN) {
551 nvt->tx.buf_count = cur_count = TX_BUF_LEN;
552 ret = TX_BUF_LEN;
553 } else {
554 nvt->tx.buf_count = cur_count = n;
555 ret = n;
556 }
557
558 memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count);
559
560 nvt->tx.cur_buf_num = 0;
561
562 /* save currently enabled interrupts */
563 iren = nvt_cir_reg_read(nvt, CIR_IREN);
564
565 /* now disable all interrupts, save TFU & TTR */
566 nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN);
567
568 nvt->tx.tx_state = ST_TX_REPLY;
569
570 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 |
571 CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
572
573 /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */
574 for (i = 0; i < 9; i++)
575 nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO);
576
577 spin_unlock_irqrestore(&nvt->tx.lock, flags);
578
579 wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST);
580
581 spin_lock_irqsave(&nvt->tx.lock, flags);
582 nvt->tx.tx_state = ST_TX_NONE;
583 spin_unlock_irqrestore(&nvt->tx.lock, flags);
584
585 /* restore enabled interrupts to prior state */
586 nvt_cir_reg_write(nvt, iren, CIR_IREN);
587
588 return ret;
589}
590
591/* dump contents of the last rx buffer we got from the hw rx fifo */
592static void nvt_dump_rx_buf(struct nvt_dev *nvt)
593{
594 int i;
595
4e6e29ad 596 printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts);
6d2f5c27 597 for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++)
4e6e29ad
JW		 598 printk(KERN_CONT "0x%02x ", nvt->buf[i]);
599 printk(KERN_CONT "\n");
6d2f5c27
JW		 600}
601
602/*
603 * Process raw data in rx driver buffer, store it in raw IR event kfifo,
604 * trigger decode when appropriate.
605 *
606 * We get IR data samples one byte at a time. If the msb is set, its a pulse,
607 * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD
608 * (default 50us) intervals for that pulse/space. A discrete signal is
609 * followed by a series of 0x7f packets, then either 0x7<something> or 0x80
610 * to signal more IR coming (repeats) or end of IR, respectively. We store
611 * sample data in the raw event kfifo until we see 0x7<something> (except f)
612 * or 0x80, at which time, we trigger a decode operation.
613 */
614static void nvt_process_rx_ir_data(struct nvt_dev *nvt)
615{
4651918a 616 DEFINE_IR_RAW_EVENT(rawir);
6d2f5c27
JW		 617 unsigned int count;
618 u32 carrier;
619 u8 sample;
620 int i;
621
622 nvt_dbg_verbose("%s firing", __func__);
623
624 if (debug)
625 nvt_dump_rx_buf(nvt);
626
627 if (nvt->carrier_detect_enabled)
628 carrier = nvt_rx_carrier_detect(nvt);
629
630 count = nvt->pkts;
631 nvt_dbg_verbose("Processing buffer of len %d", count);
632
b7582815
JW		 633 init_ir_raw_event(&rawir);
634
6d2f5c27
JW		 635 for (i = 0; i < count; i++) {
636 nvt->pkts--;
637 sample = nvt->buf[i];
638
639 rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
b4608fae
JW		 640 rawir.duration = US_TO_NS((sample & BUF_LEN_MASK)
641 * SAMPLE_PERIOD);
6d2f5c27
JW		 642
643 if ((sample & BUF_LEN_MASK) == BUF_LEN_MASK) {
644 if (nvt->rawir.pulse == rawir.pulse)
645 nvt->rawir.duration += rawir.duration;
646 else {
647 nvt->rawir.duration = rawir.duration;
648 nvt->rawir.pulse = rawir.pulse;
649 }
650 continue;
651 }
652
653 rawir.duration += nvt->rawir.duration;
4651918a
ML		 654
655 init_ir_raw_event(&nvt->rawir);
6d2f5c27
JW		 656 nvt->rawir.duration = 0;
657 nvt->rawir.pulse = rawir.pulse;
658
659 if (sample == BUF_PULSE_BIT)
660 rawir.pulse = false;
661
662 if (rawir.duration) {
663 nvt_dbg("Storing %s with duration %d",
664 rawir.pulse ? "pulse" : "space",
665 rawir.duration);
666
667 ir_raw_event_store(nvt->rdev, &rawir);
668 }
669
670 /*
671 * BUF_PULSE_BIT indicates end of IR data, BUF_REPEAT_BYTE
672 * indicates end of IR signal, but new data incoming. In both
673 * cases, it means we're ready to call ir_raw_event_handle
674 */
b7582815
JW		 675 if ((sample == BUF_PULSE_BIT) && nvt->pkts) {
676 nvt_dbg("Calling ir_raw_event_handle (signal end)\n");
6d2f5c27 677 ir_raw_event_handle(nvt->rdev);
b7582815 678 }
6d2f5c27
JW		 679 }
680
b7582815
JW		 681 nvt_dbg("Calling ir_raw_event_handle (buffer empty)\n");
682 ir_raw_event_handle(nvt->rdev);
683
6d2f5c27
JW		 684 if (nvt->pkts) {
685 nvt_dbg("Odd, pkts should be 0 now... (its %u)", nvt->pkts);
686 nvt->pkts = 0;
687 }
688
689 nvt_dbg_verbose("%s done", __func__);
690}
691
fbdc781c
JW		 692static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt)
693{
694 nvt_pr(KERN_WARNING, "RX FIFO overrun detected, flushing data!");
695
696 nvt->pkts = 0;
697 nvt_clear_cir_fifo(nvt);
698 ir_raw_event_reset(nvt->rdev);
699}
700
6d2f5c27
JW		 701/* copy data from hardware rx fifo into driver buffer */
702static void nvt_get_rx_ir_data(struct nvt_dev *nvt)
703{
704 unsigned long flags;
705 u8 fifocount, val;
706 unsigned int b_idx;
fbdc781c 707 bool overrun = false;
6d2f5c27
JW		 708 int i;
709
710 /* Get count of how many bytes to read from RX FIFO */
711 fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT);
712 /* if we get 0xff, probably means the logical dev is disabled */
713 if (fifocount == 0xff)
714 return;
fbdc781c 715 /* watch out for a fifo overrun condition */
6d2f5c27 716 else if (fifocount > RX_BUF_LEN) {
fbdc781c
JW		 717 overrun = true;
718 fifocount = RX_BUF_LEN;
6d2f5c27
JW		 719 }
720
721 nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount);
722
723 spin_lock_irqsave(&nvt->nvt_lock, flags);
724
725 b_idx = nvt->pkts;
726
727 /* This should never happen, but lets check anyway... */
728 if (b_idx + fifocount > RX_BUF_LEN) {
729 nvt_process_rx_ir_data(nvt);
730 b_idx = 0;
731 }
732
733 /* Read fifocount bytes from CIR Sample RX FIFO register */
734 for (i = 0; i < fifocount; i++) {
735 val = nvt_cir_reg_read(nvt, CIR_SRXFIFO);
736 nvt->buf[b_idx + i] = val;
737 }
738
739 nvt->pkts += fifocount;
740 nvt_dbg("%s: pkts now %d", __func__, nvt->pkts);
741
742 nvt_process_rx_ir_data(nvt);
743
fbdc781c
JW		 744 if (overrun)
745 nvt_handle_rx_fifo_overrun(nvt);
746
6d2f5c27
JW		 747 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
748}
749
750static void nvt_cir_log_irqs(u8 status, u8 iren)
751{
752 nvt_pr(KERN_INFO, "IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s",
753 status, iren,
754 status & CIR_IRSTS_RDR ? " RDR" : "",
755 status & CIR_IRSTS_RTR ? " RTR" : "",
756 status & CIR_IRSTS_PE ? " PE" : "",
757 status & CIR_IRSTS_RFO ? " RFO" : "",
758 status & CIR_IRSTS_TE ? " TE" : "",
759 status & CIR_IRSTS_TTR ? " TTR" : "",
760 status & CIR_IRSTS_TFU ? " TFU" : "",
761 status & CIR_IRSTS_GH ? " GH" : "",
762 status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE |
763 CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR |
764 CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : "");
765}
766
767static bool nvt_cir_tx_inactive(struct nvt_dev *nvt)
768{
769 unsigned long flags;
770 bool tx_inactive;
771 u8 tx_state;
772
773 spin_lock_irqsave(&nvt->tx.lock, flags);
774 tx_state = nvt->tx.tx_state;
775 spin_unlock_irqrestore(&nvt->tx.lock, flags);
776
777 tx_inactive = (tx_state == ST_TX_NONE);
778
779 return tx_inactive;
780}
781
782/* interrupt service routine for incoming and outgoing CIR data */
783static irqreturn_t nvt_cir_isr(int irq, void *data)
784{
785 struct nvt_dev *nvt = data;
786 u8 status, iren, cur_state;
787 unsigned long flags;
788
789 nvt_dbg_verbose("%s firing", __func__);
790
791 nvt_efm_enable(nvt);
792 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
793 nvt_efm_disable(nvt);
794
795 /*
796 * Get IR Status register contents. Write 1 to ack/clear
797 *
798 * bit: reg name - description
799 * 7: CIR_IRSTS_RDR - RX Data Ready
800 * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach
801 * 5: CIR_IRSTS_PE - Packet End
802 * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set)
803 * 3: CIR_IRSTS_TE - TX FIFO Empty
804 * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach
805 * 1: CIR_IRSTS_TFU - TX FIFO Underrun
806 * 0: CIR_IRSTS_GH - Min Length Detected
807 */
808 status = nvt_cir_reg_read(nvt, CIR_IRSTS);
809 if (!status) {
810 nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__);
811 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
812 return IRQ_RETVAL(IRQ_NONE);
813 }
814
815 /* ack/clear all irq flags we've got */
816 nvt_cir_reg_write(nvt, status, CIR_IRSTS);
817 nvt_cir_reg_write(nvt, 0, CIR_IRSTS);
818
819 /* Interrupt may be shared with CIR Wake, bail if CIR not enabled */
820 iren = nvt_cir_reg_read(nvt, CIR_IREN);
821 if (!iren) {
822 nvt_dbg_verbose("%s exiting, CIR not enabled", __func__);
823 return IRQ_RETVAL(IRQ_NONE);
824 }
825
826 if (debug)
827 nvt_cir_log_irqs(status, iren);
828
829 if (status & CIR_IRSTS_RTR) {
830 /* FIXME: add code for study/learn mode */
831 /* We only do rx if not tx'ing */
832 if (nvt_cir_tx_inactive(nvt))
833 nvt_get_rx_ir_data(nvt);
834 }
835
836 if (status & CIR_IRSTS_PE) {
837 if (nvt_cir_tx_inactive(nvt))
838 nvt_get_rx_ir_data(nvt);
839
840 spin_lock_irqsave(&nvt->nvt_lock, flags);
841
842 cur_state = nvt->study_state;
843
844 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
845
846 if (cur_state == ST_STUDY_NONE)
847 nvt_clear_cir_fifo(nvt);
848 }
849
850 if (status & CIR_IRSTS_TE)
851 nvt_clear_tx_fifo(nvt);
852
853 if (status & CIR_IRSTS_TTR) {
854 unsigned int pos, count;
855 u8 tmp;
856
857 spin_lock_irqsave(&nvt->tx.lock, flags);
858
859 pos = nvt->tx.cur_buf_num;
860 count = nvt->tx.buf_count;
861
862 /* Write data into the hardware tx fifo while pos < count */
863 if (pos < count) {
864 nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO);
865 nvt->tx.cur_buf_num++;
866 /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */
867 } else {
868 tmp = nvt_cir_reg_read(nvt, CIR_IREN);
869 nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN);
870 }
871
872 spin_unlock_irqrestore(&nvt->tx.lock, flags);
873
874 }
875
876 if (status & CIR_IRSTS_TFU) {
877 spin_lock_irqsave(&nvt->tx.lock, flags);
878 if (nvt->tx.tx_state == ST_TX_REPLY) {
879 nvt->tx.tx_state = ST_TX_REQUEST;
880 wake_up(&nvt->tx.queue);
881 }
882 spin_unlock_irqrestore(&nvt->tx.lock, flags);
883 }
884
885 nvt_dbg_verbose("%s done", __func__);
886 return IRQ_RETVAL(IRQ_HANDLED);
887}
888
889/* Interrupt service routine for CIR Wake */
890static irqreturn_t nvt_cir_wake_isr(int irq, void *data)
891{
892 u8 status, iren, val;
893 struct nvt_dev *nvt = data;
894 unsigned long flags;
895
896 nvt_dbg_wake("%s firing", __func__);
897
898 status = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS);
899 if (!status)
900 return IRQ_RETVAL(IRQ_NONE);
901
902 if (status & CIR_WAKE_IRSTS_IR_PENDING)
903 nvt_clear_cir_wake_fifo(nvt);
904
905 nvt_cir_wake_reg_write(nvt, status, CIR_WAKE_IRSTS);
906 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IRSTS);
907
908 /* Interrupt may be shared with CIR, bail if Wake not enabled */
909 iren = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN);
910 if (!iren) {
911 nvt_dbg_wake("%s exiting, wake not enabled", __func__);
912 return IRQ_RETVAL(IRQ_HANDLED);
913 }
914
915 if ((status & CIR_WAKE_IRSTS_PE) &&
916 (nvt->wake_state == ST_WAKE_START)) {
917 while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)) {
918 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
919 nvt_dbg("setting wake up key: 0x%x", val);
920 }
921
922 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
923 spin_lock_irqsave(&nvt->nvt_lock, flags);
924 nvt->wake_state = ST_WAKE_FINISH;
925 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
926 }
927
928 nvt_dbg_wake("%s done", __func__);
929 return IRQ_RETVAL(IRQ_HANDLED);
930}
931
932static void nvt_enable_cir(struct nvt_dev *nvt)
933{
934 /* set function enable flags */
935 nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN |
936 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
937 CIR_IRCON);
938
939 nvt_efm_enable(nvt);
940
941 /* enable the CIR logical device */
942 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
943 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
944
945 nvt_efm_disable(nvt);
946
947 /* clear all pending interrupts */
948 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
949
950 /* enable interrupts */
fbdc781c 951 nvt_set_cir_iren(nvt);
6d2f5c27
JW		 952}
953
954static void nvt_disable_cir(struct nvt_dev *nvt)
955{
956 /* disable CIR interrupts */
957 nvt_cir_reg_write(nvt, 0, CIR_IREN);
958
959 /* clear any and all pending interrupts */
960 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
961
962 /* clear all function enable flags */
963 nvt_cir_reg_write(nvt, 0, CIR_IRCON);
964
965 /* clear hardware rx and tx fifos */
966 nvt_clear_cir_fifo(nvt);
967 nvt_clear_tx_fifo(nvt);
968
969 nvt_efm_enable(nvt);
970
971 /* disable the CIR logical device */
972 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
973 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
974
975 nvt_efm_disable(nvt);
976}
977
d8b4b582 978static int nvt_open(struct rc_dev *dev)
6d2f5c27 979{
d8b4b582 980 struct nvt_dev *nvt = dev->priv;
6d2f5c27
JW		 981 unsigned long flags;
982
983 spin_lock_irqsave(&nvt->nvt_lock, flags);
984 nvt->in_use = true;
985 nvt_enable_cir(nvt);
986 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
987
988 return 0;
989}
990
d8b4b582 991static void nvt_close(struct rc_dev *dev)
6d2f5c27 992{
d8b4b582 993 struct nvt_dev *nvt = dev->priv;
6d2f5c27
JW		 994 unsigned long flags;
995
996 spin_lock_irqsave(&nvt->nvt_lock, flags);
997 nvt->in_use = false;
998 nvt_disable_cir(nvt);
999 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1000}
1001
1002/* Allocate memory, probe hardware, and initialize everything */
1003static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
1004{
d8b4b582
DH		 1005 struct nvt_dev *nvt;
1006 struct rc_dev *rdev;
6d2f5c27
JW		 1007 int ret = -ENOMEM;
1008
1009 nvt = kzalloc(sizeof(struct nvt_dev), GFP_KERNEL);
1010 if (!nvt)
1011 return ret;
1012
6d2f5c27 1013 /* input device for IR remote (and tx) */
d8b4b582 1014 rdev = rc_allocate_device();
6d2f5c27
JW		 1015 if (!rdev)
1016 goto failure;
1017
1018 ret = -ENODEV;
1019 /* validate pnp resources */
1020 if (!pnp_port_valid(pdev, 0) ||
1021 pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) {
1022 dev_err(&pdev->dev, "IR PNP Port not valid!\n");
1023 goto failure;
1024 }
1025
1026 if (!pnp_irq_valid(pdev, 0)) {
1027 dev_err(&pdev->dev, "PNP IRQ not valid!\n");
1028 goto failure;
1029 }
1030
1031 if (!pnp_port_valid(pdev, 1) ||
1032 pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) {
1033 dev_err(&pdev->dev, "Wake PNP Port not valid!\n");
1034 goto failure;
1035 }
1036
1037 nvt->cir_addr = pnp_port_start(pdev, 0);
1038 nvt->cir_irq = pnp_irq(pdev, 0);
1039
1040 nvt->cir_wake_addr = pnp_port_start(pdev, 1);
1041 /* irq is always shared between cir and cir wake */
1042 nvt->cir_wake_irq = nvt->cir_irq;
1043
1044 nvt->cr_efir = CR_EFIR;
1045 nvt->cr_efdr = CR_EFDR;
1046
1047 spin_lock_init(&nvt->nvt_lock);
1048 spin_lock_init(&nvt->tx.lock);
4651918a 1049 init_ir_raw_event(&nvt->rawir);
6d2f5c27
JW		 1050
1051 ret = -EBUSY;
1052 /* now claim resources */
1053 if (!request_region(nvt->cir_addr,
1054 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
1055 goto failure;
1056
1057 if (request_irq(nvt->cir_irq, nvt_cir_isr, IRQF_SHARED,
1058 NVT_DRIVER_NAME, (void *)nvt))
1059 goto failure;
1060
1061 if (!request_region(nvt->cir_wake_addr,
1062 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
1063 goto failure;
1064
1065 if (request_irq(nvt->cir_wake_irq, nvt_cir_wake_isr, IRQF_SHARED,
1066 NVT_DRIVER_NAME, (void *)nvt))
1067 goto failure;
1068
1069 pnp_set_drvdata(pdev, nvt);
1070 nvt->pdev = pdev;
1071
1072 init_waitqueue_head(&nvt->tx.queue);
1073
1074 ret = nvt_hw_detect(nvt);
1075 if (ret)
1076 goto failure;
1077
1078 /* Initialize CIR & CIR Wake Logical Devices */
1079 nvt_efm_enable(nvt);
1080 nvt_cir_ldev_init(nvt);
1081 nvt_cir_wake_ldev_init(nvt);
1082 nvt_efm_disable(nvt);
1083
1084 /* Initialize CIR & CIR Wake Config Registers */
1085 nvt_cir_regs_init(nvt);
1086 nvt_cir_wake_regs_init(nvt);
1087
d8b4b582
DH		 1088 /* Set up the rc device */
1089 rdev->priv = nvt;
1090 rdev->driver_type = RC_DRIVER_IR_RAW;
52b66144 1091 rdev->allowed_protos = RC_TYPE_ALL;
d8b4b582
DH		 1092 rdev->open = nvt_open;
1093 rdev->close = nvt_close;
1094 rdev->tx_ir = nvt_tx_ir;
1095 rdev->s_tx_carrier = nvt_set_tx_carrier;
1096 rdev->input_name = "Nuvoton w836x7hg Infrared Remote Transceiver";
1097 rdev->input_id.bustype = BUS_HOST;
1098 rdev->input_id.vendor = PCI_VENDOR_ID_WINBOND2;
1099 rdev->input_id.product = nvt->chip_major;
1100 rdev->input_id.version = nvt->chip_minor;
1101 rdev->driver_name = NVT_DRIVER_NAME;
1102 rdev->map_name = RC_MAP_RC6_MCE;
6d2f5c27 1103#if 0
d8b4b582
DH		 1104 rdev->min_timeout = XYZ;
1105 rdev->max_timeout = XYZ;
1106 rdev->timeout = XYZ;
6d2f5c27 1107 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
d8b4b582 1108 rdev->rx_resolution = XYZ;
6d2f5c27 1109 /* tx bits */
d8b4b582 1110 rdev->tx_resolution = XYZ;
6d2f5c27 1111#endif
6d2f5c27 1112
d8b4b582 1113 ret = rc_register_device(rdev);
6d2f5c27
JW		 1114 if (ret)
1115 goto failure;
1116
d8b4b582
DH		 1117 device_set_wakeup_capable(&pdev->dev, 1);
1118 device_set_wakeup_enable(&pdev->dev, 1);
1119 nvt->rdev = rdev;
6d2f5c27
JW		 1120 nvt_pr(KERN_NOTICE, "driver has been successfully loaded\n");
1121 if (debug) {
1122 cir_dump_regs(nvt);
1123 cir_wake_dump_regs(nvt);
1124 }
1125
1126 return 0;
1127
1128failure:
1129 if (nvt->cir_irq)
1130 free_irq(nvt->cir_irq, nvt);
1131 if (nvt->cir_addr)
1132 release_region(nvt->cir_addr, CIR_IOREG_LENGTH);
1133
1134 if (nvt->cir_wake_irq)
1135 free_irq(nvt->cir_wake_irq, nvt);
1136 if (nvt->cir_wake_addr)
1137 release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH);
1138
d8b4b582 1139 rc_free_device(rdev);
6d2f5c27
JW		 1140 kfree(nvt);
1141
1142 return ret;
1143}
1144
1145static void __devexit nvt_remove(struct pnp_dev *pdev)
1146{
1147 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1148 unsigned long flags;
1149
1150 spin_lock_irqsave(&nvt->nvt_lock, flags);
1151 /* disable CIR */
1152 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1153 nvt_disable_cir(nvt);
1154 /* enable CIR Wake (for IR power-on) */
1155 nvt_enable_wake(nvt);
1156 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1157
1158 /* free resources */
1159 free_irq(nvt->cir_irq, nvt);
1160 free_irq(nvt->cir_wake_irq, nvt);
1161 release_region(nvt->cir_addr, CIR_IOREG_LENGTH);
1162 release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH);
1163
d8b4b582 1164 rc_unregister_device(nvt->rdev);
6d2f5c27 1165
6d2f5c27
JW		 1166 kfree(nvt);
1167}
1168
1169static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state)
1170{
1171 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1172 unsigned long flags;
1173
1174 nvt_dbg("%s called", __func__);
1175
1176 /* zero out misc state tracking */
1177 spin_lock_irqsave(&nvt->nvt_lock, flags);
1178 nvt->study_state = ST_STUDY_NONE;
1179 nvt->wake_state = ST_WAKE_NONE;
1180 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1181
1182 spin_lock_irqsave(&nvt->tx.lock, flags);
1183 nvt->tx.tx_state = ST_TX_NONE;
1184 spin_unlock_irqrestore(&nvt->tx.lock, flags);
1185
1186 /* disable all CIR interrupts */
1187 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1188
1189 nvt_efm_enable(nvt);
1190
1191 /* disable cir logical dev */
1192 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1193 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
1194
1195 nvt_efm_disable(nvt);
1196
1197 /* make sure wake is enabled */
1198 nvt_enable_wake(nvt);
1199
1200 return 0;
1201}
1202
1203static int nvt_resume(struct pnp_dev *pdev)
1204{
1205 int ret = 0;
1206 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1207
1208 nvt_dbg("%s called", __func__);
1209
1210 /* open interrupt */
fbdc781c 1211 nvt_set_cir_iren(nvt);
6d2f5c27
JW		 1212
1213 /* Enable CIR logical device */
1214 nvt_efm_enable(nvt);
1215 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1216 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
1217
1218 nvt_efm_disable(nvt);
1219
1220 nvt_cir_regs_init(nvt);
1221 nvt_cir_wake_regs_init(nvt);
1222
1223 return ret;
1224}
1225
1226static void nvt_shutdown(struct pnp_dev *pdev)
1227{
1228 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1229 nvt_enable_wake(nvt);
1230}
1231
1232static const struct pnp_device_id nvt_ids[] = {
1233 { "WEC0530", 0 }, /* CIR */
1234 { "NTN0530", 0 }, /* CIR for new chip's pnp id*/
1235 { "", 0 },
1236};
1237
1238static struct pnp_driver nvt_driver = {
1239 .name = NVT_DRIVER_NAME,
1240 .id_table = nvt_ids,
1241 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
1242 .probe = nvt_probe,
1243 .remove = __devexit_p(nvt_remove),
1244 .suspend = nvt_suspend,
1245 .resume = nvt_resume,
1246 .shutdown = nvt_shutdown,
1247};
1248
1249int nvt_init(void)
1250{
1251 return pnp_register_driver(&nvt_driver);
1252}
1253
1254void nvt_exit(void)
1255{
1256 pnp_unregister_driver(&nvt_driver);
1257}
1258
1259module_param(debug, int, S_IRUGO | S_IWUSR);
1260MODULE_PARM_DESC(debug, "Enable debugging output");
1261
1262MODULE_DEVICE_TABLE(pnp, nvt_ids);
1263MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver");
1264
1265MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
1266MODULE_LICENSE("GPL");
1267
1268module_init(nvt_init);
1269module_exit(nvt_exit);
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