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6d2f5c27 JW |
1 | /* |
2 | * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR | |
3 | * | |
4 | * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com> | |
5 | * Copyright (C) 2009 Nuvoton PS Team | |
6 | * | |
7 | * Special thanks to Nuvoton for providing hardware, spec sheets and | |
8 | * sample code upon which portions of this driver are based. Indirect | |
9 | * thanks also to Maxim Levitsky, whose ene_ir driver this driver is | |
10 | * modeled after. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of the | |
15 | * License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, but | |
18 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
20 | * General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 | |
25 | * USA | |
26 | */ | |
27 | ||
28 | #include <linux/kernel.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pnp.h> | |
31 | #include <linux/io.h> | |
32 | #include <linux/interrupt.h> | |
33 | #include <linux/sched.h> | |
34 | #include <linux/slab.h> | |
6bda9644 | 35 | #include <media/rc-core.h> |
6d2f5c27 JW |
36 | #include <linux/pci_ids.h> |
37 | ||
38 | #include "nuvoton-cir.h" | |
39 | ||
40 | static char *chip_id = "w836x7hg"; | |
41 | ||
42 | /* write val to config reg */ | |
43 | static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg) | |
44 | { | |
45 | outb(reg, nvt->cr_efir); | |
46 | outb(val, nvt->cr_efdr); | |
47 | } | |
48 | ||
49 | /* read val from config reg */ | |
50 | static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg) | |
51 | { | |
52 | outb(reg, nvt->cr_efir); | |
53 | return inb(nvt->cr_efdr); | |
54 | } | |
55 | ||
56 | /* update config register bit without changing other bits */ | |
57 | static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg) | |
58 | { | |
59 | u8 tmp = nvt_cr_read(nvt, reg) | val; | |
60 | nvt_cr_write(nvt, tmp, reg); | |
61 | } | |
62 | ||
63 | /* clear config register bit without changing other bits */ | |
64 | static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg) | |
65 | { | |
66 | u8 tmp = nvt_cr_read(nvt, reg) & ~val; | |
67 | nvt_cr_write(nvt, tmp, reg); | |
68 | } | |
69 | ||
70 | /* enter extended function mode */ | |
71 | static inline void nvt_efm_enable(struct nvt_dev *nvt) | |
72 | { | |
73 | /* Enabling Extended Function Mode explicitly requires writing 2x */ | |
74 | outb(EFER_EFM_ENABLE, nvt->cr_efir); | |
75 | outb(EFER_EFM_ENABLE, nvt->cr_efir); | |
76 | } | |
77 | ||
78 | /* exit extended function mode */ | |
79 | static inline void nvt_efm_disable(struct nvt_dev *nvt) | |
80 | { | |
81 | outb(EFER_EFM_DISABLE, nvt->cr_efir); | |
82 | } | |
83 | ||
84 | /* | |
85 | * When you want to address a specific logical device, write its logical | |
86 | * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing | |
87 | * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN. | |
88 | */ | |
89 | static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev) | |
90 | { | |
91 | outb(CR_LOGICAL_DEV_SEL, nvt->cr_efir); | |
92 | outb(ldev, nvt->cr_efdr); | |
93 | } | |
94 | ||
95 | /* write val to cir config register */ | |
96 | static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset) | |
97 | { | |
98 | outb(val, nvt->cir_addr + offset); | |
99 | } | |
100 | ||
101 | /* read val from cir config register */ | |
102 | static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset) | |
103 | { | |
104 | u8 val; | |
105 | ||
106 | val = inb(nvt->cir_addr + offset); | |
107 | ||
108 | return val; | |
109 | } | |
110 | ||
111 | /* write val to cir wake register */ | |
112 | static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt, | |
113 | u8 val, u8 offset) | |
114 | { | |
115 | outb(val, nvt->cir_wake_addr + offset); | |
116 | } | |
117 | ||
118 | /* read val from cir wake config register */ | |
119 | static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset) | |
120 | { | |
121 | u8 val; | |
122 | ||
123 | val = inb(nvt->cir_wake_addr + offset); | |
124 | ||
125 | return val; | |
126 | } | |
127 | ||
4e6e29ad JW |
128 | #define pr_reg(text, ...) \ |
129 | printk(KERN_INFO KBUILD_MODNAME ": " text, ## __VA_ARGS__) | |
130 | ||
6d2f5c27 JW |
131 | /* dump current cir register contents */ |
132 | static void cir_dump_regs(struct nvt_dev *nvt) | |
133 | { | |
134 | nvt_efm_enable(nvt); | |
135 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); | |
136 | ||
4e6e29ad JW |
137 | pr_reg("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME); |
138 | pr_reg(" * CR CIR ACTIVE : 0x%x\n", | |
6d2f5c27 | 139 | nvt_cr_read(nvt, CR_LOGICAL_DEV_EN)); |
4e6e29ad | 140 | pr_reg(" * CR CIR BASE ADDR: 0x%x\n", |
6d2f5c27 JW |
141 | (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) | |
142 | nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO)); | |
4e6e29ad | 143 | pr_reg(" * CR CIR IRQ NUM: 0x%x\n", |
6d2f5c27 JW |
144 | nvt_cr_read(nvt, CR_CIR_IRQ_RSRC)); |
145 | ||
146 | nvt_efm_disable(nvt); | |
147 | ||
4e6e29ad JW |
148 | pr_reg("%s: Dump CIR registers:\n", NVT_DRIVER_NAME); |
149 | pr_reg(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON)); | |
150 | pr_reg(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS)); | |
151 | pr_reg(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN)); | |
152 | pr_reg(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT)); | |
153 | pr_reg(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP)); | |
154 | pr_reg(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC)); | |
155 | pr_reg(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH)); | |
156 | pr_reg(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL)); | |
157 | pr_reg(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON)); | |
158 | pr_reg(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS)); | |
159 | pr_reg(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO)); | |
160 | pr_reg(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT)); | |
161 | pr_reg(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO)); | |
162 | pr_reg(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH)); | |
163 | pr_reg(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL)); | |
164 | pr_reg(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM)); | |
6d2f5c27 JW |
165 | } |
166 | ||
167 | /* dump current cir wake register contents */ | |
168 | static void cir_wake_dump_regs(struct nvt_dev *nvt) | |
169 | { | |
170 | u8 i, fifo_len; | |
171 | ||
172 | nvt_efm_enable(nvt); | |
173 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); | |
174 | ||
4e6e29ad | 175 | pr_reg("%s: Dump CIR WAKE logical device registers:\n", |
6d2f5c27 | 176 | NVT_DRIVER_NAME); |
4e6e29ad | 177 | pr_reg(" * CR CIR WAKE ACTIVE : 0x%x\n", |
6d2f5c27 | 178 | nvt_cr_read(nvt, CR_LOGICAL_DEV_EN)); |
4e6e29ad | 179 | pr_reg(" * CR CIR WAKE BASE ADDR: 0x%x\n", |
6d2f5c27 | 180 | (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) | |
4e6e29ad JW |
181 | nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO)); |
182 | pr_reg(" * CR CIR WAKE IRQ NUM: 0x%x\n", | |
6d2f5c27 JW |
183 | nvt_cr_read(nvt, CR_CIR_IRQ_RSRC)); |
184 | ||
185 | nvt_efm_disable(nvt); | |
186 | ||
4e6e29ad JW |
187 | pr_reg("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME); |
188 | pr_reg(" * IRCON: 0x%x\n", | |
6d2f5c27 | 189 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON)); |
4e6e29ad | 190 | pr_reg(" * IRSTS: 0x%x\n", |
6d2f5c27 | 191 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS)); |
4e6e29ad | 192 | pr_reg(" * IREN: 0x%x\n", |
6d2f5c27 | 193 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN)); |
4e6e29ad | 194 | pr_reg(" * FIFO CMP DEEP: 0x%x\n", |
6d2f5c27 | 195 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP)); |
4e6e29ad | 196 | pr_reg(" * FIFO CMP TOL: 0x%x\n", |
6d2f5c27 | 197 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL)); |
4e6e29ad | 198 | pr_reg(" * FIFO COUNT: 0x%x\n", |
6d2f5c27 | 199 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT)); |
4e6e29ad | 200 | pr_reg(" * SLCH: 0x%x\n", |
6d2f5c27 | 201 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH)); |
4e6e29ad | 202 | pr_reg(" * SLCL: 0x%x\n", |
6d2f5c27 | 203 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL)); |
4e6e29ad | 204 | pr_reg(" * FIFOCON: 0x%x\n", |
6d2f5c27 | 205 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON)); |
4e6e29ad | 206 | pr_reg(" * SRXFSTS: 0x%x\n", |
6d2f5c27 | 207 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS)); |
4e6e29ad | 208 | pr_reg(" * SAMPLE RX FIFO: 0x%x\n", |
6d2f5c27 | 209 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO)); |
4e6e29ad | 210 | pr_reg(" * WR FIFO DATA: 0x%x\n", |
6d2f5c27 | 211 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA)); |
4e6e29ad | 212 | pr_reg(" * RD FIFO ONLY: 0x%x\n", |
6d2f5c27 | 213 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY)); |
4e6e29ad | 214 | pr_reg(" * RD FIFO ONLY IDX: 0x%x\n", |
6d2f5c27 | 215 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)); |
4e6e29ad | 216 | pr_reg(" * FIFO IGNORE: 0x%x\n", |
6d2f5c27 | 217 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE)); |
4e6e29ad | 218 | pr_reg(" * IRFSM: 0x%x\n", |
6d2f5c27 JW |
219 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM)); |
220 | ||
221 | fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT); | |
4e6e29ad JW |
222 | pr_reg("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len); |
223 | pr_reg("* Contents = "); | |
6d2f5c27 | 224 | for (i = 0; i < fifo_len; i++) |
4e6e29ad | 225 | printk(KERN_CONT "%02x ", |
6d2f5c27 | 226 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY)); |
4e6e29ad | 227 | printk(KERN_CONT "\n"); |
6d2f5c27 JW |
228 | } |
229 | ||
230 | /* detect hardware features */ | |
231 | static int nvt_hw_detect(struct nvt_dev *nvt) | |
232 | { | |
233 | unsigned long flags; | |
234 | u8 chip_major, chip_minor; | |
235 | int ret = 0; | |
236 | ||
237 | nvt_efm_enable(nvt); | |
238 | ||
239 | /* Check if we're wired for the alternate EFER setup */ | |
240 | chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI); | |
241 | if (chip_major == 0xff) { | |
242 | nvt->cr_efir = CR_EFIR2; | |
243 | nvt->cr_efdr = CR_EFDR2; | |
244 | nvt_efm_enable(nvt); | |
245 | chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI); | |
246 | } | |
247 | ||
248 | chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO); | |
249 | nvt_dbg("%s: chip id: 0x%02x 0x%02x", chip_id, chip_major, chip_minor); | |
250 | ||
5df465df NK |
251 | if (chip_major != CHIP_ID_HIGH || |
252 | (chip_minor != CHIP_ID_LOW && chip_minor != CHIP_ID_LOW2)) { | |
253 | nvt_pr(KERN_ERR, "%s: unsupported chip, id: 0x%02x 0x%02x", | |
254 | chip_id, chip_major, chip_minor); | |
6d2f5c27 | 255 | ret = -ENODEV; |
5df465df | 256 | } |
6d2f5c27 JW |
257 | |
258 | nvt_efm_disable(nvt); | |
259 | ||
260 | spin_lock_irqsave(&nvt->nvt_lock, flags); | |
261 | nvt->chip_major = chip_major; | |
262 | nvt->chip_minor = chip_minor; | |
263 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); | |
264 | ||
265 | return ret; | |
266 | } | |
267 | ||
268 | static void nvt_cir_ldev_init(struct nvt_dev *nvt) | |
269 | { | |
270 | u8 val; | |
271 | ||
272 | /* output pin selection (Pin95=CIRRX, Pin96=CIRTX1, WB enabled */ | |
273 | val = nvt_cr_read(nvt, CR_OUTPUT_PIN_SEL); | |
274 | val &= OUTPUT_PIN_SEL_MASK; | |
275 | val |= (OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB); | |
276 | nvt_cr_write(nvt, val, CR_OUTPUT_PIN_SEL); | |
277 | ||
278 | /* Select CIR logical device and enable */ | |
279 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); | |
280 | nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); | |
281 | ||
282 | nvt_cr_write(nvt, nvt->cir_addr >> 8, CR_CIR_BASE_ADDR_HI); | |
283 | nvt_cr_write(nvt, nvt->cir_addr & 0xff, CR_CIR_BASE_ADDR_LO); | |
284 | ||
285 | nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC); | |
286 | ||
287 | nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d", | |
288 | nvt->cir_addr, nvt->cir_irq); | |
289 | } | |
290 | ||
291 | static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt) | |
292 | { | |
293 | /* Select ACPI logical device, enable it and CIR Wake */ | |
294 | nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI); | |
295 | nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); | |
296 | ||
297 | /* Enable CIR Wake via PSOUT# (Pin60) */ | |
298 | nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE); | |
299 | ||
300 | /* enable cir interrupt of mouse/keyboard IRQ event */ | |
301 | nvt_set_reg_bit(nvt, CIR_INTR_MOUSE_IRQ_BIT, CR_ACPI_IRQ_EVENTS); | |
302 | ||
303 | /* enable pme interrupt of cir wakeup event */ | |
304 | nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2); | |
305 | ||
306 | /* Select CIR Wake logical device and enable */ | |
307 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); | |
308 | nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); | |
309 | ||
310 | nvt_cr_write(nvt, nvt->cir_wake_addr >> 8, CR_CIR_BASE_ADDR_HI); | |
311 | nvt_cr_write(nvt, nvt->cir_wake_addr & 0xff, CR_CIR_BASE_ADDR_LO); | |
312 | ||
313 | nvt_cr_write(nvt, nvt->cir_wake_irq, CR_CIR_IRQ_RSRC); | |
314 | ||
315 | nvt_dbg("CIR Wake initialized, base io port address: 0x%lx, irq: %d", | |
316 | nvt->cir_wake_addr, nvt->cir_wake_irq); | |
317 | } | |
318 | ||
319 | /* clear out the hardware's cir rx fifo */ | |
320 | static void nvt_clear_cir_fifo(struct nvt_dev *nvt) | |
321 | { | |
322 | u8 val; | |
323 | ||
324 | val = nvt_cir_reg_read(nvt, CIR_FIFOCON); | |
325 | nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON); | |
326 | } | |
327 | ||
328 | /* clear out the hardware's cir wake rx fifo */ | |
329 | static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt) | |
330 | { | |
331 | u8 val; | |
332 | ||
333 | val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON); | |
334 | nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR, | |
335 | CIR_WAKE_FIFOCON); | |
336 | } | |
337 | ||
338 | /* clear out the hardware's cir tx fifo */ | |
339 | static void nvt_clear_tx_fifo(struct nvt_dev *nvt) | |
340 | { | |
341 | u8 val; | |
342 | ||
343 | val = nvt_cir_reg_read(nvt, CIR_FIFOCON); | |
344 | nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON); | |
345 | } | |
346 | ||
fbdc781c JW |
347 | /* enable RX Trigger Level Reach and Packet End interrupts */ |
348 | static void nvt_set_cir_iren(struct nvt_dev *nvt) | |
349 | { | |
350 | u8 iren; | |
351 | ||
352 | iren = CIR_IREN_RTR | CIR_IREN_PE; | |
353 | nvt_cir_reg_write(nvt, iren, CIR_IREN); | |
354 | } | |
355 | ||
6d2f5c27 JW |
356 | static void nvt_cir_regs_init(struct nvt_dev *nvt) |
357 | { | |
358 | /* set sample limit count (PE interrupt raised when reached) */ | |
359 | nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH); | |
360 | nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL); | |
361 | ||
362 | /* set fifo irq trigger levels */ | |
363 | nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV | | |
364 | CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON); | |
365 | ||
366 | /* | |
367 | * Enable TX and RX, specify carrier on = low, off = high, and set | |
368 | * sample period (currently 50us) | |
369 | */ | |
4e6e29ad JW |
370 | nvt_cir_reg_write(nvt, |
371 | CIR_IRCON_TXEN | CIR_IRCON_RXEN | | |
372 | CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL, | |
373 | CIR_IRCON); | |
6d2f5c27 JW |
374 | |
375 | /* clear hardware rx and tx fifos */ | |
376 | nvt_clear_cir_fifo(nvt); | |
377 | nvt_clear_tx_fifo(nvt); | |
378 | ||
379 | /* clear any and all stray interrupts */ | |
380 | nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS); | |
381 | ||
fbdc781c JW |
382 | /* and finally, enable interrupts */ |
383 | nvt_set_cir_iren(nvt); | |
6d2f5c27 JW |
384 | } |
385 | ||
386 | static void nvt_cir_wake_regs_init(struct nvt_dev *nvt) | |
387 | { | |
3198ed16 JW |
388 | /* set number of bytes needed for wake from s3 (default 65) */ |
389 | nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFO_CMP_BYTES, | |
390 | CIR_WAKE_FIFO_CMP_DEEP); | |
6d2f5c27 JW |
391 | |
392 | /* set tolerance/variance allowed per byte during wake compare */ | |
393 | nvt_cir_wake_reg_write(nvt, CIR_WAKE_CMP_TOLERANCE, | |
394 | CIR_WAKE_FIFO_CMP_TOL); | |
395 | ||
396 | /* set sample limit count (PE interrupt raised when reached) */ | |
397 | nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_WAKE_SLCH); | |
398 | nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_WAKE_SLCL); | |
399 | ||
400 | /* set cir wake fifo rx trigger level (currently 67) */ | |
401 | nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFOCON_RX_TRIGGER_LEV, | |
402 | CIR_WAKE_FIFOCON); | |
403 | ||
404 | /* | |
405 | * Enable TX and RX, specific carrier on = low, off = high, and set | |
406 | * sample period (currently 50us) | |
407 | */ | |
408 | nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN | | |
409 | CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV | | |
410 | CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL, | |
411 | CIR_WAKE_IRCON); | |
412 | ||
413 | /* clear cir wake rx fifo */ | |
414 | nvt_clear_cir_wake_fifo(nvt); | |
415 | ||
416 | /* clear any and all stray interrupts */ | |
417 | nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS); | |
418 | } | |
419 | ||
420 | static void nvt_enable_wake(struct nvt_dev *nvt) | |
421 | { | |
422 | nvt_efm_enable(nvt); | |
423 | ||
424 | nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI); | |
425 | nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE); | |
426 | nvt_set_reg_bit(nvt, CIR_INTR_MOUSE_IRQ_BIT, CR_ACPI_IRQ_EVENTS); | |
427 | nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2); | |
428 | ||
429 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); | |
430 | nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); | |
431 | ||
432 | nvt_efm_disable(nvt); | |
433 | ||
434 | nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN | | |
435 | CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV | | |
4e6e29ad JW |
436 | CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL, |
437 | CIR_WAKE_IRCON); | |
6d2f5c27 JW |
438 | nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS); |
439 | nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN); | |
440 | } | |
441 | ||
442 | /* rx carrier detect only works in learning mode, must be called w/nvt_lock */ | |
443 | static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt) | |
444 | { | |
445 | u32 count, carrier, duration = 0; | |
446 | int i; | |
447 | ||
448 | count = nvt_cir_reg_read(nvt, CIR_FCCL) | | |
449 | nvt_cir_reg_read(nvt, CIR_FCCH) << 8; | |
450 | ||
451 | for (i = 0; i < nvt->pkts; i++) { | |
452 | if (nvt->buf[i] & BUF_PULSE_BIT) | |
453 | duration += nvt->buf[i] & BUF_LEN_MASK; | |
454 | } | |
455 | ||
456 | duration *= SAMPLE_PERIOD; | |
457 | ||
458 | if (!count || !duration) { | |
459 | nvt_pr(KERN_NOTICE, "Unable to determine carrier! (c:%u, d:%u)", | |
460 | count, duration); | |
461 | return 0; | |
462 | } | |
463 | ||
b4608fae | 464 | carrier = MS_TO_NS(count) / duration; |
6d2f5c27 JW |
465 | |
466 | if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER)) | |
467 | nvt_dbg("WTF? Carrier frequency out of range!"); | |
468 | ||
469 | nvt_dbg("Carrier frequency: %u (count %u, duration %u)", | |
470 | carrier, count, duration); | |
471 | ||
472 | return carrier; | |
473 | } | |
474 | ||
475 | /* | |
476 | * set carrier frequency | |
477 | * | |
478 | * set carrier on 2 registers: CP & CC | |
479 | * always set CP as 0x81 | |
480 | * set CC by SPEC, CC = 3MHz/carrier - 1 | |
481 | */ | |
d8b4b582 | 482 | static int nvt_set_tx_carrier(struct rc_dev *dev, u32 carrier) |
6d2f5c27 | 483 | { |
d8b4b582 | 484 | struct nvt_dev *nvt = dev->priv; |
6d2f5c27 JW |
485 | u16 val; |
486 | ||
487 | nvt_cir_reg_write(nvt, 1, CIR_CP); | |
488 | val = 3000000 / (carrier) - 1; | |
489 | nvt_cir_reg_write(nvt, val & 0xff, CIR_CC); | |
490 | ||
491 | nvt_dbg("cp: 0x%x cc: 0x%x\n", | |
492 | nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC)); | |
493 | ||
494 | return 0; | |
495 | } | |
496 | ||
497 | /* | |
498 | * nvt_tx_ir | |
499 | * | |
500 | * 1) clean TX fifo first (handled by AP) | |
501 | * 2) copy data from user space | |
502 | * 3) disable RX interrupts, enable TX interrupts: TTR & TFU | |
503 | * 4) send 9 packets to TX FIFO to open TTR | |
504 | * in interrupt_handler: | |
505 | * 5) send all data out | |
506 | * go back to write(): | |
507 | * 6) disable TX interrupts, re-enable RX interupts | |
508 | * | |
509 | * The key problem of this function is user space data may larger than | |
510 | * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to | |
511 | * buf, and keep current copied data buf num in cur_buf_num. But driver's buf | |
512 | * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to | |
513 | * set TXFCONT as 0xff, until buf_count less than 0xff. | |
514 | */ | |
d8b4b582 | 515 | static int nvt_tx_ir(struct rc_dev *dev, int *txbuf, u32 n) |
6d2f5c27 | 516 | { |
d8b4b582 | 517 | struct nvt_dev *nvt = dev->priv; |
6d2f5c27 JW |
518 | unsigned long flags; |
519 | size_t cur_count; | |
520 | unsigned int i; | |
521 | u8 iren; | |
522 | int ret; | |
523 | ||
524 | spin_lock_irqsave(&nvt->tx.lock, flags); | |
525 | ||
526 | if (n >= TX_BUF_LEN) { | |
527 | nvt->tx.buf_count = cur_count = TX_BUF_LEN; | |
528 | ret = TX_BUF_LEN; | |
529 | } else { | |
530 | nvt->tx.buf_count = cur_count = n; | |
531 | ret = n; | |
532 | } | |
533 | ||
534 | memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count); | |
535 | ||
536 | nvt->tx.cur_buf_num = 0; | |
537 | ||
538 | /* save currently enabled interrupts */ | |
539 | iren = nvt_cir_reg_read(nvt, CIR_IREN); | |
540 | ||
541 | /* now disable all interrupts, save TFU & TTR */ | |
542 | nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN); | |
543 | ||
544 | nvt->tx.tx_state = ST_TX_REPLY; | |
545 | ||
546 | nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 | | |
547 | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON); | |
548 | ||
549 | /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */ | |
550 | for (i = 0; i < 9; i++) | |
551 | nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO); | |
552 | ||
553 | spin_unlock_irqrestore(&nvt->tx.lock, flags); | |
554 | ||
555 | wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST); | |
556 | ||
557 | spin_lock_irqsave(&nvt->tx.lock, flags); | |
558 | nvt->tx.tx_state = ST_TX_NONE; | |
559 | spin_unlock_irqrestore(&nvt->tx.lock, flags); | |
560 | ||
561 | /* restore enabled interrupts to prior state */ | |
562 | nvt_cir_reg_write(nvt, iren, CIR_IREN); | |
563 | ||
564 | return ret; | |
565 | } | |
566 | ||
567 | /* dump contents of the last rx buffer we got from the hw rx fifo */ | |
568 | static void nvt_dump_rx_buf(struct nvt_dev *nvt) | |
569 | { | |
570 | int i; | |
571 | ||
4e6e29ad | 572 | printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts); |
6d2f5c27 | 573 | for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++) |
4e6e29ad JW |
574 | printk(KERN_CONT "0x%02x ", nvt->buf[i]); |
575 | printk(KERN_CONT "\n"); | |
6d2f5c27 JW |
576 | } |
577 | ||
578 | /* | |
579 | * Process raw data in rx driver buffer, store it in raw IR event kfifo, | |
580 | * trigger decode when appropriate. | |
581 | * | |
582 | * We get IR data samples one byte at a time. If the msb is set, its a pulse, | |
583 | * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD | |
584 | * (default 50us) intervals for that pulse/space. A discrete signal is | |
585 | * followed by a series of 0x7f packets, then either 0x7<something> or 0x80 | |
586 | * to signal more IR coming (repeats) or end of IR, respectively. We store | |
587 | * sample data in the raw event kfifo until we see 0x7<something> (except f) | |
588 | * or 0x80, at which time, we trigger a decode operation. | |
589 | */ | |
590 | static void nvt_process_rx_ir_data(struct nvt_dev *nvt) | |
591 | { | |
4651918a | 592 | DEFINE_IR_RAW_EVENT(rawir); |
6d2f5c27 JW |
593 | unsigned int count; |
594 | u32 carrier; | |
595 | u8 sample; | |
596 | int i; | |
597 | ||
598 | nvt_dbg_verbose("%s firing", __func__); | |
599 | ||
600 | if (debug) | |
601 | nvt_dump_rx_buf(nvt); | |
602 | ||
603 | if (nvt->carrier_detect_enabled) | |
604 | carrier = nvt_rx_carrier_detect(nvt); | |
605 | ||
606 | count = nvt->pkts; | |
607 | nvt_dbg_verbose("Processing buffer of len %d", count); | |
608 | ||
b7582815 JW |
609 | init_ir_raw_event(&rawir); |
610 | ||
6d2f5c27 JW |
611 | for (i = 0; i < count; i++) { |
612 | nvt->pkts--; | |
613 | sample = nvt->buf[i]; | |
614 | ||
615 | rawir.pulse = ((sample & BUF_PULSE_BIT) != 0); | |
b4608fae JW |
616 | rawir.duration = US_TO_NS((sample & BUF_LEN_MASK) |
617 | * SAMPLE_PERIOD); | |
6d2f5c27 JW |
618 | |
619 | if ((sample & BUF_LEN_MASK) == BUF_LEN_MASK) { | |
620 | if (nvt->rawir.pulse == rawir.pulse) | |
621 | nvt->rawir.duration += rawir.duration; | |
622 | else { | |
623 | nvt->rawir.duration = rawir.duration; | |
624 | nvt->rawir.pulse = rawir.pulse; | |
625 | } | |
626 | continue; | |
627 | } | |
628 | ||
629 | rawir.duration += nvt->rawir.duration; | |
4651918a ML |
630 | |
631 | init_ir_raw_event(&nvt->rawir); | |
6d2f5c27 JW |
632 | nvt->rawir.duration = 0; |
633 | nvt->rawir.pulse = rawir.pulse; | |
634 | ||
635 | if (sample == BUF_PULSE_BIT) | |
636 | rawir.pulse = false; | |
637 | ||
638 | if (rawir.duration) { | |
639 | nvt_dbg("Storing %s with duration %d", | |
640 | rawir.pulse ? "pulse" : "space", | |
641 | rawir.duration); | |
642 | ||
643 | ir_raw_event_store(nvt->rdev, &rawir); | |
644 | } | |
645 | ||
646 | /* | |
647 | * BUF_PULSE_BIT indicates end of IR data, BUF_REPEAT_BYTE | |
648 | * indicates end of IR signal, but new data incoming. In both | |
649 | * cases, it means we're ready to call ir_raw_event_handle | |
650 | */ | |
b7582815 JW |
651 | if ((sample == BUF_PULSE_BIT) && nvt->pkts) { |
652 | nvt_dbg("Calling ir_raw_event_handle (signal end)\n"); | |
6d2f5c27 | 653 | ir_raw_event_handle(nvt->rdev); |
b7582815 | 654 | } |
6d2f5c27 JW |
655 | } |
656 | ||
b7582815 JW |
657 | nvt_dbg("Calling ir_raw_event_handle (buffer empty)\n"); |
658 | ir_raw_event_handle(nvt->rdev); | |
659 | ||
6d2f5c27 JW |
660 | if (nvt->pkts) { |
661 | nvt_dbg("Odd, pkts should be 0 now... (its %u)", nvt->pkts); | |
662 | nvt->pkts = 0; | |
663 | } | |
664 | ||
665 | nvt_dbg_verbose("%s done", __func__); | |
666 | } | |
667 | ||
fbdc781c JW |
668 | static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt) |
669 | { | |
670 | nvt_pr(KERN_WARNING, "RX FIFO overrun detected, flushing data!"); | |
671 | ||
672 | nvt->pkts = 0; | |
673 | nvt_clear_cir_fifo(nvt); | |
674 | ir_raw_event_reset(nvt->rdev); | |
675 | } | |
676 | ||
6d2f5c27 JW |
677 | /* copy data from hardware rx fifo into driver buffer */ |
678 | static void nvt_get_rx_ir_data(struct nvt_dev *nvt) | |
679 | { | |
680 | unsigned long flags; | |
681 | u8 fifocount, val; | |
682 | unsigned int b_idx; | |
fbdc781c | 683 | bool overrun = false; |
6d2f5c27 JW |
684 | int i; |
685 | ||
686 | /* Get count of how many bytes to read from RX FIFO */ | |
687 | fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT); | |
688 | /* if we get 0xff, probably means the logical dev is disabled */ | |
689 | if (fifocount == 0xff) | |
690 | return; | |
fbdc781c | 691 | /* watch out for a fifo overrun condition */ |
6d2f5c27 | 692 | else if (fifocount > RX_BUF_LEN) { |
fbdc781c JW |
693 | overrun = true; |
694 | fifocount = RX_BUF_LEN; | |
6d2f5c27 JW |
695 | } |
696 | ||
697 | nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount); | |
698 | ||
699 | spin_lock_irqsave(&nvt->nvt_lock, flags); | |
700 | ||
701 | b_idx = nvt->pkts; | |
702 | ||
703 | /* This should never happen, but lets check anyway... */ | |
704 | if (b_idx + fifocount > RX_BUF_LEN) { | |
705 | nvt_process_rx_ir_data(nvt); | |
706 | b_idx = 0; | |
707 | } | |
708 | ||
709 | /* Read fifocount bytes from CIR Sample RX FIFO register */ | |
710 | for (i = 0; i < fifocount; i++) { | |
711 | val = nvt_cir_reg_read(nvt, CIR_SRXFIFO); | |
712 | nvt->buf[b_idx + i] = val; | |
713 | } | |
714 | ||
715 | nvt->pkts += fifocount; | |
716 | nvt_dbg("%s: pkts now %d", __func__, nvt->pkts); | |
717 | ||
718 | nvt_process_rx_ir_data(nvt); | |
719 | ||
fbdc781c JW |
720 | if (overrun) |
721 | nvt_handle_rx_fifo_overrun(nvt); | |
722 | ||
6d2f5c27 JW |
723 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); |
724 | } | |
725 | ||
726 | static void nvt_cir_log_irqs(u8 status, u8 iren) | |
727 | { | |
728 | nvt_pr(KERN_INFO, "IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s", | |
729 | status, iren, | |
730 | status & CIR_IRSTS_RDR ? " RDR" : "", | |
731 | status & CIR_IRSTS_RTR ? " RTR" : "", | |
732 | status & CIR_IRSTS_PE ? " PE" : "", | |
733 | status & CIR_IRSTS_RFO ? " RFO" : "", | |
734 | status & CIR_IRSTS_TE ? " TE" : "", | |
735 | status & CIR_IRSTS_TTR ? " TTR" : "", | |
736 | status & CIR_IRSTS_TFU ? " TFU" : "", | |
737 | status & CIR_IRSTS_GH ? " GH" : "", | |
738 | status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE | | |
739 | CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR | | |
740 | CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : ""); | |
741 | } | |
742 | ||
743 | static bool nvt_cir_tx_inactive(struct nvt_dev *nvt) | |
744 | { | |
745 | unsigned long flags; | |
746 | bool tx_inactive; | |
747 | u8 tx_state; | |
748 | ||
749 | spin_lock_irqsave(&nvt->tx.lock, flags); | |
750 | tx_state = nvt->tx.tx_state; | |
751 | spin_unlock_irqrestore(&nvt->tx.lock, flags); | |
752 | ||
753 | tx_inactive = (tx_state == ST_TX_NONE); | |
754 | ||
755 | return tx_inactive; | |
756 | } | |
757 | ||
758 | /* interrupt service routine for incoming and outgoing CIR data */ | |
759 | static irqreturn_t nvt_cir_isr(int irq, void *data) | |
760 | { | |
761 | struct nvt_dev *nvt = data; | |
762 | u8 status, iren, cur_state; | |
763 | unsigned long flags; | |
764 | ||
765 | nvt_dbg_verbose("%s firing", __func__); | |
766 | ||
767 | nvt_efm_enable(nvt); | |
768 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); | |
769 | nvt_efm_disable(nvt); | |
770 | ||
771 | /* | |
772 | * Get IR Status register contents. Write 1 to ack/clear | |
773 | * | |
774 | * bit: reg name - description | |
775 | * 7: CIR_IRSTS_RDR - RX Data Ready | |
776 | * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach | |
777 | * 5: CIR_IRSTS_PE - Packet End | |
778 | * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set) | |
779 | * 3: CIR_IRSTS_TE - TX FIFO Empty | |
780 | * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach | |
781 | * 1: CIR_IRSTS_TFU - TX FIFO Underrun | |
782 | * 0: CIR_IRSTS_GH - Min Length Detected | |
783 | */ | |
784 | status = nvt_cir_reg_read(nvt, CIR_IRSTS); | |
785 | if (!status) { | |
786 | nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__); | |
787 | nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS); | |
788 | return IRQ_RETVAL(IRQ_NONE); | |
789 | } | |
790 | ||
791 | /* ack/clear all irq flags we've got */ | |
792 | nvt_cir_reg_write(nvt, status, CIR_IRSTS); | |
793 | nvt_cir_reg_write(nvt, 0, CIR_IRSTS); | |
794 | ||
795 | /* Interrupt may be shared with CIR Wake, bail if CIR not enabled */ | |
796 | iren = nvt_cir_reg_read(nvt, CIR_IREN); | |
797 | if (!iren) { | |
798 | nvt_dbg_verbose("%s exiting, CIR not enabled", __func__); | |
799 | return IRQ_RETVAL(IRQ_NONE); | |
800 | } | |
801 | ||
802 | if (debug) | |
803 | nvt_cir_log_irqs(status, iren); | |
804 | ||
805 | if (status & CIR_IRSTS_RTR) { | |
806 | /* FIXME: add code for study/learn mode */ | |
807 | /* We only do rx if not tx'ing */ | |
808 | if (nvt_cir_tx_inactive(nvt)) | |
809 | nvt_get_rx_ir_data(nvt); | |
810 | } | |
811 | ||
812 | if (status & CIR_IRSTS_PE) { | |
813 | if (nvt_cir_tx_inactive(nvt)) | |
814 | nvt_get_rx_ir_data(nvt); | |
815 | ||
816 | spin_lock_irqsave(&nvt->nvt_lock, flags); | |
817 | ||
818 | cur_state = nvt->study_state; | |
819 | ||
820 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); | |
821 | ||
822 | if (cur_state == ST_STUDY_NONE) | |
823 | nvt_clear_cir_fifo(nvt); | |
824 | } | |
825 | ||
826 | if (status & CIR_IRSTS_TE) | |
827 | nvt_clear_tx_fifo(nvt); | |
828 | ||
829 | if (status & CIR_IRSTS_TTR) { | |
830 | unsigned int pos, count; | |
831 | u8 tmp; | |
832 | ||
833 | spin_lock_irqsave(&nvt->tx.lock, flags); | |
834 | ||
835 | pos = nvt->tx.cur_buf_num; | |
836 | count = nvt->tx.buf_count; | |
837 | ||
838 | /* Write data into the hardware tx fifo while pos < count */ | |
839 | if (pos < count) { | |
840 | nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO); | |
841 | nvt->tx.cur_buf_num++; | |
842 | /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */ | |
843 | } else { | |
844 | tmp = nvt_cir_reg_read(nvt, CIR_IREN); | |
845 | nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN); | |
846 | } | |
847 | ||
848 | spin_unlock_irqrestore(&nvt->tx.lock, flags); | |
849 | ||
850 | } | |
851 | ||
852 | if (status & CIR_IRSTS_TFU) { | |
853 | spin_lock_irqsave(&nvt->tx.lock, flags); | |
854 | if (nvt->tx.tx_state == ST_TX_REPLY) { | |
855 | nvt->tx.tx_state = ST_TX_REQUEST; | |
856 | wake_up(&nvt->tx.queue); | |
857 | } | |
858 | spin_unlock_irqrestore(&nvt->tx.lock, flags); | |
859 | } | |
860 | ||
861 | nvt_dbg_verbose("%s done", __func__); | |
862 | return IRQ_RETVAL(IRQ_HANDLED); | |
863 | } | |
864 | ||
865 | /* Interrupt service routine for CIR Wake */ | |
866 | static irqreturn_t nvt_cir_wake_isr(int irq, void *data) | |
867 | { | |
868 | u8 status, iren, val; | |
869 | struct nvt_dev *nvt = data; | |
870 | unsigned long flags; | |
871 | ||
872 | nvt_dbg_wake("%s firing", __func__); | |
873 | ||
874 | status = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS); | |
875 | if (!status) | |
876 | return IRQ_RETVAL(IRQ_NONE); | |
877 | ||
878 | if (status & CIR_WAKE_IRSTS_IR_PENDING) | |
879 | nvt_clear_cir_wake_fifo(nvt); | |
880 | ||
881 | nvt_cir_wake_reg_write(nvt, status, CIR_WAKE_IRSTS); | |
882 | nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IRSTS); | |
883 | ||
884 | /* Interrupt may be shared with CIR, bail if Wake not enabled */ | |
885 | iren = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN); | |
886 | if (!iren) { | |
887 | nvt_dbg_wake("%s exiting, wake not enabled", __func__); | |
888 | return IRQ_RETVAL(IRQ_HANDLED); | |
889 | } | |
890 | ||
891 | if ((status & CIR_WAKE_IRSTS_PE) && | |
892 | (nvt->wake_state == ST_WAKE_START)) { | |
893 | while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)) { | |
894 | val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY); | |
895 | nvt_dbg("setting wake up key: 0x%x", val); | |
896 | } | |
897 | ||
898 | nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN); | |
899 | spin_lock_irqsave(&nvt->nvt_lock, flags); | |
900 | nvt->wake_state = ST_WAKE_FINISH; | |
901 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); | |
902 | } | |
903 | ||
904 | nvt_dbg_wake("%s done", __func__); | |
905 | return IRQ_RETVAL(IRQ_HANDLED); | |
906 | } | |
907 | ||
908 | static void nvt_enable_cir(struct nvt_dev *nvt) | |
909 | { | |
910 | /* set function enable flags */ | |
911 | nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN | | |
912 | CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL, | |
913 | CIR_IRCON); | |
914 | ||
915 | nvt_efm_enable(nvt); | |
916 | ||
917 | /* enable the CIR logical device */ | |
918 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); | |
919 | nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); | |
920 | ||
921 | nvt_efm_disable(nvt); | |
922 | ||
923 | /* clear all pending interrupts */ | |
924 | nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS); | |
925 | ||
926 | /* enable interrupts */ | |
fbdc781c | 927 | nvt_set_cir_iren(nvt); |
6d2f5c27 JW |
928 | } |
929 | ||
930 | static void nvt_disable_cir(struct nvt_dev *nvt) | |
931 | { | |
932 | /* disable CIR interrupts */ | |
933 | nvt_cir_reg_write(nvt, 0, CIR_IREN); | |
934 | ||
935 | /* clear any and all pending interrupts */ | |
936 | nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS); | |
937 | ||
938 | /* clear all function enable flags */ | |
939 | nvt_cir_reg_write(nvt, 0, CIR_IRCON); | |
940 | ||
941 | /* clear hardware rx and tx fifos */ | |
942 | nvt_clear_cir_fifo(nvt); | |
943 | nvt_clear_tx_fifo(nvt); | |
944 | ||
945 | nvt_efm_enable(nvt); | |
946 | ||
947 | /* disable the CIR logical device */ | |
948 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); | |
949 | nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN); | |
950 | ||
951 | nvt_efm_disable(nvt); | |
952 | } | |
953 | ||
d8b4b582 | 954 | static int nvt_open(struct rc_dev *dev) |
6d2f5c27 | 955 | { |
d8b4b582 | 956 | struct nvt_dev *nvt = dev->priv; |
6d2f5c27 JW |
957 | unsigned long flags; |
958 | ||
959 | spin_lock_irqsave(&nvt->nvt_lock, flags); | |
960 | nvt->in_use = true; | |
961 | nvt_enable_cir(nvt); | |
962 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); | |
963 | ||
964 | return 0; | |
965 | } | |
966 | ||
d8b4b582 | 967 | static void nvt_close(struct rc_dev *dev) |
6d2f5c27 | 968 | { |
d8b4b582 | 969 | struct nvt_dev *nvt = dev->priv; |
6d2f5c27 JW |
970 | unsigned long flags; |
971 | ||
972 | spin_lock_irqsave(&nvt->nvt_lock, flags); | |
973 | nvt->in_use = false; | |
974 | nvt_disable_cir(nvt); | |
975 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); | |
976 | } | |
977 | ||
978 | /* Allocate memory, probe hardware, and initialize everything */ | |
979 | static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id) | |
980 | { | |
d8b4b582 DH |
981 | struct nvt_dev *nvt; |
982 | struct rc_dev *rdev; | |
6d2f5c27 JW |
983 | int ret = -ENOMEM; |
984 | ||
985 | nvt = kzalloc(sizeof(struct nvt_dev), GFP_KERNEL); | |
986 | if (!nvt) | |
987 | return ret; | |
988 | ||
6d2f5c27 | 989 | /* input device for IR remote (and tx) */ |
d8b4b582 | 990 | rdev = rc_allocate_device(); |
6d2f5c27 JW |
991 | if (!rdev) |
992 | goto failure; | |
993 | ||
994 | ret = -ENODEV; | |
995 | /* validate pnp resources */ | |
996 | if (!pnp_port_valid(pdev, 0) || | |
997 | pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) { | |
998 | dev_err(&pdev->dev, "IR PNP Port not valid!\n"); | |
999 | goto failure; | |
1000 | } | |
1001 | ||
1002 | if (!pnp_irq_valid(pdev, 0)) { | |
1003 | dev_err(&pdev->dev, "PNP IRQ not valid!\n"); | |
1004 | goto failure; | |
1005 | } | |
1006 | ||
1007 | if (!pnp_port_valid(pdev, 1) || | |
1008 | pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) { | |
1009 | dev_err(&pdev->dev, "Wake PNP Port not valid!\n"); | |
1010 | goto failure; | |
1011 | } | |
1012 | ||
1013 | nvt->cir_addr = pnp_port_start(pdev, 0); | |
1014 | nvt->cir_irq = pnp_irq(pdev, 0); | |
1015 | ||
1016 | nvt->cir_wake_addr = pnp_port_start(pdev, 1); | |
1017 | /* irq is always shared between cir and cir wake */ | |
1018 | nvt->cir_wake_irq = nvt->cir_irq; | |
1019 | ||
1020 | nvt->cr_efir = CR_EFIR; | |
1021 | nvt->cr_efdr = CR_EFDR; | |
1022 | ||
1023 | spin_lock_init(&nvt->nvt_lock); | |
1024 | spin_lock_init(&nvt->tx.lock); | |
4651918a | 1025 | init_ir_raw_event(&nvt->rawir); |
6d2f5c27 JW |
1026 | |
1027 | ret = -EBUSY; | |
1028 | /* now claim resources */ | |
1029 | if (!request_region(nvt->cir_addr, | |
1030 | CIR_IOREG_LENGTH, NVT_DRIVER_NAME)) | |
1031 | goto failure; | |
1032 | ||
1033 | if (request_irq(nvt->cir_irq, nvt_cir_isr, IRQF_SHARED, | |
1034 | NVT_DRIVER_NAME, (void *)nvt)) | |
1035 | goto failure; | |
1036 | ||
1037 | if (!request_region(nvt->cir_wake_addr, | |
1038 | CIR_IOREG_LENGTH, NVT_DRIVER_NAME)) | |
1039 | goto failure; | |
1040 | ||
1041 | if (request_irq(nvt->cir_wake_irq, nvt_cir_wake_isr, IRQF_SHARED, | |
1042 | NVT_DRIVER_NAME, (void *)nvt)) | |
1043 | goto failure; | |
1044 | ||
1045 | pnp_set_drvdata(pdev, nvt); | |
1046 | nvt->pdev = pdev; | |
1047 | ||
1048 | init_waitqueue_head(&nvt->tx.queue); | |
1049 | ||
1050 | ret = nvt_hw_detect(nvt); | |
1051 | if (ret) | |
1052 | goto failure; | |
1053 | ||
1054 | /* Initialize CIR & CIR Wake Logical Devices */ | |
1055 | nvt_efm_enable(nvt); | |
1056 | nvt_cir_ldev_init(nvt); | |
1057 | nvt_cir_wake_ldev_init(nvt); | |
1058 | nvt_efm_disable(nvt); | |
1059 | ||
1060 | /* Initialize CIR & CIR Wake Config Registers */ | |
1061 | nvt_cir_regs_init(nvt); | |
1062 | nvt_cir_wake_regs_init(nvt); | |
1063 | ||
d8b4b582 DH |
1064 | /* Set up the rc device */ |
1065 | rdev->priv = nvt; | |
1066 | rdev->driver_type = RC_DRIVER_IR_RAW; | |
52b66144 | 1067 | rdev->allowed_protos = RC_TYPE_ALL; |
d8b4b582 DH |
1068 | rdev->open = nvt_open; |
1069 | rdev->close = nvt_close; | |
1070 | rdev->tx_ir = nvt_tx_ir; | |
1071 | rdev->s_tx_carrier = nvt_set_tx_carrier; | |
1072 | rdev->input_name = "Nuvoton w836x7hg Infrared Remote Transceiver"; | |
1073 | rdev->input_id.bustype = BUS_HOST; | |
1074 | rdev->input_id.vendor = PCI_VENDOR_ID_WINBOND2; | |
1075 | rdev->input_id.product = nvt->chip_major; | |
1076 | rdev->input_id.version = nvt->chip_minor; | |
1077 | rdev->driver_name = NVT_DRIVER_NAME; | |
1078 | rdev->map_name = RC_MAP_RC6_MCE; | |
6d2f5c27 | 1079 | #if 0 |
d8b4b582 DH |
1080 | rdev->min_timeout = XYZ; |
1081 | rdev->max_timeout = XYZ; | |
1082 | rdev->timeout = XYZ; | |
6d2f5c27 | 1083 | /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */ |
d8b4b582 | 1084 | rdev->rx_resolution = XYZ; |
6d2f5c27 | 1085 | /* tx bits */ |
d8b4b582 | 1086 | rdev->tx_resolution = XYZ; |
6d2f5c27 | 1087 | #endif |
6d2f5c27 | 1088 | |
d8b4b582 | 1089 | ret = rc_register_device(rdev); |
6d2f5c27 JW |
1090 | if (ret) |
1091 | goto failure; | |
1092 | ||
d8b4b582 DH |
1093 | device_set_wakeup_capable(&pdev->dev, 1); |
1094 | device_set_wakeup_enable(&pdev->dev, 1); | |
1095 | nvt->rdev = rdev; | |
6d2f5c27 JW |
1096 | nvt_pr(KERN_NOTICE, "driver has been successfully loaded\n"); |
1097 | if (debug) { | |
1098 | cir_dump_regs(nvt); | |
1099 | cir_wake_dump_regs(nvt); | |
1100 | } | |
1101 | ||
1102 | return 0; | |
1103 | ||
1104 | failure: | |
1105 | if (nvt->cir_irq) | |
1106 | free_irq(nvt->cir_irq, nvt); | |
1107 | if (nvt->cir_addr) | |
1108 | release_region(nvt->cir_addr, CIR_IOREG_LENGTH); | |
1109 | ||
1110 | if (nvt->cir_wake_irq) | |
1111 | free_irq(nvt->cir_wake_irq, nvt); | |
1112 | if (nvt->cir_wake_addr) | |
1113 | release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH); | |
1114 | ||
d8b4b582 | 1115 | rc_free_device(rdev); |
6d2f5c27 JW |
1116 | kfree(nvt); |
1117 | ||
1118 | return ret; | |
1119 | } | |
1120 | ||
1121 | static void __devexit nvt_remove(struct pnp_dev *pdev) | |
1122 | { | |
1123 | struct nvt_dev *nvt = pnp_get_drvdata(pdev); | |
1124 | unsigned long flags; | |
1125 | ||
1126 | spin_lock_irqsave(&nvt->nvt_lock, flags); | |
1127 | /* disable CIR */ | |
1128 | nvt_cir_reg_write(nvt, 0, CIR_IREN); | |
1129 | nvt_disable_cir(nvt); | |
1130 | /* enable CIR Wake (for IR power-on) */ | |
1131 | nvt_enable_wake(nvt); | |
1132 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); | |
1133 | ||
1134 | /* free resources */ | |
1135 | free_irq(nvt->cir_irq, nvt); | |
1136 | free_irq(nvt->cir_wake_irq, nvt); | |
1137 | release_region(nvt->cir_addr, CIR_IOREG_LENGTH); | |
1138 | release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH); | |
1139 | ||
d8b4b582 | 1140 | rc_unregister_device(nvt->rdev); |
6d2f5c27 | 1141 | |
6d2f5c27 JW |
1142 | kfree(nvt); |
1143 | } | |
1144 | ||
1145 | static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state) | |
1146 | { | |
1147 | struct nvt_dev *nvt = pnp_get_drvdata(pdev); | |
1148 | unsigned long flags; | |
1149 | ||
1150 | nvt_dbg("%s called", __func__); | |
1151 | ||
1152 | /* zero out misc state tracking */ | |
1153 | spin_lock_irqsave(&nvt->nvt_lock, flags); | |
1154 | nvt->study_state = ST_STUDY_NONE; | |
1155 | nvt->wake_state = ST_WAKE_NONE; | |
1156 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); | |
1157 | ||
1158 | spin_lock_irqsave(&nvt->tx.lock, flags); | |
1159 | nvt->tx.tx_state = ST_TX_NONE; | |
1160 | spin_unlock_irqrestore(&nvt->tx.lock, flags); | |
1161 | ||
1162 | /* disable all CIR interrupts */ | |
1163 | nvt_cir_reg_write(nvt, 0, CIR_IREN); | |
1164 | ||
1165 | nvt_efm_enable(nvt); | |
1166 | ||
1167 | /* disable cir logical dev */ | |
1168 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); | |
1169 | nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN); | |
1170 | ||
1171 | nvt_efm_disable(nvt); | |
1172 | ||
1173 | /* make sure wake is enabled */ | |
1174 | nvt_enable_wake(nvt); | |
1175 | ||
1176 | return 0; | |
1177 | } | |
1178 | ||
1179 | static int nvt_resume(struct pnp_dev *pdev) | |
1180 | { | |
1181 | int ret = 0; | |
1182 | struct nvt_dev *nvt = pnp_get_drvdata(pdev); | |
1183 | ||
1184 | nvt_dbg("%s called", __func__); | |
1185 | ||
1186 | /* open interrupt */ | |
fbdc781c | 1187 | nvt_set_cir_iren(nvt); |
6d2f5c27 JW |
1188 | |
1189 | /* Enable CIR logical device */ | |
1190 | nvt_efm_enable(nvt); | |
1191 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); | |
1192 | nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); | |
1193 | ||
1194 | nvt_efm_disable(nvt); | |
1195 | ||
1196 | nvt_cir_regs_init(nvt); | |
1197 | nvt_cir_wake_regs_init(nvt); | |
1198 | ||
1199 | return ret; | |
1200 | } | |
1201 | ||
1202 | static void nvt_shutdown(struct pnp_dev *pdev) | |
1203 | { | |
1204 | struct nvt_dev *nvt = pnp_get_drvdata(pdev); | |
1205 | nvt_enable_wake(nvt); | |
1206 | } | |
1207 | ||
1208 | static const struct pnp_device_id nvt_ids[] = { | |
1209 | { "WEC0530", 0 }, /* CIR */ | |
1210 | { "NTN0530", 0 }, /* CIR for new chip's pnp id*/ | |
1211 | { "", 0 }, | |
1212 | }; | |
1213 | ||
1214 | static struct pnp_driver nvt_driver = { | |
1215 | .name = NVT_DRIVER_NAME, | |
1216 | .id_table = nvt_ids, | |
1217 | .flags = PNP_DRIVER_RES_DO_NOT_CHANGE, | |
1218 | .probe = nvt_probe, | |
1219 | .remove = __devexit_p(nvt_remove), | |
1220 | .suspend = nvt_suspend, | |
1221 | .resume = nvt_resume, | |
1222 | .shutdown = nvt_shutdown, | |
1223 | }; | |
1224 | ||
1225 | int nvt_init(void) | |
1226 | { | |
1227 | return pnp_register_driver(&nvt_driver); | |
1228 | } | |
1229 | ||
1230 | void nvt_exit(void) | |
1231 | { | |
1232 | pnp_unregister_driver(&nvt_driver); | |
1233 | } | |
1234 | ||
1235 | module_param(debug, int, S_IRUGO | S_IWUSR); | |
1236 | MODULE_PARM_DESC(debug, "Enable debugging output"); | |
1237 | ||
1238 | MODULE_DEVICE_TABLE(pnp, nvt_ids); | |
1239 | MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver"); | |
1240 | ||
1241 | MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>"); | |
1242 | MODULE_LICENSE("GPL"); | |
1243 | ||
1244 | module_init(nvt_init); | |
1245 | module_exit(nvt_exit); |