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6d2f5c27 JW |
1 | /* |
2 | * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR | |
3 | * | |
4 | * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com> | |
5 | * Copyright (C) 2009 Nuvoton PS Team | |
6 | * | |
7 | * Special thanks to Nuvoton for providing hardware, spec sheets and | |
8 | * sample code upon which portions of this driver are based. Indirect | |
9 | * thanks also to Maxim Levitsky, whose ene_ir driver this driver is | |
10 | * modeled after. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of the | |
15 | * License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, but | |
18 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
20 | * General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 | |
25 | * USA | |
26 | */ | |
27 | ||
563cd5ce JP |
28 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
29 | ||
6d2f5c27 JW |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/pnp.h> | |
33 | #include <linux/io.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/sched.h> | |
36 | #include <linux/slab.h> | |
6bda9644 | 37 | #include <media/rc-core.h> |
6d2f5c27 JW |
38 | #include <linux/pci_ids.h> |
39 | ||
40 | #include "nuvoton-cir.h" | |
41 | ||
b5cf725c HK |
42 | static const struct nvt_chip nvt_chips[] = { |
43 | { "w83667hg", NVT_W83667HG }, | |
44 | { "NCT6775F", NVT_6775F }, | |
45 | { "NCT6776F", NVT_6776F }, | |
d0b528d5 | 46 | { "NCT6779D", NVT_6779D }, |
b5cf725c HK |
47 | }; |
48 | ||
49 | static inline bool is_w83667hg(struct nvt_dev *nvt) | |
50 | { | |
51 | return nvt->chip_ver == NVT_W83667HG; | |
52 | } | |
53 | ||
6d2f5c27 JW |
54 | /* write val to config reg */ |
55 | static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg) | |
56 | { | |
57 | outb(reg, nvt->cr_efir); | |
58 | outb(val, nvt->cr_efdr); | |
59 | } | |
60 | ||
61 | /* read val from config reg */ | |
62 | static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg) | |
63 | { | |
64 | outb(reg, nvt->cr_efir); | |
65 | return inb(nvt->cr_efdr); | |
66 | } | |
67 | ||
68 | /* update config register bit without changing other bits */ | |
69 | static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg) | |
70 | { | |
71 | u8 tmp = nvt_cr_read(nvt, reg) | val; | |
72 | nvt_cr_write(nvt, tmp, reg); | |
73 | } | |
74 | ||
75 | /* clear config register bit without changing other bits */ | |
76 | static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg) | |
77 | { | |
78 | u8 tmp = nvt_cr_read(nvt, reg) & ~val; | |
79 | nvt_cr_write(nvt, tmp, reg); | |
80 | } | |
81 | ||
82 | /* enter extended function mode */ | |
83 | static inline void nvt_efm_enable(struct nvt_dev *nvt) | |
84 | { | |
85 | /* Enabling Extended Function Mode explicitly requires writing 2x */ | |
86 | outb(EFER_EFM_ENABLE, nvt->cr_efir); | |
87 | outb(EFER_EFM_ENABLE, nvt->cr_efir); | |
88 | } | |
89 | ||
90 | /* exit extended function mode */ | |
91 | static inline void nvt_efm_disable(struct nvt_dev *nvt) | |
92 | { | |
93 | outb(EFER_EFM_DISABLE, nvt->cr_efir); | |
94 | } | |
95 | ||
96 | /* | |
97 | * When you want to address a specific logical device, write its logical | |
98 | * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing | |
99 | * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN. | |
100 | */ | |
101 | static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev) | |
102 | { | |
103 | outb(CR_LOGICAL_DEV_SEL, nvt->cr_efir); | |
104 | outb(ldev, nvt->cr_efdr); | |
105 | } | |
106 | ||
107 | /* write val to cir config register */ | |
108 | static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset) | |
109 | { | |
110 | outb(val, nvt->cir_addr + offset); | |
111 | } | |
112 | ||
113 | /* read val from cir config register */ | |
114 | static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset) | |
115 | { | |
116 | u8 val; | |
117 | ||
118 | val = inb(nvt->cir_addr + offset); | |
119 | ||
120 | return val; | |
121 | } | |
122 | ||
123 | /* write val to cir wake register */ | |
124 | static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt, | |
125 | u8 val, u8 offset) | |
126 | { | |
127 | outb(val, nvt->cir_wake_addr + offset); | |
128 | } | |
129 | ||
130 | /* read val from cir wake config register */ | |
131 | static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset) | |
132 | { | |
133 | u8 val; | |
134 | ||
135 | val = inb(nvt->cir_wake_addr + offset); | |
136 | ||
137 | return val; | |
138 | } | |
139 | ||
140 | /* dump current cir register contents */ | |
141 | static void cir_dump_regs(struct nvt_dev *nvt) | |
142 | { | |
143 | nvt_efm_enable(nvt); | |
144 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); | |
145 | ||
563cd5ce JP |
146 | pr_info("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME); |
147 | pr_info(" * CR CIR ACTIVE : 0x%x\n", | |
148 | nvt_cr_read(nvt, CR_LOGICAL_DEV_EN)); | |
149 | pr_info(" * CR CIR BASE ADDR: 0x%x\n", | |
150 | (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) | | |
6d2f5c27 | 151 | nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO)); |
563cd5ce JP |
152 | pr_info(" * CR CIR IRQ NUM: 0x%x\n", |
153 | nvt_cr_read(nvt, CR_CIR_IRQ_RSRC)); | |
6d2f5c27 JW |
154 | |
155 | nvt_efm_disable(nvt); | |
156 | ||
563cd5ce JP |
157 | pr_info("%s: Dump CIR registers:\n", NVT_DRIVER_NAME); |
158 | pr_info(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON)); | |
159 | pr_info(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS)); | |
160 | pr_info(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN)); | |
161 | pr_info(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT)); | |
162 | pr_info(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP)); | |
163 | pr_info(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC)); | |
164 | pr_info(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH)); | |
165 | pr_info(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL)); | |
166 | pr_info(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON)); | |
167 | pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS)); | |
168 | pr_info(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO)); | |
169 | pr_info(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT)); | |
170 | pr_info(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO)); | |
171 | pr_info(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH)); | |
172 | pr_info(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL)); | |
173 | pr_info(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM)); | |
6d2f5c27 JW |
174 | } |
175 | ||
176 | /* dump current cir wake register contents */ | |
177 | static void cir_wake_dump_regs(struct nvt_dev *nvt) | |
178 | { | |
179 | u8 i, fifo_len; | |
180 | ||
181 | nvt_efm_enable(nvt); | |
182 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); | |
183 | ||
563cd5ce JP |
184 | pr_info("%s: Dump CIR WAKE logical device registers:\n", |
185 | NVT_DRIVER_NAME); | |
186 | pr_info(" * CR CIR WAKE ACTIVE : 0x%x\n", | |
187 | nvt_cr_read(nvt, CR_LOGICAL_DEV_EN)); | |
188 | pr_info(" * CR CIR WAKE BASE ADDR: 0x%x\n", | |
189 | (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) | | |
4e6e29ad | 190 | nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO)); |
563cd5ce JP |
191 | pr_info(" * CR CIR WAKE IRQ NUM: 0x%x\n", |
192 | nvt_cr_read(nvt, CR_CIR_IRQ_RSRC)); | |
6d2f5c27 JW |
193 | |
194 | nvt_efm_disable(nvt); | |
195 | ||
563cd5ce JP |
196 | pr_info("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME); |
197 | pr_info(" * IRCON: 0x%x\n", | |
198 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON)); | |
199 | pr_info(" * IRSTS: 0x%x\n", | |
200 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS)); | |
201 | pr_info(" * IREN: 0x%x\n", | |
202 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN)); | |
203 | pr_info(" * FIFO CMP DEEP: 0x%x\n", | |
204 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP)); | |
205 | pr_info(" * FIFO CMP TOL: 0x%x\n", | |
206 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL)); | |
207 | pr_info(" * FIFO COUNT: 0x%x\n", | |
208 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT)); | |
209 | pr_info(" * SLCH: 0x%x\n", | |
210 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH)); | |
211 | pr_info(" * SLCL: 0x%x\n", | |
212 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL)); | |
213 | pr_info(" * FIFOCON: 0x%x\n", | |
214 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON)); | |
215 | pr_info(" * SRXFSTS: 0x%x\n", | |
216 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS)); | |
217 | pr_info(" * SAMPLE RX FIFO: 0x%x\n", | |
218 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO)); | |
219 | pr_info(" * WR FIFO DATA: 0x%x\n", | |
220 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA)); | |
221 | pr_info(" * RD FIFO ONLY: 0x%x\n", | |
222 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY)); | |
223 | pr_info(" * RD FIFO ONLY IDX: 0x%x\n", | |
224 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)); | |
225 | pr_info(" * FIFO IGNORE: 0x%x\n", | |
226 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE)); | |
227 | pr_info(" * IRFSM: 0x%x\n", | |
228 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM)); | |
6d2f5c27 JW |
229 | |
230 | fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT); | |
563cd5ce JP |
231 | pr_info("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len); |
232 | pr_info("* Contents ="); | |
6d2f5c27 | 233 | for (i = 0; i < fifo_len; i++) |
563cd5ce JP |
234 | pr_cont(" %02x", |
235 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY)); | |
236 | pr_cont("\n"); | |
6d2f5c27 JW |
237 | } |
238 | ||
b5cf725c HK |
239 | static inline const char *nvt_find_chip(struct nvt_dev *nvt, int id) |
240 | { | |
241 | int i; | |
242 | ||
243 | for (i = 0; i < ARRAY_SIZE(nvt_chips); i++) | |
244 | if ((id & SIO_ID_MASK) == nvt_chips[i].chip_ver) { | |
245 | nvt->chip_ver = nvt_chips[i].chip_ver; | |
246 | return nvt_chips[i].name; | |
247 | } | |
248 | ||
249 | return NULL; | |
250 | } | |
251 | ||
252 | ||
6d2f5c27 | 253 | /* detect hardware features */ |
6a5a3360 | 254 | static void nvt_hw_detect(struct nvt_dev *nvt) |
6d2f5c27 | 255 | { |
b5cf725c HK |
256 | const char *chip_name; |
257 | int chip_id; | |
6d2f5c27 JW |
258 | |
259 | nvt_efm_enable(nvt); | |
260 | ||
261 | /* Check if we're wired for the alternate EFER setup */ | |
b5cf725c HK |
262 | nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI); |
263 | if (nvt->chip_major == 0xff) { | |
6d2f5c27 JW |
264 | nvt->cr_efir = CR_EFIR2; |
265 | nvt->cr_efdr = CR_EFDR2; | |
266 | nvt_efm_enable(nvt); | |
b5cf725c | 267 | nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI); |
6d2f5c27 JW |
268 | } |
269 | ||
b5cf725c HK |
270 | nvt->chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO); |
271 | ||
272 | chip_id = nvt->chip_major << 8 | nvt->chip_minor; | |
273 | chip_name = nvt_find_chip(nvt, chip_id); | |
6d2f5c27 | 274 | |
362d3a3a | 275 | /* warn, but still let the driver load, if we don't know this chip */ |
b5cf725c | 276 | if (!chip_name) |
211477fe HK |
277 | dev_warn(&nvt->pdev->dev, |
278 | "unknown chip, id: 0x%02x 0x%02x, it may not work...", | |
279 | nvt->chip_major, nvt->chip_minor); | |
362d3a3a | 280 | else |
af082334 HK |
281 | dev_info(&nvt->pdev->dev, |
282 | "found %s or compatible: chip id: 0x%02x 0x%02x", | |
283 | chip_name, nvt->chip_major, nvt->chip_minor); | |
362d3a3a | 284 | |
6d2f5c27 | 285 | nvt_efm_disable(nvt); |
6d2f5c27 JW |
286 | } |
287 | ||
288 | static void nvt_cir_ldev_init(struct nvt_dev *nvt) | |
289 | { | |
39381d4f JW |
290 | u8 val, psreg, psmask, psval; |
291 | ||
b5cf725c | 292 | if (is_w83667hg(nvt)) { |
39381d4f JW |
293 | psreg = CR_MULTIFUNC_PIN_SEL; |
294 | psmask = MULTIFUNC_PIN_SEL_MASK; | |
295 | psval = MULTIFUNC_ENABLE_CIR | MULTIFUNC_ENABLE_CIRWB; | |
296 | } else { | |
297 | psreg = CR_OUTPUT_PIN_SEL; | |
298 | psmask = OUTPUT_PIN_SEL_MASK; | |
299 | psval = OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB; | |
300 | } | |
6d2f5c27 | 301 | |
39381d4f JW |
302 | /* output pin selection: enable CIR, with WB sensor enabled */ |
303 | val = nvt_cr_read(nvt, psreg); | |
304 | val &= psmask; | |
305 | val |= psval; | |
306 | nvt_cr_write(nvt, val, psreg); | |
6d2f5c27 JW |
307 | |
308 | /* Select CIR logical device and enable */ | |
309 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); | |
310 | nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); | |
311 | ||
312 | nvt_cr_write(nvt, nvt->cir_addr >> 8, CR_CIR_BASE_ADDR_HI); | |
313 | nvt_cr_write(nvt, nvt->cir_addr & 0xff, CR_CIR_BASE_ADDR_LO); | |
314 | ||
315 | nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC); | |
316 | ||
317 | nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d", | |
318 | nvt->cir_addr, nvt->cir_irq); | |
319 | } | |
320 | ||
321 | static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt) | |
322 | { | |
323 | /* Select ACPI logical device, enable it and CIR Wake */ | |
324 | nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI); | |
325 | nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); | |
326 | ||
327 | /* Enable CIR Wake via PSOUT# (Pin60) */ | |
328 | nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE); | |
329 | ||
6d2f5c27 JW |
330 | /* enable pme interrupt of cir wakeup event */ |
331 | nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2); | |
332 | ||
333 | /* Select CIR Wake logical device and enable */ | |
334 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); | |
335 | nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); | |
336 | ||
337 | nvt_cr_write(nvt, nvt->cir_wake_addr >> 8, CR_CIR_BASE_ADDR_HI); | |
338 | nvt_cr_write(nvt, nvt->cir_wake_addr & 0xff, CR_CIR_BASE_ADDR_LO); | |
339 | ||
340 | nvt_cr_write(nvt, nvt->cir_wake_irq, CR_CIR_IRQ_RSRC); | |
341 | ||
342 | nvt_dbg("CIR Wake initialized, base io port address: 0x%lx, irq: %d", | |
343 | nvt->cir_wake_addr, nvt->cir_wake_irq); | |
344 | } | |
345 | ||
346 | /* clear out the hardware's cir rx fifo */ | |
347 | static void nvt_clear_cir_fifo(struct nvt_dev *nvt) | |
348 | { | |
349 | u8 val; | |
350 | ||
351 | val = nvt_cir_reg_read(nvt, CIR_FIFOCON); | |
352 | nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON); | |
353 | } | |
354 | ||
355 | /* clear out the hardware's cir wake rx fifo */ | |
356 | static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt) | |
357 | { | |
358 | u8 val; | |
359 | ||
360 | val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON); | |
361 | nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR, | |
362 | CIR_WAKE_FIFOCON); | |
363 | } | |
364 | ||
365 | /* clear out the hardware's cir tx fifo */ | |
366 | static void nvt_clear_tx_fifo(struct nvt_dev *nvt) | |
367 | { | |
368 | u8 val; | |
369 | ||
370 | val = nvt_cir_reg_read(nvt, CIR_FIFOCON); | |
371 | nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON); | |
372 | } | |
373 | ||
fbdc781c JW |
374 | /* enable RX Trigger Level Reach and Packet End interrupts */ |
375 | static void nvt_set_cir_iren(struct nvt_dev *nvt) | |
376 | { | |
377 | u8 iren; | |
378 | ||
379 | iren = CIR_IREN_RTR | CIR_IREN_PE; | |
380 | nvt_cir_reg_write(nvt, iren, CIR_IREN); | |
381 | } | |
382 | ||
6d2f5c27 JW |
383 | static void nvt_cir_regs_init(struct nvt_dev *nvt) |
384 | { | |
385 | /* set sample limit count (PE interrupt raised when reached) */ | |
386 | nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH); | |
387 | nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL); | |
388 | ||
389 | /* set fifo irq trigger levels */ | |
390 | nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV | | |
391 | CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON); | |
392 | ||
393 | /* | |
394 | * Enable TX and RX, specify carrier on = low, off = high, and set | |
395 | * sample period (currently 50us) | |
396 | */ | |
4e6e29ad JW |
397 | nvt_cir_reg_write(nvt, |
398 | CIR_IRCON_TXEN | CIR_IRCON_RXEN | | |
399 | CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL, | |
400 | CIR_IRCON); | |
6d2f5c27 JW |
401 | |
402 | /* clear hardware rx and tx fifos */ | |
403 | nvt_clear_cir_fifo(nvt); | |
404 | nvt_clear_tx_fifo(nvt); | |
405 | ||
406 | /* clear any and all stray interrupts */ | |
407 | nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS); | |
408 | ||
fbdc781c JW |
409 | /* and finally, enable interrupts */ |
410 | nvt_set_cir_iren(nvt); | |
6d2f5c27 JW |
411 | } |
412 | ||
413 | static void nvt_cir_wake_regs_init(struct nvt_dev *nvt) | |
414 | { | |
3198ed16 JW |
415 | /* set number of bytes needed for wake from s3 (default 65) */ |
416 | nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFO_CMP_BYTES, | |
417 | CIR_WAKE_FIFO_CMP_DEEP); | |
6d2f5c27 JW |
418 | |
419 | /* set tolerance/variance allowed per byte during wake compare */ | |
420 | nvt_cir_wake_reg_write(nvt, CIR_WAKE_CMP_TOLERANCE, | |
421 | CIR_WAKE_FIFO_CMP_TOL); | |
422 | ||
423 | /* set sample limit count (PE interrupt raised when reached) */ | |
424 | nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_WAKE_SLCH); | |
425 | nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_WAKE_SLCL); | |
426 | ||
427 | /* set cir wake fifo rx trigger level (currently 67) */ | |
428 | nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFOCON_RX_TRIGGER_LEV, | |
429 | CIR_WAKE_FIFOCON); | |
430 | ||
431 | /* | |
432 | * Enable TX and RX, specific carrier on = low, off = high, and set | |
433 | * sample period (currently 50us) | |
434 | */ | |
435 | nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN | | |
436 | CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV | | |
437 | CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL, | |
438 | CIR_WAKE_IRCON); | |
439 | ||
440 | /* clear cir wake rx fifo */ | |
441 | nvt_clear_cir_wake_fifo(nvt); | |
442 | ||
443 | /* clear any and all stray interrupts */ | |
444 | nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS); | |
445 | } | |
446 | ||
447 | static void nvt_enable_wake(struct nvt_dev *nvt) | |
448 | { | |
449 | nvt_efm_enable(nvt); | |
450 | ||
451 | nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI); | |
452 | nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE); | |
6d2f5c27 JW |
453 | nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2); |
454 | ||
455 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); | |
456 | nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); | |
457 | ||
458 | nvt_efm_disable(nvt); | |
459 | ||
460 | nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN | | |
461 | CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV | | |
4e6e29ad JW |
462 | CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL, |
463 | CIR_WAKE_IRCON); | |
6d2f5c27 JW |
464 | nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS); |
465 | nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN); | |
466 | } | |
467 | ||
230dc94a | 468 | #if 0 /* Currently unused */ |
6d2f5c27 JW |
469 | /* rx carrier detect only works in learning mode, must be called w/nvt_lock */ |
470 | static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt) | |
471 | { | |
472 | u32 count, carrier, duration = 0; | |
473 | int i; | |
474 | ||
475 | count = nvt_cir_reg_read(nvt, CIR_FCCL) | | |
476 | nvt_cir_reg_read(nvt, CIR_FCCH) << 8; | |
477 | ||
478 | for (i = 0; i < nvt->pkts; i++) { | |
479 | if (nvt->buf[i] & BUF_PULSE_BIT) | |
480 | duration += nvt->buf[i] & BUF_LEN_MASK; | |
481 | } | |
482 | ||
483 | duration *= SAMPLE_PERIOD; | |
484 | ||
485 | if (!count || !duration) { | |
211477fe HK |
486 | dev_notice(&nvt->pdev->dev, |
487 | "Unable to determine carrier! (c:%u, d:%u)", | |
488 | count, duration); | |
6d2f5c27 JW |
489 | return 0; |
490 | } | |
491 | ||
b4608fae | 492 | carrier = MS_TO_NS(count) / duration; |
6d2f5c27 JW |
493 | |
494 | if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER)) | |
495 | nvt_dbg("WTF? Carrier frequency out of range!"); | |
496 | ||
497 | nvt_dbg("Carrier frequency: %u (count %u, duration %u)", | |
498 | carrier, count, duration); | |
499 | ||
500 | return carrier; | |
501 | } | |
230dc94a | 502 | #endif |
6d2f5c27 JW |
503 | /* |
504 | * set carrier frequency | |
505 | * | |
506 | * set carrier on 2 registers: CP & CC | |
507 | * always set CP as 0x81 | |
508 | * set CC by SPEC, CC = 3MHz/carrier - 1 | |
509 | */ | |
d8b4b582 | 510 | static int nvt_set_tx_carrier(struct rc_dev *dev, u32 carrier) |
6d2f5c27 | 511 | { |
d8b4b582 | 512 | struct nvt_dev *nvt = dev->priv; |
6d2f5c27 JW |
513 | u16 val; |
514 | ||
48cafec9 DC |
515 | if (carrier == 0) |
516 | return -EINVAL; | |
517 | ||
6d2f5c27 JW |
518 | nvt_cir_reg_write(nvt, 1, CIR_CP); |
519 | val = 3000000 / (carrier) - 1; | |
520 | nvt_cir_reg_write(nvt, val & 0xff, CIR_CC); | |
521 | ||
522 | nvt_dbg("cp: 0x%x cc: 0x%x\n", | |
523 | nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC)); | |
524 | ||
525 | return 0; | |
526 | } | |
527 | ||
528 | /* | |
529 | * nvt_tx_ir | |
530 | * | |
531 | * 1) clean TX fifo first (handled by AP) | |
532 | * 2) copy data from user space | |
533 | * 3) disable RX interrupts, enable TX interrupts: TTR & TFU | |
534 | * 4) send 9 packets to TX FIFO to open TTR | |
535 | * in interrupt_handler: | |
536 | * 5) send all data out | |
537 | * go back to write(): | |
538 | * 6) disable TX interrupts, re-enable RX interupts | |
539 | * | |
540 | * The key problem of this function is user space data may larger than | |
541 | * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to | |
542 | * buf, and keep current copied data buf num in cur_buf_num. But driver's buf | |
543 | * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to | |
544 | * set TXFCONT as 0xff, until buf_count less than 0xff. | |
545 | */ | |
5588dc2b | 546 | static int nvt_tx_ir(struct rc_dev *dev, unsigned *txbuf, unsigned n) |
6d2f5c27 | 547 | { |
d8b4b582 | 548 | struct nvt_dev *nvt = dev->priv; |
6d2f5c27 | 549 | unsigned long flags; |
6d2f5c27 JW |
550 | unsigned int i; |
551 | u8 iren; | |
552 | int ret; | |
553 | ||
554 | spin_lock_irqsave(&nvt->tx.lock, flags); | |
555 | ||
5588dc2b DH |
556 | ret = min((unsigned)(TX_BUF_LEN / sizeof(unsigned)), n); |
557 | nvt->tx.buf_count = (ret * sizeof(unsigned)); | |
6d2f5c27 JW |
558 | |
559 | memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count); | |
560 | ||
561 | nvt->tx.cur_buf_num = 0; | |
562 | ||
563 | /* save currently enabled interrupts */ | |
564 | iren = nvt_cir_reg_read(nvt, CIR_IREN); | |
565 | ||
566 | /* now disable all interrupts, save TFU & TTR */ | |
567 | nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN); | |
568 | ||
569 | nvt->tx.tx_state = ST_TX_REPLY; | |
570 | ||
571 | nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 | | |
572 | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON); | |
573 | ||
574 | /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */ | |
575 | for (i = 0; i < 9; i++) | |
576 | nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO); | |
577 | ||
578 | spin_unlock_irqrestore(&nvt->tx.lock, flags); | |
579 | ||
580 | wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST); | |
581 | ||
582 | spin_lock_irqsave(&nvt->tx.lock, flags); | |
583 | nvt->tx.tx_state = ST_TX_NONE; | |
584 | spin_unlock_irqrestore(&nvt->tx.lock, flags); | |
585 | ||
586 | /* restore enabled interrupts to prior state */ | |
587 | nvt_cir_reg_write(nvt, iren, CIR_IREN); | |
588 | ||
589 | return ret; | |
590 | } | |
591 | ||
592 | /* dump contents of the last rx buffer we got from the hw rx fifo */ | |
593 | static void nvt_dump_rx_buf(struct nvt_dev *nvt) | |
594 | { | |
595 | int i; | |
596 | ||
4e6e29ad | 597 | printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts); |
6d2f5c27 | 598 | for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++) |
4e6e29ad JW |
599 | printk(KERN_CONT "0x%02x ", nvt->buf[i]); |
600 | printk(KERN_CONT "\n"); | |
6d2f5c27 JW |
601 | } |
602 | ||
603 | /* | |
604 | * Process raw data in rx driver buffer, store it in raw IR event kfifo, | |
605 | * trigger decode when appropriate. | |
606 | * | |
607 | * We get IR data samples one byte at a time. If the msb is set, its a pulse, | |
608 | * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD | |
609 | * (default 50us) intervals for that pulse/space. A discrete signal is | |
610 | * followed by a series of 0x7f packets, then either 0x7<something> or 0x80 | |
611 | * to signal more IR coming (repeats) or end of IR, respectively. We store | |
612 | * sample data in the raw event kfifo until we see 0x7<something> (except f) | |
613 | * or 0x80, at which time, we trigger a decode operation. | |
614 | */ | |
615 | static void nvt_process_rx_ir_data(struct nvt_dev *nvt) | |
616 | { | |
4651918a | 617 | DEFINE_IR_RAW_EVENT(rawir); |
6d2f5c27 JW |
618 | u8 sample; |
619 | int i; | |
620 | ||
621 | nvt_dbg_verbose("%s firing", __func__); | |
622 | ||
623 | if (debug) | |
624 | nvt_dump_rx_buf(nvt); | |
625 | ||
de4ed0c1 | 626 | nvt_dbg_verbose("Processing buffer of len %d", nvt->pkts); |
6d2f5c27 | 627 | |
b7582815 JW |
628 | init_ir_raw_event(&rawir); |
629 | ||
de4ed0c1 | 630 | for (i = 0; i < nvt->pkts; i++) { |
6d2f5c27 JW |
631 | sample = nvt->buf[i]; |
632 | ||
633 | rawir.pulse = ((sample & BUF_PULSE_BIT) != 0); | |
b4608fae JW |
634 | rawir.duration = US_TO_NS((sample & BUF_LEN_MASK) |
635 | * SAMPLE_PERIOD); | |
6d2f5c27 | 636 | |
de4ed0c1 JW |
637 | nvt_dbg("Storing %s with duration %d", |
638 | rawir.pulse ? "pulse" : "space", rawir.duration); | |
4651918a | 639 | |
de4ed0c1 | 640 | ir_raw_event_store_with_filter(nvt->rdev, &rawir); |
6d2f5c27 JW |
641 | |
642 | /* | |
643 | * BUF_PULSE_BIT indicates end of IR data, BUF_REPEAT_BYTE | |
644 | * indicates end of IR signal, but new data incoming. In both | |
645 | * cases, it means we're ready to call ir_raw_event_handle | |
646 | */ | |
de4ed0c1 | 647 | if ((sample == BUF_PULSE_BIT) && (i + 1 < nvt->pkts)) { |
b7582815 | 648 | nvt_dbg("Calling ir_raw_event_handle (signal end)\n"); |
6d2f5c27 | 649 | ir_raw_event_handle(nvt->rdev); |
b7582815 | 650 | } |
6d2f5c27 JW |
651 | } |
652 | ||
de4ed0c1 JW |
653 | nvt->pkts = 0; |
654 | ||
b7582815 JW |
655 | nvt_dbg("Calling ir_raw_event_handle (buffer empty)\n"); |
656 | ir_raw_event_handle(nvt->rdev); | |
657 | ||
6d2f5c27 JW |
658 | nvt_dbg_verbose("%s done", __func__); |
659 | } | |
660 | ||
fbdc781c JW |
661 | static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt) |
662 | { | |
211477fe | 663 | dev_warn(&nvt->pdev->dev, "RX FIFO overrun detected, flushing data!"); |
fbdc781c JW |
664 | |
665 | nvt->pkts = 0; | |
666 | nvt_clear_cir_fifo(nvt); | |
667 | ir_raw_event_reset(nvt->rdev); | |
668 | } | |
669 | ||
6d2f5c27 JW |
670 | /* copy data from hardware rx fifo into driver buffer */ |
671 | static void nvt_get_rx_ir_data(struct nvt_dev *nvt) | |
672 | { | |
673 | unsigned long flags; | |
674 | u8 fifocount, val; | |
675 | unsigned int b_idx; | |
fbdc781c | 676 | bool overrun = false; |
6d2f5c27 JW |
677 | int i; |
678 | ||
679 | /* Get count of how many bytes to read from RX FIFO */ | |
680 | fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT); | |
681 | /* if we get 0xff, probably means the logical dev is disabled */ | |
682 | if (fifocount == 0xff) | |
683 | return; | |
fbdc781c | 684 | /* watch out for a fifo overrun condition */ |
6d2f5c27 | 685 | else if (fifocount > RX_BUF_LEN) { |
fbdc781c JW |
686 | overrun = true; |
687 | fifocount = RX_BUF_LEN; | |
6d2f5c27 JW |
688 | } |
689 | ||
690 | nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount); | |
691 | ||
692 | spin_lock_irqsave(&nvt->nvt_lock, flags); | |
693 | ||
694 | b_idx = nvt->pkts; | |
695 | ||
696 | /* This should never happen, but lets check anyway... */ | |
697 | if (b_idx + fifocount > RX_BUF_LEN) { | |
698 | nvt_process_rx_ir_data(nvt); | |
699 | b_idx = 0; | |
700 | } | |
701 | ||
702 | /* Read fifocount bytes from CIR Sample RX FIFO register */ | |
703 | for (i = 0; i < fifocount; i++) { | |
704 | val = nvt_cir_reg_read(nvt, CIR_SRXFIFO); | |
705 | nvt->buf[b_idx + i] = val; | |
706 | } | |
707 | ||
708 | nvt->pkts += fifocount; | |
709 | nvt_dbg("%s: pkts now %d", __func__, nvt->pkts); | |
710 | ||
711 | nvt_process_rx_ir_data(nvt); | |
712 | ||
fbdc781c JW |
713 | if (overrun) |
714 | nvt_handle_rx_fifo_overrun(nvt); | |
715 | ||
6d2f5c27 JW |
716 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); |
717 | } | |
718 | ||
719 | static void nvt_cir_log_irqs(u8 status, u8 iren) | |
720 | { | |
068fb7dd | 721 | nvt_dbg("IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s", |
6d2f5c27 JW |
722 | status, iren, |
723 | status & CIR_IRSTS_RDR ? " RDR" : "", | |
724 | status & CIR_IRSTS_RTR ? " RTR" : "", | |
725 | status & CIR_IRSTS_PE ? " PE" : "", | |
726 | status & CIR_IRSTS_RFO ? " RFO" : "", | |
727 | status & CIR_IRSTS_TE ? " TE" : "", | |
728 | status & CIR_IRSTS_TTR ? " TTR" : "", | |
729 | status & CIR_IRSTS_TFU ? " TFU" : "", | |
730 | status & CIR_IRSTS_GH ? " GH" : "", | |
731 | status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE | | |
732 | CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR | | |
733 | CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : ""); | |
734 | } | |
735 | ||
736 | static bool nvt_cir_tx_inactive(struct nvt_dev *nvt) | |
737 | { | |
738 | unsigned long flags; | |
739 | bool tx_inactive; | |
740 | u8 tx_state; | |
741 | ||
742 | spin_lock_irqsave(&nvt->tx.lock, flags); | |
743 | tx_state = nvt->tx.tx_state; | |
744 | spin_unlock_irqrestore(&nvt->tx.lock, flags); | |
745 | ||
746 | tx_inactive = (tx_state == ST_TX_NONE); | |
747 | ||
748 | return tx_inactive; | |
749 | } | |
750 | ||
751 | /* interrupt service routine for incoming and outgoing CIR data */ | |
752 | static irqreturn_t nvt_cir_isr(int irq, void *data) | |
753 | { | |
754 | struct nvt_dev *nvt = data; | |
755 | u8 status, iren, cur_state; | |
756 | unsigned long flags; | |
757 | ||
758 | nvt_dbg_verbose("%s firing", __func__); | |
759 | ||
760 | nvt_efm_enable(nvt); | |
761 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); | |
762 | nvt_efm_disable(nvt); | |
763 | ||
764 | /* | |
765 | * Get IR Status register contents. Write 1 to ack/clear | |
766 | * | |
767 | * bit: reg name - description | |
768 | * 7: CIR_IRSTS_RDR - RX Data Ready | |
769 | * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach | |
770 | * 5: CIR_IRSTS_PE - Packet End | |
771 | * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set) | |
772 | * 3: CIR_IRSTS_TE - TX FIFO Empty | |
773 | * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach | |
774 | * 1: CIR_IRSTS_TFU - TX FIFO Underrun | |
775 | * 0: CIR_IRSTS_GH - Min Length Detected | |
776 | */ | |
777 | status = nvt_cir_reg_read(nvt, CIR_IRSTS); | |
778 | if (!status) { | |
779 | nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__); | |
780 | nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS); | |
2bbf9e06 | 781 | return IRQ_NONE; |
6d2f5c27 JW |
782 | } |
783 | ||
784 | /* ack/clear all irq flags we've got */ | |
785 | nvt_cir_reg_write(nvt, status, CIR_IRSTS); | |
786 | nvt_cir_reg_write(nvt, 0, CIR_IRSTS); | |
787 | ||
788 | /* Interrupt may be shared with CIR Wake, bail if CIR not enabled */ | |
789 | iren = nvt_cir_reg_read(nvt, CIR_IREN); | |
790 | if (!iren) { | |
791 | nvt_dbg_verbose("%s exiting, CIR not enabled", __func__); | |
2bbf9e06 | 792 | return IRQ_NONE; |
6d2f5c27 JW |
793 | } |
794 | ||
068fb7dd | 795 | nvt_cir_log_irqs(status, iren); |
6d2f5c27 JW |
796 | |
797 | if (status & CIR_IRSTS_RTR) { | |
798 | /* FIXME: add code for study/learn mode */ | |
799 | /* We only do rx if not tx'ing */ | |
800 | if (nvt_cir_tx_inactive(nvt)) | |
801 | nvt_get_rx_ir_data(nvt); | |
802 | } | |
803 | ||
804 | if (status & CIR_IRSTS_PE) { | |
805 | if (nvt_cir_tx_inactive(nvt)) | |
806 | nvt_get_rx_ir_data(nvt); | |
807 | ||
808 | spin_lock_irqsave(&nvt->nvt_lock, flags); | |
809 | ||
810 | cur_state = nvt->study_state; | |
811 | ||
812 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); | |
813 | ||
814 | if (cur_state == ST_STUDY_NONE) | |
815 | nvt_clear_cir_fifo(nvt); | |
816 | } | |
817 | ||
818 | if (status & CIR_IRSTS_TE) | |
819 | nvt_clear_tx_fifo(nvt); | |
820 | ||
821 | if (status & CIR_IRSTS_TTR) { | |
822 | unsigned int pos, count; | |
823 | u8 tmp; | |
824 | ||
825 | spin_lock_irqsave(&nvt->tx.lock, flags); | |
826 | ||
827 | pos = nvt->tx.cur_buf_num; | |
828 | count = nvt->tx.buf_count; | |
829 | ||
830 | /* Write data into the hardware tx fifo while pos < count */ | |
831 | if (pos < count) { | |
832 | nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO); | |
833 | nvt->tx.cur_buf_num++; | |
834 | /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */ | |
835 | } else { | |
836 | tmp = nvt_cir_reg_read(nvt, CIR_IREN); | |
837 | nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN); | |
838 | } | |
839 | ||
840 | spin_unlock_irqrestore(&nvt->tx.lock, flags); | |
841 | ||
842 | } | |
843 | ||
844 | if (status & CIR_IRSTS_TFU) { | |
845 | spin_lock_irqsave(&nvt->tx.lock, flags); | |
846 | if (nvt->tx.tx_state == ST_TX_REPLY) { | |
847 | nvt->tx.tx_state = ST_TX_REQUEST; | |
848 | wake_up(&nvt->tx.queue); | |
849 | } | |
850 | spin_unlock_irqrestore(&nvt->tx.lock, flags); | |
851 | } | |
852 | ||
853 | nvt_dbg_verbose("%s done", __func__); | |
2bbf9e06 | 854 | return IRQ_HANDLED; |
6d2f5c27 JW |
855 | } |
856 | ||
857 | /* Interrupt service routine for CIR Wake */ | |
858 | static irqreturn_t nvt_cir_wake_isr(int irq, void *data) | |
859 | { | |
860 | u8 status, iren, val; | |
861 | struct nvt_dev *nvt = data; | |
862 | unsigned long flags; | |
863 | ||
864 | nvt_dbg_wake("%s firing", __func__); | |
865 | ||
866 | status = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS); | |
867 | if (!status) | |
2bbf9e06 | 868 | return IRQ_NONE; |
6d2f5c27 JW |
869 | |
870 | if (status & CIR_WAKE_IRSTS_IR_PENDING) | |
871 | nvt_clear_cir_wake_fifo(nvt); | |
872 | ||
873 | nvt_cir_wake_reg_write(nvt, status, CIR_WAKE_IRSTS); | |
874 | nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IRSTS); | |
875 | ||
876 | /* Interrupt may be shared with CIR, bail if Wake not enabled */ | |
877 | iren = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN); | |
878 | if (!iren) { | |
879 | nvt_dbg_wake("%s exiting, wake not enabled", __func__); | |
2bbf9e06 | 880 | return IRQ_HANDLED; |
6d2f5c27 JW |
881 | } |
882 | ||
883 | if ((status & CIR_WAKE_IRSTS_PE) && | |
884 | (nvt->wake_state == ST_WAKE_START)) { | |
885 | while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)) { | |
886 | val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY); | |
887 | nvt_dbg("setting wake up key: 0x%x", val); | |
888 | } | |
889 | ||
890 | nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN); | |
891 | spin_lock_irqsave(&nvt->nvt_lock, flags); | |
892 | nvt->wake_state = ST_WAKE_FINISH; | |
893 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); | |
894 | } | |
895 | ||
896 | nvt_dbg_wake("%s done", __func__); | |
2bbf9e06 | 897 | return IRQ_HANDLED; |
6d2f5c27 JW |
898 | } |
899 | ||
900 | static void nvt_enable_cir(struct nvt_dev *nvt) | |
901 | { | |
902 | /* set function enable flags */ | |
903 | nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN | | |
904 | CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL, | |
905 | CIR_IRCON); | |
906 | ||
907 | nvt_efm_enable(nvt); | |
908 | ||
909 | /* enable the CIR logical device */ | |
910 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); | |
911 | nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); | |
912 | ||
913 | nvt_efm_disable(nvt); | |
914 | ||
915 | /* clear all pending interrupts */ | |
916 | nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS); | |
917 | ||
918 | /* enable interrupts */ | |
fbdc781c | 919 | nvt_set_cir_iren(nvt); |
6d2f5c27 JW |
920 | } |
921 | ||
922 | static void nvt_disable_cir(struct nvt_dev *nvt) | |
923 | { | |
924 | /* disable CIR interrupts */ | |
925 | nvt_cir_reg_write(nvt, 0, CIR_IREN); | |
926 | ||
927 | /* clear any and all pending interrupts */ | |
928 | nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS); | |
929 | ||
930 | /* clear all function enable flags */ | |
931 | nvt_cir_reg_write(nvt, 0, CIR_IRCON); | |
932 | ||
933 | /* clear hardware rx and tx fifos */ | |
934 | nvt_clear_cir_fifo(nvt); | |
935 | nvt_clear_tx_fifo(nvt); | |
936 | ||
937 | nvt_efm_enable(nvt); | |
938 | ||
939 | /* disable the CIR logical device */ | |
940 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); | |
941 | nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN); | |
942 | ||
943 | nvt_efm_disable(nvt); | |
944 | } | |
945 | ||
d8b4b582 | 946 | static int nvt_open(struct rc_dev *dev) |
6d2f5c27 | 947 | { |
d8b4b582 | 948 | struct nvt_dev *nvt = dev->priv; |
6d2f5c27 JW |
949 | unsigned long flags; |
950 | ||
951 | spin_lock_irqsave(&nvt->nvt_lock, flags); | |
6d2f5c27 JW |
952 | nvt_enable_cir(nvt); |
953 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); | |
954 | ||
955 | return 0; | |
956 | } | |
957 | ||
d8b4b582 | 958 | static void nvt_close(struct rc_dev *dev) |
6d2f5c27 | 959 | { |
d8b4b582 | 960 | struct nvt_dev *nvt = dev->priv; |
6d2f5c27 JW |
961 | unsigned long flags; |
962 | ||
963 | spin_lock_irqsave(&nvt->nvt_lock, flags); | |
6d2f5c27 JW |
964 | nvt_disable_cir(nvt); |
965 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); | |
966 | } | |
967 | ||
968 | /* Allocate memory, probe hardware, and initialize everything */ | |
969 | static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id) | |
970 | { | |
d8b4b582 DH |
971 | struct nvt_dev *nvt; |
972 | struct rc_dev *rdev; | |
6d2f5c27 JW |
973 | int ret = -ENOMEM; |
974 | ||
099256e5 | 975 | nvt = devm_kzalloc(&pdev->dev, sizeof(struct nvt_dev), GFP_KERNEL); |
6d2f5c27 JW |
976 | if (!nvt) |
977 | return ret; | |
978 | ||
6d2f5c27 | 979 | /* input device for IR remote (and tx) */ |
d8b4b582 | 980 | rdev = rc_allocate_device(); |
6d2f5c27 | 981 | if (!rdev) |
70ef6991 | 982 | goto exit_free_dev_rdev; |
6d2f5c27 JW |
983 | |
984 | ret = -ENODEV; | |
c3c2077d AS |
985 | /* activate pnp device */ |
986 | if (pnp_activate_dev(pdev) < 0) { | |
987 | dev_err(&pdev->dev, "Could not activate PNP device!\n"); | |
988 | goto exit_free_dev_rdev; | |
989 | } | |
990 | ||
6d2f5c27 JW |
991 | /* validate pnp resources */ |
992 | if (!pnp_port_valid(pdev, 0) || | |
993 | pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) { | |
994 | dev_err(&pdev->dev, "IR PNP Port not valid!\n"); | |
70ef6991 | 995 | goto exit_free_dev_rdev; |
6d2f5c27 JW |
996 | } |
997 | ||
998 | if (!pnp_irq_valid(pdev, 0)) { | |
999 | dev_err(&pdev->dev, "PNP IRQ not valid!\n"); | |
70ef6991 | 1000 | goto exit_free_dev_rdev; |
6d2f5c27 JW |
1001 | } |
1002 | ||
1003 | if (!pnp_port_valid(pdev, 1) || | |
1004 | pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) { | |
1005 | dev_err(&pdev->dev, "Wake PNP Port not valid!\n"); | |
70ef6991 | 1006 | goto exit_free_dev_rdev; |
6d2f5c27 JW |
1007 | } |
1008 | ||
1009 | nvt->cir_addr = pnp_port_start(pdev, 0); | |
1010 | nvt->cir_irq = pnp_irq(pdev, 0); | |
1011 | ||
1012 | nvt->cir_wake_addr = pnp_port_start(pdev, 1); | |
1013 | /* irq is always shared between cir and cir wake */ | |
1014 | nvt->cir_wake_irq = nvt->cir_irq; | |
1015 | ||
1016 | nvt->cr_efir = CR_EFIR; | |
1017 | nvt->cr_efdr = CR_EFDR; | |
1018 | ||
1019 | spin_lock_init(&nvt->nvt_lock); | |
1020 | spin_lock_init(&nvt->tx.lock); | |
1021 | ||
6d2f5c27 JW |
1022 | pnp_set_drvdata(pdev, nvt); |
1023 | nvt->pdev = pdev; | |
1024 | ||
1025 | init_waitqueue_head(&nvt->tx.queue); | |
1026 | ||
6a5a3360 | 1027 | nvt_hw_detect(nvt); |
6d2f5c27 JW |
1028 | |
1029 | /* Initialize CIR & CIR Wake Logical Devices */ | |
1030 | nvt_efm_enable(nvt); | |
1031 | nvt_cir_ldev_init(nvt); | |
1032 | nvt_cir_wake_ldev_init(nvt); | |
1033 | nvt_efm_disable(nvt); | |
1034 | ||
1035 | /* Initialize CIR & CIR Wake Config Registers */ | |
1036 | nvt_cir_regs_init(nvt); | |
1037 | nvt_cir_wake_regs_init(nvt); | |
1038 | ||
d8b4b582 DH |
1039 | /* Set up the rc device */ |
1040 | rdev->priv = nvt; | |
1041 | rdev->driver_type = RC_DRIVER_IR_RAW; | |
c5540fbb | 1042 | rdev->allowed_protocols = RC_BIT_ALL; |
d8b4b582 DH |
1043 | rdev->open = nvt_open; |
1044 | rdev->close = nvt_close; | |
1045 | rdev->tx_ir = nvt_tx_ir; | |
1046 | rdev->s_tx_carrier = nvt_set_tx_carrier; | |
1047 | rdev->input_name = "Nuvoton w836x7hg Infrared Remote Transceiver"; | |
46872d27 | 1048 | rdev->input_phys = "nuvoton/cir0"; |
d8b4b582 DH |
1049 | rdev->input_id.bustype = BUS_HOST; |
1050 | rdev->input_id.vendor = PCI_VENDOR_ID_WINBOND2; | |
1051 | rdev->input_id.product = nvt->chip_major; | |
1052 | rdev->input_id.version = nvt->chip_minor; | |
46872d27 | 1053 | rdev->dev.parent = &pdev->dev; |
d8b4b582 DH |
1054 | rdev->driver_name = NVT_DRIVER_NAME; |
1055 | rdev->map_name = RC_MAP_RC6_MCE; | |
d7b290a1 | 1056 | rdev->timeout = MS_TO_NS(100); |
46872d27 JW |
1057 | /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */ |
1058 | rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD); | |
6d2f5c27 | 1059 | #if 0 |
d8b4b582 DH |
1060 | rdev->min_timeout = XYZ; |
1061 | rdev->max_timeout = XYZ; | |
6d2f5c27 | 1062 | /* tx bits */ |
d8b4b582 | 1063 | rdev->tx_resolution = XYZ; |
6d2f5c27 | 1064 | #endif |
d62b6818 | 1065 | nvt->rdev = rdev; |
6d2f5c27 | 1066 | |
9fa35204 MK |
1067 | ret = rc_register_device(rdev); |
1068 | if (ret) | |
1069 | goto exit_free_dev_rdev; | |
1070 | ||
9ef449c6 LH |
1071 | ret = -EBUSY; |
1072 | /* now claim resources */ | |
099256e5 | 1073 | if (!devm_request_region(&pdev->dev, nvt->cir_addr, |
9ef449c6 | 1074 | CIR_IOREG_LENGTH, NVT_DRIVER_NAME)) |
9fa35204 | 1075 | goto exit_unregister_device; |
9ef449c6 | 1076 | |
099256e5 HK |
1077 | if (devm_request_irq(&pdev->dev, nvt->cir_irq, nvt_cir_isr, |
1078 | IRQF_SHARED, NVT_DRIVER_NAME, (void *)nvt)) | |
1079 | goto exit_unregister_device; | |
9ef449c6 | 1080 | |
099256e5 | 1081 | if (!devm_request_region(&pdev->dev, nvt->cir_wake_addr, |
9ef449c6 | 1082 | CIR_IOREG_LENGTH, NVT_DRIVER_NAME)) |
099256e5 | 1083 | goto exit_unregister_device; |
9ef449c6 | 1084 | |
099256e5 HK |
1085 | if (devm_request_irq(&pdev->dev, nvt->cir_wake_irq, |
1086 | nvt_cir_wake_isr, IRQF_SHARED, | |
1087 | NVT_DRIVER_NAME, (void *)nvt)) | |
1088 | goto exit_unregister_device; | |
9ef449c6 | 1089 | |
46872d27 | 1090 | device_init_wakeup(&pdev->dev, true); |
d62b6818 | 1091 | |
211477fe | 1092 | dev_notice(&pdev->dev, "driver has been successfully loaded\n"); |
6d2f5c27 JW |
1093 | if (debug) { |
1094 | cir_dump_regs(nvt); | |
1095 | cir_wake_dump_regs(nvt); | |
1096 | } | |
1097 | ||
1098 | return 0; | |
1099 | ||
9fa35204 MK |
1100 | exit_unregister_device: |
1101 | rc_unregister_device(rdev); | |
f73e1851 | 1102 | rdev = NULL; |
70ef6991 | 1103 | exit_free_dev_rdev: |
d8b4b582 | 1104 | rc_free_device(rdev); |
6d2f5c27 JW |
1105 | |
1106 | return ret; | |
1107 | } | |
1108 | ||
4c62e976 | 1109 | static void nvt_remove(struct pnp_dev *pdev) |
6d2f5c27 JW |
1110 | { |
1111 | struct nvt_dev *nvt = pnp_get_drvdata(pdev); | |
1112 | unsigned long flags; | |
1113 | ||
1114 | spin_lock_irqsave(&nvt->nvt_lock, flags); | |
1115 | /* disable CIR */ | |
1116 | nvt_cir_reg_write(nvt, 0, CIR_IREN); | |
1117 | nvt_disable_cir(nvt); | |
1118 | /* enable CIR Wake (for IR power-on) */ | |
1119 | nvt_enable_wake(nvt); | |
1120 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); | |
1121 | ||
d8b4b582 | 1122 | rc_unregister_device(nvt->rdev); |
6d2f5c27 JW |
1123 | } |
1124 | ||
1125 | static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state) | |
1126 | { | |
1127 | struct nvt_dev *nvt = pnp_get_drvdata(pdev); | |
1128 | unsigned long flags; | |
1129 | ||
1130 | nvt_dbg("%s called", __func__); | |
1131 | ||
1132 | /* zero out misc state tracking */ | |
1133 | spin_lock_irqsave(&nvt->nvt_lock, flags); | |
1134 | nvt->study_state = ST_STUDY_NONE; | |
1135 | nvt->wake_state = ST_WAKE_NONE; | |
1136 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); | |
1137 | ||
1138 | spin_lock_irqsave(&nvt->tx.lock, flags); | |
1139 | nvt->tx.tx_state = ST_TX_NONE; | |
1140 | spin_unlock_irqrestore(&nvt->tx.lock, flags); | |
1141 | ||
1142 | /* disable all CIR interrupts */ | |
1143 | nvt_cir_reg_write(nvt, 0, CIR_IREN); | |
1144 | ||
1145 | nvt_efm_enable(nvt); | |
1146 | ||
1147 | /* disable cir logical dev */ | |
1148 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); | |
1149 | nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN); | |
1150 | ||
1151 | nvt_efm_disable(nvt); | |
1152 | ||
1153 | /* make sure wake is enabled */ | |
1154 | nvt_enable_wake(nvt); | |
1155 | ||
1156 | return 0; | |
1157 | } | |
1158 | ||
1159 | static int nvt_resume(struct pnp_dev *pdev) | |
1160 | { | |
6d2f5c27 JW |
1161 | struct nvt_dev *nvt = pnp_get_drvdata(pdev); |
1162 | ||
1163 | nvt_dbg("%s called", __func__); | |
1164 | ||
1165 | /* open interrupt */ | |
fbdc781c | 1166 | nvt_set_cir_iren(nvt); |
6d2f5c27 JW |
1167 | |
1168 | /* Enable CIR logical device */ | |
1169 | nvt_efm_enable(nvt); | |
1170 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); | |
1171 | nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); | |
1172 | ||
1173 | nvt_efm_disable(nvt); | |
1174 | ||
1175 | nvt_cir_regs_init(nvt); | |
1176 | nvt_cir_wake_regs_init(nvt); | |
1177 | ||
f2747cf6 | 1178 | return 0; |
6d2f5c27 JW |
1179 | } |
1180 | ||
1181 | static void nvt_shutdown(struct pnp_dev *pdev) | |
1182 | { | |
1183 | struct nvt_dev *nvt = pnp_get_drvdata(pdev); | |
1184 | nvt_enable_wake(nvt); | |
1185 | } | |
1186 | ||
1187 | static const struct pnp_device_id nvt_ids[] = { | |
1188 | { "WEC0530", 0 }, /* CIR */ | |
1189 | { "NTN0530", 0 }, /* CIR for new chip's pnp id*/ | |
1190 | { "", 0 }, | |
1191 | }; | |
1192 | ||
1193 | static struct pnp_driver nvt_driver = { | |
1194 | .name = NVT_DRIVER_NAME, | |
1195 | .id_table = nvt_ids, | |
1196 | .flags = PNP_DRIVER_RES_DO_NOT_CHANGE, | |
1197 | .probe = nvt_probe, | |
4c62e976 | 1198 | .remove = nvt_remove, |
6d2f5c27 JW |
1199 | .suspend = nvt_suspend, |
1200 | .resume = nvt_resume, | |
1201 | .shutdown = nvt_shutdown, | |
1202 | }; | |
1203 | ||
6d2f5c27 JW |
1204 | module_param(debug, int, S_IRUGO | S_IWUSR); |
1205 | MODULE_PARM_DESC(debug, "Enable debugging output"); | |
1206 | ||
1207 | MODULE_DEVICE_TABLE(pnp, nvt_ids); | |
1208 | MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver"); | |
1209 | ||
1210 | MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>"); | |
1211 | MODULE_LICENSE("GPL"); | |
1212 | ||
af638a04 | 1213 | module_pnp_driver(nvt_driver); |