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Commit | Line | Data |
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6d2f5c27 JW |
1 | /* |
2 | * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR | |
3 | * | |
4 | * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com> | |
5 | * Copyright (C) 2009 Nuvoton PS Team | |
6 | * | |
7 | * Special thanks to Nuvoton for providing hardware, spec sheets and | |
8 | * sample code upon which portions of this driver are based. Indirect | |
9 | * thanks also to Maxim Levitsky, whose ene_ir driver this driver is | |
10 | * modeled after. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of the | |
15 | * License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, but | |
18 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
20 | * General Public License for more details. | |
6d2f5c27 JW |
21 | */ |
22 | ||
563cd5ce JP |
23 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
24 | ||
6d2f5c27 JW |
25 | #include <linux/kernel.h> |
26 | #include <linux/module.h> | |
27 | #include <linux/pnp.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/sched.h> | |
31 | #include <linux/slab.h> | |
6bda9644 | 32 | #include <media/rc-core.h> |
6d2f5c27 JW |
33 | #include <linux/pci_ids.h> |
34 | ||
35 | #include "nuvoton-cir.h" | |
36 | ||
449c1fcd HK |
37 | static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt); |
38 | ||
b5cf725c HK |
39 | static const struct nvt_chip nvt_chips[] = { |
40 | { "w83667hg", NVT_W83667HG }, | |
41 | { "NCT6775F", NVT_6775F }, | |
42 | { "NCT6776F", NVT_6776F }, | |
d0b528d5 | 43 | { "NCT6779D", NVT_6779D }, |
b5cf725c HK |
44 | }; |
45 | ||
b24cccca HK |
46 | static inline struct device *nvt_get_dev(const struct nvt_dev *nvt) |
47 | { | |
48 | return nvt->rdev->dev.parent; | |
49 | } | |
50 | ||
b5cf725c HK |
51 | static inline bool is_w83667hg(struct nvt_dev *nvt) |
52 | { | |
53 | return nvt->chip_ver == NVT_W83667HG; | |
54 | } | |
55 | ||
6d2f5c27 JW |
56 | /* write val to config reg */ |
57 | static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg) | |
58 | { | |
59 | outb(reg, nvt->cr_efir); | |
60 | outb(val, nvt->cr_efdr); | |
61 | } | |
62 | ||
63 | /* read val from config reg */ | |
64 | static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg) | |
65 | { | |
66 | outb(reg, nvt->cr_efir); | |
67 | return inb(nvt->cr_efdr); | |
68 | } | |
69 | ||
70 | /* update config register bit without changing other bits */ | |
71 | static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg) | |
72 | { | |
73 | u8 tmp = nvt_cr_read(nvt, reg) | val; | |
74 | nvt_cr_write(nvt, tmp, reg); | |
75 | } | |
76 | ||
77 | /* clear config register bit without changing other bits */ | |
78 | static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg) | |
79 | { | |
80 | u8 tmp = nvt_cr_read(nvt, reg) & ~val; | |
81 | nvt_cr_write(nvt, tmp, reg); | |
82 | } | |
83 | ||
84 | /* enter extended function mode */ | |
3def9ad6 | 85 | static inline int nvt_efm_enable(struct nvt_dev *nvt) |
6d2f5c27 | 86 | { |
3def9ad6 HK |
87 | if (!request_muxed_region(nvt->cr_efir, 2, NVT_DRIVER_NAME)) |
88 | return -EBUSY; | |
89 | ||
6d2f5c27 JW |
90 | /* Enabling Extended Function Mode explicitly requires writing 2x */ |
91 | outb(EFER_EFM_ENABLE, nvt->cr_efir); | |
92 | outb(EFER_EFM_ENABLE, nvt->cr_efir); | |
3def9ad6 HK |
93 | |
94 | return 0; | |
6d2f5c27 JW |
95 | } |
96 | ||
97 | /* exit extended function mode */ | |
98 | static inline void nvt_efm_disable(struct nvt_dev *nvt) | |
99 | { | |
100 | outb(EFER_EFM_DISABLE, nvt->cr_efir); | |
3def9ad6 HK |
101 | |
102 | release_region(nvt->cr_efir, 2); | |
6d2f5c27 JW |
103 | } |
104 | ||
105 | /* | |
106 | * When you want to address a specific logical device, write its logical | |
107 | * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing | |
108 | * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN. | |
109 | */ | |
110 | static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev) | |
111 | { | |
7a89836e | 112 | nvt_cr_write(nvt, ldev, CR_LOGICAL_DEV_SEL); |
6d2f5c27 JW |
113 | } |
114 | ||
0890655c HK |
115 | /* select and enable logical device with setting EFM mode*/ |
116 | static inline void nvt_enable_logical_dev(struct nvt_dev *nvt, u8 ldev) | |
117 | { | |
118 | nvt_efm_enable(nvt); | |
119 | nvt_select_logical_dev(nvt, ldev); | |
120 | nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); | |
121 | nvt_efm_disable(nvt); | |
122 | } | |
123 | ||
a17ede9a HK |
124 | /* select and disable logical device with setting EFM mode*/ |
125 | static inline void nvt_disable_logical_dev(struct nvt_dev *nvt, u8 ldev) | |
126 | { | |
127 | nvt_efm_enable(nvt); | |
128 | nvt_select_logical_dev(nvt, ldev); | |
129 | nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN); | |
130 | nvt_efm_disable(nvt); | |
131 | } | |
132 | ||
6d2f5c27 JW |
133 | /* write val to cir config register */ |
134 | static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset) | |
135 | { | |
136 | outb(val, nvt->cir_addr + offset); | |
137 | } | |
138 | ||
139 | /* read val from cir config register */ | |
140 | static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset) | |
141 | { | |
7ac7b023 | 142 | return inb(nvt->cir_addr + offset); |
6d2f5c27 JW |
143 | } |
144 | ||
145 | /* write val to cir wake register */ | |
146 | static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt, | |
147 | u8 val, u8 offset) | |
148 | { | |
149 | outb(val, nvt->cir_wake_addr + offset); | |
150 | } | |
151 | ||
152 | /* read val from cir wake config register */ | |
153 | static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset) | |
154 | { | |
7ac7b023 | 155 | return inb(nvt->cir_wake_addr + offset); |
6d2f5c27 JW |
156 | } |
157 | ||
fb16aaf5 HK |
158 | /* don't override io address if one is set already */ |
159 | static void nvt_set_ioaddr(struct nvt_dev *nvt, unsigned long *ioaddr) | |
160 | { | |
161 | unsigned long old_addr; | |
162 | ||
163 | old_addr = nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8; | |
164 | old_addr |= nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO); | |
165 | ||
166 | if (old_addr) | |
167 | *ioaddr = old_addr; | |
168 | else { | |
169 | nvt_cr_write(nvt, *ioaddr >> 8, CR_CIR_BASE_ADDR_HI); | |
170 | nvt_cr_write(nvt, *ioaddr & 0xff, CR_CIR_BASE_ADDR_LO); | |
171 | } | |
172 | } | |
173 | ||
97c12974 AS |
174 | static void nvt_write_wakeup_codes(struct rc_dev *dev, |
175 | const u8 *wbuf, int count) | |
176 | { | |
177 | u8 tolerance, config; | |
178 | struct nvt_dev *nvt = dev->priv; | |
c1305a40 | 179 | unsigned long flags; |
97c12974 AS |
180 | int i; |
181 | ||
182 | /* hardcode the tolerance to 10% */ | |
183 | tolerance = DIV_ROUND_UP(count, 10); | |
184 | ||
c1305a40 | 185 | spin_lock_irqsave(&nvt->lock, flags); |
97c12974 AS |
186 | |
187 | nvt_clear_cir_wake_fifo(nvt); | |
188 | nvt_cir_wake_reg_write(nvt, count, CIR_WAKE_FIFO_CMP_DEEP); | |
189 | nvt_cir_wake_reg_write(nvt, tolerance, CIR_WAKE_FIFO_CMP_TOL); | |
190 | ||
191 | config = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON); | |
192 | ||
193 | /* enable writes to wake fifo */ | |
194 | nvt_cir_wake_reg_write(nvt, config | CIR_WAKE_IRCON_MODE1, | |
195 | CIR_WAKE_IRCON); | |
196 | ||
197 | if (count) | |
198 | pr_info("Wake samples (%d) =", count); | |
199 | else | |
200 | pr_info("Wake sample fifo cleared"); | |
201 | ||
202 | for (i = 0; i < count; i++) | |
203 | nvt_cir_wake_reg_write(nvt, wbuf[i], CIR_WAKE_WR_FIFO_DATA); | |
204 | ||
205 | nvt_cir_wake_reg_write(nvt, config, CIR_WAKE_IRCON); | |
206 | ||
c1305a40 | 207 | spin_unlock_irqrestore(&nvt->lock, flags); |
97c12974 AS |
208 | } |
209 | ||
02212001 HK |
210 | static ssize_t wakeup_data_show(struct device *dev, |
211 | struct device_attribute *attr, | |
212 | char *buf) | |
449c1fcd | 213 | { |
449c1fcd HK |
214 | struct rc_dev *rc_dev = to_rc_dev(dev); |
215 | struct nvt_dev *nvt = rc_dev->priv; | |
02212001 | 216 | int fifo_len, duration; |
449c1fcd | 217 | unsigned long flags; |
02212001 | 218 | ssize_t buf_len = 0; |
449c1fcd HK |
219 | int i; |
220 | ||
73d4576d | 221 | spin_lock_irqsave(&nvt->lock, flags); |
449c1fcd HK |
222 | |
223 | fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT); | |
02212001 | 224 | fifo_len = min(fifo_len, WAKEUP_MAX_SIZE); |
449c1fcd HK |
225 | |
226 | /* go to first element to be read */ | |
02212001 | 227 | while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)) |
449c1fcd HK |
228 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY); |
229 | ||
02212001 HK |
230 | for (i = 0; i < fifo_len; i++) { |
231 | duration = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY); | |
232 | duration = (duration & BUF_LEN_MASK) * SAMPLE_PERIOD; | |
233 | buf_len += snprintf(buf + buf_len, PAGE_SIZE - buf_len, | |
234 | "%d ", duration); | |
235 | } | |
236 | buf_len += snprintf(buf + buf_len, PAGE_SIZE - buf_len, "\n"); | |
449c1fcd | 237 | |
73d4576d | 238 | spin_unlock_irqrestore(&nvt->lock, flags); |
449c1fcd | 239 | |
02212001 | 240 | return buf_len; |
449c1fcd HK |
241 | } |
242 | ||
02212001 HK |
243 | static ssize_t wakeup_data_store(struct device *dev, |
244 | struct device_attribute *attr, | |
245 | const char *buf, size_t len) | |
449c1fcd | 246 | { |
449c1fcd | 247 | struct rc_dev *rc_dev = to_rc_dev(dev); |
97c12974 | 248 | u8 wake_buf[WAKEUP_MAX_SIZE]; |
02212001 HK |
249 | char **argv; |
250 | int i, count; | |
251 | unsigned int val; | |
252 | ssize_t ret; | |
253 | ||
254 | argv = argv_split(GFP_KERNEL, buf, &count); | |
255 | if (!argv) | |
256 | return -ENOMEM; | |
257 | if (!count || count > WAKEUP_MAX_SIZE) { | |
258 | ret = -EINVAL; | |
259 | goto out; | |
260 | } | |
449c1fcd | 261 | |
02212001 HK |
262 | for (i = 0; i < count; i++) { |
263 | ret = kstrtouint(argv[i], 10, &val); | |
264 | if (ret) | |
265 | goto out; | |
266 | val = DIV_ROUND_CLOSEST(val, SAMPLE_PERIOD); | |
267 | if (!val || val > 0x7f) { | |
268 | ret = -EINVAL; | |
269 | goto out; | |
270 | } | |
271 | wake_buf[i] = val; | |
272 | /* sequence must start with a pulse */ | |
273 | if (i % 2 == 0) | |
274 | wake_buf[i] |= BUF_PULSE_BIT; | |
275 | } | |
449c1fcd | 276 | |
97c12974 | 277 | nvt_write_wakeup_codes(rc_dev, wake_buf, count); |
449c1fcd | 278 | |
02212001 HK |
279 | ret = len; |
280 | out: | |
281 | argv_free(argv); | |
282 | return ret; | |
449c1fcd | 283 | } |
02212001 | 284 | static DEVICE_ATTR_RW(wakeup_data); |
449c1fcd | 285 | |
6d2f5c27 JW |
286 | /* dump current cir register contents */ |
287 | static void cir_dump_regs(struct nvt_dev *nvt) | |
288 | { | |
289 | nvt_efm_enable(nvt); | |
290 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); | |
291 | ||
563cd5ce JP |
292 | pr_info("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME); |
293 | pr_info(" * CR CIR ACTIVE : 0x%x\n", | |
294 | nvt_cr_read(nvt, CR_LOGICAL_DEV_EN)); | |
295 | pr_info(" * CR CIR BASE ADDR: 0x%x\n", | |
296 | (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) | | |
6d2f5c27 | 297 | nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO)); |
563cd5ce JP |
298 | pr_info(" * CR CIR IRQ NUM: 0x%x\n", |
299 | nvt_cr_read(nvt, CR_CIR_IRQ_RSRC)); | |
6d2f5c27 JW |
300 | |
301 | nvt_efm_disable(nvt); | |
302 | ||
563cd5ce JP |
303 | pr_info("%s: Dump CIR registers:\n", NVT_DRIVER_NAME); |
304 | pr_info(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON)); | |
305 | pr_info(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS)); | |
306 | pr_info(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN)); | |
307 | pr_info(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT)); | |
308 | pr_info(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP)); | |
309 | pr_info(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC)); | |
310 | pr_info(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH)); | |
311 | pr_info(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL)); | |
312 | pr_info(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON)); | |
313 | pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS)); | |
314 | pr_info(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO)); | |
315 | pr_info(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT)); | |
316 | pr_info(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO)); | |
317 | pr_info(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH)); | |
318 | pr_info(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL)); | |
319 | pr_info(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM)); | |
6d2f5c27 JW |
320 | } |
321 | ||
322 | /* dump current cir wake register contents */ | |
323 | static void cir_wake_dump_regs(struct nvt_dev *nvt) | |
324 | { | |
325 | u8 i, fifo_len; | |
326 | ||
327 | nvt_efm_enable(nvt); | |
328 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); | |
329 | ||
563cd5ce JP |
330 | pr_info("%s: Dump CIR WAKE logical device registers:\n", |
331 | NVT_DRIVER_NAME); | |
332 | pr_info(" * CR CIR WAKE ACTIVE : 0x%x\n", | |
333 | nvt_cr_read(nvt, CR_LOGICAL_DEV_EN)); | |
334 | pr_info(" * CR CIR WAKE BASE ADDR: 0x%x\n", | |
335 | (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) | | |
4e6e29ad | 336 | nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO)); |
563cd5ce JP |
337 | pr_info(" * CR CIR WAKE IRQ NUM: 0x%x\n", |
338 | nvt_cr_read(nvt, CR_CIR_IRQ_RSRC)); | |
6d2f5c27 JW |
339 | |
340 | nvt_efm_disable(nvt); | |
341 | ||
563cd5ce JP |
342 | pr_info("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME); |
343 | pr_info(" * IRCON: 0x%x\n", | |
344 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON)); | |
345 | pr_info(" * IRSTS: 0x%x\n", | |
346 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS)); | |
347 | pr_info(" * IREN: 0x%x\n", | |
348 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN)); | |
349 | pr_info(" * FIFO CMP DEEP: 0x%x\n", | |
350 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP)); | |
351 | pr_info(" * FIFO CMP TOL: 0x%x\n", | |
352 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL)); | |
353 | pr_info(" * FIFO COUNT: 0x%x\n", | |
354 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT)); | |
355 | pr_info(" * SLCH: 0x%x\n", | |
356 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH)); | |
357 | pr_info(" * SLCL: 0x%x\n", | |
358 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL)); | |
359 | pr_info(" * FIFOCON: 0x%x\n", | |
360 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON)); | |
361 | pr_info(" * SRXFSTS: 0x%x\n", | |
362 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS)); | |
363 | pr_info(" * SAMPLE RX FIFO: 0x%x\n", | |
364 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO)); | |
365 | pr_info(" * WR FIFO DATA: 0x%x\n", | |
366 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA)); | |
367 | pr_info(" * RD FIFO ONLY: 0x%x\n", | |
368 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY)); | |
369 | pr_info(" * RD FIFO ONLY IDX: 0x%x\n", | |
370 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)); | |
371 | pr_info(" * FIFO IGNORE: 0x%x\n", | |
372 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE)); | |
373 | pr_info(" * IRFSM: 0x%x\n", | |
374 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM)); | |
6d2f5c27 JW |
375 | |
376 | fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT); | |
563cd5ce JP |
377 | pr_info("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len); |
378 | pr_info("* Contents ="); | |
6d2f5c27 | 379 | for (i = 0; i < fifo_len; i++) |
563cd5ce JP |
380 | pr_cont(" %02x", |
381 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY)); | |
382 | pr_cont("\n"); | |
6d2f5c27 JW |
383 | } |
384 | ||
b5cf725c HK |
385 | static inline const char *nvt_find_chip(struct nvt_dev *nvt, int id) |
386 | { | |
387 | int i; | |
388 | ||
389 | for (i = 0; i < ARRAY_SIZE(nvt_chips); i++) | |
390 | if ((id & SIO_ID_MASK) == nvt_chips[i].chip_ver) { | |
391 | nvt->chip_ver = nvt_chips[i].chip_ver; | |
392 | return nvt_chips[i].name; | |
393 | } | |
394 | ||
395 | return NULL; | |
396 | } | |
397 | ||
398 | ||
6d2f5c27 | 399 | /* detect hardware features */ |
3f1321cb | 400 | static int nvt_hw_detect(struct nvt_dev *nvt) |
6d2f5c27 | 401 | { |
b24cccca | 402 | struct device *dev = nvt_get_dev(nvt); |
b5cf725c HK |
403 | const char *chip_name; |
404 | int chip_id; | |
6d2f5c27 JW |
405 | |
406 | nvt_efm_enable(nvt); | |
407 | ||
408 | /* Check if we're wired for the alternate EFER setup */ | |
b5cf725c HK |
409 | nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI); |
410 | if (nvt->chip_major == 0xff) { | |
5cac1f67 | 411 | nvt_efm_disable(nvt); |
6d2f5c27 JW |
412 | nvt->cr_efir = CR_EFIR2; |
413 | nvt->cr_efdr = CR_EFDR2; | |
414 | nvt_efm_enable(nvt); | |
b5cf725c | 415 | nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI); |
6d2f5c27 | 416 | } |
b5cf725c HK |
417 | nvt->chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO); |
418 | ||
3f1321cb HK |
419 | nvt_efm_disable(nvt); |
420 | ||
b5cf725c | 421 | chip_id = nvt->chip_major << 8 | nvt->chip_minor; |
3f1321cb | 422 | if (chip_id == NVT_INVALID) { |
b24cccca | 423 | dev_err(dev, "No device found on either EFM port\n"); |
3f1321cb HK |
424 | return -ENODEV; |
425 | } | |
426 | ||
b5cf725c | 427 | chip_name = nvt_find_chip(nvt, chip_id); |
6d2f5c27 | 428 | |
362d3a3a | 429 | /* warn, but still let the driver load, if we don't know this chip */ |
b5cf725c | 430 | if (!chip_name) |
b24cccca | 431 | dev_warn(dev, |
211477fe HK |
432 | "unknown chip, id: 0x%02x 0x%02x, it may not work...", |
433 | nvt->chip_major, nvt->chip_minor); | |
362d3a3a | 434 | else |
b24cccca | 435 | dev_info(dev, "found %s or compatible: chip id: 0x%02x 0x%02x", |
af082334 | 436 | chip_name, nvt->chip_major, nvt->chip_minor); |
362d3a3a | 437 | |
3f1321cb | 438 | return 0; |
6d2f5c27 JW |
439 | } |
440 | ||
441 | static void nvt_cir_ldev_init(struct nvt_dev *nvt) | |
442 | { | |
39381d4f JW |
443 | u8 val, psreg, psmask, psval; |
444 | ||
b5cf725c | 445 | if (is_w83667hg(nvt)) { |
39381d4f JW |
446 | psreg = CR_MULTIFUNC_PIN_SEL; |
447 | psmask = MULTIFUNC_PIN_SEL_MASK; | |
448 | psval = MULTIFUNC_ENABLE_CIR | MULTIFUNC_ENABLE_CIRWB; | |
449 | } else { | |
450 | psreg = CR_OUTPUT_PIN_SEL; | |
451 | psmask = OUTPUT_PIN_SEL_MASK; | |
452 | psval = OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB; | |
453 | } | |
6d2f5c27 | 454 | |
39381d4f JW |
455 | /* output pin selection: enable CIR, with WB sensor enabled */ |
456 | val = nvt_cr_read(nvt, psreg); | |
457 | val &= psmask; | |
458 | val |= psval; | |
459 | nvt_cr_write(nvt, val, psreg); | |
6d2f5c27 | 460 | |
ccca00d6 | 461 | /* Select CIR logical device */ |
6d2f5c27 | 462 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); |
6d2f5c27 | 463 | |
fb16aaf5 | 464 | nvt_set_ioaddr(nvt, &nvt->cir_addr); |
6d2f5c27 JW |
465 | |
466 | nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC); | |
467 | ||
468 | nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d", | |
469 | nvt->cir_addr, nvt->cir_irq); | |
470 | } | |
471 | ||
472 | static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt) | |
473 | { | |
ccca00d6 | 474 | /* Select ACPI logical device and anable it */ |
6d2f5c27 JW |
475 | nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI); |
476 | nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); | |
477 | ||
478 | /* Enable CIR Wake via PSOUT# (Pin60) */ | |
479 | nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE); | |
480 | ||
6d2f5c27 JW |
481 | /* enable pme interrupt of cir wakeup event */ |
482 | nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2); | |
483 | ||
ccca00d6 | 484 | /* Select CIR Wake logical device */ |
6d2f5c27 | 485 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); |
6d2f5c27 | 486 | |
fb16aaf5 | 487 | nvt_set_ioaddr(nvt, &nvt->cir_wake_addr); |
6d2f5c27 | 488 | |
cb48b369 HK |
489 | nvt_dbg("CIR Wake initialized, base io port address: 0x%lx", |
490 | nvt->cir_wake_addr); | |
6d2f5c27 JW |
491 | } |
492 | ||
493 | /* clear out the hardware's cir rx fifo */ | |
494 | static void nvt_clear_cir_fifo(struct nvt_dev *nvt) | |
495 | { | |
7ac7b023 | 496 | u8 val = nvt_cir_reg_read(nvt, CIR_FIFOCON); |
6d2f5c27 JW |
497 | nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON); |
498 | } | |
499 | ||
500 | /* clear out the hardware's cir wake rx fifo */ | |
501 | static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt) | |
502 | { | |
e1a7d981 HK |
503 | u8 val, config; |
504 | ||
505 | config = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON); | |
506 | ||
507 | /* clearing wake fifo works in learning mode only */ | |
508 | nvt_cir_wake_reg_write(nvt, config & ~CIR_WAKE_IRCON_MODE0, | |
509 | CIR_WAKE_IRCON); | |
6d2f5c27 JW |
510 | |
511 | val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON); | |
512 | nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR, | |
513 | CIR_WAKE_FIFOCON); | |
e1a7d981 HK |
514 | |
515 | nvt_cir_wake_reg_write(nvt, config, CIR_WAKE_IRCON); | |
6d2f5c27 JW |
516 | } |
517 | ||
518 | /* clear out the hardware's cir tx fifo */ | |
519 | static void nvt_clear_tx_fifo(struct nvt_dev *nvt) | |
520 | { | |
521 | u8 val; | |
522 | ||
523 | val = nvt_cir_reg_read(nvt, CIR_FIFOCON); | |
524 | nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON); | |
525 | } | |
526 | ||
fbdc781c JW |
527 | /* enable RX Trigger Level Reach and Packet End interrupts */ |
528 | static void nvt_set_cir_iren(struct nvt_dev *nvt) | |
529 | { | |
530 | u8 iren; | |
531 | ||
398d9da8 | 532 | iren = CIR_IREN_RTR | CIR_IREN_PE | CIR_IREN_RFO; |
fbdc781c JW |
533 | nvt_cir_reg_write(nvt, iren, CIR_IREN); |
534 | } | |
535 | ||
6d2f5c27 JW |
536 | static void nvt_cir_regs_init(struct nvt_dev *nvt) |
537 | { | |
538 | /* set sample limit count (PE interrupt raised when reached) */ | |
539 | nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH); | |
540 | nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL); | |
541 | ||
542 | /* set fifo irq trigger levels */ | |
543 | nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV | | |
544 | CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON); | |
545 | ||
546 | /* | |
547 | * Enable TX and RX, specify carrier on = low, off = high, and set | |
548 | * sample period (currently 50us) | |
549 | */ | |
4e6e29ad JW |
550 | nvt_cir_reg_write(nvt, |
551 | CIR_IRCON_TXEN | CIR_IRCON_RXEN | | |
552 | CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL, | |
553 | CIR_IRCON); | |
6d2f5c27 JW |
554 | |
555 | /* clear hardware rx and tx fifos */ | |
556 | nvt_clear_cir_fifo(nvt); | |
557 | nvt_clear_tx_fifo(nvt); | |
558 | ||
559 | /* clear any and all stray interrupts */ | |
560 | nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS); | |
561 | ||
fbdc781c JW |
562 | /* and finally, enable interrupts */ |
563 | nvt_set_cir_iren(nvt); | |
ccca00d6 HK |
564 | |
565 | /* enable the CIR logical device */ | |
566 | nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR); | |
6d2f5c27 JW |
567 | } |
568 | ||
569 | static void nvt_cir_wake_regs_init(struct nvt_dev *nvt) | |
570 | { | |
6d2f5c27 | 571 | /* |
594ccee6 HK |
572 | * Disable RX, set specific carrier on = low, off = high, |
573 | * and sample period (currently 50us) | |
6d2f5c27 | 574 | */ |
594ccee6 | 575 | nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | |
6d2f5c27 JW |
576 | CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV | |
577 | CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL, | |
578 | CIR_WAKE_IRCON); | |
579 | ||
6d2f5c27 JW |
580 | /* clear any and all stray interrupts */ |
581 | nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS); | |
ccca00d6 HK |
582 | |
583 | /* enable the CIR WAKE logical device */ | |
584 | nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); | |
6d2f5c27 JW |
585 | } |
586 | ||
587 | static void nvt_enable_wake(struct nvt_dev *nvt) | |
588 | { | |
b883af30 HK |
589 | unsigned long flags; |
590 | ||
6d2f5c27 JW |
591 | nvt_efm_enable(nvt); |
592 | ||
593 | nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI); | |
594 | nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE); | |
6d2f5c27 JW |
595 | nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2); |
596 | ||
597 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); | |
598 | nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); | |
599 | ||
600 | nvt_efm_disable(nvt); | |
601 | ||
73d4576d | 602 | spin_lock_irqsave(&nvt->lock, flags); |
b883af30 | 603 | |
6d2f5c27 JW |
604 | nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN | |
605 | CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV | | |
4e6e29ad JW |
606 | CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL, |
607 | CIR_WAKE_IRCON); | |
6d2f5c27 JW |
608 | nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS); |
609 | nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN); | |
b883af30 | 610 | |
73d4576d | 611 | spin_unlock_irqrestore(&nvt->lock, flags); |
6d2f5c27 JW |
612 | } |
613 | ||
230dc94a | 614 | #if 0 /* Currently unused */ |
73d4576d | 615 | /* rx carrier detect only works in learning mode, must be called w/lock */ |
6d2f5c27 JW |
616 | static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt) |
617 | { | |
618 | u32 count, carrier, duration = 0; | |
619 | int i; | |
620 | ||
621 | count = nvt_cir_reg_read(nvt, CIR_FCCL) | | |
622 | nvt_cir_reg_read(nvt, CIR_FCCH) << 8; | |
623 | ||
624 | for (i = 0; i < nvt->pkts; i++) { | |
625 | if (nvt->buf[i] & BUF_PULSE_BIT) | |
626 | duration += nvt->buf[i] & BUF_LEN_MASK; | |
627 | } | |
628 | ||
629 | duration *= SAMPLE_PERIOD; | |
630 | ||
631 | if (!count || !duration) { | |
b24cccca | 632 | dev_notice(nvt_get_dev(nvt), |
211477fe HK |
633 | "Unable to determine carrier! (c:%u, d:%u)", |
634 | count, duration); | |
6d2f5c27 JW |
635 | return 0; |
636 | } | |
637 | ||
b4608fae | 638 | carrier = MS_TO_NS(count) / duration; |
6d2f5c27 JW |
639 | |
640 | if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER)) | |
641 | nvt_dbg("WTF? Carrier frequency out of range!"); | |
642 | ||
643 | nvt_dbg("Carrier frequency: %u (count %u, duration %u)", | |
644 | carrier, count, duration); | |
645 | ||
646 | return carrier; | |
647 | } | |
230dc94a | 648 | #endif |
6d2f5c27 JW |
649 | /* |
650 | * set carrier frequency | |
651 | * | |
652 | * set carrier on 2 registers: CP & CC | |
653 | * always set CP as 0x81 | |
654 | * set CC by SPEC, CC = 3MHz/carrier - 1 | |
655 | */ | |
d8b4b582 | 656 | static int nvt_set_tx_carrier(struct rc_dev *dev, u32 carrier) |
6d2f5c27 | 657 | { |
d8b4b582 | 658 | struct nvt_dev *nvt = dev->priv; |
6d2f5c27 JW |
659 | u16 val; |
660 | ||
48cafec9 DC |
661 | if (carrier == 0) |
662 | return -EINVAL; | |
663 | ||
6d2f5c27 JW |
664 | nvt_cir_reg_write(nvt, 1, CIR_CP); |
665 | val = 3000000 / (carrier) - 1; | |
666 | nvt_cir_reg_write(nvt, val & 0xff, CIR_CC); | |
667 | ||
668 | nvt_dbg("cp: 0x%x cc: 0x%x\n", | |
669 | nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC)); | |
670 | ||
671 | return 0; | |
672 | } | |
673 | ||
97c12974 AS |
674 | static int nvt_ir_raw_set_wakeup_filter(struct rc_dev *dev, |
675 | struct rc_scancode_filter *sc_filter) | |
676 | { | |
677 | u8 buf_val; | |
678 | int i, ret, count; | |
679 | unsigned int val; | |
680 | struct ir_raw_event *raw; | |
681 | u8 wake_buf[WAKEUP_MAX_SIZE]; | |
682 | bool complete; | |
683 | ||
684 | /* Require mask to be set */ | |
685 | if (!sc_filter->mask) | |
686 | return 0; | |
687 | ||
688 | raw = kmalloc_array(WAKEUP_MAX_SIZE, sizeof(*raw), GFP_KERNEL); | |
689 | if (!raw) | |
690 | return -ENOMEM; | |
691 | ||
692 | ret = ir_raw_encode_scancode(dev->wakeup_protocol, sc_filter->data, | |
693 | raw, WAKEUP_MAX_SIZE); | |
694 | complete = (ret != -ENOBUFS); | |
695 | if (!complete) | |
696 | ret = WAKEUP_MAX_SIZE; | |
697 | else if (ret < 0) | |
698 | goto out_raw; | |
699 | ||
700 | /* Inspect the ir samples */ | |
701 | for (i = 0, count = 0; i < ret && count < WAKEUP_MAX_SIZE; ++i) { | |
702 | /* NS to US */ | |
703 | val = DIV_ROUND_UP(raw[i].duration, 1000L) / SAMPLE_PERIOD; | |
704 | ||
705 | /* Split too large values into several smaller ones */ | |
706 | while (val > 0 && count < WAKEUP_MAX_SIZE) { | |
707 | /* Skip last value for better comparison tolerance */ | |
708 | if (complete && i == ret - 1 && val < BUF_LEN_MASK) | |
709 | break; | |
710 | ||
711 | /* Clamp values to BUF_LEN_MASK at most */ | |
712 | buf_val = (val > BUF_LEN_MASK) ? BUF_LEN_MASK : val; | |
713 | ||
714 | wake_buf[count] = buf_val; | |
715 | val -= buf_val; | |
716 | if ((raw[i]).pulse) | |
717 | wake_buf[count] |= BUF_PULSE_BIT; | |
718 | count++; | |
719 | } | |
720 | } | |
721 | ||
722 | nvt_write_wakeup_codes(dev, wake_buf, count); | |
723 | ret = 0; | |
724 | out_raw: | |
725 | kfree(raw); | |
726 | ||
727 | return ret; | |
728 | } | |
729 | ||
6d2f5c27 JW |
730 | /* |
731 | * nvt_tx_ir | |
732 | * | |
733 | * 1) clean TX fifo first (handled by AP) | |
734 | * 2) copy data from user space | |
735 | * 3) disable RX interrupts, enable TX interrupts: TTR & TFU | |
736 | * 4) send 9 packets to TX FIFO to open TTR | |
737 | * in interrupt_handler: | |
738 | * 5) send all data out | |
739 | * go back to write(): | |
740 | * 6) disable TX interrupts, re-enable RX interupts | |
741 | * | |
742 | * The key problem of this function is user space data may larger than | |
743 | * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to | |
744 | * buf, and keep current copied data buf num in cur_buf_num. But driver's buf | |
745 | * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to | |
746 | * set TXFCONT as 0xff, until buf_count less than 0xff. | |
747 | */ | |
5588dc2b | 748 | static int nvt_tx_ir(struct rc_dev *dev, unsigned *txbuf, unsigned n) |
6d2f5c27 | 749 | { |
d8b4b582 | 750 | struct nvt_dev *nvt = dev->priv; |
6d2f5c27 | 751 | unsigned long flags; |
6d2f5c27 JW |
752 | unsigned int i; |
753 | u8 iren; | |
754 | int ret; | |
755 | ||
73d4576d | 756 | spin_lock_irqsave(&nvt->lock, flags); |
6d2f5c27 | 757 | |
5588dc2b DH |
758 | ret = min((unsigned)(TX_BUF_LEN / sizeof(unsigned)), n); |
759 | nvt->tx.buf_count = (ret * sizeof(unsigned)); | |
6d2f5c27 JW |
760 | |
761 | memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count); | |
762 | ||
763 | nvt->tx.cur_buf_num = 0; | |
764 | ||
765 | /* save currently enabled interrupts */ | |
766 | iren = nvt_cir_reg_read(nvt, CIR_IREN); | |
767 | ||
768 | /* now disable all interrupts, save TFU & TTR */ | |
769 | nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN); | |
770 | ||
771 | nvt->tx.tx_state = ST_TX_REPLY; | |
772 | ||
773 | nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 | | |
774 | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON); | |
775 | ||
776 | /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */ | |
777 | for (i = 0; i < 9; i++) | |
778 | nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO); | |
779 | ||
73d4576d | 780 | spin_unlock_irqrestore(&nvt->lock, flags); |
6d2f5c27 JW |
781 | |
782 | wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST); | |
783 | ||
73d4576d | 784 | spin_lock_irqsave(&nvt->lock, flags); |
6d2f5c27 | 785 | nvt->tx.tx_state = ST_TX_NONE; |
73d4576d | 786 | spin_unlock_irqrestore(&nvt->lock, flags); |
6d2f5c27 JW |
787 | |
788 | /* restore enabled interrupts to prior state */ | |
789 | nvt_cir_reg_write(nvt, iren, CIR_IREN); | |
790 | ||
791 | return ret; | |
792 | } | |
793 | ||
794 | /* dump contents of the last rx buffer we got from the hw rx fifo */ | |
795 | static void nvt_dump_rx_buf(struct nvt_dev *nvt) | |
796 | { | |
797 | int i; | |
798 | ||
4e6e29ad | 799 | printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts); |
6d2f5c27 | 800 | for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++) |
4e6e29ad JW |
801 | printk(KERN_CONT "0x%02x ", nvt->buf[i]); |
802 | printk(KERN_CONT "\n"); | |
6d2f5c27 JW |
803 | } |
804 | ||
805 | /* | |
806 | * Process raw data in rx driver buffer, store it in raw IR event kfifo, | |
807 | * trigger decode when appropriate. | |
808 | * | |
809 | * We get IR data samples one byte at a time. If the msb is set, its a pulse, | |
810 | * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD | |
811 | * (default 50us) intervals for that pulse/space. A discrete signal is | |
812 | * followed by a series of 0x7f packets, then either 0x7<something> or 0x80 | |
813 | * to signal more IR coming (repeats) or end of IR, respectively. We store | |
814 | * sample data in the raw event kfifo until we see 0x7<something> (except f) | |
815 | * or 0x80, at which time, we trigger a decode operation. | |
816 | */ | |
817 | static void nvt_process_rx_ir_data(struct nvt_dev *nvt) | |
818 | { | |
4651918a | 819 | DEFINE_IR_RAW_EVENT(rawir); |
6d2f5c27 JW |
820 | u8 sample; |
821 | int i; | |
822 | ||
823 | nvt_dbg_verbose("%s firing", __func__); | |
824 | ||
825 | if (debug) | |
826 | nvt_dump_rx_buf(nvt); | |
827 | ||
de4ed0c1 | 828 | nvt_dbg_verbose("Processing buffer of len %d", nvt->pkts); |
6d2f5c27 | 829 | |
de4ed0c1 | 830 | for (i = 0; i < nvt->pkts; i++) { |
6d2f5c27 JW |
831 | sample = nvt->buf[i]; |
832 | ||
833 | rawir.pulse = ((sample & BUF_PULSE_BIT) != 0); | |
b4608fae JW |
834 | rawir.duration = US_TO_NS((sample & BUF_LEN_MASK) |
835 | * SAMPLE_PERIOD); | |
6d2f5c27 | 836 | |
de4ed0c1 JW |
837 | nvt_dbg("Storing %s with duration %d", |
838 | rawir.pulse ? "pulse" : "space", rawir.duration); | |
4651918a | 839 | |
de4ed0c1 | 840 | ir_raw_event_store_with_filter(nvt->rdev, &rawir); |
6d2f5c27 JW |
841 | } |
842 | ||
de4ed0c1 JW |
843 | nvt->pkts = 0; |
844 | ||
a2006ca4 | 845 | nvt_dbg("Calling ir_raw_event_handle\n"); |
b7582815 JW |
846 | ir_raw_event_handle(nvt->rdev); |
847 | ||
6d2f5c27 JW |
848 | nvt_dbg_verbose("%s done", __func__); |
849 | } | |
850 | ||
fbdc781c JW |
851 | static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt) |
852 | { | |
b24cccca | 853 | dev_warn(nvt_get_dev(nvt), "RX FIFO overrun detected, flushing data!"); |
fbdc781c JW |
854 | |
855 | nvt->pkts = 0; | |
856 | nvt_clear_cir_fifo(nvt); | |
857 | ir_raw_event_reset(nvt->rdev); | |
858 | } | |
859 | ||
6d2f5c27 JW |
860 | /* copy data from hardware rx fifo into driver buffer */ |
861 | static void nvt_get_rx_ir_data(struct nvt_dev *nvt) | |
862 | { | |
6db01688 | 863 | u8 fifocount; |
6d2f5c27 JW |
864 | int i; |
865 | ||
866 | /* Get count of how many bytes to read from RX FIFO */ | |
867 | fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT); | |
6d2f5c27 JW |
868 | |
869 | nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount); | |
870 | ||
6d2f5c27 | 871 | /* Read fifocount bytes from CIR Sample RX FIFO register */ |
6db01688 HK |
872 | for (i = 0; i < fifocount; i++) |
873 | nvt->buf[i] = nvt_cir_reg_read(nvt, CIR_SRXFIFO); | |
6d2f5c27 | 874 | |
bacf8351 | 875 | nvt->pkts = fifocount; |
6d2f5c27 JW |
876 | nvt_dbg("%s: pkts now %d", __func__, nvt->pkts); |
877 | ||
878 | nvt_process_rx_ir_data(nvt); | |
6d2f5c27 JW |
879 | } |
880 | ||
881 | static void nvt_cir_log_irqs(u8 status, u8 iren) | |
882 | { | |
068fb7dd | 883 | nvt_dbg("IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s", |
6d2f5c27 JW |
884 | status, iren, |
885 | status & CIR_IRSTS_RDR ? " RDR" : "", | |
886 | status & CIR_IRSTS_RTR ? " RTR" : "", | |
887 | status & CIR_IRSTS_PE ? " PE" : "", | |
888 | status & CIR_IRSTS_RFO ? " RFO" : "", | |
889 | status & CIR_IRSTS_TE ? " TE" : "", | |
890 | status & CIR_IRSTS_TTR ? " TTR" : "", | |
891 | status & CIR_IRSTS_TFU ? " TFU" : "", | |
892 | status & CIR_IRSTS_GH ? " GH" : "", | |
893 | status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE | | |
894 | CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR | | |
895 | CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : ""); | |
896 | } | |
897 | ||
898 | static bool nvt_cir_tx_inactive(struct nvt_dev *nvt) | |
899 | { | |
f7ceec4f | 900 | return nvt->tx.tx_state == ST_TX_NONE; |
6d2f5c27 JW |
901 | } |
902 | ||
903 | /* interrupt service routine for incoming and outgoing CIR data */ | |
904 | static irqreturn_t nvt_cir_isr(int irq, void *data) | |
905 | { | |
906 | struct nvt_dev *nvt = data; | |
e5283f5f | 907 | u8 status, iren; |
6d2f5c27 JW |
908 | |
909 | nvt_dbg_verbose("%s firing", __func__); | |
910 | ||
c044170f | 911 | spin_lock(&nvt->lock); |
e60c1e87 | 912 | |
6d2f5c27 JW |
913 | /* |
914 | * Get IR Status register contents. Write 1 to ack/clear | |
915 | * | |
916 | * bit: reg name - description | |
917 | * 7: CIR_IRSTS_RDR - RX Data Ready | |
918 | * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach | |
919 | * 5: CIR_IRSTS_PE - Packet End | |
920 | * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set) | |
921 | * 3: CIR_IRSTS_TE - TX FIFO Empty | |
922 | * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach | |
923 | * 1: CIR_IRSTS_TFU - TX FIFO Underrun | |
924 | * 0: CIR_IRSTS_GH - Min Length Detected | |
925 | */ | |
926 | status = nvt_cir_reg_read(nvt, CIR_IRSTS); | |
d42fd297 HK |
927 | iren = nvt_cir_reg_read(nvt, CIR_IREN); |
928 | ||
d14f291b HK |
929 | /* At least NCT6779D creates a spurious interrupt when the |
930 | * logical device is being disabled. | |
931 | */ | |
932 | if (status == 0xff && iren == 0xff) { | |
c044170f | 933 | spin_unlock(&nvt->lock); |
d14f291b HK |
934 | nvt_dbg_verbose("Spurious interrupt detected"); |
935 | return IRQ_HANDLED; | |
936 | } | |
937 | ||
d42fd297 HK |
938 | /* IRQ may be shared with CIR WAKE, therefore check for each |
939 | * status bit whether the related interrupt source is enabled | |
940 | */ | |
941 | if (!(status & iren)) { | |
c044170f | 942 | spin_unlock(&nvt->lock); |
6d2f5c27 | 943 | nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__); |
2bbf9e06 | 944 | return IRQ_NONE; |
6d2f5c27 JW |
945 | } |
946 | ||
947 | /* ack/clear all irq flags we've got */ | |
948 | nvt_cir_reg_write(nvt, status, CIR_IRSTS); | |
949 | nvt_cir_reg_write(nvt, 0, CIR_IRSTS); | |
950 | ||
068fb7dd | 951 | nvt_cir_log_irqs(status, iren); |
6d2f5c27 | 952 | |
398d9da8 HK |
953 | if (status & CIR_IRSTS_RFO) |
954 | nvt_handle_rx_fifo_overrun(nvt); | |
955 | ||
228942ef | 956 | else if (status & (CIR_IRSTS_RTR | CIR_IRSTS_PE)) { |
6d2f5c27 JW |
957 | /* We only do rx if not tx'ing */ |
958 | if (nvt_cir_tx_inactive(nvt)) | |
959 | nvt_get_rx_ir_data(nvt); | |
960 | } | |
961 | ||
6d2f5c27 JW |
962 | if (status & CIR_IRSTS_TE) |
963 | nvt_clear_tx_fifo(nvt); | |
964 | ||
965 | if (status & CIR_IRSTS_TTR) { | |
966 | unsigned int pos, count; | |
967 | u8 tmp; | |
968 | ||
6d2f5c27 JW |
969 | pos = nvt->tx.cur_buf_num; |
970 | count = nvt->tx.buf_count; | |
971 | ||
972 | /* Write data into the hardware tx fifo while pos < count */ | |
973 | if (pos < count) { | |
974 | nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO); | |
975 | nvt->tx.cur_buf_num++; | |
976 | /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */ | |
977 | } else { | |
978 | tmp = nvt_cir_reg_read(nvt, CIR_IREN); | |
979 | nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN); | |
980 | } | |
6d2f5c27 JW |
981 | } |
982 | ||
983 | if (status & CIR_IRSTS_TFU) { | |
6d2f5c27 JW |
984 | if (nvt->tx.tx_state == ST_TX_REPLY) { |
985 | nvt->tx.tx_state = ST_TX_REQUEST; | |
986 | wake_up(&nvt->tx.queue); | |
987 | } | |
6d2f5c27 JW |
988 | } |
989 | ||
c044170f | 990 | spin_unlock(&nvt->lock); |
f7ceec4f | 991 | |
6d2f5c27 | 992 | nvt_dbg_verbose("%s done", __func__); |
2bbf9e06 | 993 | return IRQ_HANDLED; |
6d2f5c27 JW |
994 | } |
995 | ||
6d2f5c27 JW |
996 | static void nvt_disable_cir(struct nvt_dev *nvt) |
997 | { | |
137aa361 HK |
998 | unsigned long flags; |
999 | ||
73d4576d | 1000 | spin_lock_irqsave(&nvt->lock, flags); |
137aa361 | 1001 | |
6d2f5c27 JW |
1002 | /* disable CIR interrupts */ |
1003 | nvt_cir_reg_write(nvt, 0, CIR_IREN); | |
1004 | ||
1005 | /* clear any and all pending interrupts */ | |
1006 | nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS); | |
1007 | ||
1008 | /* clear all function enable flags */ | |
1009 | nvt_cir_reg_write(nvt, 0, CIR_IRCON); | |
1010 | ||
1011 | /* clear hardware rx and tx fifos */ | |
1012 | nvt_clear_cir_fifo(nvt); | |
1013 | nvt_clear_tx_fifo(nvt); | |
1014 | ||
73d4576d | 1015 | spin_unlock_irqrestore(&nvt->lock, flags); |
137aa361 | 1016 | |
6d2f5c27 | 1017 | /* disable the CIR logical device */ |
a17ede9a | 1018 | nvt_disable_logical_dev(nvt, LOGICAL_DEV_CIR); |
6d2f5c27 JW |
1019 | } |
1020 | ||
d8b4b582 | 1021 | static int nvt_open(struct rc_dev *dev) |
6d2f5c27 | 1022 | { |
d8b4b582 | 1023 | struct nvt_dev *nvt = dev->priv; |
6d2f5c27 JW |
1024 | unsigned long flags; |
1025 | ||
73d4576d | 1026 | spin_lock_irqsave(&nvt->lock, flags); |
842096fc HK |
1027 | |
1028 | /* set function enable flags */ | |
1029 | nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN | | |
1030 | CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL, | |
1031 | CIR_IRCON); | |
1032 | ||
1033 | /* clear all pending interrupts */ | |
1034 | nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS); | |
1035 | ||
1036 | /* enable interrupts */ | |
1037 | nvt_set_cir_iren(nvt); | |
1038 | ||
73d4576d | 1039 | spin_unlock_irqrestore(&nvt->lock, flags); |
6d2f5c27 | 1040 | |
842096fc HK |
1041 | /* enable the CIR logical device */ |
1042 | nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR); | |
1043 | ||
6d2f5c27 JW |
1044 | return 0; |
1045 | } | |
1046 | ||
d8b4b582 | 1047 | static void nvt_close(struct rc_dev *dev) |
6d2f5c27 | 1048 | { |
d8b4b582 | 1049 | struct nvt_dev *nvt = dev->priv; |
6d2f5c27 | 1050 | |
6d2f5c27 | 1051 | nvt_disable_cir(nvt); |
6d2f5c27 JW |
1052 | } |
1053 | ||
1054 | /* Allocate memory, probe hardware, and initialize everything */ | |
1055 | static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id) | |
1056 | { | |
d8b4b582 DH |
1057 | struct nvt_dev *nvt; |
1058 | struct rc_dev *rdev; | |
b6f3ece3 | 1059 | int ret; |
6d2f5c27 | 1060 | |
099256e5 | 1061 | nvt = devm_kzalloc(&pdev->dev, sizeof(struct nvt_dev), GFP_KERNEL); |
6d2f5c27 | 1062 | if (!nvt) |
b6f3ece3 | 1063 | return -ENOMEM; |
6d2f5c27 | 1064 | |
6d2f5c27 | 1065 | /* input device for IR remote (and tx) */ |
0f7499fd | 1066 | nvt->rdev = devm_rc_allocate_device(&pdev->dev, RC_DRIVER_IR_RAW); |
b24cccca | 1067 | if (!nvt->rdev) |
b6f3ece3 | 1068 | return -ENOMEM; |
b24cccca | 1069 | rdev = nvt->rdev; |
6d2f5c27 | 1070 | |
c3c2077d | 1071 | /* activate pnp device */ |
b6f3ece3 HK |
1072 | ret = pnp_activate_dev(pdev); |
1073 | if (ret) { | |
c3c2077d | 1074 | dev_err(&pdev->dev, "Could not activate PNP device!\n"); |
b6f3ece3 | 1075 | return ret; |
c3c2077d AS |
1076 | } |
1077 | ||
6d2f5c27 JW |
1078 | /* validate pnp resources */ |
1079 | if (!pnp_port_valid(pdev, 0) || | |
1080 | pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) { | |
1081 | dev_err(&pdev->dev, "IR PNP Port not valid!\n"); | |
b6f3ece3 | 1082 | return -EINVAL; |
6d2f5c27 JW |
1083 | } |
1084 | ||
1085 | if (!pnp_irq_valid(pdev, 0)) { | |
1086 | dev_err(&pdev->dev, "PNP IRQ not valid!\n"); | |
b6f3ece3 | 1087 | return -EINVAL; |
6d2f5c27 JW |
1088 | } |
1089 | ||
1090 | if (!pnp_port_valid(pdev, 1) || | |
1091 | pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) { | |
1092 | dev_err(&pdev->dev, "Wake PNP Port not valid!\n"); | |
b6f3ece3 | 1093 | return -EINVAL; |
6d2f5c27 JW |
1094 | } |
1095 | ||
1096 | nvt->cir_addr = pnp_port_start(pdev, 0); | |
1097 | nvt->cir_irq = pnp_irq(pdev, 0); | |
1098 | ||
1099 | nvt->cir_wake_addr = pnp_port_start(pdev, 1); | |
6d2f5c27 JW |
1100 | |
1101 | nvt->cr_efir = CR_EFIR; | |
1102 | nvt->cr_efdr = CR_EFDR; | |
1103 | ||
73d4576d | 1104 | spin_lock_init(&nvt->lock); |
6d2f5c27 | 1105 | |
6d2f5c27 | 1106 | pnp_set_drvdata(pdev, nvt); |
6d2f5c27 JW |
1107 | |
1108 | init_waitqueue_head(&nvt->tx.queue); | |
1109 | ||
3f1321cb HK |
1110 | ret = nvt_hw_detect(nvt); |
1111 | if (ret) | |
b6f3ece3 | 1112 | return ret; |
6d2f5c27 JW |
1113 | |
1114 | /* Initialize CIR & CIR Wake Logical Devices */ | |
1115 | nvt_efm_enable(nvt); | |
1116 | nvt_cir_ldev_init(nvt); | |
1117 | nvt_cir_wake_ldev_init(nvt); | |
1118 | nvt_efm_disable(nvt); | |
1119 | ||
ccca00d6 HK |
1120 | /* |
1121 | * Initialize CIR & CIR Wake Config Registers | |
1122 | * and enable logical devices | |
1123 | */ | |
6d2f5c27 JW |
1124 | nvt_cir_regs_init(nvt); |
1125 | nvt_cir_wake_regs_init(nvt); | |
1126 | ||
d8b4b582 DH |
1127 | /* Set up the rc device */ |
1128 | rdev->priv = nvt; | |
8c34b5c4 | 1129 | rdev->allowed_protocols = RC_BIT_ALL_IR_DECODER; |
97c12974 AS |
1130 | rdev->allowed_wakeup_protocols = RC_BIT_ALL_IR_ENCODER; |
1131 | rdev->encode_wakeup = true; | |
d8b4b582 DH |
1132 | rdev->open = nvt_open; |
1133 | rdev->close = nvt_close; | |
1134 | rdev->tx_ir = nvt_tx_ir; | |
1135 | rdev->s_tx_carrier = nvt_set_tx_carrier; | |
97c12974 | 1136 | rdev->s_wakeup_filter = nvt_ir_raw_set_wakeup_filter; |
d8b4b582 | 1137 | rdev->input_name = "Nuvoton w836x7hg Infrared Remote Transceiver"; |
46872d27 | 1138 | rdev->input_phys = "nuvoton/cir0"; |
d8b4b582 DH |
1139 | rdev->input_id.bustype = BUS_HOST; |
1140 | rdev->input_id.vendor = PCI_VENDOR_ID_WINBOND2; | |
1141 | rdev->input_id.product = nvt->chip_major; | |
1142 | rdev->input_id.version = nvt->chip_minor; | |
1143 | rdev->driver_name = NVT_DRIVER_NAME; | |
1144 | rdev->map_name = RC_MAP_RC6_MCE; | |
d7b290a1 | 1145 | rdev->timeout = MS_TO_NS(100); |
46872d27 JW |
1146 | /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */ |
1147 | rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD); | |
6d2f5c27 | 1148 | #if 0 |
d8b4b582 DH |
1149 | rdev->min_timeout = XYZ; |
1150 | rdev->max_timeout = XYZ; | |
6d2f5c27 | 1151 | /* tx bits */ |
d8b4b582 | 1152 | rdev->tx_resolution = XYZ; |
6d2f5c27 | 1153 | #endif |
b6f3ece3 | 1154 | ret = devm_rc_register_device(&pdev->dev, rdev); |
9fa35204 | 1155 | if (ret) |
b6f3ece3 | 1156 | return ret; |
9fa35204 | 1157 | |
9ef449c6 | 1158 | /* now claim resources */ |
099256e5 | 1159 | if (!devm_request_region(&pdev->dev, nvt->cir_addr, |
9ef449c6 | 1160 | CIR_IOREG_LENGTH, NVT_DRIVER_NAME)) |
b6f3ece3 | 1161 | return -EBUSY; |
9ef449c6 | 1162 | |
b6f3ece3 HK |
1163 | ret = devm_request_irq(&pdev->dev, nvt->cir_irq, nvt_cir_isr, |
1164 | IRQF_SHARED, NVT_DRIVER_NAME, nvt); | |
1165 | if (ret) | |
1166 | return ret; | |
9ef449c6 | 1167 | |
099256e5 | 1168 | if (!devm_request_region(&pdev->dev, nvt->cir_wake_addr, |
33cb5401 | 1169 | CIR_IOREG_LENGTH, NVT_DRIVER_NAME "-wake")) |
b6f3ece3 | 1170 | return -EBUSY; |
9ef449c6 | 1171 | |
02212001 | 1172 | ret = device_create_file(&rdev->dev, &dev_attr_wakeup_data); |
449c1fcd | 1173 | if (ret) |
b6f3ece3 | 1174 | return ret; |
449c1fcd | 1175 | |
46872d27 | 1176 | device_init_wakeup(&pdev->dev, true); |
d62b6818 | 1177 | |
211477fe | 1178 | dev_notice(&pdev->dev, "driver has been successfully loaded\n"); |
6d2f5c27 JW |
1179 | if (debug) { |
1180 | cir_dump_regs(nvt); | |
1181 | cir_wake_dump_regs(nvt); | |
1182 | } | |
1183 | ||
1184 | return 0; | |
6d2f5c27 JW |
1185 | } |
1186 | ||
4c62e976 | 1187 | static void nvt_remove(struct pnp_dev *pdev) |
6d2f5c27 JW |
1188 | { |
1189 | struct nvt_dev *nvt = pnp_get_drvdata(pdev); | |
6d2f5c27 | 1190 | |
02212001 | 1191 | device_remove_file(&nvt->rdev->dev, &dev_attr_wakeup_data); |
449c1fcd | 1192 | |
6d2f5c27 | 1193 | nvt_disable_cir(nvt); |
b883af30 | 1194 | |
6d2f5c27 JW |
1195 | /* enable CIR Wake (for IR power-on) */ |
1196 | nvt_enable_wake(nvt); | |
6d2f5c27 JW |
1197 | } |
1198 | ||
1199 | static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state) | |
1200 | { | |
1201 | struct nvt_dev *nvt = pnp_get_drvdata(pdev); | |
1202 | unsigned long flags; | |
1203 | ||
1204 | nvt_dbg("%s called", __func__); | |
1205 | ||
73d4576d | 1206 | spin_lock_irqsave(&nvt->lock, flags); |
fb2b0065 | 1207 | |
f7ceec4f HK |
1208 | nvt->tx.tx_state = ST_TX_NONE; |
1209 | ||
6d2f5c27 JW |
1210 | /* disable all CIR interrupts */ |
1211 | nvt_cir_reg_write(nvt, 0, CIR_IREN); | |
1212 | ||
73d4576d | 1213 | spin_unlock_irqrestore(&nvt->lock, flags); |
b883af30 | 1214 | |
6d2f5c27 | 1215 | /* disable cir logical dev */ |
a17ede9a | 1216 | nvt_disable_logical_dev(nvt, LOGICAL_DEV_CIR); |
6d2f5c27 JW |
1217 | |
1218 | /* make sure wake is enabled */ | |
1219 | nvt_enable_wake(nvt); | |
1220 | ||
1221 | return 0; | |
1222 | } | |
1223 | ||
1224 | static int nvt_resume(struct pnp_dev *pdev) | |
1225 | { | |
6d2f5c27 JW |
1226 | struct nvt_dev *nvt = pnp_get_drvdata(pdev); |
1227 | ||
1228 | nvt_dbg("%s called", __func__); | |
1229 | ||
6d2f5c27 JW |
1230 | nvt_cir_regs_init(nvt); |
1231 | nvt_cir_wake_regs_init(nvt); | |
1232 | ||
f2747cf6 | 1233 | return 0; |
6d2f5c27 JW |
1234 | } |
1235 | ||
1236 | static void nvt_shutdown(struct pnp_dev *pdev) | |
1237 | { | |
1238 | struct nvt_dev *nvt = pnp_get_drvdata(pdev); | |
fb2b0065 | 1239 | |
6d2f5c27 JW |
1240 | nvt_enable_wake(nvt); |
1241 | } | |
1242 | ||
1243 | static const struct pnp_device_id nvt_ids[] = { | |
1244 | { "WEC0530", 0 }, /* CIR */ | |
1245 | { "NTN0530", 0 }, /* CIR for new chip's pnp id*/ | |
1246 | { "", 0 }, | |
1247 | }; | |
1248 | ||
1249 | static struct pnp_driver nvt_driver = { | |
1250 | .name = NVT_DRIVER_NAME, | |
1251 | .id_table = nvt_ids, | |
1252 | .flags = PNP_DRIVER_RES_DO_NOT_CHANGE, | |
1253 | .probe = nvt_probe, | |
4c62e976 | 1254 | .remove = nvt_remove, |
6d2f5c27 JW |
1255 | .suspend = nvt_suspend, |
1256 | .resume = nvt_resume, | |
1257 | .shutdown = nvt_shutdown, | |
1258 | }; | |
1259 | ||
6d2f5c27 JW |
1260 | module_param(debug, int, S_IRUGO | S_IWUSR); |
1261 | MODULE_PARM_DESC(debug, "Enable debugging output"); | |
1262 | ||
1263 | MODULE_DEVICE_TABLE(pnp, nvt_ids); | |
1264 | MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver"); | |
1265 | ||
1266 | MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>"); | |
1267 | MODULE_LICENSE("GPL"); | |
1268 | ||
af638a04 | 1269 | module_pnp_driver(nvt_driver); |