]>
Commit | Line | Data |
---|---|---|
6d2f5c27 JW |
1 | /* |
2 | * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR | |
3 | * | |
4 | * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com> | |
5 | * Copyright (C) 2009 Nuvoton PS Team | |
6 | * | |
7 | * Special thanks to Nuvoton for providing hardware, spec sheets and | |
8 | * sample code upon which portions of this driver are based. Indirect | |
9 | * thanks also to Maxim Levitsky, whose ene_ir driver this driver is | |
10 | * modeled after. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of the | |
15 | * License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, but | |
18 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
20 | * General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 | |
25 | * USA | |
26 | */ | |
27 | ||
563cd5ce JP |
28 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
29 | ||
6d2f5c27 JW |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/pnp.h> | |
33 | #include <linux/io.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/sched.h> | |
36 | #include <linux/slab.h> | |
6bda9644 | 37 | #include <media/rc-core.h> |
6d2f5c27 JW |
38 | #include <linux/pci_ids.h> |
39 | ||
40 | #include "nuvoton-cir.h" | |
41 | ||
449c1fcd HK |
42 | static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt); |
43 | ||
b5cf725c HK |
44 | static const struct nvt_chip nvt_chips[] = { |
45 | { "w83667hg", NVT_W83667HG }, | |
46 | { "NCT6775F", NVT_6775F }, | |
47 | { "NCT6776F", NVT_6776F }, | |
d0b528d5 | 48 | { "NCT6779D", NVT_6779D }, |
b5cf725c HK |
49 | }; |
50 | ||
b24cccca HK |
51 | static inline struct device *nvt_get_dev(const struct nvt_dev *nvt) |
52 | { | |
53 | return nvt->rdev->dev.parent; | |
54 | } | |
55 | ||
b5cf725c HK |
56 | static inline bool is_w83667hg(struct nvt_dev *nvt) |
57 | { | |
58 | return nvt->chip_ver == NVT_W83667HG; | |
59 | } | |
60 | ||
6d2f5c27 JW |
61 | /* write val to config reg */ |
62 | static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg) | |
63 | { | |
64 | outb(reg, nvt->cr_efir); | |
65 | outb(val, nvt->cr_efdr); | |
66 | } | |
67 | ||
68 | /* read val from config reg */ | |
69 | static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg) | |
70 | { | |
71 | outb(reg, nvt->cr_efir); | |
72 | return inb(nvt->cr_efdr); | |
73 | } | |
74 | ||
75 | /* update config register bit without changing other bits */ | |
76 | static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg) | |
77 | { | |
78 | u8 tmp = nvt_cr_read(nvt, reg) | val; | |
79 | nvt_cr_write(nvt, tmp, reg); | |
80 | } | |
81 | ||
82 | /* clear config register bit without changing other bits */ | |
83 | static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg) | |
84 | { | |
85 | u8 tmp = nvt_cr_read(nvt, reg) & ~val; | |
86 | nvt_cr_write(nvt, tmp, reg); | |
87 | } | |
88 | ||
89 | /* enter extended function mode */ | |
3def9ad6 | 90 | static inline int nvt_efm_enable(struct nvt_dev *nvt) |
6d2f5c27 | 91 | { |
3def9ad6 HK |
92 | if (!request_muxed_region(nvt->cr_efir, 2, NVT_DRIVER_NAME)) |
93 | return -EBUSY; | |
94 | ||
6d2f5c27 JW |
95 | /* Enabling Extended Function Mode explicitly requires writing 2x */ |
96 | outb(EFER_EFM_ENABLE, nvt->cr_efir); | |
97 | outb(EFER_EFM_ENABLE, nvt->cr_efir); | |
3def9ad6 HK |
98 | |
99 | return 0; | |
6d2f5c27 JW |
100 | } |
101 | ||
102 | /* exit extended function mode */ | |
103 | static inline void nvt_efm_disable(struct nvt_dev *nvt) | |
104 | { | |
105 | outb(EFER_EFM_DISABLE, nvt->cr_efir); | |
3def9ad6 HK |
106 | |
107 | release_region(nvt->cr_efir, 2); | |
6d2f5c27 JW |
108 | } |
109 | ||
110 | /* | |
111 | * When you want to address a specific logical device, write its logical | |
112 | * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing | |
113 | * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN. | |
114 | */ | |
115 | static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev) | |
116 | { | |
7a89836e | 117 | nvt_cr_write(nvt, ldev, CR_LOGICAL_DEV_SEL); |
6d2f5c27 JW |
118 | } |
119 | ||
0890655c HK |
120 | /* select and enable logical device with setting EFM mode*/ |
121 | static inline void nvt_enable_logical_dev(struct nvt_dev *nvt, u8 ldev) | |
122 | { | |
123 | nvt_efm_enable(nvt); | |
124 | nvt_select_logical_dev(nvt, ldev); | |
125 | nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); | |
126 | nvt_efm_disable(nvt); | |
127 | } | |
128 | ||
a17ede9a HK |
129 | /* select and disable logical device with setting EFM mode*/ |
130 | static inline void nvt_disable_logical_dev(struct nvt_dev *nvt, u8 ldev) | |
131 | { | |
132 | nvt_efm_enable(nvt); | |
133 | nvt_select_logical_dev(nvt, ldev); | |
134 | nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN); | |
135 | nvt_efm_disable(nvt); | |
136 | } | |
137 | ||
6d2f5c27 JW |
138 | /* write val to cir config register */ |
139 | static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset) | |
140 | { | |
141 | outb(val, nvt->cir_addr + offset); | |
142 | } | |
143 | ||
144 | /* read val from cir config register */ | |
145 | static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset) | |
146 | { | |
7ac7b023 | 147 | return inb(nvt->cir_addr + offset); |
6d2f5c27 JW |
148 | } |
149 | ||
150 | /* write val to cir wake register */ | |
151 | static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt, | |
152 | u8 val, u8 offset) | |
153 | { | |
154 | outb(val, nvt->cir_wake_addr + offset); | |
155 | } | |
156 | ||
157 | /* read val from cir wake config register */ | |
158 | static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset) | |
159 | { | |
7ac7b023 | 160 | return inb(nvt->cir_wake_addr + offset); |
6d2f5c27 JW |
161 | } |
162 | ||
fb16aaf5 HK |
163 | /* don't override io address if one is set already */ |
164 | static void nvt_set_ioaddr(struct nvt_dev *nvt, unsigned long *ioaddr) | |
165 | { | |
166 | unsigned long old_addr; | |
167 | ||
168 | old_addr = nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8; | |
169 | old_addr |= nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO); | |
170 | ||
171 | if (old_addr) | |
172 | *ioaddr = old_addr; | |
173 | else { | |
174 | nvt_cr_write(nvt, *ioaddr >> 8, CR_CIR_BASE_ADDR_HI); | |
175 | nvt_cr_write(nvt, *ioaddr & 0xff, CR_CIR_BASE_ADDR_LO); | |
176 | } | |
177 | } | |
178 | ||
02212001 HK |
179 | static ssize_t wakeup_data_show(struct device *dev, |
180 | struct device_attribute *attr, | |
181 | char *buf) | |
449c1fcd | 182 | { |
449c1fcd HK |
183 | struct rc_dev *rc_dev = to_rc_dev(dev); |
184 | struct nvt_dev *nvt = rc_dev->priv; | |
02212001 | 185 | int fifo_len, duration; |
449c1fcd | 186 | unsigned long flags; |
02212001 | 187 | ssize_t buf_len = 0; |
449c1fcd HK |
188 | int i; |
189 | ||
190 | spin_lock_irqsave(&nvt->nvt_lock, flags); | |
191 | ||
192 | fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT); | |
02212001 | 193 | fifo_len = min(fifo_len, WAKEUP_MAX_SIZE); |
449c1fcd HK |
194 | |
195 | /* go to first element to be read */ | |
02212001 | 196 | while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)) |
449c1fcd HK |
197 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY); |
198 | ||
02212001 HK |
199 | for (i = 0; i < fifo_len; i++) { |
200 | duration = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY); | |
201 | duration = (duration & BUF_LEN_MASK) * SAMPLE_PERIOD; | |
202 | buf_len += snprintf(buf + buf_len, PAGE_SIZE - buf_len, | |
203 | "%d ", duration); | |
204 | } | |
205 | buf_len += snprintf(buf + buf_len, PAGE_SIZE - buf_len, "\n"); | |
449c1fcd HK |
206 | |
207 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); | |
208 | ||
02212001 | 209 | return buf_len; |
449c1fcd HK |
210 | } |
211 | ||
02212001 HK |
212 | static ssize_t wakeup_data_store(struct device *dev, |
213 | struct device_attribute *attr, | |
214 | const char *buf, size_t len) | |
449c1fcd | 215 | { |
449c1fcd HK |
216 | struct rc_dev *rc_dev = to_rc_dev(dev); |
217 | struct nvt_dev *nvt = rc_dev->priv; | |
218 | unsigned long flags; | |
02212001 HK |
219 | u8 tolerance, config, wake_buf[WAKEUP_MAX_SIZE]; |
220 | char **argv; | |
221 | int i, count; | |
222 | unsigned int val; | |
223 | ssize_t ret; | |
224 | ||
225 | argv = argv_split(GFP_KERNEL, buf, &count); | |
226 | if (!argv) | |
227 | return -ENOMEM; | |
228 | if (!count || count > WAKEUP_MAX_SIZE) { | |
229 | ret = -EINVAL; | |
230 | goto out; | |
231 | } | |
449c1fcd | 232 | |
02212001 HK |
233 | for (i = 0; i < count; i++) { |
234 | ret = kstrtouint(argv[i], 10, &val); | |
235 | if (ret) | |
236 | goto out; | |
237 | val = DIV_ROUND_CLOSEST(val, SAMPLE_PERIOD); | |
238 | if (!val || val > 0x7f) { | |
239 | ret = -EINVAL; | |
240 | goto out; | |
241 | } | |
242 | wake_buf[i] = val; | |
243 | /* sequence must start with a pulse */ | |
244 | if (i % 2 == 0) | |
245 | wake_buf[i] |= BUF_PULSE_BIT; | |
246 | } | |
449c1fcd HK |
247 | |
248 | /* hardcode the tolerance to 10% */ | |
249 | tolerance = DIV_ROUND_UP(count, 10); | |
250 | ||
251 | spin_lock_irqsave(&nvt->nvt_lock, flags); | |
252 | ||
253 | nvt_clear_cir_wake_fifo(nvt); | |
254 | nvt_cir_wake_reg_write(nvt, count, CIR_WAKE_FIFO_CMP_DEEP); | |
255 | nvt_cir_wake_reg_write(nvt, tolerance, CIR_WAKE_FIFO_CMP_TOL); | |
256 | ||
257 | config = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON); | |
258 | ||
259 | /* enable writes to wake fifo */ | |
260 | nvt_cir_wake_reg_write(nvt, config | CIR_WAKE_IRCON_MODE1, | |
261 | CIR_WAKE_IRCON); | |
262 | ||
263 | for (i = 0; i < count; i++) | |
02212001 | 264 | nvt_cir_wake_reg_write(nvt, wake_buf[i], CIR_WAKE_WR_FIFO_DATA); |
449c1fcd HK |
265 | |
266 | nvt_cir_wake_reg_write(nvt, config, CIR_WAKE_IRCON); | |
267 | ||
268 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); | |
269 | ||
02212001 HK |
270 | ret = len; |
271 | out: | |
272 | argv_free(argv); | |
273 | return ret; | |
449c1fcd | 274 | } |
02212001 | 275 | static DEVICE_ATTR_RW(wakeup_data); |
449c1fcd | 276 | |
6d2f5c27 JW |
277 | /* dump current cir register contents */ |
278 | static void cir_dump_regs(struct nvt_dev *nvt) | |
279 | { | |
280 | nvt_efm_enable(nvt); | |
281 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); | |
282 | ||
563cd5ce JP |
283 | pr_info("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME); |
284 | pr_info(" * CR CIR ACTIVE : 0x%x\n", | |
285 | nvt_cr_read(nvt, CR_LOGICAL_DEV_EN)); | |
286 | pr_info(" * CR CIR BASE ADDR: 0x%x\n", | |
287 | (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) | | |
6d2f5c27 | 288 | nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO)); |
563cd5ce JP |
289 | pr_info(" * CR CIR IRQ NUM: 0x%x\n", |
290 | nvt_cr_read(nvt, CR_CIR_IRQ_RSRC)); | |
6d2f5c27 JW |
291 | |
292 | nvt_efm_disable(nvt); | |
293 | ||
563cd5ce JP |
294 | pr_info("%s: Dump CIR registers:\n", NVT_DRIVER_NAME); |
295 | pr_info(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON)); | |
296 | pr_info(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS)); | |
297 | pr_info(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN)); | |
298 | pr_info(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT)); | |
299 | pr_info(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP)); | |
300 | pr_info(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC)); | |
301 | pr_info(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH)); | |
302 | pr_info(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL)); | |
303 | pr_info(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON)); | |
304 | pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS)); | |
305 | pr_info(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO)); | |
306 | pr_info(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT)); | |
307 | pr_info(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO)); | |
308 | pr_info(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH)); | |
309 | pr_info(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL)); | |
310 | pr_info(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM)); | |
6d2f5c27 JW |
311 | } |
312 | ||
313 | /* dump current cir wake register contents */ | |
314 | static void cir_wake_dump_regs(struct nvt_dev *nvt) | |
315 | { | |
316 | u8 i, fifo_len; | |
317 | ||
318 | nvt_efm_enable(nvt); | |
319 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); | |
320 | ||
563cd5ce JP |
321 | pr_info("%s: Dump CIR WAKE logical device registers:\n", |
322 | NVT_DRIVER_NAME); | |
323 | pr_info(" * CR CIR WAKE ACTIVE : 0x%x\n", | |
324 | nvt_cr_read(nvt, CR_LOGICAL_DEV_EN)); | |
325 | pr_info(" * CR CIR WAKE BASE ADDR: 0x%x\n", | |
326 | (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) | | |
4e6e29ad | 327 | nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO)); |
563cd5ce JP |
328 | pr_info(" * CR CIR WAKE IRQ NUM: 0x%x\n", |
329 | nvt_cr_read(nvt, CR_CIR_IRQ_RSRC)); | |
6d2f5c27 JW |
330 | |
331 | nvt_efm_disable(nvt); | |
332 | ||
563cd5ce JP |
333 | pr_info("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME); |
334 | pr_info(" * IRCON: 0x%x\n", | |
335 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON)); | |
336 | pr_info(" * IRSTS: 0x%x\n", | |
337 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS)); | |
338 | pr_info(" * IREN: 0x%x\n", | |
339 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN)); | |
340 | pr_info(" * FIFO CMP DEEP: 0x%x\n", | |
341 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP)); | |
342 | pr_info(" * FIFO CMP TOL: 0x%x\n", | |
343 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL)); | |
344 | pr_info(" * FIFO COUNT: 0x%x\n", | |
345 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT)); | |
346 | pr_info(" * SLCH: 0x%x\n", | |
347 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH)); | |
348 | pr_info(" * SLCL: 0x%x\n", | |
349 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL)); | |
350 | pr_info(" * FIFOCON: 0x%x\n", | |
351 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON)); | |
352 | pr_info(" * SRXFSTS: 0x%x\n", | |
353 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS)); | |
354 | pr_info(" * SAMPLE RX FIFO: 0x%x\n", | |
355 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO)); | |
356 | pr_info(" * WR FIFO DATA: 0x%x\n", | |
357 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA)); | |
358 | pr_info(" * RD FIFO ONLY: 0x%x\n", | |
359 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY)); | |
360 | pr_info(" * RD FIFO ONLY IDX: 0x%x\n", | |
361 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)); | |
362 | pr_info(" * FIFO IGNORE: 0x%x\n", | |
363 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE)); | |
364 | pr_info(" * IRFSM: 0x%x\n", | |
365 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM)); | |
6d2f5c27 JW |
366 | |
367 | fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT); | |
563cd5ce JP |
368 | pr_info("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len); |
369 | pr_info("* Contents ="); | |
6d2f5c27 | 370 | for (i = 0; i < fifo_len; i++) |
563cd5ce JP |
371 | pr_cont(" %02x", |
372 | nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY)); | |
373 | pr_cont("\n"); | |
6d2f5c27 JW |
374 | } |
375 | ||
b5cf725c HK |
376 | static inline const char *nvt_find_chip(struct nvt_dev *nvt, int id) |
377 | { | |
378 | int i; | |
379 | ||
380 | for (i = 0; i < ARRAY_SIZE(nvt_chips); i++) | |
381 | if ((id & SIO_ID_MASK) == nvt_chips[i].chip_ver) { | |
382 | nvt->chip_ver = nvt_chips[i].chip_ver; | |
383 | return nvt_chips[i].name; | |
384 | } | |
385 | ||
386 | return NULL; | |
387 | } | |
388 | ||
389 | ||
6d2f5c27 | 390 | /* detect hardware features */ |
3f1321cb | 391 | static int nvt_hw_detect(struct nvt_dev *nvt) |
6d2f5c27 | 392 | { |
b24cccca | 393 | struct device *dev = nvt_get_dev(nvt); |
b5cf725c HK |
394 | const char *chip_name; |
395 | int chip_id; | |
6d2f5c27 JW |
396 | |
397 | nvt_efm_enable(nvt); | |
398 | ||
399 | /* Check if we're wired for the alternate EFER setup */ | |
b5cf725c HK |
400 | nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI); |
401 | if (nvt->chip_major == 0xff) { | |
5cac1f67 | 402 | nvt_efm_disable(nvt); |
6d2f5c27 JW |
403 | nvt->cr_efir = CR_EFIR2; |
404 | nvt->cr_efdr = CR_EFDR2; | |
405 | nvt_efm_enable(nvt); | |
b5cf725c | 406 | nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI); |
6d2f5c27 | 407 | } |
b5cf725c HK |
408 | nvt->chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO); |
409 | ||
3f1321cb HK |
410 | nvt_efm_disable(nvt); |
411 | ||
b5cf725c | 412 | chip_id = nvt->chip_major << 8 | nvt->chip_minor; |
3f1321cb | 413 | if (chip_id == NVT_INVALID) { |
b24cccca | 414 | dev_err(dev, "No device found on either EFM port\n"); |
3f1321cb HK |
415 | return -ENODEV; |
416 | } | |
417 | ||
b5cf725c | 418 | chip_name = nvt_find_chip(nvt, chip_id); |
6d2f5c27 | 419 | |
362d3a3a | 420 | /* warn, but still let the driver load, if we don't know this chip */ |
b5cf725c | 421 | if (!chip_name) |
b24cccca | 422 | dev_warn(dev, |
211477fe HK |
423 | "unknown chip, id: 0x%02x 0x%02x, it may not work...", |
424 | nvt->chip_major, nvt->chip_minor); | |
362d3a3a | 425 | else |
b24cccca | 426 | dev_info(dev, "found %s or compatible: chip id: 0x%02x 0x%02x", |
af082334 | 427 | chip_name, nvt->chip_major, nvt->chip_minor); |
362d3a3a | 428 | |
3f1321cb | 429 | return 0; |
6d2f5c27 JW |
430 | } |
431 | ||
432 | static void nvt_cir_ldev_init(struct nvt_dev *nvt) | |
433 | { | |
39381d4f JW |
434 | u8 val, psreg, psmask, psval; |
435 | ||
b5cf725c | 436 | if (is_w83667hg(nvt)) { |
39381d4f JW |
437 | psreg = CR_MULTIFUNC_PIN_SEL; |
438 | psmask = MULTIFUNC_PIN_SEL_MASK; | |
439 | psval = MULTIFUNC_ENABLE_CIR | MULTIFUNC_ENABLE_CIRWB; | |
440 | } else { | |
441 | psreg = CR_OUTPUT_PIN_SEL; | |
442 | psmask = OUTPUT_PIN_SEL_MASK; | |
443 | psval = OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB; | |
444 | } | |
6d2f5c27 | 445 | |
39381d4f JW |
446 | /* output pin selection: enable CIR, with WB sensor enabled */ |
447 | val = nvt_cr_read(nvt, psreg); | |
448 | val &= psmask; | |
449 | val |= psval; | |
450 | nvt_cr_write(nvt, val, psreg); | |
6d2f5c27 | 451 | |
ccca00d6 | 452 | /* Select CIR logical device */ |
6d2f5c27 | 453 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); |
6d2f5c27 | 454 | |
fb16aaf5 | 455 | nvt_set_ioaddr(nvt, &nvt->cir_addr); |
6d2f5c27 JW |
456 | |
457 | nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC); | |
458 | ||
459 | nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d", | |
460 | nvt->cir_addr, nvt->cir_irq); | |
461 | } | |
462 | ||
463 | static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt) | |
464 | { | |
ccca00d6 | 465 | /* Select ACPI logical device and anable it */ |
6d2f5c27 JW |
466 | nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI); |
467 | nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); | |
468 | ||
469 | /* Enable CIR Wake via PSOUT# (Pin60) */ | |
470 | nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE); | |
471 | ||
6d2f5c27 JW |
472 | /* enable pme interrupt of cir wakeup event */ |
473 | nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2); | |
474 | ||
ccca00d6 | 475 | /* Select CIR Wake logical device */ |
6d2f5c27 | 476 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); |
6d2f5c27 | 477 | |
fb16aaf5 | 478 | nvt_set_ioaddr(nvt, &nvt->cir_wake_addr); |
6d2f5c27 | 479 | |
cb48b369 HK |
480 | nvt_dbg("CIR Wake initialized, base io port address: 0x%lx", |
481 | nvt->cir_wake_addr); | |
6d2f5c27 JW |
482 | } |
483 | ||
484 | /* clear out the hardware's cir rx fifo */ | |
485 | static void nvt_clear_cir_fifo(struct nvt_dev *nvt) | |
486 | { | |
7ac7b023 | 487 | u8 val = nvt_cir_reg_read(nvt, CIR_FIFOCON); |
6d2f5c27 JW |
488 | nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON); |
489 | } | |
490 | ||
491 | /* clear out the hardware's cir wake rx fifo */ | |
492 | static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt) | |
493 | { | |
e1a7d981 HK |
494 | u8 val, config; |
495 | ||
496 | config = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON); | |
497 | ||
498 | /* clearing wake fifo works in learning mode only */ | |
499 | nvt_cir_wake_reg_write(nvt, config & ~CIR_WAKE_IRCON_MODE0, | |
500 | CIR_WAKE_IRCON); | |
6d2f5c27 JW |
501 | |
502 | val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON); | |
503 | nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR, | |
504 | CIR_WAKE_FIFOCON); | |
e1a7d981 HK |
505 | |
506 | nvt_cir_wake_reg_write(nvt, config, CIR_WAKE_IRCON); | |
6d2f5c27 JW |
507 | } |
508 | ||
509 | /* clear out the hardware's cir tx fifo */ | |
510 | static void nvt_clear_tx_fifo(struct nvt_dev *nvt) | |
511 | { | |
512 | u8 val; | |
513 | ||
514 | val = nvt_cir_reg_read(nvt, CIR_FIFOCON); | |
515 | nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON); | |
516 | } | |
517 | ||
fbdc781c JW |
518 | /* enable RX Trigger Level Reach and Packet End interrupts */ |
519 | static void nvt_set_cir_iren(struct nvt_dev *nvt) | |
520 | { | |
521 | u8 iren; | |
522 | ||
398d9da8 | 523 | iren = CIR_IREN_RTR | CIR_IREN_PE | CIR_IREN_RFO; |
fbdc781c JW |
524 | nvt_cir_reg_write(nvt, iren, CIR_IREN); |
525 | } | |
526 | ||
6d2f5c27 JW |
527 | static void nvt_cir_regs_init(struct nvt_dev *nvt) |
528 | { | |
529 | /* set sample limit count (PE interrupt raised when reached) */ | |
530 | nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH); | |
531 | nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL); | |
532 | ||
533 | /* set fifo irq trigger levels */ | |
534 | nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV | | |
535 | CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON); | |
536 | ||
537 | /* | |
538 | * Enable TX and RX, specify carrier on = low, off = high, and set | |
539 | * sample period (currently 50us) | |
540 | */ | |
4e6e29ad JW |
541 | nvt_cir_reg_write(nvt, |
542 | CIR_IRCON_TXEN | CIR_IRCON_RXEN | | |
543 | CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL, | |
544 | CIR_IRCON); | |
6d2f5c27 JW |
545 | |
546 | /* clear hardware rx and tx fifos */ | |
547 | nvt_clear_cir_fifo(nvt); | |
548 | nvt_clear_tx_fifo(nvt); | |
549 | ||
550 | /* clear any and all stray interrupts */ | |
551 | nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS); | |
552 | ||
fbdc781c JW |
553 | /* and finally, enable interrupts */ |
554 | nvt_set_cir_iren(nvt); | |
ccca00d6 HK |
555 | |
556 | /* enable the CIR logical device */ | |
557 | nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR); | |
6d2f5c27 JW |
558 | } |
559 | ||
560 | static void nvt_cir_wake_regs_init(struct nvt_dev *nvt) | |
561 | { | |
6d2f5c27 | 562 | /* |
594ccee6 HK |
563 | * Disable RX, set specific carrier on = low, off = high, |
564 | * and sample period (currently 50us) | |
6d2f5c27 | 565 | */ |
594ccee6 | 566 | nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | |
6d2f5c27 JW |
567 | CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV | |
568 | CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL, | |
569 | CIR_WAKE_IRCON); | |
570 | ||
6d2f5c27 JW |
571 | /* clear any and all stray interrupts */ |
572 | nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS); | |
ccca00d6 HK |
573 | |
574 | /* enable the CIR WAKE logical device */ | |
575 | nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); | |
6d2f5c27 JW |
576 | } |
577 | ||
578 | static void nvt_enable_wake(struct nvt_dev *nvt) | |
579 | { | |
b883af30 HK |
580 | unsigned long flags; |
581 | ||
6d2f5c27 JW |
582 | nvt_efm_enable(nvt); |
583 | ||
584 | nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI); | |
585 | nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE); | |
6d2f5c27 JW |
586 | nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2); |
587 | ||
588 | nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); | |
589 | nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN); | |
590 | ||
591 | nvt_efm_disable(nvt); | |
592 | ||
b883af30 HK |
593 | spin_lock_irqsave(&nvt->nvt_lock, flags); |
594 | ||
6d2f5c27 JW |
595 | nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN | |
596 | CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV | | |
4e6e29ad JW |
597 | CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL, |
598 | CIR_WAKE_IRCON); | |
6d2f5c27 JW |
599 | nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS); |
600 | nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN); | |
b883af30 HK |
601 | |
602 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); | |
6d2f5c27 JW |
603 | } |
604 | ||
230dc94a | 605 | #if 0 /* Currently unused */ |
6d2f5c27 JW |
606 | /* rx carrier detect only works in learning mode, must be called w/nvt_lock */ |
607 | static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt) | |
608 | { | |
609 | u32 count, carrier, duration = 0; | |
610 | int i; | |
611 | ||
612 | count = nvt_cir_reg_read(nvt, CIR_FCCL) | | |
613 | nvt_cir_reg_read(nvt, CIR_FCCH) << 8; | |
614 | ||
615 | for (i = 0; i < nvt->pkts; i++) { | |
616 | if (nvt->buf[i] & BUF_PULSE_BIT) | |
617 | duration += nvt->buf[i] & BUF_LEN_MASK; | |
618 | } | |
619 | ||
620 | duration *= SAMPLE_PERIOD; | |
621 | ||
622 | if (!count || !duration) { | |
b24cccca | 623 | dev_notice(nvt_get_dev(nvt), |
211477fe HK |
624 | "Unable to determine carrier! (c:%u, d:%u)", |
625 | count, duration); | |
6d2f5c27 JW |
626 | return 0; |
627 | } | |
628 | ||
b4608fae | 629 | carrier = MS_TO_NS(count) / duration; |
6d2f5c27 JW |
630 | |
631 | if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER)) | |
632 | nvt_dbg("WTF? Carrier frequency out of range!"); | |
633 | ||
634 | nvt_dbg("Carrier frequency: %u (count %u, duration %u)", | |
635 | carrier, count, duration); | |
636 | ||
637 | return carrier; | |
638 | } | |
230dc94a | 639 | #endif |
6d2f5c27 JW |
640 | /* |
641 | * set carrier frequency | |
642 | * | |
643 | * set carrier on 2 registers: CP & CC | |
644 | * always set CP as 0x81 | |
645 | * set CC by SPEC, CC = 3MHz/carrier - 1 | |
646 | */ | |
d8b4b582 | 647 | static int nvt_set_tx_carrier(struct rc_dev *dev, u32 carrier) |
6d2f5c27 | 648 | { |
d8b4b582 | 649 | struct nvt_dev *nvt = dev->priv; |
6d2f5c27 JW |
650 | u16 val; |
651 | ||
48cafec9 DC |
652 | if (carrier == 0) |
653 | return -EINVAL; | |
654 | ||
6d2f5c27 JW |
655 | nvt_cir_reg_write(nvt, 1, CIR_CP); |
656 | val = 3000000 / (carrier) - 1; | |
657 | nvt_cir_reg_write(nvt, val & 0xff, CIR_CC); | |
658 | ||
659 | nvt_dbg("cp: 0x%x cc: 0x%x\n", | |
660 | nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC)); | |
661 | ||
662 | return 0; | |
663 | } | |
664 | ||
665 | /* | |
666 | * nvt_tx_ir | |
667 | * | |
668 | * 1) clean TX fifo first (handled by AP) | |
669 | * 2) copy data from user space | |
670 | * 3) disable RX interrupts, enable TX interrupts: TTR & TFU | |
671 | * 4) send 9 packets to TX FIFO to open TTR | |
672 | * in interrupt_handler: | |
673 | * 5) send all data out | |
674 | * go back to write(): | |
675 | * 6) disable TX interrupts, re-enable RX interupts | |
676 | * | |
677 | * The key problem of this function is user space data may larger than | |
678 | * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to | |
679 | * buf, and keep current copied data buf num in cur_buf_num. But driver's buf | |
680 | * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to | |
681 | * set TXFCONT as 0xff, until buf_count less than 0xff. | |
682 | */ | |
5588dc2b | 683 | static int nvt_tx_ir(struct rc_dev *dev, unsigned *txbuf, unsigned n) |
6d2f5c27 | 684 | { |
d8b4b582 | 685 | struct nvt_dev *nvt = dev->priv; |
6d2f5c27 | 686 | unsigned long flags; |
6d2f5c27 JW |
687 | unsigned int i; |
688 | u8 iren; | |
689 | int ret; | |
690 | ||
f7ceec4f | 691 | spin_lock_irqsave(&nvt->nvt_lock, flags); |
6d2f5c27 | 692 | |
5588dc2b DH |
693 | ret = min((unsigned)(TX_BUF_LEN / sizeof(unsigned)), n); |
694 | nvt->tx.buf_count = (ret * sizeof(unsigned)); | |
6d2f5c27 JW |
695 | |
696 | memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count); | |
697 | ||
698 | nvt->tx.cur_buf_num = 0; | |
699 | ||
700 | /* save currently enabled interrupts */ | |
701 | iren = nvt_cir_reg_read(nvt, CIR_IREN); | |
702 | ||
703 | /* now disable all interrupts, save TFU & TTR */ | |
704 | nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN); | |
705 | ||
706 | nvt->tx.tx_state = ST_TX_REPLY; | |
707 | ||
708 | nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 | | |
709 | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON); | |
710 | ||
711 | /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */ | |
712 | for (i = 0; i < 9; i++) | |
713 | nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO); | |
714 | ||
f7ceec4f | 715 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); |
6d2f5c27 JW |
716 | |
717 | wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST); | |
718 | ||
f7ceec4f | 719 | spin_lock_irqsave(&nvt->nvt_lock, flags); |
6d2f5c27 | 720 | nvt->tx.tx_state = ST_TX_NONE; |
f7ceec4f | 721 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); |
6d2f5c27 JW |
722 | |
723 | /* restore enabled interrupts to prior state */ | |
724 | nvt_cir_reg_write(nvt, iren, CIR_IREN); | |
725 | ||
726 | return ret; | |
727 | } | |
728 | ||
729 | /* dump contents of the last rx buffer we got from the hw rx fifo */ | |
730 | static void nvt_dump_rx_buf(struct nvt_dev *nvt) | |
731 | { | |
732 | int i; | |
733 | ||
4e6e29ad | 734 | printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts); |
6d2f5c27 | 735 | for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++) |
4e6e29ad JW |
736 | printk(KERN_CONT "0x%02x ", nvt->buf[i]); |
737 | printk(KERN_CONT "\n"); | |
6d2f5c27 JW |
738 | } |
739 | ||
740 | /* | |
741 | * Process raw data in rx driver buffer, store it in raw IR event kfifo, | |
742 | * trigger decode when appropriate. | |
743 | * | |
744 | * We get IR data samples one byte at a time. If the msb is set, its a pulse, | |
745 | * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD | |
746 | * (default 50us) intervals for that pulse/space. A discrete signal is | |
747 | * followed by a series of 0x7f packets, then either 0x7<something> or 0x80 | |
748 | * to signal more IR coming (repeats) or end of IR, respectively. We store | |
749 | * sample data in the raw event kfifo until we see 0x7<something> (except f) | |
750 | * or 0x80, at which time, we trigger a decode operation. | |
751 | */ | |
752 | static void nvt_process_rx_ir_data(struct nvt_dev *nvt) | |
753 | { | |
4651918a | 754 | DEFINE_IR_RAW_EVENT(rawir); |
6d2f5c27 JW |
755 | u8 sample; |
756 | int i; | |
757 | ||
758 | nvt_dbg_verbose("%s firing", __func__); | |
759 | ||
760 | if (debug) | |
761 | nvt_dump_rx_buf(nvt); | |
762 | ||
de4ed0c1 | 763 | nvt_dbg_verbose("Processing buffer of len %d", nvt->pkts); |
6d2f5c27 | 764 | |
de4ed0c1 | 765 | for (i = 0; i < nvt->pkts; i++) { |
6d2f5c27 JW |
766 | sample = nvt->buf[i]; |
767 | ||
768 | rawir.pulse = ((sample & BUF_PULSE_BIT) != 0); | |
b4608fae JW |
769 | rawir.duration = US_TO_NS((sample & BUF_LEN_MASK) |
770 | * SAMPLE_PERIOD); | |
6d2f5c27 | 771 | |
de4ed0c1 JW |
772 | nvt_dbg("Storing %s with duration %d", |
773 | rawir.pulse ? "pulse" : "space", rawir.duration); | |
4651918a | 774 | |
de4ed0c1 | 775 | ir_raw_event_store_with_filter(nvt->rdev, &rawir); |
6d2f5c27 JW |
776 | } |
777 | ||
de4ed0c1 JW |
778 | nvt->pkts = 0; |
779 | ||
a2006ca4 | 780 | nvt_dbg("Calling ir_raw_event_handle\n"); |
b7582815 JW |
781 | ir_raw_event_handle(nvt->rdev); |
782 | ||
6d2f5c27 JW |
783 | nvt_dbg_verbose("%s done", __func__); |
784 | } | |
785 | ||
fbdc781c JW |
786 | static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt) |
787 | { | |
b24cccca | 788 | dev_warn(nvt_get_dev(nvt), "RX FIFO overrun detected, flushing data!"); |
fbdc781c JW |
789 | |
790 | nvt->pkts = 0; | |
791 | nvt_clear_cir_fifo(nvt); | |
792 | ir_raw_event_reset(nvt->rdev); | |
793 | } | |
794 | ||
6d2f5c27 JW |
795 | /* copy data from hardware rx fifo into driver buffer */ |
796 | static void nvt_get_rx_ir_data(struct nvt_dev *nvt) | |
797 | { | |
6db01688 | 798 | u8 fifocount; |
6d2f5c27 JW |
799 | int i; |
800 | ||
801 | /* Get count of how many bytes to read from RX FIFO */ | |
802 | fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT); | |
6d2f5c27 JW |
803 | |
804 | nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount); | |
805 | ||
6d2f5c27 | 806 | /* Read fifocount bytes from CIR Sample RX FIFO register */ |
6db01688 HK |
807 | for (i = 0; i < fifocount; i++) |
808 | nvt->buf[i] = nvt_cir_reg_read(nvt, CIR_SRXFIFO); | |
6d2f5c27 | 809 | |
bacf8351 | 810 | nvt->pkts = fifocount; |
6d2f5c27 JW |
811 | nvt_dbg("%s: pkts now %d", __func__, nvt->pkts); |
812 | ||
813 | nvt_process_rx_ir_data(nvt); | |
6d2f5c27 JW |
814 | } |
815 | ||
816 | static void nvt_cir_log_irqs(u8 status, u8 iren) | |
817 | { | |
068fb7dd | 818 | nvt_dbg("IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s", |
6d2f5c27 JW |
819 | status, iren, |
820 | status & CIR_IRSTS_RDR ? " RDR" : "", | |
821 | status & CIR_IRSTS_RTR ? " RTR" : "", | |
822 | status & CIR_IRSTS_PE ? " PE" : "", | |
823 | status & CIR_IRSTS_RFO ? " RFO" : "", | |
824 | status & CIR_IRSTS_TE ? " TE" : "", | |
825 | status & CIR_IRSTS_TTR ? " TTR" : "", | |
826 | status & CIR_IRSTS_TFU ? " TFU" : "", | |
827 | status & CIR_IRSTS_GH ? " GH" : "", | |
828 | status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE | | |
829 | CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR | | |
830 | CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : ""); | |
831 | } | |
832 | ||
833 | static bool nvt_cir_tx_inactive(struct nvt_dev *nvt) | |
834 | { | |
f7ceec4f | 835 | return nvt->tx.tx_state == ST_TX_NONE; |
6d2f5c27 JW |
836 | } |
837 | ||
838 | /* interrupt service routine for incoming and outgoing CIR data */ | |
839 | static irqreturn_t nvt_cir_isr(int irq, void *data) | |
840 | { | |
841 | struct nvt_dev *nvt = data; | |
e5283f5f | 842 | u8 status, iren; |
6d2f5c27 JW |
843 | unsigned long flags; |
844 | ||
845 | nvt_dbg_verbose("%s firing", __func__); | |
846 | ||
e60c1e87 HK |
847 | spin_lock_irqsave(&nvt->nvt_lock, flags); |
848 | ||
6d2f5c27 JW |
849 | /* |
850 | * Get IR Status register contents. Write 1 to ack/clear | |
851 | * | |
852 | * bit: reg name - description | |
853 | * 7: CIR_IRSTS_RDR - RX Data Ready | |
854 | * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach | |
855 | * 5: CIR_IRSTS_PE - Packet End | |
856 | * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set) | |
857 | * 3: CIR_IRSTS_TE - TX FIFO Empty | |
858 | * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach | |
859 | * 1: CIR_IRSTS_TFU - TX FIFO Underrun | |
860 | * 0: CIR_IRSTS_GH - Min Length Detected | |
861 | */ | |
862 | status = nvt_cir_reg_read(nvt, CIR_IRSTS); | |
d42fd297 HK |
863 | iren = nvt_cir_reg_read(nvt, CIR_IREN); |
864 | ||
d14f291b HK |
865 | /* At least NCT6779D creates a spurious interrupt when the |
866 | * logical device is being disabled. | |
867 | */ | |
868 | if (status == 0xff && iren == 0xff) { | |
869 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); | |
870 | nvt_dbg_verbose("Spurious interrupt detected"); | |
871 | return IRQ_HANDLED; | |
872 | } | |
873 | ||
d42fd297 HK |
874 | /* IRQ may be shared with CIR WAKE, therefore check for each |
875 | * status bit whether the related interrupt source is enabled | |
876 | */ | |
877 | if (!(status & iren)) { | |
e60c1e87 | 878 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); |
6d2f5c27 | 879 | nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__); |
2bbf9e06 | 880 | return IRQ_NONE; |
6d2f5c27 JW |
881 | } |
882 | ||
883 | /* ack/clear all irq flags we've got */ | |
884 | nvt_cir_reg_write(nvt, status, CIR_IRSTS); | |
885 | nvt_cir_reg_write(nvt, 0, CIR_IRSTS); | |
886 | ||
068fb7dd | 887 | nvt_cir_log_irqs(status, iren); |
6d2f5c27 | 888 | |
398d9da8 HK |
889 | if (status & CIR_IRSTS_RFO) |
890 | nvt_handle_rx_fifo_overrun(nvt); | |
891 | ||
228942ef | 892 | else if (status & (CIR_IRSTS_RTR | CIR_IRSTS_PE)) { |
6d2f5c27 JW |
893 | /* We only do rx if not tx'ing */ |
894 | if (nvt_cir_tx_inactive(nvt)) | |
895 | nvt_get_rx_ir_data(nvt); | |
896 | } | |
897 | ||
6d2f5c27 JW |
898 | if (status & CIR_IRSTS_TE) |
899 | nvt_clear_tx_fifo(nvt); | |
900 | ||
901 | if (status & CIR_IRSTS_TTR) { | |
902 | unsigned int pos, count; | |
903 | u8 tmp; | |
904 | ||
6d2f5c27 JW |
905 | pos = nvt->tx.cur_buf_num; |
906 | count = nvt->tx.buf_count; | |
907 | ||
908 | /* Write data into the hardware tx fifo while pos < count */ | |
909 | if (pos < count) { | |
910 | nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO); | |
911 | nvt->tx.cur_buf_num++; | |
912 | /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */ | |
913 | } else { | |
914 | tmp = nvt_cir_reg_read(nvt, CIR_IREN); | |
915 | nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN); | |
916 | } | |
6d2f5c27 JW |
917 | } |
918 | ||
919 | if (status & CIR_IRSTS_TFU) { | |
6d2f5c27 JW |
920 | if (nvt->tx.tx_state == ST_TX_REPLY) { |
921 | nvt->tx.tx_state = ST_TX_REQUEST; | |
922 | wake_up(&nvt->tx.queue); | |
923 | } | |
6d2f5c27 JW |
924 | } |
925 | ||
f7ceec4f HK |
926 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); |
927 | ||
6d2f5c27 | 928 | nvt_dbg_verbose("%s done", __func__); |
2bbf9e06 | 929 | return IRQ_HANDLED; |
6d2f5c27 JW |
930 | } |
931 | ||
6d2f5c27 JW |
932 | static void nvt_disable_cir(struct nvt_dev *nvt) |
933 | { | |
137aa361 HK |
934 | unsigned long flags; |
935 | ||
936 | spin_lock_irqsave(&nvt->nvt_lock, flags); | |
937 | ||
6d2f5c27 JW |
938 | /* disable CIR interrupts */ |
939 | nvt_cir_reg_write(nvt, 0, CIR_IREN); | |
940 | ||
941 | /* clear any and all pending interrupts */ | |
942 | nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS); | |
943 | ||
944 | /* clear all function enable flags */ | |
945 | nvt_cir_reg_write(nvt, 0, CIR_IRCON); | |
946 | ||
947 | /* clear hardware rx and tx fifos */ | |
948 | nvt_clear_cir_fifo(nvt); | |
949 | nvt_clear_tx_fifo(nvt); | |
950 | ||
137aa361 HK |
951 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); |
952 | ||
6d2f5c27 | 953 | /* disable the CIR logical device */ |
a17ede9a | 954 | nvt_disable_logical_dev(nvt, LOGICAL_DEV_CIR); |
6d2f5c27 JW |
955 | } |
956 | ||
d8b4b582 | 957 | static int nvt_open(struct rc_dev *dev) |
6d2f5c27 | 958 | { |
d8b4b582 | 959 | struct nvt_dev *nvt = dev->priv; |
6d2f5c27 JW |
960 | unsigned long flags; |
961 | ||
962 | spin_lock_irqsave(&nvt->nvt_lock, flags); | |
842096fc HK |
963 | |
964 | /* set function enable flags */ | |
965 | nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN | | |
966 | CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL, | |
967 | CIR_IRCON); | |
968 | ||
969 | /* clear all pending interrupts */ | |
970 | nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS); | |
971 | ||
972 | /* enable interrupts */ | |
973 | nvt_set_cir_iren(nvt); | |
974 | ||
6d2f5c27 JW |
975 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); |
976 | ||
842096fc HK |
977 | /* enable the CIR logical device */ |
978 | nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR); | |
979 | ||
6d2f5c27 JW |
980 | return 0; |
981 | } | |
982 | ||
d8b4b582 | 983 | static void nvt_close(struct rc_dev *dev) |
6d2f5c27 | 984 | { |
d8b4b582 | 985 | struct nvt_dev *nvt = dev->priv; |
6d2f5c27 | 986 | |
6d2f5c27 | 987 | nvt_disable_cir(nvt); |
6d2f5c27 JW |
988 | } |
989 | ||
990 | /* Allocate memory, probe hardware, and initialize everything */ | |
991 | static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id) | |
992 | { | |
d8b4b582 DH |
993 | struct nvt_dev *nvt; |
994 | struct rc_dev *rdev; | |
b6f3ece3 | 995 | int ret; |
6d2f5c27 | 996 | |
099256e5 | 997 | nvt = devm_kzalloc(&pdev->dev, sizeof(struct nvt_dev), GFP_KERNEL); |
6d2f5c27 | 998 | if (!nvt) |
b6f3ece3 | 999 | return -ENOMEM; |
6d2f5c27 | 1000 | |
6d2f5c27 | 1001 | /* input device for IR remote (and tx) */ |
b24cccca HK |
1002 | nvt->rdev = devm_rc_allocate_device(&pdev->dev); |
1003 | if (!nvt->rdev) | |
b6f3ece3 | 1004 | return -ENOMEM; |
b24cccca | 1005 | rdev = nvt->rdev; |
6d2f5c27 | 1006 | |
c3c2077d | 1007 | /* activate pnp device */ |
b6f3ece3 HK |
1008 | ret = pnp_activate_dev(pdev); |
1009 | if (ret) { | |
c3c2077d | 1010 | dev_err(&pdev->dev, "Could not activate PNP device!\n"); |
b6f3ece3 | 1011 | return ret; |
c3c2077d AS |
1012 | } |
1013 | ||
6d2f5c27 JW |
1014 | /* validate pnp resources */ |
1015 | if (!pnp_port_valid(pdev, 0) || | |
1016 | pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) { | |
1017 | dev_err(&pdev->dev, "IR PNP Port not valid!\n"); | |
b6f3ece3 | 1018 | return -EINVAL; |
6d2f5c27 JW |
1019 | } |
1020 | ||
1021 | if (!pnp_irq_valid(pdev, 0)) { | |
1022 | dev_err(&pdev->dev, "PNP IRQ not valid!\n"); | |
b6f3ece3 | 1023 | return -EINVAL; |
6d2f5c27 JW |
1024 | } |
1025 | ||
1026 | if (!pnp_port_valid(pdev, 1) || | |
1027 | pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) { | |
1028 | dev_err(&pdev->dev, "Wake PNP Port not valid!\n"); | |
b6f3ece3 | 1029 | return -EINVAL; |
6d2f5c27 JW |
1030 | } |
1031 | ||
1032 | nvt->cir_addr = pnp_port_start(pdev, 0); | |
1033 | nvt->cir_irq = pnp_irq(pdev, 0); | |
1034 | ||
1035 | nvt->cir_wake_addr = pnp_port_start(pdev, 1); | |
6d2f5c27 JW |
1036 | |
1037 | nvt->cr_efir = CR_EFIR; | |
1038 | nvt->cr_efdr = CR_EFDR; | |
1039 | ||
1040 | spin_lock_init(&nvt->nvt_lock); | |
6d2f5c27 | 1041 | |
6d2f5c27 | 1042 | pnp_set_drvdata(pdev, nvt); |
6d2f5c27 JW |
1043 | |
1044 | init_waitqueue_head(&nvt->tx.queue); | |
1045 | ||
3f1321cb HK |
1046 | ret = nvt_hw_detect(nvt); |
1047 | if (ret) | |
b6f3ece3 | 1048 | return ret; |
6d2f5c27 JW |
1049 | |
1050 | /* Initialize CIR & CIR Wake Logical Devices */ | |
1051 | nvt_efm_enable(nvt); | |
1052 | nvt_cir_ldev_init(nvt); | |
1053 | nvt_cir_wake_ldev_init(nvt); | |
1054 | nvt_efm_disable(nvt); | |
1055 | ||
ccca00d6 HK |
1056 | /* |
1057 | * Initialize CIR & CIR Wake Config Registers | |
1058 | * and enable logical devices | |
1059 | */ | |
6d2f5c27 JW |
1060 | nvt_cir_regs_init(nvt); |
1061 | nvt_cir_wake_regs_init(nvt); | |
1062 | ||
d8b4b582 DH |
1063 | /* Set up the rc device */ |
1064 | rdev->priv = nvt; | |
1065 | rdev->driver_type = RC_DRIVER_IR_RAW; | |
c5540fbb | 1066 | rdev->allowed_protocols = RC_BIT_ALL; |
d8b4b582 DH |
1067 | rdev->open = nvt_open; |
1068 | rdev->close = nvt_close; | |
1069 | rdev->tx_ir = nvt_tx_ir; | |
1070 | rdev->s_tx_carrier = nvt_set_tx_carrier; | |
1071 | rdev->input_name = "Nuvoton w836x7hg Infrared Remote Transceiver"; | |
46872d27 | 1072 | rdev->input_phys = "nuvoton/cir0"; |
d8b4b582 DH |
1073 | rdev->input_id.bustype = BUS_HOST; |
1074 | rdev->input_id.vendor = PCI_VENDOR_ID_WINBOND2; | |
1075 | rdev->input_id.product = nvt->chip_major; | |
1076 | rdev->input_id.version = nvt->chip_minor; | |
1077 | rdev->driver_name = NVT_DRIVER_NAME; | |
1078 | rdev->map_name = RC_MAP_RC6_MCE; | |
d7b290a1 | 1079 | rdev->timeout = MS_TO_NS(100); |
46872d27 JW |
1080 | /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */ |
1081 | rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD); | |
6d2f5c27 | 1082 | #if 0 |
d8b4b582 DH |
1083 | rdev->min_timeout = XYZ; |
1084 | rdev->max_timeout = XYZ; | |
6d2f5c27 | 1085 | /* tx bits */ |
d8b4b582 | 1086 | rdev->tx_resolution = XYZ; |
6d2f5c27 | 1087 | #endif |
b6f3ece3 | 1088 | ret = devm_rc_register_device(&pdev->dev, rdev); |
9fa35204 | 1089 | if (ret) |
b6f3ece3 | 1090 | return ret; |
9fa35204 | 1091 | |
9ef449c6 | 1092 | /* now claim resources */ |
099256e5 | 1093 | if (!devm_request_region(&pdev->dev, nvt->cir_addr, |
9ef449c6 | 1094 | CIR_IOREG_LENGTH, NVT_DRIVER_NAME)) |
b6f3ece3 | 1095 | return -EBUSY; |
9ef449c6 | 1096 | |
b6f3ece3 HK |
1097 | ret = devm_request_irq(&pdev->dev, nvt->cir_irq, nvt_cir_isr, |
1098 | IRQF_SHARED, NVT_DRIVER_NAME, nvt); | |
1099 | if (ret) | |
1100 | return ret; | |
9ef449c6 | 1101 | |
099256e5 | 1102 | if (!devm_request_region(&pdev->dev, nvt->cir_wake_addr, |
33cb5401 | 1103 | CIR_IOREG_LENGTH, NVT_DRIVER_NAME "-wake")) |
b6f3ece3 | 1104 | return -EBUSY; |
9ef449c6 | 1105 | |
02212001 | 1106 | ret = device_create_file(&rdev->dev, &dev_attr_wakeup_data); |
449c1fcd | 1107 | if (ret) |
b6f3ece3 | 1108 | return ret; |
449c1fcd | 1109 | |
46872d27 | 1110 | device_init_wakeup(&pdev->dev, true); |
d62b6818 | 1111 | |
211477fe | 1112 | dev_notice(&pdev->dev, "driver has been successfully loaded\n"); |
6d2f5c27 JW |
1113 | if (debug) { |
1114 | cir_dump_regs(nvt); | |
1115 | cir_wake_dump_regs(nvt); | |
1116 | } | |
1117 | ||
1118 | return 0; | |
6d2f5c27 JW |
1119 | } |
1120 | ||
4c62e976 | 1121 | static void nvt_remove(struct pnp_dev *pdev) |
6d2f5c27 JW |
1122 | { |
1123 | struct nvt_dev *nvt = pnp_get_drvdata(pdev); | |
6d2f5c27 | 1124 | |
02212001 | 1125 | device_remove_file(&nvt->rdev->dev, &dev_attr_wakeup_data); |
449c1fcd | 1126 | |
6d2f5c27 | 1127 | nvt_disable_cir(nvt); |
b883af30 | 1128 | |
6d2f5c27 JW |
1129 | /* enable CIR Wake (for IR power-on) */ |
1130 | nvt_enable_wake(nvt); | |
6d2f5c27 JW |
1131 | } |
1132 | ||
1133 | static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state) | |
1134 | { | |
1135 | struct nvt_dev *nvt = pnp_get_drvdata(pdev); | |
1136 | unsigned long flags; | |
1137 | ||
1138 | nvt_dbg("%s called", __func__); | |
1139 | ||
fb2b0065 HK |
1140 | spin_lock_irqsave(&nvt->nvt_lock, flags); |
1141 | ||
f7ceec4f HK |
1142 | nvt->tx.tx_state = ST_TX_NONE; |
1143 | ||
6d2f5c27 JW |
1144 | /* disable all CIR interrupts */ |
1145 | nvt_cir_reg_write(nvt, 0, CIR_IREN); | |
1146 | ||
b883af30 HK |
1147 | spin_unlock_irqrestore(&nvt->nvt_lock, flags); |
1148 | ||
6d2f5c27 | 1149 | /* disable cir logical dev */ |
a17ede9a | 1150 | nvt_disable_logical_dev(nvt, LOGICAL_DEV_CIR); |
6d2f5c27 JW |
1151 | |
1152 | /* make sure wake is enabled */ | |
1153 | nvt_enable_wake(nvt); | |
1154 | ||
1155 | return 0; | |
1156 | } | |
1157 | ||
1158 | static int nvt_resume(struct pnp_dev *pdev) | |
1159 | { | |
6d2f5c27 JW |
1160 | struct nvt_dev *nvt = pnp_get_drvdata(pdev); |
1161 | ||
1162 | nvt_dbg("%s called", __func__); | |
1163 | ||
6d2f5c27 JW |
1164 | nvt_cir_regs_init(nvt); |
1165 | nvt_cir_wake_regs_init(nvt); | |
1166 | ||
f2747cf6 | 1167 | return 0; |
6d2f5c27 JW |
1168 | } |
1169 | ||
1170 | static void nvt_shutdown(struct pnp_dev *pdev) | |
1171 | { | |
1172 | struct nvt_dev *nvt = pnp_get_drvdata(pdev); | |
fb2b0065 | 1173 | |
6d2f5c27 JW |
1174 | nvt_enable_wake(nvt); |
1175 | } | |
1176 | ||
1177 | static const struct pnp_device_id nvt_ids[] = { | |
1178 | { "WEC0530", 0 }, /* CIR */ | |
1179 | { "NTN0530", 0 }, /* CIR for new chip's pnp id*/ | |
1180 | { "", 0 }, | |
1181 | }; | |
1182 | ||
1183 | static struct pnp_driver nvt_driver = { | |
1184 | .name = NVT_DRIVER_NAME, | |
1185 | .id_table = nvt_ids, | |
1186 | .flags = PNP_DRIVER_RES_DO_NOT_CHANGE, | |
1187 | .probe = nvt_probe, | |
4c62e976 | 1188 | .remove = nvt_remove, |
6d2f5c27 JW |
1189 | .suspend = nvt_suspend, |
1190 | .resume = nvt_resume, | |
1191 | .shutdown = nvt_shutdown, | |
1192 | }; | |
1193 | ||
6d2f5c27 JW |
1194 | module_param(debug, int, S_IRUGO | S_IWUSR); |
1195 | MODULE_PARM_DESC(debug, "Enable debugging output"); | |
1196 | ||
1197 | MODULE_DEVICE_TABLE(pnp, nvt_ids); | |
1198 | MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver"); | |
1199 | ||
1200 | MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>"); | |
1201 | MODULE_LICENSE("GPL"); | |
1202 | ||
af638a04 | 1203 | module_pnp_driver(nvt_driver); |