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Commit | Line | Data |
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1beef3c1 | 1 | /* |
fa5dc29c | 2 | * serial_ir.c |
1beef3c1 | 3 | * |
fa5dc29c | 4 | * serial_ir - Device driver that records pulse- and pause-lengths |
1beef3c1 JW |
5 | * (space-lengths) between DDCD event on a serial port. |
6 | * | |
7 | * Copyright (C) 1996,97 Ralph Metzler <rjkm@thp.uni-koeln.de> | |
8 | * Copyright (C) 1998 Trent Piepho <xyzzy@u.washington.edu> | |
9 | * Copyright (C) 1998 Ben Pfaff <blp@gnu.org> | |
10 | * Copyright (C) 1999 Christoph Bartelmus <lirc@bartelmus.de> | |
11 | * Copyright (C) 2007 Andrei Tanas <andrei@tanas.ca> (suspend/resume support) | |
b66db53f | 12 | * Copyright (C) 2016 Sean Young <sean@mess.org> (port to rc-core) |
1beef3c1 JW |
13 | * This program is free software; you can redistribute it and/or modify |
14 | * it under the terms of the GNU General Public License as published by | |
15 | * the Free Software Foundation; either version 2 of the License, or | |
16 | * (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
1beef3c1 JW |
22 | */ |
23 | ||
df4f07b5 YT |
24 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
25 | ||
1beef3c1 JW |
26 | #include <linux/module.h> |
27 | #include <linux/errno.h> | |
1beef3c1 | 28 | #include <linux/interrupt.h> |
1beef3c1 JW |
29 | #include <linux/kernel.h> |
30 | #include <linux/serial_reg.h> | |
1beef3c1 | 31 | #include <linux/types.h> |
1beef3c1 | 32 | #include <linux/delay.h> |
1beef3c1 | 33 | #include <linux/platform_device.h> |
1beef3c1 | 34 | #include <linux/spinlock.h> |
b66db53f | 35 | #include <media/rc-core.h> |
1beef3c1 | 36 | |
b66db53f | 37 | struct serial_ir_hw { |
1beef3c1 JW |
38 | int signal_pin; |
39 | int signal_pin_change; | |
40 | u8 on; | |
41 | u8 off; | |
b66db53f SY |
42 | unsigned set_send_carrier:1; |
43 | unsigned set_duty_cycle:1; | |
0a847634 SY |
44 | void (*send_pulse)(unsigned int length, ktime_t edge); |
45 | void (*send_space)(void); | |
1beef3c1 JW |
46 | spinlock_t lock; |
47 | }; | |
48 | ||
b66db53f SY |
49 | #define IR_HOMEBREW 0 |
50 | #define IR_IRDEO 1 | |
51 | #define IR_IRDEO_REMOTE 2 | |
52 | #define IR_ANIMAX 3 | |
53 | #define IR_IGOR 4 | |
1beef3c1 | 54 | |
b66db53f | 55 | /* module parameters */ |
1beef3c1 JW |
56 | static int type; |
57 | static int io; | |
58 | static int irq; | |
90ab5ee9 | 59 | static bool iommap; |
1beef3c1 | 60 | static int ioshift; |
f3a9d7ef | 61 | static bool softcarrier = true; |
90ab5ee9 | 62 | static bool share_irq; |
1beef3c1 | 63 | static int sense = -1; /* -1 = auto, 0 = active high, 1 = active low */ |
90ab5ee9 | 64 | static bool txsense; /* 0 = active high, 1 = active low */ |
1beef3c1 | 65 | |
1beef3c1 | 66 | /* forward declarations */ |
0a847634 SY |
67 | static void send_pulse_irdeo(unsigned int length, ktime_t edge); |
68 | static void send_space_irdeo(void); | |
b66db53f | 69 | #ifdef CONFIG_IR_SERIAL_TRANSMITTER |
0a847634 SY |
70 | static void send_pulse_homebrew(unsigned int length, ktime_t edge); |
71 | static void send_space_homebrew(void); | |
b66db53f | 72 | #endif |
1beef3c1 | 73 | |
b66db53f SY |
74 | static struct serial_ir_hw hardware[] = { |
75 | [IR_HOMEBREW] = { | |
76 | .lock = __SPIN_LOCK_UNLOCKED(hardware[IR_HOMEBREW].lock), | |
77 | .signal_pin = UART_MSR_DCD, | |
1beef3c1 JW |
78 | .signal_pin_change = UART_MSR_DDCD, |
79 | .on = (UART_MCR_RTS | UART_MCR_OUT2 | UART_MCR_DTR), | |
80 | .off = (UART_MCR_RTS | UART_MCR_OUT2), | |
b66db53f | 81 | #ifdef CONFIG_IR_SERIAL_TRANSMITTER |
1beef3c1 JW |
82 | .send_pulse = send_pulse_homebrew, |
83 | .send_space = send_space_homebrew, | |
b66db53f SY |
84 | .set_send_carrier = true, |
85 | .set_duty_cycle = true, | |
1beef3c1 JW |
86 | #endif |
87 | }, | |
88 | ||
b66db53f SY |
89 | [IR_IRDEO] = { |
90 | .lock = __SPIN_LOCK_UNLOCKED(hardware[IR_IRDEO].lock), | |
91 | .signal_pin = UART_MSR_DSR, | |
1beef3c1 JW |
92 | .signal_pin_change = UART_MSR_DDSR, |
93 | .on = UART_MCR_OUT2, | |
94 | .off = (UART_MCR_RTS | UART_MCR_DTR | UART_MCR_OUT2), | |
b66db53f SY |
95 | .send_pulse = send_pulse_irdeo, |
96 | .send_space = send_space_irdeo, | |
97 | .set_duty_cycle = true, | |
1beef3c1 JW |
98 | }, |
99 | ||
b66db53f SY |
100 | [IR_IRDEO_REMOTE] = { |
101 | .lock = __SPIN_LOCK_UNLOCKED(hardware[IR_IRDEO_REMOTE].lock), | |
102 | .signal_pin = UART_MSR_DSR, | |
1beef3c1 JW |
103 | .signal_pin_change = UART_MSR_DDSR, |
104 | .on = (UART_MCR_RTS | UART_MCR_DTR | UART_MCR_OUT2), | |
105 | .off = (UART_MCR_RTS | UART_MCR_DTR | UART_MCR_OUT2), | |
b66db53f SY |
106 | .send_pulse = send_pulse_irdeo, |
107 | .send_space = send_space_irdeo, | |
108 | .set_duty_cycle = true, | |
1beef3c1 JW |
109 | }, |
110 | ||
b66db53f SY |
111 | [IR_ANIMAX] = { |
112 | .lock = __SPIN_LOCK_UNLOCKED(hardware[IR_ANIMAX].lock), | |
113 | .signal_pin = UART_MSR_DCD, | |
1beef3c1 JW |
114 | .signal_pin_change = UART_MSR_DDCD, |
115 | .on = 0, | |
116 | .off = (UART_MCR_RTS | UART_MCR_DTR | UART_MCR_OUT2), | |
1beef3c1 JW |
117 | }, |
118 | ||
b66db53f SY |
119 | [IR_IGOR] = { |
120 | .lock = __SPIN_LOCK_UNLOCKED(hardware[IR_IGOR].lock), | |
121 | .signal_pin = UART_MSR_DSR, | |
1beef3c1 JW |
122 | .signal_pin_change = UART_MSR_DDSR, |
123 | .on = (UART_MCR_RTS | UART_MCR_OUT2 | UART_MCR_DTR), | |
124 | .off = (UART_MCR_RTS | UART_MCR_OUT2), | |
b66db53f | 125 | #ifdef CONFIG_IR_SERIAL_TRANSMITTER |
1beef3c1 JW |
126 | .send_pulse = send_pulse_homebrew, |
127 | .send_space = send_space_homebrew, | |
b66db53f SY |
128 | .set_send_carrier = true, |
129 | .set_duty_cycle = true, | |
1beef3c1 JW |
130 | #endif |
131 | }, | |
1beef3c1 JW |
132 | }; |
133 | ||
134 | #define RS_ISR_PASS_LIMIT 256 | |
135 | ||
b66db53f SY |
136 | struct serial_ir { |
137 | ktime_t lastkt; | |
138 | struct rc_dev *rcdev; | |
139 | struct platform_device *pdev; | |
2940c7e4 | 140 | struct timer_list timeout_timer; |
1beef3c1 | 141 | |
b66db53f SY |
142 | unsigned int freq; |
143 | unsigned int duty_cycle; | |
1beef3c1 | 144 | |
0a847634 | 145 | unsigned int pulse_width, space_width; |
b66db53f | 146 | }; |
1beef3c1 | 147 | |
b66db53f | 148 | static struct serial_ir serial_ir; |
1beef3c1 | 149 | |
1beef3c1 JW |
150 | /* fetch serial input packet (1 byte) from register offset */ |
151 | static u8 sinp(int offset) | |
152 | { | |
f3a9d7ef | 153 | if (iommap) |
1beef3c1 JW |
154 | /* the register is memory-mapped */ |
155 | offset <<= ioshift; | |
156 | ||
157 | return inb(io + offset); | |
158 | } | |
159 | ||
160 | /* write serial output packet (1 byte) of value to register offset */ | |
161 | static void soutp(int offset, u8 value) | |
162 | { | |
f3a9d7ef | 163 | if (iommap) |
1beef3c1 JW |
164 | /* the register is memory-mapped */ |
165 | offset <<= ioshift; | |
166 | ||
167 | outb(value, io + offset); | |
168 | } | |
169 | ||
170 | static void on(void) | |
171 | { | |
1beef3c1 JW |
172 | if (txsense) |
173 | soutp(UART_MCR, hardware[type].off); | |
174 | else | |
175 | soutp(UART_MCR, hardware[type].on); | |
176 | } | |
177 | ||
178 | static void off(void) | |
179 | { | |
1beef3c1 JW |
180 | if (txsense) |
181 | soutp(UART_MCR, hardware[type].on); | |
182 | else | |
183 | soutp(UART_MCR, hardware[type].off); | |
184 | } | |
185 | ||
0a847634 SY |
186 | static void init_timing_params(unsigned int new_duty_cycle, |
187 | unsigned int new_freq) | |
1beef3c1 | 188 | { |
b66db53f SY |
189 | serial_ir.duty_cycle = new_duty_cycle; |
190 | serial_ir.freq = new_freq; | |
1beef3c1 | 191 | |
0a847634 SY |
192 | serial_ir.pulse_width = DIV_ROUND_CLOSEST( |
193 | new_duty_cycle * NSEC_PER_SEC, new_freq * 100l); | |
194 | serial_ir.space_width = DIV_ROUND_CLOSEST( | |
195 | (100l - new_duty_cycle) * NSEC_PER_SEC, new_freq * 100l); | |
1beef3c1 | 196 | } |
1beef3c1 | 197 | |
0a847634 | 198 | static void send_pulse_irdeo(unsigned int length, ktime_t target) |
1beef3c1 | 199 | { |
0a847634 | 200 | long rawbits; |
1beef3c1 JW |
201 | int i; |
202 | unsigned char output; | |
203 | unsigned char chunk, shifted; | |
204 | ||
205 | /* how many bits have to be sent ? */ | |
206 | rawbits = length * 1152 / 10000; | |
b66db53f | 207 | if (serial_ir.duty_cycle > 50) |
1beef3c1 JW |
208 | chunk = 3; |
209 | else | |
210 | chunk = 1; | |
211 | for (i = 0, output = 0x7f; rawbits > 0; rawbits -= 3) { | |
212 | shifted = chunk << (i * 3); | |
213 | shifted >>= 1; | |
214 | output &= (~shifted); | |
215 | i++; | |
216 | if (i == 3) { | |
217 | soutp(UART_TX, output); | |
218 | while (!(sinp(UART_LSR) & UART_LSR_THRE)) | |
219 | ; | |
220 | output = 0x7f; | |
221 | i = 0; | |
222 | } | |
223 | } | |
224 | if (i != 0) { | |
225 | soutp(UART_TX, output); | |
226 | while (!(sinp(UART_LSR) & UART_LSR_TEMT)) | |
227 | ; | |
228 | } | |
1beef3c1 JW |
229 | } |
230 | ||
0a847634 | 231 | static void send_space_irdeo(void) |
b66db53f | 232 | { |
b66db53f SY |
233 | } |
234 | ||
235 | #ifdef CONFIG_IR_SERIAL_TRANSMITTER | |
0a847634 | 236 | static void send_pulse_homebrew_softcarrier(unsigned int length, ktime_t edge) |
1beef3c1 | 237 | { |
0a847634 SY |
238 | ktime_t now, target = ktime_add_us(edge, length); |
239 | /* | |
240 | * delta should never exceed 4 seconds and on m68k | |
241 | * ndelay(s64) does not compile; so use s32 rather than s64. | |
242 | */ | |
243 | s32 delta; | |
1beef3c1 | 244 | |
0a847634 SY |
245 | for (;;) { |
246 | now = ktime_get(); | |
247 | if (ktime_compare(now, target) >= 0) | |
248 | break; | |
249 | on(); | |
250 | edge = ktime_add_ns(edge, serial_ir.pulse_width); | |
251 | delta = ktime_to_ns(ktime_sub(edge, now)); | |
252 | if (delta > 0) | |
253 | ndelay(delta); | |
254 | now = ktime_get(); | |
255 | off(); | |
256 | if (ktime_compare(now, target) >= 0) | |
257 | break; | |
258 | edge = ktime_add_ns(edge, serial_ir.space_width); | |
259 | delta = ktime_to_ns(ktime_sub(edge, now)); | |
260 | if (delta > 0) | |
261 | ndelay(delta); | |
1beef3c1 | 262 | } |
1beef3c1 | 263 | } |
1beef3c1 | 264 | |
0a847634 | 265 | static void send_pulse_homebrew(unsigned int length, ktime_t edge) |
1beef3c1 | 266 | { |
1beef3c1 | 267 | if (softcarrier) |
0a847634 SY |
268 | send_pulse_homebrew_softcarrier(length, edge); |
269 | else | |
270 | on(); | |
1beef3c1 JW |
271 | } |
272 | ||
0a847634 | 273 | static void send_space_homebrew(void) |
1beef3c1 JW |
274 | { |
275 | off(); | |
1beef3c1 | 276 | } |
b66db53f | 277 | #endif |
1beef3c1 | 278 | |
b66db53f | 279 | static void frbwrite(unsigned int l, bool is_pulse) |
1beef3c1 JW |
280 | { |
281 | /* simple noise filter */ | |
b66db53f SY |
282 | static unsigned int ptr, pulse, space; |
283 | DEFINE_IR_RAW_EVENT(ev); | |
284 | ||
285 | if (ptr > 0 && is_pulse) { | |
286 | pulse += l; | |
287 | if (pulse > 250000) { | |
288 | ev.duration = space; | |
289 | ev.pulse = false; | |
290 | ir_raw_event_store_with_filter(serial_ir.rcdev, &ev); | |
291 | ev.duration = pulse; | |
292 | ev.pulse = true; | |
293 | ir_raw_event_store_with_filter(serial_ir.rcdev, &ev); | |
1beef3c1 JW |
294 | ptr = 0; |
295 | pulse = 0; | |
296 | } | |
297 | return; | |
298 | } | |
b66db53f | 299 | if (!is_pulse) { |
1beef3c1 | 300 | if (ptr == 0) { |
b66db53f | 301 | if (l > 20000000) { |
1beef3c1 JW |
302 | space = l; |
303 | ptr++; | |
304 | return; | |
305 | } | |
306 | } else { | |
b66db53f | 307 | if (l > 20000000) { |
1beef3c1 | 308 | space += pulse; |
b66db53f SY |
309 | if (space > IR_MAX_DURATION) |
310 | space = IR_MAX_DURATION; | |
1beef3c1 | 311 | space += l; |
b66db53f SY |
312 | if (space > IR_MAX_DURATION) |
313 | space = IR_MAX_DURATION; | |
1beef3c1 JW |
314 | pulse = 0; |
315 | return; | |
316 | } | |
b66db53f SY |
317 | |
318 | ev.duration = space; | |
319 | ev.pulse = false; | |
320 | ir_raw_event_store_with_filter(serial_ir.rcdev, &ev); | |
321 | ev.duration = pulse; | |
322 | ev.pulse = true; | |
323 | ir_raw_event_store_with_filter(serial_ir.rcdev, &ev); | |
1beef3c1 JW |
324 | ptr = 0; |
325 | pulse = 0; | |
326 | } | |
327 | } | |
b66db53f SY |
328 | |
329 | ev.duration = l; | |
330 | ev.pulse = is_pulse; | |
331 | ir_raw_event_store_with_filter(serial_ir.rcdev, &ev); | |
1beef3c1 JW |
332 | } |
333 | ||
b66db53f | 334 | static irqreturn_t serial_ir_irq_handler(int i, void *blah) |
1beef3c1 | 335 | { |
84595032 | 336 | ktime_t kt; |
1beef3c1 JW |
337 | int counter, dcd; |
338 | u8 status; | |
84595032 | 339 | ktime_t delkt; |
b66db53f | 340 | unsigned int data; |
1beef3c1 JW |
341 | static int last_dcd = -1; |
342 | ||
343 | if ((sinp(UART_IIR) & UART_IIR_NO_INT)) { | |
344 | /* not our interrupt */ | |
345 | return IRQ_NONE; | |
346 | } | |
347 | ||
348 | counter = 0; | |
349 | do { | |
350 | counter++; | |
351 | status = sinp(UART_MSR); | |
352 | if (counter > RS_ISR_PASS_LIMIT) { | |
b66db53f | 353 | dev_err(&serial_ir.pdev->dev, "Trapped in interrupt"); |
1beef3c1 JW |
354 | break; |
355 | } | |
a6f6ad41 MCC |
356 | if ((status & hardware[type].signal_pin_change) && |
357 | sense != -1) { | |
1beef3c1 | 358 | /* get current time */ |
84595032 | 359 | kt = ktime_get(); |
1beef3c1 | 360 | |
1beef3c1 | 361 | /* |
b66db53f SY |
362 | * The driver needs to know if your receiver is |
363 | * active high or active low, or the space/pulse | |
364 | * sense could be inverted. | |
1beef3c1 JW |
365 | */ |
366 | ||
b66db53f | 367 | /* calc time since last interrupt in nanoseconds */ |
1beef3c1 JW |
368 | dcd = (status & hardware[type].signal_pin) ? 1 : 0; |
369 | ||
370 | if (dcd == last_dcd) { | |
b66db53f SY |
371 | dev_err(&serial_ir.pdev->dev, |
372 | "ignoring spike: %d %d %lldns %lldns\n", | |
373 | dcd, sense, ktime_to_ns(kt), | |
374 | ktime_to_ns(serial_ir.lastkt)); | |
1beef3c1 JW |
375 | continue; |
376 | } | |
377 | ||
b66db53f | 378 | delkt = ktime_sub(kt, serial_ir.lastkt); |
84595032 | 379 | if (ktime_compare(delkt, ktime_set(15, 0)) > 0) { |
b66db53f | 380 | data = IR_MAX_DURATION; /* really long time */ |
a6f6ad41 | 381 | if (!(dcd ^ sense)) { |
1beef3c1 | 382 | /* sanity check */ |
b66db53f SY |
383 | dev_err(&serial_ir.pdev->dev, |
384 | "dcd unexpected: %d %d %lldns %lldns\n", | |
385 | dcd, sense, ktime_to_ns(kt), | |
386 | ktime_to_ns(serial_ir.lastkt)); | |
1beef3c1 JW |
387 | /* |
388 | * detecting pulse while this | |
389 | * MUST be a space! | |
390 | */ | |
391 | sense = sense ? 0 : 1; | |
392 | } | |
a6f6ad41 | 393 | } else { |
b66db53f | 394 | data = ktime_to_ns(delkt); |
a6f6ad41 | 395 | } |
b66db53f SY |
396 | frbwrite(data, !(dcd ^ sense)); |
397 | serial_ir.lastkt = kt; | |
1beef3c1 | 398 | last_dcd = dcd; |
1beef3c1 JW |
399 | } |
400 | } while (!(sinp(UART_IIR) & UART_IIR_NO_INT)); /* still pending ? */ | |
2940c7e4 SY |
401 | |
402 | mod_timer(&serial_ir.timeout_timer, | |
403 | jiffies + nsecs_to_jiffies(serial_ir.rcdev->timeout)); | |
404 | ||
405 | ir_raw_event_handle(serial_ir.rcdev); | |
406 | ||
1beef3c1 JW |
407 | return IRQ_HANDLED; |
408 | } | |
409 | ||
1beef3c1 JW |
410 | static int hardware_init_port(void) |
411 | { | |
412 | u8 scratch, scratch2, scratch3; | |
413 | ||
414 | /* | |
415 | * This is a simple port existence test, borrowed from the autoconfig | |
c60b4088 | 416 | * function in drivers/tty/serial/8250/8250_port.c |
1beef3c1 JW |
417 | */ |
418 | scratch = sinp(UART_IER); | |
419 | soutp(UART_IER, 0); | |
420 | #ifdef __i386__ | |
421 | outb(0xff, 0x080); | |
422 | #endif | |
423 | scratch2 = sinp(UART_IER) & 0x0f; | |
424 | soutp(UART_IER, 0x0f); | |
425 | #ifdef __i386__ | |
426 | outb(0x00, 0x080); | |
427 | #endif | |
428 | scratch3 = sinp(UART_IER) & 0x0f; | |
429 | soutp(UART_IER, scratch); | |
430 | if (scratch2 != 0 || scratch3 != 0x0f) { | |
431 | /* we fail, there's nothing here */ | |
df4f07b5 | 432 | pr_err("port existence test failed, cannot continue\n"); |
9b98d606 | 433 | return -ENODEV; |
1beef3c1 JW |
434 | } |
435 | ||
1beef3c1 JW |
436 | /* Set DLAB 0. */ |
437 | soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB)); | |
438 | ||
439 | /* First of all, disable all interrupts */ | |
440 | soutp(UART_IER, sinp(UART_IER) & | |
a6f6ad41 | 441 | (~(UART_IER_MSI | UART_IER_RLSI | UART_IER_THRI | UART_IER_RDI))); |
1beef3c1 JW |
442 | |
443 | /* Clear registers. */ | |
444 | sinp(UART_LSR); | |
445 | sinp(UART_RX); | |
446 | sinp(UART_IIR); | |
447 | sinp(UART_MSR); | |
448 | ||
1beef3c1 JW |
449 | /* Set line for power source */ |
450 | off(); | |
451 | ||
452 | /* Clear registers again to be sure. */ | |
453 | sinp(UART_LSR); | |
454 | sinp(UART_RX); | |
455 | sinp(UART_IIR); | |
456 | sinp(UART_MSR); | |
457 | ||
458 | switch (type) { | |
b66db53f SY |
459 | case IR_IRDEO: |
460 | case IR_IRDEO_REMOTE: | |
1beef3c1 JW |
461 | /* setup port to 7N1 @ 115200 Baud */ |
462 | /* 7N1+start = 9 bits at 115200 ~ 3 bits at 38kHz */ | |
463 | ||
464 | /* Set DLAB 1. */ | |
465 | soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB); | |
466 | /* Set divisor to 1 => 115200 Baud */ | |
467 | soutp(UART_DLM, 0); | |
468 | soutp(UART_DLL, 1); | |
469 | /* Set DLAB 0 + 7N1 */ | |
470 | soutp(UART_LCR, UART_LCR_WLEN7); | |
471 | /* THR interrupt already disabled at this point */ | |
472 | break; | |
473 | default: | |
474 | break; | |
475 | } | |
476 | ||
477 | return 0; | |
478 | } | |
479 | ||
2940c7e4 SY |
480 | static void serial_ir_timeout(unsigned long arg) |
481 | { | |
482 | DEFINE_IR_RAW_EVENT(ev); | |
483 | ||
484 | ev.timeout = true; | |
485 | ev.duration = serial_ir.rcdev->timeout; | |
486 | ir_raw_event_store_with_filter(serial_ir.rcdev, &ev); | |
487 | ir_raw_event_handle(serial_ir.rcdev); | |
488 | } | |
489 | ||
0265634e SY |
490 | /* Needed by serial_ir_probe() */ |
491 | static int serial_ir_tx(struct rc_dev *dev, unsigned int *txbuf, | |
492 | unsigned int count); | |
493 | static int serial_ir_tx_duty_cycle(struct rc_dev *dev, u32 cycle); | |
494 | static int serial_ir_tx_carrier(struct rc_dev *dev, u32 carrier); | |
495 | static int serial_ir_open(struct rc_dev *rcdev); | |
496 | static void serial_ir_close(struct rc_dev *rcdev); | |
497 | ||
b66db53f | 498 | static int serial_ir_probe(struct platform_device *dev) |
1beef3c1 | 499 | { |
0265634e | 500 | struct rc_dev *rcdev; |
c4b0afee JW |
501 | int i, nlow, nhigh, result; |
502 | ||
0265634e SY |
503 | rcdev = devm_rc_allocate_device(&dev->dev, RC_DRIVER_IR_RAW); |
504 | if (!rcdev) | |
505 | return -ENOMEM; | |
506 | ||
507 | if (hardware[type].send_pulse && hardware[type].send_space) | |
508 | rcdev->tx_ir = serial_ir_tx; | |
509 | if (hardware[type].set_send_carrier) | |
510 | rcdev->s_tx_carrier = serial_ir_tx_carrier; | |
511 | if (hardware[type].set_duty_cycle) | |
512 | rcdev->s_tx_duty_cycle = serial_ir_tx_duty_cycle; | |
513 | ||
514 | switch (type) { | |
515 | case IR_HOMEBREW: | |
516 | rcdev->input_name = "Serial IR type home-brew"; | |
517 | break; | |
518 | case IR_IRDEO: | |
519 | rcdev->input_name = "Serial IR type IRdeo"; | |
520 | break; | |
521 | case IR_IRDEO_REMOTE: | |
522 | rcdev->input_name = "Serial IR type IRdeo remote"; | |
523 | break; | |
524 | case IR_ANIMAX: | |
525 | rcdev->input_name = "Serial IR type AnimaX"; | |
526 | break; | |
527 | case IR_IGOR: | |
528 | rcdev->input_name = "Serial IR type IgorPlug"; | |
529 | break; | |
530 | } | |
531 | ||
532 | rcdev->input_phys = KBUILD_MODNAME "/input0"; | |
533 | rcdev->input_id.bustype = BUS_HOST; | |
534 | rcdev->input_id.vendor = 0x0001; | |
535 | rcdev->input_id.product = 0x0001; | |
536 | rcdev->input_id.version = 0x0100; | |
537 | rcdev->open = serial_ir_open; | |
538 | rcdev->close = serial_ir_close; | |
539 | rcdev->dev.parent = &serial_ir.pdev->dev; | |
540 | rcdev->allowed_protocols = RC_BIT_ALL_IR_DECODER; | |
541 | rcdev->driver_name = KBUILD_MODNAME; | |
542 | rcdev->map_name = RC_MAP_RC6_MCE; | |
543 | rcdev->min_timeout = 1; | |
544 | rcdev->timeout = IR_DEFAULT_TIMEOUT; | |
545 | rcdev->max_timeout = 10 * IR_DEFAULT_TIMEOUT; | |
546 | rcdev->rx_resolution = 250000; | |
547 | ||
548 | serial_ir.rcdev = rcdev; | |
549 | ||
550 | setup_timer(&serial_ir.timeout_timer, serial_ir_timeout, | |
551 | (unsigned long)&serial_ir); | |
552 | ||
b66db53f SY |
553 | result = devm_request_irq(&dev->dev, irq, serial_ir_irq_handler, |
554 | share_irq ? IRQF_SHARED : 0, | |
555 | KBUILD_MODNAME, &hardware); | |
affc9a0d BH |
556 | if (result < 0) { |
557 | if (result == -EBUSY) | |
df4f07b5 | 558 | dev_err(&dev->dev, "IRQ %d busy\n", irq); |
affc9a0d | 559 | else if (result == -EINVAL) |
df4f07b5 | 560 | dev_err(&dev->dev, "Bad irq number or handler\n"); |
affc9a0d BH |
561 | return result; |
562 | } | |
1beef3c1 JW |
563 | |
564 | /* Reserve io region. */ | |
a6f6ad41 MCC |
565 | if ((iommap && |
566 | (devm_request_mem_region(&dev->dev, iommap, 8 << ioshift, | |
567 | KBUILD_MODNAME) == NULL)) || | |
568 | (!iommap && (devm_request_region(&dev->dev, io, 8, | |
569 | KBUILD_MODNAME) == NULL))) { | |
df4f07b5 YT |
570 | dev_err(&dev->dev, "port %04x already in use\n", io); |
571 | dev_warn(&dev->dev, "use 'setserial /dev/ttySX uart none'\n"); | |
572 | dev_warn(&dev->dev, | |
573 | "or compile the serial port driver as module and\n"); | |
574 | dev_warn(&dev->dev, "make sure this module is loaded first\n"); | |
56a65a1e | 575 | return -EBUSY; |
1beef3c1 JW |
576 | } |
577 | ||
9b98d606 BH |
578 | result = hardware_init_port(); |
579 | if (result < 0) | |
56a65a1e | 580 | return result; |
1beef3c1 JW |
581 | |
582 | /* Initialize pulse/space widths */ | |
b66db53f | 583 | init_timing_params(50, 38000); |
1beef3c1 JW |
584 | |
585 | /* If pin is high, then this must be an active low receiver. */ | |
586 | if (sense == -1) { | |
587 | /* wait 1/2 sec for the power supply */ | |
588 | msleep(500); | |
589 | ||
590 | /* | |
591 | * probe 9 times every 0.04s, collect "votes" for | |
592 | * active high/low | |
593 | */ | |
594 | nlow = 0; | |
595 | nhigh = 0; | |
596 | for (i = 0; i < 9; i++) { | |
597 | if (sinp(UART_MSR) & hardware[type].signal_pin) | |
598 | nlow++; | |
599 | else | |
600 | nhigh++; | |
601 | msleep(40); | |
602 | } | |
8126e17f | 603 | sense = nlow >= nhigh ? 1 : 0; |
df4f07b5 YT |
604 | dev_info(&dev->dev, "auto-detected active %s receiver\n", |
605 | sense ? "low" : "high"); | |
1beef3c1 | 606 | } else |
df4f07b5 YT |
607 | dev_info(&dev->dev, "Manually using active %s receiver\n", |
608 | sense ? "low" : "high"); | |
1beef3c1 | 609 | |
4b4c7a19 | 610 | dev_dbg(&dev->dev, "Interrupt %d, port %04x obtained\n", irq, io); |
0265634e SY |
611 | |
612 | return devm_rc_register_device(&dev->dev, rcdev); | |
1beef3c1 JW |
613 | } |
614 | ||
b66db53f | 615 | static int serial_ir_open(struct rc_dev *rcdev) |
1beef3c1 | 616 | { |
1beef3c1 JW |
617 | unsigned long flags; |
618 | ||
619 | /* initialize timestamp */ | |
b66db53f | 620 | serial_ir.lastkt = ktime_get(); |
1beef3c1 | 621 | |
1beef3c1 JW |
622 | spin_lock_irqsave(&hardware[type].lock, flags); |
623 | ||
624 | /* Set DLAB 0. */ | |
625 | soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB)); | |
626 | ||
a6f6ad41 | 627 | soutp(UART_IER, sinp(UART_IER) | UART_IER_MSI); |
1beef3c1 JW |
628 | |
629 | spin_unlock_irqrestore(&hardware[type].lock, flags); | |
630 | ||
631 | return 0; | |
632 | } | |
633 | ||
b66db53f SY |
634 | static void serial_ir_close(struct rc_dev *rcdev) |
635 | { | |
636 | unsigned long flags; | |
1beef3c1 JW |
637 | |
638 | spin_lock_irqsave(&hardware[type].lock, flags); | |
639 | ||
640 | /* Set DLAB 0. */ | |
641 | soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB)); | |
642 | ||
643 | /* First of all, disable all interrupts */ | |
644 | soutp(UART_IER, sinp(UART_IER) & | |
a6f6ad41 | 645 | (~(UART_IER_MSI | UART_IER_RLSI | UART_IER_THRI | UART_IER_RDI))); |
1beef3c1 | 646 | spin_unlock_irqrestore(&hardware[type].lock, flags); |
1beef3c1 JW |
647 | } |
648 | ||
b66db53f SY |
649 | static int serial_ir_tx(struct rc_dev *dev, unsigned int *txbuf, |
650 | unsigned int count) | |
1beef3c1 | 651 | { |
1beef3c1 | 652 | unsigned long flags; |
0a847634 SY |
653 | ktime_t edge; |
654 | s64 delta; | |
b66db53f | 655 | int i; |
1beef3c1 | 656 | |
1beef3c1 | 657 | spin_lock_irqsave(&hardware[type].lock, flags); |
b66db53f | 658 | if (type == IR_IRDEO) { |
1beef3c1 JW |
659 | /* DTR, RTS down */ |
660 | on(); | |
661 | } | |
0a847634 SY |
662 | |
663 | edge = ktime_get(); | |
1beef3c1 | 664 | for (i = 0; i < count; i++) { |
a6f6ad41 | 665 | if (i % 2) |
0a847634 | 666 | hardware[type].send_space(); |
1beef3c1 | 667 | else |
0a847634 SY |
668 | hardware[type].send_pulse(txbuf[i], edge); |
669 | ||
670 | edge = ktime_add_us(edge, txbuf[i]); | |
671 | delta = ktime_us_delta(edge, ktime_get()); | |
672 | if (delta > 25) { | |
673 | spin_unlock_irqrestore(&hardware[type].lock, flags); | |
674 | usleep_range(delta - 25, delta + 25); | |
675 | spin_lock_irqsave(&hardware[type].lock, flags); | |
a6f6ad41 | 676 | } else if (delta > 0) { |
0a847634 | 677 | udelay(delta); |
a6f6ad41 | 678 | } |
1beef3c1 JW |
679 | } |
680 | off(); | |
681 | spin_unlock_irqrestore(&hardware[type].lock, flags); | |
b66db53f | 682 | return count; |
1beef3c1 JW |
683 | } |
684 | ||
b66db53f | 685 | static int serial_ir_tx_duty_cycle(struct rc_dev *dev, u32 cycle) |
1beef3c1 | 686 | { |
0a847634 SY |
687 | init_timing_params(cycle, serial_ir.freq); |
688 | return 0; | |
1beef3c1 JW |
689 | } |
690 | ||
b66db53f SY |
691 | static int serial_ir_tx_carrier(struct rc_dev *dev, u32 carrier) |
692 | { | |
693 | if (carrier > 500000 || carrier < 20000) | |
694 | return -EINVAL; | |
1beef3c1 | 695 | |
0a847634 SY |
696 | init_timing_params(serial_ir.duty_cycle, carrier); |
697 | return 0; | |
b66db53f | 698 | } |
1beef3c1 | 699 | |
b66db53f SY |
700 | static int serial_ir_suspend(struct platform_device *dev, |
701 | pm_message_t state) | |
1beef3c1 JW |
702 | { |
703 | /* Set DLAB 0. */ | |
704 | soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB)); | |
705 | ||
706 | /* Disable all interrupts */ | |
707 | soutp(UART_IER, sinp(UART_IER) & | |
a6f6ad41 | 708 | (~(UART_IER_MSI | UART_IER_RLSI | UART_IER_THRI | UART_IER_RDI))); |
1beef3c1 JW |
709 | |
710 | /* Clear registers. */ | |
711 | sinp(UART_LSR); | |
712 | sinp(UART_RX); | |
713 | sinp(UART_IIR); | |
714 | sinp(UART_MSR); | |
715 | ||
716 | return 0; | |
717 | } | |
718 | ||
b66db53f | 719 | static int serial_ir_resume(struct platform_device *dev) |
1beef3c1 JW |
720 | { |
721 | unsigned long flags; | |
9b98d606 | 722 | int result; |
1beef3c1 | 723 | |
9b98d606 BH |
724 | result = hardware_init_port(); |
725 | if (result < 0) | |
726 | return result; | |
1beef3c1 JW |
727 | |
728 | spin_lock_irqsave(&hardware[type].lock, flags); | |
729 | /* Enable Interrupt */ | |
b66db53f | 730 | serial_ir.lastkt = ktime_get(); |
a6f6ad41 | 731 | soutp(UART_IER, sinp(UART_IER) | UART_IER_MSI); |
1beef3c1 JW |
732 | off(); |
733 | ||
1beef3c1 JW |
734 | spin_unlock_irqrestore(&hardware[type].lock, flags); |
735 | ||
736 | return 0; | |
737 | } | |
738 | ||
b66db53f SY |
739 | static struct platform_driver serial_ir_driver = { |
740 | .probe = serial_ir_probe, | |
741 | .suspend = serial_ir_suspend, | |
742 | .resume = serial_ir_resume, | |
1beef3c1 | 743 | .driver = { |
b66db53f | 744 | .name = "serial_ir", |
1beef3c1 JW |
745 | }, |
746 | }; | |
747 | ||
b66db53f | 748 | static int __init serial_ir_init(void) |
1beef3c1 JW |
749 | { |
750 | int result; | |
751 | ||
b66db53f SY |
752 | result = platform_driver_register(&serial_ir_driver); |
753 | if (result) | |
9b98d606 | 754 | return result; |
1beef3c1 | 755 | |
b66db53f SY |
756 | serial_ir.pdev = platform_device_alloc("serial_ir", 0); |
757 | if (!serial_ir.pdev) { | |
1beef3c1 JW |
758 | result = -ENOMEM; |
759 | goto exit_driver_unregister; | |
760 | } | |
761 | ||
b66db53f | 762 | result = platform_device_add(serial_ir.pdev); |
1beef3c1 JW |
763 | if (result) |
764 | goto exit_device_put; | |
765 | ||
766 | return 0; | |
767 | ||
768 | exit_device_put: | |
b66db53f | 769 | platform_device_put(serial_ir.pdev); |
1beef3c1 | 770 | exit_driver_unregister: |
b66db53f | 771 | platform_driver_unregister(&serial_ir_driver); |
1beef3c1 JW |
772 | return result; |
773 | } | |
774 | ||
b66db53f | 775 | static void serial_ir_exit(void) |
1beef3c1 | 776 | { |
b66db53f SY |
777 | platform_device_unregister(serial_ir.pdev); |
778 | platform_driver_unregister(&serial_ir_driver); | |
1beef3c1 JW |
779 | } |
780 | ||
b66db53f | 781 | static int __init serial_ir_init_module(void) |
1beef3c1 JW |
782 | { |
783 | int result; | |
784 | ||
1beef3c1 | 785 | switch (type) { |
b66db53f SY |
786 | case IR_HOMEBREW: |
787 | case IR_IRDEO: | |
788 | case IR_IRDEO_REMOTE: | |
789 | case IR_ANIMAX: | |
790 | case IR_IGOR: | |
1beef3c1 JW |
791 | /* if nothing specified, use ttyS0/com1 and irq 4 */ |
792 | io = io ? io : 0x3f8; | |
793 | irq = irq ? irq : 4; | |
794 | break; | |
1beef3c1 | 795 | default: |
9105b8b2 | 796 | return -EINVAL; |
1beef3c1 JW |
797 | } |
798 | if (!softcarrier) { | |
799 | switch (type) { | |
b66db53f SY |
800 | case IR_HOMEBREW: |
801 | case IR_IGOR: | |
802 | hardware[type].set_send_carrier = false; | |
803 | hardware[type].set_duty_cycle = false; | |
1beef3c1 JW |
804 | break; |
805 | } | |
806 | } | |
807 | ||
895507c1 PB |
808 | /* make sure sense is either -1, 0, or 1 */ |
809 | if (sense != -1) | |
810 | sense = !!sense; | |
811 | ||
b66db53f | 812 | result = serial_ir_init(); |
b66db53f SY |
813 | if (!result) |
814 | return 0; | |
0265634e | 815 | |
b66db53f SY |
816 | serial_ir_exit(); |
817 | return result; | |
1beef3c1 JW |
818 | } |
819 | ||
b66db53f | 820 | static void __exit serial_ir_exit_module(void) |
1beef3c1 | 821 | { |
2940c7e4 | 822 | del_timer_sync(&serial_ir.timeout_timer); |
b66db53f | 823 | serial_ir_exit(); |
1beef3c1 JW |
824 | } |
825 | ||
b66db53f SY |
826 | module_init(serial_ir_init_module); |
827 | module_exit(serial_ir_exit_module); | |
1beef3c1 JW |
828 | |
829 | MODULE_DESCRIPTION("Infra-red receiver driver for serial ports."); | |
b66db53f | 830 | MODULE_AUTHOR("Ralph Metzler, Trent Piepho, Ben Pfaff, Christoph Bartelmus, Andrei Tanas"); |
1beef3c1 JW |
831 | MODULE_LICENSE("GPL"); |
832 | ||
b66db53f SY |
833 | module_param(type, int, 0444); |
834 | MODULE_PARM_DESC(type, "Hardware type (0 = home-brew, 1 = IRdeo, 2 = IRdeo Remote, 3 = AnimaX, 4 = IgorPlug"); | |
1beef3c1 | 835 | |
5a8fc6a3 | 836 | module_param_hw(io, int, ioport, 0444); |
1beef3c1 JW |
837 | MODULE_PARM_DESC(io, "I/O address base (0x3f8 or 0x2f8)"); |
838 | ||
839 | /* some architectures (e.g. intel xscale) have memory mapped registers */ | |
5a8fc6a3 | 840 | module_param_hw(iommap, bool, other, 0444); |
b66db53f | 841 | MODULE_PARM_DESC(iommap, "physical base for memory mapped I/O (0 = no memory mapped io)"); |
1beef3c1 JW |
842 | |
843 | /* | |
844 | * some architectures (e.g. intel xscale) align the 8bit serial registers | |
845 | * on 32bit word boundaries. | |
b47acf2a | 846 | * See linux-kernel/drivers/tty/serial/8250/8250.c serial_in()/out() |
1beef3c1 | 847 | */ |
5a8fc6a3 | 848 | module_param_hw(ioshift, int, other, 0444); |
1beef3c1 JW |
849 | MODULE_PARM_DESC(ioshift, "shift I/O register offset (0 = no shift)"); |
850 | ||
5a8fc6a3 | 851 | module_param_hw(irq, int, irq, 0444); |
1beef3c1 JW |
852 | MODULE_PARM_DESC(irq, "Interrupt (4 or 3)"); |
853 | ||
5a8fc6a3 | 854 | module_param_hw(share_irq, bool, other, 0444); |
1beef3c1 JW |
855 | MODULE_PARM_DESC(share_irq, "Share interrupts (0 = off, 1 = on)"); |
856 | ||
b66db53f SY |
857 | module_param(sense, int, 0444); |
858 | MODULE_PARM_DESC(sense, "Override autodetection of IR receiver circuit (0 = active high, 1 = active low )"); | |
1beef3c1 | 859 | |
b66db53f SY |
860 | #ifdef CONFIG_IR_SERIAL_TRANSMITTER |
861 | module_param(txsense, bool, 0444); | |
862 | MODULE_PARM_DESC(txsense, "Sense of transmitter circuit (0 = active high, 1 = active low )"); | |
1beef3c1 JW |
863 | #endif |
864 | ||
b66db53f | 865 | module_param(softcarrier, bool, 0444); |
1beef3c1 | 866 | MODULE_PARM_DESC(softcarrier, "Software carrier (0 = off, 1 = on, default on)"); |