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c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
e258b80e DH |
2 | /* |
3 | * winbond-cir.c - Driver for the Consumer IR functionality of Winbond | |
4 | * SuperI/O chips. | |
5 | * | |
6 | * Currently supports the Winbond WPCD376i chip (PNP id WEC1022), but | |
7 | * could probably support others (Winbond WEC102X, NatSemi, etc) | |
8 | * with minor modifications. | |
9 | * | |
b87f2edd | 10 | * Original Author: David Härdeman <david@hardeman.nu> |
37b0b4e9 | 11 | * Copyright (C) 2012 Sean Young <sean@mess.org> |
b87f2edd | 12 | * Copyright (C) 2009 - 2011 David Härdeman <david@hardeman.nu> |
e258b80e | 13 | * |
5b2e303f DH |
14 | * Dedicated to my daughter Matilda, without whose loving attention this |
15 | * driver would have been finished in half the time and with a fraction | |
e258b80e DH |
16 | * of the bugs. |
17 | * | |
18 | * Written using: | |
19 | * o Winbond WPCD376I datasheet helpfully provided by Jesse Barnes at Intel | |
20 | * o NatSemi PC87338/PC97338 datasheet (for the serial port stuff) | |
21 | * o DSDT dumps | |
22 | * | |
23 | * Supported features: | |
c829f267 DH |
24 | * o IR Receive |
25 | * o IR Transmit | |
e258b80e | 26 | * o Wake-On-CIR functionality |
37b0b4e9 | 27 | * o Carrier detection |
e258b80e DH |
28 | */ |
29 | ||
d8a10ac9 JP |
30 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
31 | ||
e258b80e DH |
32 | #include <linux/module.h> |
33 | #include <linux/pnp.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/timer.h> | |
e258b80e | 36 | #include <linux/leds.h> |
e258b80e DH |
37 | #include <linux/spinlock.h> |
38 | #include <linux/pci_ids.h> | |
39 | #include <linux/io.h> | |
40 | #include <linux/bitrev.h> | |
5a0e3ad6 | 41 | #include <linux/slab.h> |
c829f267 DH |
42 | #include <linux/wait.h> |
43 | #include <linux/sched.h> | |
6bda9644 | 44 | #include <media/rc-core.h> |
e258b80e DH |
45 | |
46 | #define DRVNAME "winbond-cir" | |
47 | ||
48 | /* CEIR Wake-Up Registers, relative to data->wbase */ | |
49 | #define WBCIR_REG_WCEIR_CTL 0x03 /* CEIR Receiver Control */ | |
50 | #define WBCIR_REG_WCEIR_STS 0x04 /* CEIR Receiver Status */ | |
51 | #define WBCIR_REG_WCEIR_EV_EN 0x05 /* CEIR Receiver Event Enable */ | |
52 | #define WBCIR_REG_WCEIR_CNTL 0x06 /* CEIR Receiver Counter Low */ | |
53 | #define WBCIR_REG_WCEIR_CNTH 0x07 /* CEIR Receiver Counter High */ | |
54 | #define WBCIR_REG_WCEIR_INDEX 0x08 /* CEIR Receiver Index */ | |
55 | #define WBCIR_REG_WCEIR_DATA 0x09 /* CEIR Receiver Data */ | |
56 | #define WBCIR_REG_WCEIR_CSL 0x0A /* CEIR Re. Compare Strlen */ | |
57 | #define WBCIR_REG_WCEIR_CFG1 0x0B /* CEIR Re. Configuration 1 */ | |
58 | #define WBCIR_REG_WCEIR_CFG2 0x0C /* CEIR Re. Configuration 2 */ | |
59 | ||
60 | /* CEIR Enhanced Functionality Registers, relative to data->ebase */ | |
61 | #define WBCIR_REG_ECEIR_CTS 0x00 /* Enhanced IR Control Status */ | |
62 | #define WBCIR_REG_ECEIR_CCTL 0x01 /* Infrared Counter Control */ | |
63 | #define WBCIR_REG_ECEIR_CNT_LO 0x02 /* Infrared Counter LSB */ | |
64 | #define WBCIR_REG_ECEIR_CNT_HI 0x03 /* Infrared Counter MSB */ | |
65 | #define WBCIR_REG_ECEIR_IREM 0x04 /* Infrared Emitter Status */ | |
66 | ||
67 | /* SP3 Banked Registers, relative to data->sbase */ | |
68 | #define WBCIR_REG_SP3_BSR 0x03 /* Bank Select, all banks */ | |
69 | /* Bank 0 */ | |
70 | #define WBCIR_REG_SP3_RXDATA 0x00 /* FIFO RX data (r) */ | |
71 | #define WBCIR_REG_SP3_TXDATA 0x00 /* FIFO TX data (w) */ | |
72 | #define WBCIR_REG_SP3_IER 0x01 /* Interrupt Enable */ | |
73 | #define WBCIR_REG_SP3_EIR 0x02 /* Event Identification (r) */ | |
74 | #define WBCIR_REG_SP3_FCR 0x02 /* FIFO Control (w) */ | |
75 | #define WBCIR_REG_SP3_MCR 0x04 /* Mode Control */ | |
76 | #define WBCIR_REG_SP3_LSR 0x05 /* Link Status */ | |
77 | #define WBCIR_REG_SP3_MSR 0x06 /* Modem Status */ | |
78 | #define WBCIR_REG_SP3_ASCR 0x07 /* Aux Status and Control */ | |
79 | /* Bank 2 */ | |
80 | #define WBCIR_REG_SP3_BGDL 0x00 /* Baud Divisor LSB */ | |
81 | #define WBCIR_REG_SP3_BGDH 0x01 /* Baud Divisor MSB */ | |
82 | #define WBCIR_REG_SP3_EXCR1 0x02 /* Extended Control 1 */ | |
83 | #define WBCIR_REG_SP3_EXCR2 0x04 /* Extended Control 2 */ | |
84 | #define WBCIR_REG_SP3_TXFLV 0x06 /* TX FIFO Level */ | |
85 | #define WBCIR_REG_SP3_RXFLV 0x07 /* RX FIFO Level */ | |
86 | /* Bank 3 */ | |
87 | #define WBCIR_REG_SP3_MRID 0x00 /* Module Identification */ | |
88 | #define WBCIR_REG_SP3_SH_LCR 0x01 /* LCR Shadow */ | |
89 | #define WBCIR_REG_SP3_SH_FCR 0x02 /* FCR Shadow */ | |
90 | /* Bank 4 */ | |
91 | #define WBCIR_REG_SP3_IRCR1 0x02 /* Infrared Control 1 */ | |
92 | /* Bank 5 */ | |
93 | #define WBCIR_REG_SP3_IRCR2 0x04 /* Infrared Control 2 */ | |
94 | /* Bank 6 */ | |
95 | #define WBCIR_REG_SP3_IRCR3 0x00 /* Infrared Control 3 */ | |
5b2e303f | 96 | #define WBCIR_REG_SP3_SIR_PW 0x02 /* SIR Pulse Width */ |
e258b80e DH |
97 | /* Bank 7 */ |
98 | #define WBCIR_REG_SP3_IRRXDC 0x00 /* IR RX Demod Control */ | |
99 | #define WBCIR_REG_SP3_IRTXMC 0x01 /* IR TX Mod Control */ | |
100 | #define WBCIR_REG_SP3_RCCFG 0x02 /* CEIR Config */ | |
101 | #define WBCIR_REG_SP3_IRCFG1 0x04 /* Infrared Config 1 */ | |
102 | #define WBCIR_REG_SP3_IRCFG4 0x07 /* Infrared Config 4 */ | |
103 | ||
104 | /* | |
105 | * Magic values follow | |
106 | */ | |
107 | ||
108 | /* No interrupts for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ | |
109 | #define WBCIR_IRQ_NONE 0x00 | |
110 | /* RX data bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ | |
111 | #define WBCIR_IRQ_RX 0x01 | |
c829f267 DH |
112 | /* TX data low bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ |
113 | #define WBCIR_IRQ_TX_LOW 0x02 | |
e258b80e DH |
114 | /* Over/Under-flow bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ |
115 | #define WBCIR_IRQ_ERR 0x04 | |
c829f267 DH |
116 | /* TX data empty bit for WBCEIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ |
117 | #define WBCIR_IRQ_TX_EMPTY 0x20 | |
e258b80e DH |
118 | /* Led enable/disable bit for WBCIR_REG_ECEIR_CTS */ |
119 | #define WBCIR_LED_ENABLE 0x80 | |
120 | /* RX data available bit for WBCIR_REG_SP3_LSR */ | |
121 | #define WBCIR_RX_AVAIL 0x01 | |
c829f267 DH |
122 | /* RX data overrun error bit for WBCIR_REG_SP3_LSR */ |
123 | #define WBCIR_RX_OVERRUN 0x02 | |
124 | /* TX End-Of-Transmission bit for WBCIR_REG_SP3_ASCR */ | |
125 | #define WBCIR_TX_EOT 0x04 | |
e258b80e DH |
126 | /* RX disable bit for WBCIR_REG_SP3_ASCR */ |
127 | #define WBCIR_RX_DISABLE 0x20 | |
c829f267 DH |
128 | /* TX data underrun error bit for WBCIR_REG_SP3_ASCR */ |
129 | #define WBCIR_TX_UNDERRUN 0x40 | |
e258b80e DH |
130 | /* Extended mode enable bit for WBCIR_REG_SP3_EXCR1 */ |
131 | #define WBCIR_EXT_ENABLE 0x01 | |
132 | /* Select compare register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */ | |
133 | #define WBCIR_REGSEL_COMPARE 0x10 | |
134 | /* Select mask register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */ | |
135 | #define WBCIR_REGSEL_MASK 0x20 | |
136 | /* Starting address of selected register in WBCIR_REG_WCEIR_INDEX */ | |
137 | #define WBCIR_REG_ADDR0 0x00 | |
37b0b4e9 SY |
138 | /* Enable carrier counter */ |
139 | #define WBCIR_CNTR_EN 0x01 | |
140 | /* Reset carrier counter */ | |
141 | #define WBCIR_CNTR_R 0x02 | |
142 | /* Invert TX */ | |
143 | #define WBCIR_IRTX_INV 0x04 | |
6f2627c2 SY |
144 | /* Receiver oversampling */ |
145 | #define WBCIR_RX_T_OV 0x40 | |
e258b80e DH |
146 | |
147 | /* Valid banks for the SP3 UART */ | |
148 | enum wbcir_bank { | |
149 | WBCIR_BANK_0 = 0x00, | |
150 | WBCIR_BANK_1 = 0x80, | |
151 | WBCIR_BANK_2 = 0xE0, | |
152 | WBCIR_BANK_3 = 0xE4, | |
153 | WBCIR_BANK_4 = 0xE8, | |
154 | WBCIR_BANK_5 = 0xEC, | |
155 | WBCIR_BANK_6 = 0xF0, | |
156 | WBCIR_BANK_7 = 0xF4, | |
157 | }; | |
158 | ||
5b2e303f | 159 | /* Supported power-on IR Protocols */ |
e258b80e DH |
160 | enum wbcir_protocol { |
161 | IR_PROTOCOL_RC5 = 0x0, | |
162 | IR_PROTOCOL_NEC = 0x1, | |
163 | IR_PROTOCOL_RC6 = 0x2, | |
164 | }; | |
165 | ||
c829f267 DH |
166 | /* Possible states for IR reception */ |
167 | enum wbcir_rxstate { | |
168 | WBCIR_RXSTATE_INACTIVE = 0, | |
169 | WBCIR_RXSTATE_ACTIVE, | |
170 | WBCIR_RXSTATE_ERROR | |
171 | }; | |
172 | ||
173 | /* Possible states for IR transmission */ | |
174 | enum wbcir_txstate { | |
175 | WBCIR_TXSTATE_INACTIVE = 0, | |
176 | WBCIR_TXSTATE_ACTIVE, | |
c829f267 DH |
177 | WBCIR_TXSTATE_ERROR |
178 | }; | |
179 | ||
e258b80e | 180 | /* Misc */ |
a66cd0b6 | 181 | #define WBCIR_NAME "Winbond CIR" |
e258b80e DH |
182 | #define WBCIR_ID_FAMILY 0xF1 /* Family ID for the WPCD376I */ |
183 | #define WBCIR_ID_CHIP 0x04 /* Chip ID for the WPCD376I */ | |
e258b80e DH |
184 | #define WAKEUP_IOMEM_LEN 0x10 /* Wake-Up I/O Reg Len */ |
185 | #define EHFUNC_IOMEM_LEN 0x10 /* Enhanced Func I/O Reg Len */ | |
186 | #define SP_IOMEM_LEN 0x08 /* Serial Port 3 (IR) Reg Len */ | |
e258b80e | 187 | |
5b2e303f | 188 | /* Per-device data */ |
e258b80e | 189 | struct wbcir_data { |
5b2e303f | 190 | spinlock_t spinlock; |
c829f267 DH |
191 | struct rc_dev *dev; |
192 | struct led_classdev led; | |
5b2e303f | 193 | |
e258b80e DH |
194 | unsigned long wbase; /* Wake-Up Baseaddr */ |
195 | unsigned long ebase; /* Enhanced Func. Baseaddr */ | |
196 | unsigned long sbase; /* Serial Port Baseaddr */ | |
197 | unsigned int irq; /* Serial Port IRQ */ | |
c829f267 | 198 | u8 irqmask; |
e258b80e | 199 | |
c829f267 DH |
200 | /* RX state */ |
201 | enum wbcir_rxstate rxstate; | |
37b0b4e9 SY |
202 | int carrier_report_enabled; |
203 | u32 pulse_duration; | |
e258b80e | 204 | |
c829f267 DH |
205 | /* TX state */ |
206 | enum wbcir_txstate txstate; | |
c829f267 DH |
207 | u32 txlen; |
208 | u32 txoff; | |
209 | u32 *txbuf; | |
c829f267 DH |
210 | u8 txmask; |
211 | u32 txcarrier; | |
e258b80e DH |
212 | }; |
213 | ||
90ab5ee9 | 214 | static bool invert; /* default = 0 */ |
e258b80e DH |
215 | module_param(invert, bool, 0444); |
216 | MODULE_PARM_DESC(invert, "Invert the signal from the IR receiver"); | |
217 | ||
90ab5ee9 | 218 | static bool txandrx; /* default = 0 */ |
c829f267 | 219 | module_param(txandrx, bool, 0444); |
57f4422f | 220 | MODULE_PARM_DESC(txandrx, "Allow simultaneous TX and RX"); |
c829f267 | 221 | |
e258b80e DH |
222 | |
223 | /***************************************************************************** | |
224 | * | |
225 | * UTILITY FUNCTIONS | |
226 | * | |
227 | *****************************************************************************/ | |
228 | ||
229 | /* Caller needs to hold wbcir_lock */ | |
230 | static void | |
231 | wbcir_set_bits(unsigned long addr, u8 bits, u8 mask) | |
232 | { | |
233 | u8 val; | |
234 | ||
235 | val = inb(addr); | |
236 | val = ((val & ~mask) | (bits & mask)); | |
237 | outb(val, addr); | |
238 | } | |
239 | ||
240 | /* Selects the register bank for the serial port */ | |
241 | static inline void | |
242 | wbcir_select_bank(struct wbcir_data *data, enum wbcir_bank bank) | |
243 | { | |
244 | outb(bank, data->sbase + WBCIR_REG_SP3_BSR); | |
245 | } | |
246 | ||
c829f267 DH |
247 | static inline void |
248 | wbcir_set_irqmask(struct wbcir_data *data, u8 irqmask) | |
249 | { | |
250 | if (data->irqmask == irqmask) | |
251 | return; | |
252 | ||
253 | wbcir_select_bank(data, WBCIR_BANK_0); | |
254 | outb(irqmask, data->sbase + WBCIR_REG_SP3_IER); | |
255 | data->irqmask = irqmask; | |
256 | } | |
257 | ||
e258b80e DH |
258 | static enum led_brightness |
259 | wbcir_led_brightness_get(struct led_classdev *led_cdev) | |
260 | { | |
261 | struct wbcir_data *data = container_of(led_cdev, | |
262 | struct wbcir_data, | |
263 | led); | |
264 | ||
265 | if (inb(data->ebase + WBCIR_REG_ECEIR_CTS) & WBCIR_LED_ENABLE) | |
266 | return LED_FULL; | |
267 | else | |
268 | return LED_OFF; | |
269 | } | |
270 | ||
271 | static void | |
272 | wbcir_led_brightness_set(struct led_classdev *led_cdev, | |
5b2e303f | 273 | enum led_brightness brightness) |
e258b80e DH |
274 | { |
275 | struct wbcir_data *data = container_of(led_cdev, | |
276 | struct wbcir_data, | |
277 | led); | |
278 | ||
279 | wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS, | |
280 | brightness == LED_OFF ? 0x00 : WBCIR_LED_ENABLE, | |
281 | WBCIR_LED_ENABLE); | |
282 | } | |
283 | ||
5b2e303f | 284 | /* Manchester encodes bits to RC6 message cells (see wbcir_shutdown) */ |
e258b80e DH |
285 | static u8 |
286 | wbcir_to_rc6cells(u8 val) | |
287 | { | |
288 | u8 coded = 0x00; | |
289 | int i; | |
290 | ||
291 | val &= 0x0F; | |
292 | for (i = 0; i < 4; i++) { | |
293 | if (val & 0x01) | |
294 | coded |= 0x02 << (i * 2); | |
295 | else | |
296 | coded |= 0x01 << (i * 2); | |
297 | val >>= 1; | |
298 | } | |
299 | ||
300 | return coded; | |
301 | } | |
302 | ||
e258b80e DH |
303 | /***************************************************************************** |
304 | * | |
305 | * INTERRUPT FUNCTIONS | |
306 | * | |
307 | *****************************************************************************/ | |
308 | ||
37b0b4e9 SY |
309 | static void |
310 | wbcir_carrier_report(struct wbcir_data *data) | |
311 | { | |
312 | unsigned counter = inb(data->ebase + WBCIR_REG_ECEIR_CNT_LO) | | |
313 | inb(data->ebase + WBCIR_REG_ECEIR_CNT_HI) << 8; | |
314 | ||
315 | if (counter > 0 && counter < 0xffff) { | |
183e19f5 SY |
316 | struct ir_raw_event ev = { |
317 | .carrier_report = 1, | |
318 | .carrier = DIV_ROUND_CLOSEST(counter * 1000000u, | |
319 | data->pulse_duration) | |
320 | }; | |
37b0b4e9 SY |
321 | |
322 | ir_raw_event_store(data->dev, &ev); | |
323 | } | |
324 | ||
325 | /* reset and restart the counter */ | |
326 | data->pulse_duration = 0; | |
327 | wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_R, | |
328 | WBCIR_CNTR_EN | WBCIR_CNTR_R); | |
329 | wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_EN, | |
330 | WBCIR_CNTR_EN | WBCIR_CNTR_R); | |
331 | } | |
332 | ||
c829f267 | 333 | static void |
488ebc48 | 334 | wbcir_idle_rx(struct rc_dev *dev, bool idle) |
e258b80e | 335 | { |
488ebc48 | 336 | struct wbcir_data *data = dev->priv; |
e258b80e | 337 | |
1ac7fdee | 338 | if (!idle && data->rxstate == WBCIR_RXSTATE_INACTIVE) |
c829f267 | 339 | data->rxstate = WBCIR_RXSTATE_ACTIVE; |
5b2e303f | 340 | |
e5eda7fa SY |
341 | if (idle && data->rxstate != WBCIR_RXSTATE_INACTIVE) { |
342 | data->rxstate = WBCIR_RXSTATE_INACTIVE; | |
37b0b4e9 SY |
343 | |
344 | if (data->carrier_report_enabled) | |
345 | wbcir_carrier_report(data); | |
346 | ||
488ebc48 DH |
347 | /* Tell hardware to go idle by setting RXINACTIVE */ |
348 | outb(WBCIR_RX_DISABLE, data->sbase + WBCIR_REG_SP3_ASCR); | |
e5eda7fa | 349 | } |
488ebc48 | 350 | } |
e258b80e | 351 | |
488ebc48 DH |
352 | static void |
353 | wbcir_irq_rx(struct wbcir_data *data, struct pnp_dev *device) | |
354 | { | |
355 | u8 irdata; | |
183e19f5 | 356 | struct ir_raw_event rawir = {}; |
5b2e303f | 357 | |
488ebc48 DH |
358 | /* Since RXHDLEV is set, at least 8 bytes are in the FIFO */ |
359 | while (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_AVAIL) { | |
360 | irdata = inb(data->sbase + WBCIR_REG_SP3_RXDATA); | |
c829f267 | 361 | if (data->rxstate == WBCIR_RXSTATE_ERROR) |
5b2e303f | 362 | continue; |
37b0b4e9 | 363 | |
528222d8 | 364 | rawir.duration = ((irdata & 0x7F) + 1) * |
6f2627c2 | 365 | (data->carrier_report_enabled ? 2 : 10); |
488ebc48 | 366 | rawir.pulse = irdata & 0x80 ? false : true; |
37b0b4e9 SY |
367 | |
368 | if (rawir.pulse) | |
528222d8 | 369 | data->pulse_duration += rawir.duration; |
37b0b4e9 | 370 | |
488ebc48 | 371 | ir_raw_event_store_with_filter(data->dev, &rawir); |
e258b80e DH |
372 | } |
373 | ||
5b2e303f | 374 | ir_raw_event_handle(data->dev); |
c829f267 DH |
375 | } |
376 | ||
377 | static void | |
378 | wbcir_irq_tx(struct wbcir_data *data) | |
379 | { | |
380 | unsigned int space; | |
381 | unsigned int used; | |
382 | u8 bytes[16]; | |
383 | u8 byte; | |
384 | ||
385 | if (!data->txbuf) | |
386 | return; | |
387 | ||
388 | switch (data->txstate) { | |
389 | case WBCIR_TXSTATE_INACTIVE: | |
390 | /* TX FIFO empty */ | |
391 | space = 16; | |
c829f267 DH |
392 | break; |
393 | case WBCIR_TXSTATE_ACTIVE: | |
394 | /* TX FIFO low (3 bytes or less) */ | |
395 | space = 13; | |
396 | break; | |
397 | case WBCIR_TXSTATE_ERROR: | |
398 | space = 0; | |
399 | break; | |
400 | default: | |
401 | return; | |
402 | } | |
403 | ||
404 | /* | |
405 | * TX data is run-length coded in bytes: YXXXXXXX | |
406 | * Y = space (1) or pulse (0) | |
407 | * X = duration, encoded as (X + 1) * 10us (i.e 10 to 1280 us) | |
408 | */ | |
409 | for (used = 0; used < space && data->txoff != data->txlen; used++) { | |
410 | if (data->txbuf[data->txoff] == 0) { | |
411 | data->txoff++; | |
412 | continue; | |
413 | } | |
414 | byte = min((u32)0x80, data->txbuf[data->txoff]); | |
415 | data->txbuf[data->txoff] -= byte; | |
416 | byte--; | |
417 | byte |= (data->txoff % 2 ? 0x80 : 0x00); /* pulse/space */ | |
418 | bytes[used] = byte; | |
419 | } | |
420 | ||
4fe055ec | 421 | while (data->txoff != data->txlen && data->txbuf[data->txoff] == 0) |
c829f267 DH |
422 | data->txoff++; |
423 | ||
424 | if (used == 0) { | |
425 | /* Finished */ | |
426 | if (data->txstate == WBCIR_TXSTATE_ERROR) | |
427 | /* Clear TX underrun bit */ | |
428 | outb(WBCIR_TX_UNDERRUN, data->sbase + WBCIR_REG_SP3_ASCR); | |
c829f267 | 429 | wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR); |
7bfb5dc1 DH |
430 | kfree(data->txbuf); |
431 | data->txbuf = NULL; | |
432 | data->txstate = WBCIR_TXSTATE_INACTIVE; | |
c829f267 DH |
433 | } else if (data->txoff == data->txlen) { |
434 | /* At the end of transmission, tell the hw before last byte */ | |
435 | outsb(data->sbase + WBCIR_REG_SP3_TXDATA, bytes, used - 1); | |
436 | outb(WBCIR_TX_EOT, data->sbase + WBCIR_REG_SP3_ASCR); | |
437 | outb(bytes[used - 1], data->sbase + WBCIR_REG_SP3_TXDATA); | |
438 | wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR | | |
439 | WBCIR_IRQ_TX_EMPTY); | |
440 | } else { | |
441 | /* More data to follow... */ | |
442 | outsb(data->sbase + WBCIR_REG_SP3_RXDATA, bytes, used); | |
443 | if (data->txstate == WBCIR_TXSTATE_INACTIVE) { | |
444 | wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR | | |
445 | WBCIR_IRQ_TX_LOW); | |
446 | data->txstate = WBCIR_TXSTATE_ACTIVE; | |
447 | } | |
448 | } | |
449 | } | |
450 | ||
451 | static irqreturn_t | |
452 | wbcir_irq_handler(int irqno, void *cookie) | |
453 | { | |
454 | struct pnp_dev *device = cookie; | |
455 | struct wbcir_data *data = pnp_get_drvdata(device); | |
456 | unsigned long flags; | |
457 | u8 status; | |
458 | ||
459 | spin_lock_irqsave(&data->spinlock, flags); | |
460 | wbcir_select_bank(data, WBCIR_BANK_0); | |
461 | status = inb(data->sbase + WBCIR_REG_SP3_EIR); | |
462 | status &= data->irqmask; | |
463 | ||
464 | if (!status) { | |
465 | spin_unlock_irqrestore(&data->spinlock, flags); | |
466 | return IRQ_NONE; | |
467 | } | |
468 | ||
469 | if (status & WBCIR_IRQ_ERR) { | |
470 | /* RX overflow? (read clears bit) */ | |
471 | if (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_OVERRUN) { | |
472 | data->rxstate = WBCIR_RXSTATE_ERROR; | |
473 | ir_raw_event_reset(data->dev); | |
474 | } | |
475 | ||
476 | /* TX underflow? */ | |
477 | if (inb(data->sbase + WBCIR_REG_SP3_ASCR) & WBCIR_TX_UNDERRUN) | |
478 | data->txstate = WBCIR_TXSTATE_ERROR; | |
479 | } | |
480 | ||
481 | if (status & WBCIR_IRQ_RX) | |
482 | wbcir_irq_rx(data, device); | |
483 | ||
484 | if (status & (WBCIR_IRQ_TX_LOW | WBCIR_IRQ_TX_EMPTY)) | |
485 | wbcir_irq_tx(data); | |
5b2e303f | 486 | |
5b2e303f | 487 | spin_unlock_irqrestore(&data->spinlock, flags); |
e258b80e DH |
488 | return IRQ_HANDLED; |
489 | } | |
490 | ||
c829f267 DH |
491 | /***************************************************************************** |
492 | * | |
493 | * RC-CORE INTERFACE FUNCTIONS | |
494 | * | |
495 | *****************************************************************************/ | |
496 | ||
37b0b4e9 SY |
497 | static int |
498 | wbcir_set_carrier_report(struct rc_dev *dev, int enable) | |
499 | { | |
500 | struct wbcir_data *data = dev->priv; | |
501 | unsigned long flags; | |
502 | ||
503 | spin_lock_irqsave(&data->spinlock, flags); | |
504 | ||
505 | if (data->carrier_report_enabled == enable) { | |
506 | spin_unlock_irqrestore(&data->spinlock, flags); | |
507 | return 0; | |
508 | } | |
509 | ||
510 | data->pulse_duration = 0; | |
511 | wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_R, | |
512 | WBCIR_CNTR_EN | WBCIR_CNTR_R); | |
513 | ||
514 | if (enable && data->dev->idle) | |
515 | wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, | |
516 | WBCIR_CNTR_EN, WBCIR_CNTR_EN | WBCIR_CNTR_R); | |
517 | ||
6f2627c2 SY |
518 | /* Set a higher sampling resolution if carrier reports are enabled */ |
519 | wbcir_select_bank(data, WBCIR_BANK_2); | |
528222d8 | 520 | data->dev->rx_resolution = enable ? 2 : 10; |
6f2627c2 SY |
521 | outb(enable ? 0x03 : 0x0f, data->sbase + WBCIR_REG_SP3_BGDL); |
522 | outb(0x00, data->sbase + WBCIR_REG_SP3_BGDH); | |
523 | ||
524 | /* Enable oversampling if carrier reports are enabled */ | |
525 | wbcir_select_bank(data, WBCIR_BANK_7); | |
526 | wbcir_set_bits(data->sbase + WBCIR_REG_SP3_RCCFG, | |
527 | enable ? WBCIR_RX_T_OV : 0, WBCIR_RX_T_OV); | |
528 | ||
37b0b4e9 SY |
529 | data->carrier_report_enabled = enable; |
530 | spin_unlock_irqrestore(&data->spinlock, flags); | |
531 | ||
532 | return 0; | |
533 | } | |
534 | ||
c829f267 DH |
535 | static int |
536 | wbcir_txcarrier(struct rc_dev *dev, u32 carrier) | |
537 | { | |
538 | struct wbcir_data *data = dev->priv; | |
539 | unsigned long flags; | |
540 | u8 val; | |
541 | u32 freq; | |
542 | ||
543 | freq = DIV_ROUND_CLOSEST(carrier, 1000); | |
544 | if (freq < 30 || freq > 60) | |
545 | return -EINVAL; | |
546 | ||
547 | switch (freq) { | |
548 | case 58: | |
549 | case 59: | |
550 | case 60: | |
551 | val = freq - 58; | |
552 | freq *= 1000; | |
553 | break; | |
554 | case 57: | |
555 | val = freq - 27; | |
556 | freq = 56900; | |
557 | break; | |
558 | default: | |
559 | val = freq - 27; | |
560 | freq *= 1000; | |
561 | break; | |
562 | } | |
563 | ||
564 | spin_lock_irqsave(&data->spinlock, flags); | |
565 | if (data->txstate != WBCIR_TXSTATE_INACTIVE) { | |
566 | spin_unlock_irqrestore(&data->spinlock, flags); | |
567 | return -EBUSY; | |
568 | } | |
569 | ||
570 | if (data->txcarrier != freq) { | |
571 | wbcir_select_bank(data, WBCIR_BANK_7); | |
572 | wbcir_set_bits(data->sbase + WBCIR_REG_SP3_IRTXMC, val, 0x1F); | |
573 | data->txcarrier = freq; | |
574 | } | |
575 | ||
576 | spin_unlock_irqrestore(&data->spinlock, flags); | |
577 | return 0; | |
578 | } | |
579 | ||
580 | static int | |
581 | wbcir_txmask(struct rc_dev *dev, u32 mask) | |
582 | { | |
583 | struct wbcir_data *data = dev->priv; | |
584 | unsigned long flags; | |
585 | u8 val; | |
586 | ||
20f5a827 SY |
587 | /* return the number of transmitters */ |
588 | if (mask > 15) | |
589 | return 4; | |
590 | ||
c829f267 DH |
591 | /* Four outputs, only one output can be enabled at a time */ |
592 | switch (mask) { | |
593 | case 0x1: | |
594 | val = 0x0; | |
595 | break; | |
596 | case 0x2: | |
597 | val = 0x1; | |
598 | break; | |
599 | case 0x4: | |
600 | val = 0x2; | |
601 | break; | |
602 | case 0x8: | |
603 | val = 0x3; | |
604 | break; | |
605 | default: | |
606 | return -EINVAL; | |
607 | } | |
608 | ||
609 | spin_lock_irqsave(&data->spinlock, flags); | |
610 | if (data->txstate != WBCIR_TXSTATE_INACTIVE) { | |
611 | spin_unlock_irqrestore(&data->spinlock, flags); | |
612 | return -EBUSY; | |
613 | } | |
614 | ||
615 | if (data->txmask != mask) { | |
616 | wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS, val, 0x0c); | |
617 | data->txmask = mask; | |
618 | } | |
619 | ||
620 | spin_unlock_irqrestore(&data->spinlock, flags); | |
621 | return 0; | |
622 | } | |
623 | ||
624 | static int | |
7bfb5dc1 | 625 | wbcir_tx(struct rc_dev *dev, unsigned *b, unsigned count) |
c829f267 DH |
626 | { |
627 | struct wbcir_data *data = dev->priv; | |
7bfb5dc1 | 628 | unsigned *buf; |
c829f267 DH |
629 | unsigned i; |
630 | unsigned long flags; | |
631 | ||
ce3aeaf2 | 632 | buf = kmalloc_array(count, sizeof(*b), GFP_KERNEL); |
7bfb5dc1 DH |
633 | if (!buf) |
634 | return -ENOMEM; | |
635 | ||
636 | /* Convert values to multiples of 10us */ | |
637 | for (i = 0; i < count; i++) | |
638 | buf[i] = DIV_ROUND_CLOSEST(b[i], 10); | |
639 | ||
c829f267 DH |
640 | /* Not sure if this is possible, but better safe than sorry */ |
641 | spin_lock_irqsave(&data->spinlock, flags); | |
642 | if (data->txstate != WBCIR_TXSTATE_INACTIVE) { | |
643 | spin_unlock_irqrestore(&data->spinlock, flags); | |
7bfb5dc1 | 644 | kfree(buf); |
c829f267 DH |
645 | return -EBUSY; |
646 | } | |
647 | ||
c829f267 DH |
648 | /* Fill the TX fifo once, the irq handler will do the rest */ |
649 | data->txbuf = buf; | |
650 | data->txlen = count; | |
651 | data->txoff = 0; | |
652 | wbcir_irq_tx(data); | |
653 | ||
c829f267 | 654 | /* We're done */ |
c829f267 | 655 | spin_unlock_irqrestore(&data->spinlock, flags); |
c829f267 DH |
656 | return count; |
657 | } | |
e258b80e DH |
658 | |
659 | /***************************************************************************** | |
660 | * | |
197d4db7 | 661 | * SETUP/INIT/SUSPEND/RESUME FUNCTIONS |
e258b80e DH |
662 | * |
663 | *****************************************************************************/ | |
664 | ||
665 | static void | |
666 | wbcir_shutdown(struct pnp_dev *device) | |
667 | { | |
668 | struct device *dev = &device->dev; | |
669 | struct wbcir_data *data = pnp_get_drvdata(device); | |
f4742e1d | 670 | struct rc_dev *rc = data->dev; |
67cdd42e | 671 | bool do_wake = true; |
e258b80e DH |
672 | u8 match[11]; |
673 | u8 mask[11]; | |
674 | u8 rc6_csl = 0; | |
f4742e1d SY |
675 | u8 proto; |
676 | u32 wake_sc = rc->scancode_wakeup_filter.data; | |
677 | u32 mask_sc = rc->scancode_wakeup_filter.mask; | |
e258b80e DH |
678 | int i; |
679 | ||
680 | memset(match, 0, sizeof(match)); | |
681 | memset(mask, 0, sizeof(mask)); | |
682 | ||
f4742e1d | 683 | if (!mask_sc || !device_may_wakeup(dev)) { |
67cdd42e | 684 | do_wake = false; |
e258b80e DH |
685 | goto finish; |
686 | } | |
687 | ||
f4742e1d | 688 | switch (rc->wakeup_protocol) { |
6d741bfe | 689 | case RC_PROTO_RC5: |
e258b80e | 690 | /* Mask = 13 bits, ex toggle */ |
f4742e1d SY |
691 | mask[0] = (mask_sc & 0x003f); |
692 | mask[0] |= (mask_sc & 0x0300) >> 2; | |
693 | mask[1] = (mask_sc & 0x1c00) >> 10; | |
694 | if (mask_sc & 0x0040) /* 2nd start bit */ | |
695 | match[1] |= 0x10; | |
e258b80e | 696 | |
f4742e1d SY |
697 | match[0] = (wake_sc & 0x003F); /* 6 command bits */ |
698 | match[0] |= (wake_sc & 0x0300) >> 2; /* 2 address bits */ | |
699 | match[1] = (wake_sc & 0x1c00) >> 10; /* 3 address bits */ | |
700 | if (!(wake_sc & 0x0040)) /* 2nd start bit */ | |
e258b80e DH |
701 | match[1] |= 0x10; |
702 | ||
f4742e1d | 703 | proto = IR_PROTOCOL_RC5; |
e258b80e DH |
704 | break; |
705 | ||
6d741bfe | 706 | case RC_PROTO_NEC: |
f4742e1d SY |
707 | mask[1] = bitrev8(mask_sc); |
708 | mask[0] = mask[1]; | |
709 | mask[3] = bitrev8(mask_sc >> 8); | |
710 | mask[2] = mask[3]; | |
e258b80e | 711 | |
f4742e1d | 712 | match[1] = bitrev8(wake_sc); |
e258b80e | 713 | match[0] = ~match[1]; |
f4742e1d SY |
714 | match[3] = bitrev8(wake_sc >> 8); |
715 | match[2] = ~match[3]; | |
e258b80e | 716 | |
f4742e1d SY |
717 | proto = IR_PROTOCOL_NEC; |
718 | break; | |
e258b80e | 719 | |
6d741bfe | 720 | case RC_PROTO_NECX: |
f4742e1d SY |
721 | mask[1] = bitrev8(mask_sc); |
722 | mask[0] = mask[1]; | |
723 | mask[2] = bitrev8(mask_sc >> 8); | |
724 | mask[3] = bitrev8(mask_sc >> 16); | |
725 | ||
726 | match[1] = bitrev8(wake_sc); | |
727 | match[0] = ~match[1]; | |
728 | match[2] = bitrev8(wake_sc >> 8); | |
729 | match[3] = bitrev8(wake_sc >> 16); | |
730 | ||
731 | proto = IR_PROTOCOL_NEC; | |
e258b80e DH |
732 | break; |
733 | ||
6d741bfe | 734 | case RC_PROTO_NEC32: |
f4742e1d SY |
735 | mask[0] = bitrev8(mask_sc); |
736 | mask[1] = bitrev8(mask_sc >> 8); | |
737 | mask[2] = bitrev8(mask_sc >> 16); | |
738 | mask[3] = bitrev8(mask_sc >> 24); | |
e258b80e | 739 | |
f4742e1d SY |
740 | match[0] = bitrev8(wake_sc); |
741 | match[1] = bitrev8(wake_sc >> 8); | |
742 | match[2] = bitrev8(wake_sc >> 16); | |
743 | match[3] = bitrev8(wake_sc >> 24); | |
744 | ||
745 | proto = IR_PROTOCOL_NEC; | |
746 | break; | |
747 | ||
6d741bfe | 748 | case RC_PROTO_RC6_0: |
f4742e1d SY |
749 | /* Command */ |
750 | match[0] = wbcir_to_rc6cells(wake_sc >> 0); | |
751 | mask[0] = wbcir_to_rc6cells(mask_sc >> 0); | |
752 | match[1] = wbcir_to_rc6cells(wake_sc >> 4); | |
753 | mask[1] = wbcir_to_rc6cells(mask_sc >> 4); | |
754 | ||
755 | /* Address */ | |
756 | match[2] = wbcir_to_rc6cells(wake_sc >> 8); | |
757 | mask[2] = wbcir_to_rc6cells(mask_sc >> 8); | |
758 | match[3] = wbcir_to_rc6cells(wake_sc >> 12); | |
759 | mask[3] = wbcir_to_rc6cells(mask_sc >> 12); | |
760 | ||
761 | /* Header */ | |
762 | match[4] = 0x50; /* mode1 = mode0 = 0, ignore toggle */ | |
763 | mask[4] = 0xF0; | |
764 | match[5] = 0x09; /* start bit = 1, mode2 = 0 */ | |
765 | mask[5] = 0x0F; | |
766 | ||
767 | rc6_csl = 44; | |
768 | proto = IR_PROTOCOL_RC6; | |
769 | break; | |
e258b80e | 770 | |
6d741bfe SY |
771 | case RC_PROTO_RC6_6A_24: |
772 | case RC_PROTO_RC6_6A_32: | |
773 | case RC_PROTO_RC6_MCE: | |
f4742e1d SY |
774 | i = 0; |
775 | ||
776 | /* Command */ | |
777 | match[i] = wbcir_to_rc6cells(wake_sc >> 0); | |
778 | mask[i++] = wbcir_to_rc6cells(mask_sc >> 0); | |
779 | match[i] = wbcir_to_rc6cells(wake_sc >> 4); | |
780 | mask[i++] = wbcir_to_rc6cells(mask_sc >> 4); | |
781 | ||
782 | /* Address + Toggle */ | |
783 | match[i] = wbcir_to_rc6cells(wake_sc >> 8); | |
784 | mask[i++] = wbcir_to_rc6cells(mask_sc >> 8); | |
785 | match[i] = wbcir_to_rc6cells(wake_sc >> 12); | |
786 | mask[i++] = wbcir_to_rc6cells(mask_sc >> 12); | |
787 | ||
788 | /* Customer bits 7 - 0 */ | |
789 | match[i] = wbcir_to_rc6cells(wake_sc >> 16); | |
790 | mask[i++] = wbcir_to_rc6cells(mask_sc >> 16); | |
791 | ||
6d741bfe | 792 | if (rc->wakeup_protocol == RC_PROTO_RC6_6A_20) { |
f4742e1d SY |
793 | rc6_csl = 52; |
794 | } else { | |
e258b80e | 795 | match[i] = wbcir_to_rc6cells(wake_sc >> 20); |
f4742e1d | 796 | mask[i++] = wbcir_to_rc6cells(mask_sc >> 20); |
e258b80e | 797 | |
6d741bfe | 798 | if (rc->wakeup_protocol == RC_PROTO_RC6_6A_24) { |
f4742e1d SY |
799 | rc6_csl = 60; |
800 | } else { | |
e258b80e DH |
801 | /* Customer range bit and bits 15 - 8 */ |
802 | match[i] = wbcir_to_rc6cells(wake_sc >> 24); | |
f4742e1d | 803 | mask[i++] = wbcir_to_rc6cells(mask_sc >> 24); |
e258b80e | 804 | match[i] = wbcir_to_rc6cells(wake_sc >> 28); |
f4742e1d | 805 | mask[i++] = wbcir_to_rc6cells(mask_sc >> 28); |
e258b80e | 806 | rc6_csl = 76; |
e258b80e | 807 | } |
e258b80e DH |
808 | } |
809 | ||
f4742e1d SY |
810 | /* Header */ |
811 | match[i] = 0x93; /* mode1 = mode0 = 1, submode = 0 */ | |
812 | mask[i++] = 0xFF; | |
813 | match[i] = 0x0A; /* start bit = 1, mode2 = 1 */ | |
814 | mask[i++] = 0x0F; | |
815 | proto = IR_PROTOCOL_RC6; | |
e258b80e | 816 | break; |
e258b80e | 817 | default: |
67cdd42e | 818 | do_wake = false; |
e258b80e DH |
819 | break; |
820 | } | |
821 | ||
822 | finish: | |
823 | if (do_wake) { | |
824 | /* Set compare and compare mask */ | |
825 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX, | |
826 | WBCIR_REGSEL_COMPARE | WBCIR_REG_ADDR0, | |
827 | 0x3F); | |
828 | outsb(data->wbase + WBCIR_REG_WCEIR_DATA, match, 11); | |
829 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX, | |
830 | WBCIR_REGSEL_MASK | WBCIR_REG_ADDR0, | |
831 | 0x3F); | |
832 | outsb(data->wbase + WBCIR_REG_WCEIR_DATA, mask, 11); | |
833 | ||
834 | /* RC6 Compare String Len */ | |
835 | outb(rc6_csl, data->wbase + WBCIR_REG_WCEIR_CSL); | |
836 | ||
837 | /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */ | |
838 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17); | |
839 | ||
840 | /* Clear BUFF_EN, Clear END_EN, Set MATCH_EN */ | |
841 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x01, 0x07); | |
842 | ||
843 | /* Set CEIR_EN */ | |
f4742e1d SY |
844 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, |
845 | (proto << 4) | 0x01, 0x31); | |
e258b80e DH |
846 | |
847 | } else { | |
848 | /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */ | |
849 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07); | |
850 | ||
851 | /* Clear CEIR_EN */ | |
852 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01); | |
853 | } | |
854 | ||
197d4db7 DH |
855 | /* |
856 | * ACPI will set the HW disable bit for SP3 which means that the | |
857 | * output signals are left in an undefined state which may cause | |
858 | * spurious interrupts which we need to ignore until the hardware | |
859 | * is reinitialized. | |
860 | */ | |
c829f267 | 861 | wbcir_set_irqmask(data, WBCIR_IRQ_NONE); |
197d4db7 | 862 | disable_irq(data->irq); |
e258b80e DH |
863 | } |
864 | ||
f4742e1d SY |
865 | /* |
866 | * Wakeup handling is done on shutdown. | |
867 | */ | |
868 | static int | |
869 | wbcir_set_wakeup_filter(struct rc_dev *rc, struct rc_scancode_filter *filter) | |
870 | { | |
871 | return 0; | |
872 | } | |
873 | ||
e258b80e DH |
874 | static int |
875 | wbcir_suspend(struct pnp_dev *device, pm_message_t state) | |
876 | { | |
1ac7fdee SY |
877 | struct wbcir_data *data = pnp_get_drvdata(device); |
878 | led_classdev_suspend(&data->led); | |
e258b80e DH |
879 | wbcir_shutdown(device); |
880 | return 0; | |
881 | } | |
882 | ||
e258b80e | 883 | static void |
197d4db7 | 884 | wbcir_init_hw(struct wbcir_data *data) |
e258b80e | 885 | { |
197d4db7 | 886 | /* Disable interrupts */ |
c829f267 | 887 | wbcir_set_irqmask(data, WBCIR_IRQ_NONE); |
197d4db7 | 888 | |
f4742e1d SY |
889 | /* Set RX_INV, Clear CEIR_EN (needed for the led) */ |
890 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, invert ? 8 : 0, 0x09); | |
e258b80e DH |
891 | |
892 | /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */ | |
893 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17); | |
894 | ||
895 | /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */ | |
896 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07); | |
897 | ||
898 | /* Set RC5 cell time to correspond to 36 kHz */ | |
899 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CFG1, 0x4A, 0x7F); | |
900 | ||
901 | /* Set IRTX_INV */ | |
902 | if (invert) | |
37b0b4e9 | 903 | outb(WBCIR_IRTX_INV, data->ebase + WBCIR_REG_ECEIR_CCTL); |
e258b80e DH |
904 | else |
905 | outb(0x00, data->ebase + WBCIR_REG_ECEIR_CCTL); | |
906 | ||
907 | /* | |
c829f267 | 908 | * Clear IR LED, set SP3 clock to 24Mhz, set TX mask to IRTX1, |
e258b80e DH |
909 | * set SP3_IRRX_SW to binary 01, helpfully not documented |
910 | */ | |
911 | outb(0x10, data->ebase + WBCIR_REG_ECEIR_CTS); | |
c829f267 | 912 | data->txmask = 0x1; |
197d4db7 DH |
913 | |
914 | /* Enable extended mode */ | |
915 | wbcir_select_bank(data, WBCIR_BANK_2); | |
916 | outb(WBCIR_EXT_ENABLE, data->sbase + WBCIR_REG_SP3_EXCR1); | |
917 | ||
918 | /* | |
919 | * Configure baud generator, IR data will be sampled at | |
920 | * a bitrate of: (24Mhz * prescaler) / (divisor * 16). | |
921 | * | |
922 | * The ECIR registers include a flag to change the | |
923 | * 24Mhz clock freq to 48Mhz. | |
924 | * | |
925 | * It's not documented in the specs, but fifo levels | |
926 | * other than 16 seems to be unsupported. | |
927 | */ | |
928 | ||
929 | /* prescaler 1.0, tx/rx fifo lvl 16 */ | |
930 | outb(0x30, data->sbase + WBCIR_REG_SP3_EXCR2); | |
931 | ||
6f2627c2 SY |
932 | /* Set baud divisor to sample every 10 us */ |
933 | outb(0x0f, data->sbase + WBCIR_REG_SP3_BGDL); | |
197d4db7 DH |
934 | outb(0x00, data->sbase + WBCIR_REG_SP3_BGDH); |
935 | ||
936 | /* Set CEIR mode */ | |
937 | wbcir_select_bank(data, WBCIR_BANK_0); | |
938 | outb(0xC0, data->sbase + WBCIR_REG_SP3_MCR); | |
939 | inb(data->sbase + WBCIR_REG_SP3_LSR); /* Clear LSR */ | |
940 | inb(data->sbase + WBCIR_REG_SP3_MSR); /* Clear MSR */ | |
941 | ||
6f2627c2 | 942 | /* Disable RX demod, enable run-length enc/dec, set freq span */ |
197d4db7 | 943 | wbcir_select_bank(data, WBCIR_BANK_7); |
6f2627c2 | 944 | outb(0x90, data->sbase + WBCIR_REG_SP3_RCCFG); |
197d4db7 DH |
945 | |
946 | /* Disable timer */ | |
947 | wbcir_select_bank(data, WBCIR_BANK_4); | |
948 | outb(0x00, data->sbase + WBCIR_REG_SP3_IRCR1); | |
949 | ||
c829f267 | 950 | /* Disable MSR interrupt, clear AUX_IRX, mask RX during TX? */ |
197d4db7 | 951 | wbcir_select_bank(data, WBCIR_BANK_5); |
c829f267 | 952 | outb(txandrx ? 0x03 : 0x02, data->sbase + WBCIR_REG_SP3_IRCR2); |
197d4db7 DH |
953 | |
954 | /* Disable CRC */ | |
955 | wbcir_select_bank(data, WBCIR_BANK_6); | |
956 | outb(0x20, data->sbase + WBCIR_REG_SP3_IRCR3); | |
957 | ||
c829f267 | 958 | /* Set RX demodulation freq, not really used */ |
197d4db7 DH |
959 | wbcir_select_bank(data, WBCIR_BANK_7); |
960 | outb(0xF2, data->sbase + WBCIR_REG_SP3_IRRXDC); | |
c829f267 DH |
961 | |
962 | /* Set TX modulation, 36kHz, 7us pulse width */ | |
197d4db7 | 963 | outb(0x69, data->sbase + WBCIR_REG_SP3_IRTXMC); |
c829f267 | 964 | data->txcarrier = 36000; |
197d4db7 DH |
965 | |
966 | /* Set invert and pin direction */ | |
967 | if (invert) | |
968 | outb(0x10, data->sbase + WBCIR_REG_SP3_IRCFG4); | |
969 | else | |
970 | outb(0x00, data->sbase + WBCIR_REG_SP3_IRCFG4); | |
971 | ||
972 | /* Set FIFO thresholds (RX = 8, TX = 3), reset RX/TX */ | |
973 | wbcir_select_bank(data, WBCIR_BANK_0); | |
974 | outb(0x97, data->sbase + WBCIR_REG_SP3_FCR); | |
975 | ||
976 | /* Clear AUX status bits */ | |
977 | outb(0xE0, data->sbase + WBCIR_REG_SP3_ASCR); | |
978 | ||
c829f267 DH |
979 | /* Clear RX state */ |
980 | data->rxstate = WBCIR_RXSTATE_INACTIVE; | |
5dae9cea | 981 | wbcir_idle_rx(data->dev, true); |
5b2e303f | 982 | |
7bfb5dc1 | 983 | /* Clear TX state */ |
c829f267 | 984 | if (data->txstate == WBCIR_TXSTATE_ACTIVE) { |
7bfb5dc1 DH |
985 | kfree(data->txbuf); |
986 | data->txbuf = NULL; | |
987 | data->txstate = WBCIR_TXSTATE_INACTIVE; | |
c829f267 DH |
988 | } |
989 | ||
197d4db7 | 990 | /* Enable interrupts */ |
c829f267 | 991 | wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR); |
197d4db7 DH |
992 | } |
993 | ||
994 | static int | |
995 | wbcir_resume(struct pnp_dev *device) | |
996 | { | |
997 | struct wbcir_data *data = pnp_get_drvdata(device); | |
998 | ||
999 | wbcir_init_hw(data); | |
5dae9cea | 1000 | ir_raw_event_reset(data->dev); |
197d4db7 | 1001 | enable_irq(data->irq); |
1ac7fdee | 1002 | led_classdev_resume(&data->led); |
197d4db7 DH |
1003 | |
1004 | return 0; | |
e258b80e DH |
1005 | } |
1006 | ||
4c62e976 | 1007 | static int |
e258b80e DH |
1008 | wbcir_probe(struct pnp_dev *device, const struct pnp_device_id *dev_id) |
1009 | { | |
1010 | struct device *dev = &device->dev; | |
1011 | struct wbcir_data *data; | |
1012 | int err; | |
1013 | ||
1014 | if (!(pnp_port_len(device, 0) == EHFUNC_IOMEM_LEN && | |
1015 | pnp_port_len(device, 1) == WAKEUP_IOMEM_LEN && | |
1016 | pnp_port_len(device, 2) == SP_IOMEM_LEN)) { | |
1017 | dev_err(dev, "Invalid resources\n"); | |
1018 | return -ENODEV; | |
1019 | } | |
1020 | ||
1021 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
1022 | if (!data) { | |
1023 | err = -ENOMEM; | |
1024 | goto exit; | |
1025 | } | |
1026 | ||
1027 | pnp_set_drvdata(device, data); | |
1028 | ||
5b2e303f | 1029 | spin_lock_init(&data->spinlock); |
e258b80e DH |
1030 | data->ebase = pnp_port_start(device, 0); |
1031 | data->wbase = pnp_port_start(device, 1); | |
1032 | data->sbase = pnp_port_start(device, 2); | |
1033 | data->irq = pnp_irq(device, 0); | |
1034 | ||
1035 | if (data->wbase == 0 || data->ebase == 0 || | |
621fa19a | 1036 | data->sbase == 0 || data->irq == -1) { |
e258b80e DH |
1037 | err = -ENODEV; |
1038 | dev_err(dev, "Invalid resources\n"); | |
1039 | goto exit_free_data; | |
1040 | } | |
1041 | ||
25ec587c | 1042 | dev_dbg(&device->dev, "Found device (w: 0x%lX, e: 0x%lX, s: 0x%lX, i: %u)\n", |
e258b80e DH |
1043 | data->wbase, data->ebase, data->sbase, data->irq); |
1044 | ||
e258b80e | 1045 | data->led.name = "cir::activity"; |
1ac7fdee | 1046 | data->led.default_trigger = "rc-feedback"; |
e258b80e DH |
1047 | data->led.brightness_set = wbcir_led_brightness_set; |
1048 | data->led.brightness_get = wbcir_led_brightness_get; | |
1049 | err = led_classdev_register(&device->dev, &data->led); | |
1050 | if (err) | |
1ac7fdee | 1051 | goto exit_free_data; |
e258b80e | 1052 | |
0f7499fd | 1053 | data->dev = rc_allocate_device(RC_DRIVER_IR_RAW); |
5b2e303f | 1054 | if (!data->dev) { |
e258b80e DH |
1055 | err = -ENOMEM; |
1056 | goto exit_unregister_led; | |
1057 | } | |
1058 | ||
a66cd0b6 | 1059 | data->dev->driver_name = DRVNAME; |
518f4b26 | 1060 | data->dev->device_name = WBCIR_NAME; |
5b2e303f DH |
1061 | data->dev->input_phys = "wbcir/cir0"; |
1062 | data->dev->input_id.bustype = BUS_HOST; | |
1063 | data->dev->input_id.vendor = PCI_VENDOR_ID_WINBOND; | |
1064 | data->dev->input_id.product = WBCIR_ID_FAMILY; | |
1065 | data->dev->input_id.version = WBCIR_ID_CHIP; | |
c829f267 | 1066 | data->dev->map_name = RC_MAP_RC6_MCE; |
488ebc48 | 1067 | data->dev->s_idle = wbcir_idle_rx; |
37b0b4e9 | 1068 | data->dev->s_carrier_report = wbcir_set_carrier_report; |
c829f267 DH |
1069 | data->dev->s_tx_mask = wbcir_txmask; |
1070 | data->dev->s_tx_carrier = wbcir_txcarrier; | |
1071 | data->dev->tx_ir = wbcir_tx; | |
5b2e303f DH |
1072 | data->dev->priv = data; |
1073 | data->dev->dev.parent = &device->dev; | |
ea80fb6d SY |
1074 | data->dev->min_timeout = 1; |
1075 | data->dev->timeout = IR_DEFAULT_TIMEOUT; | |
1076 | data->dev->max_timeout = 10 * IR_DEFAULT_TIMEOUT; | |
528222d8 | 1077 | data->dev->rx_resolution = 2; |
6d741bfe SY |
1078 | data->dev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER; |
1079 | data->dev->allowed_wakeup_protocols = RC_PROTO_BIT_NEC | | |
1080 | RC_PROTO_BIT_NECX | RC_PROTO_BIT_NEC32 | RC_PROTO_BIT_RC5 | | |
1081 | RC_PROTO_BIT_RC6_0 | RC_PROTO_BIT_RC6_6A_20 | | |
1082 | RC_PROTO_BIT_RC6_6A_24 | RC_PROTO_BIT_RC6_6A_32 | | |
1083 | RC_PROTO_BIT_RC6_MCE; | |
1084 | data->dev->wakeup_protocol = RC_PROTO_RC6_MCE; | |
f4742e1d SY |
1085 | data->dev->scancode_wakeup_filter.data = 0x800f040c; |
1086 | data->dev->scancode_wakeup_filter.mask = 0xffff7fff; | |
1087 | data->dev->s_wakeup_filter = wbcir_set_wakeup_filter; | |
5b2e303f | 1088 | |
9fa35204 MK |
1089 | err = rc_register_device(data->dev); |
1090 | if (err) | |
1091 | goto exit_free_rc; | |
1092 | ||
9ef449c6 LH |
1093 | if (!request_region(data->wbase, WAKEUP_IOMEM_LEN, DRVNAME)) { |
1094 | dev_err(dev, "Region 0x%lx-0x%lx already in use!\n", | |
1095 | data->wbase, data->wbase + WAKEUP_IOMEM_LEN - 1); | |
1096 | err = -EBUSY; | |
9fa35204 | 1097 | goto exit_unregister_device; |
9ef449c6 LH |
1098 | } |
1099 | ||
1100 | if (!request_region(data->ebase, EHFUNC_IOMEM_LEN, DRVNAME)) { | |
1101 | dev_err(dev, "Region 0x%lx-0x%lx already in use!\n", | |
1102 | data->ebase, data->ebase + EHFUNC_IOMEM_LEN - 1); | |
1103 | err = -EBUSY; | |
1104 | goto exit_release_wbase; | |
1105 | } | |
1106 | ||
1107 | if (!request_region(data->sbase, SP_IOMEM_LEN, DRVNAME)) { | |
1108 | dev_err(dev, "Region 0x%lx-0x%lx already in use!\n", | |
1109 | data->sbase, data->sbase + SP_IOMEM_LEN - 1); | |
1110 | err = -EBUSY; | |
1111 | goto exit_release_ebase; | |
1112 | } | |
1113 | ||
1114 | err = request_irq(data->irq, wbcir_irq_handler, | |
b9e9f02a | 1115 | 0, DRVNAME, device); |
9ef449c6 LH |
1116 | if (err) { |
1117 | dev_err(dev, "Failed to claim IRQ %u\n", data->irq); | |
1118 | err = -EBUSY; | |
1119 | goto exit_release_sbase; | |
1120 | } | |
1121 | ||
e258b80e DH |
1122 | device_init_wakeup(&device->dev, 1); |
1123 | ||
197d4db7 | 1124 | wbcir_init_hw(data); |
e258b80e DH |
1125 | |
1126 | return 0; | |
1127 | ||
e258b80e DH |
1128 | exit_release_sbase: |
1129 | release_region(data->sbase, SP_IOMEM_LEN); | |
1130 | exit_release_ebase: | |
1131 | release_region(data->ebase, EHFUNC_IOMEM_LEN); | |
1132 | exit_release_wbase: | |
1133 | release_region(data->wbase, WAKEUP_IOMEM_LEN); | |
9fa35204 MK |
1134 | exit_unregister_device: |
1135 | rc_unregister_device(data->dev); | |
4ec16da7 | 1136 | data->dev = NULL; |
9ef449c6 LH |
1137 | exit_free_rc: |
1138 | rc_free_device(data->dev); | |
1139 | exit_unregister_led: | |
1140 | led_classdev_unregister(&data->led); | |
e258b80e DH |
1141 | exit_free_data: |
1142 | kfree(data); | |
1143 | pnp_set_drvdata(device, NULL); | |
1144 | exit: | |
1145 | return err; | |
1146 | } | |
1147 | ||
4c62e976 | 1148 | static void |
e258b80e DH |
1149 | wbcir_remove(struct pnp_dev *device) |
1150 | { | |
1151 | struct wbcir_data *data = pnp_get_drvdata(device); | |
e258b80e DH |
1152 | |
1153 | /* Disable interrupts */ | |
c829f267 | 1154 | wbcir_set_irqmask(data, WBCIR_IRQ_NONE); |
e258b80e DH |
1155 | free_irq(data->irq, device); |
1156 | ||
1157 | /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */ | |
1158 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17); | |
1159 | ||
1160 | /* Clear CEIR_EN */ | |
1161 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01); | |
1162 | ||
1163 | /* Clear BUFF_EN, END_EN, MATCH_EN */ | |
1164 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07); | |
1165 | ||
5b2e303f | 1166 | rc_unregister_device(data->dev); |
e258b80e | 1167 | |
e258b80e DH |
1168 | led_classdev_unregister(&data->led); |
1169 | ||
1170 | /* This is ok since &data->led isn't actually used */ | |
1171 | wbcir_led_brightness_set(&data->led, LED_OFF); | |
1172 | ||
1173 | release_region(data->wbase, WAKEUP_IOMEM_LEN); | |
1174 | release_region(data->ebase, EHFUNC_IOMEM_LEN); | |
1175 | release_region(data->sbase, SP_IOMEM_LEN); | |
1176 | ||
e258b80e DH |
1177 | kfree(data); |
1178 | ||
1179 | pnp_set_drvdata(device, NULL); | |
1180 | } | |
1181 | ||
1182 | static const struct pnp_device_id wbcir_ids[] = { | |
1183 | { "WEC1022", 0 }, | |
1184 | { "", 0 } | |
1185 | }; | |
1186 | MODULE_DEVICE_TABLE(pnp, wbcir_ids); | |
1187 | ||
1188 | static struct pnp_driver wbcir_driver = { | |
6932234f | 1189 | .name = DRVNAME, |
e258b80e DH |
1190 | .id_table = wbcir_ids, |
1191 | .probe = wbcir_probe, | |
4c62e976 | 1192 | .remove = wbcir_remove, |
e258b80e DH |
1193 | .suspend = wbcir_suspend, |
1194 | .resume = wbcir_resume, | |
1195 | .shutdown = wbcir_shutdown | |
1196 | }; | |
1197 | ||
1198 | static int __init | |
1199 | wbcir_init(void) | |
1200 | { | |
1201 | int ret; | |
1202 | ||
e258b80e DH |
1203 | ret = pnp_register_driver(&wbcir_driver); |
1204 | if (ret) | |
d8a10ac9 | 1205 | pr_err("Unable to register driver\n"); |
e258b80e DH |
1206 | |
1207 | return ret; | |
1208 | } | |
1209 | ||
1210 | static void __exit | |
1211 | wbcir_exit(void) | |
1212 | { | |
1213 | pnp_unregister_driver(&wbcir_driver); | |
1214 | } | |
1215 | ||
e258b80e DH |
1216 | module_init(wbcir_init); |
1217 | module_exit(wbcir_exit); | |
1218 | ||
d36b6910 | 1219 | MODULE_AUTHOR("David Härdeman <david@hardeman.nu>"); |
5b2e303f DH |
1220 | MODULE_DESCRIPTION("Winbond SuperI/O Consumer IR Driver"); |
1221 | MODULE_LICENSE("GPL"); |