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ab33d507 AC |
1 | /**************************************************************************** |
2 | * | |
3 | * Filename: cpia2registers.h | |
4 | * | |
5 | * Copyright 2001, STMicrolectronics, Inc. | |
6 | * | |
7 | * Description: | |
8 | * Definitions for the CPia2 register set | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
ab33d507 AC |
20 | ****************************************************************************/ |
21 | ||
22 | #ifndef CPIA2_REGISTER_HEADER | |
23 | #define CPIA2_REGISTER_HEADER | |
24 | ||
25 | /*** | |
26 | * System register set (Bank 0) | |
27 | ***/ | |
28 | #define CPIA2_SYSTEM_DEVICE_HI 0x00 | |
29 | #define CPIA2_SYSTEM_DEVICE_LO 0x01 | |
30 | ||
31 | #define CPIA2_SYSTEM_SYSTEM_CONTROL 0x02 | |
32 | #define CPIA2_SYSTEM_CONTROL_LOW_POWER 0x00 | |
33 | #define CPIA2_SYSTEM_CONTROL_HIGH_POWER 0x01 | |
34 | #define CPIA2_SYSTEM_CONTROL_SUSPEND 0x02 | |
35 | #define CPIA2_SYSTEM_CONTROL_V2W_ERR 0x10 | |
36 | #define CPIA2_SYSTEM_CONTROL_RB_ERR 0x10 | |
37 | #define CPIA2_SYSTEM_CONTROL_CLEAR_ERR 0x80 | |
38 | ||
39 | #define CPIA2_SYSTEM_INT_PACKET_CTRL 0x04 | |
40 | #define CPIA2_SYSTEM_INT_PACKET_CTRL_ENABLE_SW_XX 0x01 | |
41 | #define CPIA2_SYSTEM_INT_PACKET_CTRL_ENABLE_EOF 0x02 | |
42 | #define CPIA2_SYSTEM_INT_PACKET_CTRL_ENABLE_INT1 0x04 | |
43 | ||
44 | #define CPIA2_SYSTEM_CACHE_CTRL 0x05 | |
45 | #define CPIA2_SYSTEM_CACHE_CTRL_CACHE_RESET 0x01 | |
46 | #define CPIA2_SYSTEM_CACHE_CTRL_CACHE_FLUSH 0x02 | |
47 | ||
48 | #define CPIA2_SYSTEM_SERIAL_CTRL 0x06 | |
49 | #define CPIA2_SYSTEM_SERIAL_CTRL_NULL_CMD 0x00 | |
50 | #define CPIA2_SYSTEM_SERIAL_CTRL_START_CMD 0x01 | |
51 | #define CPIA2_SYSTEM_SERIAL_CTRL_STOP_CMD 0x02 | |
52 | #define CPIA2_SYSTEM_SERIAL_CTRL_WRITE_CMD 0x03 | |
53 | #define CPIA2_SYSTEM_SERIAL_CTRL_READ_ACK_CMD 0x04 | |
54 | #define CPIA2_SYSTEM_SERIAL_CTRL_READ_NACK_CMD 0x05 | |
55 | ||
56 | #define CPIA2_SYSTEM_SERIAL_DATA 0x07 | |
57 | ||
58 | #define CPIA2_SYSTEM_VP_SERIAL_ADDR 0x08 | |
59 | ||
60 | /*** | |
61 | * I2C addresses for various devices in CPiA2 | |
62 | ***/ | |
63 | #define CPIA2_SYSTEM_VP_SERIAL_ADDR_SENSOR 0x20 | |
64 | #define CPIA2_SYSTEM_VP_SERIAL_ADDR_VP 0x88 | |
65 | #define CPIA2_SYSTEM_VP_SERIAL_ADDR_676_VP 0x8A | |
66 | ||
67 | #define CPIA2_SYSTEM_SPARE_REG1 0x09 | |
68 | #define CPIA2_SYSTEM_SPARE_REG2 0x0A | |
69 | #define CPIA2_SYSTEM_SPARE_REG3 0x0B | |
70 | ||
71 | #define CPIA2_SYSTEM_MC_PORT_0 0x0C | |
72 | #define CPIA2_SYSTEM_MC_PORT_1 0x0D | |
73 | #define CPIA2_SYSTEM_MC_PORT_2 0x0E | |
74 | #define CPIA2_SYSTEM_MC_PORT_3 0x0F | |
75 | ||
76 | #define CPIA2_SYSTEM_STATUS_PKT 0x20 | |
77 | #define CPIA2_SYSTEM_STATUS_PKT_END 0x27 | |
78 | ||
79 | #define CPIA2_SYSTEM_DESCRIP_VID_HI 0x30 | |
80 | #define CPIA2_SYSTEM_DESCRIP_VID_LO 0x31 | |
81 | #define CPIA2_SYSTEM_DESCRIP_PID_HI 0x32 | |
82 | #define CPIA2_SYSTEM_DESCRIP_PID_LO 0x33 | |
83 | ||
84 | #define CPIA2_SYSTEM_FW_VERSION_HI 0x34 | |
85 | #define CPIA2_SYSTEM_FW_VERSION_LO 0x35 | |
86 | ||
87 | #define CPIA2_SYSTEM_CACHE_START_INDEX 0x80 | |
88 | #define CPIA2_SYSTEM_CACHE_MAX_WRITES 0x10 | |
89 | ||
90 | /*** | |
91 | * VC register set (Bank 1) | |
92 | ***/ | |
93 | #define CPIA2_VC_ASIC_ID 0x80 | |
94 | ||
95 | #define CPIA2_VC_ASIC_REV 0x81 | |
96 | ||
97 | #define CPIA2_VC_PW_CTRL 0x82 | |
98 | #define CPIA2_VC_PW_CTRL_COLDSTART 0x01 | |
99 | #define CPIA2_VC_PW_CTRL_CP_CLK_EN 0x02 | |
100 | #define CPIA2_VC_PW_CTRL_VP_RESET_N 0x04 | |
101 | #define CPIA2_VC_PW_CTRL_VC_CLK_EN 0x08 | |
102 | #define CPIA2_VC_PW_CTRL_VC_RESET_N 0x10 | |
103 | #define CPIA2_VC_PW_CTRL_GOTO_SUSPEND 0x20 | |
104 | #define CPIA2_VC_PW_CTRL_UDC_SUSPEND 0x40 | |
105 | #define CPIA2_VC_PW_CTRL_PWR_DOWN 0x80 | |
106 | ||
107 | #define CPIA2_VC_WAKEUP 0x83 | |
108 | #define CPIA2_VC_WAKEUP_SW_ENABLE 0x01 | |
109 | #define CPIA2_VC_WAKEUP_XX_ENABLE 0x02 | |
110 | #define CPIA2_VC_WAKEUP_SW_ATWAKEUP 0x04 | |
111 | #define CPIA2_VC_WAKEUP_XX_ATWAKEUP 0x08 | |
112 | ||
113 | #define CPIA2_VC_CLOCK_CTRL 0x84 | |
114 | #define CPIA2_VC_CLOCK_CTRL_TESTUP72 0x01 | |
115 | ||
116 | #define CPIA2_VC_INT_ENABLE 0x88 | |
117 | #define CPIA2_VC_INT_ENABLE_XX_IE 0x01 | |
118 | #define CPIA2_VC_INT_ENABLE_SW_IE 0x02 | |
119 | #define CPIA2_VC_INT_ENABLE_VC_IE 0x04 | |
120 | #define CPIA2_VC_INT_ENABLE_USBDATA_IE 0x08 | |
121 | #define CPIA2_VC_INT_ENABLE_USBSETUP_IE 0x10 | |
122 | #define CPIA2_VC_INT_ENABLE_USBCFG_IE 0x20 | |
123 | ||
124 | #define CPIA2_VC_INT_FLAG 0x89 | |
125 | #define CPIA2_VC_INT_ENABLE_XX_FLAG 0x01 | |
126 | #define CPIA2_VC_INT_ENABLE_SW_FLAG 0x02 | |
127 | #define CPIA2_VC_INT_ENABLE_VC_FLAG 0x04 | |
128 | #define CPIA2_VC_INT_ENABLE_USBDATA_FLAG 0x08 | |
129 | #define CPIA2_VC_INT_ENABLE_USBSETUP_FLAG 0x10 | |
130 | #define CPIA2_VC_INT_ENABLE_USBCFG_FLAG 0x20 | |
131 | #define CPIA2_VC_INT_ENABLE_SET_RESET_BIT 0x80 | |
132 | ||
133 | #define CPIA2_VC_INT_STATE 0x8A | |
134 | #define CPIA2_VC_INT_STATE_XX_STATE 0x01 | |
135 | #define CPIA2_VC_INT_STATE_SW_STATE 0x02 | |
136 | ||
137 | #define CPIA2_VC_MP_DIR 0x90 | |
138 | #define CPIA2_VC_MP_DIR_INPUT 0x00 | |
139 | #define CPIA2_VC_MP_DIR_OUTPUT 0x01 | |
140 | ||
141 | #define CPIA2_VC_MP_DATA 0x91 | |
142 | ||
143 | #define CPIA2_VC_DP_CTRL 0x98 | |
144 | #define CPIA2_VC_DP_CTRL_MODE_0 0x00 | |
145 | #define CPIA2_VC_DP_CTRL_MODE_A 0x01 | |
146 | #define CPIA2_VC_DP_CTRL_MODE_B 0x02 | |
147 | #define CPIA2_VC_DP_CTRL_MODE_C 0x03 | |
148 | #define CPIA2_VC_DP_CTRL_FAKE_FST 0x04 | |
149 | ||
150 | #define CPIA2_VC_AD_CTRL 0x99 | |
151 | #define CPIA2_VC_AD_CTRL_SRC_0 0x00 | |
152 | #define CPIA2_VC_AD_CTRL_SRC_DIGI_A 0x01 | |
153 | #define CPIA2_VC_AD_CTRL_SRC_REG 0x02 | |
154 | #define CPIA2_VC_AD_CTRL_DST_USB 0x00 | |
155 | #define CPIA2_VC_AD_CTRL_DST_REG 0x04 | |
156 | ||
157 | #define CPIA2_VC_AD_TEST_IN 0x9B | |
158 | ||
159 | #define CPIA2_VC_AD_TEST_OUT 0x9C | |
160 | ||
161 | #define CPIA2_VC_AD_STATUS 0x9D | |
162 | #define CPIA2_VC_AD_STATUS_EMPTY 0x01 | |
163 | #define CPIA2_VC_AD_STATUS_FULL 0x02 | |
164 | ||
165 | #define CPIA2_VC_DP_DATA 0x9E | |
166 | ||
167 | #define CPIA2_VC_ST_CTRL 0xA0 | |
168 | #define CPIA2_VC_ST_CTRL_SRC_VC 0x00 | |
169 | #define CPIA2_VC_ST_CTRL_SRC_DP 0x01 | |
170 | #define CPIA2_VC_ST_CTRL_SRC_REG 0x02 | |
171 | ||
172 | #define CPIA2_VC_ST_CTRL_RAW_SELECT 0x04 | |
173 | ||
174 | #define CPIA2_VC_ST_CTRL_DST_USB 0x00 | |
175 | #define CPIA2_VC_ST_CTRL_DST_DP 0x08 | |
176 | #define CPIA2_VC_ST_CTRL_DST_REG 0x10 | |
177 | ||
178 | #define CPIA2_VC_ST_CTRL_FIFO_ENABLE 0x20 | |
179 | #define CPIA2_VC_ST_CTRL_EOF_DETECT 0x40 | |
180 | ||
181 | #define CPIA2_VC_ST_TEST 0xA1 | |
182 | #define CPIA2_VC_ST_TEST_MODE_MANUAL 0x00 | |
183 | #define CPIA2_VC_ST_TEST_MODE_INCREMENT 0x02 | |
184 | ||
185 | #define CPIA2_VC_ST_TEST_AUTO_FILL 0x08 | |
186 | ||
187 | #define CPIA2_VC_ST_TEST_REPEAT_FIFO 0x10 | |
188 | ||
189 | #define CPIA2_VC_ST_TEST_IN 0xA2 | |
190 | ||
191 | #define CPIA2_VC_ST_TEST_OUT 0xA3 | |
192 | ||
193 | #define CPIA2_VC_ST_STATUS 0xA4 | |
194 | #define CPIA2_VC_ST_STATUS_EMPTY 0x01 | |
195 | #define CPIA2_VC_ST_STATUS_FULL 0x02 | |
196 | ||
197 | #define CPIA2_VC_ST_FRAME_DETECT_1 0xA5 | |
198 | ||
199 | #define CPIA2_VC_ST_FRAME_DETECT_2 0xA6 | |
200 | ||
201 | #define CPIA2_VC_USB_CTRL 0xA8 | |
202 | #define CPIA2_VC_USB_CTRL_CMD_STALLED 0x01 | |
203 | #define CPIA2_VC_USB_CTRL_CMD_READY 0x02 | |
204 | #define CPIA2_VC_USB_CTRL_CMD_STATUS 0x04 | |
205 | #define CPIA2_VC_USB_CTRL_CMD_STATUS_DIR 0x08 | |
206 | #define CPIA2_VC_USB_CTRL_CMD_NO_CLASH 0x10 | |
207 | #define CPIA2_VC_USB_CTRL_CMD_MICRO_ACCESS 0x80 | |
208 | ||
209 | #define CPIA2_VC_USB_STRM 0xA9 | |
210 | #define CPIA2_VC_USB_STRM_ISO_ENABLE 0x01 | |
211 | #define CPIA2_VC_USB_STRM_BLK_ENABLE 0x02 | |
212 | #define CPIA2_VC_USB_STRM_INT_ENABLE 0x04 | |
213 | #define CPIA2_VC_USB_STRM_AUD_ENABLE 0x08 | |
214 | ||
215 | #define CPIA2_VC_USB_STATUS 0xAA | |
216 | #define CPIA2_VC_USB_STATUS_CMD_IN_PROGRESS 0x01 | |
217 | #define CPIA2_VC_USB_STATUS_CMD_STATUS_STALL 0x02 | |
218 | #define CPIA2_VC_USB_STATUS_CMD_HANDSHAKE 0x04 | |
219 | #define CPIA2_VC_USB_STATUS_CMD_OVERRIDE 0x08 | |
220 | #define CPIA2_VC_USB_STATUS_CMD_FIFO_BUSY 0x10 | |
221 | #define CPIA2_VC_USB_STATUS_BULK_REPEAT_TXN 0x20 | |
222 | #define CPIA2_VC_USB_STATUS_CONFIG_DONE 0x40 | |
223 | #define CPIA2_VC_USB_STATUS_USB_SUSPEND 0x80 | |
224 | ||
225 | #define CPIA2_VC_USB_CMDW 0xAB | |
226 | ||
227 | #define CPIA2_VC_USB_DATARW 0xAC | |
228 | ||
229 | #define CPIA2_VC_USB_INFO 0xAD | |
230 | ||
231 | #define CPIA2_VC_USB_CONFIG 0xAE | |
232 | ||
233 | #define CPIA2_VC_USB_SETTINGS 0xAF | |
234 | #define CPIA2_VC_USB_SETTINGS_CONFIG_MASK 0x03 | |
235 | #define CPIA2_VC_USB_SETTINGS_INTERFACE_MASK 0x0C | |
236 | #define CPIA2_VC_USB_SETTINGS_ALTERNATE_MASK 0x70 | |
237 | ||
238 | #define CPIA2_VC_USB_ISOLIM 0xB0 | |
239 | ||
240 | #define CPIA2_VC_USB_ISOFAILS 0xB1 | |
241 | ||
242 | #define CPIA2_VC_USB_ISOMAXPKTHI 0xB2 | |
243 | ||
244 | #define CPIA2_VC_USB_ISOMAXPKTLO 0xB3 | |
245 | ||
246 | #define CPIA2_VC_V2W_CTRL 0xB8 | |
247 | #define CPIA2_VC_V2W_SELECT 0x01 | |
248 | ||
249 | #define CPIA2_VC_V2W_SCL 0xB9 | |
250 | ||
251 | #define CPIA2_VC_V2W_SDA 0xBA | |
252 | ||
253 | #define CPIA2_VC_VC_CTRL 0xC0 | |
254 | #define CPIA2_VC_VC_CTRL_RUN 0x01 | |
255 | #define CPIA2_VC_VC_CTRL_SINGLESHOT 0x02 | |
256 | #define CPIA2_VC_VC_CTRL_IDLING 0x04 | |
257 | #define CPIA2_VC_VC_CTRL_INHIBIT_H_TABLES 0x10 | |
258 | #define CPIA2_VC_VC_CTRL_INHIBIT_Q_TABLES 0x20 | |
259 | #define CPIA2_VC_VC_CTRL_INHIBIT_PRIVATE 0x40 | |
260 | ||
261 | #define CPIA2_VC_VC_RESTART_IVAL_HI 0xC1 | |
262 | ||
263 | #define CPIA2_VC_VC_RESTART_IVAL_LO 0xC2 | |
264 | ||
265 | #define CPIA2_VC_VC_FORMAT 0xC3 | |
266 | #define CPIA2_VC_VC_FORMAT_UFIRST 0x01 | |
267 | #define CPIA2_VC_VC_FORMAT_MONO 0x02 | |
268 | #define CPIA2_VC_VC_FORMAT_DECIMATING 0x04 | |
269 | #define CPIA2_VC_VC_FORMAT_SHORTLINE 0x08 | |
270 | #define CPIA2_VC_VC_FORMAT_SELFTEST 0x10 | |
271 | ||
272 | #define CPIA2_VC_VC_CLOCKS 0xC4 | |
273 | #define CPIA2_VC_VC_CLOCKS_CLKDIV_MASK 0x03 | |
274 | #define CPIA2_VC_VC_672_CLOCKS_CIF_DIV_BY_3 0x04 | |
275 | #define CPIA2_VC_VC_672_CLOCKS_SCALING 0x08 | |
276 | #define CPIA2_VC_VC_CLOCKS_LOGDIV0 0x00 | |
277 | #define CPIA2_VC_VC_CLOCKS_LOGDIV1 0x01 | |
278 | #define CPIA2_VC_VC_CLOCKS_LOGDIV2 0x02 | |
279 | #define CPIA2_VC_VC_CLOCKS_LOGDIV3 0x03 | |
280 | #define CPIA2_VC_VC_676_CLOCKS_CIF_DIV_BY_3 0x08 | |
281 | #define CPIA2_VC_VC_676_CLOCKS_SCALING 0x10 | |
282 | ||
283 | #define CPIA2_VC_VC_IHSIZE_LO 0xC5 | |
284 | ||
285 | #define CPIA2_VC_VC_XLIM_HI 0xC6 | |
286 | ||
287 | #define CPIA2_VC_VC_XLIM_LO 0xC7 | |
288 | ||
289 | #define CPIA2_VC_VC_YLIM_HI 0xC8 | |
290 | ||
291 | #define CPIA2_VC_VC_YLIM_LO 0xC9 | |
292 | ||
293 | #define CPIA2_VC_VC_OHSIZE 0xCA | |
294 | ||
295 | #define CPIA2_VC_VC_OVSIZE 0xCB | |
296 | ||
297 | #define CPIA2_VC_VC_HCROP 0xCC | |
298 | ||
299 | #define CPIA2_VC_VC_VCROP 0xCD | |
300 | ||
301 | #define CPIA2_VC_VC_HPHASE 0xCE | |
302 | ||
303 | #define CPIA2_VC_VC_VPHASE 0xCF | |
304 | ||
305 | #define CPIA2_VC_VC_HISPAN 0xD0 | |
306 | ||
307 | #define CPIA2_VC_VC_VISPAN 0xD1 | |
308 | ||
309 | #define CPIA2_VC_VC_HICROP 0xD2 | |
310 | ||
311 | #define CPIA2_VC_VC_VICROP 0xD3 | |
312 | ||
313 | #define CPIA2_VC_VC_HFRACT 0xD4 | |
314 | #define CPIA2_VC_VC_HFRACT_DEN_MASK 0x0F | |
315 | #define CPIA2_VC_VC_HFRACT_NUM_MASK 0xF0 | |
316 | ||
317 | #define CPIA2_VC_VC_VFRACT 0xD5 | |
318 | #define CPIA2_VC_VC_VFRACT_DEN_MASK 0x0F | |
319 | #define CPIA2_VC_VC_VFRACT_NUM_MASK 0xF0 | |
320 | ||
321 | #define CPIA2_VC_VC_JPEG_OPT 0xD6 | |
322 | #define CPIA2_VC_VC_JPEG_OPT_DOUBLE_SQUEEZE 0x01 | |
323 | #define CPIA2_VC_VC_JPEG_OPT_NO_DC_AUTO_SQUEEZE 0x02 | |
324 | #define CPIA2_VC_VC_JPEG_OPT_AUTO_SQUEEZE 0x04 | |
325 | #define CPIA2_VC_VC_JPEG_OPT_DEFAULT (CPIA2_VC_VC_JPEG_OPT_DOUBLE_SQUEEZE|\ | |
326 | CPIA2_VC_VC_JPEG_OPT_AUTO_SQUEEZE) | |
327 | ||
328 | ||
329 | #define CPIA2_VC_VC_CREEP_PERIOD 0xD7 | |
330 | #define CPIA2_VC_VC_USER_SQUEEZE 0xD8 | |
331 | #define CPIA2_VC_VC_TARGET_KB 0xD9 | |
332 | ||
333 | #define CPIA2_VC_VC_AUTO_SQUEEZE 0xE6 | |
334 | ||
335 | ||
336 | /*** | |
337 | * VP register set (Bank 2) | |
338 | ***/ | |
339 | #define CPIA2_VP_DEVICEH 0 | |
340 | #define CPIA2_VP_DEVICEL 1 | |
341 | ||
342 | #define CPIA2_VP_SYSTEMSTATE 0x02 | |
343 | #define CPIA2_VP_SYSTEMSTATE_HK_ALIVE 0x01 | |
344 | ||
345 | #define CPIA2_VP_SYSTEMCTRL 0x03 | |
346 | #define CPIA2_VP_SYSTEMCTRL_REQ_CLEAR_ERROR 0x80 | |
347 | #define CPIA2_VP_SYSTEMCTRL_POWER_DOWN_PLL 0x20 | |
348 | #define CPIA2_VP_SYSTEMCTRL_REQ_SUSPEND_STATE 0x10 | |
349 | #define CPIA2_VP_SYSTEMCTRL_REQ_SERIAL_WAKEUP 0x08 | |
350 | #define CPIA2_VP_SYSTEMCTRL_REQ_AUTOLOAD 0x04 | |
351 | #define CPIA2_VP_SYSTEMCTRL_HK_CONTROL 0x02 | |
352 | #define CPIA2_VP_SYSTEMCTRL_POWER_CONTROL 0x01 | |
353 | ||
354 | #define CPIA2_VP_SENSOR_FLAGS 0x05 | |
355 | #define CPIA2_VP_SENSOR_FLAGS_404 0x01 | |
356 | #define CPIA2_VP_SENSOR_FLAGS_407 0x02 | |
357 | #define CPIA2_VP_SENSOR_FLAGS_409 0x04 | |
358 | #define CPIA2_VP_SENSOR_FLAGS_410 0x08 | |
359 | #define CPIA2_VP_SENSOR_FLAGS_500 0x10 | |
360 | ||
361 | #define CPIA2_VP_SENSOR_REV 0x06 | |
362 | ||
363 | #define CPIA2_VP_DEVICE_CONFIG 0x07 | |
364 | #define CPIA2_VP_DEVICE_CONFIG_SERIAL_BRIDGE 0x01 | |
365 | ||
366 | #define CPIA2_VP_GPIO_DIRECTION 0x08 | |
367 | #define CPIA2_VP_GPIO_READ 0xFF | |
368 | #define CPIA2_VP_GPIO_WRITE 0x00 | |
369 | ||
370 | #define CPIA2_VP_GPIO_DATA 0x09 | |
371 | ||
372 | #define CPIA2_VP_RAM_ADDR_H 0x0A | |
373 | #define CPIA2_VP_RAM_ADDR_L 0x0B | |
374 | #define CPIA2_VP_RAM_DATA 0x0C | |
375 | ||
376 | #define CPIA2_VP_PATCH_REV 0x0F | |
377 | ||
378 | #define CPIA2_VP4_USER_MODE 0x10 | |
379 | #define CPIA2_VP5_USER_MODE 0x13 | |
380 | #define CPIA2_VP_USER_MODE_CIF 0x01 | |
381 | #define CPIA2_VP_USER_MODE_QCIFDS 0x02 | |
382 | #define CPIA2_VP_USER_MODE_QCIFPTC 0x04 | |
383 | #define CPIA2_VP_USER_MODE_QVGADS 0x08 | |
384 | #define CPIA2_VP_USER_MODE_QVGAPTC 0x10 | |
385 | #define CPIA2_VP_USER_MODE_VGA 0x20 | |
386 | ||
387 | #define CPIA2_VP4_FRAMERATE_REQUEST 0x11 | |
388 | #define CPIA2_VP5_FRAMERATE_REQUEST 0x14 | |
389 | #define CPIA2_VP_FRAMERATE_60 0x80 | |
390 | #define CPIA2_VP_FRAMERATE_50 0x40 | |
391 | #define CPIA2_VP_FRAMERATE_30 0x20 | |
392 | #define CPIA2_VP_FRAMERATE_25 0x10 | |
393 | #define CPIA2_VP_FRAMERATE_15 0x08 | |
394 | #define CPIA2_VP_FRAMERATE_12_5 0x04 | |
395 | #define CPIA2_VP_FRAMERATE_7_5 0x02 | |
396 | #define CPIA2_VP_FRAMERATE_6_25 0x01 | |
397 | ||
398 | #define CPIA2_VP4_USER_EFFECTS 0x12 | |
399 | #define CPIA2_VP5_USER_EFFECTS 0x15 | |
400 | #define CPIA2_VP_USER_EFFECTS_COLBARS 0x01 | |
401 | #define CPIA2_VP_USER_EFFECTS_COLBARS_GRAD 0x02 | |
402 | #define CPIA2_VP_USER_EFFECTS_MIRROR 0x04 | |
403 | #define CPIA2_VP_USER_EFFECTS_FLIP 0x40 // VP5 only | |
404 | ||
405 | /* NOTE: CPIA2_VP_EXPOSURE_MODES shares the same register as VP5 User | |
406 | * Effects */ | |
407 | #define CPIA2_VP_EXPOSURE_MODES 0x15 | |
408 | #define CPIA2_VP_EXPOSURE_MODES_INHIBIT_FLICKER 0x20 | |
409 | #define CPIA2_VP_EXPOSURE_MODES_COMPILE_EXP 0x10 | |
410 | ||
411 | #define CPIA2_VP4_EXPOSURE_TARGET 0x16 // VP4 | |
412 | #define CPIA2_VP5_EXPOSURE_TARGET 0x20 // VP5 | |
413 | ||
414 | #define CPIA2_VP_FLICKER_MODES 0x1B | |
415 | #define CPIA2_VP_FLICKER_MODES_50HZ 0x80 | |
416 | #define CPIA2_VP_FLICKER_MODES_CUSTOM_FLT_FFREQ 0x40 | |
417 | #define CPIA2_VP_FLICKER_MODES_NEVER_FLICKER 0x20 | |
418 | #define CPIA2_VP_FLICKER_MODES_INHIBIT_RUB 0x10 | |
419 | #define CPIA2_VP_FLICKER_MODES_ADJUST_LINE_FREQ 0x08 | |
420 | #define CPIA2_VP_FLICKER_MODES_CUSTOM_INT_FFREQ 0x04 | |
421 | ||
422 | #define CPIA2_VP_UMISC 0x1D | |
423 | #define CPIA2_VP_UMISC_FORCE_MONO 0x80 | |
424 | #define CPIA2_VP_UMISC_FORCE_ID_MASK 0x40 | |
425 | #define CPIA2_VP_UMISC_INHIBIT_AUTO_FGS 0x20 | |
426 | #define CPIA2_VP_UMISC_INHIBIT_AUTO_DIMS 0x08 | |
427 | #define CPIA2_VP_UMISC_OPT_FOR_SENSOR_DS 0x04 | |
428 | #define CPIA2_VP_UMISC_INHIBIT_AUTO_MODE_INT 0x02 | |
429 | ||
430 | #define CPIA2_VP5_ANTIFLKRSETUP 0x22 //34 | |
431 | ||
432 | #define CPIA2_VP_INTERPOLATION 0x24 | |
433 | #define CPIA2_VP_INTERPOLATION_EVEN_FIRST 0x40 | |
434 | #define CPIA2_VP_INTERPOLATION_HJOG 0x20 | |
435 | #define CPIA2_VP_INTERPOLATION_VJOG 0x10 | |
436 | ||
437 | #define CPIA2_VP_GAMMA 0x25 | |
438 | #define CPIA2_VP_DEFAULT_GAMMA 0x10 | |
439 | ||
440 | #define CPIA2_VP_YRANGE 0x26 | |
441 | ||
442 | #define CPIA2_VP_SATURATION 0x27 | |
443 | ||
444 | #define CPIA2_VP5_MYBLACK_LEVEL 0x3A //58 | |
445 | #define CPIA2_VP5_MCYRANGE 0x3B //59 | |
446 | #define CPIA2_VP5_MYCEILING 0x3C //60 | |
447 | #define CPIA2_VP5_MCUVSATURATION 0x3D //61 | |
448 | ||
449 | ||
450 | #define CPIA2_VP_REHASH_VALUES 0x60 | |
451 | ||
452 | ||
453 | /*** | |
454 | * Common sensor registers | |
455 | ***/ | |
456 | #define CPIA2_SENSOR_DEVICE_H 0x00 | |
457 | #define CPIA2_SENSOR_DEVICE_L 0x01 | |
458 | ||
459 | #define CPIA2_SENSOR_DATA_FORMAT 0x16 | |
460 | #define CPIA2_SENSOR_DATA_FORMAT_HMIRROR 0x08 | |
461 | #define CPIA2_SENSOR_DATA_FORMAT_VMIRROR 0x10 | |
462 | ||
463 | #define CPIA2_SENSOR_CR1 0x76 | |
464 | #define CPIA2_SENSOR_CR1_STAND_BY 0x01 | |
465 | #define CPIA2_SENSOR_CR1_DOWN_RAMP_GEN 0x02 | |
466 | #define CPIA2_SENSOR_CR1_DOWN_COLUMN_ADC 0x04 | |
467 | #define CPIA2_SENSOR_CR1_DOWN_CAB_REGULATOR 0x08 | |
468 | #define CPIA2_SENSOR_CR1_DOWN_AUDIO_REGULATOR 0x10 | |
469 | #define CPIA2_SENSOR_CR1_DOWN_VRT_AMP 0x20 | |
470 | #define CPIA2_SENSOR_CR1_DOWN_BAND_GAP 0x40 | |
471 | ||
472 | #endif |