[mirror_ubuntu-artful-kernel.git] / drivers / media / usb / gspca / stv06xx / stv06xx_hdcs.h

/*
 * Copyright (c) 2001 Jean-Fredric Clere, Nikolas Zimmermann, Georg Acher
 *		      Mark Cave-Ayland, Carlo E Prelz, Dick Streefland
 * Copyright (c) 2002, 2003 Tuukka Toivonen
 * Copyright (c) 2008 Erik Andrén
 * Copyright (c) 2008 Chia-I Wu
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * P/N 861037:      Sensor HDCS1000        ASIC STV0600
 * P/N 861050-0010: Sensor HDCS1000        ASIC STV0600
 * P/N 861050-0020: Sensor Photobit PB100  ASIC STV0600-1 - QuickCam Express
 * P/N 861055:      Sensor ST VV6410       ASIC STV0610   - LEGO cam
 * P/N 861075-0040: Sensor HDCS1000        ASIC
 * P/N 961179-0700: Sensor ST VV6410       ASIC STV0602   - Dexxa WebCam USB
 * P/N 861040-0000: Sensor ST VV6410       ASIC STV0610   - QuickCam Web
 */

#ifndef STV06XX_HDCS_H_
#define STV06XX_HDCS_H_

#include "stv06xx_sensor.h"

#define HDCS_REG_CONFIG(sd)	(IS_1020(sd) ? HDCS20_CONFIG : HDCS00_CONFIG)
#define HDCS_REG_CONTROL(sd)	(IS_1020(sd) ? HDCS20_CONTROL : HDCS00_CONTROL)

#define HDCS_1X00_DEF_WIDTH	360
#define HDCS_1X00_DEF_HEIGHT	296

#define HDCS_1020_DEF_WIDTH	352
#define HDCS_1020_DEF_HEIGHT	292

#define HDCS_1020_BOTTOM_Y_SKIP	4

#define HDCS_CLK_FREQ_MHZ	25

#define HDCS_ADC_START_SIG_DUR	3

/* LSB bit of I2C or register address signifies write (0) or read (1) */
/* I2C Registers common for both HDCS-1000/1100 and HDCS-1020 */
/* Identifications Register */
#define HDCS_IDENT		(0x00 << 1)
/* Status Register */
#define HDCS_STATUS		(0x01 << 1)
/* Interrupt Mask Register */
#define HDCS_IMASK		(0x02 << 1)
/* Pad Control Register */
#define HDCS_PCTRL		(0x03 << 1)
/* Pad Drive Control Register */
#define HDCS_PDRV		(0x04 << 1)
/* Interface Control Register */
#define HDCS_ICTRL		(0x05 << 1)
/* Interface Timing Register */
#define HDCS_ITMG		(0x06 << 1)
/* Baud Fraction Register */
#define HDCS_BFRAC		(0x07 << 1)
/* Baud Rate Register */
#define HDCS_BRATE		(0x08 << 1)
/* ADC Control Register */
#define HDCS_ADCCTRL		(0x09 << 1)
/* First Window Row Register */
#define HDCS_FWROW		(0x0a << 1)
/* First Window Column Register */
#define HDCS_FWCOL		(0x0b << 1)
/* Last Window Row Register */
#define HDCS_LWROW		(0x0c << 1)
/* Last Window Column Register */
#define HDCS_LWCOL		(0x0d << 1)
/* Timing Control Register */
#define HDCS_TCTRL		(0x0e << 1)
/* PGA Gain Register: Even Row, Even Column */
#define HDCS_ERECPGA		(0x0f << 1)
/* PGA Gain Register: Even Row, Odd Column */
#define HDCS_EROCPGA		(0x10 << 1)
/* PGA Gain Register: Odd Row, Even Column */
#define HDCS_ORECPGA		(0x11 << 1)
/* PGA Gain Register: Odd Row, Odd Column */
#define HDCS_OROCPGA		(0x12 << 1)
/* Row Exposure Low Register */
#define HDCS_ROWEXPL		(0x13 << 1)
/* Row Exposure High Register */
#define HDCS_ROWEXPH		(0x14 << 1)

/* I2C Registers only for HDCS-1000/1100 */
/* Sub-Row Exposure Low Register */
#define HDCS00_SROWEXPL		(0x15 << 1)
/* Sub-Row Exposure High Register */
#define HDCS00_SROWEXPH		(0x16 << 1)
/* Configuration Register */
#define HDCS00_CONFIG		(0x17 << 1)
/* Control Register */
#define HDCS00_CONTROL		(0x18 << 1)

/* I2C Registers only for HDCS-1020 */
/* Sub-Row Exposure Register */
#define HDCS20_SROWEXP		(0x15 << 1)
/* Error Control Register */
#define HDCS20_ERROR		(0x16 << 1)
/* Interface Timing 2 Register */
#define HDCS20_ITMG2		(0x17 << 1)
/* Interface Control 2 Register	*/
#define HDCS20_ICTRL2		(0x18 << 1)
/* Horizontal Blank Register */
#define HDCS20_HBLANK		(0x19 << 1)
/* Vertical Blank Register */
#define HDCS20_VBLANK		(0x1a << 1)
/* Configuration Register */
#define HDCS20_CONFIG		(0x1b << 1)
/* Control Register */
#define HDCS20_CONTROL		(0x1c << 1)

#define HDCS_RUN_ENABLE		(1 << 2)
#define HDCS_SLEEP_MODE		(1 << 1)

#define HDCS_DEFAULT_EXPOSURE	48
#define HDCS_DEFAULT_GAIN	50

static int hdcs_probe_1x00(struct sd *sd);
static int hdcs_probe_1020(struct sd *sd);
static int hdcs_start(struct sd *sd);
static int hdcs_init(struct sd *sd);
static int hdcs_init_controls(struct sd *sd);
static int hdcs_stop(struct sd *sd);
static int hdcs_dump(struct sd *sd);

static int hdcs_set_exposure(struct gspca_dev *gspca_dev, __s32 val);
static int hdcs_set_gain(struct gspca_dev *gspca_dev, __s32 val);

const struct stv06xx_sensor stv06xx_sensor_hdcs1x00 = {
	.name = "HP HDCS-1000/1100",
	.i2c_flush = 0,
	.i2c_addr = (0x55 << 1),
	.i2c_len = 1,

	/* FIXME (see if we can lower min_packet_size, needs testing, and also
	   adjusting framerate when the bandwidth gets lower) */
	.min_packet_size = { 847 },
	.max_packet_size = { 847 },

	.init = hdcs_init,
	.init_controls = hdcs_init_controls,
	.probe = hdcs_probe_1x00,
	.start = hdcs_start,
	.stop = hdcs_stop,
	.dump = hdcs_dump,
};

const struct stv06xx_sensor stv06xx_sensor_hdcs1020 = {
	.name = "HDCS-1020",
	.i2c_flush = 0,
	.i2c_addr = (0x55 << 1),
	.i2c_len = 1,

	/* FIXME (see if we can lower min_packet_size, needs testing, and also
	   adjusting framerate when the bandwidthm gets lower) */
	.min_packet_size = { 847 },
	.max_packet_size = { 847 },

	.init = hdcs_init,
	.init_controls = hdcs_init_controls,
	.probe = hdcs_probe_1020,
	.start = hdcs_start,
	.stop = hdcs_stop,
	.dump = hdcs_dump,
};

static const u16 stv_bridge_init[][2] = {
	{STV_ISO_ENABLE, 0},
	{STV_REG23, 0},
	{STV_REG00, 0x1d},
	{STV_REG01, 0xb5},
	{STV_REG02, 0xa8},
	{STV_REG03, 0x95},
	{STV_REG04, 0x07},

	{STV_SCAN_RATE, 0x20},
	{STV_Y_CTRL, 0x01},
	{STV_X_CTRL, 0x0a}
};

static const u8 stv_sensor_init[][2] = {
	/* Clear status (writing 1 will clear the corresponding status bit) */
	{HDCS_STATUS, BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1)},
	/* Disable all interrupts */
	{HDCS_IMASK, 0x00},
	{HDCS_PCTRL, BIT(6) | BIT(5) | BIT(1) | BIT(0)},
	{HDCS_PDRV,  0x00},
	{HDCS_ICTRL, BIT(5)},
	{HDCS_ITMG,  BIT(4) | BIT(1)},
	/* ADC output resolution to 10 bits */
	{HDCS_ADCCTRL, 10}
};

#endif
Commit	Line	Data
4c98834a EA	1	/*
	2	* Copyright (c) 2001 Jean-Fredric Clere, Nikolas Zimmermann, Georg Acher
	3	* Mark Cave-Ayland, Carlo E Prelz, Dick Streefland
	4	* Copyright (c) 2002, 2003 Tuukka Toivonen
	5	* Copyright (c) 2008 Erik Andrén
	6	* Copyright (c) 2008 Chia-I Wu
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
4c98834a EA	18	* P/N 861037: Sensor HDCS1000 ASIC STV0600
	19	* P/N 861050-0010: Sensor HDCS1000 ASIC STV0600
	20	* P/N 861050-0020: Sensor Photobit PB100 ASIC STV0600-1 - QuickCam Express
	21	* P/N 861055: Sensor ST VV6410 ASIC STV0610 - LEGO cam
	22	* P/N 861075-0040: Sensor HDCS1000 ASIC
	23	* P/N 961179-0700: Sensor ST VV6410 ASIC STV0602 - Dexxa WebCam USB
	24	* P/N 861040-0000: Sensor ST VV6410 ASIC STV0610 - QuickCam Web
	25	*/
	26
	27	#ifndef STV06XX_HDCS_H_
	28	#define STV06XX_HDCS_H_
	29
	30	#include "stv06xx_sensor.h"
	31
	32	#define HDCS_REG_CONFIG(sd) (IS_1020(sd) ? HDCS20_CONFIG : HDCS00_CONFIG)
	33	#define HDCS_REG_CONTROL(sd) (IS_1020(sd) ? HDCS20_CONTROL : HDCS00_CONTROL)
	34
	35	#define HDCS_1X00_DEF_WIDTH 360
780e3121	36	#define HDCS_1X00_DEF_HEIGHT 296
4c98834a EA	37
	38	#define HDCS_1020_DEF_WIDTH 352
	39	#define HDCS_1020_DEF_HEIGHT 292
	40
	41	#define HDCS_1020_BOTTOM_Y_SKIP 4
	42
	43	#define HDCS_CLK_FREQ_MHZ 25
	44
	45	#define HDCS_ADC_START_SIG_DUR 3
	46
	47	/* LSB bit of I2C or register address signifies write (0) or read (1) */
	48	/* I2C Registers common for both HDCS-1000/1100 and HDCS-1020 */
	49	/* Identifications Register */
	50	#define HDCS_IDENT (0x00 << 1)
	51	/* Status Register */
	52	#define HDCS_STATUS (0x01 << 1)
	53	/* Interrupt Mask Register */
	54	#define HDCS_IMASK (0x02 << 1)
	55	/* Pad Control Register */
	56	#define HDCS_PCTRL (0x03 << 1)
	57	/* Pad Drive Control Register */
	58	#define HDCS_PDRV (0x04 << 1)
	59	/* Interface Control Register */
	60	#define HDCS_ICTRL (0x05 << 1)
	61	/* Interface Timing Register */
	62	#define HDCS_ITMG (0x06 << 1)
	63	/* Baud Fraction Register */
	64	#define HDCS_BFRAC (0x07 << 1)
	65	/* Baud Rate Register */
	66	#define HDCS_BRATE (0x08 << 1)
	67	/* ADC Control Register */
	68	#define HDCS_ADCCTRL (0x09 << 1)
	69	/* First Window Row Register */
	70	#define HDCS_FWROW (0x0a << 1)
	71	/* First Window Column Register */
	72	#define HDCS_FWCOL (0x0b << 1)
	73	/* Last Window Row Register */
	74	#define HDCS_LWROW (0x0c << 1)
	75	/* Last Window Column Register */
	76	#define HDCS_LWCOL (0x0d << 1)
	77	/* Timing Control Register */
	78	#define HDCS_TCTRL (0x0e << 1)
	79	/* PGA Gain Register: Even Row, Even Column */
	80	#define HDCS_ERECPGA (0x0f << 1)
	81	/* PGA Gain Register: Even Row, Odd Column */
	82	#define HDCS_EROCPGA (0x10 << 1)
	83	/* PGA Gain Register: Odd Row, Even Column */
	84	#define HDCS_ORECPGA (0x11 << 1)
	85	/* PGA Gain Register: Odd Row, Odd Column */
	86	#define HDCS_OROCPGA (0x12 << 1)
	87	/* Row Exposure Low Register */
	88	#define HDCS_ROWEXPL (0x13 << 1)
	89	/* Row Exposure High Register */
	90	#define HDCS_ROWEXPH (0x14 << 1)
	91
	92	/* I2C Registers only for HDCS-1000/1100 */
	93	/* Sub-Row Exposure Low Register */
	94	#define HDCS00_SROWEXPL (0x15 << 1)
	95	/* Sub-Row Exposure High Register */
	96	#define HDCS00_SROWEXPH (0x16 << 1)
	97	/* Configuration Register */
	98	#define HDCS00_CONFIG (0x17 << 1)
	99	/* Control Register */
	100	#define HDCS00_CONTROL (0x18 << 1)
101
102	/* I2C Registers only for HDCS-1020 */
103	/* Sub-Row Exposure Register */
104	#define HDCS20_SROWEXP (0x15 << 1)
105	/* Error Control Register */
106	#define HDCS20_ERROR (0x16 << 1)
107	/* Interface Timing 2 Register */
108	#define HDCS20_ITMG2 (0x17 << 1)
109	/* Interface Control 2 Register */
110	#define HDCS20_ICTRL2 (0x18 << 1)
111	/* Horizontal Blank Register */
112	#define HDCS20_HBLANK (0x19 << 1)
113	/* Vertical Blank Register */
114	#define HDCS20_VBLANK (0x1a << 1)
115	/* Configuration Register */
116	#define HDCS20_CONFIG (0x1b << 1)
117	/* Control Register */
118	#define HDCS20_CONTROL (0x1c << 1)
119
120	#define HDCS_RUN_ENABLE (1 << 2)
121	#define HDCS_SLEEP_MODE (1 << 1)
122
35ccf8f8	123	#define HDCS_DEFAULT_EXPOSURE 48
5ff01d54	124	#define HDCS_DEFAULT_GAIN 50
4c98834a EA	125
	126	static int hdcs_probe_1x00(struct sd *sd);
	127	static int hdcs_probe_1020(struct sd *sd);
	128	static int hdcs_start(struct sd *sd);
	129	static int hdcs_init(struct sd *sd);
dec9c514	130	static int hdcs_init_controls(struct sd *sd);
4c98834a EA	131	static int hdcs_stop(struct sd *sd);
4c98834a EA	132	static int hdcs_dump(struct sd *sd);
4c98834a	133
4c98834a EA	134	static int hdcs_set_exposure(struct gspca_dev *gspca_dev, __s32 val);
4c98834a EA	135	static int hdcs_set_gain(struct gspca_dev *gspca_dev, __s32 val);
4c98834a EA	136
	137	const struct stv06xx_sensor stv06xx_sensor_hdcs1x00 = {
	138	.name = "HP HDCS-1000/1100",
	139	.i2c_flush = 0,
	140	.i2c_addr = (0x55 << 1),
	141	.i2c_len = 1,
	142
c0b33bdc HG	143	/* FIXME (see if we can lower min_packet_size, needs testing, and also
	144	adjusting framerate when the bandwidth gets lower) */
	145	.min_packet_size = { 847 },
	146	.max_packet_size = { 847 },
	147
4c98834a	148	.init = hdcs_init,
dec9c514	149	.init_controls = hdcs_init_controls,
4c98834a EA	150	.probe = hdcs_probe_1x00,
	151	.start = hdcs_start,
	152	.stop = hdcs_stop,
4c98834a	153	.dump = hdcs_dump,
4c98834a EA	154	};
	155
	156	const struct stv06xx_sensor stv06xx_sensor_hdcs1020 = {
	157	.name = "HDCS-1020",
	158	.i2c_flush = 0,
	159	.i2c_addr = (0x55 << 1),
	160	.i2c_len = 1,
	161
c0b33bdc HG	162	/* FIXME (see if we can lower min_packet_size, needs testing, and also
	163	adjusting framerate when the bandwidthm gets lower) */
	164	.min_packet_size = { 847 },
	165	.max_packet_size = { 847 },
	166
4c98834a	167	.init = hdcs_init,
dec9c514	168	.init_controls = hdcs_init_controls,
4c98834a EA	169	.probe = hdcs_probe_1020,
	170	.start = hdcs_start,
	171	.stop = hdcs_stop,
	172	.dump = hdcs_dump,
4c98834a EA	173	};
	174
	175	static const u16 stv_bridge_init[][2] = {
	176	{STV_ISO_ENABLE, 0},
	177	{STV_REG23, 0},
	178	{STV_REG00, 0x1d},
	179	{STV_REG01, 0xb5},
	180	{STV_REG02, 0xa8},
	181	{STV_REG03, 0x95},
	182	{STV_REG04, 0x07},
	183
	184	{STV_SCAN_RATE, 0x20},
4c98834a EA	185	{STV_Y_CTRL, 0x01},
	186	{STV_X_CTRL, 0x0a}
	187	};
	188
	189	static const u8 stv_sensor_init[][2] = {
	190	/* Clear status (writing 1 will clear the corresponding status bit) */
	191	{HDCS_STATUS, BIT(6) \| BIT(5) \| BIT(4) \| BIT(3) \| BIT(2) \| BIT(1)},
	192	/* Disable all interrupts */
	193	{HDCS_IMASK, 0x00},
	194	{HDCS_PCTRL, BIT(6) \| BIT(5) \| BIT(1) \| BIT(0)},
	195	{HDCS_PDRV, 0x00},
	196	{HDCS_ICTRL, BIT(5)},
	197	{HDCS_ITMG, BIT(4) \| BIT(1)},
	198	/* ADC output resolution to 10 bits */
	199	{HDCS_ADCCTRL, 10}
	200	};
	201
	202	#endif