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[mirror_ubuntu-hirsute-kernel.git] / drivers / media / usb / gspca / w996Xcf.c
CommitLineData
a511ba94
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1/**
2 *
3 * GSPCA sub driver for W996[78]CF JPEG USB Dual Mode Camera Chip.
4 *
5 * Copyright (C) 2009 Hans de Goede <hdegoede@redhat.com>
6 *
7 * This module is adapted from the in kernel v4l1 w9968cf driver:
8 *
9 * Copyright (C) 2002-2004 by Luca Risolia <luca.risolia@studio.unibo.it>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
a511ba94
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21 */
22
23/* Note this is not a stand alone driver, it gets included in ov519.c, this
24 is a bit of a hack, but it needs the driver code for a lot of different
25 ov sensors which is already present in ov519.c (the old v4l1 driver used
26 the ovchipcam framework). When we have the time we really should move
27 the sensor drivers to v4l2 sub drivers, and properly split of this
28 driver from ov519.c */
29
133a9fe9
JP
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
79b35902 32#define W9968CF_I2C_BUS_DELAY 4 /* delay in us for I2C bit r/w operations */
a511ba94 33
9a731a32
JFM
34#define Y_QUANTABLE (&sd->jpeg_hdr[JPEG_QT0_OFFSET])
35#define UV_QUANTABLE (&sd->jpeg_hdr[JPEG_QT1_OFFSET])
a511ba94
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36
37static const struct v4l2_pix_format w9968cf_vga_mode[] = {
38 {160, 120, V4L2_PIX_FMT_UYVY, V4L2_FIELD_NONE,
39 .bytesperline = 160 * 2,
40 .sizeimage = 160 * 120 * 2,
41 .colorspace = V4L2_COLORSPACE_JPEG},
42 {176, 144, V4L2_PIX_FMT_UYVY, V4L2_FIELD_NONE,
43 .bytesperline = 176 * 2,
44 .sizeimage = 176 * 144 * 2,
45 .colorspace = V4L2_COLORSPACE_JPEG},
79b35902 46 {320, 240, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
a511ba94
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47 .bytesperline = 320 * 2,
48 .sizeimage = 320 * 240 * 2,
49 .colorspace = V4L2_COLORSPACE_JPEG},
79b35902 50 {352, 288, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
a511ba94
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51 .bytesperline = 352 * 2,
52 .sizeimage = 352 * 288 * 2,
53 .colorspace = V4L2_COLORSPACE_JPEG},
79b35902 54 {640, 480, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
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55 .bytesperline = 640 * 2,
56 .sizeimage = 640 * 480 * 2,
79b35902 57 .colorspace = V4L2_COLORSPACE_JPEG},
a511ba94
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58};
59
f8f20188 60static void reg_w(struct sd *sd, u16 index, u16 value);
a511ba94
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61
62/*--------------------------------------------------------------------------
63 Write 64-bit data to the fast serial bus registers.
64 Return 0 on success, -1 otherwise.
65 --------------------------------------------------------------------------*/
f8f20188 66static void w9968cf_write_fsb(struct sd *sd, u16* data)
a511ba94 67{
780e3121 68 struct usb_device *udev = sd->gspca_dev.dev;
a511ba94
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69 u16 value;
70 int ret;
71
f8f20188
JFM
72 if (sd->gspca_dev.usb_err < 0)
73 return;
74
a511ba94
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75 value = *data++;
76 memcpy(sd->gspca_dev.usb_buf, data, 6);
77
f7c7ac48
WP
78 /* Avoid things going to fast for the bridge with a xhci host */
79 udelay(150);
a511ba94
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80 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 0,
81 USB_TYPE_VENDOR | USB_DIR_OUT | USB_RECIP_DEVICE,
82 value, 0x06, sd->gspca_dev.usb_buf, 6, 500);
83 if (ret < 0) {
133a9fe9 84 pr_err("Write FSB registers failed (%d)\n", ret);
f8f20188 85 sd->gspca_dev.usb_err = ret;
a511ba94 86 }
a511ba94
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87}
88
89/*--------------------------------------------------------------------------
90 Write data to the serial bus control register.
91 Return 0 on success, a negative number otherwise.
92 --------------------------------------------------------------------------*/
f8f20188 93static void w9968cf_write_sb(struct sd *sd, u16 value)
a511ba94
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94{
95 int ret;
96
f8f20188
JFM
97 if (sd->gspca_dev.usb_err < 0)
98 return;
99
f7c7ac48
WP
100 /* Avoid things going to fast for the bridge with a xhci host */
101 udelay(150);
102
a511ba94
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103 /* We don't use reg_w here, as that would cause all writes when
104 bitbanging i2c to be logged, making the logs impossible to read */
105 ret = usb_control_msg(sd->gspca_dev.dev,
106 usb_sndctrlpipe(sd->gspca_dev.dev, 0),
107 0,
108 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
109 value, 0x01, NULL, 0, 500);
110
111 udelay(W9968CF_I2C_BUS_DELAY);
112
113 if (ret < 0) {
133a9fe9 114 pr_err("Write SB reg [01] %04x failed\n", value);
f8f20188 115 sd->gspca_dev.usb_err = ret;
a511ba94 116 }
a511ba94
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117}
118
119/*--------------------------------------------------------------------------
120 Read data from the serial bus control register.
121 Return 0 on success, a negative number otherwise.
122 --------------------------------------------------------------------------*/
123static int w9968cf_read_sb(struct sd *sd)
124{
125 int ret;
126
f8f20188
JFM
127 if (sd->gspca_dev.usb_err < 0)
128 return -1;
129
f7c7ac48
WP
130 /* Avoid things going to fast for the bridge with a xhci host */
131 udelay(150);
132
a511ba94
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133 /* We don't use reg_r here, as the w9968cf is special and has 16
134 bit registers instead of 8 bit */
135 ret = usb_control_msg(sd->gspca_dev.dev,
136 usb_rcvctrlpipe(sd->gspca_dev.dev, 0),
137 1,
138 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
139 0, 0x01, sd->gspca_dev.usb_buf, 2, 500);
f8f20188 140 if (ret >= 0) {
a511ba94
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141 ret = sd->gspca_dev.usb_buf[0] |
142 (sd->gspca_dev.usb_buf[1] << 8);
f8f20188 143 } else {
133a9fe9 144 pr_err("Read SB reg [01] failed\n");
f8f20188
JFM
145 sd->gspca_dev.usb_err = ret;
146 }
a511ba94
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147
148 udelay(W9968CF_I2C_BUS_DELAY);
149
150 return ret;
151}
152
153/*--------------------------------------------------------------------------
154 Upload quantization tables for the JPEG compression.
155 This function is called by w9968cf_start_transfer().
156 Return 0 on success, a negative number otherwise.
157 --------------------------------------------------------------------------*/
f8f20188 158static void w9968cf_upload_quantizationtables(struct sd *sd)
a511ba94
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159{
160 u16 a, b;
f8f20188 161 int i, j;
a511ba94 162
f8f20188 163 reg_w(sd, 0x39, 0x0010); /* JPEG clock enable */
a511ba94
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164
165 for (i = 0, j = 0; i < 32; i++, j += 2) {
87bae740
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166 a = Y_QUANTABLE[j] | ((unsigned)(Y_QUANTABLE[j + 1]) << 8);
167 b = UV_QUANTABLE[j] | ((unsigned)(UV_QUANTABLE[j + 1]) << 8);
168 reg_w(sd, 0x40 + i, a);
169 reg_w(sd, 0x60 + i, b);
a511ba94 170 }
f8f20188 171 reg_w(sd, 0x39, 0x0012); /* JPEG encoder enable */
a511ba94
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172}
173
174/****************************************************************************
175 * Low-level I2C I/O functions. *
176 * The adapter supports the following I2C transfer functions: *
177 * i2c_adap_fastwrite_byte_data() (at 400 kHz bit frequency only) *
178 * i2c_adap_read_byte_data() *
179 * i2c_adap_read_byte() *
180 ****************************************************************************/
181
f8f20188 182static void w9968cf_smbus_start(struct sd *sd)
a511ba94 183{
f8f20188
JFM
184 w9968cf_write_sb(sd, 0x0011); /* SDE=1, SDA=0, SCL=1 */
185 w9968cf_write_sb(sd, 0x0010); /* SDE=1, SDA=0, SCL=0 */
a511ba94
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186}
187
f8f20188 188static void w9968cf_smbus_stop(struct sd *sd)
a511ba94 189{
f8f20188
JFM
190 w9968cf_write_sb(sd, 0x0010); /* SDE=1, SDA=0, SCL=0 */
191 w9968cf_write_sb(sd, 0x0011); /* SDE=1, SDA=0, SCL=1 */
192 w9968cf_write_sb(sd, 0x0013); /* SDE=1, SDA=1, SCL=1 */
a511ba94
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193}
194
f8f20188 195static void w9968cf_smbus_write_byte(struct sd *sd, u8 v)
a511ba94
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196{
197 u8 bit;
f8f20188 198 int sda;
a511ba94
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199
200 for (bit = 0 ; bit < 8 ; bit++) {
201 sda = (v & 0x80) ? 2 : 0;
202 v <<= 1;
203 /* SDE=1, SDA=sda, SCL=0 */
f8f20188 204 w9968cf_write_sb(sd, 0x10 | sda);
a511ba94 205 /* SDE=1, SDA=sda, SCL=1 */
f8f20188 206 w9968cf_write_sb(sd, 0x11 | sda);
a511ba94 207 /* SDE=1, SDA=sda, SCL=0 */
f8f20188 208 w9968cf_write_sb(sd, 0x10 | sda);
a511ba94 209 }
a511ba94
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210}
211
f8f20188 212static void w9968cf_smbus_read_byte(struct sd *sd, u8 *v)
a511ba94
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213{
214 u8 bit;
a511ba94
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215
216 /* No need to ensure SDA is high as we are always called after
217 read_ack which ends with SDA high */
218 *v = 0;
219 for (bit = 0 ; bit < 8 ; bit++) {
220 *v <<= 1;
221 /* SDE=1, SDA=1, SCL=1 */
f8f20188 222 w9968cf_write_sb(sd, 0x0013);
a511ba94
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223 *v |= (w9968cf_read_sb(sd) & 0x0008) ? 1 : 0;
224 /* SDE=1, SDA=1, SCL=0 */
f8f20188 225 w9968cf_write_sb(sd, 0x0012);
a511ba94 226 }
a511ba94
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227}
228
f8f20188 229static void w9968cf_smbus_write_nack(struct sd *sd)
a511ba94 230{
a511ba94
HG
231 /* No need to ensure SDA is high as we are always called after
232 read_byte which ends with SDA high */
f8f20188
JFM
233 w9968cf_write_sb(sd, 0x0013); /* SDE=1, SDA=1, SCL=1 */
234 w9968cf_write_sb(sd, 0x0012); /* SDE=1, SDA=1, SCL=0 */
a511ba94
HG
235}
236
f8f20188 237static void w9968cf_smbus_read_ack(struct sd *sd)
a511ba94 238{
c93396e1 239 struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
f8f20188 240 int sda;
a511ba94
HG
241
242 /* Ensure SDA is high before raising clock to avoid a spurious stop */
f8f20188
JFM
243 w9968cf_write_sb(sd, 0x0012); /* SDE=1, SDA=1, SCL=0 */
244 w9968cf_write_sb(sd, 0x0013); /* SDE=1, SDA=1, SCL=1 */
a511ba94 245 sda = w9968cf_read_sb(sd);
f8f20188
JFM
246 w9968cf_write_sb(sd, 0x0012); /* SDE=1, SDA=1, SCL=0 */
247 if (sda >= 0 && (sda & 0x08)) {
a511ba94 248 PDEBUG(D_USBI, "Did not receive i2c ACK");
f8f20188 249 sd->gspca_dev.usb_err = -EIO;
a511ba94 250 }
a511ba94
HG
251}
252
253/* SMBus protocol: S Addr Wr [A] Subaddr [A] Value [A] P */
f8f20188 254static void w9968cf_i2c_w(struct sd *sd, u8 reg, u8 value)
a511ba94 255{
c93396e1 256 struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
a511ba94 257 u16* data = (u16 *)sd->gspca_dev.usb_buf;
a511ba94
HG
258
259 data[0] = 0x082f | ((sd->sensor_addr & 0x80) ? 0x1500 : 0x0);
260 data[0] |= (sd->sensor_addr & 0x40) ? 0x4000 : 0x0;
261 data[1] = 0x2082 | ((sd->sensor_addr & 0x40) ? 0x0005 : 0x0);
262 data[1] |= (sd->sensor_addr & 0x20) ? 0x0150 : 0x0;
263 data[1] |= (sd->sensor_addr & 0x10) ? 0x5400 : 0x0;
264 data[2] = 0x8208 | ((sd->sensor_addr & 0x08) ? 0x0015 : 0x0);
265 data[2] |= (sd->sensor_addr & 0x04) ? 0x0540 : 0x0;
266 data[2] |= (sd->sensor_addr & 0x02) ? 0x5000 : 0x0;
267 data[3] = 0x1d20 | ((sd->sensor_addr & 0x02) ? 0x0001 : 0x0);
268 data[3] |= (sd->sensor_addr & 0x01) ? 0x0054 : 0x0;
269
f8f20188 270 w9968cf_write_fsb(sd, data);
a511ba94
HG
271
272 data[0] = 0x8208 | ((reg & 0x80) ? 0x0015 : 0x0);
273 data[0] |= (reg & 0x40) ? 0x0540 : 0x0;
274 data[0] |= (reg & 0x20) ? 0x5000 : 0x0;
275 data[1] = 0x0820 | ((reg & 0x20) ? 0x0001 : 0x0);
276 data[1] |= (reg & 0x10) ? 0x0054 : 0x0;
277 data[1] |= (reg & 0x08) ? 0x1500 : 0x0;
278 data[1] |= (reg & 0x04) ? 0x4000 : 0x0;
279 data[2] = 0x2082 | ((reg & 0x04) ? 0x0005 : 0x0);
280 data[2] |= (reg & 0x02) ? 0x0150 : 0x0;
281 data[2] |= (reg & 0x01) ? 0x5400 : 0x0;
282 data[3] = 0x001d;
283
f8f20188 284 w9968cf_write_fsb(sd, data);
a511ba94
HG
285
286 data[0] = 0x8208 | ((value & 0x80) ? 0x0015 : 0x0);
287 data[0] |= (value & 0x40) ? 0x0540 : 0x0;
288 data[0] |= (value & 0x20) ? 0x5000 : 0x0;
289 data[1] = 0x0820 | ((value & 0x20) ? 0x0001 : 0x0);
290 data[1] |= (value & 0x10) ? 0x0054 : 0x0;
291 data[1] |= (value & 0x08) ? 0x1500 : 0x0;
292 data[1] |= (value & 0x04) ? 0x4000 : 0x0;
293 data[2] = 0x2082 | ((value & 0x04) ? 0x0005 : 0x0);
294 data[2] |= (value & 0x02) ? 0x0150 : 0x0;
295 data[2] |= (value & 0x01) ? 0x5400 : 0x0;
296 data[3] = 0xfe1d;
297
f8f20188 298 w9968cf_write_fsb(sd, data);
a511ba94 299
f8f20188 300 PDEBUG(D_USBO, "i2c 0x%02x -> [0x%02x]", value, reg);
a511ba94
HG
301}
302
303/* SMBus protocol: S Addr Wr [A] Subaddr [A] P S Addr+1 Rd [A] [Value] NA P */
304static int w9968cf_i2c_r(struct sd *sd, u8 reg)
305{
c93396e1 306 struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
a511ba94
HG
307 int ret = 0;
308 u8 value;
309
310 /* Fast serial bus data control disable */
f8f20188
JFM
311 w9968cf_write_sb(sd, 0x0013); /* don't change ! */
312
313 w9968cf_smbus_start(sd);
314 w9968cf_smbus_write_byte(sd, sd->sensor_addr);
315 w9968cf_smbus_read_ack(sd);
316 w9968cf_smbus_write_byte(sd, reg);
317 w9968cf_smbus_read_ack(sd);
318 w9968cf_smbus_stop(sd);
319 w9968cf_smbus_start(sd);
320 w9968cf_smbus_write_byte(sd, sd->sensor_addr + 1);
321 w9968cf_smbus_read_ack(sd);
322 w9968cf_smbus_read_byte(sd, &value);
a511ba94
HG
323 /* signal we don't want to read anymore, the v4l1 driver used to
324 send an ack here which is very wrong! (and then fixed
325 the issues this gave by retrying reads) */
f8f20188
JFM
326 w9968cf_smbus_write_nack(sd);
327 w9968cf_smbus_stop(sd);
a511ba94
HG
328
329 /* Fast serial bus data control re-enable */
f8f20188 330 w9968cf_write_sb(sd, 0x0030);
a511ba94 331
f8f20188 332 if (sd->gspca_dev.usb_err >= 0) {
a511ba94
HG
333 ret = value;
334 PDEBUG(D_USBI, "i2c [0x%02X] -> 0x%02X", reg, value);
335 } else
c93396e1 336 PERR("i2c read [0x%02x] failed", reg);
a511ba94
HG
337
338 return ret;
339}
340
a511ba94
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341/*--------------------------------------------------------------------------
342 Turn on the LED on some webcams. A beep should be heard too.
343 Return 0 on success, a negative number otherwise.
344 --------------------------------------------------------------------------*/
f8f20188 345static void w9968cf_configure(struct sd *sd)
a511ba94 346{
f8f20188
JFM
347 reg_w(sd, 0x00, 0xff00); /* power-down */
348 reg_w(sd, 0x00, 0xbf17); /* reset everything */
349 reg_w(sd, 0x00, 0xbf10); /* normal operation */
350 reg_w(sd, 0x01, 0x0010); /* serial bus, SDS high */
351 reg_w(sd, 0x01, 0x0000); /* serial bus, SDS low */
352 reg_w(sd, 0x01, 0x0010); /* ..high 'beep-beep' */
353 reg_w(sd, 0x01, 0x0030); /* Set sda scl to FSB mode */
a511ba94
HG
354
355 sd->stopped = 1;
a511ba94
HG
356}
357
f8f20188 358static void w9968cf_init(struct sd *sd)
a511ba94 359{
a511ba94
HG
360 unsigned long hw_bufsize = sd->sif ? (352 * 288 * 2) : (640 * 480 * 2),
361 y0 = 0x0000,
87bae740
JFM
362 u0 = y0 + hw_bufsize / 2,
363 v0 = u0 + hw_bufsize / 4,
364 y1 = v0 + hw_bufsize / 4,
365 u1 = y1 + hw_bufsize / 2,
366 v1 = u1 + hw_bufsize / 4;
a511ba94 367
f8f20188
JFM
368 reg_w(sd, 0x00, 0xff00); /* power off */
369 reg_w(sd, 0x00, 0xbf10); /* power on */
a511ba94 370
f8f20188
JFM
371 reg_w(sd, 0x03, 0x405d); /* DRAM timings */
372 reg_w(sd, 0x04, 0x0030); /* SDRAM timings */
a511ba94 373
f8f20188
JFM
374 reg_w(sd, 0x20, y0 & 0xffff); /* Y buf.0, low */
375 reg_w(sd, 0x21, y0 >> 16); /* Y buf.0, high */
376 reg_w(sd, 0x24, u0 & 0xffff); /* U buf.0, low */
377 reg_w(sd, 0x25, u0 >> 16); /* U buf.0, high */
378 reg_w(sd, 0x28, v0 & 0xffff); /* V buf.0, low */
379 reg_w(sd, 0x29, v0 >> 16); /* V buf.0, high */
a511ba94 380
f8f20188
JFM
381 reg_w(sd, 0x22, y1 & 0xffff); /* Y buf.1, low */
382 reg_w(sd, 0x23, y1 >> 16); /* Y buf.1, high */
383 reg_w(sd, 0x26, u1 & 0xffff); /* U buf.1, low */
384 reg_w(sd, 0x27, u1 >> 16); /* U buf.1, high */
385 reg_w(sd, 0x2a, v1 & 0xffff); /* V buf.1, low */
386 reg_w(sd, 0x2b, v1 >> 16); /* V buf.1, high */
a511ba94 387
f8f20188
JFM
388 reg_w(sd, 0x32, y1 & 0xffff); /* JPEG buf 0 low */
389 reg_w(sd, 0x33, y1 >> 16); /* JPEG buf 0 high */
a511ba94 390
f8f20188
JFM
391 reg_w(sd, 0x34, y1 & 0xffff); /* JPEG buf 1 low */
392 reg_w(sd, 0x35, y1 >> 16); /* JPEG bug 1 high */
a511ba94 393
f8f20188
JFM
394 reg_w(sd, 0x36, 0x0000);/* JPEG restart interval */
395 reg_w(sd, 0x37, 0x0804);/*JPEG VLE FIFO threshold*/
396 reg_w(sd, 0x38, 0x0000);/* disable hw up-scaling */
397 reg_w(sd, 0x3f, 0x0000); /* JPEG/MCTL test data */
a511ba94
HG
398}
399
f8f20188 400static void w9968cf_set_crop_window(struct sd *sd)
a511ba94 401{
f8f20188 402 int start_cropx, start_cropy, x, y, fw, fh, cw, ch,
a511ba94
HG
403 max_width, max_height;
404
405 if (sd->sif) {
406 max_width = 352;
407 max_height = 288;
408 } else {
409 max_width = 640;
410 max_height = 480;
411 }
412
413 if (sd->sensor == SEN_OV7620) {
cf9211e8
HV
414 /*
415 * Sigh, this is dependend on the clock / framerate changes
416 * made by the frequency control, sick.
417 *
418 * Note we cannot use v4l2_ctrl_g_ctrl here, as we get called
419 * from ov519.c:setfreq() with the ctrl lock held!
420 */
421 if (sd->freq->val == 1) {
73997870
HG
422 start_cropx = 277;
423 start_cropy = 37;
a511ba94 424 } else {
73997870
HG
425 start_cropx = 105;
426 start_cropy = 37;
a511ba94
HG
427 }
428 } else {
429 start_cropx = 320;
430 start_cropy = 35;
431 }
432
433 /* Work around to avoid FP arithmetics */
434 #define SC(x) ((x) << 10)
435
436 /* Scaling factors */
1966bc2a
OZ
437 fw = SC(sd->gspca_dev.pixfmt.width) / max_width;
438 fh = SC(sd->gspca_dev.pixfmt.height) / max_height;
a511ba94 439
1966bc2a
OZ
440 cw = (fw >= fh) ? max_width : SC(sd->gspca_dev.pixfmt.width) / fh;
441 ch = (fw >= fh) ? SC(sd->gspca_dev.pixfmt.height) / fw : max_height;
a511ba94
HG
442
443 sd->sensor_width = max_width;
444 sd->sensor_height = max_height;
445
446 x = (max_width - cw) / 2;
447 y = (max_height - ch) / 2;
448
f8f20188
JFM
449 reg_w(sd, 0x10, start_cropx + x);
450 reg_w(sd, 0x11, start_cropy + y);
451 reg_w(sd, 0x12, start_cropx + x + cw);
452 reg_w(sd, 0x13, start_cropy + y + ch);
a511ba94
HG
453}
454
f8f20188 455static void w9968cf_mode_init_regs(struct sd *sd)
a511ba94 456{
f8f20188 457 int val, vs_polarity, hs_polarity;
a511ba94 458
f8f20188 459 w9968cf_set_crop_window(sd);
a511ba94 460
1966bc2a
OZ
461 reg_w(sd, 0x14, sd->gspca_dev.pixfmt.width);
462 reg_w(sd, 0x15, sd->gspca_dev.pixfmt.height);
a511ba94
HG
463
464 /* JPEG width & height */
1966bc2a
OZ
465 reg_w(sd, 0x30, sd->gspca_dev.pixfmt.width);
466 reg_w(sd, 0x31, sd->gspca_dev.pixfmt.height);
a511ba94
HG
467
468 /* Y & UV frame buffer strides (in WORD) */
79b35902
HG
469 if (w9968cf_vga_mode[sd->gspca_dev.curr_mode].pixelformat ==
470 V4L2_PIX_FMT_JPEG) {
1966bc2a
OZ
471 reg_w(sd, 0x2c, sd->gspca_dev.pixfmt.width / 2);
472 reg_w(sd, 0x2d, sd->gspca_dev.pixfmt.width / 4);
79b35902 473 } else
1966bc2a 474 reg_w(sd, 0x2c, sd->gspca_dev.pixfmt.width);
a511ba94 475
f8f20188
JFM
476 reg_w(sd, 0x00, 0xbf17); /* reset everything */
477 reg_w(sd, 0x00, 0xbf10); /* normal operation */
a511ba94 478
79b35902 479 /* Transfer size in WORDS (for UYVY format only) */
1966bc2a 480 val = sd->gspca_dev.pixfmt.width * sd->gspca_dev.pixfmt.height;
f8f20188
JFM
481 reg_w(sd, 0x3d, val & 0xffff); /* low bits */
482 reg_w(sd, 0x3e, val >> 16); /* high bits */
a511ba94 483
79b35902
HG
484 if (w9968cf_vga_mode[sd->gspca_dev.curr_mode].pixelformat ==
485 V4L2_PIX_FMT_JPEG) {
486 /* We may get called multiple times (usb isoc bw negotiat.) */
1966bc2a
OZ
487 jpeg_define(sd->jpeg_hdr, sd->gspca_dev.pixfmt.height,
488 sd->gspca_dev.pixfmt.width, 0x22); /* JPEG 420 */
cf9211e8 489 jpeg_set_qual(sd->jpeg_hdr, v4l2_ctrl_g_ctrl(sd->jpegqual));
f8f20188 490 w9968cf_upload_quantizationtables(sd);
cf9211e8 491 v4l2_ctrl_grab(sd->jpegqual, true);
79b35902
HG
492 }
493
a511ba94
HG
494 /* Video Capture Control Register */
495 if (sd->sensor == SEN_OV7620) {
496 /* Seems to work around a bug in the image sensor */
497 vs_polarity = 1;
498 hs_polarity = 1;
499 } else {
500 vs_polarity = 1;
501 hs_polarity = 0;
502 }
503
504 val = (vs_polarity << 12) | (hs_polarity << 11);
505
79b35902
HG
506 /* NOTE: We may not have enough memory to do double buffering while
507 doing compression (amount of memory differs per model cam).
508 So we use the second image buffer also as jpeg stream buffer
509 (see w9968cf_init), and disable double buffering. */
510 if (w9968cf_vga_mode[sd->gspca_dev.curr_mode].pixelformat ==
511 V4L2_PIX_FMT_JPEG) {
512 /* val |= 0x0002; YUV422P */
513 val |= 0x0003; /* YUV420P */
514 } else
a511ba94
HG
515 val |= 0x0080; /* Enable HW double buffering */
516
517 /* val |= 0x0020; enable clamping */
518 /* val |= 0x0008; enable (1-2-1) filter */
519 /* val |= 0x000c; enable (2-3-6-3-2) filter */
520
521 val |= 0x8000; /* capt. enable */
522
f8f20188 523 reg_w(sd, 0x16, val);
a511ba94
HG
524
525 sd->gspca_dev.empty_packet = 0;
a511ba94
HG
526}
527
79b35902
HG
528static void w9968cf_stop0(struct sd *sd)
529{
cf9211e8 530 v4l2_ctrl_grab(sd->jpegqual, false);
d65174c0
JFM
531 reg_w(sd, 0x39, 0x0000); /* disable JPEG encoder */
532 reg_w(sd, 0x16, 0x0000); /* stop video capture */
79b35902
HG
533}
534
535/* The w9968cf docs say that a 0 sized packet means EOF (and also SOF
536 for the next frame). This seems to simply not be true when operating
537 in JPEG mode, in this case there may be empty packets within the
538 frame. So in JPEG mode use the JPEG SOI marker to detect SOF.
539
540 Note to make things even more interesting the w9968cf sends *PLANAR* jpeg,
541 to be precise it sends: SOI, SOF, DRI, SOS, Y-data, SOS, U-data, SOS,
542 V-data, EOI. */
a511ba94 543static void w9968cf_pkt_scan(struct gspca_dev *gspca_dev,
76dd272b 544 u8 *data, /* isoc packet */
a511ba94
HG
545 int len) /* iso packet length */
546{
79b35902
HG
547 struct sd *sd = (struct sd *) gspca_dev;
548
549 if (w9968cf_vga_mode[gspca_dev->curr_mode].pixelformat ==
550 V4L2_PIX_FMT_JPEG) {
551 if (len >= 2 &&
552 data[0] == 0xff &&
553 data[1] == 0xd8) {
76dd272b 554 gspca_frame_add(gspca_dev, LAST_PACKET,
8394bcf3 555 NULL, 0);
76dd272b 556 gspca_frame_add(gspca_dev, FIRST_PACKET,
79b35902
HG
557 sd->jpeg_hdr, JPEG_HDR_SZ);
558 /* Strip the ff d8, our own header (which adds
559 huffman and quantization tables) already has this */
560 len -= 2;
561 data += 2;
562 }
563 } else {
564 /* In UYVY mode an empty packet signals EOF */
565 if (gspca_dev->empty_packet) {
76dd272b 566 gspca_frame_add(gspca_dev, LAST_PACKET,
79b35902 567 NULL, 0);
76dd272b 568 gspca_frame_add(gspca_dev, FIRST_PACKET,
79b35902
HG
569 NULL, 0);
570 gspca_dev->empty_packet = 0;
571 }
a511ba94 572 }
76dd272b 573 gspca_frame_add(gspca_dev, INTER_PACKET, data, len);
a511ba94 574}