[mirror_ubuntu-artful-kernel.git] / drivers / media / usb / pvrusb2 / pvrusb2-encoder.c

/*
 *
 *
 *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
 *  Copyright (C) 2004 Aurelien Alleaume <slts@free.fr>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 */

#include <linux/device.h>   // for linux/firmware.h
#include <linux/firmware.h>
#include "pvrusb2-util.h"
#include "pvrusb2-encoder.h"
#include "pvrusb2-hdw-internal.h"
#include "pvrusb2-debug.h"
#include "pvrusb2-fx2-cmd.h"


/* Firmware mailbox flags - definitions found from ivtv */
#define IVTV_MBOX_FIRMWARE_DONE 0x00000004
#define IVTV_MBOX_DRIVER_DONE 0x00000002
#define IVTV_MBOX_DRIVER_BUSY 0x00000001

#define MBOX_BASE 0x44


static int pvr2_encoder_write_words(struct pvr2_hdw *hdw,
				    unsigned int offs,
				    const u32 *data, unsigned int dlen)
{
	unsigned int idx,addr;
	unsigned int bAddr;
	int ret;
	unsigned int chunkCnt;

	/*

	Format: First byte must be 0x01.  Remaining 32 bit words are
	spread out into chunks of 7 bytes each, with the first 4 bytes
	being the data word (little endian), and the next 3 bytes
	being the address where that data word is to be written (big
	endian).  Repeat request for additional words, with offset
	adjusted accordingly.

	*/
	while (dlen) {
		chunkCnt = 8;
		if (chunkCnt > dlen) chunkCnt = dlen;
		memset(hdw->cmd_buffer,0,sizeof(hdw->cmd_buffer));
		bAddr = 0;
		hdw->cmd_buffer[bAddr++] = FX2CMD_MEM_WRITE_DWORD;
		for (idx = 0; idx < chunkCnt; idx++) {
			addr = idx + offs;
			hdw->cmd_buffer[bAddr+6] = (addr & 0xffu);
			hdw->cmd_buffer[bAddr+5] = ((addr>>8) & 0xffu);
			hdw->cmd_buffer[bAddr+4] = ((addr>>16) & 0xffu);
			PVR2_DECOMPOSE_LE(hdw->cmd_buffer, bAddr,data[idx]);
			bAddr += 7;
		}
		ret = pvr2_send_request(hdw,
					hdw->cmd_buffer,1+(chunkCnt*7),
					NULL,0);
		if (ret) return ret;
		data += chunkCnt;
		dlen -= chunkCnt;
		offs += chunkCnt;
	}

	return 0;
}


static int pvr2_encoder_read_words(struct pvr2_hdw *hdw,
				   unsigned int offs,
				   u32 *data, unsigned int dlen)
{
	unsigned int idx;
	int ret;
	unsigned int chunkCnt;

	/*

	Format: First byte must be 0x02 (status check) or 0x28 (read
	back block of 32 bit words).  Next 6 bytes must be zero,
	followed by a single byte of MBOX_BASE+offset for portion to
	be read.  Returned data is packed set of 32 bits words that
	were read.

	*/

	while (dlen) {
		chunkCnt = 16;
		if (chunkCnt > dlen) chunkCnt = dlen;
		if (chunkCnt < 16) chunkCnt = 1;
		hdw->cmd_buffer[0] =
			((chunkCnt == 1) ?
			 FX2CMD_MEM_READ_DWORD : FX2CMD_MEM_READ_64BYTES);
		hdw->cmd_buffer[1] = 0;
		hdw->cmd_buffer[2] = 0;
		hdw->cmd_buffer[3] = 0;
		hdw->cmd_buffer[4] = 0;
		hdw->cmd_buffer[5] = ((offs>>16) & 0xffu);
		hdw->cmd_buffer[6] = ((offs>>8) & 0xffu);
		hdw->cmd_buffer[7] = (offs & 0xffu);
		ret = pvr2_send_request(hdw,
					hdw->cmd_buffer,8,
					hdw->cmd_buffer,
					(chunkCnt == 1 ? 4 : 16 * 4));
		if (ret) return ret;

		for (idx = 0; idx < chunkCnt; idx++) {
			data[idx] = PVR2_COMPOSE_LE(hdw->cmd_buffer,idx*4);
		}
		data += chunkCnt;
		dlen -= chunkCnt;
		offs += chunkCnt;
	}

	return 0;
}


/* This prototype is set up to be compatible with the
   cx2341x_mbox_func prototype in cx2341x.h, which should be in
   kernels 2.6.18 or later.  We do this so that we can enable
   cx2341x.ko to write to our encoder (by handing it a pointer to this
   function).  For earlier kernels this doesn't really matter. */
static int pvr2_encoder_cmd(void *ctxt,
			    u32 cmd,
			    int arg_cnt_send,
			    int arg_cnt_recv,
			    u32 *argp)
{
	unsigned int poll_count;
	unsigned int try_count = 0;
	int retry_flag;
	int ret = 0;
	unsigned int idx;
	/* These sizes look to be limited by the FX2 firmware implementation */
	u32 wrData[16];
	u32 rdData[16];
	struct pvr2_hdw *hdw = (struct pvr2_hdw *)ctxt;


	/*

	The encoder seems to speak entirely using blocks 32 bit words.
	In ivtv driver terms, this is a mailbox at MBOX_BASE which we
	populate with data and watch what the hardware does with it.
	The first word is a set of flags used to control the
	transaction, the second word is the command to execute, the
	third byte is zero (ivtv driver suggests that this is some
	kind of return value), and the fourth byte is a specified
	timeout (windows driver always uses 0x00060000 except for one
	case when it is zero).  All successive words are the argument
	words for the command.

	First, write out the entire set of words, with the first word
	being zero.

	Next, write out just the first word again, but set it to
	IVTV_MBOX_DRIVER_DONE | IVTV_DRIVER_BUSY this time (which
	probably means "go").

	Next, read back the return count words.  Check the first word,
	which should have IVTV_MBOX_FIRMWARE_DONE set.  If however
	that bit is not set, then the command isn't done so repeat the
	read until it is set.

	Finally, write out just the first word again, but set it to
	0x0 this time (which probably means "idle").

	*/

	if (arg_cnt_send > (ARRAY_SIZE(wrData) - 4)) {
		pvr2_trace(
			PVR2_TRACE_ERROR_LEGS,
			"Failed to write cx23416 command - too many input arguments (was given %u limit %lu)",
			arg_cnt_send, (long unsigned) ARRAY_SIZE(wrData) - 4);
		return -EINVAL;
	}

	if (arg_cnt_recv > (ARRAY_SIZE(rdData) - 4)) {
		pvr2_trace(
			PVR2_TRACE_ERROR_LEGS,
			"Failed to write cx23416 command - too many return arguments (was given %u limit %lu)",
			arg_cnt_recv, (long unsigned) ARRAY_SIZE(rdData) - 4);
		return -EINVAL;
	}


	LOCK_TAKE(hdw->ctl_lock); do {

		if (!hdw->state_encoder_ok) {
			ret = -EIO;
			break;
		}

		retry_flag = 0;
		try_count++;
		ret = 0;
		wrData[0] = 0;
		wrData[1] = cmd;
		wrData[2] = 0;
		wrData[3] = 0x00060000;
		for (idx = 0; idx < arg_cnt_send; idx++) {
			wrData[idx+4] = argp[idx];
		}
		for (; idx < ARRAY_SIZE(wrData) - 4; idx++) {
			wrData[idx+4] = 0;
		}

		ret = pvr2_encoder_write_words(hdw,MBOX_BASE,wrData,idx);
		if (ret) break;
		wrData[0] = IVTV_MBOX_DRIVER_DONE|IVTV_MBOX_DRIVER_BUSY;
		ret = pvr2_encoder_write_words(hdw,MBOX_BASE,wrData,1);
		if (ret) break;
		poll_count = 0;
		while (1) {
			poll_count++;
			ret = pvr2_encoder_read_words(hdw,MBOX_BASE,rdData,
						      arg_cnt_recv+4);
			if (ret) {
				break;
			}
			if (rdData[0] & IVTV_MBOX_FIRMWARE_DONE) {
				break;
			}
			if (rdData[0] && (poll_count < 1000)) continue;
			if (!rdData[0]) {
				retry_flag = !0;
				pvr2_trace(
					PVR2_TRACE_ERROR_LEGS,
					"Encoder timed out waiting for us; arranging to retry");
			} else {
				pvr2_trace(
					PVR2_TRACE_ERROR_LEGS,
					"***WARNING*** device's encoder appears to be stuck (status=0x%08x)",
rdData[0]);
			}
			pvr2_trace(
				PVR2_TRACE_ERROR_LEGS,
				"Encoder command: 0x%02x",cmd);
			for (idx = 4; idx < arg_cnt_send; idx++) {
				pvr2_trace(
					PVR2_TRACE_ERROR_LEGS,
					"Encoder arg%d: 0x%08x",
					idx-3,wrData[idx]);
			}
			ret = -EBUSY;
			break;
		}
		if (retry_flag) {
			if (try_count < 20) continue;
			pvr2_trace(
				PVR2_TRACE_ERROR_LEGS,
				"Too many retries...");
			ret = -EBUSY;
		}
		if (ret) {
			del_timer_sync(&hdw->encoder_run_timer);
			hdw->state_encoder_ok = 0;
			pvr2_trace(PVR2_TRACE_STBITS,
				   "State bit %s <-- %s",
				   "state_encoder_ok",
				   (hdw->state_encoder_ok ? "true" : "false"));
			if (hdw->state_encoder_runok) {
				hdw->state_encoder_runok = 0;
				pvr2_trace(PVR2_TRACE_STBITS,
				   "State bit %s <-- %s",
					   "state_encoder_runok",
					   (hdw->state_encoder_runok ?
					    "true" : "false"));
			}
			pvr2_trace(
				PVR2_TRACE_ERROR_LEGS,
				"Giving up on command.  This is normally recovered via a firmware reload and re-initialization; concern is only warranted if this happens repeatedly and rapidly.");
			break;
		}
		wrData[0] = 0x7;
		for (idx = 0; idx < arg_cnt_recv; idx++) {
			argp[idx] = rdData[idx+4];
		}

		wrData[0] = 0x0;
		ret = pvr2_encoder_write_words(hdw,MBOX_BASE,wrData,1);
		if (ret) break;

	} while(0); LOCK_GIVE(hdw->ctl_lock);

	return ret;
}


static int pvr2_encoder_vcmd(struct pvr2_hdw *hdw, int cmd,
			     int args, ...)
{
	va_list vl;
	unsigned int idx;
	u32 data[12];

	if (args > ARRAY_SIZE(data)) {
		pvr2_trace(
			PVR2_TRACE_ERROR_LEGS,
			"Failed to write cx23416 command - too many arguments (was given %u limit %lu)",
			args, (long unsigned) ARRAY_SIZE(data));
		return -EINVAL;
	}

	va_start(vl, args);
	for (idx = 0; idx < args; idx++) {
		data[idx] = va_arg(vl, u32);
	}
	va_end(vl);

	return pvr2_encoder_cmd(hdw,cmd,args,0,data);
}


/* This implements some extra setup for the encoder that seems to be
   specific to the PVR USB2 hardware. */
static int pvr2_encoder_prep_config(struct pvr2_hdw *hdw)
{
	int ret = 0;
	int encMisc3Arg = 0;

#if 0
	/* This inexplicable bit happens in the Hauppauge windows
	   driver (for both 24xxx and 29xxx devices).  However I
	   currently see no difference in behavior with or without
	   this stuff.  Leave this here as a note of its existence,
	   but don't use it. */
	LOCK_TAKE(hdw->ctl_lock); do {
		u32 dat[1];
		dat[0] = 0x80000640;
		pvr2_encoder_write_words(hdw,0x01fe,dat,1);
		pvr2_encoder_write_words(hdw,0x023e,dat,1);
	} while(0); LOCK_GIVE(hdw->ctl_lock);
#endif

	/* Mike Isely <isely@pobox.com> 26-Jan-2006 The windows driver
	   sends the following list of ENC_MISC commands (for both
	   24xxx and 29xxx devices).  Meanings are not entirely clear,
	   however without the ENC_MISC(3,1) command then we risk
	   random perpetual video corruption whenever the video input
	   breaks up for a moment (like when switching channels). */


#if 0
	/* This ENC_MISC(5,0) command seems to hurt 29xxx sync
	   performance on channel changes, but is not a problem on
	   24xxx devices. */
	ret |= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC,4, 5,0,0,0);
#endif

	/* This ENC_MISC(3,encMisc3Arg) command is critical - without
	   it there will eventually be video corruption.  Also, the
	   saa7115 case is strange - the Windows driver is passing 1
	   regardless of device type but if we have 1 for saa7115
	   devices the video turns sluggish.  */
	if (hdw->hdw_desc->flag_has_cx25840) {
		encMisc3Arg = 1;
	} else {
		encMisc3Arg = 0;
	}
	ret |= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC,4, 3,
				 encMisc3Arg,0,0);

	ret |= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC,4, 8,0,0,0);

#if 0
	/* This ENC_MISC(4,1) command is poisonous, so it is commented
	   out.  But I'm leaving it here anyway to document its
	   existence in the Windows driver.  The effect of this
	   command is that apps displaying the stream become sluggish
	   with stuttering video. */
	ret |= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC,4, 4,1,0,0);
#endif

	ret |= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC,4, 0,3,0,0);
	ret |= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC,4,15,0,0,0);

	/* prevent the PTSs from slowly drifting away in the generated
	   MPEG stream */
	ret |= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC, 2, 4, 1);

	return ret;
}

int pvr2_encoder_adjust(struct pvr2_hdw *hdw)
{
	int ret;
	ret = cx2341x_update(hdw,pvr2_encoder_cmd,
			     (hdw->enc_cur_valid ? &hdw->enc_cur_state : NULL),
			     &hdw->enc_ctl_state);
	if (ret) {
		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
			   "Error from cx2341x module code=%d",ret);
	} else {
		hdw->enc_cur_state = hdw->enc_ctl_state;
		hdw->enc_cur_valid = !0;
	}
	return ret;
}


int pvr2_encoder_configure(struct pvr2_hdw *hdw)
{
	int ret;
	int val;
	pvr2_trace(PVR2_TRACE_ENCODER, "pvr2_encoder_configure (cx2341x module)");
	hdw->enc_ctl_state.port = CX2341X_PORT_STREAMING;
	hdw->enc_ctl_state.width = hdw->res_hor_val;
	hdw->enc_ctl_state.height = hdw->res_ver_val;
	hdw->enc_ctl_state.is_50hz = ((hdw->std_mask_cur & V4L2_STD_525_60) ?
				      0 : 1);

	ret = 0;

	ret |= pvr2_encoder_prep_config(hdw);

	/* saa7115: 0xf0 */
	val = 0xf0;
	if (hdw->hdw_desc->flag_has_cx25840) {
		/* ivtv cx25840: 0x140 */
		val = 0x140;
	}

	if (!ret) ret = pvr2_encoder_vcmd(
		hdw,CX2341X_ENC_SET_NUM_VSYNC_LINES, 2,
		val, val);

	/* setup firmware to notify us about some events (don't know why...) */
	if (!ret) ret = pvr2_encoder_vcmd(
		hdw,CX2341X_ENC_SET_EVENT_NOTIFICATION, 4,
		0, 0, 0x10000000, 0xffffffff);

	if (!ret) ret = pvr2_encoder_vcmd(
		hdw,CX2341X_ENC_SET_VBI_LINE, 5,
		0xffffffff,0,0,0,0);

	if (ret) {
		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
			   "Failed to configure cx23416");
		return ret;
	}

	ret = pvr2_encoder_adjust(hdw);
	if (ret) return ret;

	ret = pvr2_encoder_vcmd(
		hdw, CX2341X_ENC_INITIALIZE_INPUT, 0);

	if (ret) {
		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
			   "Failed to initialize cx23416 video input");
		return ret;
	}

	return 0;
}


int pvr2_encoder_start(struct pvr2_hdw *hdw)
{
	int status;

	/* unmask some interrupts */
	pvr2_write_register(hdw, 0x0048, 0xbfffffff);

	pvr2_encoder_vcmd(hdw,CX2341X_ENC_MUTE_VIDEO,1,
			  hdw->input_val == PVR2_CVAL_INPUT_RADIO ? 1 : 0);

	switch (hdw->active_stream_type) {
	case pvr2_config_vbi:
		status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_START_CAPTURE,2,
					   0x01,0x14);
		break;
	case pvr2_config_mpeg:
		status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_START_CAPTURE,2,
					   0,0x13);
		break;
	default: /* Unhandled cases for now */
		status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_START_CAPTURE,2,
					   0,0x13);
		break;
	}
	return status;
}

int pvr2_encoder_stop(struct pvr2_hdw *hdw)
{
	int status;

	/* mask all interrupts */
	pvr2_write_register(hdw, 0x0048, 0xffffffff);

	switch (hdw->active_stream_type) {
	case pvr2_config_vbi:
		status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_STOP_CAPTURE,3,
					   0x01,0x01,0x14);
		break;
	case pvr2_config_mpeg:
		status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_STOP_CAPTURE,3,
					   0x01,0,0x13);
		break;
	default: /* Unhandled cases for now */
		status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_STOP_CAPTURE,3,
					   0x01,0,0x13);
		break;
	}

	return status;
}
Commit	Line	Data
d855497e MI	1	/*
d855497e MI	2	*
d855497e MI	3	*
	4	* Copyright (C) 2005 Mike Isely <isely@pobox.com>
	5	* Copyright (C) 2004 Aurelien Alleaume <slts@free.fr>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
d855497e MI	16	*/
	17
	18	#include <linux/device.h> // for linux/firmware.h
	19	#include <linux/firmware.h>
d855497e MI	20	#include "pvrusb2-util.h"
	21	#include "pvrusb2-encoder.h"
	22	#include "pvrusb2-hdw-internal.h"
	23	#include "pvrusb2-debug.h"
8d364363	24	#include "pvrusb2-fx2-cmd.h"
d855497e	25
d855497e MI	26
	27
	28	/* Firmware mailbox flags - definitions found from ivtv */
	29	#define IVTV_MBOX_FIRMWARE_DONE 0x00000004
	30	#define IVTV_MBOX_DRIVER_DONE 0x00000002
	31	#define IVTV_MBOX_DRIVER_BUSY 0x00000001
	32
c43000ef MI	33	#define MBOX_BASE 0x44
c43000ef MI	34
d855497e	35
eacbe7c5	36	static int pvr2_encoder_write_words(struct pvr2_hdw *hdw,
c43000ef	37	unsigned int offs,
d855497e MI	38	const u32 *data, unsigned int dlen)
d855497e MI	39	{
c43000ef MI	40	unsigned int idx,addr;
c43000ef MI	41	unsigned int bAddr;
d855497e	42	int ret;
d855497e MI	43	unsigned int chunkCnt;
	44
	45	/*
	46
	47	Format: First byte must be 0x01. Remaining 32 bit words are
c43000ef MI	48	spread out into chunks of 7 bytes each, with the first 4 bytes
	49	being the data word (little endian), and the next 3 bytes
	50	being the address where that data word is to be written (big
	51	endian). Repeat request for additional words, with offset
	52	adjusted accordingly.
d855497e MI	53
	54	*/
	55	while (dlen) {
	56	chunkCnt = 8;
	57	if (chunkCnt > dlen) chunkCnt = dlen;
	58	memset(hdw->cmd_buffer,0,sizeof(hdw->cmd_buffer));
c43000ef MI	59	bAddr = 0;
c43000ef MI	60	hdw->cmd_buffer[bAddr++] = FX2CMD_MEM_WRITE_DWORD;
d855497e	61	for (idx = 0; idx < chunkCnt; idx++) {
c43000ef MI	62	addr = idx + offs;
	63	hdw->cmd_buffer[bAddr+6] = (addr & 0xffu);
	64	hdw->cmd_buffer[bAddr+5] = ((addr>>8) & 0xffu);
	65	hdw->cmd_buffer[bAddr+4] = ((addr>>16) & 0xffu);
	66	PVR2_DECOMPOSE_LE(hdw->cmd_buffer, bAddr,data[idx]);
	67	bAddr += 7;
d855497e MI	68	}
	69	ret = pvr2_send_request(hdw,
	70	hdw->cmd_buffer,1+(chunkCnt*7),
a0fd1cb1	71	NULL,0);
d855497e MI	72	if (ret) return ret;
	73	data += chunkCnt;
	74	dlen -= chunkCnt;
	75	offs += chunkCnt;
	76	}
	77
	78	return 0;
	79	}
	80
	81
c43000ef MI	82	static int pvr2_encoder_read_words(struct pvr2_hdw *hdw,
c43000ef MI	83	unsigned int offs,
d855497e MI	84	u32 *data, unsigned int dlen)
	85	{
	86	unsigned int idx;
	87	int ret;
d855497e MI	88	unsigned int chunkCnt;
	89
	90	/*
	91
	92	Format: First byte must be 0x02 (status check) or 0x28 (read
	93	back block of 32 bit words). Next 6 bytes must be zero,
c43000ef MI	94	followed by a single byte of MBOX_BASE+offset for portion to
	95	be read. Returned data is packed set of 32 bits words that
	96	were read.
d855497e MI	97
	98	*/
	99
	100	while (dlen) {
	101	chunkCnt = 16;
	102	if (chunkCnt > dlen) chunkCnt = dlen;
c43000ef	103	if (chunkCnt < 16) chunkCnt = 1;
8d364363	104	hdw->cmd_buffer[0] =
c43000ef MI	105	((chunkCnt == 1) ?
	106	FX2CMD_MEM_READ_DWORD : FX2CMD_MEM_READ_64BYTES);
	107	hdw->cmd_buffer[1] = 0;
	108	hdw->cmd_buffer[2] = 0;
	109	hdw->cmd_buffer[3] = 0;
	110	hdw->cmd_buffer[4] = 0;
	111	hdw->cmd_buffer[5] = ((offs>>16) & 0xffu);
	112	hdw->cmd_buffer[6] = ((offs>>8) & 0xffu);
	113	hdw->cmd_buffer[7] = (offs & 0xffu);
d855497e MI	114	ret = pvr2_send_request(hdw,
d855497e MI	115	hdw->cmd_buffer,8,
c43000ef MI	116	hdw->cmd_buffer,
c43000ef MI	117	(chunkCnt == 1 ? 4 : 16 * 4));
d855497e MI	118	if (ret) return ret;
	119
	120	for (idx = 0; idx < chunkCnt; idx++) {
	121	data[idx] = PVR2_COMPOSE_LE(hdw->cmd_buffer,idx*4);
	122	}
	123	data += chunkCnt;
	124	dlen -= chunkCnt;
	125	offs += chunkCnt;
	126	}
	127
	128	return 0;
	129	}
	130
	131
eacbe7c5 MI	132	/* This prototype is set up to be compatible with the
	133	cx2341x_mbox_func prototype in cx2341x.h, which should be in
	134	kernels 2.6.18 or later. We do this so that we can enable
	135	cx2341x.ko to write to our encoder (by handing it a pointer to this
	136	function). For earlier kernels this doesn't really matter. */
	137	static int pvr2_encoder_cmd(void *ctxt,
ea48c13a	138	u32 cmd,
eacbe7c5 MI	139	int arg_cnt_send,
	140	int arg_cnt_recv,
	141	u32 *argp)
d855497e MI	142	{
d855497e MI	143	unsigned int poll_count;
c43000ef MI	144	unsigned int try_count = 0;
c43000ef MI	145	int retry_flag;
d855497e	146	int ret = 0;
d855497e	147	unsigned int idx;
eacbe7c5	148	/* These sizes look to be limited by the FX2 firmware implementation */
d855497e	149	u32 wrData[16];
eacbe7c5 MI	150	u32 rdData[16];
eacbe7c5 MI	151	struct pvr2_hdw hdw = (struct pvr2_hdw )ctxt;
d855497e	152
c05c0462	153
d855497e MI	154	/*
	155
	156	The encoder seems to speak entirely using blocks 32 bit words.
c43000ef MI	157	In ivtv driver terms, this is a mailbox at MBOX_BASE which we
	158	populate with data and watch what the hardware does with it.
	159	The first word is a set of flags used to control the
	160	transaction, the second word is the command to execute, the
	161	third byte is zero (ivtv driver suggests that this is some
	162	kind of return value), and the fourth byte is a specified
	163	timeout (windows driver always uses 0x00060000 except for one
	164	case when it is zero). All successive words are the argument
	165	words for the command.
d855497e MI	166
	167	First, write out the entire set of words, with the first word
	168	being zero.
	169
	170	Next, write out just the first word again, but set it to
	171	IVTV_MBOX_DRIVER_DONE \| IVTV_DRIVER_BUSY this time (which
	172	probably means "go").
	173
c43000ef	174	Next, read back the return count words. Check the first word,
d855497e MI	175	which should have IVTV_MBOX_FIRMWARE_DONE set. If however
d855497e MI	176	that bit is not set, then the command isn't done so repeat the
c43000ef	177	read until it is set.
d855497e MI	178
	179	Finally, write out just the first word again, but set it to
	180	0x0 this time (which probably means "idle").
	181
	182	*/
	183
eca8ebfc	184	if (arg_cnt_send > (ARRAY_SIZE(wrData) - 4)) {
eacbe7c5 MI	185	pvr2_trace(
eacbe7c5 MI	186	PVR2_TRACE_ERROR_LEGS,
96292c89	187	"Failed to write cx23416 command - too many input arguments (was given %u limit %lu)",
69b04f0d	188	arg_cnt_send, (long unsigned) ARRAY_SIZE(wrData) - 4);
eacbe7c5 MI	189	return -EINVAL;
	190	}
	191
eca8ebfc	192	if (arg_cnt_recv > (ARRAY_SIZE(rdData) - 4)) {
eacbe7c5 MI	193	pvr2_trace(
eacbe7c5 MI	194	PVR2_TRACE_ERROR_LEGS,
96292c89	195	"Failed to write cx23416 command - too many return arguments (was given %u limit %lu)",
69b04f0d	196	arg_cnt_recv, (long unsigned) ARRAY_SIZE(rdData) - 4);
eacbe7c5 MI	197	return -EINVAL;
	198	}
	199
d855497e MI	200
	201	LOCK_TAKE(hdw->ctl_lock); do {
	202
681c7399	203	if (!hdw->state_encoder_ok) {
9a607f01 MI	204	ret = -EIO;
	205	break;
	206	}
	207
c43000ef MI	208	retry_flag = 0;
	209	try_count++;
	210	ret = 0;
d855497e MI	211	wrData[0] = 0;
	212	wrData[1] = cmd;
	213	wrData[2] = 0;
	214	wrData[3] = 0x00060000;
eacbe7c5 MI	215	for (idx = 0; idx < arg_cnt_send; idx++) {
eacbe7c5 MI	216	wrData[idx+4] = argp[idx];
d855497e	217	}
eca8ebfc	218	for (; idx < ARRAY_SIZE(wrData) - 4; idx++) {
eacbe7c5	219	wrData[idx+4] = 0;
d855497e MI	220	}
d855497e MI	221
c43000ef	222	ret = pvr2_encoder_write_words(hdw,MBOX_BASE,wrData,idx);
d855497e MI	223	if (ret) break;
d855497e MI	224	wrData[0] = IVTV_MBOX_DRIVER_DONE\|IVTV_MBOX_DRIVER_BUSY;
c43000ef	225	ret = pvr2_encoder_write_words(hdw,MBOX_BASE,wrData,1);
d855497e MI	226	if (ret) break;
	227	poll_count = 0;
	228	while (1) {
c43000ef MI	229	poll_count++;
	230	ret = pvr2_encoder_read_words(hdw,MBOX_BASE,rdData,
	231	arg_cnt_recv+4);
	232	if (ret) {
	233	break;
	234	}
d855497e MI	235	if (rdData[0] & IVTV_MBOX_FIRMWARE_DONE) {
	236	break;
	237	}
c43000ef MI	238	if (rdData[0] && (poll_count < 1000)) continue;
	239	if (!rdData[0]) {
	240	retry_flag = !0;
	241	pvr2_trace(
	242	PVR2_TRACE_ERROR_LEGS,
96292c89	243	"Encoder timed out waiting for us; arranging to retry");
c43000ef	244	} else {
d855497e MI	245	pvr2_trace(
d855497e MI	246	PVR2_TRACE_ERROR_LEGS,
96292c89 MCC	247	"*WARNING* device's encoder appears to be stuck (status=0x%08x)",
96292c89 MCC	248	rdData[0]);
c43000ef MI	249	}
	250	pvr2_trace(
	251	PVR2_TRACE_ERROR_LEGS,
	252	"Encoder command: 0x%02x",cmd);
	253	for (idx = 4; idx < arg_cnt_send; idx++) {
d855497e MI	254	pvr2_trace(
d855497e MI	255	PVR2_TRACE_ERROR_LEGS,
c43000ef MI	256	"Encoder arg%d: 0x%08x",
c43000ef MI	257	idx-3,wrData[idx]);
d855497e	258	}
c43000ef MI	259	ret = -EBUSY;
	260	break;
	261	}
	262	if (retry_flag) {
	263	if (try_count < 20) continue;
	264	pvr2_trace(
	265	PVR2_TRACE_ERROR_LEGS,
	266	"Too many retries...");
	267	ret = -EBUSY;
	268	}
	269	if (ret) {
d913d630	270	del_timer_sync(&hdw->encoder_run_timer);
681c7399 MI	271	hdw->state_encoder_ok = 0;
	272	pvr2_trace(PVR2_TRACE_STBITS,
	273	"State bit %s <-- %s",
	274	"state_encoder_ok",
	275	(hdw->state_encoder_ok ? "true" : "false"));
d913d630 MI	276	if (hdw->state_encoder_runok) {
	277	hdw->state_encoder_runok = 0;
	278	pvr2_trace(PVR2_TRACE_STBITS,
	279	"State bit %s <-- %s",
	280	"state_encoder_runok",
	281	(hdw->state_encoder_runok ?
	282	"true" : "false"));
	283	}
c43000ef MI	284	pvr2_trace(
c43000ef MI	285	PVR2_TRACE_ERROR_LEGS,
96292c89	286	"Giving up on command. This is normally recovered via a firmware reload and re-initialization; concern is only warranted if this happens repeatedly and rapidly.");
c43000ef	287	break;
d855497e	288	}
d855497e	289	wrData[0] = 0x7;
eacbe7c5 MI	290	for (idx = 0; idx < arg_cnt_recv; idx++) {
eacbe7c5 MI	291	argp[idx] = rdData[idx+4];
d855497e MI	292	}
	293
	294	wrData[0] = 0x0;
c43000ef	295	ret = pvr2_encoder_write_words(hdw,MBOX_BASE,wrData,1);
d855497e MI	296	if (ret) break;
	297
	298	} while(0); LOCK_GIVE(hdw->ctl_lock);
	299
	300	return ret;
	301	}
	302
eacbe7c5 MI	303
	304	static int pvr2_encoder_vcmd(struct pvr2_hdw *hdw, int cmd,
	305	int args, ...)
	306	{
	307	va_list vl;
	308	unsigned int idx;
	309	u32 data[12];
	310
eca8ebfc	311	if (args > ARRAY_SIZE(data)) {
eacbe7c5 MI	312	pvr2_trace(
eacbe7c5 MI	313	PVR2_TRACE_ERROR_LEGS,
96292c89	314	"Failed to write cx23416 command - too many arguments (was given %u limit %lu)",
69b04f0d	315	args, (long unsigned) ARRAY_SIZE(data));
eacbe7c5 MI	316	return -EINVAL;
	317	}
	318
	319	va_start(vl, args);
	320	for (idx = 0; idx < args; idx++) {
	321	data[idx] = va_arg(vl, u32);
	322	}
	323	va_end(vl);
	324
	325	return pvr2_encoder_cmd(hdw,cmd,args,0,data);
	326	}
	327
6fe7d2c4 MI	328
	329	/* This implements some extra setup for the encoder that seems to be
	330	specific to the PVR USB2 hardware. */
5948e52c	331	static int pvr2_encoder_prep_config(struct pvr2_hdw *hdw)
6fe7d2c4 MI	332	{
	333	int ret = 0;
	334	int encMisc3Arg = 0;
	335
	336	#if 0
e86da6f0	337	/* This inexplicable bit happens in the Hauppauge windows
6fe7d2c4 MI	338	driver (for both 24xxx and 29xxx devices). However I
	339	currently see no difference in behavior with or without
	340	this stuff. Leave this here as a note of its existence,
	341	but don't use it. */
	342	LOCK_TAKE(hdw->ctl_lock); do {
	343	u32 dat[1];
	344	dat[0] = 0x80000640;
	345	pvr2_encoder_write_words(hdw,0x01fe,dat,1);
	346	pvr2_encoder_write_words(hdw,0x023e,dat,1);
	347	} while(0); LOCK_GIVE(hdw->ctl_lock);
	348	#endif
	349
	350	/* Mike Isely <isely@pobox.com> 26-Jan-2006 The windows driver
	351	sends the following list of ENC_MISC commands (for both
	352	24xxx and 29xxx devices). Meanings are not entirely clear,
	353	however without the ENC_MISC(3,1) command then we risk
	354	random perpetual video corruption whenever the video input
	355	breaks up for a moment (like when switching channels). */
	356
	357
	358	#if 0
	359	/* This ENC_MISC(5,0) command seems to hurt 29xxx sync
	360	performance on channel changes, but is not a problem on
	361	24xxx devices. */
	362	ret \|= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC,4, 5,0,0,0);
	363	#endif
	364
	365	/* This ENC_MISC(3,encMisc3Arg) command is critical - without
	366	it there will eventually be video corruption. Also, the
989eb154 MI	367	saa7115 case is strange - the Windows driver is passing 1
	368	regardless of device type but if we have 1 for saa7115
	369	devices the video turns sluggish. */
	370	if (hdw->hdw_desc->flag_has_cx25840) {
	371	encMisc3Arg = 1;
	372	} else {
	373	encMisc3Arg = 0;
6fe7d2c4 MI	374	}
	375	ret \|= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC,4, 3,
	376	encMisc3Arg,0,0);
	377
	378	ret \|= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC,4, 8,0,0,0);
	379
	380	#if 0
	381	/* This ENC_MISC(4,1) command is poisonous, so it is commented
	382	out. But I'm leaving it here anyway to document its
	383	existence in the Windows driver. The effect of this
	384	command is that apps displaying the stream become sluggish
	385	with stuttering video. */
	386	ret \|= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC,4, 4,1,0,0);
	387	#endif
	388
	389	ret \|= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC,4, 0,3,0,0);
	390	ret \|= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC,4,15,0,0,0);
	391
3f93d1ad BD	392	/* prevent the PTSs from slowly drifting away in the generated
	393	MPEG stream */
	394	ret \|= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC, 2, 4, 1);
	395
6fe7d2c4 MI	396	return ret;
	397	}
	398
681c7399 MI	399	int pvr2_encoder_adjust(struct pvr2_hdw *hdw)
	400	{
	401	int ret;
	402	ret = cx2341x_update(hdw,pvr2_encoder_cmd,
	403	(hdw->enc_cur_valid ? &hdw->enc_cur_state : NULL),
	404	&hdw->enc_ctl_state);
	405	if (ret) {
	406	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
	407	"Error from cx2341x module code=%d",ret);
	408	} else {
5338c169	409	hdw->enc_cur_state = hdw->enc_ctl_state;
681c7399 MI	410	hdw->enc_cur_valid = !0;
	411	}
	412	return ret;
	413	}
	414
	415
d855497e MI	416	int pvr2_encoder_configure(struct pvr2_hdw *hdw)
d855497e MI	417	{
b30d2441	418	int ret;
db71b7df	419	int val;
96292c89	420	pvr2_trace(PVR2_TRACE_ENCODER, "pvr2_encoder_configure (cx2341x module)");
b30d2441 MI	421	hdw->enc_ctl_state.port = CX2341X_PORT_STREAMING;
	422	hdw->enc_ctl_state.width = hdw->res_hor_val;
	423	hdw->enc_ctl_state.height = hdw->res_ver_val;
db71b7df	424	hdw->enc_ctl_state.is_50hz = ((hdw->std_mask_cur & V4L2_STD_525_60) ?
b30d2441	425	0 : 1);
d855497e	426
b30d2441 MI	427	ret = 0;
b30d2441 MI	428
6fe7d2c4 MI	429	ret \|= pvr2_encoder_prep_config(hdw);
6fe7d2c4 MI	430
db71b7df MI	431	/* saa7115: 0xf0 */
db71b7df MI	432	val = 0xf0;
989eb154	433	if (hdw->hdw_desc->flag_has_cx25840) {
db71b7df MI	434	/* ivtv cx25840: 0x140 */
	435	val = 0x140;
	436	}
	437
b30d2441 MI	438	if (!ret) ret = pvr2_encoder_vcmd(
b30d2441 MI	439	hdw,CX2341X_ENC_SET_NUM_VSYNC_LINES, 2,
db71b7df	440	val, val);
d855497e MI	441
d855497e MI	442	/* setup firmware to notify us about some events (don't know why...) */
b30d2441 MI	443	if (!ret) ret = pvr2_encoder_vcmd(
	444	hdw,CX2341X_ENC_SET_EVENT_NOTIFICATION, 4,
	445	0, 0, 0x10000000, 0xffffffff);
	446
	447	if (!ret) ret = pvr2_encoder_vcmd(
	448	hdw,CX2341X_ENC_SET_VBI_LINE, 5,
	449	0xffffffff,0,0,0,0);
	450
	451	if (ret) {
	452	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
58f56cbe	453	"Failed to configure cx23416");
b30d2441 MI	454	return ret;
b30d2441 MI	455	}
d855497e	456
681c7399 MI	457	ret = pvr2_encoder_adjust(hdw);
681c7399 MI	458	if (ret) return ret;
d855497e	459
681c7399	460	ret = pvr2_encoder_vcmd(
b30d2441	461	hdw, CX2341X_ENC_INITIALIZE_INPUT, 0);
d855497e	462
b30d2441 MI	463	if (ret) {
b30d2441 MI	464	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
58f56cbe	465	"Failed to initialize cx23416 video input");
b30d2441	466	return ret;
d855497e MI	467	}
d855497e MI	468
b30d2441	469	return 0;
d855497e MI	470	}
d855497e MI	471
b30d2441	472
d855497e MI	473	int pvr2_encoder_start(struct pvr2_hdw *hdw)
	474	{
	475	int status;
	476
	477	/* unmask some interrupts */
	478	pvr2_write_register(hdw, 0x0048, 0xbfffffff);
	479
275b2e28 PK	480	pvr2_encoder_vcmd(hdw,CX2341X_ENC_MUTE_VIDEO,1,
	481	hdw->input_val == PVR2_CVAL_INPUT_RADIO ? 1 : 0);
	482
681c7399	483	switch (hdw->active_stream_type) {
16eb40d3	484	case pvr2_config_vbi:
eacbe7c5 MI	485	status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_START_CAPTURE,2,
eacbe7c5 MI	486	0x01,0x14);
16eb40d3 MI	487	break;
16eb40d3 MI	488	case pvr2_config_mpeg:
eacbe7c5 MI	489	status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_START_CAPTURE,2,
eacbe7c5 MI	490	0,0x13);
16eb40d3 MI	491	break;
16eb40d3 MI	492	default: /* Unhandled cases for now */
eacbe7c5 MI	493	status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_START_CAPTURE,2,
eacbe7c5 MI	494	0,0x13);
16eb40d3	495	break;
d855497e	496	}
d855497e MI	497	return status;
	498	}
	499
	500	int pvr2_encoder_stop(struct pvr2_hdw *hdw)
	501	{
	502	int status;
	503
	504	/* mask all interrupts */
	505	pvr2_write_register(hdw, 0x0048, 0xffffffff);
	506
681c7399	507	switch (hdw->active_stream_type) {
16eb40d3	508	case pvr2_config_vbi:
eacbe7c5 MI	509	status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_STOP_CAPTURE,3,
eacbe7c5 MI	510	0x01,0x01,0x14);
16eb40d3 MI	511	break;
16eb40d3 MI	512	case pvr2_config_mpeg:
eacbe7c5 MI	513	status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_STOP_CAPTURE,3,
eacbe7c5 MI	514	0x01,0,0x13);
16eb40d3 MI	515	break;
16eb40d3 MI	516	default: /* Unhandled cases for now */
eacbe7c5 MI	517	status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_STOP_CAPTURE,3,
eacbe7c5 MI	518	0x01,0,0x13);
16eb40d3	519	break;
d855497e MI	520	}
d855497e MI	521
d855497e MI	522	return status;
d855497e MI	523	}