]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/media/usb/pvrusb2/pvrusb2-hdw.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[media] media: usb: zr364xx: zr364xx: don't print error when allocating urb fails
[mirror_ubuntu-artful-kernel.git] / drivers / media / usb / pvrusb2 / pvrusb2-hdw.c
CommitLineData
d855497e
MI		 1/*
2 *
d855497e
MI		 3 *
4 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 *
19 */
20
21#include <linux/errno.h>
22#include <linux/string.h>
23#include <linux/slab.h>
7a707b89 24#include <linux/module.h>
d855497e 25#include <linux/firmware.h>
d855497e 26#include <linux/videodev2.h>
32ffa9ae 27#include <media/v4l2-common.h>
75212a02 28#include <media/tuner.h>
d855497e
MI		 29#include "pvrusb2.h"
30#include "pvrusb2-std.h"
31#include "pvrusb2-util.h"
32#include "pvrusb2-hdw.h"
33#include "pvrusb2-i2c-core.h"
d855497e
MI		 34#include "pvrusb2-eeprom.h"
35#include "pvrusb2-hdw-internal.h"
36#include "pvrusb2-encoder.h"
37#include "pvrusb2-debug.h"
8d364363 38#include "pvrusb2-fx2-cmd.h"
5f6dae80 39#include "pvrusb2-wm8775.h"
6f956512 40#include "pvrusb2-video-v4l.h"
634ba268 41#include "pvrusb2-cx2584x-v4l.h"
2a6b627f 42#include "pvrusb2-cs53l32a.h"
76891d65 43#include "pvrusb2-audio.h"
d855497e 44
1bde0289
MI		 45#define TV_MIN_FREQ 55250000L
46#define TV_MAX_FREQ 850000000L
25d8527a 47
83ce57aa
MI		 48/* This defines a minimum interval that the decoder must remain quiet
49 before we are allowed to start it running. */
50#define TIME_MSEC_DECODER_WAIT 50
51
6e931375
MI		 52/* This defines a minimum interval that the decoder must be allowed to run
53 before we can safely begin using its streaming output. */
54#define TIME_MSEC_DECODER_STABILIZATION_WAIT 300
55
83ce57aa 56/* This defines a minimum interval that the encoder must remain quiet
91b5b489
MI		 57 before we are allowed to configure it. */
58#define TIME_MSEC_ENCODER_WAIT 50
83ce57aa
MI		 59
60/* This defines the minimum interval that the encoder must successfully run
61 before we consider that the encoder has run at least once since its
62 firmware has been loaded. This measurement is in important for cases
63 where we can't do something until we know that the encoder has been run
64 at least once. */
65#define TIME_MSEC_ENCODER_OK 250
66
a0fd1cb1 67static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
8df0c87c 68static DEFINE_MUTEX(pvr2_unit_mtx);
d855497e 69
ff699e6b 70static int ctlchg;
ff699e6b 71static int procreload;
d855497e
MI		 72static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
73static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
74static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
ff699e6b 75static int init_pause_msec;
d855497e
MI		 76
77module_param(ctlchg, int, S_IRUGO|S_IWUSR);
78MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
79module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
80MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
d855497e
MI		 81module_param(procreload, int, S_IRUGO|S_IWUSR);
82MODULE_PARM_DESC(procreload,
83 "Attempt init failure recovery with firmware reload");
84module_param_array(tuner, int, NULL, 0444);
85MODULE_PARM_DESC(tuner,"specify installed tuner type");
86module_param_array(video_std, int, NULL, 0444);
87MODULE_PARM_DESC(video_std,"specify initial video standard");
88module_param_array(tolerance, int, NULL, 0444);
89MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
90
6f441ed7
MI		 91/* US Broadcast channel 3 (61.25 MHz), to help with testing */
92static int default_tv_freq = 61250000L;
5a4f5da6
MK		 93/* 104.3 MHz, a usable FM station for my area */
94static int default_radio_freq = 104300000L;
95
96module_param_named(tv_freq, default_tv_freq, int, 0444);
97MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
98module_param_named(radio_freq, default_radio_freq, int, 0444);
99MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
100
d855497e
MI		 101#define PVR2_CTL_WRITE_ENDPOINT 0x01
102#define PVR2_CTL_READ_ENDPOINT 0x81
103
104#define PVR2_GPIO_IN 0x9008
105#define PVR2_GPIO_OUT 0x900c
106#define PVR2_GPIO_DIR 0x9020
107
108#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
109
110#define PVR2_FIRMWARE_ENDPOINT 0x02
111
112/* size of a firmware chunk */
113#define FIRMWARE_CHUNK_SIZE 0x2000
114
edb9dcb8
MI		 115typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
116 struct v4l2_subdev *);
117
118static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
4ecbc28d 119 [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
6f956512 120 [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
76891d65 121 [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
634ba268 122 [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
2a6b627f 123 [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
edb9dcb8
MI		 124};
125
e9c64a78
MI		 126static const char *module_names[] = {
127 [PVR2_CLIENT_ID_MSP3400] = "msp3400",
128 [PVR2_CLIENT_ID_CX25840] = "cx25840",
129 [PVR2_CLIENT_ID_SAA7115] = "saa7115",
130 [PVR2_CLIENT_ID_TUNER] = "tuner",
bb65242a 131 [PVR2_CLIENT_ID_DEMOD] = "tuner",
851981a1 132 [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
5f6dae80 133 [PVR2_CLIENT_ID_WM8775] = "wm8775",
e9c64a78
MI		 134};
135
136
137static const unsigned char *module_i2c_addresses[] = {
138 [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
bb65242a 139 [PVR2_CLIENT_ID_DEMOD] = "\x43",
1dfe6c77
MI		 140 [PVR2_CLIENT_ID_MSP3400] = "\x40",
141 [PVR2_CLIENT_ID_SAA7115] = "\x21",
ae111f76 142 [PVR2_CLIENT_ID_WM8775] = "\x1b",
0b467014 143 [PVR2_CLIENT_ID_CX25840] = "\x44",
23334a22 144 [PVR2_CLIENT_ID_CS53L32A] = "\x11",
e9c64a78
MI		 145};
146
147
27eab384
MI		 148static const char *ir_scheme_names[] = {
149 [PVR2_IR_SCHEME_NONE] = "none",
150 [PVR2_IR_SCHEME_29XXX] = "29xxx",
151 [PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)",
152 [PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)",
153 [PVR2_IR_SCHEME_ZILOG] = "Zilog",
154};
155
156
b30d2441
MI		 157/* Define the list of additional controls we'll dynamically construct based
158 on query of the cx2341x module. */
159struct pvr2_mpeg_ids {
160 const char *strid;
161 int id;
162};
163static const struct pvr2_mpeg_ids mpeg_ids[] = {
164 {
165 .strid = "audio_layer",
166 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
167 },{
168 .strid = "audio_bitrate",
169 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
170 },{
171 /* Already using audio_mode elsewhere :-( */
172 .strid = "mpeg_audio_mode",
173 .id = V4L2_CID_MPEG_AUDIO_MODE,
174 },{
175 .strid = "mpeg_audio_mode_extension",
176 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
177 },{
178 .strid = "audio_emphasis",
179 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
180 },{
181 .strid = "audio_crc",
182 .id = V4L2_CID_MPEG_AUDIO_CRC,
183 },{
184 .strid = "video_aspect",
185 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
186 },{
187 .strid = "video_b_frames",
188 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
189 },{
190 .strid = "video_gop_size",
191 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
192 },{
193 .strid = "video_gop_closure",
194 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
b30d2441
MI		 195 },{
196 .strid = "video_bitrate_mode",
197 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
198 },{
199 .strid = "video_bitrate",
200 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
201 },{
202 .strid = "video_bitrate_peak",
203 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
204 },{
205 .strid = "video_temporal_decimation",
206 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
207 },{
208 .strid = "stream_type",
209 .id = V4L2_CID_MPEG_STREAM_TYPE,
210 },{
211 .strid = "video_spatial_filter_mode",
212 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
213 },{
214 .strid = "video_spatial_filter",
215 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
216 },{
217 .strid = "video_luma_spatial_filter_type",
218 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
219 },{
220 .strid = "video_chroma_spatial_filter_type",
221 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
222 },{
223 .strid = "video_temporal_filter_mode",
224 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
225 },{
226 .strid = "video_temporal_filter",
227 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
228 },{
229 .strid = "video_median_filter_type",
230 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
231 },{
232 .strid = "video_luma_median_filter_top",
233 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
234 },{
235 .strid = "video_luma_median_filter_bottom",
236 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
237 },{
238 .strid = "video_chroma_median_filter_top",
239 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
240 },{
241 .strid = "video_chroma_median_filter_bottom",
242 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
243 }
244};
eca8ebfc 245#define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
c05c0462 246
434449f4 247
d855497e 248static const char *control_values_srate[] = {
434449f4
MI		 249 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
250 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
251 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
d855497e
MI		 252};
253
254
d855497e 255
d855497e
MI		 256static const char *control_values_input[] = {
257 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
29bf5b1d 258 [PVR2_CVAL_INPUT_DTV] = "dtv",
d855497e
MI		 259 [PVR2_CVAL_INPUT_RADIO] = "radio",
260 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
261 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
262};
263
264
265static const char *control_values_audiomode[] = {
266 [V4L2_TUNER_MODE_MONO] = "Mono",
267 [V4L2_TUNER_MODE_STEREO] = "Stereo",
268 [V4L2_TUNER_MODE_LANG1] = "Lang1",
269 [V4L2_TUNER_MODE_LANG2] = "Lang2",
270 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
271};
272
273
274static const char *control_values_hsm[] = {
275 [PVR2_CVAL_HSM_FAIL] = "Fail",
276 [PVR2_CVAL_HSM_HIGH] = "High",
277 [PVR2_CVAL_HSM_FULL] = "Full",
278};
279
280
681c7399
MI		 281static const char *pvr2_state_names[] = {
282 [PVR2_STATE_NONE] = "none",
283 [PVR2_STATE_DEAD] = "dead",
284 [PVR2_STATE_COLD] = "cold",
285 [PVR2_STATE_WARM] = "warm",
286 [PVR2_STATE_ERROR] = "error",
287 [PVR2_STATE_READY] = "ready",
288 [PVR2_STATE_RUN] = "run",
d855497e
MI		 289};
290
681c7399 291
694dca2b 292struct pvr2_fx2cmd_descdef {
1c9d10d4
MI		 293 unsigned char id;
294 unsigned char *desc;
295};
296
694dca2b 297static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
1c9d10d4
MI		 298 {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
299 {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
31335b13 300 {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
1c9d10d4
MI		 301 {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
302 {FX2CMD_REG_WRITE, "write encoder register"},
303 {FX2CMD_REG_READ, "read encoder register"},
304 {FX2CMD_MEMSEL, "encoder memsel"},
305 {FX2CMD_I2C_WRITE, "i2c write"},
306 {FX2CMD_I2C_READ, "i2c read"},
307 {FX2CMD_GET_USB_SPEED, "get USB speed"},
308 {FX2CMD_STREAMING_ON, "stream on"},
309 {FX2CMD_STREAMING_OFF, "stream off"},
310 {FX2CMD_FWPOST1, "fwpost1"},
311 {FX2CMD_POWER_OFF, "power off"},
312 {FX2CMD_POWER_ON, "power on"},
313 {FX2CMD_DEEP_RESET, "deep reset"},
314 {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
315 {FX2CMD_GET_IR_CODE, "get IR code"},
316 {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
317 {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
318 {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
319 {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
320 {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
321 {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
322 {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
323};
324
325
1cb03b76 326static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
681c7399
MI		 327static void pvr2_hdw_state_sched(struct pvr2_hdw *);
328static int pvr2_hdw_state_eval(struct pvr2_hdw *);
1bde0289 329static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
681c7399 330static void pvr2_hdw_worker_poll(struct work_struct *work);
681c7399
MI		 331static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
332static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
333static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
07e337ee 334static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
681c7399 335static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
07e337ee 336static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
681c7399 337static void pvr2_hdw_quiescent_timeout(unsigned long);
6e931375 338static void pvr2_hdw_decoder_stabilization_timeout(unsigned long);
681c7399 339static void pvr2_hdw_encoder_wait_timeout(unsigned long);
d913d630 340static void pvr2_hdw_encoder_run_timeout(unsigned long);
1c9d10d4 341static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
07e337ee
AB		 342static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
343 unsigned int timeout,int probe_fl,
344 void *write_data,unsigned int write_len,
345 void *read_data,unsigned int read_len);
432907f7 346static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
ac04d00e 347static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw);
681c7399
MI		 348
349static void trace_stbit(const char *name,int val)
350{
351 pvr2_trace(PVR2_TRACE_STBITS,
352 "State bit %s <-- %s",
353 name,(val ? "true" : "false"));
354}
355
d855497e
MI		 356static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
357{
358 struct pvr2_hdw *hdw = cptr->hdw;
359 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
360 *vp = hdw->freqTable[hdw->freqProgSlot-1];
361 } else {
362 *vp = 0;
363 }
364 return 0;
365}
366
367static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
368{
369 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 370 unsigned int slotId = hdw->freqProgSlot;
371 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
372 hdw->freqTable[slotId-1] = v;
373 /* Handle side effects correctly - if we're tuned to this
374 slot, then forgot the slot id relation since the stored
375 frequency has been changed. */
376 if (hdw->freqSelector) {
377 if (hdw->freqSlotRadio == slotId) {
378 hdw->freqSlotRadio = 0;
379 }
380 } else {
381 if (hdw->freqSlotTelevision == slotId) {
382 hdw->freqSlotTelevision = 0;
383 }
384 }
d855497e
MI		 385 }
386 return 0;
387}
388
389static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
390{
391 *vp = cptr->hdw->freqProgSlot;
392 return 0;
393}
394
395static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
396{
397 struct pvr2_hdw *hdw = cptr->hdw;
398 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
399 hdw->freqProgSlot = v;
400 }
401 return 0;
402}
403
404static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
405{
1bde0289
MI		 406 struct pvr2_hdw *hdw = cptr->hdw;
407 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
d855497e
MI		 408 return 0;
409}
410
1bde0289 411static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
d855497e
MI		 412{
413 unsigned freq = 0;
414 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 415 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
416 if (slotId > 0) {
417 freq = hdw->freqTable[slotId-1];
418 if (!freq) return 0;
419 pvr2_hdw_set_cur_freq(hdw,freq);
d855497e 420 }
1bde0289
MI		 421 if (hdw->freqSelector) {
422 hdw->freqSlotRadio = slotId;
423 } else {
424 hdw->freqSlotTelevision = slotId;
d855497e
MI		 425 }
426 return 0;
427}
428
429static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
430{
1bde0289 431 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
d855497e
MI		 432 return 0;
433}
434
435static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
436{
437 return cptr->hdw->freqDirty != 0;
438}
439
440static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
441{
442 cptr->hdw->freqDirty = 0;
443}
444
445static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
446{
1bde0289 447 pvr2_hdw_set_cur_freq(cptr->hdw,v);
d855497e
MI		 448 return 0;
449}
450
e784bfb9 451static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
452{
432907f7
MI		 453 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
454 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
455 if (stat != 0) {
432907f7 456 return stat;
e784bfb9 457 }
432907f7 458 *left = cap->bounds.left;
e784bfb9 459 return 0;
460}
461
462static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
463{
432907f7
MI		 464 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
465 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
466 if (stat != 0) {
432907f7
MI		 467 return stat;
468 }
469 *left = cap->bounds.left;
470 if (cap->bounds.width > cptr->hdw->cropw_val) {
432907f7 471 *left += cap->bounds.width - cptr->hdw->cropw_val;
e784bfb9 472 }
473 return 0;
474}
475
476static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
477{
432907f7
MI		 478 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
479 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
480 if (stat != 0) {
432907f7 481 return stat;
e784bfb9 482 }
432907f7 483 *top = cap->bounds.top;
e784bfb9 484 return 0;
485}
486
432907f7 487static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
3ad9fc37 488{
432907f7
MI		 489 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
490 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
491 if (stat != 0) {
432907f7
MI		 492 return stat;
493 }
494 *top = cap->bounds.top;
495 if (cap->bounds.height > cptr->hdw->croph_val) {
432907f7 496 *top += cap->bounds.height - cptr->hdw->croph_val;
3ad9fc37
MI		 497 }
498 return 0;
499}
500
6188a0f1 501static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *width)
432907f7
MI		 502{
503 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
6188a0f1
SV		 504 int stat, bleftend, cleft;
505
506 stat = pvr2_hdw_check_cropcap(cptr->hdw);
432907f7 507 if (stat != 0) {
432907f7
MI		 508 return stat;
509 }
6188a0f1
SV		 510 bleftend = cap->bounds.left+cap->bounds.width;
511 cleft = cptr->hdw->cropl_val;
512
513 *width = cleft < bleftend ? bleftend-cleft : 0;
432907f7
MI		 514 return 0;
515}
516
6188a0f1 517static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *height)
432907f7
MI		 518{
519 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
6188a0f1
SV		 520 int stat, btopend, ctop;
521
522 stat = pvr2_hdw_check_cropcap(cptr->hdw);
432907f7 523 if (stat != 0) {
432907f7
MI		 524 return stat;
525 }
6188a0f1
SV		 526 btopend = cap->bounds.top+cap->bounds.height;
527 ctop = cptr->hdw->cropt_val;
528
529 *height = ctop < btopend ? btopend-ctop : 0;
432907f7
MI		 530 return 0;
531}
532
533static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
534{
535 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
536 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
537 if (stat != 0) {
432907f7
MI		 538 return stat;
539 }
540 *val = cap->bounds.left;
541 return 0;
542}
543
544static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
545{
546 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
547 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
548 if (stat != 0) {
432907f7
MI		 549 return stat;
550 }
551 *val = cap->bounds.top;
552 return 0;
553}
554
555static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
556{
557 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
558 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
559 if (stat != 0) {
432907f7
MI		 560 return stat;
561 }
562 *val = cap->bounds.width;
563 return 0;
564}
565
566static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
567{
568 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
569 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
570 if (stat != 0) {
432907f7
MI		 571 return stat;
572 }
573 *val = cap->bounds.height;
574 return 0;
575}
576
577static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
578{
579 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
580 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
581 if (stat != 0) {
432907f7
MI		 582 return stat;
583 }
584 *val = cap->defrect.left;
585 return 0;
586}
587
588static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
589{
590 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
591 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
592 if (stat != 0) {
432907f7
MI		 593 return stat;
594 }
595 *val = cap->defrect.top;
596 return 0;
597}
598
599static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
600{
601 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
602 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
603 if (stat != 0) {
432907f7
MI		 604 return stat;
605 }
606 *val = cap->defrect.width;
607 return 0;
608}
609
610static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
611{
612 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
613 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
614 if (stat != 0) {
432907f7
MI		 615 return stat;
616 }
617 *val = cap->defrect.height;
618 return 0;
619}
620
621static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
622{
623 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
624 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
625 if (stat != 0) {
432907f7
MI		 626 return stat;
627 }
628 *val = cap->pixelaspect.numerator;
629 return 0;
630}
631
632static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
633{
634 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
635 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
636 if (stat != 0) {
432907f7
MI		 637 return stat;
638 }
639 *val = cap->pixelaspect.denominator;
640 return 0;
641}
642
643static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
e784bfb9 644{
432907f7
MI		 645 /* Actual maximum depends on the video standard in effect. */
646 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
647 *vp = 480;
e784bfb9 648 } else {
432907f7 649 *vp = 576;
e784bfb9 650 }
651 return 0;
652}
653
3ad9fc37
MI		 654static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
655{
989eb154
MI		 656 /* Actual minimum depends on device digitizer type. */
657 if (cptr->hdw->hdw_desc->flag_has_cx25840) {
3ad9fc37
MI		 658 *vp = 75;
659 } else {
660 *vp = 17;
661 }
662 return 0;
663}
664
1bde0289 665static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
5549f54f 666{
1bde0289
MI		 667 *vp = cptr->hdw->input_val;
668 return 0;
669}
670
29bf5b1d
MI		 671static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
672{
1cb03b76 673 return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
29bf5b1d
MI		 674}
675
1bde0289
MI		 676static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
677{
1cb03b76 678 return pvr2_hdw_set_input(cptr->hdw,v);
1bde0289
MI		 679}
680
681static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
682{
683 return cptr->hdw->input_dirty != 0;
684}
685
686static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
687{
688 cptr->hdw->input_dirty = 0;
689}
690
5549f54f 691
25d8527a
PK		 692static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
693{
644afdb9
MI		 694 unsigned long fv;
695 struct pvr2_hdw *hdw = cptr->hdw;
696 if (hdw->tuner_signal_stale) {
a51f5000 697 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 698 }
699 fv = hdw->tuner_signal_info.rangehigh;
700 if (!fv) {
701 /* Safety fallback */
25d8527a 702 *vp = TV_MAX_FREQ;
644afdb9 703 return 0;
25d8527a 704 }
644afdb9
MI		 705 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
706 fv = (fv * 125) / 2;
707 } else {
708 fv = fv * 62500;
709 }
710 *vp = fv;
25d8527a
PK		 711 return 0;
712}
713
714static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
715{
644afdb9
MI		 716 unsigned long fv;
717 struct pvr2_hdw *hdw = cptr->hdw;
718 if (hdw->tuner_signal_stale) {
a51f5000 719 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 720 }
721 fv = hdw->tuner_signal_info.rangelow;
722 if (!fv) {
723 /* Safety fallback */
25d8527a 724 *vp = TV_MIN_FREQ;
644afdb9
MI		 725 return 0;
726 }
727 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
728 fv = (fv * 125) / 2;
729 } else {
730 fv = fv * 62500;
25d8527a 731 }
644afdb9 732 *vp = fv;
25d8527a
PK		 733 return 0;
734}
735
b30d2441
MI		 736static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
737{
738 return cptr->hdw->enc_stale != 0;
739}
740
741static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
742{
743 cptr->hdw->enc_stale = 0;
681c7399 744 cptr->hdw->enc_unsafe_stale = 0;
b30d2441
MI		 745}
746
747static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
748{
749 int ret;
750 struct v4l2_ext_controls cs;
751 struct v4l2_ext_control c1;
752 memset(&cs,0,sizeof(cs));
753 memset(&c1,0,sizeof(c1));
754 cs.controls = &c1;
755 cs.count = 1;
756 c1.id = cptr->info->v4l_id;
01f1e44f 757 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
b30d2441
MI		 758 VIDIOC_G_EXT_CTRLS);
759 if (ret) return ret;
760 *vp = c1.value;
761 return 0;
762}
763
764static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
765{
766 int ret;
681c7399 767 struct pvr2_hdw *hdw = cptr->hdw;
b30d2441
MI		 768 struct v4l2_ext_controls cs;
769 struct v4l2_ext_control c1;
770 memset(&cs,0,sizeof(cs));
771 memset(&c1,0,sizeof(c1));
772 cs.controls = &c1;
773 cs.count = 1;
774 c1.id = cptr->info->v4l_id;
775 c1.value = v;
681c7399
MI		 776 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
777 hdw->state_encoder_run, &cs,
b30d2441 778 VIDIOC_S_EXT_CTRLS);
681c7399
MI		 779 if (ret == -EBUSY) {
780 /* Oops. cx2341x is telling us it's not safe to change
781 this control while we're capturing. Make a note of this
782 fact so that the pipeline will be stopped the next time
783 controls are committed. Then go on ahead and store this
784 change anyway. */
785 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
786 0, &cs,
787 VIDIOC_S_EXT_CTRLS);
788 if (!ret) hdw->enc_unsafe_stale = !0;
789 }
b30d2441 790 if (ret) return ret;
681c7399 791 hdw->enc_stale = !0;
b30d2441
MI		 792 return 0;
793}
794
795static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
796{
797 struct v4l2_queryctrl qctrl;
798 struct pvr2_ctl_info *info;
799 qctrl.id = cptr->info->v4l_id;
800 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
801 /* Strip out the const so we can adjust a function pointer. It's
802 OK to do this here because we know this is a dynamically created
803 control, so the underlying storage for the info pointer is (a)
804 private to us, and (b) not in read-only storage. Either we do
805 this or we significantly complicate the underlying control
806 implementation. */
807 info = (struct pvr2_ctl_info *)(cptr->info);
808 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
809 if (info->set_value) {
a0fd1cb1 810 info->set_value = NULL;
b30d2441
MI		 811 }
812 } else {
813 if (!(info->set_value)) {
814 info->set_value = ctrl_cx2341x_set;
815 }
816 }
817 return qctrl.flags;
818}
819
d855497e
MI		 820static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
821{
681c7399
MI		 822 *vp = cptr->hdw->state_pipeline_req;
823 return 0;
824}
825
826static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
827{
828 *vp = cptr->hdw->master_state;
d855497e
MI		 829 return 0;
830}
831
832static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
833{
834 int result = pvr2_hdw_is_hsm(cptr->hdw);
835 *vp = PVR2_CVAL_HSM_FULL;
836 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
837 if (result) *vp = PVR2_CVAL_HSM_HIGH;
838 return 0;
839}
840
ac04d00e
MI		 841static int ctrl_stddetect_get(struct pvr2_ctrl *cptr, int *vp)
842{
843 *vp = pvr2_hdw_get_detected_std(cptr->hdw);
844 return 0;
845}
846
d855497e
MI		 847static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
848{
849 *vp = cptr->hdw->std_mask_avail;
850 return 0;
851}
852
853static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
854{
855 struct pvr2_hdw *hdw = cptr->hdw;
856 v4l2_std_id ns;
857 ns = hdw->std_mask_avail;
858 ns = (ns & ~m) | (v & m);
859 if (ns == hdw->std_mask_avail) return 0;
860 hdw->std_mask_avail = ns;
c0bb609f 861 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
d855497e
MI		 862 return 0;
863}
864
865static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
866 char *bufPtr,unsigned int bufSize,
867 unsigned int *len)
868{
869 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
870 return 0;
871}
872
873static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
874 const char *bufPtr,unsigned int bufSize,
875 int *mskp,int *valp)
876{
877 int ret;
878 v4l2_std_id id;
879 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
880 if (ret < 0) return ret;
881 if (mskp) *mskp = id;
882 if (valp) *valp = id;
883 return 0;
884}
885
886static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
887{
888 *vp = cptr->hdw->std_mask_cur;
889 return 0;
890}
891
892static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
893{
894 struct pvr2_hdw *hdw = cptr->hdw;
895 v4l2_std_id ns;
896 ns = hdw->std_mask_cur;
897 ns = (ns & ~m) | (v & m);
898 if (ns == hdw->std_mask_cur) return 0;
899 hdw->std_mask_cur = ns;
900 hdw->std_dirty = !0;
d855497e
MI		 901 return 0;
902}
903
904static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
905{
906 return cptr->hdw->std_dirty != 0;
907}
908
909static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
910{
911 cptr->hdw->std_dirty = 0;
912}
913
914static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
915{
18103c57 916 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 917 pvr2_hdw_status_poll(hdw);
18103c57
MI		 918 *vp = hdw->tuner_signal_info.signal;
919 return 0;
920}
921
922static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
923{
924 int val = 0;
925 unsigned int subchan;
926 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 927 pvr2_hdw_status_poll(hdw);
18103c57
MI		 928 subchan = hdw->tuner_signal_info.rxsubchans;
929 if (subchan & V4L2_TUNER_SUB_MONO) {
930 val |= (1 << V4L2_TUNER_MODE_MONO);
931 }
932 if (subchan & V4L2_TUNER_SUB_STEREO) {
933 val |= (1 << V4L2_TUNER_MODE_STEREO);
934 }
935 if (subchan & V4L2_TUNER_SUB_LANG1) {
936 val |= (1 << V4L2_TUNER_MODE_LANG1);
937 }
938 if (subchan & V4L2_TUNER_SUB_LANG2) {
939 val |= (1 << V4L2_TUNER_MODE_LANG2);
940 }
941 *vp = val;
d855497e
MI		 942 return 0;
943}
944
d855497e 945
d855497e
MI		 946#define DEFINT(vmin,vmax) \
947 .type = pvr2_ctl_int, \
948 .def.type_int.min_value = vmin, \
949 .def.type_int.max_value = vmax
950
951#define DEFENUM(tab) \
952 .type = pvr2_ctl_enum, \
27c7b710 953 .def.type_enum.count = ARRAY_SIZE(tab), \
d855497e
MI		 954 .def.type_enum.value_names = tab
955
33213963
MI		 956#define DEFBOOL \
957 .type = pvr2_ctl_bool
958
d855497e
MI		 959#define DEFMASK(msk,tab) \
960 .type = pvr2_ctl_bitmask, \
961 .def.type_bitmask.valid_bits = msk, \
962 .def.type_bitmask.bit_names = tab
963
964#define DEFREF(vname) \
965 .set_value = ctrl_set_##vname, \
966 .get_value = ctrl_get_##vname, \
967 .is_dirty = ctrl_isdirty_##vname, \
968 .clear_dirty = ctrl_cleardirty_##vname
969
970
971#define VCREATE_FUNCS(vname) \
972static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
973{*vp = cptr->hdw->vname##_val; return 0;} \
974static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
975{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
976static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
977{return cptr->hdw->vname##_dirty != 0;} \
978static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
979{cptr->hdw->vname##_dirty = 0;}
980
981VCREATE_FUNCS(brightness)
982VCREATE_FUNCS(contrast)
983VCREATE_FUNCS(saturation)
984VCREATE_FUNCS(hue)
985VCREATE_FUNCS(volume)
986VCREATE_FUNCS(balance)
987VCREATE_FUNCS(bass)
988VCREATE_FUNCS(treble)
989VCREATE_FUNCS(mute)
e784bfb9 990VCREATE_FUNCS(cropl)
991VCREATE_FUNCS(cropt)
992VCREATE_FUNCS(cropw)
993VCREATE_FUNCS(croph)
c05c0462
MI		 994VCREATE_FUNCS(audiomode)
995VCREATE_FUNCS(res_hor)
996VCREATE_FUNCS(res_ver)
d855497e 997VCREATE_FUNCS(srate)
d855497e 998
d855497e
MI		 999/* Table definition of all controls which can be manipulated */
1000static const struct pvr2_ctl_info control_defs[] = {
1001 {
1002 .v4l_id = V4L2_CID_BRIGHTNESS,
1003 .desc = "Brightness",
1004 .name = "brightness",
1005 .default_value = 128,
1006 DEFREF(brightness),
1007 DEFINT(0,255),
1008 },{
1009 .v4l_id = V4L2_CID_CONTRAST,
1010 .desc = "Contrast",
1011 .name = "contrast",
1012 .default_value = 68,
1013 DEFREF(contrast),
1014 DEFINT(0,127),
1015 },{
1016 .v4l_id = V4L2_CID_SATURATION,
1017 .desc = "Saturation",
1018 .name = "saturation",
1019 .default_value = 64,
1020 DEFREF(saturation),
1021 DEFINT(0,127),
1022 },{
1023 .v4l_id = V4L2_CID_HUE,
1024 .desc = "Hue",
1025 .name = "hue",
1026 .default_value = 0,
1027 DEFREF(hue),
1028 DEFINT(-128,127),
1029 },{
1030 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1031 .desc = "Volume",
1032 .name = "volume",
139eecf9 1033 .default_value = 62000,
d855497e
MI		 1034 DEFREF(volume),
1035 DEFINT(0,65535),
1036 },{
1037 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1038 .desc = "Balance",
1039 .name = "balance",
1040 .default_value = 0,
1041 DEFREF(balance),
1042 DEFINT(-32768,32767),
1043 },{
1044 .v4l_id = V4L2_CID_AUDIO_BASS,
1045 .desc = "Bass",
1046 .name = "bass",
1047 .default_value = 0,
1048 DEFREF(bass),
1049 DEFINT(-32768,32767),
1050 },{
1051 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1052 .desc = "Treble",
1053 .name = "treble",
1054 .default_value = 0,
1055 DEFREF(treble),
1056 DEFINT(-32768,32767),
1057 },{
1058 .v4l_id = V4L2_CID_AUDIO_MUTE,
1059 .desc = "Mute",
1060 .name = "mute",
1061 .default_value = 0,
1062 DEFREF(mute),
33213963 1063 DEFBOOL,
e784bfb9 1064 }, {
432907f7 1065 .desc = "Capture crop left margin",
e784bfb9 1066 .name = "crop_left",
1067 .internal_id = PVR2_CID_CROPL,
1068 .default_value = 0,
1069 DEFREF(cropl),
1070 DEFINT(-129, 340),
1071 .get_min_value = ctrl_cropl_min_get,
1072 .get_max_value = ctrl_cropl_max_get,
432907f7 1073 .get_def_value = ctrl_get_cropcapdl,
e784bfb9 1074 }, {
432907f7 1075 .desc = "Capture crop top margin",
e784bfb9 1076 .name = "crop_top",
1077 .internal_id = PVR2_CID_CROPT,
1078 .default_value = 0,
1079 DEFREF(cropt),
1080 DEFINT(-35, 544),
1081 .get_min_value = ctrl_cropt_min_get,
1082 .get_max_value = ctrl_cropt_max_get,
432907f7 1083 .get_def_value = ctrl_get_cropcapdt,
e784bfb9 1084 }, {
432907f7 1085 .desc = "Capture crop width",
e784bfb9 1086 .name = "crop_width",
1087 .internal_id = PVR2_CID_CROPW,
1088 .default_value = 720,
1089 DEFREF(cropw),
35fa5d4c 1090 DEFINT(0, 864),
432907f7
MI		 1091 .get_max_value = ctrl_cropw_max_get,
1092 .get_def_value = ctrl_get_cropcapdw,
e784bfb9 1093 }, {
432907f7 1094 .desc = "Capture crop height",
e784bfb9 1095 .name = "crop_height",
1096 .internal_id = PVR2_CID_CROPH,
1097 .default_value = 480,
1098 DEFREF(croph),
35fa5d4c 1099 DEFINT(0, 576),
432907f7
MI		 1100 .get_max_value = ctrl_croph_max_get,
1101 .get_def_value = ctrl_get_cropcapdh,
1102 }, {
1103 .desc = "Capture capability pixel aspect numerator",
1104 .name = "cropcap_pixel_numerator",
1105 .internal_id = PVR2_CID_CROPCAPPAN,
1106 .get_value = ctrl_get_cropcappan,
1107 }, {
1108 .desc = "Capture capability pixel aspect denominator",
1109 .name = "cropcap_pixel_denominator",
1110 .internal_id = PVR2_CID_CROPCAPPAD,
1111 .get_value = ctrl_get_cropcappad,
1112 }, {
1113 .desc = "Capture capability bounds top",
1114 .name = "cropcap_bounds_top",
1115 .internal_id = PVR2_CID_CROPCAPBT,
1116 .get_value = ctrl_get_cropcapbt,
1117 }, {
1118 .desc = "Capture capability bounds left",
1119 .name = "cropcap_bounds_left",
1120 .internal_id = PVR2_CID_CROPCAPBL,
1121 .get_value = ctrl_get_cropcapbl,
1122 }, {
1123 .desc = "Capture capability bounds width",
1124 .name = "cropcap_bounds_width",
1125 .internal_id = PVR2_CID_CROPCAPBW,
1126 .get_value = ctrl_get_cropcapbw,
1127 }, {
1128 .desc = "Capture capability bounds height",
1129 .name = "cropcap_bounds_height",
1130 .internal_id = PVR2_CID_CROPCAPBH,
1131 .get_value = ctrl_get_cropcapbh,
c05c0462
MI		 1132 },{
1133 .desc = "Video Source",
1134 .name = "input",
1135 .internal_id = PVR2_CID_INPUT,
1136 .default_value = PVR2_CVAL_INPUT_TV,
29bf5b1d 1137 .check_value = ctrl_check_input,
c05c0462
MI		 1138 DEFREF(input),
1139 DEFENUM(control_values_input),
1140 },{
1141 .desc = "Audio Mode",
1142 .name = "audio_mode",
1143 .internal_id = PVR2_CID_AUDIOMODE,
1144 .default_value = V4L2_TUNER_MODE_STEREO,
1145 DEFREF(audiomode),
1146 DEFENUM(control_values_audiomode),
1147 },{
1148 .desc = "Horizontal capture resolution",
1149 .name = "resolution_hor",
1150 .internal_id = PVR2_CID_HRES,
1151 .default_value = 720,
1152 DEFREF(res_hor),
3ad9fc37 1153 DEFINT(19,720),
c05c0462
MI		 1154 },{
1155 .desc = "Vertical capture resolution",
1156 .name = "resolution_ver",
1157 .internal_id = PVR2_CID_VRES,
1158 .default_value = 480,
1159 DEFREF(res_ver),
3ad9fc37
MI		 1160 DEFINT(17,576),
1161 /* Hook in check for video standard and adjust maximum
1162 depending on the standard. */
1163 .get_max_value = ctrl_vres_max_get,
1164 .get_min_value = ctrl_vres_min_get,
d855497e 1165 },{
b30d2441 1166 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
434449f4
MI		 1167 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1168 .desc = "Audio Sampling Frequency",
d855497e 1169 .name = "srate",
d855497e
MI		 1170 DEFREF(srate),
1171 DEFENUM(control_values_srate),
d855497e
MI		 1172 },{
1173 .desc = "Tuner Frequency (Hz)",
1174 .name = "frequency",
1175 .internal_id = PVR2_CID_FREQUENCY,
1bde0289 1176 .default_value = 0,
d855497e
MI		 1177 .set_value = ctrl_freq_set,
1178 .get_value = ctrl_freq_get,
1179 .is_dirty = ctrl_freq_is_dirty,
1180 .clear_dirty = ctrl_freq_clear_dirty,
644afdb9 1181 DEFINT(0,0),
25d8527a
PK		 1182 /* Hook in check for input value (tv/radio) and adjust
1183 max/min values accordingly */
1184 .get_max_value = ctrl_freq_max_get,
1185 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1186 },{
1187 .desc = "Channel",
1188 .name = "channel",
1189 .set_value = ctrl_channel_set,
1190 .get_value = ctrl_channel_get,
1191 DEFINT(0,FREQTABLE_SIZE),
1192 },{
1193 .desc = "Channel Program Frequency",
1194 .name = "freq_table_value",
1195 .set_value = ctrl_channelfreq_set,
1196 .get_value = ctrl_channelfreq_get,
644afdb9 1197 DEFINT(0,0),
1bde0289
MI		 1198 /* Hook in check for input value (tv/radio) and adjust
1199 max/min values accordingly */
1bde0289
MI		 1200 .get_max_value = ctrl_freq_max_get,
1201 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1202 },{
1203 .desc = "Channel Program ID",
1204 .name = "freq_table_channel",
1205 .set_value = ctrl_channelprog_set,
1206 .get_value = ctrl_channelprog_get,
1207 DEFINT(0,FREQTABLE_SIZE),
d855497e
MI		 1208 },{
1209 .desc = "Streaming Enabled",
1210 .name = "streaming_enabled",
1211 .get_value = ctrl_streamingenabled_get,
33213963 1212 DEFBOOL,
d855497e
MI		 1213 },{
1214 .desc = "USB Speed",
1215 .name = "usb_speed",
1216 .get_value = ctrl_hsm_get,
1217 DEFENUM(control_values_hsm),
681c7399
MI		 1218 },{
1219 .desc = "Master State",
1220 .name = "master_state",
1221 .get_value = ctrl_masterstate_get,
1222 DEFENUM(pvr2_state_names),
d855497e
MI		 1223 },{
1224 .desc = "Signal Present",
1225 .name = "signal_present",
1226 .get_value = ctrl_signal_get,
18103c57
MI		 1227 DEFINT(0,65535),
1228 },{
1229 .desc = "Audio Modes Present",
1230 .name = "audio_modes_present",
1231 .get_value = ctrl_audio_modes_present_get,
1232 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1233 v4l. Nothing outside of this module cares about this,
1234 but I reuse it in order to also reuse the
1235 control_values_audiomode string table. */
1236 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1237 (1 << V4L2_TUNER_MODE_STEREO)|
1238 (1 << V4L2_TUNER_MODE_LANG1)|
1239 (1 << V4L2_TUNER_MODE_LANG2)),
1240 control_values_audiomode),
d855497e
MI		 1241 },{
1242 .desc = "Video Standards Available Mask",
1243 .name = "video_standard_mask_available",
1244 .internal_id = PVR2_CID_STDAVAIL,
1245 .skip_init = !0,
1246 .get_value = ctrl_stdavail_get,
1247 .set_value = ctrl_stdavail_set,
1248 .val_to_sym = ctrl_std_val_to_sym,
1249 .sym_to_val = ctrl_std_sym_to_val,
1250 .type = pvr2_ctl_bitmask,
1251 },{
1252 .desc = "Video Standards In Use Mask",
1253 .name = "video_standard_mask_active",
1254 .internal_id = PVR2_CID_STDCUR,
1255 .skip_init = !0,
1256 .get_value = ctrl_stdcur_get,
1257 .set_value = ctrl_stdcur_set,
1258 .is_dirty = ctrl_stdcur_is_dirty,
1259 .clear_dirty = ctrl_stdcur_clear_dirty,
1260 .val_to_sym = ctrl_std_val_to_sym,
1261 .sym_to_val = ctrl_std_sym_to_val,
1262 .type = pvr2_ctl_bitmask,
ac04d00e
MI		 1263 },{
1264 .desc = "Video Standards Detected Mask",
1265 .name = "video_standard_mask_detected",
1266 .internal_id = PVR2_CID_STDDETECT,
1267 .skip_init = !0,
1268 .get_value = ctrl_stddetect_get,
1269 .val_to_sym = ctrl_std_val_to_sym,
1270 .sym_to_val = ctrl_std_sym_to_val,
1271 .type = pvr2_ctl_bitmask,
d855497e
MI		 1272 }
1273};
1274
eca8ebfc 1275#define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
d855497e
MI		 1276
1277
1278const char *pvr2_config_get_name(enum pvr2_config cfg)
1279{
1280 switch (cfg) {
1281 case pvr2_config_empty: return "empty";
1282 case pvr2_config_mpeg: return "mpeg";
1283 case pvr2_config_vbi: return "vbi";
16eb40d3
MI		 1284 case pvr2_config_pcm: return "pcm";
1285 case pvr2_config_rawvideo: return "raw video";
d855497e
MI		 1286 }
1287 return "<unknown>";
1288}
1289
1290
1291struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1292{
1293 return hdw->usb_dev;
1294}
1295
1296
1297unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1298{
1299 return hdw->serial_number;
1300}
1301
31a18547
MI		 1302
1303const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1304{
1305 return hdw->bus_info;
1306}
1307
1308
13a88797
MI		 1309const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1310{
1311 return hdw->identifier;
1312}
1313
1314
1bde0289
MI		 1315unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1316{
1317 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1318}
1319
1320/* Set the currently tuned frequency and account for all possible
1321 driver-core side effects of this action. */
f55a8712 1322static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1bde0289 1323{
7c74e57e 1324 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1bde0289
MI		 1325 if (hdw->freqSelector) {
1326 /* Swing over to radio frequency selection */
1327 hdw->freqSelector = 0;
1328 hdw->freqDirty = !0;
1329 }
1bde0289
MI		 1330 if (hdw->freqValRadio != val) {
1331 hdw->freqValRadio = val;
1332 hdw->freqSlotRadio = 0;
7c74e57e 1333 hdw->freqDirty = !0;
1bde0289 1334 }
7c74e57e 1335 } else {
1bde0289
MI		 1336 if (!(hdw->freqSelector)) {
1337 /* Swing over to television frequency selection */
1338 hdw->freqSelector = 1;
1339 hdw->freqDirty = !0;
1340 }
1bde0289
MI		 1341 if (hdw->freqValTelevision != val) {
1342 hdw->freqValTelevision = val;
1343 hdw->freqSlotTelevision = 0;
7c74e57e 1344 hdw->freqDirty = !0;
1bde0289 1345 }
1bde0289
MI		 1346 }
1347}
1348
d855497e
MI		 1349int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1350{
1351 return hdw->unit_number;
1352}
1353
1354
1355/* Attempt to locate one of the given set of files. Messages are logged
1356 appropriate to what has been found. The return value will be 0 or
1357 greater on success (it will be the index of the file name found) and
1358 fw_entry will be filled in. Otherwise a negative error is returned on
1359 failure. If the return value is -ENOENT then no viable firmware file
1360 could be located. */
1361static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1362 const struct firmware **fw_entry,
1363 const char *fwtypename,
1364 unsigned int fwcount,
1365 const char *fwnames[])
1366{
1367 unsigned int idx;
1368 int ret = -EINVAL;
1369 for (idx = 0; idx < fwcount; idx++) {
1370 ret = request_firmware(fw_entry,
1371 fwnames[idx],
1372 &hdw->usb_dev->dev);
1373 if (!ret) {
1374 trace_firmware("Located %s firmware: %s;"
1375 " uploading...",
1376 fwtypename,
1377 fwnames[idx]);
1378 return idx;
1379 }
1380 if (ret == -ENOENT) continue;
1381 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1382 "request_firmware fatal error with code=%d",ret);
1383 return ret;
1384 }
1385 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1386 "***WARNING***"
1387 " Device %s firmware"
1388 " seems to be missing.",
1389 fwtypename);
1390 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1391 "Did you install the pvrusb2 firmware files"
1392 " in their proper location?");
1393 if (fwcount == 1) {
1394 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1395 "request_firmware unable to locate %s file %s",
1396 fwtypename,fwnames[0]);
1397 } else {
1398 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1399 "request_firmware unable to locate"
1400 " one of the following %s files:",
1401 fwtypename);
1402 for (idx = 0; idx < fwcount; idx++) {
1403 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1404 "request_firmware: Failed to find %s",
1405 fwnames[idx]);
1406 }
1407 }
1408 return ret;
1409}
1410
1411
1412/*
1413 * pvr2_upload_firmware1().
1414 *
1415 * Send the 8051 firmware to the device. After the upload, arrange for
1416 * device to re-enumerate.
1417 *
1418 * NOTE : the pointer to the firmware data given by request_firmware()
1419 * is not suitable for an usb transaction.
1420 *
1421 */
07e337ee 1422static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
d855497e 1423{
a0fd1cb1 1424 const struct firmware *fw_entry = NULL;
d855497e
MI		 1425 void *fw_ptr;
1426 unsigned int pipe;
9081d901 1427 unsigned int fwsize;
d855497e
MI		 1428 int ret;
1429 u16 address;
1d643a37 1430
989eb154 1431 if (!hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37 1432 hdw->fw1_state = FW1_STATE_OK;
56dcbfa0
MI		 1433 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1434 "Connected device type defines"
1435 " no firmware to upload; ignoring firmware");
1436 return -ENOTTY;
1d643a37
MI		 1437 }
1438
d855497e
MI		 1439 hdw->fw1_state = FW1_STATE_FAILED; // default result
1440
1441 trace_firmware("pvr2_upload_firmware1");
1442
1443 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
989eb154
MI		 1444 hdw->hdw_desc->fx2_firmware.cnt,
1445 hdw->hdw_desc->fx2_firmware.lst);
d855497e
MI		 1446 if (ret < 0) {
1447 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1448 return ret;
1449 }
1450
d855497e
MI		 1451 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1452
1453 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
9081d901 1454 fwsize = fw_entry->size;
d855497e 1455
9081d901
MI		 1456 if ((fwsize != 0x2000) &&
1457 (!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) {
c21c2db4
MI		 1458 if (hdw->hdw_desc->flag_fx2_16kb) {
1459 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1460 "Wrong fx2 firmware size"
1461 " (expected 8192 or 16384, got %u)",
9081d901 1462 fwsize);
c21c2db4
MI		 1463 } else {
1464 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1465 "Wrong fx2 firmware size"
1466 " (expected 8192, got %u)",
9081d901 1467 fwsize);
c21c2db4 1468 }
d855497e
MI		 1469 release_firmware(fw_entry);
1470 return -ENOMEM;
1471 }
1472
1473 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1474 if (fw_ptr == NULL){
1475 release_firmware(fw_entry);
1476 return -ENOMEM;
1477 }
1478
1479 /* We have to hold the CPU during firmware upload. */
1480 pvr2_hdw_cpureset_assert(hdw,1);
1481
1482 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1483 chunk. */
1484
1485 ret = 0;
9081d901 1486 for (address = 0; address < fwsize; address += 0x800) {
d855497e
MI		 1487 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1488 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1489 0, fw_ptr, 0x800, HZ);
1490 }
1491
1492 trace_firmware("Upload done, releasing device's CPU");
1493
1494 /* Now release the CPU. It will disconnect and reconnect later. */
1495 pvr2_hdw_cpureset_assert(hdw,0);
1496
1497 kfree(fw_ptr);
1498 release_firmware(fw_entry);
1499
1500 trace_firmware("Upload done (%d bytes sent)",ret);
1501
75727460
GF		 1502 /* We should have written fwsize bytes */
1503 if (ret == fwsize) {
d855497e
MI		 1504 hdw->fw1_state = FW1_STATE_RELOAD;
1505 return 0;
1506 }
1507
1508 return -EIO;
1509}
1510
1511
1512/*
1513 * pvr2_upload_firmware2()
1514 *
1515 * This uploads encoder firmware on endpoint 2.
1516 *
1517 */
1518
1519int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1520{
a0fd1cb1 1521 const struct firmware *fw_entry = NULL;
d855497e 1522 void *fw_ptr;
90060d32 1523 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
d855497e
MI		 1524 int actual_length;
1525 int ret = 0;
1526 int fwidx;
1527 static const char *fw_files[] = {
1528 CX2341X_FIRM_ENC_FILENAME,
1529 };
1530
989eb154 1531 if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1d643a37
MI		 1532 return 0;
1533 }
1534
d855497e
MI		 1535 trace_firmware("pvr2_upload_firmware2");
1536
1537 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
eca8ebfc 1538 ARRAY_SIZE(fw_files), fw_files);
d855497e
MI		 1539 if (ret < 0) return ret;
1540 fwidx = ret;
1541 ret = 0;
b30d2441
MI		 1542 /* Since we're about to completely reinitialize the encoder,
1543 invalidate our cached copy of its configuration state. Next
1544 time we configure the encoder, then we'll fully configure it. */
1545 hdw->enc_cur_valid = 0;
d855497e 1546
d913d630
MI		 1547 /* Encoder is about to be reset so note that as far as we're
1548 concerned now, the encoder has never been run. */
1549 del_timer_sync(&hdw->encoder_run_timer);
1550 if (hdw->state_encoder_runok) {
1551 hdw->state_encoder_runok = 0;
1552 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1553 }
1554
d855497e
MI		 1555 /* First prepare firmware loading */
1556 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1557 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1558 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1559 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1560 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1561 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1562 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1563 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1564 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1565 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1566 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1567 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1568 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1569 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1570 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1571 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1c9d10d4
MI		 1572 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1573 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1574
1575 if (ret) {
1576 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1577 "firmware2 upload prep failed, ret=%d",ret);
1578 release_firmware(fw_entry);
21684ba9 1579 goto done;
d855497e
MI		 1580 }
1581
1582 /* Now send firmware */
1583
1584 fw_len = fw_entry->size;
1585
90060d32 1586 if (fw_len % sizeof(u32)) {
d855497e
MI		 1587 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1588 "size of %s firmware"
48dc30a1 1589 " must be a multiple of %zu bytes",
90060d32 1590 fw_files[fwidx],sizeof(u32));
d855497e 1591 release_firmware(fw_entry);
21684ba9
MI		 1592 ret = -EINVAL;
1593 goto done;
d855497e
MI		 1594 }
1595
1596 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1597 if (fw_ptr == NULL){
1598 release_firmware(fw_entry);
1599 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1600 "failed to allocate memory for firmware2 upload");
21684ba9
MI		 1601 ret = -ENOMEM;
1602 goto done;
d855497e
MI		 1603 }
1604
1605 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1606
90060d32
MI		 1607 fw_done = 0;
1608 for (fw_done = 0; fw_done < fw_len;) {
1609 bcnt = fw_len - fw_done;
1610 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1611 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1612 /* Usbsnoop log shows that we must swap bytes... */
5f33df14
MI		 1613 /* Some background info: The data being swapped here is a
1614 firmware image destined for the mpeg encoder chip that
1615 lives at the other end of a USB endpoint. The encoder
1616 chip always talks in 32 bit chunks and its storage is
1617 organized into 32 bit words. However from the file
1618 system to the encoder chip everything is purely a byte
1619 stream. The firmware file's contents are always 32 bit
1620 swapped from what the encoder expects. Thus the need
1621 always exists to swap the bytes regardless of the endian
1622 type of the host processor and therefore swab32() makes
1623 the most sense. */
90060d32 1624 for (icnt = 0; icnt < bcnt/4 ; icnt++)
513edce6 1625 ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
90060d32
MI		 1626
1627 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
d855497e 1628 &actual_length, HZ);
90060d32
MI		 1629 ret |= (actual_length != bcnt);
1630 if (ret) break;
1631 fw_done += bcnt;
d855497e
MI		 1632 }
1633
1634 trace_firmware("upload of %s : %i / %i ",
1635 fw_files[fwidx],fw_done,fw_len);
1636
1637 kfree(fw_ptr);
1638 release_firmware(fw_entry);
1639
1640 if (ret) {
1641 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1642 "firmware2 upload transfer failure");
21684ba9 1643 goto done;
d855497e
MI		 1644 }
1645
1646 /* Finish upload */
1647
1648 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1649 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1c9d10d4 1650 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1651
1652 if (ret) {
1653 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1654 "firmware2 upload post-proc failure");
d855497e 1655 }
21684ba9
MI		 1656
1657 done:
1df59f0b
MI		 1658 if (hdw->hdw_desc->signal_routing_scheme ==
1659 PVR2_ROUTING_SCHEME_GOTVIEW) {
1660 /* Ensure that GPIO 11 is set to output for GOTVIEW
1661 hardware. */
1662 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1663 }
d855497e
MI		 1664 return ret;
1665}
1666
1667
681c7399
MI		 1668static const char *pvr2_get_state_name(unsigned int st)
1669{
1670 if (st < ARRAY_SIZE(pvr2_state_names)) {
1671 return pvr2_state_names[st];
d855497e 1672 }
681c7399 1673 return "???";
d855497e
MI		 1674}
1675
681c7399 1676static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
d855497e 1677{
af78e16b
MI		 1678 /* Even though we really only care about the video decoder chip at
1679 this point, we'll broadcast stream on/off to all sub-devices
1680 anyway, just in case somebody else wants to hear the
1681 command... */
e260508d
MI		 1682 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1683 (enablefl ? "on" : "off"));
af78e16b 1684 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
3ccc646b 1685 v4l2_device_call_all(&hdw->v4l2_dev, 0, audio, s_stream, enablefl);
af78e16b
MI		 1686 if (hdw->decoder_client_id) {
1687 /* We get here if the encoder has been noticed. Otherwise
1688 we'll issue a warning to the user (which should
1689 normally never happen). */
1690 return 0;
1691 }
1692 if (!hdw->flag_decoder_missed) {
1693 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1694 "WARNING: No decoder present");
1695 hdw->flag_decoder_missed = !0;
1696 trace_stbit("flag_decoder_missed",
1697 hdw->flag_decoder_missed);
1698 }
1699 return -EIO;
d855497e
MI		 1700}
1701
1702
681c7399 1703int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
d855497e 1704{
681c7399 1705 return hdw->master_state;
d855497e
MI		 1706}
1707
1708
681c7399 1709static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
d855497e 1710{
681c7399
MI		 1711 if (!hdw->flag_tripped) return 0;
1712 hdw->flag_tripped = 0;
1713 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1714 "Clearing driver error statuss");
1715 return !0;
d855497e
MI		 1716}
1717
1718
681c7399 1719int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
d855497e 1720{
681c7399 1721 int fl;
d855497e 1722 LOCK_TAKE(hdw->big_lock); do {
681c7399 1723 fl = pvr2_hdw_untrip_unlocked(hdw);
d855497e 1724 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1725 if (fl) pvr2_hdw_state_sched(hdw);
1726 return 0;
d855497e
MI		 1727}
1728
1729
d855497e
MI		 1730
1731
1732int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1733{
681c7399 1734 return hdw->state_pipeline_req != 0;
d855497e
MI		 1735}
1736
1737
1738int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1739{
681c7399 1740 int ret,st;
d855497e 1741 LOCK_TAKE(hdw->big_lock); do {
681c7399
MI		 1742 pvr2_hdw_untrip_unlocked(hdw);
1743 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1744 hdw->state_pipeline_req = enable_flag != 0;
1745 pvr2_trace(PVR2_TRACE_START_STOP,
1746 "/*--TRACE_STREAM--*/ %s",
1747 enable_flag ? "enable" : "disable");
1748 }
1749 pvr2_hdw_state_sched(hdw);
d855497e 1750 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1751 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1752 if (enable_flag) {
1753 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1754 if (st != PVR2_STATE_READY) return -EIO;
1755 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1756 }
1757 }
d855497e
MI		 1758 return 0;
1759}
1760
1761
1762int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1763{
681c7399 1764 int fl;
d855497e 1765 LOCK_TAKE(hdw->big_lock);
681c7399
MI		 1766 if ((fl = (hdw->desired_stream_type != config)) != 0) {
1767 hdw->desired_stream_type = config;
1768 hdw->state_pipeline_config = 0;
1769 trace_stbit("state_pipeline_config",
1770 hdw->state_pipeline_config);
1771 pvr2_hdw_state_sched(hdw);
1772 }
d855497e 1773 LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1774 if (fl) return 0;
1775 return pvr2_hdw_wait(hdw,0);
d855497e
MI		 1776}
1777
1778
1779static int get_default_tuner_type(struct pvr2_hdw *hdw)
1780{
1781 int unit_number = hdw->unit_number;
1782 int tp = -1;
1783 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1784 tp = tuner[unit_number];
1785 }
1786 if (tp < 0) return -EINVAL;
1787 hdw->tuner_type = tp;
aaf7884d 1788 hdw->tuner_updated = !0;
d855497e
MI		 1789 return 0;
1790}
1791
1792
1793static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1794{
1795 int unit_number = hdw->unit_number;
1796 int tp = 0;
1797 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1798 tp = video_std[unit_number];
6a540254 1799 if (tp) return tp;
d855497e 1800 }
6a540254 1801 return 0;
d855497e
MI		 1802}
1803
1804
1805static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1806{
1807 int unit_number = hdw->unit_number;
1808 int tp = 0;
1809 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1810 tp = tolerance[unit_number];
1811 }
1812 return tp;
1813}
1814
1815
1816static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1817{
1818 /* Try a harmless request to fetch the eeprom's address over
1819 endpoint 1. See what happens. Only the full FX2 image can
1820 respond to this. If this probe fails then likely the FX2
1821 firmware needs be loaded. */
1822 int result;
1823 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 1824 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 1825 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1826 hdw->cmd_buffer,1,
1827 hdw->cmd_buffer,1);
1828 if (result < 0) break;
1829 } while(0); LOCK_GIVE(hdw->ctl_lock);
1830 if (result) {
1831 pvr2_trace(PVR2_TRACE_INIT,
1832 "Probe of device endpoint 1 result status %d",
1833 result);
1834 } else {
1835 pvr2_trace(PVR2_TRACE_INIT,
1836 "Probe of device endpoint 1 succeeded");
1837 }
1838 return result == 0;
1839}
1840
9f66d4ea
MI		 1841struct pvr2_std_hack {
1842 v4l2_std_id pat; /* Pattern to match */
1843 v4l2_std_id msk; /* Which bits we care about */
1844 v4l2_std_id std; /* What additional standards or default to set */
1845};
1846
1847/* This data structure labels specific combinations of standards from
1848 tveeprom that we'll try to recognize. If we recognize one, then assume
1849 a specified default standard to use. This is here because tveeprom only
1850 tells us about available standards not the intended default standard (if
1851 any) for the device in question. We guess the default based on what has
1852 been reported as available. Note that this is only for guessing a
1853 default - which can always be overridden explicitly - and if the user
1854 has otherwise named a default then that default will always be used in
1855 place of this table. */
ebff0330 1856static const struct pvr2_std_hack std_eeprom_maps[] = {
9f66d4ea
MI		 1857 { /* PAL(B/G) */
1858 .pat = V4L2_STD_B|V4L2_STD_GH,
1859 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1860 },
1861 { /* NTSC(M) */
1862 .pat = V4L2_STD_MN,
1863 .std = V4L2_STD_NTSC_M,
1864 },
1865 { /* PAL(I) */
1866 .pat = V4L2_STD_PAL_I,
1867 .std = V4L2_STD_PAL_I,
1868 },
1869 { /* SECAM(L/L') */
1870 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1871 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1872 },
1873 { /* PAL(D/D1/K) */
1874 .pat = V4L2_STD_DK,
ea2562d9 1875 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
9f66d4ea
MI		 1876 },
1877};
1878
d855497e
MI		 1879static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1880{
1881 char buf[40];
1882 unsigned int bcnt;
3d290bdb 1883 v4l2_std_id std1,std2,std3;
d855497e
MI		 1884
1885 std1 = get_default_standard(hdw);
3d290bdb 1886 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
d855497e
MI		 1887
1888 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
56585386 1889 pvr2_trace(PVR2_TRACE_STD,
56dcbfa0
MI		 1890 "Supported video standard(s) reported available"
1891 " in hardware: %.*s",
d855497e
MI		 1892 bcnt,buf);
1893
1894 hdw->std_mask_avail = hdw->std_mask_eeprom;
1895
3d290bdb 1896 std2 = (std1|std3) & ~hdw->std_mask_avail;
d855497e
MI		 1897 if (std2) {
1898 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
56585386 1899 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1900 "Expanding supported video standards"
1901 " to include: %.*s",
1902 bcnt,buf);
1903 hdw->std_mask_avail |= std2;
1904 }
1905
c0bb609f 1906 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
d855497e
MI		 1907
1908 if (std1) {
1909 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
56585386 1910 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1911 "Initial video standard forced to %.*s",
1912 bcnt,buf);
1913 hdw->std_mask_cur = std1;
1914 hdw->std_dirty = !0;
d855497e
MI		 1915 return;
1916 }
3d290bdb
MI		 1917 if (std3) {
1918 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1919 pvr2_trace(PVR2_TRACE_STD,
1920 "Initial video standard"
1921 " (determined by device type): %.*s",bcnt,buf);
1922 hdw->std_mask_cur = std3;
1923 hdw->std_dirty = !0;
3d290bdb
MI		 1924 return;
1925 }
d855497e 1926
9f66d4ea
MI		 1927 {
1928 unsigned int idx;
1929 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1930 if (std_eeprom_maps[idx].msk ?
1931 ((std_eeprom_maps[idx].pat ^
1932 hdw->std_mask_eeprom) &
1933 std_eeprom_maps[idx].msk) :
1934 (std_eeprom_maps[idx].pat !=
1935 hdw->std_mask_eeprom)) continue;
1936 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1937 std_eeprom_maps[idx].std);
56585386 1938 pvr2_trace(PVR2_TRACE_STD,
9f66d4ea
MI		 1939 "Initial video standard guessed as %.*s",
1940 bcnt,buf);
1941 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1942 hdw->std_dirty = !0;
9f66d4ea
MI		 1943 return;
1944 }
1945 }
1946
d855497e
MI		 1947}
1948
1949
e9c64a78
MI		 1950static unsigned int pvr2_copy_i2c_addr_list(
1951 unsigned short *dst, const unsigned char *src,
1952 unsigned int dst_max)
1953{
3ab8d295 1954 unsigned int cnt = 0;
e9c64a78
MI		 1955 if (!src) return 0;
1956 while (src[cnt] && (cnt + 1) < dst_max) {
1957 dst[cnt] = src[cnt];
1958 cnt++;
1959 }
1960 dst[cnt] = I2C_CLIENT_END;
1961 return cnt;
1962}
1963
1964
e17d787c
MI		 1965static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw)
1966{
1967 /*
1968 Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness
1969 for cx25840 causes that module to correctly set up its video
1970 scaling. This is really a problem in the cx25840 module itself,
1971 but we work around it here. The problem has not been seen in
1972 ivtv because there VBI is supported and set up. We don't do VBI
1973 here (at least not yet) and thus we never attempted to even set
1974 it up.
1975 */
1976 struct v4l2_format fmt;
1977 if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) {
1978 /* We're not using a cx25840 so don't enable the hack */
1979 return;
1980 }
1981
1982 pvr2_trace(PVR2_TRACE_INIT,
1983 "Module ID %u:"
1984 " Executing cx25840 VBI hack",
1985 hdw->decoder_client_id);
1986 memset(&fmt, 0, sizeof(fmt));
1987 fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
058caa87
MI		 1988 fmt.fmt.sliced.service_lines[0][21] = V4L2_SLICED_CAPTION_525;
1989 fmt.fmt.sliced.service_lines[1][21] = V4L2_SLICED_CAPTION_525;
e17d787c 1990 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
09419af3 1991 vbi, s_sliced_fmt, &fmt.fmt.sliced);
e17d787c
MI		 1992}
1993
1994
1ab5e74f
MI		 1995static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
1996 const struct pvr2_device_client_desc *cd)
e9c64a78
MI		 1997{
1998 const char *fname;
1999 unsigned char mid;
2000 struct v4l2_subdev *sd;
2001 unsigned int i2ccnt;
2002 const unsigned char *p;
2003 /* Arbitrary count - max # i2c addresses we will probe */
2004 unsigned short i2caddr[25];
2005
2006 mid = cd->module_id;
2007 fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
2008 if (!fname) {
2009 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
27108147
MI		 2010 "Module ID %u for device %s has no name?"
2011 " The driver might have a configuration problem.",
e9c64a78
MI		 2012 mid,
2013 hdw->hdw_desc->description);
1ab5e74f 2014 return -EINVAL;
e9c64a78 2015 }
bd14d4f8
MI		 2016 pvr2_trace(PVR2_TRACE_INIT,
2017 "Module ID %u (%s) for device %s being loaded...",
2018 mid, fname,
2019 hdw->hdw_desc->description);
e9c64a78
MI		 2020
2021 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2022 ARRAY_SIZE(i2caddr));
2023 if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2024 module_i2c_addresses[mid] : NULL) != NULL)) {
2025 /* Second chance: Try default i2c address list */
2026 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2027 ARRAY_SIZE(i2caddr));
bd14d4f8
MI		 2028 if (i2ccnt) {
2029 pvr2_trace(PVR2_TRACE_INIT,
2030 "Module ID %u:"
2031 " Using default i2c address list",
2032 mid);
2033 }
e9c64a78
MI		 2034 }
2035
2036 if (!i2ccnt) {
2037 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1ab5e74f 2038 "Module ID %u (%s) for device %s:"
27108147
MI		 2039 " No i2c addresses."
2040 " The driver might have a configuration problem.",
1ab5e74f
MI		 2041 mid, fname, hdw->hdw_desc->description);
2042 return -EINVAL;
e9c64a78
MI		 2043 }
2044
e9c64a78 2045 if (i2ccnt == 1) {
bd14d4f8
MI		 2046 pvr2_trace(PVR2_TRACE_INIT,
2047 "Module ID %u:"
2048 " Setting up with specified i2c address 0x%x",
2049 mid, i2caddr[0]);
e6574f2f 2050 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
9a1f8b34 2051 fname, i2caddr[0], NULL);
e9c64a78 2052 } else {
bd14d4f8
MI		 2053 pvr2_trace(PVR2_TRACE_INIT,
2054 "Module ID %u:"
2055 " Setting up with address probe list",
2056 mid);
53dacb15 2057 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
9a1f8b34 2058 fname, 0, i2caddr);
e9c64a78
MI		 2059 }
2060
446dfdc6
MI		 2061 if (!sd) {
2062 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
27108147
MI		 2063 "Module ID %u (%s) for device %s failed to load."
2064 " Possible missing sub-device kernel module or"
2065 " initialization failure within module.",
1ab5e74f
MI		 2066 mid, fname, hdw->hdw_desc->description);
2067 return -EIO;
446dfdc6
MI		 2068 }
2069
2070 /* Tag this sub-device instance with the module ID we know about.
2071 In other places we'll use that tag to determine if the instance
2072 requires special handling. */
2073 sd->grp_id = mid;
2074
bd14d4f8 2075 pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
a932f507 2076
e9c64a78 2077
00e5f736
MI		 2078 /* client-specific setup... */
2079 switch (mid) {
2080 case PVR2_CLIENT_ID_CX25840:
00e5f736
MI		 2081 case PVR2_CLIENT_ID_SAA7115:
2082 hdw->decoder_client_id = mid;
2083 break;
2084 default: break;
2085 }
1ab5e74f
MI		 2086
2087 return 0;
e9c64a78
MI		 2088}
2089
2090
2091static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2092{
2093 unsigned int idx;
2094 const struct pvr2_string_table *cm;
2095 const struct pvr2_device_client_table *ct;
1ab5e74f 2096 int okFl = !0;
e9c64a78
MI		 2097
2098 cm = &hdw->hdw_desc->client_modules;
2099 for (idx = 0; idx < cm->cnt; idx++) {
2100 request_module(cm->lst[idx]);
2101 }
2102
2103 ct = &hdw->hdw_desc->client_table;
2104 for (idx = 0; idx < ct->cnt; idx++) {
bd14d4f8 2105 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
e9c64a78 2106 }
27108147
MI		 2107 if (!okFl) {
2108 hdw->flag_modulefail = !0;
2109 pvr2_hdw_render_useless(hdw);
2110 }
e9c64a78
MI		 2111}
2112
2113
d855497e
MI		 2114static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2115{
2116 int ret;
2117 unsigned int idx;
2118 struct pvr2_ctrl *cptr;
2119 int reloadFl = 0;
989eb154 2120 if (hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37
MI		 2121 if (!reloadFl) {
2122 reloadFl =
2123 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2124 == 0);
2125 if (reloadFl) {
2126 pvr2_trace(PVR2_TRACE_INIT,
2127 "USB endpoint config looks strange"
2128 "; possibly firmware needs to be"
2129 " loaded");
2130 }
d855497e 2131 }
1d643a37
MI		 2132 if (!reloadFl) {
2133 reloadFl = !pvr2_hdw_check_firmware(hdw);
2134 if (reloadFl) {
2135 pvr2_trace(PVR2_TRACE_INIT,
2136 "Check for FX2 firmware failed"
2137 "; possibly firmware needs to be"
2138 " loaded");
2139 }
d855497e 2140 }
1d643a37
MI		 2141 if (reloadFl) {
2142 if (pvr2_upload_firmware1(hdw) != 0) {
2143 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2144 "Failure uploading firmware1");
2145 }
2146 return;
d855497e 2147 }
d855497e
MI		 2148 }
2149 hdw->fw1_state = FW1_STATE_OK;
2150
d855497e
MI		 2151 if (!pvr2_hdw_dev_ok(hdw)) return;
2152
27764726
MI		 2153 hdw->force_dirty = !0;
2154
989eb154 2155 if (!hdw->hdw_desc->flag_no_powerup) {
1d643a37
MI		 2156 pvr2_hdw_cmd_powerup(hdw);
2157 if (!pvr2_hdw_dev_ok(hdw)) return;
d855497e
MI		 2158 }
2159
31335b13 2160 /* Take the IR chip out of reset, if appropriate */
27eab384 2161 if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) {
31335b13
MI		 2162 pvr2_issue_simple_cmd(hdw,
2163 FX2CMD_HCW_ZILOG_RESET |
2164 (1 << 8) |
2165 ((0) << 16));
2166 }
2167
d855497e
MI		 2168 // This step MUST happen after the earlier powerup step.
2169 pvr2_i2c_core_init(hdw);
2170 if (!pvr2_hdw_dev_ok(hdw)) return;
2171
e9c64a78 2172 pvr2_hdw_load_modules(hdw);
1ab5e74f 2173 if (!pvr2_hdw_dev_ok(hdw)) return;
e9c64a78 2174
cc26b076 2175 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
5c6cb4e2 2176
c05c0462 2177 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e
MI		 2178 cptr = hdw->controls + idx;
2179 if (cptr->info->skip_init) continue;
2180 if (!cptr->info->set_value) continue;
2181 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2182 }
2183
e17d787c
MI		 2184 pvr2_hdw_cx25840_vbi_hack(hdw);
2185
1bde0289
MI		 2186 /* Set up special default values for the television and radio
2187 frequencies here. It's not really important what these defaults
2188 are, but I set them to something usable in the Chicago area just
2189 to make driver testing a little easier. */
2190
5a4f5da6
MK		 2191 hdw->freqValTelevision = default_tv_freq;
2192 hdw->freqValRadio = default_radio_freq;
1bde0289 2193
d855497e
MI		 2194 // Do not use pvr2_reset_ctl_endpoints() here. It is not
2195 // thread-safe against the normal pvr2_send_request() mechanism.
2196 // (We should make it thread safe).
2197
aaf7884d
MI		 2198 if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2199 ret = pvr2_hdw_get_eeprom_addr(hdw);
d855497e 2200 if (!pvr2_hdw_dev_ok(hdw)) return;
aaf7884d
MI		 2201 if (ret < 0) {
2202 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2203 "Unable to determine location of eeprom,"
2204 " skipping");
2205 } else {
2206 hdw->eeprom_addr = ret;
2207 pvr2_eeprom_analyze(hdw);
2208 if (!pvr2_hdw_dev_ok(hdw)) return;
2209 }
2210 } else {
2211 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2212 hdw->tuner_updated = !0;
2213 hdw->std_mask_eeprom = V4L2_STD_ALL;
d855497e
MI		 2214 }
2215
13a88797
MI		 2216 if (hdw->serial_number) {
2217 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2218 "sn-%lu", hdw->serial_number);
2219 } else if (hdw->unit_number >= 0) {
2220 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2221 "unit-%c",
2222 hdw->unit_number + 'a');
2223 } else {
2224 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2225 "unit-??");
2226 }
2227 hdw->identifier[idx] = 0;
2228
d855497e
MI		 2229 pvr2_hdw_setup_std(hdw);
2230
2231 if (!get_default_tuner_type(hdw)) {
2232 pvr2_trace(PVR2_TRACE_INIT,
2233 "pvr2_hdw_setup: Tuner type overridden to %d",
2234 hdw->tuner_type);
2235 }
2236
d855497e
MI		 2237
2238 if (!pvr2_hdw_dev_ok(hdw)) return;
2239
1df59f0b
MI		 2240 if (hdw->hdw_desc->signal_routing_scheme ==
2241 PVR2_ROUTING_SCHEME_GOTVIEW) {
2242 /* Ensure that GPIO 11 is set to output for GOTVIEW
2243 hardware. */
2244 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2245 }
2246
681c7399 2247 pvr2_hdw_commit_setup(hdw);
d855497e
MI		 2248
2249 hdw->vid_stream = pvr2_stream_create();
2250 if (!pvr2_hdw_dev_ok(hdw)) return;
2251 pvr2_trace(PVR2_TRACE_INIT,
2252 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2253 if (hdw->vid_stream) {
2254 idx = get_default_error_tolerance(hdw);
2255 if (idx) {
2256 pvr2_trace(PVR2_TRACE_INIT,
2257 "pvr2_hdw_setup: video stream %p"
2258 " setting tolerance %u",
2259 hdw->vid_stream,idx);
2260 }
2261 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2262 PVR2_VID_ENDPOINT,idx);
2263 }
2264
2265 if (!pvr2_hdw_dev_ok(hdw)) return;
2266
d855497e 2267 hdw->flag_init_ok = !0;
681c7399
MI		 2268
2269 pvr2_hdw_state_sched(hdw);
d855497e
MI		 2270}
2271
2272
681c7399
MI		 2273/* Set up the structure and attempt to put the device into a usable state.
2274 This can be a time-consuming operation, which is why it is not done
2275 internally as part of the create() step. */
2276static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
d855497e
MI		 2277{
2278 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
681c7399 2279 do {
d855497e
MI		 2280 pvr2_hdw_setup_low(hdw);
2281 pvr2_trace(PVR2_TRACE_INIT,
2282 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
681c7399 2283 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
d855497e 2284 if (pvr2_hdw_dev_ok(hdw)) {
681c7399 2285 if (hdw->flag_init_ok) {
d855497e
MI		 2286 pvr2_trace(
2287 PVR2_TRACE_INFO,
2288 "Device initialization"
2289 " completed successfully.");
2290 break;
2291 }
2292 if (hdw->fw1_state == FW1_STATE_RELOAD) {
2293 pvr2_trace(
2294 PVR2_TRACE_INFO,
2295 "Device microcontroller firmware"
2296 " (re)loaded; it should now reset"
2297 " and reconnect.");
2298 break;
2299 }
2300 pvr2_trace(
2301 PVR2_TRACE_ERROR_LEGS,
2302 "Device initialization was not successful.");
2303 if (hdw->fw1_state == FW1_STATE_MISSING) {
2304 pvr2_trace(
2305 PVR2_TRACE_ERROR_LEGS,
2306 "Giving up since device"
2307 " microcontroller firmware"
2308 " appears to be missing.");
2309 break;
2310 }
2311 }
27108147
MI		 2312 if (hdw->flag_modulefail) {
2313 pvr2_trace(
2314 PVR2_TRACE_ERROR_LEGS,
2315 "***WARNING*** pvrusb2 driver initialization"
2316 " failed due to the failure of one or more"
2317 " sub-device kernel modules.");
2318 pvr2_trace(
2319 PVR2_TRACE_ERROR_LEGS,
2320 "You need to resolve the failing condition"
2321 " before this driver can function. There"
2322 " should be some earlier messages giving more"
2323 " information about the problem.");
515ebf79 2324 break;
27108147 2325 }
d855497e
MI		 2326 if (procreload) {
2327 pvr2_trace(
2328 PVR2_TRACE_ERROR_LEGS,
2329 "Attempting pvrusb2 recovery by reloading"
2330 " primary firmware.");
2331 pvr2_trace(
2332 PVR2_TRACE_ERROR_LEGS,
2333 "If this works, device should disconnect"
2334 " and reconnect in a sane state.");
2335 hdw->fw1_state = FW1_STATE_UNKNOWN;
2336 pvr2_upload_firmware1(hdw);
2337 } else {
2338 pvr2_trace(
2339 PVR2_TRACE_ERROR_LEGS,
2340 "***WARNING*** pvrusb2 device hardware"
2341 " appears to be jammed"
2342 " and I can't clear it.");
2343 pvr2_trace(
2344 PVR2_TRACE_ERROR_LEGS,
2345 "You might need to power cycle"
2346 " the pvrusb2 device"
2347 " in order to recover.");
2348 }
681c7399 2349 } while (0);
d855497e 2350 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
d855497e
MI		 2351}
2352
2353
c4a8828d
MI		 2354/* Perform second stage initialization. Set callback pointer first so that
2355 we can avoid a possible initialization race (if the kernel thread runs
2356 before the callback has been set). */
794b1607
MI		 2357int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2358 void (*callback_func)(void *),
2359 void *callback_data)
c4a8828d
MI		 2360{
2361 LOCK_TAKE(hdw->big_lock); do {
97f26ff6
MI		 2362 if (hdw->flag_disconnected) {
2363 /* Handle a race here: If we're already
2364 disconnected by this point, then give up. If we
2365 get past this then we'll remain connected for
2366 the duration of initialization since the entire
2367 initialization sequence is now protected by the
2368 big_lock. */
2369 break;
2370 }
c4a8828d
MI		 2371 hdw->state_data = callback_data;
2372 hdw->state_func = callback_func;
97f26ff6 2373 pvr2_hdw_setup(hdw);
c4a8828d 2374 } while (0); LOCK_GIVE(hdw->big_lock);
794b1607 2375 return hdw->flag_init_ok;
c4a8828d
MI		 2376}
2377
2378
2379/* Create, set up, and return a structure for interacting with the
2380 underlying hardware. */
d855497e
MI		 2381struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2382 const struct usb_device_id *devid)
2383{
7fb20fa3 2384 unsigned int idx,cnt1,cnt2,m;
fe15f136 2385 struct pvr2_hdw *hdw = NULL;
d855497e
MI		 2386 int valid_std_mask;
2387 struct pvr2_ctrl *cptr;
b72b7bf5 2388 struct usb_device *usb_dev;
989eb154 2389 const struct pvr2_device_desc *hdw_desc;
d855497e 2390 __u8 ifnum;
b30d2441
MI		 2391 struct v4l2_queryctrl qctrl;
2392 struct pvr2_ctl_info *ciptr;
d855497e 2393
b72b7bf5
MI		 2394 usb_dev = interface_to_usbdev(intf);
2395
d130fa8a 2396 hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
d855497e 2397
fe15f136
MI		 2398 if (hdw_desc == NULL) {
2399 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2400 " No device description pointer,"
2401 " unable to continue.");
2402 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2403 " please contact Mike Isely <isely@pobox.com>"
2404 " to get it included in the driver\n");
2405 goto fail;
2406 }
2407
ca545f7c 2408 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
d855497e 2409 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
989eb154 2410 hdw,hdw_desc->description);
e67e376b 2411 pvr2_trace(PVR2_TRACE_INFO, "Hardware description: %s",
00970beb 2412 hdw_desc->description);
8fd04448
MI		 2413 if (hdw_desc->flag_is_experimental) {
2414 pvr2_trace(PVR2_TRACE_INFO, "**********");
2415 pvr2_trace(PVR2_TRACE_INFO,
2416 "WARNING: Support for this device (%s) is"
2417 " experimental.", hdw_desc->description);
2418 pvr2_trace(PVR2_TRACE_INFO,
2419 "Important functionality might not be"
2420 " entirely working.");
2421 pvr2_trace(PVR2_TRACE_INFO,
2422 "Please consider contacting the driver author to"
2423 " help with further stabilization of the driver.");
2424 pvr2_trace(PVR2_TRACE_INFO, "**********");
2425 }
d855497e 2426 if (!hdw) goto fail;
681c7399 2427
03f23fc5
JL		 2428 setup_timer(&hdw->quiescent_timer, pvr2_hdw_quiescent_timeout,
2429 (unsigned long)hdw);
681c7399 2430
03f23fc5
JL		 2431 setup_timer(&hdw->decoder_stabilization_timer,
2432 pvr2_hdw_decoder_stabilization_timeout,
2433 (unsigned long)hdw);
6e931375 2434
03f23fc5
JL		 2435 setup_timer(&hdw->encoder_wait_timer, pvr2_hdw_encoder_wait_timeout,
2436 (unsigned long)hdw);
681c7399 2437
03f23fc5
JL		 2438 setup_timer(&hdw->encoder_run_timer, pvr2_hdw_encoder_run_timeout,
2439 (unsigned long)hdw);
d913d630 2440
681c7399
MI		 2441 hdw->master_state = PVR2_STATE_DEAD;
2442
2443 init_waitqueue_head(&hdw->state_wait_data);
2444
18103c57 2445 hdw->tuner_signal_stale = !0;
b30d2441 2446 cx2341x_fill_defaults(&hdw->enc_ctl_state);
d855497e 2447
7fb20fa3
MI		 2448 /* Calculate which inputs are OK */
2449 m = 0;
2450 if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
e8f5bacf
MI		 2451 if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2452 m |= 1 << PVR2_CVAL_INPUT_DTV;
2453 }
7fb20fa3
MI		 2454 if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2455 if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2456 if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2457 hdw->input_avail_mask = m;
1cb03b76 2458 hdw->input_allowed_mask = hdw->input_avail_mask;
7fb20fa3 2459
62433e31
MI		 2460 /* If not a hybrid device, pathway_state never changes. So
2461 initialize it here to what it should forever be. */
2462 if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2463 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2464 } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2465 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2466 }
2467
c05c0462 2468 hdw->control_cnt = CTRLDEF_COUNT;
b30d2441 2469 hdw->control_cnt += MPEGDEF_COUNT;
ca545f7c 2470 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
d855497e
MI		 2471 GFP_KERNEL);
2472 if (!hdw->controls) goto fail;
989eb154 2473 hdw->hdw_desc = hdw_desc;
27eab384 2474 hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme;
c05c0462
MI		 2475 for (idx = 0; idx < hdw->control_cnt; idx++) {
2476 cptr = hdw->controls + idx;
2477 cptr->hdw = hdw;
2478 }
d855497e
MI		 2479 for (idx = 0; idx < 32; idx++) {
2480 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2481 }
c05c0462 2482 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e 2483 cptr = hdw->controls + idx;
d855497e
MI		 2484 cptr->info = control_defs+idx;
2485 }
dbc40a0e
MI		 2486
2487 /* Ensure that default input choice is a valid one. */
2488 m = hdw->input_avail_mask;
2489 if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2490 if (!((1 << idx) & m)) continue;
2491 hdw->input_val = idx;
2492 break;
2493 }
2494
b30d2441 2495 /* Define and configure additional controls from cx2341x module. */
e79c70e6
TM		 2496 hdw->mpeg_ctrl_info = kcalloc(MPEGDEF_COUNT,
2497 sizeof(*(hdw->mpeg_ctrl_info)),
2498 GFP_KERNEL);
b30d2441 2499 if (!hdw->mpeg_ctrl_info) goto fail;
b30d2441
MI		 2500 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2501 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2502 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2503 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2504 ciptr->name = mpeg_ids[idx].strid;
2505 ciptr->v4l_id = mpeg_ids[idx].id;
2506 ciptr->skip_init = !0;
2507 ciptr->get_value = ctrl_cx2341x_get;
2508 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2509 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2510 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2511 qctrl.id = ciptr->v4l_id;
2512 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2513 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2514 ciptr->set_value = ctrl_cx2341x_set;
2515 }
2516 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2517 PVR2_CTLD_INFO_DESC_SIZE);
2518 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2519 ciptr->default_value = qctrl.default_value;
2520 switch (qctrl.type) {
2521 default:
2522 case V4L2_CTRL_TYPE_INTEGER:
2523 ciptr->type = pvr2_ctl_int;
2524 ciptr->def.type_int.min_value = qctrl.minimum;
2525 ciptr->def.type_int.max_value = qctrl.maximum;
2526 break;
2527 case V4L2_CTRL_TYPE_BOOLEAN:
2528 ciptr->type = pvr2_ctl_bool;
2529 break;
2530 case V4L2_CTRL_TYPE_MENU:
2531 ciptr->type = pvr2_ctl_enum;
2532 ciptr->def.type_enum.value_names =
e0e31cdb
HV		 2533 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2534 ciptr->v4l_id);
b30d2441
MI		 2535 for (cnt1 = 0;
2536 ciptr->def.type_enum.value_names[cnt1] != NULL;
2537 cnt1++) { }
2538 ciptr->def.type_enum.count = cnt1;
2539 break;
2540 }
2541 cptr->info = ciptr;
2542 }
d855497e 2543
d855497e
MI		 2544 // Initialize control data regarding video standard masks
2545 valid_std_mask = pvr2_std_get_usable();
2546 for (idx = 0; idx < 32; idx++) {
2547 if (!(valid_std_mask & (1 << idx))) continue;
2548 cnt1 = pvr2_std_id_to_str(
2549 hdw->std_mask_names[idx],
2550 sizeof(hdw->std_mask_names[idx])-1,
2551 1 << idx);
2552 hdw->std_mask_names[idx][cnt1] = 0;
2553 }
2554 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2555 if (cptr) {
2556 memcpy(&hdw->std_info_avail,cptr->info,
2557 sizeof(hdw->std_info_avail));
2558 cptr->info = &hdw->std_info_avail;
2559 hdw->std_info_avail.def.type_bitmask.bit_names =
2560 hdw->std_mask_ptrs;
2561 hdw->std_info_avail.def.type_bitmask.valid_bits =
2562 valid_std_mask;
2563 }
2564 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2565 if (cptr) {
2566 memcpy(&hdw->std_info_cur,cptr->info,
2567 sizeof(hdw->std_info_cur));
2568 cptr->info = &hdw->std_info_cur;
2569 hdw->std_info_cur.def.type_bitmask.bit_names =
2570 hdw->std_mask_ptrs;
ac04d00e
MI		 2571 hdw->std_info_cur.def.type_bitmask.valid_bits =
2572 valid_std_mask;
2573 }
2574 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDDETECT);
2575 if (cptr) {
2576 memcpy(&hdw->std_info_detect,cptr->info,
2577 sizeof(hdw->std_info_detect));
2578 cptr->info = &hdw->std_info_detect;
2579 hdw->std_info_detect.def.type_bitmask.bit_names =
2580 hdw->std_mask_ptrs;
2581 hdw->std_info_detect.def.type_bitmask.valid_bits =
d855497e
MI		 2582 valid_std_mask;
2583 }
2584
432907f7 2585 hdw->cropcap_stale = !0;
d855497e
MI		 2586 hdw->eeprom_addr = -1;
2587 hdw->unit_number = -1;
8079384e
MI		 2588 hdw->v4l_minor_number_video = -1;
2589 hdw->v4l_minor_number_vbi = -1;
fd5a75fe 2590 hdw->v4l_minor_number_radio = -1;
d855497e
MI		 2591 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2592 if (!hdw->ctl_write_buffer) goto fail;
2593 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2594 if (!hdw->ctl_read_buffer) goto fail;
2595 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2596 if (!hdw->ctl_write_urb) goto fail;
2597 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2598 if (!hdw->ctl_read_urb) goto fail;
2599
70ad6383 2600 if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) {
b72b7bf5
MI		 2601 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2602 "Error registering with v4l core, giving up");
2603 goto fail;
2604 }
f419edd4
MCC		 2605 mutex_lock(&pvr2_unit_mtx);
2606 do {
d855497e
MI		 2607 for (idx = 0; idx < PVR_NUM; idx++) {
2608 if (unit_pointers[idx]) continue;
2609 hdw->unit_number = idx;
2610 unit_pointers[idx] = hdw;
2611 break;
2612 }
f419edd4
MCC		 2613 } while (0);
2614 mutex_unlock(&pvr2_unit_mtx);
d855497e
MI		 2615
2616 cnt1 = 0;
2617 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2618 cnt1 += cnt2;
2619 if (hdw->unit_number >= 0) {
2620 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2621 ('a' + hdw->unit_number));
2622 cnt1 += cnt2;
2623 }
2624 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2625 hdw->name[cnt1] = 0;
2626
681c7399
MI		 2627 hdw->workqueue = create_singlethread_workqueue(hdw->name);
2628 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
681c7399 2629
d855497e
MI		 2630 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2631 hdw->unit_number,hdw->name);
2632
2633 hdw->tuner_type = -1;
2634 hdw->flag_ok = !0;
d855497e
MI		 2635
2636 hdw->usb_intf = intf;
b72b7bf5 2637 hdw->usb_dev = usb_dev;
d855497e 2638
87e3495c 2639 usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
31a18547 2640
d855497e
MI		 2641 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2642 usb_set_interface(hdw->usb_dev,ifnum,0);
2643
2644 mutex_init(&hdw->ctl_lock_mutex);
2645 mutex_init(&hdw->big_lock_mutex);
2646
2647 return hdw;
2648 fail:
2649 if (hdw) {
681c7399 2650 del_timer_sync(&hdw->quiescent_timer);
6e931375 2651 del_timer_sync(&hdw->decoder_stabilization_timer);
d913d630 2652 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 2653 del_timer_sync(&hdw->encoder_wait_timer);
2654 if (hdw->workqueue) {
2655 flush_workqueue(hdw->workqueue);
2656 destroy_workqueue(hdw->workqueue);
2657 hdw->workqueue = NULL;
2658 }
5e55d2ce
MK		 2659 usb_free_urb(hdw->ctl_read_urb);
2660 usb_free_urb(hdw->ctl_write_urb);
22071a42
MK		 2661 kfree(hdw->ctl_read_buffer);
2662 kfree(hdw->ctl_write_buffer);
2663 kfree(hdw->controls);
2664 kfree(hdw->mpeg_ctrl_info);
d855497e
MI		 2665 kfree(hdw);
2666 }
a0fd1cb1 2667 return NULL;
d855497e
MI		 2668}
2669
2670
2671/* Remove _all_ associations between this driver and the underlying USB
2672 layer. */
07e337ee 2673static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
d855497e
MI		 2674{
2675 if (hdw->flag_disconnected) return;
2676 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2677 if (hdw->ctl_read_urb) {
2678 usb_kill_urb(hdw->ctl_read_urb);
2679 usb_free_urb(hdw->ctl_read_urb);
a0fd1cb1 2680 hdw->ctl_read_urb = NULL;
d855497e
MI		 2681 }
2682 if (hdw->ctl_write_urb) {
2683 usb_kill_urb(hdw->ctl_write_urb);
2684 usb_free_urb(hdw->ctl_write_urb);
a0fd1cb1 2685 hdw->ctl_write_urb = NULL;
d855497e
MI		 2686 }
2687 if (hdw->ctl_read_buffer) {
2688 kfree(hdw->ctl_read_buffer);
a0fd1cb1 2689 hdw->ctl_read_buffer = NULL;
d855497e
MI		 2690 }
2691 if (hdw->ctl_write_buffer) {
2692 kfree(hdw->ctl_write_buffer);
a0fd1cb1 2693 hdw->ctl_write_buffer = NULL;
d855497e 2694 }
d855497e 2695 hdw->flag_disconnected = !0;
b72b7bf5
MI		 2696 /* If we don't do this, then there will be a dangling struct device
2697 reference to our disappearing device persisting inside the V4L
2698 core... */
dc070bcc 2699 v4l2_device_disconnect(&hdw->v4l2_dev);
a0fd1cb1
MI		 2700 hdw->usb_dev = NULL;
2701 hdw->usb_intf = NULL;
681c7399 2702 pvr2_hdw_render_useless(hdw);
d855497e
MI		 2703}
2704
a28fbd04
HV		 2705void pvr2_hdw_set_v4l2_dev(struct pvr2_hdw *hdw, struct video_device *vdev)
2706{
2707 vdev->v4l2_dev = &hdw->v4l2_dev;
2708}
d855497e
MI		 2709
2710/* Destroy hardware interaction structure */
2711void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2712{
401c27ce 2713 if (!hdw) return;
d855497e 2714 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
681c7399
MI		 2715 if (hdw->workqueue) {
2716 flush_workqueue(hdw->workqueue);
2717 destroy_workqueue(hdw->workqueue);
2718 hdw->workqueue = NULL;
2719 }
8f59100a 2720 del_timer_sync(&hdw->quiescent_timer);
6e931375 2721 del_timer_sync(&hdw->decoder_stabilization_timer);
d913d630 2722 del_timer_sync(&hdw->encoder_run_timer);
8f59100a 2723 del_timer_sync(&hdw->encoder_wait_timer);
d855497e
MI		 2724 if (hdw->fw_buffer) {
2725 kfree(hdw->fw_buffer);
a0fd1cb1 2726 hdw->fw_buffer = NULL;
d855497e
MI		 2727 }
2728 if (hdw->vid_stream) {
2729 pvr2_stream_destroy(hdw->vid_stream);
a0fd1cb1 2730 hdw->vid_stream = NULL;
d855497e 2731 }
d855497e 2732 pvr2_i2c_core_done(hdw);
b72b7bf5 2733 v4l2_device_unregister(&hdw->v4l2_dev);
d855497e 2734 pvr2_hdw_remove_usb_stuff(hdw);
f419edd4
MCC		 2735 mutex_lock(&pvr2_unit_mtx);
2736 do {
d855497e
MI		 2737 if ((hdw->unit_number >= 0) &&
2738 (hdw->unit_number < PVR_NUM) &&
2739 (unit_pointers[hdw->unit_number] == hdw)) {
a0fd1cb1 2740 unit_pointers[hdw->unit_number] = NULL;
d855497e 2741 }
f419edd4
MCC		 2742 } while (0);
2743 mutex_unlock(&pvr2_unit_mtx);
22071a42
MK		 2744 kfree(hdw->controls);
2745 kfree(hdw->mpeg_ctrl_info);
d855497e
MI		 2746 kfree(hdw);
2747}
2748
2749
d855497e
MI		 2750int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2751{
2752 return (hdw && hdw->flag_ok);
2753}
2754
2755
2756/* Called when hardware has been unplugged */
2757void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2758{
2759 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2760 LOCK_TAKE(hdw->big_lock);
2761 LOCK_TAKE(hdw->ctl_lock);
2762 pvr2_hdw_remove_usb_stuff(hdw);
2763 LOCK_GIVE(hdw->ctl_lock);
2764 LOCK_GIVE(hdw->big_lock);
2765}
2766
2767
d855497e
MI		 2768/* Get the number of defined controls */
2769unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2770{
c05c0462 2771 return hdw->control_cnt;
d855497e
MI		 2772}
2773
2774
2775/* Retrieve a control handle given its index (0..count-1) */
2776struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2777 unsigned int idx)
2778{
a0fd1cb1 2779 if (idx >= hdw->control_cnt) return NULL;
d855497e
MI		 2780 return hdw->controls + idx;
2781}
2782
2783
2784/* Retrieve a control handle given its index (0..count-1) */
2785struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2786 unsigned int ctl_id)
2787{
2788 struct pvr2_ctrl *cptr;
2789 unsigned int idx;
2790 int i;
2791
2792 /* This could be made a lot more efficient, but for now... */
c05c0462 2793 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2794 cptr = hdw->controls + idx;
2795 i = cptr->info->internal_id;
2796 if (i && (i == ctl_id)) return cptr;
2797 }
a0fd1cb1 2798 return NULL;
d855497e
MI		 2799}
2800
2801
a761f431 2802/* Given a V4L ID, retrieve the control structure associated with it. */
d855497e
MI		 2803struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2804{
2805 struct pvr2_ctrl *cptr;
2806 unsigned int idx;
2807 int i;
2808
2809 /* This could be made a lot more efficient, but for now... */
c05c0462 2810 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2811 cptr = hdw->controls + idx;
2812 i = cptr->info->v4l_id;
2813 if (i && (i == ctl_id)) return cptr;
2814 }
a0fd1cb1 2815 return NULL;
d855497e
MI		 2816}
2817
2818
a761f431
MI		 2819/* Given a V4L ID for its immediate predecessor, retrieve the control
2820 structure associated with it. */
2821struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2822 unsigned int ctl_id)
2823{
2824 struct pvr2_ctrl *cptr,*cp2;
2825 unsigned int idx;
2826 int i;
2827
2828 /* This could be made a lot more efficient, but for now... */
a0fd1cb1 2829 cp2 = NULL;
a761f431
MI		 2830 for (idx = 0; idx < hdw->control_cnt; idx++) {
2831 cptr = hdw->controls + idx;
2832 i = cptr->info->v4l_id;
2833 if (!i) continue;
2834 if (i <= ctl_id) continue;
2835 if (cp2 && (cp2->info->v4l_id < i)) continue;
2836 cp2 = cptr;
2837 }
2838 return cp2;
a0fd1cb1 2839 return NULL;
a761f431
MI		 2840}
2841
2842
d855497e
MI		 2843static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2844{
2845 switch (tp) {
2846 case pvr2_ctl_int: return "integer";
2847 case pvr2_ctl_enum: return "enum";
33213963 2848 case pvr2_ctl_bool: return "boolean";
d855497e
MI		 2849 case pvr2_ctl_bitmask: return "bitmask";
2850 }
2851 return "";
2852}
2853
2854
2641df36
MI		 2855static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2856 const char *name, int val)
2857{
2858 struct v4l2_control ctrl;
b5b97f34
HV		 2859 struct v4l2_subdev *sd;
2860
2641df36
MI		 2861 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2862 memset(&ctrl, 0, sizeof(ctrl));
2863 ctrl.id = id;
2864 ctrl.value = val;
b5b97f34
HV		 2865
2866 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev)
2867 v4l2_s_ctrl(NULL, sd->ctrl_handler, &ctrl);
2641df36
MI		 2868}
2869
2870#define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
27764726 2871 if ((hdw)->lab##_dirty || (hdw)->force_dirty) { \
2641df36
MI		 2872 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2873 }
2874
45bc3fce 2875static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw)
7383a473 2876{
ac04d00e 2877 v4l2_std_id std;
aeebb1b3 2878 std = (v4l2_std_id)hdw->std_mask_avail;
7383a473 2879 v4l2_device_call_all(&hdw->v4l2_dev, 0,
ac04d00e
MI		 2880 video, querystd, &std);
2881 return std;
7383a473
MCC		 2882}
2883
5ceaad14 2884/* Execute whatever commands are required to update the state of all the
2641df36 2885 sub-devices so that they match our current control values. */
5ceaad14
MI		 2886static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2887{
edb9dcb8
MI		 2888 struct v4l2_subdev *sd;
2889 unsigned int id;
2890 pvr2_subdev_update_func fp;
2891
75212a02
MI		 2892 pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
2893
27764726 2894 if (hdw->tuner_updated || hdw->force_dirty) {
75212a02
MI		 2895 struct tuner_setup setup;
2896 pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
2897 hdw->tuner_type);
2898 if (((int)(hdw->tuner_type)) >= 0) {
fcd62cf7 2899 memset(&setup, 0, sizeof(setup));
75212a02
MI		 2900 setup.addr = ADDR_UNSET;
2901 setup.type = hdw->tuner_type;
2902 setup.mode_mask = T_RADIO | T_ANALOG_TV;
2903 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2904 tuner, s_type_addr, &setup);
2905 }
2906 }
2907
27764726 2908 if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
b481880b 2909 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
2641df36
MI		 2910 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2911 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2912 tuner, s_radio);
2913 } else {
2914 v4l2_std_id vs;
2915 vs = hdw->std_mask_cur;
2916 v4l2_device_call_all(&hdw->v4l2_dev, 0,
8774bed9 2917 video, s_std, vs);
a6862da2 2918 pvr2_hdw_cx25840_vbi_hack(hdw);
2641df36
MI		 2919 }
2920 hdw->tuner_signal_stale = !0;
2921 hdw->cropcap_stale = !0;
2922 }
2923
2924 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2925 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2926 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2927 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2928 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2929 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2930 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2931 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2932 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2933
27764726 2934 if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
2641df36
MI		 2935 struct v4l2_tuner vt;
2936 memset(&vt, 0, sizeof(vt));
50e9efd6
HV		 2937 vt.type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
2938 V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
2641df36
MI		 2939 vt.audmode = hdw->audiomode_val;
2940 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
2941 }
2942
27764726 2943 if (hdw->freqDirty || hdw->force_dirty) {
2641df36
MI		 2944 unsigned long fv;
2945 struct v4l2_frequency freq;
2946 fv = pvr2_hdw_get_cur_freq(hdw);
2947 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
2948 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
2949 memset(&freq, 0, sizeof(freq));
2950 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
2951 /* ((fv * 1000) / 62500) */
2952 freq.frequency = (fv * 2) / 125;
2953 } else {
2954 freq.frequency = fv / 62500;
2955 }
2956 /* tuner-core currently doesn't seem to care about this, but
2957 let's set it anyway for completeness. */
2958 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2959 freq.type = V4L2_TUNER_RADIO;
2960 } else {
2961 freq.type = V4L2_TUNER_ANALOG_TV;
2962 }
2963 freq.tuner = 0;
2964 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
2965 s_frequency, &freq);
2966 }
2967
27764726 2968 if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
ebf984bb
HV		 2969 struct v4l2_subdev_format format = {
2970 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
2971 };
2972
2973 format.format.width = hdw->res_hor_val;
2974 format.format.height = hdw->res_ver_val;
2975 format.format.code = MEDIA_BUS_FMT_FIXED;
7dfdf1ee 2976 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
ebf984bb
HV		 2977 format.format.width, format.format.height);
2978 v4l2_device_call_all(&hdw->v4l2_dev, 0, pad, set_fmt,
2979 NULL, &format);
2641df36
MI		 2980 }
2981
27764726 2982 if (hdw->srate_dirty || hdw->force_dirty) {
01c59df8
MI		 2983 u32 val;
2984 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
2985 hdw->srate_val);
2986 switch (hdw->srate_val) {
2987 default:
2988 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
2989 val = 48000;
2990 break;
2991 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
2992 val = 44100;
2993 break;
2994 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
2995 val = 32000;
2996 break;
2997 }
2998 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2999 audio, s_clock_freq, val);
3000 }
3001
2641df36
MI		 3002 /* Unable to set crop parameters; there is apparently no equivalent
3003 for VIDIOC_S_CROP */
3004
edb9dcb8
MI		 3005 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
3006 id = sd->grp_id;
3007 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
3008 fp = pvr2_module_update_functions[id];
3009 if (!fp) continue;
3010 (*fp)(hdw, sd);
3011 }
2641df36 3012
27764726 3013 if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
2641df36
MI		 3014 pvr2_hdw_status_poll(hdw);
3015 }
5ceaad14
MI		 3016}
3017
3018
681c7399
MI		 3019/* Figure out if we need to commit control changes. If so, mark internal
3020 state flags to indicate this fact and return true. Otherwise do nothing
3021 else and return false. */
3022static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
d855497e 3023{
d855497e
MI		 3024 unsigned int idx;
3025 struct pvr2_ctrl *cptr;
3026 int value;
27764726 3027 int commit_flag = hdw->force_dirty;
d855497e
MI		 3028 char buf[100];
3029 unsigned int bcnt,ccnt;
3030
c05c0462 3031 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e 3032 cptr = hdw->controls + idx;
5fa1247a 3033 if (!cptr->info->is_dirty) continue;
d855497e 3034 if (!cptr->info->is_dirty(cptr)) continue;
fe23a280 3035 commit_flag = !0;
d855497e 3036
fe23a280 3037 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
d855497e
MI		 3038 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3039 cptr->info->name);
3040 value = 0;
3041 cptr->info->get_value(cptr,&value);
3042 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3043 buf+bcnt,
3044 sizeof(buf)-bcnt,&ccnt);
3045 bcnt += ccnt;
3046 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3047 get_ctrl_typename(cptr->info->type));
3048 pvr2_trace(PVR2_TRACE_CTL,
3049 "/*--TRACE_COMMIT--*/ %.*s",
3050 bcnt,buf);
3051 }
3052
3053 if (!commit_flag) {
3054 /* Nothing has changed */
3055 return 0;
3056 }
3057
681c7399
MI		 3058 hdw->state_pipeline_config = 0;
3059 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3060 pvr2_hdw_state_sched(hdw);
3061
3062 return !0;
3063}
3064
3065
3066/* Perform all operations needed to commit all control changes. This must
3067 be performed in synchronization with the pipeline state and is thus
3068 expected to be called as part of the driver's worker thread. Return
3069 true if commit successful, otherwise return false to indicate that
3070 commit isn't possible at this time. */
3071static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3072{
3073 unsigned int idx;
3074 struct pvr2_ctrl *cptr;
3075 int disruptive_change;
3076
9bf98321
MI		 3077 if (hdw->input_dirty && hdw->state_pathway_ok &&
3078 (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3079 PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3080 hdw->pathway_state)) {
3081 /* Change of mode being asked for... */
3082 hdw->state_pathway_ok = 0;
3083 trace_stbit("state_pathway_ok", hdw->state_pathway_ok);
3084 }
3085 if (!hdw->state_pathway_ok) {
3086 /* Can't commit anything until pathway is ok. */
3087 return 0;
3088 }
3089
ab062fe3
MI		 3090 /* Handle some required side effects when the video standard is
3091 changed.... */
d855497e 3092 if (hdw->std_dirty) {
d855497e 3093 int nvres;
00528d9c 3094 int gop_size;
d855497e
MI		 3095 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3096 nvres = 480;
00528d9c 3097 gop_size = 15;
d855497e
MI		 3098 } else {
3099 nvres = 576;
00528d9c 3100 gop_size = 12;
d855497e 3101 }
00528d9c
MI		 3102 /* Rewrite the vertical resolution to be appropriate to the
3103 video standard that has been selected. */
d855497e
MI		 3104 if (nvres != hdw->res_ver_val) {
3105 hdw->res_ver_val = nvres;
3106 hdw->res_ver_dirty = !0;
3107 }
00528d9c
MI		 3108 /* Rewrite the GOP size to be appropriate to the video
3109 standard that has been selected. */
3110 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3111 struct v4l2_ext_controls cs;
3112 struct v4l2_ext_control c1;
3113 memset(&cs, 0, sizeof(cs));
3114 memset(&c1, 0, sizeof(c1));
3115 cs.controls = &c1;
3116 cs.count = 1;
3117 c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3118 c1.value = gop_size;
3119 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3120 VIDIOC_S_EXT_CTRLS);
3121 }
d855497e
MI		 3122 }
3123
e784bfb9 3124 /* The broadcast decoder can only scale down, so if
3125 * res_*_dirty && crop window < output format ==> enlarge crop.
3126 *
3127 * The mpeg encoder receives fields of res_hor_val dots and
3128 * res_ver_val halflines. Limits: hor<=720, ver<=576.
3129 */
3130 if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3131 hdw->cropw_val = hdw->res_hor_val;
3132 hdw->cropw_dirty = !0;
3133 } else if (hdw->cropw_dirty) {
3134 hdw->res_hor_dirty = !0; /* must rescale */
3135 hdw->res_hor_val = min(720, hdw->cropw_val);
3136 }
3137 if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3138 hdw->croph_val = hdw->res_ver_val;
3139 hdw->croph_dirty = !0;
3140 } else if (hdw->croph_dirty) {
3141 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3142 hdw->res_ver_dirty = !0;
3143 hdw->res_ver_val = min(nvres, hdw->croph_val);
3144 }
3145
681c7399
MI		 3146 /* If any of the below has changed, then we can't do the update
3147 while the pipeline is running. Pipeline must be paused first
3148 and decoder -> encoder connection be made quiescent before we
3149 can proceed. */
3150 disruptive_change =
3151 (hdw->std_dirty ||
3152 hdw->enc_unsafe_stale ||
3153 hdw->srate_dirty ||
3154 hdw->res_ver_dirty ||
3155 hdw->res_hor_dirty ||
755879c6
MI		 3156 hdw->cropw_dirty ||
3157 hdw->croph_dirty ||
681c7399
MI		 3158 hdw->input_dirty ||
3159 (hdw->active_stream_type != hdw->desired_stream_type));
3160 if (disruptive_change && !hdw->state_pipeline_idle) {
3161 /* Pipeline is not idle; we can't proceed. Arrange to
3162 cause pipeline to stop so that we can try this again
3163 later.... */
3164 hdw->state_pipeline_pause = !0;
3165 return 0;
275b2e28
PK		 3166 }
3167
b30d2441
MI		 3168 if (hdw->srate_dirty) {
3169 /* Write new sample rate into control structure since
3170 * the master copy is stale. We must track srate
3171 * separate from the mpeg control structure because
3172 * other logic also uses this value. */
3173 struct v4l2_ext_controls cs;
3174 struct v4l2_ext_control c1;
3175 memset(&cs,0,sizeof(cs));
3176 memset(&c1,0,sizeof(c1));
3177 cs.controls = &c1;
3178 cs.count = 1;
3179 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3180 c1.value = hdw->srate_val;
01f1e44f 3181 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
b30d2441 3182 }
c05c0462 3183
681c7399
MI		 3184 if (hdw->active_stream_type != hdw->desired_stream_type) {
3185 /* Handle any side effects of stream config here */
3186 hdw->active_stream_type = hdw->desired_stream_type;
3187 }
3188
1df59f0b
MI		 3189 if (hdw->hdw_desc->signal_routing_scheme ==
3190 PVR2_ROUTING_SCHEME_GOTVIEW) {
3191 u32 b;
3192 /* Handle GOTVIEW audio switching */
3193 pvr2_hdw_gpio_get_out(hdw,&b);
3194 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3195 /* Set GPIO 11 */
3196 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3197 } else {
3198 /* Clear GPIO 11 */
3199 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3200 }
3201 }
3202
e68a619a
MI		 3203 /* Check and update state for all sub-devices. */
3204 pvr2_subdev_update(hdw);
3205
75212a02 3206 hdw->tuner_updated = 0;
27764726 3207 hdw->force_dirty = 0;
5ceaad14
MI		 3208 for (idx = 0; idx < hdw->control_cnt; idx++) {
3209 cptr = hdw->controls + idx;
3210 if (!cptr->info->clear_dirty) continue;
3211 cptr->info->clear_dirty(cptr);
3212 }
3213
62433e31
MI		 3214 if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3215 hdw->state_encoder_run) {
3216 /* If encoder isn't running or it can't be touched, then
3217 this will get worked out later when we start the
3218 encoder. */
681c7399
MI		 3219 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3220 }
d855497e 3221
681c7399 3222 hdw->state_pipeline_config = !0;
432907f7
MI		 3223 /* Hardware state may have changed in a way to cause the cropping
3224 capabilities to have changed. So mark it stale, which will
3225 cause a later re-fetch. */
681c7399
MI		 3226 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3227 return !0;
d855497e
MI		 3228}
3229
3230
3231int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3232{
681c7399
MI		 3233 int fl;
3234 LOCK_TAKE(hdw->big_lock);
3235 fl = pvr2_hdw_commit_setup(hdw);
3236 LOCK_GIVE(hdw->big_lock);
3237 if (!fl) return 0;
3238 return pvr2_hdw_wait(hdw,0);
3239}
3240
3241
681c7399 3242static void pvr2_hdw_worker_poll(struct work_struct *work)
d855497e 3243{
681c7399
MI		 3244 int fl = 0;
3245 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
d855497e 3246 LOCK_TAKE(hdw->big_lock); do {
681c7399 3247 fl = pvr2_hdw_state_eval(hdw);
d855497e 3248 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 3249 if (fl && hdw->state_func) {
3250 hdw->state_func(hdw->state_data);
3251 }
d855497e
MI		 3252}
3253
3254
681c7399 3255static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
d855497e 3256{
681c7399
MI		 3257 return wait_event_interruptible(
3258 hdw->state_wait_data,
3259 (hdw->state_stale == 0) &&
3260 (!state || (hdw->master_state != state)));
3261}
3262
3263
d855497e
MI		 3264/* Return name for this driver instance */
3265const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3266{
3267 return hdw->name;
3268}
3269
3270
78a47101
MI		 3271const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3272{
3273 return hdw->hdw_desc->description;
3274}
3275
3276
3277const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3278{
3279 return hdw->hdw_desc->shortname;
3280}
3281
3282
d855497e
MI		 3283int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3284{
3285 int result;
3286 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 3287 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
d855497e
MI		 3288 result = pvr2_send_request(hdw,
3289 hdw->cmd_buffer,1,
3290 hdw->cmd_buffer,1);
3291 if (result < 0) break;
3292 result = (hdw->cmd_buffer[0] != 0);
3293 } while(0); LOCK_GIVE(hdw->ctl_lock);
3294 return result;
3295}
3296
3297
18103c57
MI		 3298/* Execute poll of tuner status */
3299void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
d855497e 3300{
d855497e 3301 LOCK_TAKE(hdw->big_lock); do {
a51f5000 3302 pvr2_hdw_status_poll(hdw);
d855497e 3303 } while (0); LOCK_GIVE(hdw->big_lock);
18103c57
MI		 3304}
3305
3306
432907f7
MI		 3307static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3308{
3309 if (!hdw->cropcap_stale) {
432907f7
MI		 3310 return 0;
3311 }
a51f5000 3312 pvr2_hdw_status_poll(hdw);
432907f7 3313 if (hdw->cropcap_stale) {
432907f7
MI		 3314 return -EIO;
3315 }
3316 return 0;
3317}
3318
3319
3320/* Return information about cropping capabilities */
3321int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3322{
3323 int stat = 0;
3324 LOCK_TAKE(hdw->big_lock);
3325 stat = pvr2_hdw_check_cropcap(hdw);
3326 if (!stat) {
432907f7
MI		 3327 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3328 }
3329 LOCK_GIVE(hdw->big_lock);
3330 return stat;
3331}
3332
3333
18103c57
MI		 3334/* Return information about the tuner */
3335int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3336{
3337 LOCK_TAKE(hdw->big_lock); do {
3338 if (hdw->tuner_signal_stale) {
a51f5000 3339 pvr2_hdw_status_poll(hdw);
18103c57
MI		 3340 }
3341 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3342 } while (0); LOCK_GIVE(hdw->big_lock);
3343 return 0;
d855497e
MI		 3344}
3345
3346
3347/* Get handle to video output stream */
3348struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3349{
3350 return hp->vid_stream;
3351}
3352
3353
3354void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3355{
4f1a3e5b 3356 int nr = pvr2_hdw_get_unit_number(hdw);
f419edd4
MCC		 3357 LOCK_TAKE(hdw->big_lock);
3358 do {
4f1a3e5b 3359 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
ed3261a8 3360 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
b30d2441 3361 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
99eb44fe 3362 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
681c7399 3363 pvr2_hdw_state_log_state(hdw);
4f1a3e5b 3364 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
f419edd4
MCC		 3365 } while (0);
3366 LOCK_GIVE(hdw->big_lock);
d855497e
MI		 3367}
3368
4db666cc
MI		 3369
3370/* Grab EEPROM contents, needed for direct method. */
3371#define EEPROM_SIZE 8192
3372#define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3373static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3374{
3375 struct i2c_msg msg[2];
3376 u8 *eeprom;
3377 u8 iadd[2];
3378 u8 addr;
3379 u16 eepromSize;
3380 unsigned int offs;
3381 int ret;
3382 int mode16 = 0;
3383 unsigned pcnt,tcnt;
3384 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3385 if (!eeprom) {
3386 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3387 "Failed to allocate memory"
3388 " required to read eeprom");
3389 return NULL;
3390 }
3391
3392 trace_eeprom("Value for eeprom addr from controller was 0x%x",
3393 hdw->eeprom_addr);
3394 addr = hdw->eeprom_addr;
3395 /* Seems that if the high bit is set, then the *real* eeprom
3396 address is shifted right now bit position (noticed this in
3397 newer PVR USB2 hardware) */
3398 if (addr & 0x80) addr >>= 1;
3399
3400 /* FX2 documentation states that a 16bit-addressed eeprom is
3401 expected if the I2C address is an odd number (yeah, this is
3402 strange but it's what they do) */
3403 mode16 = (addr & 1);
3404 eepromSize = (mode16 ? EEPROM_SIZE : 256);
3405 trace_eeprom("Examining %d byte eeprom at location 0x%x"
3406 " using %d bit addressing",eepromSize,addr,
3407 mode16 ? 16 : 8);
3408
3409 msg[0].addr = addr;
3410 msg[0].flags = 0;
3411 msg[0].len = mode16 ? 2 : 1;
3412 msg[0].buf = iadd;
3413 msg[1].addr = addr;
3414 msg[1].flags = I2C_M_RD;
3415
3416 /* We have to do the actual eeprom data fetch ourselves, because
3417 (1) we're only fetching part of the eeprom, and (2) if we were
3418 getting the whole thing our I2C driver can't grab it in one
3419 pass - which is what tveeprom is otherwise going to attempt */
3420 memset(eeprom,0,EEPROM_SIZE);
3421 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3422 pcnt = 16;
3423 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3424 offs = tcnt + (eepromSize - EEPROM_SIZE);
3425 if (mode16) {
3426 iadd[0] = offs >> 8;
3427 iadd[1] = offs;
3428 } else {
3429 iadd[0] = offs;
3430 }
3431 msg[1].len = pcnt;
3432 msg[1].buf = eeprom+tcnt;
3433 if ((ret = i2c_transfer(&hdw->i2c_adap,
3434 msg,ARRAY_SIZE(msg))) != 2) {
3435 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3436 "eeprom fetch set offs err=%d",ret);
3437 kfree(eeprom);
3438 return NULL;
3439 }
3440 }
3441 return eeprom;
3442}
3443
3444
3445void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
568efaa2 3446 int mode,
4db666cc 3447 int enable_flag)
d855497e
MI		 3448{
3449 int ret;
3450 u16 address;
3451 unsigned int pipe;
3452 LOCK_TAKE(hdw->big_lock); do {
5fa1247a 3453 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
d855497e
MI		 3454
3455 if (!enable_flag) {
3456 pvr2_trace(PVR2_TRACE_FIRMWARE,
3457 "Cleaning up after CPU firmware fetch");
3458 kfree(hdw->fw_buffer);
a0fd1cb1 3459 hdw->fw_buffer = NULL;
d855497e 3460 hdw->fw_size = 0;
4db666cc
MI		 3461 if (hdw->fw_cpu_flag) {
3462 /* Now release the CPU. It will disconnect
3463 and reconnect later. */
3464 pvr2_hdw_cpureset_assert(hdw,0);
3465 }
d855497e
MI		 3466 break;
3467 }
3468
568efaa2 3469 hdw->fw_cpu_flag = (mode != 2);
4db666cc 3470 if (hdw->fw_cpu_flag) {
568efaa2 3471 hdw->fw_size = (mode == 1) ? 0x4000 : 0x2000;
4db666cc 3472 pvr2_trace(PVR2_TRACE_FIRMWARE,
568efaa2
MI		 3473 "Preparing to suck out CPU firmware"
3474 " (size=%u)", hdw->fw_size);
4db666cc
MI		 3475 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3476 if (!hdw->fw_buffer) {
3477 hdw->fw_size = 0;
3478 break;
3479 }
d855497e 3480
4db666cc
MI		 3481 /* We have to hold the CPU during firmware upload. */
3482 pvr2_hdw_cpureset_assert(hdw,1);
d855497e 3483
4db666cc
MI		 3484 /* download the firmware from address 0000-1fff in 2048
3485 (=0x800) bytes chunk. */
d855497e 3486
4db666cc
MI		 3487 pvr2_trace(PVR2_TRACE_FIRMWARE,
3488 "Grabbing CPU firmware");
3489 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3490 for(address = 0; address < hdw->fw_size;
3491 address += 0x800) {
3492 ret = usb_control_msg(hdw->usb_dev,pipe,
3493 0xa0,0xc0,
3494 address,0,
3495 hdw->fw_buffer+address,
3496 0x800,HZ);
3497 if (ret < 0) break;
3498 }
d855497e 3499
4db666cc
MI		 3500 pvr2_trace(PVR2_TRACE_FIRMWARE,
3501 "Done grabbing CPU firmware");
3502 } else {
3503 pvr2_trace(PVR2_TRACE_FIRMWARE,
3504 "Sucking down EEPROM contents");
3505 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3506 if (!hdw->fw_buffer) {
3507 pvr2_trace(PVR2_TRACE_FIRMWARE,
3508 "EEPROM content suck failed.");
3509 break;
3510 }
3511 hdw->fw_size = EEPROM_SIZE;
3512 pvr2_trace(PVR2_TRACE_FIRMWARE,
3513 "Done sucking down EEPROM contents");
3514 }
d855497e
MI		 3515
3516 } while (0); LOCK_GIVE(hdw->big_lock);
3517}
3518
3519
3520/* Return true if we're in a mode for retrieval CPU firmware */
3521int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3522{
5fa1247a 3523 return hdw->fw_buffer != NULL;
d855497e
MI		 3524}
3525
3526
3527int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3528 char *buf,unsigned int cnt)
3529{
3530 int ret = -EINVAL;
3531 LOCK_TAKE(hdw->big_lock); do {
3532 if (!buf) break;
3533 if (!cnt) break;
3534
3535 if (!hdw->fw_buffer) {
3536 ret = -EIO;
3537 break;
3538 }
3539
3540 if (offs >= hdw->fw_size) {
3541 pvr2_trace(PVR2_TRACE_FIRMWARE,
3542 "Read firmware data offs=%d EOF",
3543 offs);
3544 ret = 0;
3545 break;
3546 }
3547
3548 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3549
3550 memcpy(buf,hdw->fw_buffer+offs,cnt);
3551
3552 pvr2_trace(PVR2_TRACE_FIRMWARE,
3553 "Read firmware data offs=%d cnt=%d",
3554 offs,cnt);
3555 ret = cnt;
3556 } while (0); LOCK_GIVE(hdw->big_lock);
3557
3558 return ret;
3559}
3560
3561
fd5a75fe 3562int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
8079384e 3563 enum pvr2_v4l_type index)
d855497e 3564{
fd5a75fe 3565 switch (index) {
8079384e
MI		 3566 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3567 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3568 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
fd5a75fe
MI		 3569 default: return -1;
3570 }
d855497e
MI		 3571}
3572
3573
2fdf3d9c 3574/* Store a v4l minor device number */
fd5a75fe 3575void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
8079384e 3576 enum pvr2_v4l_type index,int v)
d855497e 3577{
fd5a75fe 3578 switch (index) {
6c058fb6
AC		 3579 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;break;
3580 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;break;
3581 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;break;
fd5a75fe
MI		 3582 default: break;
3583 }
d855497e
MI		 3584}
3585
3586
7d12e780 3587static void pvr2_ctl_write_complete(struct urb *urb)
d855497e
MI		 3588{
3589 struct pvr2_hdw *hdw = urb->context;
3590 hdw->ctl_write_pend_flag = 0;
3591 if (hdw->ctl_read_pend_flag) return;
3592 complete(&hdw->ctl_done);
3593}
3594
3595
7d12e780 3596static void pvr2_ctl_read_complete(struct urb *urb)
d855497e
MI		 3597{
3598 struct pvr2_hdw *hdw = urb->context;
3599 hdw->ctl_read_pend_flag = 0;
3600 if (hdw->ctl_write_pend_flag) return;
3601 complete(&hdw->ctl_done);
3602}
3603
3604
3605static void pvr2_ctl_timeout(unsigned long data)
3606{
3607 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3608 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3609 hdw->ctl_timeout_flag = !0;
5e55d2ce 3610 if (hdw->ctl_write_pend_flag)
d855497e 3611 usb_unlink_urb(hdw->ctl_write_urb);
5e55d2ce 3612 if (hdw->ctl_read_pend_flag)
d855497e 3613 usb_unlink_urb(hdw->ctl_read_urb);
d855497e
MI		 3614 }
3615}
3616
3617
e61b6fc5
MI		 3618/* Issue a command and get a response from the device. This extended
3619 version includes a probe flag (which if set means that device errors
3620 should not be logged or treated as fatal) and a timeout in jiffies.
3621 This can be used to non-lethally probe the health of endpoint 1. */
07e337ee
AB		 3622static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3623 unsigned int timeout,int probe_fl,
3624 void *write_data,unsigned int write_len,
3625 void *read_data,unsigned int read_len)
d855497e
MI		 3626{
3627 unsigned int idx;
3628 int status = 0;
3629 struct timer_list timer;
3630 if (!hdw->ctl_lock_held) {
3631 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3632 "Attempted to execute control transfer"
3633 " without lock!!");
3634 return -EDEADLK;
3635 }
681c7399 3636 if (!hdw->flag_ok && !probe_fl) {
d855497e
MI		 3637 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3638 "Attempted to execute control transfer"
3639 " when device not ok");
3640 return -EIO;
3641 }
3642 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3643 if (!probe_fl) {
3644 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3645 "Attempted to execute control transfer"
3646 " when USB is disconnected");
3647 }
3648 return -ENOTTY;
3649 }
3650
3651 /* Ensure that we have sane parameters */
3652 if (!write_data) write_len = 0;
3653 if (!read_data) read_len = 0;
3654 if (write_len > PVR2_CTL_BUFFSIZE) {
3655 pvr2_trace(
3656 PVR2_TRACE_ERROR_LEGS,
3657 "Attempted to execute %d byte"
3658 " control-write transfer (limit=%d)",
3659 write_len,PVR2_CTL_BUFFSIZE);
3660 return -EINVAL;
3661 }
3662 if (read_len > PVR2_CTL_BUFFSIZE) {
3663 pvr2_trace(
3664 PVR2_TRACE_ERROR_LEGS,
3665 "Attempted to execute %d byte"
3666 " control-read transfer (limit=%d)",
3667 write_len,PVR2_CTL_BUFFSIZE);
3668 return -EINVAL;
3669 }
3670 if ((!write_len) && (!read_len)) {
3671 pvr2_trace(
3672 PVR2_TRACE_ERROR_LEGS,
3673 "Attempted to execute null control transfer?");
3674 return -EINVAL;
3675 }
3676
3677
3678 hdw->cmd_debug_state = 1;
62220293 3679 if (write_len && write_data)
d855497e 3680 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
62220293 3681 else
d855497e 3682 hdw->cmd_debug_code = 0;
d855497e
MI		 3683 hdw->cmd_debug_write_len = write_len;
3684 hdw->cmd_debug_read_len = read_len;
3685
3686 /* Initialize common stuff */
3687 init_completion(&hdw->ctl_done);
3688 hdw->ctl_timeout_flag = 0;
3689 hdw->ctl_write_pend_flag = 0;
3690 hdw->ctl_read_pend_flag = 0;
03f23fc5 3691 setup_timer(&timer, pvr2_ctl_timeout, (unsigned long)hdw);
d855497e 3692 timer.expires = jiffies + timeout;
d855497e 3693
62220293 3694 if (write_len && write_data) {
d855497e
MI		 3695 hdw->cmd_debug_state = 2;
3696 /* Transfer write data to internal buffer */
3697 for (idx = 0; idx < write_len; idx++) {
3698 hdw->ctl_write_buffer[idx] =
3699 ((unsigned char *)write_data)[idx];
3700 }
3701 /* Initiate a write request */
3702 usb_fill_bulk_urb(hdw->ctl_write_urb,
3703 hdw->usb_dev,
3704 usb_sndbulkpipe(hdw->usb_dev,
3705 PVR2_CTL_WRITE_ENDPOINT),
3706 hdw->ctl_write_buffer,
3707 write_len,
3708 pvr2_ctl_write_complete,
3709 hdw);
3710 hdw->ctl_write_urb->actual_length = 0;
3711 hdw->ctl_write_pend_flag = !0;
3712 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3713 if (status < 0) {
3714 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3715 "Failed to submit write-control"
3716 " URB status=%d",status);
3717 hdw->ctl_write_pend_flag = 0;
3718 goto done;
3719 }
3720 }
3721
3722 if (read_len) {
3723 hdw->cmd_debug_state = 3;
3724 memset(hdw->ctl_read_buffer,0x43,read_len);
3725 /* Initiate a read request */
3726 usb_fill_bulk_urb(hdw->ctl_read_urb,
3727 hdw->usb_dev,
3728 usb_rcvbulkpipe(hdw->usb_dev,
3729 PVR2_CTL_READ_ENDPOINT),
3730 hdw->ctl_read_buffer,
3731 read_len,
3732 pvr2_ctl_read_complete,
3733 hdw);
3734 hdw->ctl_read_urb->actual_length = 0;
3735 hdw->ctl_read_pend_flag = !0;
3736 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3737 if (status < 0) {
3738 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3739 "Failed to submit read-control"
3740 " URB status=%d",status);
3741 hdw->ctl_read_pend_flag = 0;
3742 goto done;
3743 }
3744 }
3745
3746 /* Start timer */
3747 add_timer(&timer);
3748
3749 /* Now wait for all I/O to complete */
3750 hdw->cmd_debug_state = 4;
3751 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3752 wait_for_completion(&hdw->ctl_done);
3753 }
3754 hdw->cmd_debug_state = 5;
3755
3756 /* Stop timer */
3757 del_timer_sync(&timer);
3758
3759 hdw->cmd_debug_state = 6;
3760 status = 0;
3761
3762 if (hdw->ctl_timeout_flag) {
3763 status = -ETIMEDOUT;
3764 if (!probe_fl) {
3765 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3766 "Timed out control-write");
3767 }
3768 goto done;
3769 }
3770
3771 if (write_len) {
3772 /* Validate results of write request */
3773 if ((hdw->ctl_write_urb->status != 0) &&
3774 (hdw->ctl_write_urb->status != -ENOENT) &&
3775 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3776 (hdw->ctl_write_urb->status != -ECONNRESET)) {
3777 /* USB subsystem is reporting some kind of failure
3778 on the write */
3779 status = hdw->ctl_write_urb->status;
3780 if (!probe_fl) {
3781 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3782 "control-write URB failure,"
3783 " status=%d",
3784 status);
3785 }
3786 goto done;
3787 }
3788 if (hdw->ctl_write_urb->actual_length < write_len) {
3789 /* Failed to write enough data */
3790 status = -EIO;
3791 if (!probe_fl) {
3792 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3793 "control-write URB short,"
3794 " expected=%d got=%d",
3795 write_len,
3796 hdw->ctl_write_urb->actual_length);
3797 }
3798 goto done;
3799 }
3800 }
62220293 3801 if (read_len && read_data) {
d855497e
MI		 3802 /* Validate results of read request */
3803 if ((hdw->ctl_read_urb->status != 0) &&
3804 (hdw->ctl_read_urb->status != -ENOENT) &&
3805 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3806 (hdw->ctl_read_urb->status != -ECONNRESET)) {
3807 /* USB subsystem is reporting some kind of failure
3808 on the read */
3809 status = hdw->ctl_read_urb->status;
3810 if (!probe_fl) {
3811 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3812 "control-read URB failure,"
3813 " status=%d",
3814 status);
3815 }
3816 goto done;
3817 }
3818 if (hdw->ctl_read_urb->actual_length < read_len) {
3819 /* Failed to read enough data */
3820 status = -EIO;
3821 if (!probe_fl) {
3822 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3823 "control-read URB short,"
3824 " expected=%d got=%d",
3825 read_len,
3826 hdw->ctl_read_urb->actual_length);
3827 }
3828 goto done;
3829 }
3830 /* Transfer retrieved data out from internal buffer */
3831 for (idx = 0; idx < read_len; idx++) {
3832 ((unsigned char *)read_data)[idx] =
3833 hdw->ctl_read_buffer[idx];
3834 }
3835 }
3836
3837 done:
3838
3839 hdw->cmd_debug_state = 0;
3840 if ((status < 0) && (!probe_fl)) {
681c7399 3841 pvr2_hdw_render_useless(hdw);
d855497e
MI		 3842 }
3843 return status;
3844}
3845
3846
3847int pvr2_send_request(struct pvr2_hdw *hdw,
3848 void *write_data,unsigned int write_len,
3849 void *read_data,unsigned int read_len)
3850{
3851 return pvr2_send_request_ex(hdw,HZ*4,0,
3852 write_data,write_len,
3853 read_data,read_len);
3854}
3855
1c9d10d4
MI		 3856
3857static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3858{
3859 int ret;
3860 unsigned int cnt = 1;
3861 unsigned int args = 0;
3862 LOCK_TAKE(hdw->ctl_lock);
3863 hdw->cmd_buffer[0] = cmdcode & 0xffu;
3864 args = (cmdcode >> 8) & 0xffu;
3865 args = (args > 2) ? 2 : args;
3866 if (args) {
3867 cnt += args;
3868 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3869 if (args > 1) {
3870 hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3871 }
3872 }
3873 if (pvrusb2_debug & PVR2_TRACE_INIT) {
3874 unsigned int idx;
3875 unsigned int ccnt,bcnt;
3876 char tbuf[50];
3877 cmdcode &= 0xffu;
3878 bcnt = 0;
3879 ccnt = scnprintf(tbuf+bcnt,
3880 sizeof(tbuf)-bcnt,
3881 "Sending FX2 command 0x%x",cmdcode);
3882 bcnt += ccnt;
3883 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3884 if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3885 ccnt = scnprintf(tbuf+bcnt,
3886 sizeof(tbuf)-bcnt,
3887 " \"%s\"",
3888 pvr2_fx2cmd_desc[idx].desc);
3889 bcnt += ccnt;
3890 break;
3891 }
3892 }
3893 if (args) {
3894 ccnt = scnprintf(tbuf+bcnt,
3895 sizeof(tbuf)-bcnt,
3896 " (%u",hdw->cmd_buffer[1]);
3897 bcnt += ccnt;
3898 if (args > 1) {
3899 ccnt = scnprintf(tbuf+bcnt,
3900 sizeof(tbuf)-bcnt,
3901 ",%u",hdw->cmd_buffer[2]);
3902 bcnt += ccnt;
3903 }
3904 ccnt = scnprintf(tbuf+bcnt,
3905 sizeof(tbuf)-bcnt,
3906 ")");
3907 bcnt += ccnt;
3908 }
3909 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3910 }
3911 ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3912 LOCK_GIVE(hdw->ctl_lock);
3913 return ret;
3914}
3915
3916
d855497e
MI		 3917int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3918{
3919 int ret;
3920
3921 LOCK_TAKE(hdw->ctl_lock);
3922
8d364363 3923 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
d855497e
MI		 3924 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3925 hdw->cmd_buffer[5] = 0;
3926 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3927 hdw->cmd_buffer[7] = reg & 0xff;
3928
3929
3930 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3931
3932 LOCK_GIVE(hdw->ctl_lock);
3933
3934 return ret;
3935}
3936
3937
07e337ee 3938static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
d855497e
MI		 3939{
3940 int ret = 0;
3941
3942 LOCK_TAKE(hdw->ctl_lock);
3943
8d364363 3944 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
d855497e
MI		 3945 hdw->cmd_buffer[1] = 0;
3946 hdw->cmd_buffer[2] = 0;
3947 hdw->cmd_buffer[3] = 0;
3948 hdw->cmd_buffer[4] = 0;
3949 hdw->cmd_buffer[5] = 0;
3950 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3951 hdw->cmd_buffer[7] = reg & 0xff;
3952
3953 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3954 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3955
3956 LOCK_GIVE(hdw->ctl_lock);
3957
3958 return ret;
3959}
3960
3961
681c7399 3962void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
d855497e
MI		 3963{
3964 if (!hdw->flag_ok) return;
681c7399
MI		 3965 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3966 "Device being rendered inoperable");
d855497e 3967 if (hdw->vid_stream) {
a0fd1cb1 3968 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
d855497e 3969 }
681c7399
MI		 3970 hdw->flag_ok = 0;
3971 trace_stbit("flag_ok",hdw->flag_ok);
3972 pvr2_hdw_state_sched(hdw);
d855497e
MI		 3973}
3974
3975
3976void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3977{
3978 int ret;
3979 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
a0fd1cb1 3980 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
011b15df 3981 if (ret == 0) {
d855497e
MI		 3982 ret = usb_reset_device(hdw->usb_dev);
3983 usb_unlock_device(hdw->usb_dev);
3984 } else {
3985 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3986 "Failed to lock USB device ret=%d",ret);
3987 }
3988 if (init_pause_msec) {
3989 pvr2_trace(PVR2_TRACE_INFO,
3990 "Waiting %u msec for hardware to settle",
3991 init_pause_msec);
3992 msleep(init_pause_msec);
3993 }
3994
3995}
3996
3997
3998void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3999{
6861800c 4000 char *da;
d855497e
MI		 4001 unsigned int pipe;
4002 int ret;
4003
4004 if (!hdw->usb_dev) return;
4005
6861800c
MI		 4006 da = kmalloc(16, GFP_KERNEL);
4007
4008 if (da == NULL) {
4009 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4010 "Unable to allocate memory to control CPU reset");
4011 return;
4012 }
4013
d855497e
MI		 4014 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4015
4016 da[0] = val ? 0x01 : 0x00;
4017
4018 /* Write the CPUCS register on the 8051. The lsb of the register
4019 is the reset bit; a 1 asserts reset while a 0 clears it. */
4020 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4021 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4022 if (ret < 0) {
4023 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4024 "cpureset_assert(%d) error=%d",val,ret);
4025 pvr2_hdw_render_useless(hdw);
4026 }
6861800c
MI		 4027
4028 kfree(da);
d855497e
MI		 4029}
4030
4031
4032int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4033{
1c9d10d4 4034 return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
d855497e
MI		 4035}
4036
4037
e1edb19a
MK		 4038int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4039{
1c9d10d4 4040 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
e1edb19a
MK		 4041}
4042
1c9d10d4 4043
d855497e
MI		 4044
4045int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4046{
af78e16b
MI		 4047 pvr2_trace(PVR2_TRACE_INIT,
4048 "Requesting decoder reset");
af78e16b
MI		 4049 if (hdw->decoder_client_id) {
4050 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4051 core, reset, 0);
e17d787c 4052 pvr2_hdw_cx25840_vbi_hack(hdw);
af78e16b 4053 return 0;
d855497e 4054 }
d855497e 4055 pvr2_trace(PVR2_TRACE_INIT,
af78e16b
MI		 4056 "Unable to reset decoder: nothing attached");
4057 return -ENOTTY;
d855497e
MI		 4058}
4059
4060
62433e31 4061static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
84147f3d 4062{
1c9d10d4
MI		 4063 hdw->flag_ok = !0;
4064 return pvr2_issue_simple_cmd(hdw,
4065 FX2CMD_HCW_DEMOD_RESETIN |
4066 (1 << 8) |
4067 ((onoff ? 1 : 0) << 16));
84147f3d
MI		 4068}
4069
84147f3d 4070
62433e31 4071static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
84147f3d 4072{
1c9d10d4
MI		 4073 hdw->flag_ok = !0;
4074 return pvr2_issue_simple_cmd(hdw,(onoff ?
4075 FX2CMD_ONAIR_DTV_POWER_ON :
4076 FX2CMD_ONAIR_DTV_POWER_OFF));
84147f3d
MI		 4077}
4078
62433e31
MI		 4079
4080static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4081 int onoff)
84147f3d 4082{
1c9d10d4
MI		 4083 return pvr2_issue_simple_cmd(hdw,(onoff ?
4084 FX2CMD_ONAIR_DTV_STREAMING_ON :
4085 FX2CMD_ONAIR_DTV_STREAMING_OFF));
84147f3d
MI		 4086}
4087
62433e31
MI		 4088
4089static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4090{
4091 int cmode;
4092 /* Compare digital/analog desired setting with current setting. If
4093 they don't match, fix it... */
4094 cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4095 if (cmode == hdw->pathway_state) {
4096 /* They match; nothing to do */
4097 return;
4098 }
4099
4100 switch (hdw->hdw_desc->digital_control_scheme) {
4101 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4102 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4103 if (cmode == PVR2_PATHWAY_ANALOG) {
4104 /* If moving to analog mode, also force the decoder
4105 to reset. If no decoder is attached, then it's
4106 ok to ignore this because if/when the decoder
4107 attaches, it will reset itself at that time. */
4108 pvr2_hdw_cmd_decoder_reset(hdw);
4109 }
4110 break;
4111 case PVR2_DIGITAL_SCHEME_ONAIR:
4112 /* Supposedly we should always have the power on whether in
4113 digital or analog mode. But for now do what appears to
4114 work... */
bb0c2fe0 4115 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
62433e31
MI		 4116 break;
4117 default: break;
4118 }
4119
1b9c18c5 4120 pvr2_hdw_untrip_unlocked(hdw);
62433e31
MI		 4121 hdw->pathway_state = cmode;
4122}
4123
4124
e9b59f6e 4125static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
c55a97d7
MI		 4126{
4127 /* change some GPIO data
4128 *
4129 * note: bit d7 of dir appears to control the LED,
4130 * so we shut it off here.
4131 *
c55a97d7 4132 */
40381cb0 4133 if (onoff) {
c55a97d7 4134 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
40381cb0 4135 } else {
c55a97d7 4136 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
40381cb0 4137 }
c55a97d7 4138 pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
40381cb0 4139}
c55a97d7 4140
40381cb0
MI		 4141
4142typedef void (*led_method_func)(struct pvr2_hdw *,int);
4143
4144static led_method_func led_methods[] = {
4145 [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4146};
4147
4148
4149/* Toggle LED */
4150static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4151{
4152 unsigned int scheme_id;
4153 led_method_func fp;
4154
4155 if ((!onoff) == (!hdw->led_on)) return;
4156
4157 hdw->led_on = onoff != 0;
4158
4159 scheme_id = hdw->hdw_desc->led_scheme;
4160 if (scheme_id < ARRAY_SIZE(led_methods)) {
4161 fp = led_methods[scheme_id];
4162 } else {
4163 fp = NULL;
4164 }
4165
4166 if (fp) (*fp)(hdw,onoff);
c55a97d7
MI		 4167}
4168
4169
e61b6fc5 4170/* Stop / start video stream transport */
07e337ee 4171static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
d855497e 4172{
bb0c2fe0
MI		 4173 int ret;
4174
4175 /* If we're in analog mode, then just issue the usual analog
4176 command. */
4177 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4178 return pvr2_issue_simple_cmd(hdw,
4179 (runFl ?
4180 FX2CMD_STREAMING_ON :
4181 FX2CMD_STREAMING_OFF));
4182 /*Note: Not reached */
4183 }
4184
4185 if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4186 /* Whoops, we don't know what mode we're in... */
4187 return -EINVAL;
4188 }
4189
4190 /* To get here we have to be in digital mode. The mechanism here
4191 is unfortunately different for different vendors. So we switch
4192 on the device's digital scheme attribute in order to figure out
4193 what to do. */
4194 switch (hdw->hdw_desc->digital_control_scheme) {
4195 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4196 return pvr2_issue_simple_cmd(hdw,
4197 (runFl ?
4198 FX2CMD_HCW_DTV_STREAMING_ON :
4199 FX2CMD_HCW_DTV_STREAMING_OFF));
4200 case PVR2_DIGITAL_SCHEME_ONAIR:
4201 ret = pvr2_issue_simple_cmd(hdw,
4202 (runFl ?
4203 FX2CMD_STREAMING_ON :
4204 FX2CMD_STREAMING_OFF));
4205 if (ret) return ret;
4206 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4207 default:
4208 return -EINVAL;
62433e31 4209 }
d855497e
MI		 4210}
4211
4212
62433e31
MI		 4213/* Evaluate whether or not state_pathway_ok can change */
4214static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4215{
4216 if (hdw->state_pathway_ok) {
4217 /* Nothing to do if pathway is already ok */
4218 return 0;
4219 }
4220 if (!hdw->state_pipeline_idle) {
4221 /* Not allowed to change anything if pipeline is not idle */
4222 return 0;
4223 }
4224 pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4225 hdw->state_pathway_ok = !0;
e9db1ff2 4226 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 4227 return !0;
4228}
4229
4230
681c7399
MI		 4231/* Evaluate whether or not state_encoder_ok can change */
4232static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4233{
4234 if (hdw->state_encoder_ok) return 0;
4235 if (hdw->flag_tripped) return 0;
4236 if (hdw->state_encoder_run) return 0;
4237 if (hdw->state_encoder_config) return 0;
4238 if (hdw->state_decoder_run) return 0;
4239 if (hdw->state_usbstream_run) return 0;
72998b71
MI		 4240 if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4241 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4242 } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4243 return 0;
4244 }
4245
681c7399
MI		 4246 if (pvr2_upload_firmware2(hdw) < 0) {
4247 hdw->flag_tripped = !0;
4248 trace_stbit("flag_tripped",hdw->flag_tripped);
4249 return !0;
4250 }
4251 hdw->state_encoder_ok = !0;
4252 trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4253 return !0;
4254}
4255
4256
4257/* Evaluate whether or not state_encoder_config can change */
4258static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4259{
4260 if (hdw->state_encoder_config) {
4261 if (hdw->state_encoder_ok) {
4262 if (hdw->state_pipeline_req &&
4263 !hdw->state_pipeline_pause) return 0;
4264 }
4265 hdw->state_encoder_config = 0;
4266 hdw->state_encoder_waitok = 0;
4267 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4268 /* paranoia - solve race if timer just completed */
4269 del_timer_sync(&hdw->encoder_wait_timer);
4270 } else {
62433e31
MI		 4271 if (!hdw->state_pathway_ok ||
4272 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4273 !hdw->state_encoder_ok ||
681c7399
MI		 4274 !hdw->state_pipeline_idle ||
4275 hdw->state_pipeline_pause ||
4276 !hdw->state_pipeline_req ||
4277 !hdw->state_pipeline_config) {
4278 /* We must reset the enforced wait interval if
4279 anything has happened that might have disturbed
4280 the encoder. This should be a rare case. */
4281 if (timer_pending(&hdw->encoder_wait_timer)) {
4282 del_timer_sync(&hdw->encoder_wait_timer);
4283 }
4284 if (hdw->state_encoder_waitok) {
4285 /* Must clear the state - therefore we did
4286 something to a state bit and must also
4287 return true. */
4288 hdw->state_encoder_waitok = 0;
4289 trace_stbit("state_encoder_waitok",
4290 hdw->state_encoder_waitok);
4291 return !0;
4292 }
4293 return 0;
4294 }
4295 if (!hdw->state_encoder_waitok) {
4296 if (!timer_pending(&hdw->encoder_wait_timer)) {
4297 /* waitok flag wasn't set and timer isn't
4298 running. Check flag once more to avoid
4299 a race then start the timer. This is
4300 the point when we measure out a minimal
4301 quiet interval before doing something to
4302 the encoder. */
4303 if (!hdw->state_encoder_waitok) {
4304 hdw->encoder_wait_timer.expires =
3edf7eb8
NMG		 4305 jiffies + msecs_to_jiffies(
4306 TIME_MSEC_ENCODER_WAIT);
681c7399
MI		 4307 add_timer(&hdw->encoder_wait_timer);
4308 }
4309 }
4310 /* We can't continue until we know we have been
4311 quiet for the interval measured by this
4312 timer. */
4313 return 0;
4314 }
4315 pvr2_encoder_configure(hdw);
4316 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4317 }
4318 trace_stbit("state_encoder_config",hdw->state_encoder_config);
4319 return !0;
4320}
4321
4322
d913d630
MI		 4323/* Return true if the encoder should not be running. */
4324static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4325{
4326 if (!hdw->state_encoder_ok) {
4327 /* Encoder isn't healthy at the moment, so stop it. */
4328 return !0;
4329 }
4330 if (!hdw->state_pathway_ok) {
4331 /* Mode is not understood at the moment (i.e. it wants to
4332 change), so encoder must be stopped. */
4333 return !0;
4334 }
4335
4336 switch (hdw->pathway_state) {
4337 case PVR2_PATHWAY_ANALOG:
4338 if (!hdw->state_decoder_run) {
4339 /* We're in analog mode and the decoder is not
4340 running; thus the encoder should be stopped as
4341 well. */
4342 return !0;
4343 }
4344 break;
4345 case PVR2_PATHWAY_DIGITAL:
4346 if (hdw->state_encoder_runok) {
4347 /* This is a funny case. We're in digital mode so
4348 really the encoder should be stopped. However
4349 if it really is running, only kill it after
4350 runok has been set. This gives a chance for the
4351 onair quirk to function (encoder must run
4352 briefly first, at least once, before onair
4353 digital streaming can work). */
4354 return !0;
4355 }
4356 break;
4357 default:
4358 /* Unknown mode; so encoder should be stopped. */
4359 return !0;
4360 }
4361
4362 /* If we get here, we haven't found a reason to stop the
4363 encoder. */
4364 return 0;
4365}
4366
4367
4368/* Return true if the encoder should be running. */
4369static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4370{
4371 if (!hdw->state_encoder_ok) {
4372 /* Don't run the encoder if it isn't healthy... */
4373 return 0;
4374 }
4375 if (!hdw->state_pathway_ok) {
4376 /* Don't run the encoder if we don't (yet) know what mode
4377 we need to be in... */
4378 return 0;
4379 }
4380
4381 switch (hdw->pathway_state) {
4382 case PVR2_PATHWAY_ANALOG:
6e931375 4383 if (hdw->state_decoder_run && hdw->state_decoder_ready) {
d913d630
MI		 4384 /* In analog mode, if the decoder is running, then
4385 run the encoder. */
4386 return !0;
4387 }
4388 break;
4389 case PVR2_PATHWAY_DIGITAL:
4390 if ((hdw->hdw_desc->digital_control_scheme ==
4391 PVR2_DIGITAL_SCHEME_ONAIR) &&
4392 !hdw->state_encoder_runok) {
4393 /* This is a quirk. OnAir hardware won't stream
4394 digital until the encoder has been run at least
4395 once, for a minimal period of time (empiricially
4396 measured to be 1/4 second). So if we're on
4397 OnAir hardware and the encoder has never been
4398 run at all, then start the encoder. Normal
4399 state machine logic in the driver will
4400 automatically handle the remaining bits. */
4401 return !0;
4402 }
4403 break;
4404 default:
4405 /* For completeness (unknown mode; encoder won't run ever) */
4406 break;
4407 }
4408 /* If we get here, then we haven't found any reason to run the
4409 encoder, so don't run it. */
4410 return 0;
4411}
4412
4413
681c7399
MI		 4414/* Evaluate whether or not state_encoder_run can change */
4415static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4416{
4417 if (hdw->state_encoder_run) {
d913d630 4418 if (!state_check_disable_encoder_run(hdw)) return 0;
681c7399 4419 if (hdw->state_encoder_ok) {
d913d630 4420 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 4421 if (pvr2_encoder_stop(hdw) < 0) return !0;
4422 }
4423 hdw->state_encoder_run = 0;
4424 } else {
d913d630 4425 if (!state_check_enable_encoder_run(hdw)) return 0;
681c7399
MI		 4426 if (pvr2_encoder_start(hdw) < 0) return !0;
4427 hdw->state_encoder_run = !0;
d913d630 4428 if (!hdw->state_encoder_runok) {
3edf7eb8
NMG		 4429 hdw->encoder_run_timer.expires = jiffies +
4430 msecs_to_jiffies(TIME_MSEC_ENCODER_OK);
d913d630
MI		 4431 add_timer(&hdw->encoder_run_timer);
4432 }
681c7399
MI		 4433 }
4434 trace_stbit("state_encoder_run",hdw->state_encoder_run);
4435 return !0;
4436}
4437
4438
4439/* Timeout function for quiescent timer. */
4440static void pvr2_hdw_quiescent_timeout(unsigned long data)
4441{
4442 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4443 hdw->state_decoder_quiescent = !0;
4444 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4445 hdw->state_stale = !0;
4446 queue_work(hdw->workqueue,&hdw->workpoll);
4447}
4448
4449
6e931375
MI		 4450/* Timeout function for decoder stabilization timer. */
4451static void pvr2_hdw_decoder_stabilization_timeout(unsigned long data)
4452{
4453 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4454 hdw->state_decoder_ready = !0;
4455 trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4456 hdw->state_stale = !0;
4457 queue_work(hdw->workqueue, &hdw->workpoll);
4458}
4459
4460
681c7399
MI		 4461/* Timeout function for encoder wait timer. */
4462static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4463{
4464 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4465 hdw->state_encoder_waitok = !0;
4466 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4467 hdw->state_stale = !0;
4468 queue_work(hdw->workqueue,&hdw->workpoll);
4469}
4470
4471
d913d630
MI		 4472/* Timeout function for encoder run timer. */
4473static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4474{
4475 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4476 if (!hdw->state_encoder_runok) {
4477 hdw->state_encoder_runok = !0;
4478 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4479 hdw->state_stale = !0;
4480 queue_work(hdw->workqueue,&hdw->workpoll);
4481 }
4482}
4483
4484
681c7399
MI		 4485/* Evaluate whether or not state_decoder_run can change */
4486static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4487{
4488 if (hdw->state_decoder_run) {
4489 if (hdw->state_encoder_ok) {
4490 if (hdw->state_pipeline_req &&
62433e31
MI		 4491 !hdw->state_pipeline_pause &&
4492 hdw->state_pathway_ok) return 0;
681c7399
MI		 4493 }
4494 if (!hdw->flag_decoder_missed) {
4495 pvr2_decoder_enable(hdw,0);
4496 }
4497 hdw->state_decoder_quiescent = 0;
4498 hdw->state_decoder_run = 0;
6e931375 4499 /* paranoia - solve race if timer(s) just completed */
681c7399 4500 del_timer_sync(&hdw->quiescent_timer);
6e931375
MI		 4501 /* Kill the stabilization timer, in case we're killing the
4502 encoder before the previous stabilization interval has
4503 been properly timed. */
4504 del_timer_sync(&hdw->decoder_stabilization_timer);
4505 hdw->state_decoder_ready = 0;
681c7399
MI		 4506 } else {
4507 if (!hdw->state_decoder_quiescent) {
4508 if (!timer_pending(&hdw->quiescent_timer)) {
4509 /* We don't do something about the
4510 quiescent timer until right here because
4511 we also want to catch cases where the
4512 decoder was already not running (like
4513 after initialization) as opposed to
4514 knowing that we had just stopped it.
4515 The second flag check is here to cover a
4516 race - the timer could have run and set
4517 this flag just after the previous check
4518 but before we did the pending check. */
4519 if (!hdw->state_decoder_quiescent) {
4520 hdw->quiescent_timer.expires =
3edf7eb8
NMG		 4521 jiffies + msecs_to_jiffies(
4522 TIME_MSEC_DECODER_WAIT);
681c7399
MI		 4523 add_timer(&hdw->quiescent_timer);
4524 }
4525 }
4526 /* Don't allow decoder to start again until it has
4527 been quiesced first. This little detail should
4528 hopefully further stabilize the encoder. */
4529 return 0;
4530 }
62433e31
MI		 4531 if (!hdw->state_pathway_ok ||
4532 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4533 !hdw->state_pipeline_req ||
681c7399
MI		 4534 hdw->state_pipeline_pause ||
4535 !hdw->state_pipeline_config ||
4536 !hdw->state_encoder_config ||
4537 !hdw->state_encoder_ok) return 0;
4538 del_timer_sync(&hdw->quiescent_timer);
4539 if (hdw->flag_decoder_missed) return 0;
4540 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4541 hdw->state_decoder_quiescent = 0;
6e931375 4542 hdw->state_decoder_ready = 0;
681c7399 4543 hdw->state_decoder_run = !0;
fb640224
MI		 4544 if (hdw->decoder_client_id == PVR2_CLIENT_ID_SAA7115) {
4545 hdw->decoder_stabilization_timer.expires =
3edf7eb8
NMG		 4546 jiffies + msecs_to_jiffies(
4547 TIME_MSEC_DECODER_STABILIZATION_WAIT);
fb640224
MI		 4548 add_timer(&hdw->decoder_stabilization_timer);
4549 } else {
4550 hdw->state_decoder_ready = !0;
4551 }
681c7399
MI		 4552 }
4553 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4554 trace_stbit("state_decoder_run",hdw->state_decoder_run);
6e931375 4555 trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
681c7399
MI		 4556 return !0;
4557}
4558
4559
4560/* Evaluate whether or not state_usbstream_run can change */
4561static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4562{
4563 if (hdw->state_usbstream_run) {
72998b71 4564 int fl = !0;
62433e31 4565 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
72998b71
MI		 4566 fl = (hdw->state_encoder_ok &&
4567 hdw->state_encoder_run);
4568 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4569 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4570 fl = hdw->state_encoder_ok;
4571 }
4572 if (fl &&
4573 hdw->state_pipeline_req &&
4574 !hdw->state_pipeline_pause &&
4575 hdw->state_pathway_ok) {
4576 return 0;
681c7399
MI		 4577 }
4578 pvr2_hdw_cmd_usbstream(hdw,0);
4579 hdw->state_usbstream_run = 0;
4580 } else {
62433e31
MI		 4581 if (!hdw->state_pipeline_req ||
4582 hdw->state_pipeline_pause ||
4583 !hdw->state_pathway_ok) return 0;
4584 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4585 if (!hdw->state_encoder_ok ||
4586 !hdw->state_encoder_run) return 0;
72998b71
MI		 4587 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4588 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4589 if (!hdw->state_encoder_ok) return 0;
d913d630
MI		 4590 if (hdw->state_encoder_run) return 0;
4591 if (hdw->hdw_desc->digital_control_scheme ==
4592 PVR2_DIGITAL_SCHEME_ONAIR) {
4593 /* OnAir digital receivers won't stream
4594 unless the analog encoder has run first.
4595 Why? I have no idea. But don't even
4596 try until we know the analog side is
4597 known to have run. */
4598 if (!hdw->state_encoder_runok) return 0;
4599 }
62433e31 4600 }
681c7399
MI		 4601 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4602 hdw->state_usbstream_run = !0;
4603 }
4604 trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4605 return !0;
4606}
4607
4608
4609/* Attempt to configure pipeline, if needed */
4610static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4611{
4612 if (hdw->state_pipeline_config ||
4613 hdw->state_pipeline_pause) return 0;
4614 pvr2_hdw_commit_execute(hdw);
4615 return !0;
4616}
4617
4618
4619/* Update pipeline idle and pipeline pause tracking states based on other
4620 inputs. This must be called whenever the other relevant inputs have
4621 changed. */
4622static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4623{
4624 unsigned int st;
4625 int updatedFl = 0;
4626 /* Update pipeline state */
4627 st = !(hdw->state_encoder_run ||
4628 hdw->state_decoder_run ||
4629 hdw->state_usbstream_run ||
4630 (!hdw->state_decoder_quiescent));
4631 if (!st != !hdw->state_pipeline_idle) {
4632 hdw->state_pipeline_idle = st;
4633 updatedFl = !0;
4634 }
4635 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4636 hdw->state_pipeline_pause = 0;
4637 updatedFl = !0;
4638 }
4639 return updatedFl;
4640}
4641
4642
4643typedef int (*state_eval_func)(struct pvr2_hdw *);
4644
4645/* Set of functions to be run to evaluate various states in the driver. */
ebff0330 4646static const state_eval_func eval_funcs[] = {
62433e31 4647 state_eval_pathway_ok,
681c7399
MI		 4648 state_eval_pipeline_config,
4649 state_eval_encoder_ok,
4650 state_eval_encoder_config,
4651 state_eval_decoder_run,
4652 state_eval_encoder_run,
4653 state_eval_usbstream_run,
4654};
4655
4656
4657/* Process various states and return true if we did anything interesting. */
4658static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4659{
4660 unsigned int i;
4661 int state_updated = 0;
4662 int check_flag;
4663
4664 if (!hdw->state_stale) return 0;
4665 if ((hdw->fw1_state != FW1_STATE_OK) ||
4666 !hdw->flag_ok) {
4667 hdw->state_stale = 0;
4668 return !0;
4669 }
4670 /* This loop is the heart of the entire driver. It keeps trying to
4671 evaluate various bits of driver state until nothing changes for
4672 one full iteration. Each "bit of state" tracks some global
4673 aspect of the driver, e.g. whether decoder should run, if
4674 pipeline is configured, usb streaming is on, etc. We separately
4675 evaluate each of those questions based on other driver state to
4676 arrive at the correct running configuration. */
4677 do {
4678 check_flag = 0;
4679 state_update_pipeline_state(hdw);
4680 /* Iterate over each bit of state */
4681 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4682 if ((*eval_funcs[i])(hdw)) {
4683 check_flag = !0;
4684 state_updated = !0;
4685 state_update_pipeline_state(hdw);
4686 }
4687 }
4688 } while (check_flag && hdw->flag_ok);
4689 hdw->state_stale = 0;
4690 trace_stbit("state_stale",hdw->state_stale);
4691 return state_updated;
4692}
4693
4694
1cb03b76
MI		 4695static unsigned int print_input_mask(unsigned int msk,
4696 char *buf,unsigned int acnt)
4697{
4698 unsigned int idx,ccnt;
4699 unsigned int tcnt = 0;
4700 for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4701 if (!((1 << idx) & msk)) continue;
4702 ccnt = scnprintf(buf+tcnt,
4703 acnt-tcnt,
4704 "%s%s",
4705 (tcnt ? ", " : ""),
4706 control_values_input[idx]);
4707 tcnt += ccnt;
4708 }
4709 return tcnt;
4710}
4711
4712
62433e31
MI		 4713static const char *pvr2_pathway_state_name(int id)
4714{
4715 switch (id) {
4716 case PVR2_PATHWAY_ANALOG: return "analog";
4717 case PVR2_PATHWAY_DIGITAL: return "digital";
4718 default: return "unknown";
4719 }
4720}
4721
4722
681c7399
MI		 4723static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4724 char *buf,unsigned int acnt)
4725{
4726 switch (which) {
4727 case 0:
4728 return scnprintf(
4729 buf,acnt,
e9db1ff2 4730 "driver:%s%s%s%s%s <mode=%s>",
681c7399
MI		 4731 (hdw->flag_ok ? " <ok>" : " <fail>"),
4732 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4733 (hdw->flag_disconnected ? " <disconnected>" :
4734 " <connected>"),
4735 (hdw->flag_tripped ? " <tripped>" : ""),
62433e31
MI		 4736 (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4737 pvr2_pathway_state_name(hdw->pathway_state));
4738
681c7399
MI		 4739 case 1:
4740 return scnprintf(
4741 buf,acnt,
4742 "pipeline:%s%s%s%s",
4743 (hdw->state_pipeline_idle ? " <idle>" : ""),
4744 (hdw->state_pipeline_config ?
4745 " <configok>" : " <stale>"),
4746 (hdw->state_pipeline_req ? " <req>" : ""),
4747 (hdw->state_pipeline_pause ? " <pause>" : ""));
4748 case 2:
4749 return scnprintf(
4750 buf,acnt,
62433e31 4751 "worker:%s%s%s%s%s%s%s",
681c7399 4752 (hdw->state_decoder_run ?
6e931375
MI		 4753 (hdw->state_decoder_ready ?
4754 "<decode:run>" : " <decode:start>") :
681c7399
MI		 4755 (hdw->state_decoder_quiescent ?
4756 "" : " <decode:stop>")),
4757 (hdw->state_decoder_quiescent ?
4758 " <decode:quiescent>" : ""),
4759 (hdw->state_encoder_ok ?
4760 "" : " <encode:init>"),
4761 (hdw->state_encoder_run ?
d913d630
MI		 4762 (hdw->state_encoder_runok ?
4763 " <encode:run>" :
4764 " <encode:firstrun>") :
4765 (hdw->state_encoder_runok ?
4766 " <encode:stop>" :
4767 " <encode:virgin>")),
681c7399
MI		 4768 (hdw->state_encoder_config ?
4769 " <encode:configok>" :
4770 (hdw->state_encoder_waitok ?
b9a37d91 4771 "" : " <encode:waitok>")),
681c7399 4772 (hdw->state_usbstream_run ?
62433e31
MI		 4773 " <usb:run>" : " <usb:stop>"),
4774 (hdw->state_pathway_ok ?
e9db1ff2 4775 " <pathway:ok>" : ""));
681c7399
MI		 4776 case 3:
4777 return scnprintf(
4778 buf,acnt,
4779 "state: %s",
4780 pvr2_get_state_name(hdw->master_state));
ad0992e9 4781 case 4: {
1cb03b76
MI		 4782 unsigned int tcnt = 0;
4783 unsigned int ccnt;
4784
4785 ccnt = scnprintf(buf,
4786 acnt,
4787 "Hardware supported inputs: ");
4788 tcnt += ccnt;
4789 tcnt += print_input_mask(hdw->input_avail_mask,
4790 buf+tcnt,
4791 acnt-tcnt);
4792 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4793 ccnt = scnprintf(buf+tcnt,
4794 acnt-tcnt,
4795 "; allowed inputs: ");
4796 tcnt += ccnt;
4797 tcnt += print_input_mask(hdw->input_allowed_mask,
4798 buf+tcnt,
4799 acnt-tcnt);
4800 }
4801 return tcnt;
4802 }
4803 case 5: {
ad0992e9
MI		 4804 struct pvr2_stream_stats stats;
4805 if (!hdw->vid_stream) break;
4806 pvr2_stream_get_stats(hdw->vid_stream,
4807 &stats,
4808 0);
4809 return scnprintf(
4810 buf,acnt,
4811 "Bytes streamed=%u"
4812 " URBs: queued=%u idle=%u ready=%u"
4813 " processed=%u failed=%u",
4814 stats.bytes_processed,
4815 stats.buffers_in_queue,
4816 stats.buffers_in_idle,
4817 stats.buffers_in_ready,
4818 stats.buffers_processed,
4819 stats.buffers_failed);
4820 }
27eab384
MI		 4821 case 6: {
4822 unsigned int id = hdw->ir_scheme_active;
4823 return scnprintf(buf, acnt, "ir scheme: id=%d %s", id,
4824 (id >= ARRAY_SIZE(ir_scheme_names) ?
4825 "?" : ir_scheme_names[id]));
4826 }
2eb563b7
MI		 4827 default: break;
4828 }
4829 return 0;
4830}
4831
4832
4833/* Generate report containing info about attached sub-devices and attached
4834 i2c clients, including an indication of which attached i2c clients are
4835 actually sub-devices. */
4836static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
4837 char *buf, unsigned int acnt)
4838{
4839 struct v4l2_subdev *sd;
4840 unsigned int tcnt = 0;
4841 unsigned int ccnt;
4842 struct i2c_client *client;
2eb563b7
MI		 4843 const char *p;
4844 unsigned int id;
4845
fa7ce764 4846 ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n");
2eb563b7
MI		 4847 tcnt += ccnt;
4848 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4849 id = sd->grp_id;
4850 p = NULL;
4851 if (id < ARRAY_SIZE(module_names)) p = module_names[id];
4852 if (p) {
fa7ce764 4853 ccnt = scnprintf(buf + tcnt, acnt - tcnt, " %s:", p);
2eb563b7
MI		 4854 tcnt += ccnt;
4855 } else {
4856 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
fa7ce764 4857 " (unknown id=%u):", id);
2eb563b7
MI		 4858 tcnt += ccnt;
4859 }
fa7ce764
JD		 4860 client = v4l2_get_subdevdata(sd);
4861 if (client) {
4862 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4863 " %s @ %02x\n", client->name,
4864 client->addr);
4865 tcnt += ccnt;
4866 } else {
4867 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4868 " no i2c client\n");
4869 tcnt += ccnt;
858f910e 4870 }
681c7399 4871 }
2eb563b7 4872 return tcnt;
681c7399
MI		 4873}
4874
4875
4876unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4877 char *buf,unsigned int acnt)
4878{
4879 unsigned int bcnt,ccnt,idx;
4880 bcnt = 0;
4881 LOCK_TAKE(hdw->big_lock);
4882 for (idx = 0; ; idx++) {
4883 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4884 if (!ccnt) break;
4885 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4886 if (!acnt) break;
4887 buf[0] = '\n'; ccnt = 1;
4888 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4889 }
2eb563b7
MI		 4890 ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
4891 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
681c7399
MI		 4892 LOCK_GIVE(hdw->big_lock);
4893 return bcnt;
4894}
4895
4896
4897static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4898{
2eb563b7
MI		 4899 char buf[256];
4900 unsigned int idx, ccnt;
4901 unsigned int lcnt, ucnt;
681c7399
MI		 4902
4903 for (idx = 0; ; idx++) {
4904 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4905 if (!ccnt) break;
4906 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4907 }
2eb563b7 4908 ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
2e158d45
MCC		 4909 if (ccnt >= sizeof(buf))
4910 ccnt = sizeof(buf);
4911
2eb563b7
MI		 4912 ucnt = 0;
4913 while (ucnt < ccnt) {
4914 lcnt = 0;
4915 while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
4916 lcnt++;
4917 }
4918 printk(KERN_INFO "%s %.*s\n", hdw->name, lcnt, buf + ucnt);
4919 ucnt += lcnt + 1;
4920 }
681c7399
MI		 4921}
4922
4923
4924/* Evaluate and update the driver's current state, taking various actions
4925 as appropriate for the update. */
4926static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4927{
4928 unsigned int st;
4929 int state_updated = 0;
4930 int callback_flag = 0;
1b9c18c5 4931 int analog_mode;
681c7399
MI		 4932
4933 pvr2_trace(PVR2_TRACE_STBITS,
4934 "Drive state check START");
4935 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4936 pvr2_hdw_state_log_state(hdw);
4937 }
4938
4939 /* Process all state and get back over disposition */
4940 state_updated = pvr2_hdw_state_update(hdw);
4941
1b9c18c5
MI		 4942 analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4943
681c7399
MI		 4944 /* Update master state based upon all other states. */
4945 if (!hdw->flag_ok) {
4946 st = PVR2_STATE_DEAD;
4947 } else if (hdw->fw1_state != FW1_STATE_OK) {
4948 st = PVR2_STATE_COLD;
72998b71
MI		 4949 } else if ((analog_mode ||
4950 hdw->hdw_desc->flag_digital_requires_cx23416) &&
4951 !hdw->state_encoder_ok) {
681c7399 4952 st = PVR2_STATE_WARM;
1b9c18c5
MI		 4953 } else if (hdw->flag_tripped ||
4954 (analog_mode && hdw->flag_decoder_missed)) {
681c7399 4955 st = PVR2_STATE_ERROR;
62433e31 4956 } else if (hdw->state_usbstream_run &&
1b9c18c5 4957 (!analog_mode ||
62433e31 4958 (hdw->state_encoder_run && hdw->state_decoder_run))) {
681c7399
MI		 4959 st = PVR2_STATE_RUN;
4960 } else {
4961 st = PVR2_STATE_READY;
4962 }
4963 if (hdw->master_state != st) {
4964 pvr2_trace(PVR2_TRACE_STATE,
4965 "Device state change from %s to %s",
4966 pvr2_get_state_name(hdw->master_state),
4967 pvr2_get_state_name(st));
40381cb0 4968 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
681c7399
MI		 4969 hdw->master_state = st;
4970 state_updated = !0;
4971 callback_flag = !0;
4972 }
4973 if (state_updated) {
4974 /* Trigger anyone waiting on any state changes here. */
4975 wake_up(&hdw->state_wait_data);
4976 }
4977
4978 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4979 pvr2_hdw_state_log_state(hdw);
4980 }
4981 pvr2_trace(PVR2_TRACE_STBITS,
4982 "Drive state check DONE callback=%d",callback_flag);
4983
4984 return callback_flag;
4985}
4986
4987
4988/* Cause kernel thread to check / update driver state */
4989static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4990{
4991 if (hdw->state_stale) return;
4992 hdw->state_stale = !0;
4993 trace_stbit("state_stale",hdw->state_stale);
4994 queue_work(hdw->workqueue,&hdw->workpoll);
4995}
4996
4997
d855497e
MI		 4998int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4999{
5000 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
5001}
5002
5003
5004int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
5005{
5006 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
5007}
5008
5009
5010int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
5011{
5012 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
5013}
5014
5015
5016int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
5017{
5018 u32 cval,nval;
5019 int ret;
5020 if (~msk) {
5021 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
5022 if (ret) return ret;
5023 nval = (cval & ~msk) | (val & msk);
5024 pvr2_trace(PVR2_TRACE_GPIO,
5025 "GPIO direction changing 0x%x:0x%x"
5026 " from 0x%x to 0x%x",
5027 msk,val,cval,nval);
5028 } else {
5029 nval = val;
5030 pvr2_trace(PVR2_TRACE_GPIO,
5031 "GPIO direction changing to 0x%x",nval);
5032 }
5033 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5034}
5035
5036
5037int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5038{
5039 u32 cval,nval;
5040 int ret;
5041 if (~msk) {
5042 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5043 if (ret) return ret;
5044 nval = (cval & ~msk) | (val & msk);
5045 pvr2_trace(PVR2_TRACE_GPIO,
5046 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5047 msk,val,cval,nval);
5048 } else {
5049 nval = val;
5050 pvr2_trace(PVR2_TRACE_GPIO,
5051 "GPIO output changing to 0x%x",nval);
5052 }
5053 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5054}
5055
5056
a51f5000
MI		 5057void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5058{
40f07111
MI		 5059 struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5060 memset(vtp, 0, sizeof(*vtp));
50e9efd6
HV		 5061 vtp->type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
5062 V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
2641df36 5063 hdw->tuner_signal_stale = 0;
40f07111
MI		 5064 /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5065 using v4l2-subdev - therefore we can't support that AT ALL right
5066 now. (Of course, no sub-drivers seem to implement it either.
5067 But now it's a a chicken and egg problem...) */
4cfe3319 5068 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner, vtp);
2641df36 5069 pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
40f07111
MI		 5070 " type=%u strength=%u audio=0x%x cap=0x%x"
5071 " low=%u hi=%u",
5072 vtp->type,
5073 vtp->signal, vtp->rxsubchans, vtp->capability,
5074 vtp->rangelow, vtp->rangehigh);
2641df36
MI		 5075
5076 /* We have to do this to avoid getting into constant polling if
5077 there's nobody to answer a poll of cropcap info. */
5078 hdw->cropcap_stale = 0;
a51f5000
MI		 5079}
5080
5081
7fb20fa3
MI		 5082unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5083{
5084 return hdw->input_avail_mask;
5085}
5086
5087
1cb03b76
MI		 5088unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5089{
5090 return hdw->input_allowed_mask;
5091}
5092
5093
5094static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5095{
5096 if (hdw->input_val != v) {
5097 hdw->input_val = v;
5098 hdw->input_dirty = !0;
5099 }
5100
5101 /* Handle side effects - if we switch to a mode that needs the RF
5102 tuner, then select the right frequency choice as well and mark
5103 it dirty. */
5104 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5105 hdw->freqSelector = 0;
5106 hdw->freqDirty = !0;
5107 } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5108 (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5109 hdw->freqSelector = 1;
5110 hdw->freqDirty = !0;
5111 }
5112 return 0;
5113}
5114
5115
5116int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5117 unsigned int change_mask,
5118 unsigned int change_val)
5119{
5120 int ret = 0;
5121 unsigned int nv,m,idx;
5122 LOCK_TAKE(hdw->big_lock);
5123 do {
5124 nv = hdw->input_allowed_mask & ~change_mask;
5125 nv |= (change_val & change_mask);
5126 nv &= hdw->input_avail_mask;
5127 if (!nv) {
5128 /* No legal modes left; return error instead. */
5129 ret = -EPERM;
5130 break;
5131 }
5132 hdw->input_allowed_mask = nv;
5133 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5134 /* Current mode is still in the allowed mask, so
5135 we're done. */
5136 break;
5137 }
5138 /* Select and switch to a mode that is still in the allowed
5139 mask */
5140 if (!hdw->input_allowed_mask) {
5141 /* Nothing legal; give up */
5142 break;
5143 }
5144 m = hdw->input_allowed_mask;
5145 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5146 if (!((1 << idx) & m)) continue;
5147 pvr2_hdw_set_input(hdw,idx);
5148 break;
5149 }
5150 } while (0);
5151 LOCK_GIVE(hdw->big_lock);
5152 return ret;
5153}
5154
5155
e61b6fc5 5156/* Find I2C address of eeprom */
07e337ee 5157static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
d855497e
MI		 5158{
5159 int result;
5160 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 5161 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 5162 result = pvr2_send_request(hdw,
5163 hdw->cmd_buffer,1,
5164 hdw->cmd_buffer,1);
5165 if (result < 0) break;
5166 result = hdw->cmd_buffer[0];
5167 } while(0); LOCK_GIVE(hdw->ctl_lock);
5168 return result;
5169}
Ubuntu Artful kernel mirror