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1c1e45d1 HV |
1 | /* |
2 | * cx18 ADEC firmware functions | |
3 | * | |
4 | * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> | |
1ed9dcc8 | 5 | * Copyright (C) 2008 Andy Walls <awalls@radix.net> |
1c1e45d1 HV |
6 | * |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version 2 | |
10 | * of the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
20 | * 02110-1301, USA. | |
21 | */ | |
22 | ||
23 | #include "cx18-driver.h" | |
b1526421 | 24 | #include "cx18-io.h" |
1c1e45d1 HV |
25 | #include <linux/firmware.h> |
26 | ||
81cb727d | 27 | #define CX18_AUDIO_ENABLE 0xc72014 |
1c1e45d1 HV |
28 | #define FWFILE "v4l-cx23418-dig.fw" |
29 | ||
30 | int cx18_av_loadfw(struct cx18 *cx) | |
31 | { | |
6246d4e1 | 32 | struct v4l2_subdev *sd = &cx->av_state.sd; |
1c1e45d1 HV |
33 | const struct firmware *fw = NULL; |
34 | u32 size; | |
35 | u32 v; | |
9b8a3e4c | 36 | const u8 *ptr; |
1c1e45d1 | 37 | int i; |
c6eb8eaf | 38 | int retries1 = 0; |
1c1e45d1 | 39 | |
3d05913d | 40 | if (request_firmware(&fw, FWFILE, &cx->pci_dev->dev) != 0) { |
6246d4e1 | 41 | CX18_ERR_DEV(sd, "unable to open firmware %s\n", FWFILE); |
1c1e45d1 HV |
42 | return -EINVAL; |
43 | } | |
44 | ||
f313da11 HV |
45 | /* The firmware load often has byte errors, so allow for several |
46 | retries, both at byte level and at the firmware load level. */ | |
c6eb8eaf | 47 | while (retries1 < 5) { |
ced07371 AW |
48 | cx18_av_write4_expect(cx, CXADEC_CHIP_CTRL, 0x00010000, |
49 | 0x00008430, 0xffffffff); /* cx25843 */ | |
50 | cx18_av_write_expect(cx, CXADEC_STD_DET_CTL, 0xf6, 0xf6, 0xff); | |
1c1e45d1 | 51 | |
ced07371 AW |
52 | /* Reset the Mako core, Register is alias of CXADEC_CHIP_CTRL */ |
53 | cx18_av_write4_expect(cx, 0x8100, 0x00010000, | |
54 | 0x00008430, 0xffffffff); /* cx25843 */ | |
1c1e45d1 | 55 | |
f313da11 | 56 | /* Put the 8051 in reset and enable firmware upload */ |
d267d851 | 57 | cx18_av_write4_noretry(cx, CXADEC_DL_CTL, 0x0F000000); |
1c1e45d1 | 58 | |
f313da11 HV |
59 | ptr = fw->data; |
60 | size = fw->size; | |
1c1e45d1 | 61 | |
f313da11 HV |
62 | for (i = 0; i < size; i++) { |
63 | u32 dl_control = 0x0F000000 | i | ((u32)ptr[i] << 16); | |
64 | u32 value = 0; | |
c6eb8eaf | 65 | int retries2; |
d267d851 | 66 | int unrec_err = 0; |
1c1e45d1 | 67 | |
f7823f8f | 68 | for (retries2 = 0; retries2 < CX18_MAX_MMIO_WR_RETRIES; |
d267d851 AW |
69 | retries2++) { |
70 | cx18_av_write4_noretry(cx, CXADEC_DL_CTL, | |
71 | dl_control); | |
f313da11 | 72 | udelay(10); |
3f75c616 | 73 | value = cx18_av_read4(cx, CXADEC_DL_CTL); |
f313da11 HV |
74 | if (value == dl_control) |
75 | break; | |
76 | /* Check if we can correct the byte by changing | |
77 | the address. We can only write the lower | |
78 | address byte of the address. */ | |
79 | if ((value & 0x3F00) != (dl_control & 0x3F00)) { | |
d267d851 | 80 | unrec_err = 1; |
f313da11 HV |
81 | break; |
82 | } | |
83 | } | |
f7823f8f | 84 | if (unrec_err || retries2 >= CX18_MAX_MMIO_WR_RETRIES) |
1c1e45d1 HV |
85 | break; |
86 | } | |
f313da11 HV |
87 | if (i == size) |
88 | break; | |
c6eb8eaf | 89 | retries1++; |
f313da11 | 90 | } |
c6eb8eaf | 91 | if (retries1 >= 5) { |
6246d4e1 | 92 | CX18_ERR_DEV(sd, "unable to load firmware %s\n", FWFILE); |
f313da11 HV |
93 | release_firmware(fw); |
94 | return -EIO; | |
1c1e45d1 HV |
95 | } |
96 | ||
ced07371 AW |
97 | cx18_av_write4_expect(cx, CXADEC_DL_CTL, |
98 | 0x13000000 | fw->size, 0x13000000, 0x13000000); | |
1c1e45d1 HV |
99 | |
100 | /* Output to the 416 */ | |
101 | cx18_av_and_or4(cx, CXADEC_PIN_CTRL1, ~0, 0x78000); | |
102 | ||
103 | /* Audio input control 1 set to Sony mode */ | |
104 | /* Audio output input 2 is 0 for slave operation input */ | |
105 | /* 0xC4000914[5]: 0 = left sample on WS=0, 1 = left sample on WS=1 */ | |
106 | /* 0xC4000914[7]: 0 = Philips mode, 1 = Sony mode (1st SCK rising edge | |
107 | after WS transition for first bit of audio word. */ | |
108 | cx18_av_write4(cx, CXADEC_I2S_IN_CTL, 0x000000A0); | |
109 | ||
110 | /* Audio output control 1 is set to Sony mode */ | |
111 | /* Audio output control 2 is set to 1 for master mode */ | |
112 | /* 0xC4000918[5]: 0 = left sample on WS=0, 1 = left sample on WS=1 */ | |
113 | /* 0xC4000918[7]: 0 = Philips mode, 1 = Sony mode (1st SCK rising edge | |
114 | after WS transition for first bit of audio word. */ | |
115 | /* 0xC4000918[8]: 0 = slave operation, 1 = master (SCK_OUT and WS_OUT | |
116 | are generated) */ | |
117 | cx18_av_write4(cx, CXADEC_I2S_OUT_CTL, 0x000001A0); | |
118 | ||
903bfeac | 119 | /* set alt I2s master clock to /0x16 and enable alt divider i2s |
1c1e45d1 | 120 | passthrough */ |
903bfeac | 121 | cx18_av_write4(cx, CXADEC_PIN_CFG3, 0x5600B687); |
1c1e45d1 | 122 | |
ced07371 AW |
123 | cx18_av_write4_expect(cx, CXADEC_STD_DET_CTL, 0x000000F6, 0x000000F6, |
124 | 0x3F00FFFF); | |
1c1e45d1 HV |
125 | /* CxDevWrReg(CXADEC_STD_DET_CTL, 0x000000FF); */ |
126 | ||
127 | /* Set bit 0 in register 0x9CC to signify that this is MiniMe. */ | |
128 | /* Register 0x09CC is defined by the Merlin firmware, and doesn't | |
129 | have a name in the spec. */ | |
130 | cx18_av_write4(cx, 0x09CC, 1); | |
131 | ||
b1526421 AW |
132 | v = cx18_read_reg(cx, CX18_AUDIO_ENABLE); |
133 | /* If bit 11 is 1, clear bit 10 */ | |
1c1e45d1 | 134 | if (v & 0x800) |
072e6183 AW |
135 | cx18_write_reg_expect(cx, v & 0xFFFFFBFF, CX18_AUDIO_ENABLE, |
136 | 0, 0x400); | |
1c1e45d1 HV |
137 | |
138 | /* Enable WW auto audio standard detection */ | |
139 | v = cx18_av_read4(cx, CXADEC_STD_DET_CTL); | |
140 | v |= 0xFF; /* Auto by default */ | |
141 | v |= 0x400; /* Stereo by default */ | |
142 | v |= 0x14000000; | |
ced07371 | 143 | cx18_av_write4_expect(cx, CXADEC_STD_DET_CTL, v, v, 0x3F00FFFF); |
1c1e45d1 HV |
144 | |
145 | release_firmware(fw); | |
146 | ||
6246d4e1 | 147 | CX18_INFO_DEV(sd, "loaded %s firmware (%d bytes)\n", FWFILE, size); |
1c1e45d1 HV |
148 | return 0; |
149 | } |