projects / mirror_ubuntu-zesty-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| e0d3bafd | 1 | /* |
| cde4362f MCC |
2 | cx231xx_avcore.c - driver for Conexant Cx23100/101/102 |
| 3 | USB video capture devices | |
| e0d3bafd SD |
4 | |
| 5 | Copyright (C) 2008 <srinivasa.deevi at conexant dot com> | |
| 6 | ||
| 7 | This program contains the specific code to control the avdecoder chip and | |
| 8 | other related usb control functions for cx231xx based chipset. | |
| 9 | ||
| 10 | This program is free software; you can redistribute it and/or modify | |
| 11 | it under the terms of the GNU General Public License as published by | |
| 12 | the Free Software Foundation; either version 2 of the License, or | |
| 13 | (at your option) any later version. | |
| 14 | ||
| 15 | This program is distributed in the hope that it will be useful, | |
| 16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 18 | GNU General Public License for more details. | |
| 19 | ||
| 20 | You should have received a copy of the GNU General Public License | |
| 21 | along with this program; if not, write to the Free Software | |
| 22 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
| 23 | */ | |
| 24 | ||
| 25 | #include <linux/init.h> | |
| 26 | #include <linux/list.h> | |
| 27 | #include <linux/module.h> | |
| 28 | #include <linux/kernel.h> | |
| 29 | #include <linux/bitmap.h> | |
| 30 | #include <linux/usb.h> | |
| 31 | #include <linux/i2c.h> | |
| e0d3bafd SD |
32 | #include <linux/mm.h> |
| 33 | #include <linux/mutex.h> | |
| 64fbf444 | 34 | #include <media/tuner.h> |
| e0d3bafd SD |
35 | |
| 36 | #include <media/v4l2-common.h> | |
| 37 | #include <media/v4l2-ioctl.h> | |
| 38 | #include <media/v4l2-chip-ident.h> | |
| 39 | ||
| 40 | #include "cx231xx.h" | |
| 64fbf444 | 41 | #include "cx231xx-dif.h" |
| e0d3bafd | 42 | |
| 64fbf444 | 43 | #define TUNER_MODE_FM_RADIO 0 |
| cde4362f | 44 | /****************************************************************************** |
| ecc67d10 SD |
45 | -: BLOCK ARRANGEMENT :- |
| 46 | I2S block ----------------------| | |
| 47 | [I2S audio] | | |
| 48 | | | |
| 49 | Analog Front End --> Direct IF -|-> Cx25840 --> Audio | |
| 50 | [video & audio] | [Audio] | |
| 51 | | | |
| 52 | |-> Cx25840 --> Video | |
| 53 | [Video] | |
| 54 | ||
| 55 | *******************************************************************************/ | |
| 64fbf444 PB |
56 | /****************************************************************************** |
| 57 | * VERVE REGISTER * | |
| 955e6ed8 | 58 | * * |
| 64fbf444 PB |
59 | ******************************************************************************/ |
| 60 | static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data) | |
| 61 | { | |
| 62 | return cx231xx_write_i2c_data(dev, VERVE_I2C_ADDRESS, | |
| 63 | saddr, 1, data, 1); | |
| 64 | } | |
| 65 | ||
| 66 | static int verve_read_byte(struct cx231xx *dev, u8 saddr, u8 *data) | |
| 67 | { | |
| 68 | int status; | |
| 69 | u32 temp = 0; | |
| 70 | ||
| 71 | status = cx231xx_read_i2c_data(dev, VERVE_I2C_ADDRESS, | |
| 72 | saddr, 1, &temp, 1); | |
| 73 | *data = (u8) temp; | |
| 74 | return status; | |
| 75 | } | |
| 76 | void initGPIO(struct cx231xx *dev) | |
| 77 | { | |
| 78 | u32 _gpio_direction = 0; | |
| 79 | u32 value = 0; | |
| 80 | u8 val = 0; | |
| 81 | ||
| 82 | _gpio_direction = _gpio_direction & 0xFC0003FF; | |
| 83 | _gpio_direction = _gpio_direction | 0x03FDFC00; | |
| 84 | cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0); | |
| 85 | ||
| 86 | verve_read_byte(dev, 0x07, &val); | |
| 87 | cx231xx_info(" verve_read_byte address0x07=0x%x\n", val); | |
| 88 | verve_write_byte(dev, 0x07, 0xF4); | |
| 89 | verve_read_byte(dev, 0x07, &val); | |
| 90 | cx231xx_info(" verve_read_byte address0x07=0x%x\n", val); | |
| 91 | ||
| 92 | cx231xx_capture_start(dev, 1, 2); | |
| 93 | ||
| 94 | cx231xx_mode_register(dev, EP_MODE_SET, 0x0500FE00); | |
| 95 | cx231xx_mode_register(dev, GBULK_BIT_EN, 0xFFFDFFFF); | |
| 96 | ||
| 97 | } | |
| 98 | void uninitGPIO(struct cx231xx *dev) | |
| 99 | { | |
| 100 | u8 value[4] = { 0, 0, 0, 0 }; | |
| 101 | ||
| 102 | cx231xx_capture_start(dev, 0, 2); | |
| 103 | verve_write_byte(dev, 0x07, 0x14); | |
| 104 | cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, | |
| 105 | 0x68, value, 4); | |
| 106 | } | |
| ecc67d10 SD |
107 | |
| 108 | /****************************************************************************** | |
| 109 | * A F E - B L O C K C O N T R O L functions * | |
| 110 | * [ANALOG FRONT END] * | |
| 6e4f574b | 111 | ******************************************************************************/ |
| ecc67d10 SD |
112 | static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data) |
| 113 | { | |
| 114 | return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS, | |
| 115 | saddr, 2, data, 1); | |
| 116 | } | |
| 117 | ||
| 118 | static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data) | |
| 119 | { | |
| 120 | int status; | |
| 121 | u32 temp = 0; | |
| 122 | ||
| 123 | status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS, | |
| 124 | saddr, 2, &temp, 1); | |
| 125 | *data = (u8) temp; | |
| 126 | return status; | |
| 127 | } | |
| 128 | ||
| 129 | int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count) | |
| e0d3bafd | 130 | { |
| 84b5dbf3 MCC |
131 | int status = 0; |
| 132 | u8 temp = 0; | |
| ecc67d10 | 133 | u8 afe_power_status = 0; |
| 84b5dbf3 MCC |
134 | int i = 0; |
| 135 | ||
| 136 | /* super block initialize */ | |
| 137 | temp = (u8) (ref_count & 0xff); | |
| ecc67d10 | 138 | status = afe_write_byte(dev, SUP_BLK_TUNE2, temp); |
| 6e4f574b SD |
139 | if (status < 0) |
| 140 | return status; | |
| 84b5dbf3 | 141 | |
| ecc67d10 | 142 | status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status); |
| 6e4f574b SD |
143 | if (status < 0) |
| 144 | return status; | |
| 84b5dbf3 MCC |
145 | |
| 146 | temp = (u8) ((ref_count & 0x300) >> 8); | |
| 147 | temp |= 0x40; | |
| ecc67d10 | 148 | status = afe_write_byte(dev, SUP_BLK_TUNE1, temp); |
| 6e4f574b SD |
149 | if (status < 0) |
| 150 | return status; | |
| 151 | ||
| ecc67d10 | 152 | status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f); |
| 6e4f574b SD |
153 | if (status < 0) |
| 154 | return status; | |
| 84b5dbf3 MCC |
155 | |
| 156 | /* enable pll */ | |
| ecc67d10 SD |
157 | while (afe_power_status != 0x18) { |
| 158 | status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18); | |
| 6e4f574b SD |
159 | if (status < 0) { |
| 160 | cx231xx_info( | |
| 161 | ": Init Super Block failed in send cmd\n"); | |
| 162 | break; | |
| 163 | } | |
| 164 | ||
| ecc67d10 SD |
165 | status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status); |
| 166 | afe_power_status &= 0xff; | |
| 84b5dbf3 | 167 | if (status < 0) { |
| b9255176 | 168 | cx231xx_info( |
| 6e4f574b | 169 | ": Init Super Block failed in receive cmd\n"); |
| 84b5dbf3 MCC |
170 | break; |
| 171 | } | |
| 172 | i++; | |
| 173 | if (i == 10) { | |
| b9255176 SD |
174 | cx231xx_info( |
| 175 | ": Init Super Block force break in loop !!!!\n"); | |
| 84b5dbf3 MCC |
176 | status = -1; |
| 177 | break; | |
| 178 | } | |
| 179 | } | |
| 180 | ||
| 181 | if (status < 0) | |
| 182 | return status; | |
| 183 | ||
| 184 | /* start tuning filter */ | |
| ecc67d10 | 185 | status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40); |
| 6e4f574b SD |
186 | if (status < 0) |
| 187 | return status; | |
| 188 | ||
| 84b5dbf3 MCC |
189 | msleep(5); |
| 190 | ||
| 191 | /* exit tuning */ | |
| ecc67d10 | 192 | status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00); |
| 84b5dbf3 MCC |
193 | |
| 194 | return status; | |
| e0d3bafd SD |
195 | } |
| 196 | ||
| ecc67d10 | 197 | int cx231xx_afe_init_channels(struct cx231xx *dev) |
| e0d3bafd | 198 | { |
| 84b5dbf3 MCC |
199 | int status = 0; |
| 200 | ||
| 201 | /* power up all 3 channels, clear pd_buffer */ | |
| ecc67d10 SD |
202 | status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00); |
| 203 | status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00); | |
| 204 | status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00); | |
| 84b5dbf3 MCC |
205 | |
| 206 | /* Enable quantizer calibration */ | |
| ecc67d10 | 207 | status = afe_write_byte(dev, ADC_COM_QUANT, 0x02); |
| 84b5dbf3 MCC |
208 | |
| 209 | /* channel initialize, force modulator (fb) reset */ | |
| ecc67d10 SD |
210 | status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17); |
| 211 | status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17); | |
| 212 | status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17); | |
| 84b5dbf3 MCC |
213 | |
| 214 | /* start quantilizer calibration */ | |
| ecc67d10 SD |
215 | status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10); |
| 216 | status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10); | |
| 217 | status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10); | |
| 84b5dbf3 MCC |
218 | msleep(5); |
| 219 | ||
| 220 | /* exit modulator (fb) reset */ | |
| ecc67d10 SD |
221 | status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07); |
| 222 | status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07); | |
| 223 | status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07); | |
| 84b5dbf3 MCC |
224 | |
| 225 | /* enable the pre_clamp in each channel for single-ended input */ | |
| ecc67d10 SD |
226 | status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0); |
| 227 | status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0); | |
| 228 | status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0); | |
| 84b5dbf3 MCC |
229 | |
| 230 | /* use diode instead of resistor, so set term_en to 0, res_en to 0 */ | |
| ecc67d10 | 231 | status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, |
| 84b5dbf3 | 232 | ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00); |
| ecc67d10 | 233 | status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, |
| 84b5dbf3 | 234 | ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00); |
| ecc67d10 | 235 | status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, |
| 84b5dbf3 MCC |
236 | ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00); |
| 237 | ||
| 238 | /* dynamic element matching off */ | |
| ecc67d10 SD |
239 | status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03); |
| 240 | status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03); | |
| 241 | status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03); | |
| 84b5dbf3 MCC |
242 | |
| 243 | return status; | |
| e0d3bafd SD |
244 | } |
| 245 | ||
| ecc67d10 | 246 | int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev) |
| e0d3bafd | 247 | { |
| ecc67d10 | 248 | u8 c_value = 0; |
| 84b5dbf3 | 249 | int status = 0; |
| e0d3bafd | 250 | |
| ecc67d10 | 251 | status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value); |
| 84b5dbf3 | 252 | c_value &= (~(0x50)); |
| ecc67d10 | 253 | status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value); |
| e0d3bafd | 254 | |
| 84b5dbf3 | 255 | return status; |
| e0d3bafd SD |
256 | } |
| 257 | ||
| 258 | /* | |
| 6e4f574b SD |
259 | The Analog Front End in Cx231xx has 3 channels. These |
| 260 | channels are used to share between different inputs | |
| 261 | like tuner, s-video and composite inputs. | |
| 262 | ||
| e0d3bafd SD |
263 | channel 1 ----- pin 1 to pin4(in reg is 1-4) |
| 264 | channel 2 ----- pin 5 to pin8(in reg is 5-8) | |
| 265 | channel 3 ----- pin 9 to pin 12(in reg is 9-11) | |
| 266 | */ | |
| ecc67d10 | 267 | int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux) |
| e0d3bafd | 268 | { |
| 84b5dbf3 MCC |
269 | u8 ch1_setting = (u8) input_mux; |
| 270 | u8 ch2_setting = (u8) (input_mux >> 8); | |
| 271 | u8 ch3_setting = (u8) (input_mux >> 16); | |
| 272 | int status = 0; | |
| ecc67d10 | 273 | u8 value = 0; |
| 84b5dbf3 MCC |
274 | |
| 275 | if (ch1_setting != 0) { | |
| ecc67d10 | 276 | status = afe_read_byte(dev, ADC_INPUT_CH1, &value); |
| 5f63306d | 277 | value &= ~INPUT_SEL_MASK; |
| 84b5dbf3 MCC |
278 | value |= (ch1_setting - 1) << 4; |
| 279 | value &= 0xff; | |
| ecc67d10 | 280 | status = afe_write_byte(dev, ADC_INPUT_CH1, value); |
| 84b5dbf3 MCC |
281 | } |
| 282 | ||
| 283 | if (ch2_setting != 0) { | |
| ecc67d10 | 284 | status = afe_read_byte(dev, ADC_INPUT_CH2, &value); |
| 5f63306d | 285 | value &= ~INPUT_SEL_MASK; |
| 84b5dbf3 MCC |
286 | value |= (ch2_setting - 1) << 4; |
| 287 | value &= 0xff; | |
| ecc67d10 | 288 | status = afe_write_byte(dev, ADC_INPUT_CH2, value); |
| 84b5dbf3 MCC |
289 | } |
| 290 | ||
| cde4362f MCC |
291 | /* For ch3_setting, the value to put in the register is |
| 292 | 7 less than the input number */ | |
| 84b5dbf3 | 293 | if (ch3_setting != 0) { |
| ecc67d10 | 294 | status = afe_read_byte(dev, ADC_INPUT_CH3, &value); |
| 5f63306d | 295 | value &= ~INPUT_SEL_MASK; |
| 84b5dbf3 MCC |
296 | value |= (ch3_setting - 1) << 4; |
| 297 | value &= 0xff; | |
| ecc67d10 | 298 | status = afe_write_byte(dev, ADC_INPUT_CH3, value); |
| 84b5dbf3 MCC |
299 | } |
| 300 | ||
| 301 | return status; | |
| e0d3bafd SD |
302 | } |
| 303 | ||
| ecc67d10 | 304 | int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode) |
| e0d3bafd | 305 | { |
| 84b5dbf3 MCC |
306 | int status = 0; |
| 307 | ||
| 6e4f574b SD |
308 | /* |
| 309 | * FIXME: We need to implement the AFE code for LOW IF and for HI IF. | |
| 310 | * Currently, only baseband works. | |
| 311 | */ | |
| 312 | ||
| 84b5dbf3 MCC |
313 | switch (mode) { |
| 314 | case AFE_MODE_LOW_IF: | |
| 64fbf444 | 315 | cx231xx_Setup_AFE_for_LowIF(dev); |
| 84b5dbf3 MCC |
316 | break; |
| 317 | case AFE_MODE_BASEBAND: | |
| ecc67d10 | 318 | status = cx231xx_afe_setup_AFE_for_baseband(dev); |
| 84b5dbf3 MCC |
319 | break; |
| 320 | case AFE_MODE_EU_HI_IF: | |
| 321 | /* SetupAFEforEuHiIF(); */ | |
| 322 | break; | |
| 323 | case AFE_MODE_US_HI_IF: | |
| 324 | /* SetupAFEforUsHiIF(); */ | |
| 325 | break; | |
| 326 | case AFE_MODE_JAPAN_HI_IF: | |
| 327 | /* SetupAFEforJapanHiIF(); */ | |
| 328 | break; | |
| 329 | } | |
| 330 | ||
| ecc67d10 | 331 | if ((mode != dev->afe_mode) && |
| b9255176 | 332 | (dev->video_input == CX231XX_VMUX_TELEVISION)) |
| ecc67d10 | 333 | status = cx231xx_afe_adjust_ref_count(dev, |
| 84b5dbf3 | 334 | CX231XX_VMUX_TELEVISION); |
| 84b5dbf3 | 335 | |
| ecc67d10 | 336 | dev->afe_mode = mode; |
| 84b5dbf3 MCC |
337 | |
| 338 | return status; | |
| e0d3bafd SD |
339 | } |
| 340 | ||
| ecc67d10 | 341 | int cx231xx_afe_update_power_control(struct cx231xx *dev, |
| 6e4f574b | 342 | enum AV_MODE avmode) |
| e0d3bafd | 343 | { |
| ecc67d10 | 344 | u8 afe_power_status = 0; |
| 84b5dbf3 MCC |
345 | int status = 0; |
| 346 | ||
| 347 | switch (dev->model) { | |
| 64fbf444 | 348 | case CX231XX_BOARD_CNXT_CARRAERA: |
| 84b5dbf3 | 349 | case CX231XX_BOARD_CNXT_RDE_250: |
| 64fbf444 | 350 | case CX231XX_BOARD_CNXT_SHELBY: |
| 84b5dbf3 | 351 | case CX231XX_BOARD_CNXT_RDU_250: |
| 64fbf444 PB |
352 | case CX231XX_BOARD_CNXT_RDE_253S: |
| 353 | case CX231XX_BOARD_CNXT_RDU_253S: | |
| 354 | case CX231XX_BOARD_CNXT_VIDEO_GRABBER: | |
| 1a50fdde | 355 | case CX231XX_BOARD_HAUPPAUGE_EXETER: |
| 4270c3ca | 356 | case CX231XX_BOARD_HAUPPAUGE_USBLIVE2: |
| 9417bc6d | 357 | case CX231XX_BOARD_PV_PLAYTV_USB_HYBRID: |
| 84b5dbf3 | 358 | if (avmode == POLARIS_AVMODE_ANALOGT_TV) { |
| ecc67d10 | 359 | while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | |
| 6e4f574b | 360 | FLD_PWRDN_ENABLE_PLL)) { |
| ecc67d10 | 361 | status = afe_write_byte(dev, SUP_BLK_PWRDN, |
| 6e4f574b | 362 | FLD_PWRDN_TUNING_BIAS | |
| ecc67d10 SD |
363 | FLD_PWRDN_ENABLE_PLL); |
| 364 | status |= afe_read_byte(dev, SUP_BLK_PWRDN, | |
| 365 | &afe_power_status); | |
| 84b5dbf3 MCC |
366 | if (status < 0) |
| 367 | break; | |
| 368 | } | |
| 369 | ||
| ecc67d10 SD |
370 | status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, |
| 371 | 0x00); | |
| 372 | status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, | |
| 373 | 0x00); | |
| 374 | status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, | |
| 375 | 0x00); | |
| 84b5dbf3 | 376 | } else if (avmode == POLARIS_AVMODE_DIGITAL) { |
| ecc67d10 SD |
377 | status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, |
| 378 | 0x70); | |
| 379 | status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, | |
| 380 | 0x70); | |
| 381 | status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, | |
| 382 | 0x70); | |
| 383 | ||
| 384 | status |= afe_read_byte(dev, SUP_BLK_PWRDN, | |
| 385 | &afe_power_status); | |
| 386 | afe_power_status |= FLD_PWRDN_PD_BANDGAP | | |
| 6e4f574b SD |
387 | FLD_PWRDN_PD_BIAS | |
| 388 | FLD_PWRDN_PD_TUNECK; | |
| ecc67d10 SD |
389 | status |= afe_write_byte(dev, SUP_BLK_PWRDN, |
| 390 | afe_power_status); | |
| 84b5dbf3 | 391 | } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { |
| ecc67d10 | 392 | while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | |
| 6e4f574b | 393 | FLD_PWRDN_ENABLE_PLL)) { |
| ecc67d10 | 394 | status = afe_write_byte(dev, SUP_BLK_PWRDN, |
| 6e4f574b | 395 | FLD_PWRDN_TUNING_BIAS | |
| ecc67d10 SD |
396 | FLD_PWRDN_ENABLE_PLL); |
| 397 | status |= afe_read_byte(dev, SUP_BLK_PWRDN, | |
| 398 | &afe_power_status); | |
| 84b5dbf3 MCC |
399 | if (status < 0) |
| 400 | break; | |
| 401 | } | |
| 402 | ||
| ecc67d10 SD |
403 | status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, |
| 404 | 0x00); | |
| 405 | status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, | |
| 406 | 0x00); | |
| 407 | status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, | |
| 408 | 0x00); | |
| 84b5dbf3 MCC |
409 | } else { |
| 410 | cx231xx_info("Invalid AV mode input\n"); | |
| 411 | status = -1; | |
| 412 | } | |
| 413 | break; | |
| 414 | default: | |
| 415 | if (avmode == POLARIS_AVMODE_ANALOGT_TV) { | |
| ecc67d10 | 416 | while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | |
| 6e4f574b | 417 | FLD_PWRDN_ENABLE_PLL)) { |
| ecc67d10 | 418 | status = afe_write_byte(dev, SUP_BLK_PWRDN, |
| 6e4f574b | 419 | FLD_PWRDN_TUNING_BIAS | |
| ecc67d10 SD |
420 | FLD_PWRDN_ENABLE_PLL); |
| 421 | status |= afe_read_byte(dev, SUP_BLK_PWRDN, | |
| 422 | &afe_power_status); | |
| 84b5dbf3 MCC |
423 | if (status < 0) |
| 424 | break; | |
| 425 | } | |
| 426 | ||
| ecc67d10 SD |
427 | status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, |
| 428 | 0x40); | |
| 429 | status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, | |
| 430 | 0x40); | |
| 431 | status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, | |
| 432 | 0x00); | |
| 84b5dbf3 | 433 | } else if (avmode == POLARIS_AVMODE_DIGITAL) { |
| ecc67d10 SD |
434 | status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, |
| 435 | 0x70); | |
| 436 | status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, | |
| 437 | 0x70); | |
| 438 | status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, | |
| 439 | 0x70); | |
| 440 | ||
| 441 | status |= afe_read_byte(dev, SUP_BLK_PWRDN, | |
| 442 | &afe_power_status); | |
| 443 | afe_power_status |= FLD_PWRDN_PD_BANDGAP | | |
| 6e4f574b SD |
444 | FLD_PWRDN_PD_BIAS | |
| 445 | FLD_PWRDN_PD_TUNECK; | |
| ecc67d10 SD |
446 | status |= afe_write_byte(dev, SUP_BLK_PWRDN, |
| 447 | afe_power_status); | |
| 84b5dbf3 | 448 | } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { |
| ecc67d10 | 449 | while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | |
| 6e4f574b | 450 | FLD_PWRDN_ENABLE_PLL)) { |
| ecc67d10 | 451 | status = afe_write_byte(dev, SUP_BLK_PWRDN, |
| 6e4f574b | 452 | FLD_PWRDN_TUNING_BIAS | |
| ecc67d10 SD |
453 | FLD_PWRDN_ENABLE_PLL); |
| 454 | status |= afe_read_byte(dev, SUP_BLK_PWRDN, | |
| 455 | &afe_power_status); | |
| 84b5dbf3 MCC |
456 | if (status < 0) |
| 457 | break; | |
| 458 | } | |
| 459 | ||
| ecc67d10 SD |
460 | status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, |
| 461 | 0x00); | |
| 462 | status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, | |
| 463 | 0x00); | |
| 464 | status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, | |
| 465 | 0x40); | |
| 84b5dbf3 MCC |
466 | } else { |
| 467 | cx231xx_info("Invalid AV mode input\n"); | |
| 468 | status = -1; | |
| 469 | } | |
| 470 | } /* switch */ | |
| 471 | ||
| 472 | return status; | |
| e0d3bafd SD |
473 | } |
| 474 | ||
| ecc67d10 | 475 | int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input) |
| e0d3bafd | 476 | { |
| ecc67d10 SD |
477 | u8 input_mode = 0; |
| 478 | u8 ntf_mode = 0; | |
| 84b5dbf3 MCC |
479 | int status = 0; |
| 480 | ||
| 481 | dev->video_input = video_input; | |
| 482 | ||
| 483 | if (video_input == CX231XX_VMUX_TELEVISION) { | |
| ecc67d10 SD |
484 | status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode); |
| 485 | status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, | |
| 486 | &ntf_mode); | |
| 84b5dbf3 | 487 | } else { |
| ecc67d10 SD |
488 | status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode); |
| 489 | status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1, | |
| 490 | &ntf_mode); | |
| 84b5dbf3 | 491 | } |
| e0d3bafd | 492 | |
| 84b5dbf3 MCC |
493 | input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1); |
| 494 | ||
| 495 | switch (input_mode) { | |
| 496 | case SINGLE_ENDED: | |
| ecc67d10 | 497 | dev->afe_ref_count = 0x23C; |
| 84b5dbf3 MCC |
498 | break; |
| 499 | case LOW_IF: | |
| ecc67d10 | 500 | dev->afe_ref_count = 0x24C; |
| 84b5dbf3 MCC |
501 | break; |
| 502 | case EU_IF: | |
| ecc67d10 | 503 | dev->afe_ref_count = 0x258; |
| 84b5dbf3 MCC |
504 | break; |
| 505 | case US_IF: | |
| ecc67d10 | 506 | dev->afe_ref_count = 0x260; |
| 84b5dbf3 MCC |
507 | break; |
| 508 | default: | |
| 509 | break; | |
| 510 | } | |
| 511 | ||
| ecc67d10 | 512 | status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count); |
| e0d3bafd | 513 | |
| 84b5dbf3 MCC |
514 | return status; |
| 515 | } | |
| e0d3bafd | 516 | |
| cde4362f MCC |
517 | /****************************************************************************** |
| 518 | * V I D E O / A U D I O D E C O D E R C O N T R O L functions * | |
| 6e4f574b | 519 | ******************************************************************************/ |
| ecc67d10 SD |
520 | static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data) |
| 521 | { | |
| 522 | return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS, | |
| 523 | saddr, 2, data, 1); | |
| 524 | } | |
| 525 | ||
| 526 | static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data) | |
| 527 | { | |
| 528 | int status; | |
| 529 | u32 temp = 0; | |
| 530 | ||
| 531 | status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS, | |
| 532 | saddr, 2, &temp, 1); | |
| 533 | *data = (u8) temp; | |
| 534 | return status; | |
| 535 | } | |
| 536 | ||
| 537 | static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data) | |
| 538 | { | |
| 539 | return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS, | |
| 540 | saddr, 2, data, 4); | |
| 541 | } | |
| 542 | ||
| 543 | static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data) | |
| 544 | { | |
| 545 | return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS, | |
| 546 | saddr, 2, data, 4); | |
| 547 | } | |
| 64fbf444 PB |
548 | int cx231xx_check_fw(struct cx231xx *dev) |
| 549 | { | |
| 550 | u8 temp = 0; | |
| 551 | int status = 0; | |
| 552 | status = vid_blk_read_byte(dev, DL_CTL_ADDRESS_LOW, &temp); | |
| 553 | if (status < 0) | |
| 554 | return status; | |
| 555 | else | |
| 556 | return temp; | |
| 557 | ||
| 558 | } | |
| ecc67d10 | 559 | |
| e0d3bafd SD |
560 | int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input) |
| 561 | { | |
| 84b5dbf3 MCC |
562 | int status = 0; |
| 563 | ||
| 564 | switch (INPUT(input)->type) { | |
| 565 | case CX231XX_VMUX_COMPOSITE1: | |
| 566 | case CX231XX_VMUX_SVIDEO: | |
| 567 | if ((dev->current_pcb_config.type == USB_BUS_POWER) && | |
| 568 | (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) { | |
| cde4362f MCC |
569 | /* External AV */ |
| 570 | status = cx231xx_set_power_mode(dev, | |
| 571 | POLARIS_AVMODE_ENXTERNAL_AV); | |
| 84b5dbf3 | 572 | if (status < 0) { |
| b9255176 SD |
573 | cx231xx_errdev("%s: set_power_mode : Failed to" |
| 574 | " set Power - errCode [%d]!\n", | |
| 575 | __func__, status); | |
| 84b5dbf3 MCC |
576 | return status; |
| 577 | } | |
| 578 | } | |
| cde4362f MCC |
579 | status = cx231xx_set_decoder_video_input(dev, |
| 580 | INPUT(input)->type, | |
| 581 | INPUT(input)->vmux); | |
| 84b5dbf3 MCC |
582 | break; |
| 583 | case CX231XX_VMUX_TELEVISION: | |
| 584 | case CX231XX_VMUX_CABLE: | |
| 585 | if ((dev->current_pcb_config.type == USB_BUS_POWER) && | |
| 586 | (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) { | |
| cde4362f MCC |
587 | /* Tuner */ |
| 588 | status = cx231xx_set_power_mode(dev, | |
| 589 | POLARIS_AVMODE_ANALOGT_TV); | |
| 84b5dbf3 | 590 | if (status < 0) { |
| b9255176 SD |
591 | cx231xx_errdev("%s: set_power_mode:Failed" |
| 592 | " to set Power - errCode [%d]!\n", | |
| 593 | __func__, status); | |
| 84b5dbf3 MCC |
594 | return status; |
| 595 | } | |
| 596 | } | |
| 64fbf444 PB |
597 | if (dev->tuner_type == TUNER_NXP_TDA18271) |
| 598 | status = cx231xx_set_decoder_video_input(dev, | |
| 599 | CX231XX_VMUX_TELEVISION, | |
| 600 | INPUT(input)->vmux); | |
| 601 | else | |
| 602 | status = cx231xx_set_decoder_video_input(dev, | |
| cde4362f MCC |
603 | CX231XX_VMUX_COMPOSITE1, |
| 604 | INPUT(input)->vmux); | |
| 64fbf444 | 605 | |
| 84b5dbf3 MCC |
606 | break; |
| 607 | default: | |
| b9255176 | 608 | cx231xx_errdev("%s: set_power_mode : Unknown Input %d !\n", |
| 84b5dbf3 MCC |
609 | __func__, INPUT(input)->type); |
| 610 | break; | |
| 611 | } | |
| 612 | ||
| 613 | /* save the selection */ | |
| 614 | dev->video_input = input; | |
| 615 | ||
| 616 | return status; | |
| e0d3bafd SD |
617 | } |
| 618 | ||
| b9255176 SD |
619 | int cx231xx_set_decoder_video_input(struct cx231xx *dev, |
| 620 | u8 pin_type, u8 input) | |
| e0d3bafd | 621 | { |
| 84b5dbf3 MCC |
622 | int status = 0; |
| 623 | u32 value = 0; | |
| 624 | ||
| 625 | if (pin_type != dev->video_input) { | |
| ecc67d10 | 626 | status = cx231xx_afe_adjust_ref_count(dev, pin_type); |
| 84b5dbf3 | 627 | if (status < 0) { |
| b9255176 | 628 | cx231xx_errdev("%s: adjust_ref_count :Failed to set" |
| ecc67d10 | 629 | "AFE input mux - errCode [%d]!\n", |
| b9255176 | 630 | __func__, status); |
| 84b5dbf3 MCC |
631 | return status; |
| 632 | } | |
| 633 | } | |
| e0d3bafd | 634 | |
| ecc67d10 SD |
635 | /* call afe block to set video inputs */ |
| 636 | status = cx231xx_afe_set_input_mux(dev, input); | |
| 84b5dbf3 | 637 | if (status < 0) { |
| b9255176 | 638 | cx231xx_errdev("%s: set_input_mux :Failed to set" |
| ecc67d10 | 639 | " AFE input mux - errCode [%d]!\n", |
| b9255176 | 640 | __func__, status); |
| 84b5dbf3 MCC |
641 | return status; |
| 642 | } | |
| 643 | ||
| 644 | switch (pin_type) { | |
| 645 | case CX231XX_VMUX_COMPOSITE1: | |
| ecc67d10 | 646 | status = vid_blk_read_word(dev, AFE_CTRL, &value); |
| cde4362f MCC |
647 | value |= (0 << 13) | (1 << 4); |
| 648 | value &= ~(1 << 5); | |
| 649 | ||
| b9255176 SD |
650 | /* set [24:23] [22:15] to 0 */ |
| 651 | value &= (~(0x1ff8000)); | |
| 652 | /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ | |
| 653 | value |= 0x1000000; | |
| ecc67d10 | 654 | status = vid_blk_write_word(dev, AFE_CTRL, value); |
| cde4362f | 655 | |
| ecc67d10 | 656 | status = vid_blk_read_word(dev, OUT_CTRL1, &value); |
| cde4362f | 657 | value |= (1 << 7); |
| ecc67d10 | 658 | status = vid_blk_write_word(dev, OUT_CTRL1, value); |
| cde4362f | 659 | |
| 88806218 | 660 | /* Set output mode */ |
| cde4362f | 661 | status = cx231xx_read_modify_write_i2c_dword(dev, |
| ecc67d10 | 662 | VID_BLK_I2C_ADDRESS, |
| cde4362f MCC |
663 | OUT_CTRL1, |
| 664 | FLD_OUT_MODE, | |
| 88806218 | 665 | dev->board.output_mode); |
| cde4362f MCC |
666 | |
| 667 | /* Tell DIF object to go to baseband mode */ | |
| 668 | status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); | |
| 669 | if (status < 0) { | |
| b9255176 SD |
670 | cx231xx_errdev("%s: cx231xx_dif set to By pass" |
| 671 | " mode- errCode [%d]!\n", | |
| cde4362f MCC |
672 | __func__, status); |
| 673 | return status; | |
| 674 | } | |
| 675 | ||
| 676 | /* Read the DFE_CTRL1 register */ | |
| ecc67d10 | 677 | status = vid_blk_read_word(dev, DFE_CTRL1, &value); |
| cde4362f MCC |
678 | |
| 679 | /* enable the VBI_GATE_EN */ | |
| 680 | value |= FLD_VBI_GATE_EN; | |
| 681 | ||
| 682 | /* Enable the auto-VGA enable */ | |
| 683 | value |= FLD_VGA_AUTO_EN; | |
| 684 | ||
| 685 | /* Write it back */ | |
| ecc67d10 | 686 | status = vid_blk_write_word(dev, DFE_CTRL1, value); |
| cde4362f MCC |
687 | |
| 688 | /* Disable auto config of registers */ | |
| 689 | status = cx231xx_read_modify_write_i2c_dword(dev, | |
| ecc67d10 | 690 | VID_BLK_I2C_ADDRESS, |
| cde4362f MCC |
691 | MODE_CTRL, FLD_ACFG_DIS, |
| 692 | cx231xx_set_field(FLD_ACFG_DIS, 1)); | |
| 693 | ||
| 694 | /* Set CVBS input mode */ | |
| 695 | status = cx231xx_read_modify_write_i2c_dword(dev, | |
| ecc67d10 | 696 | VID_BLK_I2C_ADDRESS, |
| cde4362f MCC |
697 | MODE_CTRL, FLD_INPUT_MODE, |
| 698 | cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0)); | |
| 699 | break; | |
| 700 | case CX231XX_VMUX_SVIDEO: | |
| 701 | /* Disable the use of DIF */ | |
| 702 | ||
| ecc67d10 | 703 | status = vid_blk_read_word(dev, AFE_CTRL, &value); |
| cde4362f | 704 | |
| b9255176 SD |
705 | /* set [24:23] [22:15] to 0 */ |
| 706 | value &= (~(0x1ff8000)); | |
| 707 | /* set FUNC_MODE[24:23] = 2 | |
| 708 | IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */ | |
| 709 | value |= 0x1000010; | |
| ecc67d10 | 710 | status = vid_blk_write_word(dev, AFE_CTRL, value); |
| cde4362f MCC |
711 | |
| 712 | /* Tell DIF object to go to baseband mode */ | |
| 713 | status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); | |
| 714 | if (status < 0) { | |
| b9255176 SD |
715 | cx231xx_errdev("%s: cx231xx_dif set to By pass" |
| 716 | " mode- errCode [%d]!\n", | |
| cde4362f MCC |
717 | __func__, status); |
| 718 | return status; | |
| 719 | } | |
| 720 | ||
| 721 | /* Read the DFE_CTRL1 register */ | |
| ecc67d10 | 722 | status = vid_blk_read_word(dev, DFE_CTRL1, &value); |
| cde4362f MCC |
723 | |
| 724 | /* enable the VBI_GATE_EN */ | |
| 725 | value |= FLD_VBI_GATE_EN; | |
| 726 | ||
| 727 | /* Enable the auto-VGA enable */ | |
| 728 | value |= FLD_VGA_AUTO_EN; | |
| 729 | ||
| 730 | /* Write it back */ | |
| ecc67d10 | 731 | status = vid_blk_write_word(dev, DFE_CTRL1, value); |
| cde4362f MCC |
732 | |
| 733 | /* Disable auto config of registers */ | |
| 734 | status = cx231xx_read_modify_write_i2c_dword(dev, | |
| ecc67d10 | 735 | VID_BLK_I2C_ADDRESS, |
| cde4362f MCC |
736 | MODE_CTRL, FLD_ACFG_DIS, |
| 737 | cx231xx_set_field(FLD_ACFG_DIS, 1)); | |
| 738 | ||
| 739 | /* Set YC input mode */ | |
| 740 | status = cx231xx_read_modify_write_i2c_dword(dev, | |
| ecc67d10 | 741 | VID_BLK_I2C_ADDRESS, |
| cde4362f MCC |
742 | MODE_CTRL, |
| 743 | FLD_INPUT_MODE, | |
| 744 | cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1)); | |
| 745 | ||
| 746 | /* Chroma to ADC2 */ | |
| ecc67d10 | 747 | status = vid_blk_read_word(dev, AFE_CTRL, &value); |
| cde4362f MCC |
748 | value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */ |
| 749 | ||
| 750 | /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8) | |
| 751 | This sets them to use video | |
| 752 | rather than audio. Only one of the two will be in use. */ | |
| 753 | value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3); | |
| 754 | ||
| ecc67d10 | 755 | status = vid_blk_write_word(dev, AFE_CTRL, value); |
| cde4362f | 756 | |
| ecc67d10 | 757 | status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND); |
| cde4362f MCC |
758 | break; |
| 759 | case CX231XX_VMUX_TELEVISION: | |
| 760 | case CX231XX_VMUX_CABLE: | |
| 761 | default: | |
| 2f861387 MCC |
762 | /* TODO: Test if this is also needed for xc2028/xc3028 */ |
| 763 | if (dev->board.tuner_type == TUNER_XC5000) { | |
| cde4362f MCC |
764 | /* Disable the use of DIF */ |
| 765 | ||
| ecc67d10 | 766 | status = vid_blk_read_word(dev, AFE_CTRL, &value); |
| 84b5dbf3 MCC |
767 | value |= (0 << 13) | (1 << 4); |
| 768 | value &= ~(1 << 5); | |
| 769 | ||
| b9255176 SD |
770 | /* set [24:23] [22:15] to 0 */ |
| 771 | value &= (~(0x1FF8000)); | |
| 772 | /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ | |
| 773 | value |= 0x1000000; | |
| ecc67d10 SD |
774 | status = vid_blk_write_word(dev, AFE_CTRL, value); |
| 775 | ||
| 776 | status = vid_blk_read_word(dev, OUT_CTRL1, &value); | |
| 84b5dbf3 | 777 | value |= (1 << 7); |
| ecc67d10 | 778 | status = vid_blk_write_word(dev, OUT_CTRL1, value); |
| 84b5dbf3 | 779 | |
| 88806218 | 780 | /* Set output mode */ |
| cde4362f | 781 | status = cx231xx_read_modify_write_i2c_dword(dev, |
| ecc67d10 | 782 | VID_BLK_I2C_ADDRESS, |
| cde4362f | 783 | OUT_CTRL1, FLD_OUT_MODE, |
| 88806218 | 784 | dev->board.output_mode); |
| 84b5dbf3 | 785 | |
| cde4362f MCC |
786 | /* Tell DIF object to go to baseband mode */ |
| 787 | status = cx231xx_dif_set_standard(dev, | |
| 788 | DIF_USE_BASEBAND); | |
| 84b5dbf3 | 789 | if (status < 0) { |
| b9255176 SD |
790 | cx231xx_errdev("%s: cx231xx_dif set to By pass" |
| 791 | " mode- errCode [%d]!\n", | |
| 792 | __func__, status); | |
| 84b5dbf3 MCC |
793 | return status; |
| 794 | } | |
| 795 | ||
| 796 | /* Read the DFE_CTRL1 register */ | |
| ecc67d10 | 797 | status = vid_blk_read_word(dev, DFE_CTRL1, &value); |
| 84b5dbf3 MCC |
798 | |
| 799 | /* enable the VBI_GATE_EN */ | |
| 800 | value |= FLD_VBI_GATE_EN; | |
| 801 | ||
| 802 | /* Enable the auto-VGA enable */ | |
| 803 | value |= FLD_VGA_AUTO_EN; | |
| 804 | ||
| 805 | /* Write it back */ | |
| ecc67d10 | 806 | status = vid_blk_write_word(dev, DFE_CTRL1, value); |
| 84b5dbf3 MCC |
807 | |
| 808 | /* Disable auto config of registers */ | |
| cde4362f | 809 | status = cx231xx_read_modify_write_i2c_dword(dev, |
| ecc67d10 | 810 | VID_BLK_I2C_ADDRESS, |
| cde4362f MCC |
811 | MODE_CTRL, FLD_ACFG_DIS, |
| 812 | cx231xx_set_field(FLD_ACFG_DIS, 1)); | |
| 84b5dbf3 MCC |
813 | |
| 814 | /* Set CVBS input mode */ | |
| cde4362f | 815 | status = cx231xx_read_modify_write_i2c_dword(dev, |
| ecc67d10 | 816 | VID_BLK_I2C_ADDRESS, |
| cde4362f | 817 | MODE_CTRL, FLD_INPUT_MODE, |
| b9255176 SD |
818 | cx231xx_set_field(FLD_INPUT_MODE, |
| 819 | INPUT_MODE_CVBS_0)); | |
| 2f861387 | 820 | } else { |
| cde4362f | 821 | /* Enable the DIF for the tuner */ |
| 84b5dbf3 | 822 | |
| cde4362f MCC |
823 | /* Reinitialize the DIF */ |
| 824 | status = cx231xx_dif_set_standard(dev, dev->norm); | |
| 84b5dbf3 | 825 | if (status < 0) { |
| b9255176 SD |
826 | cx231xx_errdev("%s: cx231xx_dif set to By pass" |
| 827 | " mode- errCode [%d]!\n", | |
| 828 | __func__, status); | |
| 84b5dbf3 MCC |
829 | return status; |
| 830 | } | |
| 831 | ||
| cde4362f | 832 | /* Make sure bypass is cleared */ |
| ecc67d10 | 833 | status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value); |
| cde4362f MCC |
834 | |
| 835 | /* Clear the bypass bit */ | |
| 836 | value &= ~FLD_DIF_DIF_BYPASS; | |
| 837 | ||
| 838 | /* Enable the use of the DIF block */ | |
| ecc67d10 | 839 | status = vid_blk_write_word(dev, DIF_MISC_CTRL, value); |
| cde4362f | 840 | |
| 84b5dbf3 | 841 | /* Read the DFE_CTRL1 register */ |
| ecc67d10 | 842 | status = vid_blk_read_word(dev, DFE_CTRL1, &value); |
| 84b5dbf3 | 843 | |
| cde4362f MCC |
844 | /* Disable the VBI_GATE_EN */ |
| 845 | value &= ~FLD_VBI_GATE_EN; | |
| 84b5dbf3 | 846 | |
| cde4362f MCC |
847 | /* Enable the auto-VGA enable, AGC, and |
| 848 | set the skip count to 2 */ | |
| 849 | value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000; | |
| 84b5dbf3 MCC |
850 | |
| 851 | /* Write it back */ | |
| ecc67d10 | 852 | status = vid_blk_write_word(dev, DFE_CTRL1, value); |
| 84b5dbf3 | 853 | |
| 6e4f574b | 854 | /* Wait until AGC locks up */ |
| cde4362f | 855 | msleep(1); |
| 84b5dbf3 | 856 | |
| cde4362f MCC |
857 | /* Disable the auto-VGA enable AGC */ |
| 858 | value &= ~(FLD_VGA_AUTO_EN); | |
| 84b5dbf3 | 859 | |
| cde4362f | 860 | /* Write it back */ |
| ecc67d10 | 861 | status = vid_blk_write_word(dev, DFE_CTRL1, value); |
| 84b5dbf3 | 862 | |
| cde4362f | 863 | /* Enable Polaris B0 AGC output */ |
| ecc67d10 | 864 | status = vid_blk_read_word(dev, PIN_CTRL, &value); |
| cde4362f MCC |
865 | value |= (FLD_OEF_AGC_RF) | |
| 866 | (FLD_OEF_AGC_IFVGA) | | |
| 867 | (FLD_OEF_AGC_IF); | |
| ecc67d10 | 868 | status = vid_blk_write_word(dev, PIN_CTRL, value); |
| cde4362f | 869 | |
| 88806218 | 870 | /* Set output mode */ |
| cde4362f | 871 | status = cx231xx_read_modify_write_i2c_dword(dev, |
| ecc67d10 | 872 | VID_BLK_I2C_ADDRESS, |
| cde4362f | 873 | OUT_CTRL1, FLD_OUT_MODE, |
| 88806218 | 874 | dev->board.output_mode); |
| cde4362f MCC |
875 | |
| 876 | /* Disable auto config of registers */ | |
| 877 | status = cx231xx_read_modify_write_i2c_dword(dev, | |
| ecc67d10 | 878 | VID_BLK_I2C_ADDRESS, |
| cde4362f MCC |
879 | MODE_CTRL, FLD_ACFG_DIS, |
| 880 | cx231xx_set_field(FLD_ACFG_DIS, 1)); | |
| 881 | ||
| 882 | /* Set CVBS input mode */ | |
| 883 | status = cx231xx_read_modify_write_i2c_dword(dev, | |
| ecc67d10 | 884 | VID_BLK_I2C_ADDRESS, |
| cde4362f | 885 | MODE_CTRL, FLD_INPUT_MODE, |
| b9255176 SD |
886 | cx231xx_set_field(FLD_INPUT_MODE, |
| 887 | INPUT_MODE_CVBS_0)); | |
| cde4362f | 888 | |
| b9255176 SD |
889 | /* Set some bits in AFE_CTRL so that channel 2 or 3 |
| 890 | * is ready to receive audio */ | |
| cde4362f MCC |
891 | /* Clear clamp for channels 2 and 3 (bit 16-17) */ |
| 892 | /* Clear droop comp (bit 19-20) */ | |
| 893 | /* Set VGA_SEL (for audio control) (bit 7-8) */ | |
| ecc67d10 | 894 | status = vid_blk_read_word(dev, AFE_CTRL, &value); |
| cde4362f | 895 | |
| 64fbf444 PB |
896 | /*Set Func mode:01-DIF 10-baseband 11-YUV*/ |
| 897 | value &= (~(FLD_FUNC_MODE)); | |
| 898 | value |= 0x800000; | |
| 899 | ||
| cde4362f MCC |
900 | value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2; |
| 901 | ||
| ecc67d10 | 902 | status = vid_blk_write_word(dev, AFE_CTRL, value); |
| 64fbf444 PB |
903 | |
| 904 | if (dev->tuner_type == TUNER_NXP_TDA18271) { | |
| 905 | status = vid_blk_read_word(dev, PIN_CTRL, | |
| 906 | &value); | |
| 907 | status = vid_blk_write_word(dev, PIN_CTRL, | |
| 908 | (value & 0xFFFFFFEF)); | |
| 909 | } | |
| 910 | ||
| cde4362f | 911 | break; |
| 84b5dbf3 | 912 | |
| 84b5dbf3 MCC |
913 | } |
| 914 | break; | |
| 915 | } | |
| 916 | ||
| 917 | /* Set raw VBI mode */ | |
| cde4362f | 918 | status = cx231xx_read_modify_write_i2c_dword(dev, |
| ecc67d10 | 919 | VID_BLK_I2C_ADDRESS, |
| cde4362f MCC |
920 | OUT_CTRL1, FLD_VBIHACTRAW_EN, |
| 921 | cx231xx_set_field(FLD_VBIHACTRAW_EN, 1)); | |
| 84b5dbf3 | 922 | |
| ecc67d10 | 923 | status = vid_blk_read_word(dev, OUT_CTRL1, &value); |
| 84b5dbf3 MCC |
924 | if (value & 0x02) { |
| 925 | value |= (1 << 19); | |
| ecc67d10 | 926 | status = vid_blk_write_word(dev, OUT_CTRL1, value); |
| 84b5dbf3 MCC |
927 | } |
| 928 | ||
| 929 | return status; | |
| e0d3bafd SD |
930 | } |
| 931 | ||
| 64fbf444 PB |
932 | void cx231xx_enable656(struct cx231xx *dev) |
| 933 | { | |
| 934 | u8 temp = 0; | |
| 935 | int status; | |
| 955e6ed8 | 936 | /*enable TS1 data[0:7] as output to export 656*/ |
| 64fbf444 PB |
937 | |
| 938 | status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF); | |
| 939 | ||
| 955e6ed8 | 940 | /*enable TS1 clock as output to export 656*/ |
| 64fbf444 PB |
941 | |
| 942 | status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp); | |
| 943 | temp = temp|0x04; | |
| 944 | ||
| 945 | status = vid_blk_write_byte(dev, TS1_PIN_CTL1, temp); | |
| 946 | ||
| 947 | } | |
| 948 | EXPORT_SYMBOL_GPL(cx231xx_enable656); | |
| 949 | ||
| 950 | void cx231xx_disable656(struct cx231xx *dev) | |
| 951 | { | |
| 952 | u8 temp = 0; | |
| 953 | int status; | |
| 954 | ||
| 955 | ||
| 956 | status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00); | |
| 957 | ||
| 958 | status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp); | |
| 959 | temp = temp&0xFB; | |
| 960 | ||
| 961 | status = vid_blk_write_byte(dev, TS1_PIN_CTL1, temp); | |
| 962 | } | |
| 963 | EXPORT_SYMBOL_GPL(cx231xx_disable656); | |
| 964 | ||
| e0d3bafd | 965 | /* |
| b9255176 SD |
966 | * Handle any video-mode specific overrides that are different |
| 967 | * on a per video standards basis after touching the MODE_CTRL | |
| 968 | * register which resets many values for autodetect | |
| e0d3bafd SD |
969 | */ |
| 970 | int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev) | |
| 971 | { | |
| 84b5dbf3 MCC |
972 | int status = 0; |
| 973 | ||
| 974 | cx231xx_info("do_mode_ctrl_overrides : 0x%x\n", | |
| 975 | (unsigned int)dev->norm); | |
| 976 | ||
| 977 | /* Change the DFE_CTRL3 bp_percent to fix flagging */ | |
| ecc67d10 | 978 | status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280); |
| 84b5dbf3 | 979 | |
| 6e4f574b | 980 | if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) { |
| 84b5dbf3 MCC |
981 | cx231xx_info("do_mode_ctrl_overrides NTSC\n"); |
| 982 | ||
| cde4362f MCC |
983 | /* Move the close caption lines out of active video, |
| 984 | adjust the active video start point */ | |
| 985 | status = cx231xx_read_modify_write_i2c_dword(dev, | |
| ecc67d10 | 986 | VID_BLK_I2C_ADDRESS, |
| 84b5dbf3 MCC |
987 | VERT_TIM_CTRL, |
| 988 | FLD_VBLANK_CNT, 0x18); | |
| cde4362f | 989 | status = cx231xx_read_modify_write_i2c_dword(dev, |
| ecc67d10 | 990 | VID_BLK_I2C_ADDRESS, |
| 84b5dbf3 MCC |
991 | VERT_TIM_CTRL, |
| 992 | FLD_VACTIVE_CNT, | |
| 435b4f78 | 993 | 0x1E7000); |
| cde4362f | 994 | status = cx231xx_read_modify_write_i2c_dword(dev, |
| ecc67d10 | 995 | VID_BLK_I2C_ADDRESS, |
| 84b5dbf3 MCC |
996 | VERT_TIM_CTRL, |
| 997 | FLD_V656BLANK_CNT, | |
| 64fbf444 | 998 | 0x1C000000); |
| 84b5dbf3 | 999 | |
| cde4362f | 1000 | status = cx231xx_read_modify_write_i2c_dword(dev, |
| ecc67d10 | 1001 | VID_BLK_I2C_ADDRESS, |
| 84b5dbf3 MCC |
1002 | HORIZ_TIM_CTRL, |
| 1003 | FLD_HBLANK_CNT, | |
| 1004 | cx231xx_set_field | |
| 1005 | (FLD_HBLANK_CNT, 0x79)); | |
| 64fbf444 | 1006 | |
| 6e4f574b SD |
1007 | } else if (dev->norm & V4L2_STD_SECAM) { |
| 1008 | cx231xx_info("do_mode_ctrl_overrides SECAM\n"); | |
| 1009 | status = cx231xx_read_modify_write_i2c_dword(dev, | |
| ecc67d10 | 1010 | VID_BLK_I2C_ADDRESS, |
| 84b5dbf3 | 1011 | VERT_TIM_CTRL, |
| 6af8cc0b | 1012 | FLD_VBLANK_CNT, 0x20); |
| 222c4352 DH |
1013 | status = cx231xx_read_modify_write_i2c_dword(dev, |
| 1014 | VID_BLK_I2C_ADDRESS, | |
| 1015 | VERT_TIM_CTRL, | |
| 1016 | FLD_VACTIVE_CNT, | |
| 1017 | cx231xx_set_field | |
| 1018 | (FLD_VACTIVE_CNT, | |
| 6af8cc0b | 1019 | 0x244)); |
| 64fbf444 PB |
1020 | status = cx231xx_read_modify_write_i2c_dword(dev, |
| 1021 | VID_BLK_I2C_ADDRESS, | |
| 1022 | VERT_TIM_CTRL, | |
| 1023 | FLD_V656BLANK_CNT, | |
| 1024 | cx231xx_set_field | |
| 1025 | (FLD_V656BLANK_CNT, | |
| 6af8cc0b | 1026 | 0x24)); |
| 84b5dbf3 | 1027 | /* Adjust the active video horizontal start point */ |
| cde4362f | 1028 | status = cx231xx_read_modify_write_i2c_dword(dev, |
| ecc67d10 | 1029 | VID_BLK_I2C_ADDRESS, |
| 84b5dbf3 MCC |
1030 | HORIZ_TIM_CTRL, |
| 1031 | FLD_HBLANK_CNT, | |
| 1032 | cx231xx_set_field | |
| 1033 | (FLD_HBLANK_CNT, 0x85)); | |
| 6e4f574b SD |
1034 | } else { |
| 1035 | cx231xx_info("do_mode_ctrl_overrides PAL\n"); | |
| 1036 | status = cx231xx_read_modify_write_i2c_dword(dev, | |
| ecc67d10 | 1037 | VID_BLK_I2C_ADDRESS, |
| 84b5dbf3 | 1038 | VERT_TIM_CTRL, |
| 6af8cc0b | 1039 | FLD_VBLANK_CNT, 0x20); |
| 222c4352 DH |
1040 | status = cx231xx_read_modify_write_i2c_dword(dev, |
| 1041 | VID_BLK_I2C_ADDRESS, | |
| 1042 | VERT_TIM_CTRL, | |
| 1043 | FLD_VACTIVE_CNT, | |
| 1044 | cx231xx_set_field | |
| 1045 | (FLD_VACTIVE_CNT, | |
| 6af8cc0b | 1046 | 0x244)); |
| 64fbf444 PB |
1047 | status = cx231xx_read_modify_write_i2c_dword(dev, |
| 1048 | VID_BLK_I2C_ADDRESS, | |
| 1049 | VERT_TIM_CTRL, | |
| 1050 | FLD_V656BLANK_CNT, | |
| 1051 | cx231xx_set_field | |
| 1052 | (FLD_V656BLANK_CNT, | |
| 6af8cc0b | 1053 | 0x24)); |
| 84b5dbf3 | 1054 | /* Adjust the active video horizontal start point */ |
| cde4362f | 1055 | status = cx231xx_read_modify_write_i2c_dword(dev, |
| ecc67d10 | 1056 | VID_BLK_I2C_ADDRESS, |
| 84b5dbf3 MCC |
1057 | HORIZ_TIM_CTRL, |
| 1058 | FLD_HBLANK_CNT, | |
| 1059 | cx231xx_set_field | |
| 1060 | (FLD_HBLANK_CNT, 0x85)); | |
| 64fbf444 | 1061 | |
| 84b5dbf3 MCC |
1062 | } |
| 1063 | ||
| 1064 | return status; | |
| e0d3bafd SD |
1065 | } |
| 1066 | ||
| 64fbf444 PB |
1067 | int cx231xx_unmute_audio(struct cx231xx *dev) |
| 1068 | { | |
| 1069 | return vid_blk_write_byte(dev, PATH1_VOL_CTL, 0x24); | |
| 1070 | } | |
| 1071 | EXPORT_SYMBOL_GPL(cx231xx_unmute_audio); | |
| 1072 | ||
| 1073 | int stopAudioFirmware(struct cx231xx *dev) | |
| 1074 | { | |
| 1075 | return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x03); | |
| 1076 | } | |
| 1077 | ||
| 1078 | int restartAudioFirmware(struct cx231xx *dev) | |
| 1079 | { | |
| 1080 | return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x13); | |
| 1081 | } | |
| 1082 | ||
| e0d3bafd SD |
1083 | int cx231xx_set_audio_input(struct cx231xx *dev, u8 input) |
| 1084 | { | |
| 84b5dbf3 MCC |
1085 | int status = 0; |
| 1086 | enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE; | |
| 1087 | ||
| 1088 | switch (INPUT(input)->amux) { | |
| 1089 | case CX231XX_AMUX_VIDEO: | |
| 1090 | ainput = AUDIO_INPUT_TUNER_TV; | |
| 1091 | break; | |
| 1092 | case CX231XX_AMUX_LINE_IN: | |
| ecc67d10 | 1093 | status = cx231xx_i2s_blk_set_audio_input(dev, input); |
| 84b5dbf3 MCC |
1094 | ainput = AUDIO_INPUT_LINE; |
| 1095 | break; | |
| 1096 | default: | |
| 1097 | break; | |
| 1098 | } | |
| 1099 | ||
| 1100 | status = cx231xx_set_audio_decoder_input(dev, ainput); | |
| 1101 | ||
| 1102 | return status; | |
| e0d3bafd SD |
1103 | } |
| 1104 | ||
| 84b5dbf3 MCC |
1105 | int cx231xx_set_audio_decoder_input(struct cx231xx *dev, |
| 1106 | enum AUDIO_INPUT audio_input) | |
| e0d3bafd | 1107 | { |
| 84b5dbf3 MCC |
1108 | u32 dwval; |
| 1109 | int status; | |
| ecc67d10 | 1110 | u8 gen_ctrl; |
| 84b5dbf3 MCC |
1111 | u32 value = 0; |
| 1112 | ||
| 1113 | /* Put it in soft reset */ | |
| ecc67d10 | 1114 | status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl); |
| 84b5dbf3 | 1115 | gen_ctrl |= 1; |
| ecc67d10 | 1116 | status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl); |
| 84b5dbf3 MCC |
1117 | |
| 1118 | switch (audio_input) { | |
| 1119 | case AUDIO_INPUT_LINE: | |
| 84b5dbf3 | 1120 | /* setup AUD_IO control from Merlin paralle output */ |
| cde4362f MCC |
1121 | value = cx231xx_set_field(FLD_AUD_CHAN1_SRC, |
| 1122 | AUD_CHAN_SRC_PARALLEL); | |
| ecc67d10 | 1123 | status = vid_blk_write_word(dev, AUD_IO_CTRL, value); |
| 84b5dbf3 MCC |
1124 | |
| 1125 | /* setup input to Merlin, SRC2 connect to AC97 | |
| 1126 | bypass upsample-by-2, slave mode, sony mode, left justify | |
| 1127 | adr 091c, dat 01000000 */ | |
| ecc67d10 | 1128 | status = vid_blk_read_word(dev, AC97_CTL, &dwval); |
| 84b5dbf3 | 1129 | |
| ecc67d10 SD |
1130 | status = vid_blk_write_word(dev, AC97_CTL, |
| 1131 | (dwval | FLD_AC97_UP2X_BYPASS)); | |
| 84b5dbf3 MCC |
1132 | |
| 1133 | /* select the parallel1 and SRC3 */ | |
| ecc67d10 | 1134 | status = vid_blk_write_word(dev, BAND_OUT_SEL, |
| cde4362f MCC |
1135 | cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) | |
| 1136 | cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) | | |
| ecc67d10 | 1137 | cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0)); |
| 84b5dbf3 MCC |
1138 | |
| 1139 | /* unmute all, AC97 in, independence mode | |
| 1140 | adr 08d0, data 0x00063073 */ | |
| 64fbf444 | 1141 | status = vid_blk_write_word(dev, DL_CTL, 0x3000001); |
| ecc67d10 | 1142 | status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073); |
| 84b5dbf3 MCC |
1143 | |
| 1144 | /* set AVC maximum threshold, adr 08d4, dat ffff0024 */ | |
| ecc67d10 SD |
1145 | status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval); |
| 1146 | status = vid_blk_write_word(dev, PATH1_VOL_CTL, | |
| 1147 | (dwval | FLD_PATH1_AVC_THRESHOLD)); | |
| 84b5dbf3 MCC |
1148 | |
| 1149 | /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */ | |
| ecc67d10 SD |
1150 | status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval); |
| 1151 | status = vid_blk_write_word(dev, PATH1_SC_CTL, | |
| 1152 | (dwval | FLD_PATH1_SC_THRESHOLD)); | |
| 84b5dbf3 MCC |
1153 | break; |
| 1154 | ||
| 1155 | case AUDIO_INPUT_TUNER_TV: | |
| 1156 | default: | |
| 64fbf444 | 1157 | status = stopAudioFirmware(dev); |
| 84b5dbf3 | 1158 | /* Setup SRC sources and clocks */ |
| ecc67d10 | 1159 | status = vid_blk_write_word(dev, BAND_OUT_SEL, |
| cde4362f MCC |
1160 | cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) | |
| 1161 | cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) | | |
| 1162 | cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) | | |
| 1163 | cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02) | | |
| 1164 | cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02) | | |
| 1165 | cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03) | | |
| 1166 | cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00) | | |
| 1167 | cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00) | | |
| 1168 | cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) | | |
| 1169 | cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) | | |
| 1170 | cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) | | |
| 1171 | cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) | | |
| ecc67d10 | 1172 | cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01)); |
| 84b5dbf3 MCC |
1173 | |
| 1174 | /* Setup the AUD_IO control */ | |
| ecc67d10 | 1175 | status = vid_blk_write_word(dev, AUD_IO_CTRL, |
| cde4362f MCC |
1176 | cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) | |
| 1177 | cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) | | |
| 1178 | cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) | | |
| 1179 | cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) | | |
| ecc67d10 | 1180 | cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03)); |
| 84b5dbf3 | 1181 | |
| ecc67d10 | 1182 | status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870); |
| 84b5dbf3 MCC |
1183 | |
| 1184 | /* setAudioStandard(_audio_standard); */ | |
| ecc67d10 | 1185 | status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870); |
| 64fbf444 PB |
1186 | |
| 1187 | status = restartAudioFirmware(dev); | |
| 1188 | ||
| 8aed3f47 DH |
1189 | switch (dev->board.tuner_type) { |
| 1190 | case TUNER_XC5000: | |
| 1191 | /* SIF passthrough at 28.6363 MHz sample rate */ | |
| cde4362f | 1192 | status = cx231xx_read_modify_write_i2c_dword(dev, |
| ecc67d10 | 1193 | VID_BLK_I2C_ADDRESS, |
| cde4362f MCC |
1194 | CHIP_CTRL, |
| 1195 | FLD_SIF_EN, | |
| 1196 | cx231xx_set_field(FLD_SIF_EN, 1)); | |
| 84b5dbf3 | 1197 | break; |
| 8aed3f47 DH |
1198 | case TUNER_NXP_TDA18271: |
| 1199 | /* Normal mode: SIF passthrough at 14.32 MHz */ | |
| 64fbf444 PB |
1200 | status = cx231xx_read_modify_write_i2c_dword(dev, |
| 1201 | VID_BLK_I2C_ADDRESS, | |
| 1202 | CHIP_CTRL, | |
| 1203 | FLD_SIF_EN, | |
| 1204 | cx231xx_set_field(FLD_SIF_EN, 0)); | |
| 1205 | break; | |
| 84b5dbf3 | 1206 | default: |
| 8aed3f47 DH |
1207 | /* This is just a casual suggestion to people adding |
| 1208 | new boards in case they use a tuner type we don't | |
| 1209 | currently know about */ | |
| 1210 | printk(KERN_INFO "Unknown tuner type configuring SIF"); | |
| 84b5dbf3 MCC |
1211 | break; |
| 1212 | } | |
| 1213 | break; | |
| 1214 | ||
| 1215 | case AUDIO_INPUT_TUNER_FM: | |
| 1216 | /* use SIF for FM radio | |
| 1217 | setupFM(); | |
| 1218 | setAudioStandard(_audio_standard); | |
| 1219 | */ | |
| 1220 | break; | |
| 1221 | ||
| 1222 | case AUDIO_INPUT_MUTE: | |
| ecc67d10 | 1223 | status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012); |
| 84b5dbf3 MCC |
1224 | break; |
| 1225 | } | |
| e0d3bafd | 1226 | |
| 84b5dbf3 | 1227 | /* Take it out of soft reset */ |
| ecc67d10 | 1228 | status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl); |
| 84b5dbf3 | 1229 | gen_ctrl &= ~1; |
| ecc67d10 | 1230 | status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl); |
| e0d3bafd | 1231 | |
| 84b5dbf3 MCC |
1232 | return status; |
| 1233 | } | |
| e0d3bafd | 1234 | |
| cde4362f MCC |
1235 | /****************************************************************************** |
| 1236 | * C H I P Specific C O N T R O L functions * | |
| 1237 | ******************************************************************************/ | |
| e0d3bafd SD |
1238 | int cx231xx_init_ctrl_pin_status(struct cx231xx *dev) |
| 1239 | { | |
| 84b5dbf3 MCC |
1240 | u32 value; |
| 1241 | int status = 0; | |
| e0d3bafd | 1242 | |
| ecc67d10 | 1243 | status = vid_blk_read_word(dev, PIN_CTRL, &value); |
| 84b5dbf3 | 1244 | value |= (~dev->board.ctl_pin_status_mask); |
| ecc67d10 | 1245 | status = vid_blk_write_word(dev, PIN_CTRL, value); |
| e0d3bafd | 1246 | |
| 84b5dbf3 | 1247 | return status; |
| e0d3bafd SD |
1248 | } |
| 1249 | ||
| 84b5dbf3 MCC |
1250 | int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev, |
| 1251 | u8 analog_or_digital) | |
| e0d3bafd | 1252 | { |
| 84b5dbf3 | 1253 | int status = 0; |
| e0d3bafd | 1254 | |
| 84b5dbf3 | 1255 | /* first set the direction to output */ |
| cde4362f MCC |
1256 | status = cx231xx_set_gpio_direction(dev, |
| 1257 | dev->board. | |
| 1258 | agc_analog_digital_select_gpio, 1); | |
| e0d3bafd | 1259 | |
| 84b5dbf3 | 1260 | /* 0 - demod ; 1 - Analog mode */ |
| cde4362f | 1261 | status = cx231xx_set_gpio_value(dev, |
| 84b5dbf3 MCC |
1262 | dev->board.agc_analog_digital_select_gpio, |
| 1263 | analog_or_digital); | |
| e0d3bafd | 1264 | |
| 84b5dbf3 | 1265 | return status; |
| e0d3bafd SD |
1266 | } |
| 1267 | ||
| a6f6fb9c | 1268 | int cx231xx_enable_i2c_port_3(struct cx231xx *dev, bool is_port_3) |
| e0d3bafd | 1269 | { |
| 84b5dbf3 MCC |
1270 | u8 value[4] = { 0, 0, 0, 0 }; |
| 1271 | int status = 0; | |
| a6f6fb9c | 1272 | bool current_is_port_3; |
| e0d3bafd | 1273 | |
| 38f5ddc1 MCC |
1274 | if (dev->board.dont_use_port_3) |
| 1275 | is_port_3 = false; | |
| cde4362f MCC |
1276 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, |
| 1277 | PWR_CTL_EN, value, 4); | |
| 84b5dbf3 MCC |
1278 | if (status < 0) |
| 1279 | return status; | |
| e0d3bafd | 1280 | |
| a6f6fb9c MCC |
1281 | current_is_port_3 = value[0] & I2C_DEMOD_EN ? true : false; |
| 1282 | ||
| 1283 | /* Just return, if already using the right port */ | |
| 1284 | if (current_is_port_3 == is_port_3) | |
| 1285 | return 0; | |
| 1286 | ||
| 1287 | if (is_port_3) | |
| 1288 | value[0] |= I2C_DEMOD_EN; | |
| 1289 | else | |
| 1290 | value[0] &= ~I2C_DEMOD_EN; | |
| 1291 | ||
| 1292 | cx231xx_info("Changing the i2c master port to %d\n", | |
| 1293 | is_port_3 ? 3 : 1); | |
| 1294 | ||
| 1295 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, | |
| 1296 | PWR_CTL_EN, value, 4); | |
| e0d3bafd | 1297 | |
| 84b5dbf3 | 1298 | return status; |
| e0d3bafd | 1299 | |
| 64fbf444 | 1300 | } |
| a6f6fb9c MCC |
1301 | EXPORT_SYMBOL_GPL(cx231xx_enable_i2c_port_3); |
| 1302 | ||
| 64fbf444 PB |
1303 | void update_HH_register_after_set_DIF(struct cx231xx *dev) |
| 1304 | { | |
| 1305 | /* | |
| 1306 | u8 status = 0; | |
| 1307 | u32 value = 0; | |
| 1308 | ||
| 1309 | vid_blk_write_word(dev, PIN_CTRL, 0xA0FFF82F); | |
| 1310 | vid_blk_write_word(dev, DIF_MISC_CTRL, 0x0A203F11); | |
| 1311 | vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0x1BEFBF06); | |
| 1312 | ||
| 1313 | status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); | |
| 1314 | vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390); | |
| 1315 | status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); | |
| 1316 | */ | |
| 1317 | } | |
| 1318 | ||
| 1319 | void cx231xx_dump_HH_reg(struct cx231xx *dev) | |
| 1320 | { | |
| 1321 | u8 status = 0; | |
| 1322 | u32 value = 0; | |
| 1323 | u16 i = 0; | |
| 1324 | ||
| 1325 | value = 0x45005390; | |
| 1326 | status = vid_blk_write_word(dev, 0x104, value); | |
| 1327 | ||
| 1328 | for (i = 0x100; i < 0x140; i++) { | |
| 1329 | status = vid_blk_read_word(dev, i, &value); | |
| 1330 | cx231xx_info("reg0x%x=0x%x\n", i, value); | |
| 1331 | i = i+3; | |
| 1332 | } | |
| 1333 | ||
| 1334 | for (i = 0x300; i < 0x400; i++) { | |
| 1335 | status = vid_blk_read_word(dev, i, &value); | |
| 1336 | cx231xx_info("reg0x%x=0x%x\n", i, value); | |
| 1337 | i = i+3; | |
| 1338 | } | |
| 1339 | ||
| 1340 | for (i = 0x400; i < 0x440; i++) { | |
| 1341 | status = vid_blk_read_word(dev, i, &value); | |
| 1342 | cx231xx_info("reg0x%x=0x%x\n", i, value); | |
| 1343 | i = i+3; | |
| 1344 | } | |
| 1345 | ||
| 955e6ed8 MCC |
1346 | status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); |
| 1347 | cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value); | |
| 1348 | vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390); | |
| 1349 | status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); | |
| 1350 | cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value); | |
| 64fbf444 | 1351 | } |
| 955e6ed8 | 1352 | |
| 64fbf444 PB |
1353 | void cx231xx_dump_SC_reg(struct cx231xx *dev) |
| 1354 | { | |
| 1355 | u8 value[4] = { 0, 0, 0, 0 }; | |
| 1356 | int status = 0; | |
| 1357 | cx231xx_info("cx231xx_dump_SC_reg %s!\n", __TIME__); | |
| 1358 | ||
| 1359 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT, | |
| 1360 | value, 4); | |
| 1361 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", BOARD_CFG_STAT, value[0], | |
| 1362 | value[1], value[2], value[3]); | |
| 1363 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG, | |
| 1364 | value, 4); | |
| 1365 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS_MODE_REG, value[0], | |
| 1366 | value[1], value[2], value[3]); | |
| 1367 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG, | |
| 1368 | value, 4); | |
| 1369 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_CFG_REG, value[0], | |
| 1370 | value[1], value[2], value[3]); | |
| 1371 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG, | |
| 1372 | value, 4); | |
| 1373 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_LENGTH_REG, value[0], | |
| 1374 | value[1], value[2], value[3]); | |
| 1375 | ||
| 1376 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG, | |
| 1377 | value, 4); | |
| 1378 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_CFG_REG, value[0], | |
| 1379 | value[1], value[2], value[3]); | |
| 1380 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG, | |
| 1381 | value, 4); | |
| 1382 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_LENGTH_REG, value[0], | |
| 1383 | value[1], value[2], value[3]); | |
| 1384 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, | |
| 1385 | value, 4); | |
| 1386 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", EP_MODE_SET, value[0], | |
| 1387 | value[1], value[2], value[3]); | |
| 1388 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1, | |
| 1389 | value, 4); | |
| 1390 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN1, value[0], | |
| 1391 | value[1], value[2], value[3]); | |
| 1392 | ||
| 1393 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2, | |
| 1394 | value, 4); | |
| 1395 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN2, value[0], | |
| 1396 | value[1], value[2], value[3]); | |
| 1397 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3, | |
| 1398 | value, 4); | |
| 1399 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN3, value[0], | |
| 1400 | value[1], value[2], value[3]); | |
| 1401 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0, | |
| 1402 | value, 4); | |
| 1403 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK0, value[0], | |
| 1404 | value[1], value[2], value[3]); | |
| 1405 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1, | |
| 1406 | value, 4); | |
| 1407 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK1, value[0], | |
| 1408 | value[1], value[2], value[3]); | |
| 1409 | ||
| 1410 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2, | |
| 1411 | value, 4); | |
| 1412 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK2, value[0], | |
| 1413 | value[1], value[2], value[3]); | |
| 1414 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN, | |
| 1415 | value, 4); | |
| 1416 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_GAIN, value[0], | |
| 1417 | value[1], value[2], value[3]); | |
| 1418 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG, | |
| 1419 | value, 4); | |
| 1420 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_CAR_REG, value[0], | |
| 1421 | value[1], value[2], value[3]); | |
| 1422 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1, | |
| 1423 | value, 4); | |
| 1424 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG1, value[0], | |
| 1425 | value[1], value[2], value[3]); | |
| 1426 | ||
| 1427 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2, | |
| 1428 | value, 4); | |
| 1429 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG2, value[0], | |
| 1430 | value[1], value[2], value[3]); | |
| 1431 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, | |
| 1432 | value, 4); | |
| 1433 | cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0], | |
| 1434 | value[1], value[2], value[3]); | |
| 1435 | ||
| 1436 | ||
| 1437 | } | |
| 1438 | ||
| 1439 | void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev) | |
| 1440 | ||
| 1441 | { | |
| 1442 | u8 status = 0; | |
| 1443 | u8 value = 0; | |
| 1444 | ||
| 1445 | ||
| 1446 | ||
| 1447 | status = afe_read_byte(dev, ADC_STATUS2_CH3, &value); | |
| 1448 | value = (value & 0xFE)|0x01; | |
| 1449 | status = afe_write_byte(dev, ADC_STATUS2_CH3, value); | |
| 1450 | ||
| 1451 | status = afe_read_byte(dev, ADC_STATUS2_CH3, &value); | |
| 1452 | value = (value & 0xFE)|0x00; | |
| 1453 | status = afe_write_byte(dev, ADC_STATUS2_CH3, value); | |
| 1454 | ||
| 1455 | ||
| 1456 | /* | |
| 955e6ed8 | 1457 | config colibri to lo-if mode |
| 64fbf444 | 1458 | |
| 955e6ed8 MCC |
1459 | FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce |
| 1460 | the diff IF input by half, | |
| 64fbf444 | 1461 | |
| 955e6ed8 | 1462 | for low-if agc defect |
| 64fbf444 PB |
1463 | */ |
| 1464 | ||
| 1465 | status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value); | |
| 1466 | value = (value & 0xFC)|0x00; | |
| 1467 | status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value); | |
| 1468 | ||
| 1469 | status = afe_read_byte(dev, ADC_INPUT_CH3, &value); | |
| 1470 | value = (value & 0xF9)|0x02; | |
| 1471 | status = afe_write_byte(dev, ADC_INPUT_CH3, value); | |
| 1472 | ||
| 1473 | status = afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value); | |
| 1474 | value = (value & 0xFB)|0x04; | |
| 1475 | status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, value); | |
| 1476 | ||
| 1477 | status = afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value); | |
| 1478 | value = (value & 0xFC)|0x03; | |
| 1479 | status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value); | |
| 1480 | ||
| 1481 | status = afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value); | |
| 1482 | value = (value & 0xFB)|0x04; | |
| 1483 | status = afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value); | |
| 1484 | ||
| 1485 | status = afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value); | |
| 1486 | value = (value & 0xF8)|0x06; | |
| 1487 | status = afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value); | |
| 1488 | ||
| 1489 | status = afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value); | |
| 1490 | value = (value & 0x8F)|0x40; | |
| 1491 | status = afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value); | |
| 1492 | ||
| 1493 | status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value); | |
| 1494 | value = (value & 0xDF)|0x20; | |
| 1495 | status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value); | |
| 1496 | } | |
| 1497 | ||
| 1498 | void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq, | |
| 1499 | u8 spectral_invert, u32 mode) | |
| 1500 | { | |
| 2ded0fe1 DH |
1501 | u32 colibri_carrier_offset = 0; |
| 1502 | u8 status = 0; | |
| 1503 | u32 func_mode = 0x01; /* Device has a DIF if this function is called */ | |
| 1504 | u32 standard = 0; | |
| 64fbf444 PB |
1505 | u8 value[4] = { 0, 0, 0, 0 }; |
| 1506 | ||
| 64fbf444 | 1507 | cx231xx_info("Enter cx231xx_set_Colibri_For_LowIF()\n"); |
| 2ded0fe1 DH |
1508 | value[0] = (u8) 0x6F; |
| 1509 | value[1] = (u8) 0x6F; | |
| 1510 | value[2] = (u8) 0x6F; | |
| 1511 | value[3] = (u8) 0x6F; | |
| 1512 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, | |
| 1513 | PWR_CTL_EN, value, 4); | |
| 64fbf444 PB |
1514 | |
| 1515 | /*Set colibri for low IF*/ | |
| 1516 | status = cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF); | |
| 1517 | ||
| 64fbf444 PB |
1518 | /* Set C2HH for low IF operation.*/ |
| 1519 | standard = dev->norm; | |
| 1520 | status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode, | |
| 2ded0fe1 | 1521 | func_mode, standard); |
| 64fbf444 PB |
1522 | |
| 1523 | /* Get colibri offsets.*/ | |
| 1524 | colibri_carrier_offset = cx231xx_Get_Colibri_CarrierOffset(mode, | |
| 2ded0fe1 | 1525 | standard); |
| 64fbf444 PB |
1526 | |
| 1527 | cx231xx_info("colibri_carrier_offset=%d, standard=0x%x\n", | |
| 2ded0fe1 | 1528 | colibri_carrier_offset, standard); |
| 64fbf444 PB |
1529 | |
| 1530 | /* Set the band Pass filter for DIF*/ | |
| 2ded0fe1 DH |
1531 | cx231xx_set_DIF_bandpass(dev, (if_freq+colibri_carrier_offset), |
| 1532 | spectral_invert, mode); | |
| 64fbf444 PB |
1533 | } |
| 1534 | ||
| 1535 | u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd) | |
| 1536 | { | |
| 955e6ed8 | 1537 | u32 colibri_carrier_offset = 0; |
| 64fbf444 | 1538 | |
| 955e6ed8 | 1539 | if (mode == TUNER_MODE_FM_RADIO) { |
| 64fbf444 | 1540 | colibri_carrier_offset = 1100000; |
| 0f861583 | 1541 | } else if (standerd & (V4L2_STD_MN | V4L2_STD_NTSC_M_JP)) { |
| 64fbf444 PB |
1542 | colibri_carrier_offset = 4832000; /*4.83MHz */ |
| 1543 | } else if (standerd & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) { | |
| 1544 | colibri_carrier_offset = 2700000; /*2.70MHz */ | |
| 1545 | } else if (standerd & (V4L2_STD_PAL_D | V4L2_STD_PAL_I | |
| 1546 | | V4L2_STD_SECAM)) { | |
| 1547 | colibri_carrier_offset = 2100000; /*2.10MHz */ | |
| 1548 | } | |
| 1549 | ||
| 955e6ed8 | 1550 | return colibri_carrier_offset; |
| 64fbf444 PB |
1551 | } |
| 1552 | ||
| 1553 | void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq, | |
| 1554 | u8 spectral_invert, u32 mode) | |
| 1555 | { | |
| 955e6ed8 MCC |
1556 | unsigned long pll_freq_word; |
| 1557 | int status = 0; | |
| 1558 | u32 dif_misc_ctrl_value = 0; | |
| 1559 | u64 pll_freq_u64 = 0; | |
| 1560 | u32 i = 0; | |
| 64fbf444 PB |
1561 | |
| 1562 | cx231xx_info("if_freq=%d;spectral_invert=0x%x;mode=0x%x\n", | |
| 1563 | if_freq, spectral_invert, mode); | |
| 1564 | ||
| 1565 | ||
| 955e6ed8 MCC |
1566 | if (mode == TUNER_MODE_FM_RADIO) { |
| 1567 | pll_freq_word = 0x905A1CAC; | |
| 1568 | status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word); | |
| 64fbf444 | 1569 | |
| 955e6ed8 MCC |
1570 | } else /*KSPROPERTY_TUNER_MODE_TV*/{ |
| 1571 | /* Calculate the PLL frequency word based on the adjusted if_freq*/ | |
| 1572 | pll_freq_word = if_freq; | |
| 1573 | pll_freq_u64 = (u64)pll_freq_word << 28L; | |
| 1574 | do_div(pll_freq_u64, 50000000); | |
| 1575 | pll_freq_word = (u32)pll_freq_u64; | |
| 1576 | /*pll_freq_word = 0x3463497;*/ | |
| 1577 | status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word); | |
| 64fbf444 | 1578 | |
| 955e6ed8 MCC |
1579 | if (spectral_invert) { |
| 1580 | if_freq -= 400000; | |
| 1581 | /* Enable Spectral Invert*/ | |
| 1582 | status = vid_blk_read_word(dev, DIF_MISC_CTRL, | |
| 1583 | &dif_misc_ctrl_value); | |
| 1584 | dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000; | |
| 1585 | status = vid_blk_write_word(dev, DIF_MISC_CTRL, | |
| 1586 | dif_misc_ctrl_value); | |
| 1587 | } else { | |
| 1588 | if_freq += 400000; | |
| 1589 | /* Disable Spectral Invert*/ | |
| 1590 | status = vid_blk_read_word(dev, DIF_MISC_CTRL, | |
| 1591 | &dif_misc_ctrl_value); | |
| 1592 | dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF; | |
| 1593 | status = vid_blk_write_word(dev, DIF_MISC_CTRL, | |
| 1594 | dif_misc_ctrl_value); | |
| 1595 | } | |
| 1596 | ||
| 1597 | if_freq = (if_freq/100000)*100000; | |
| 64fbf444 | 1598 | |
| 955e6ed8 MCC |
1599 | if (if_freq < 3000000) |
| 1600 | if_freq = 3000000; | |
| 64fbf444 | 1601 | |
| 955e6ed8 MCC |
1602 | if (if_freq > 16000000) |
| 1603 | if_freq = 16000000; | |
| 64fbf444 | 1604 | } |
| 64fbf444 | 1605 | |
| 955e6ed8 MCC |
1606 | cx231xx_info("Enter IF=%zd\n", |
| 1607 | sizeof(Dif_set_array)/sizeof(struct dif_settings)); | |
| 1608 | for (i = 0; i < sizeof(Dif_set_array)/sizeof(struct dif_settings); i++) { | |
| 1609 | if (Dif_set_array[i].if_freq == if_freq) { | |
| 1610 | status = vid_blk_write_word(dev, | |
| 1611 | Dif_set_array[i].register_address, Dif_set_array[i].value); | |
| 1612 | } | |
| 1613 | } | |
| e0d3bafd SD |
1614 | } |
| 1615 | ||
| cde4362f MCC |
1616 | /****************************************************************************** |
| 1617 | * D I F - B L O C K C O N T R O L functions * | |
| 1618 | ******************************************************************************/ | |
| e0d3bafd | 1619 | int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, |
| 84b5dbf3 | 1620 | u32 function_mode, u32 standard) |
| e0d3bafd | 1621 | { |
| 84b5dbf3 MCC |
1622 | int status = 0; |
| 1623 | ||
| 64fbf444 | 1624 | |
| 84b5dbf3 MCC |
1625 | if (mode == V4L2_TUNER_RADIO) { |
| 1626 | /* C2HH */ | |
| b9255176 SD |
1627 | /* lo if big signal */ |
| 1628 | status = cx231xx_reg_mask_write(dev, | |
| ecc67d10 | 1629 | VID_BLK_I2C_ADDRESS, 32, |
| b9255176 SD |
1630 | AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); |
| 1631 | /* FUNC_MODE = DIF */ | |
| 1632 | status = cx231xx_reg_mask_write(dev, | |
| ecc67d10 | 1633 | VID_BLK_I2C_ADDRESS, 32, |
| b9255176 SD |
1634 | AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); |
| 1635 | /* IF_MODE */ | |
| 1636 | status = cx231xx_reg_mask_write(dev, | |
| ecc67d10 | 1637 | VID_BLK_I2C_ADDRESS, 32, |
| b9255176 SD |
1638 | AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF); |
| 1639 | /* no inv */ | |
| 1640 | status = cx231xx_reg_mask_write(dev, | |
| ecc67d10 | 1641 | VID_BLK_I2C_ADDRESS, 32, |
| b9255176 | 1642 | AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); |
| 6e4f574b SD |
1643 | } else if (standard != DIF_USE_BASEBAND) { |
| 1644 | if (standard & V4L2_STD_MN) { | |
| b9255176 | 1645 | /* lo if big signal */ |
| cde4362f | 1646 | status = cx231xx_reg_mask_write(dev, |
| ecc67d10 | 1647 | VID_BLK_I2C_ADDRESS, 32, |
| b9255176 SD |
1648 | AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); |
| 1649 | /* FUNC_MODE = DIF */ | |
| cde4362f | 1650 | status = cx231xx_reg_mask_write(dev, |
| ecc67d10 | 1651 | VID_BLK_I2C_ADDRESS, 32, |
| cde4362f | 1652 | AFE_CTRL_C2HH_SRC_CTRL, 23, 24, |
| b9255176 SD |
1653 | function_mode); |
| 1654 | /* IF_MODE */ | |
| cde4362f | 1655 | status = cx231xx_reg_mask_write(dev, |
| ecc67d10 | 1656 | VID_BLK_I2C_ADDRESS, 32, |
| b9255176 SD |
1657 | AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb); |
| 1658 | /* no inv */ | |
| cde4362f | 1659 | status = cx231xx_reg_mask_write(dev, |
| ecc67d10 | 1660 | VID_BLK_I2C_ADDRESS, 32, |
| b9255176 SD |
1661 | AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); |
| 1662 | /* 0x124, AUD_CHAN1_SRC = 0x3 */ | |
| cde4362f | 1663 | status = cx231xx_reg_mask_write(dev, |
| ecc67d10 | 1664 | VID_BLK_I2C_ADDRESS, 32, |
| b9255176 | 1665 | AUD_IO_CTRL, 0, 31, 0x00000003); |
| 6e4f574b | 1666 | } else if ((standard == V4L2_STD_PAL_I) | |
| 64fbf444 | 1667 | (standard & V4L2_STD_PAL_D) | |
| 6e4f574b | 1668 | (standard & V4L2_STD_SECAM)) { |
| 84b5dbf3 | 1669 | /* C2HH setup */ |
| b9255176 | 1670 | /* lo if big signal */ |
| cde4362f | 1671 | status = cx231xx_reg_mask_write(dev, |
| ecc67d10 | 1672 | VID_BLK_I2C_ADDRESS, 32, |
| b9255176 SD |
1673 | AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); |
| 1674 | /* FUNC_MODE = DIF */ | |
| cde4362f | 1675 | status = cx231xx_reg_mask_write(dev, |
| ecc67d10 | 1676 | VID_BLK_I2C_ADDRESS, 32, |
| cde4362f | 1677 | AFE_CTRL_C2HH_SRC_CTRL, 23, 24, |
| b9255176 SD |
1678 | function_mode); |
| 1679 | /* IF_MODE */ | |
| cde4362f | 1680 | status = cx231xx_reg_mask_write(dev, |
| ecc67d10 | 1681 | VID_BLK_I2C_ADDRESS, 32, |
| 6e4f574b | 1682 | AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF); |
| b9255176 | 1683 | /* no inv */ |
| cde4362f | 1684 | status = cx231xx_reg_mask_write(dev, |
| ecc67d10 | 1685 | VID_BLK_I2C_ADDRESS, 32, |
| b9255176 | 1686 | AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); |
| 6e4f574b SD |
1687 | } else { |
| 1688 | /* default PAL BG */ | |
| 84b5dbf3 | 1689 | /* C2HH setup */ |
| b9255176 | 1690 | /* lo if big signal */ |
| cde4362f | 1691 | status = cx231xx_reg_mask_write(dev, |
| ecc67d10 | 1692 | VID_BLK_I2C_ADDRESS, 32, |
| b9255176 SD |
1693 | AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); |
| 1694 | /* FUNC_MODE = DIF */ | |
| cde4362f | 1695 | status = cx231xx_reg_mask_write(dev, |
| ecc67d10 | 1696 | VID_BLK_I2C_ADDRESS, 32, |
| cde4362f | 1697 | AFE_CTRL_C2HH_SRC_CTRL, 23, 24, |
| b9255176 SD |
1698 | function_mode); |
| 1699 | /* IF_MODE */ | |
| cde4362f | 1700 | status = cx231xx_reg_mask_write(dev, |
| ecc67d10 | 1701 | VID_BLK_I2C_ADDRESS, 32, |
| 6e4f574b | 1702 | AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE); |
| b9255176 | 1703 | /* no inv */ |
| cde4362f | 1704 | status = cx231xx_reg_mask_write(dev, |
| ecc67d10 | 1705 | VID_BLK_I2C_ADDRESS, 32, |
| b9255176 | 1706 | AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); |
| 84b5dbf3 MCC |
1707 | } |
| 1708 | } | |
| 1709 | ||
| 1710 | return status; | |
| e0d3bafd SD |
1711 | } |
| 1712 | ||
| 1713 | int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) | |
| 1714 | { | |
| 84b5dbf3 MCC |
1715 | int status = 0; |
| 1716 | u32 dif_misc_ctrl_value = 0; | |
| 1717 | u32 func_mode = 0; | |
| 1718 | ||
| 1719 | cx231xx_info("%s: setStandard to %x\n", __func__, standard); | |
| 1720 | ||
| ecc67d10 | 1721 | status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value); |
| 84b5dbf3 MCC |
1722 | if (standard != DIF_USE_BASEBAND) |
| 1723 | dev->norm = standard; | |
| 1724 | ||
| 1725 | switch (dev->model) { | |
| 64fbf444 | 1726 | case CX231XX_BOARD_CNXT_CARRAERA: |
| 84b5dbf3 | 1727 | case CX231XX_BOARD_CNXT_RDE_250: |
| 64fbf444 | 1728 | case CX231XX_BOARD_CNXT_SHELBY: |
| 84b5dbf3 | 1729 | case CX231XX_BOARD_CNXT_RDU_250: |
| 64fbf444 | 1730 | case CX231XX_BOARD_CNXT_VIDEO_GRABBER: |
| 1a50fdde | 1731 | case CX231XX_BOARD_HAUPPAUGE_EXETER: |
| 84b5dbf3 MCC |
1732 | func_mode = 0x03; |
| 1733 | break; | |
| 64fbf444 PB |
1734 | case CX231XX_BOARD_CNXT_RDE_253S: |
| 1735 | case CX231XX_BOARD_CNXT_RDU_253S: | |
| 1736 | func_mode = 0x01; | |
| 1737 | break; | |
| 84b5dbf3 MCC |
1738 | default: |
| 1739 | func_mode = 0x01; | |
| 1740 | } | |
| 1741 | ||
| cde4362f | 1742 | status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode, |
| 84b5dbf3 MCC |
1743 | func_mode, standard); |
| 1744 | ||
| 1745 | if (standard == DIF_USE_BASEBAND) { /* base band */ | |
| cde4362f MCC |
1746 | /* There is a different SRC_PHASE_INC value |
| 1747 | for baseband vs. DIF */ | |
| ecc67d10 SD |
1748 | status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83); |
| 1749 | status = vid_blk_read_word(dev, DIF_MISC_CTRL, | |
| 1750 | &dif_misc_ctrl_value); | |
| 84b5dbf3 | 1751 | dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS; |
| ecc67d10 SD |
1752 | status = vid_blk_write_word(dev, DIF_MISC_CTRL, |
| 1753 | dif_misc_ctrl_value); | |
| 84b5dbf3 | 1754 | } else if (standard & V4L2_STD_PAL_D) { |
| ecc67d10 | 1755 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1756 | DIF_PLL_CTRL, 0, 31, 0x6503bc0c); |
| ecc67d10 | 1757 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1758 | DIF_PLL_CTRL1, 0, 31, 0xbd038c85); |
| ecc67d10 | 1759 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1760 | DIF_PLL_CTRL2, 0, 31, 0x1db4640a); |
| ecc67d10 | 1761 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1762 | DIF_PLL_CTRL3, 0, 31, 0x00008800); |
| ecc67d10 | 1763 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1764 | DIF_AGC_IF_REF, 0, 31, 0x444C1380); |
| ecc67d10 | 1765 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1766 | DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); |
| ecc67d10 | 1767 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1768 | DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); |
| ecc67d10 | 1769 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1770 | DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); |
| ecc67d10 | 1771 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 MCC |
1772 | DIF_AGC_IF_INT_CURRENT, 0, 31, |
| 1773 | 0x26001700); | |
| ecc67d10 | 1774 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 MCC |
1775 | DIF_AGC_RF_CURRENT, 0, 31, |
| 1776 | 0x00002660); | |
| ecc67d10 | 1777 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 MCC |
1778 | DIF_VIDEO_AGC_CTRL, 0, 31, |
| 1779 | 0x72500800); | |
| ecc67d10 | 1780 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 MCC |
1781 | DIF_VID_AUD_OVERRIDE, 0, 31, |
| 1782 | 0x27000100); | |
| ecc67d10 | 1783 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1784 | DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA); |
| ecc67d10 | 1785 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 MCC |
1786 | DIF_COMP_FLT_CTRL, 0, 31, |
| 1787 | 0x00000000); | |
| ecc67d10 | 1788 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 MCC |
1789 | DIF_SRC_PHASE_INC, 0, 31, |
| 1790 | 0x1befbf06); | |
| ecc67d10 | 1791 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 MCC |
1792 | DIF_SRC_GAIN_CONTROL, 0, 31, |
| 1793 | 0x000035e8); | |
| ecc67d10 | 1794 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 MCC |
1795 | DIF_RPT_VARIANCE, 0, 31, 0x00000000); |
| 1796 | /* Save the Spec Inversion value */ | |
| 1797 | dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; | |
| 1798 | dif_misc_ctrl_value |= 0x3a023F11; | |
| 84b5dbf3 | 1799 | } else if (standard & V4L2_STD_PAL_I) { |
| ecc67d10 | 1800 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1801 | DIF_PLL_CTRL, 0, 31, 0x6503bc0c); |
| ecc67d10 | 1802 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1803 | DIF_PLL_CTRL1, 0, 31, 0xbd038c85); |
| ecc67d10 | 1804 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1805 | DIF_PLL_CTRL2, 0, 31, 0x1db4640a); |
| ecc67d10 | 1806 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1807 | DIF_PLL_CTRL3, 0, 31, 0x00008800); |
| ecc67d10 | 1808 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1809 | DIF_AGC_IF_REF, 0, 31, 0x444C1380); |
| ecc67d10 | 1810 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1811 | DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); |
| ecc67d10 | 1812 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1813 | DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); |
| ecc67d10 | 1814 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1815 | DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); |
| ecc67d10 | 1816 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 MCC |
1817 | DIF_AGC_IF_INT_CURRENT, 0, 31, |
| 1818 | 0x26001700); | |
| ecc67d10 | 1819 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 MCC |
1820 | DIF_AGC_RF_CURRENT, 0, 31, |
| 1821 | 0x00002660); | |
| ecc67d10 | 1822 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 MCC |
1823 | DIF_VIDEO_AGC_CTRL, 0, 31, |
| 1824 | 0x72500800); | |
| ecc67d10 | 1825 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 MCC |
1826 | DIF_VID_AUD_OVERRIDE, 0, 31, |
| 1827 | 0x27000100); | |
| ecc67d10 | 1828 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1829 | DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934); |
| ecc67d10 | 1830 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 MCC |
1831 | DIF_COMP_FLT_CTRL, 0, 31, |
| 1832 | 0x00000000); | |
| ecc67d10 | 1833 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 MCC |
1834 | DIF_SRC_PHASE_INC, 0, 31, |
| 1835 | 0x1befbf06); | |
| ecc67d10 | 1836 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 MCC |
1837 | DIF_SRC_GAIN_CONTROL, 0, 31, |
| 1838 | 0x000035e8); | |
| ecc67d10 | 1839 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 MCC |
1840 | DIF_RPT_VARIANCE, 0, 31, 0x00000000); |
| 1841 | /* Save the Spec Inversion value */ | |
| 1842 | dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; | |
| 1843 | dif_misc_ctrl_value |= 0x3a033F11; | |
| 84b5dbf3 | 1844 | } else if (standard & V4L2_STD_PAL_M) { |
| 84b5dbf3 | 1845 | /* improved Low Frequency Phase Noise */ |
| ecc67d10 SD |
1846 | status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C); |
| 1847 | status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85); | |
| 1848 | status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a); | |
| 1849 | status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); | |
| 1850 | status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380); | |
| 1851 | status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, | |
| 1852 | 0x26001700); | |
| 1853 | status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, | |
| 1854 | 0x00002660); | |
| 1855 | status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, | |
| 1856 | 0x72500800); | |
| 1857 | status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, | |
| 1858 | 0x27000100); | |
| 1859 | status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d); | |
| 1860 | status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, | |
| 1861 | 0x009f50c1); | |
| 1862 | status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, | |
| 1863 | 0x1befbf06); | |
| 1864 | status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, | |
| 1865 | 0x000035e8); | |
| 1866 | status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB, | |
| 1867 | 0x00000000); | |
| 84b5dbf3 MCC |
1868 | /* Save the Spec Inversion value */ |
| 1869 | dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; | |
| 1870 | dif_misc_ctrl_value |= 0x3A0A3F10; | |
| 84b5dbf3 | 1871 | } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) { |
| 84b5dbf3 | 1872 | /* improved Low Frequency Phase Noise */ |
| ecc67d10 SD |
1873 | status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C); |
| 1874 | status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85); | |
| 1875 | status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a); | |
| 1876 | status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); | |
| 1877 | status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380); | |
| 1878 | status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, | |
| 1879 | 0x26001700); | |
| 1880 | status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, | |
| 1881 | 0x00002660); | |
| 1882 | status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, | |
| 1883 | 0x72500800); | |
| 1884 | status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, | |
| 1885 | 0x27000100); | |
| 1886 | status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, | |
| 1887 | 0x012c405d); | |
| 1888 | status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, | |
| 1889 | 0x009f50c1); | |
| 1890 | status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, | |
| 1891 | 0x1befbf06); | |
| 1892 | status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, | |
| 1893 | 0x000035e8); | |
| 1894 | status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB, | |
| 1895 | 0x00000000); | |
| 84b5dbf3 MCC |
1896 | /* Save the Spec Inversion value */ |
| 1897 | dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; | |
| 1898 | dif_misc_ctrl_value = 0x3A093F10; | |
| 84b5dbf3 | 1899 | } else if (standard & |
| 6e4f574b SD |
1900 | (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G | |
| 1901 | V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) { | |
| 84b5dbf3 | 1902 | |
| ecc67d10 | 1903 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1904 | DIF_PLL_CTRL, 0, 31, 0x6503bc0c); |
| ecc67d10 | 1905 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1906 | DIF_PLL_CTRL1, 0, 31, 0xbd038c85); |
| ecc67d10 | 1907 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1908 | DIF_PLL_CTRL2, 0, 31, 0x1db4640a); |
| ecc67d10 | 1909 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1910 | DIF_PLL_CTRL3, 0, 31, 0x00008800); |
| ecc67d10 | 1911 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1912 | DIF_AGC_IF_REF, 0, 31, 0x888C0380); |
| ecc67d10 | 1913 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1914 | DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); |
| ecc67d10 | 1915 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1916 | DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); |
| ecc67d10 | 1917 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1918 | DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); |
| ecc67d10 | 1919 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 MCC |
1920 | DIF_AGC_IF_INT_CURRENT, 0, 31, |
| 1921 | 0x26001700); | |
| ecc67d10 | 1922 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 MCC |
1923 | DIF_AGC_RF_CURRENT, 0, 31, |
| 1924 | 0x00002660); | |
| ecc67d10 | 1925 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 MCC |
1926 | DIF_VID_AUD_OVERRIDE, 0, 31, |
| 1927 | 0x27000100); | |
| ecc67d10 | 1928 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1929 | DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); |
| ecc67d10 | 1930 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 MCC |
1931 | DIF_COMP_FLT_CTRL, 0, 31, |
| 1932 | 0x00000000); | |
| ecc67d10 | 1933 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 MCC |
1934 | DIF_SRC_PHASE_INC, 0, 31, |
| 1935 | 0x1befbf06); | |
| ecc67d10 | 1936 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 MCC |
1937 | DIF_SRC_GAIN_CONTROL, 0, 31, |
| 1938 | 0x000035e8); | |
| ecc67d10 | 1939 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1940 | DIF_RPT_VARIANCE, 0, 31, 0x00000000); |
| ecc67d10 | 1941 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 MCC |
1942 | DIF_VIDEO_AGC_CTRL, 0, 31, |
| 1943 | 0xf4000000); | |
| 1944 | ||
| 1945 | /* Save the Spec Inversion value */ | |
| 1946 | dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; | |
| 1947 | dif_misc_ctrl_value |= 0x3a023F11; | |
| 84b5dbf3 | 1948 | } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) { |
| 84b5dbf3 | 1949 | /* Is it SECAM_L1? */ |
| ecc67d10 | 1950 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1951 | DIF_PLL_CTRL, 0, 31, 0x6503bc0c); |
| ecc67d10 | 1952 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1953 | DIF_PLL_CTRL1, 0, 31, 0xbd038c85); |
| ecc67d10 | 1954 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1955 | DIF_PLL_CTRL2, 0, 31, 0x1db4640a); |
| ecc67d10 | 1956 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1957 | DIF_PLL_CTRL3, 0, 31, 0x00008800); |
| ecc67d10 | 1958 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1959 | DIF_AGC_IF_REF, 0, 31, 0x888C0380); |
| ecc67d10 | 1960 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1961 | DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); |
| ecc67d10 | 1962 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1963 | DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); |
| ecc67d10 | 1964 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1965 | DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); |
| ecc67d10 | 1966 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 MCC |
1967 | DIF_AGC_IF_INT_CURRENT, 0, 31, |
| 1968 | 0x26001700); | |
| ecc67d10 | 1969 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 MCC |
1970 | DIF_AGC_RF_CURRENT, 0, 31, |
| 1971 | 0x00002660); | |
| ecc67d10 | 1972 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 MCC |
1973 | DIF_VID_AUD_OVERRIDE, 0, 31, |
| 1974 | 0x27000100); | |
| ecc67d10 | 1975 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1976 | DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); |
| ecc67d10 | 1977 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 MCC |
1978 | DIF_COMP_FLT_CTRL, 0, 31, |
| 1979 | 0x00000000); | |
| ecc67d10 | 1980 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 MCC |
1981 | DIF_SRC_PHASE_INC, 0, 31, |
| 1982 | 0x1befbf06); | |
| ecc67d10 | 1983 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 MCC |
1984 | DIF_SRC_GAIN_CONTROL, 0, 31, |
| 1985 | 0x000035e8); | |
| ecc67d10 | 1986 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 | 1987 | DIF_RPT_VARIANCE, 0, 31, 0x00000000); |
| ecc67d10 | 1988 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 84b5dbf3 MCC |
1989 | DIF_VIDEO_AGC_CTRL, 0, 31, |
| 1990 | 0xf2560000); | |
| 1991 | ||
| 1992 | /* Save the Spec Inversion value */ | |
| 1993 | dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; | |
| 1994 | dif_misc_ctrl_value |= 0x3a023F11; | |
| 1995 | ||
| 6e4f574b | 1996 | } else if (standard & V4L2_STD_NTSC_M) { |
| cde4362f MCC |
1997 | /* V4L2_STD_NTSC_M (75 IRE Setup) Or |
| 1998 | V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */ | |
| 84b5dbf3 | 1999 | |
| cde4362f MCC |
2000 | /* For NTSC the centre frequency of video coming out of |
| 2001 | sidewinder is around 7.1MHz or 3.6MHz depending on the | |
| 2002 | spectral inversion. so for a non spectrally inverted channel | |
| 2003 | the pll freq word is 0x03420c49 | |
| 84b5dbf3 MCC |
2004 | */ |
| 2005 | ||
| ecc67d10 SD |
2006 | status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C); |
| 2007 | status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85); | |
| 2008 | status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A); | |
| 2009 | status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); | |
| 2010 | status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380); | |
| 2011 | status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, | |
| 2012 | 0x26001700); | |
| 2013 | status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, | |
| 2014 | 0x00002660); | |
| 2015 | status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, | |
| 2016 | 0x04000800); | |
| 2017 | status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, | |
| 2018 | 0x27000100); | |
| 2019 | status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f); | |
| 2020 | ||
| 2021 | status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, | |
| 2022 | 0x009f50c1); | |
| 2023 | status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, | |
| 2024 | 0x1befbf06); | |
| 2025 | status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, | |
| 2026 | 0x000035e8); | |
| 2027 | ||
| 2028 | status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600); | |
| 2029 | status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT, | |
| 2030 | 0xC2262600); | |
| 2031 | status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600); | |
| 84b5dbf3 MCC |
2032 | |
| 2033 | /* Save the Spec Inversion value */ | |
| 2034 | dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; | |
| 2035 | dif_misc_ctrl_value |= 0x3a003F10; | |
| 6e4f574b SD |
2036 | } else { |
| 2037 | /* default PAL BG */ | |
| ecc67d10 | 2038 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 6e4f574b | 2039 | DIF_PLL_CTRL, 0, 31, 0x6503bc0c); |
| ecc67d10 | 2040 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 6e4f574b | 2041 | DIF_PLL_CTRL1, 0, 31, 0xbd038c85); |
| ecc67d10 | 2042 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 6e4f574b | 2043 | DIF_PLL_CTRL2, 0, 31, 0x1db4640a); |
| ecc67d10 | 2044 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 6e4f574b | 2045 | DIF_PLL_CTRL3, 0, 31, 0x00008800); |
| ecc67d10 | 2046 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 6e4f574b | 2047 | DIF_AGC_IF_REF, 0, 31, 0x444C1380); |
| ecc67d10 | 2048 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 6e4f574b | 2049 | DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); |
| ecc67d10 | 2050 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 6e4f574b | 2051 | DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); |
| ecc67d10 | 2052 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 6e4f574b | 2053 | DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); |
| ecc67d10 | 2054 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 6e4f574b SD |
2055 | DIF_AGC_IF_INT_CURRENT, 0, 31, |
| 2056 | 0x26001700); | |
| ecc67d10 | 2057 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 6e4f574b SD |
2058 | DIF_AGC_RF_CURRENT, 0, 31, |
| 2059 | 0x00002660); | |
| ecc67d10 | 2060 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 6e4f574b SD |
2061 | DIF_VIDEO_AGC_CTRL, 0, 31, |
| 2062 | 0x72500800); | |
| ecc67d10 | 2063 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 6e4f574b SD |
2064 | DIF_VID_AUD_OVERRIDE, 0, 31, |
| 2065 | 0x27000100); | |
| ecc67d10 | 2066 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 6e4f574b | 2067 | DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC); |
| ecc67d10 | 2068 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 6e4f574b SD |
2069 | DIF_COMP_FLT_CTRL, 0, 31, |
| 2070 | 0x00A653A8); | |
| ecc67d10 | 2071 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 6e4f574b SD |
2072 | DIF_SRC_PHASE_INC, 0, 31, |
| 2073 | 0x1befbf06); | |
| ecc67d10 | 2074 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 6e4f574b SD |
2075 | DIF_SRC_GAIN_CONTROL, 0, 31, |
| 2076 | 0x000035e8); | |
| ecc67d10 | 2077 | status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, |
| 6e4f574b SD |
2078 | DIF_RPT_VARIANCE, 0, 31, 0x00000000); |
| 2079 | /* Save the Spec Inversion value */ | |
| 2080 | dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; | |
| 2081 | dif_misc_ctrl_value |= 0x3a013F11; | |
| 84b5dbf3 MCC |
2082 | } |
| 2083 | ||
| 2084 | /* The AGC values should be the same for all standards, | |
| 2085 | AUD_SRC_SEL[19] should always be disabled */ | |
| 2086 | dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL; | |
| 2087 | ||
| cde4362f MCC |
2088 | /* It is still possible to get Set Standard calls even when we |
| 2089 | are in FM mode. | |
| 84b5dbf3 MCC |
2090 | This is done to override the value for FM. */ |
| 2091 | if (dev->active_mode == V4L2_TUNER_RADIO) | |
| 2092 | dif_misc_ctrl_value = 0x7a080000; | |
| 2093 | ||
| 2094 | /* Write the calculated value for misc ontrol register */ | |
| ecc67d10 | 2095 | status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value); |
| 84b5dbf3 MCC |
2096 | |
| 2097 | return status; | |
| e0d3bafd SD |
2098 | } |
| 2099 | ||
| 2100 | int cx231xx_tuner_pre_channel_change(struct cx231xx *dev) | |
| 2101 | { | |
| 2102 | int status = 0; | |
| 2103 | u32 dwval; | |
| 2104 | ||
| 2105 | /* Set the RF and IF k_agc values to 3 */ | |
| ecc67d10 | 2106 | status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval); |
| e0d3bafd SD |
2107 | dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); |
| 2108 | dwval |= 0x33000000; | |
| 2109 | ||
| ecc67d10 | 2110 | status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval); |
| e0d3bafd | 2111 | |
| 84b5dbf3 | 2112 | return status; |
| e0d3bafd SD |
2113 | } |
| 2114 | ||
| 2115 | int cx231xx_tuner_post_channel_change(struct cx231xx *dev) | |
| 2116 | { | |
| 84b5dbf3 | 2117 | int status = 0; |
| e0d3bafd | 2118 | u32 dwval; |
| 955e6ed8 MCC |
2119 | cx231xx_info("cx231xx_tuner_post_channel_change dev->tuner_type =0%d\n", |
| 2120 | dev->tuner_type); | |
| 6e4f574b SD |
2121 | /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for |
| 2122 | * SECAM L/B/D standards */ | |
| ecc67d10 | 2123 | status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval); |
| 84b5dbf3 | 2124 | dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); |
| e0d3bafd | 2125 | |
| cde4362f | 2126 | if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B | |
| 64fbf444 PB |
2127 | V4L2_STD_SECAM_D)) { |
| 2128 | if (dev->tuner_type == TUNER_NXP_TDA18271) { | |
| 2129 | dwval &= ~FLD_DIF_IF_REF; | |
| 2130 | dwval |= 0x88000300; | |
| 2131 | } else | |
| 2132 | dwval |= 0x88000000; | |
| 2133 | } else { | |
| 2134 | if (dev->tuner_type == TUNER_NXP_TDA18271) { | |
| 2135 | dwval &= ~FLD_DIF_IF_REF; | |
| 2136 | dwval |= 0xCC000300; | |
| 2137 | } else | |
| 2138 | dwval |= 0x44000000; | |
| 2139 | } | |
| e0d3bafd | 2140 | |
| ecc67d10 | 2141 | status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval); |
| e0d3bafd | 2142 | |
| 84b5dbf3 | 2143 | return status; |
| e0d3bafd SD |
2144 | } |
| 2145 | ||
| cde4362f | 2146 | /****************************************************************************** |
| ecc67d10 | 2147 | * I 2 S - B L O C K C O N T R O L functions * |
| cde4362f | 2148 | ******************************************************************************/ |
| ecc67d10 | 2149 | int cx231xx_i2s_blk_initialize(struct cx231xx *dev) |
| e0d3bafd | 2150 | { |
| 84b5dbf3 MCC |
2151 | int status = 0; |
| 2152 | u32 value; | |
| 2153 | ||
| ecc67d10 | 2154 | status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, |
| cde4362f | 2155 | CH_PWR_CTRL1, 1, &value, 1); |
| 84b5dbf3 MCC |
2156 | /* enables clock to delta-sigma and decimation filter */ |
| 2157 | value |= 0x80; | |
| ecc67d10 | 2158 | status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, |
| 84b5dbf3 MCC |
2159 | CH_PWR_CTRL1, 1, value, 1); |
| 2160 | /* power up all channel */ | |
| ecc67d10 | 2161 | status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, |
| 84b5dbf3 MCC |
2162 | CH_PWR_CTRL2, 1, 0x00, 1); |
| 2163 | ||
| 2164 | return status; | |
| e0d3bafd SD |
2165 | } |
| 2166 | ||
| ecc67d10 | 2167 | int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev, |
| 6e4f574b | 2168 | enum AV_MODE avmode) |
| e0d3bafd | 2169 | { |
| 84b5dbf3 MCC |
2170 | int status = 0; |
| 2171 | u32 value = 0; | |
| 2172 | ||
| 2173 | if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) { | |
| ecc67d10 | 2174 | status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, |
| 84b5dbf3 MCC |
2175 | CH_PWR_CTRL2, 1, &value, 1); |
| 2176 | value |= 0xfe; | |
| ecc67d10 | 2177 | status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, |
| 84b5dbf3 MCC |
2178 | CH_PWR_CTRL2, 1, value, 1); |
| 2179 | } else { | |
| ecc67d10 | 2180 | status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, |
| 84b5dbf3 MCC |
2181 | CH_PWR_CTRL2, 1, 0x00, 1); |
| 2182 | } | |
| 2183 | ||
| 2184 | return status; | |
| e0d3bafd SD |
2185 | } |
| 2186 | ||
| ecc67d10 SD |
2187 | /* set i2s_blk for audio input types */ |
| 2188 | int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input) | |
| e0d3bafd | 2189 | { |
| 84b5dbf3 | 2190 | int status = 0; |
| e0d3bafd | 2191 | |
| 84b5dbf3 MCC |
2192 | switch (audio_input) { |
| 2193 | case CX231XX_AMUX_LINE_IN: | |
| ecc67d10 | 2194 | status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, |
| 84b5dbf3 | 2195 | CH_PWR_CTRL2, 1, 0x00, 1); |
| ecc67d10 | 2196 | status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, |
| 84b5dbf3 MCC |
2197 | CH_PWR_CTRL1, 1, 0x80, 1); |
| 2198 | break; | |
| 2199 | case CX231XX_AMUX_VIDEO: | |
| 2200 | default: | |
| 2201 | break; | |
| 2202 | } | |
| e0d3bafd | 2203 | |
| 84b5dbf3 | 2204 | dev->ctl_ainput = audio_input; |
| e0d3bafd | 2205 | |
| 84b5dbf3 | 2206 | return status; |
| e0d3bafd SD |
2207 | } |
| 2208 | ||
| cde4362f MCC |
2209 | /****************************************************************************** |
| 2210 | * P O W E R C O N T R O L functions * | |
| 2211 | ******************************************************************************/ | |
| 6e4f574b | 2212 | int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode) |
| e0d3bafd | 2213 | { |
| 84b5dbf3 MCC |
2214 | u8 value[4] = { 0, 0, 0, 0 }; |
| 2215 | u32 tmp = 0; | |
| 2216 | int status = 0; | |
| 2217 | ||
| 2218 | if (dev->power_mode != mode) | |
| 2219 | dev->power_mode = mode; | |
| 2220 | else { | |
| 2221 | cx231xx_info(" setPowerMode::mode = %d, No Change req.\n", | |
| 2222 | mode); | |
| 2223 | return 0; | |
| 2224 | } | |
| 2225 | ||
| cde4362f MCC |
2226 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, |
| 2227 | 4); | |
| 84b5dbf3 MCC |
2228 | if (status < 0) |
| 2229 | return status; | |
| 2230 | ||
| 2231 | tmp = *((u32 *) value); | |
| 2232 | ||
| 2233 | switch (mode) { | |
| 2234 | case POLARIS_AVMODE_ENXTERNAL_AV: | |
| 2235 | ||
| 2236 | tmp &= (~PWR_MODE_MASK); | |
| 2237 | ||
| 2238 | tmp |= PWR_AV_EN; | |
| 2239 | value[0] = (u8) tmp; | |
| 2240 | value[1] = (u8) (tmp >> 8); | |
| 2241 | value[2] = (u8) (tmp >> 16); | |
| 2242 | value[3] = (u8) (tmp >> 24); | |
| cde4362f MCC |
2243 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 2244 | PWR_CTL_EN, value, 4); | |
| 84b5dbf3 MCC |
2245 | msleep(PWR_SLEEP_INTERVAL); |
| 2246 | ||
| 2247 | tmp |= PWR_ISO_EN; | |
| 2248 | value[0] = (u8) tmp; | |
| 2249 | value[1] = (u8) (tmp >> 8); | |
| 2250 | value[2] = (u8) (tmp >> 16); | |
| 2251 | value[3] = (u8) (tmp >> 24); | |
| 2252 | status = | |
| 2253 | cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, | |
| 2254 | value, 4); | |
| 2255 | msleep(PWR_SLEEP_INTERVAL); | |
| 2256 | ||
| 2257 | tmp |= POLARIS_AVMODE_ENXTERNAL_AV; | |
| 2258 | value[0] = (u8) tmp; | |
| 2259 | value[1] = (u8) (tmp >> 8); | |
| 2260 | value[2] = (u8) (tmp >> 16); | |
| 2261 | value[3] = (u8) (tmp >> 24); | |
| cde4362f MCC |
2262 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 2263 | PWR_CTL_EN, value, 4); | |
| 84b5dbf3 | 2264 | |
| b9255176 SD |
2265 | /* reset state of xceive tuner */ |
| 2266 | dev->xc_fw_load_done = 0; | |
| 84b5dbf3 MCC |
2267 | break; |
| 2268 | ||
| 2269 | case POLARIS_AVMODE_ANALOGT_TV: | |
| 2270 | ||
| 64fbf444 | 2271 | tmp |= PWR_DEMOD_EN; |
| 84b5dbf3 MCC |
2272 | tmp |= (I2C_DEMOD_EN); |
| 2273 | value[0] = (u8) tmp; | |
| 2274 | value[1] = (u8) (tmp >> 8); | |
| 2275 | value[2] = (u8) (tmp >> 16); | |
| 2276 | value[3] = (u8) (tmp >> 24); | |
| cde4362f MCC |
2277 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 2278 | PWR_CTL_EN, value, 4); | |
| 84b5dbf3 MCC |
2279 | msleep(PWR_SLEEP_INTERVAL); |
| 2280 | ||
| 2281 | if (!(tmp & PWR_TUNER_EN)) { | |
| 2282 | tmp |= (PWR_TUNER_EN); | |
| 2283 | value[0] = (u8) tmp; | |
| 2284 | value[1] = (u8) (tmp >> 8); | |
| 2285 | value[2] = (u8) (tmp >> 16); | |
| 2286 | value[3] = (u8) (tmp >> 24); | |
| cde4362f MCC |
2287 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 2288 | PWR_CTL_EN, value, 4); | |
| 84b5dbf3 MCC |
2289 | msleep(PWR_SLEEP_INTERVAL); |
| 2290 | } | |
| 2291 | ||
| 2292 | if (!(tmp & PWR_AV_EN)) { | |
| 2293 | tmp |= PWR_AV_EN; | |
| 2294 | value[0] = (u8) tmp; | |
| 2295 | value[1] = (u8) (tmp >> 8); | |
| 2296 | value[2] = (u8) (tmp >> 16); | |
| 2297 | value[3] = (u8) (tmp >> 24); | |
| cde4362f MCC |
2298 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 2299 | PWR_CTL_EN, value, 4); | |
| 84b5dbf3 MCC |
2300 | msleep(PWR_SLEEP_INTERVAL); |
| 2301 | } | |
| 2302 | if (!(tmp & PWR_ISO_EN)) { | |
| 2303 | tmp |= PWR_ISO_EN; | |
| 2304 | value[0] = (u8) tmp; | |
| 2305 | value[1] = (u8) (tmp >> 8); | |
| 2306 | value[2] = (u8) (tmp >> 16); | |
| 2307 | value[3] = (u8) (tmp >> 24); | |
| cde4362f MCC |
2308 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 2309 | PWR_CTL_EN, value, 4); | |
| 84b5dbf3 MCC |
2310 | msleep(PWR_SLEEP_INTERVAL); |
| 2311 | } | |
| 2312 | ||
| 2313 | if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) { | |
| 2314 | tmp |= POLARIS_AVMODE_ANALOGT_TV; | |
| 2315 | value[0] = (u8) tmp; | |
| 2316 | value[1] = (u8) (tmp >> 8); | |
| 2317 | value[2] = (u8) (tmp >> 16); | |
| 2318 | value[3] = (u8) (tmp >> 24); | |
| cde4362f MCC |
2319 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 2320 | PWR_CTL_EN, value, 4); | |
| 84b5dbf3 MCC |
2321 | msleep(PWR_SLEEP_INTERVAL); |
| 2322 | } | |
| 2323 | ||
| a6f6fb9c MCC |
2324 | if (dev->board.tuner_type != TUNER_ABSENT) { |
| 2325 | /* Enable tuner */ | |
| 2326 | cx231xx_enable_i2c_port_3(dev, true); | |
| 84b5dbf3 | 2327 | |
| 64fbf444 | 2328 | /* reset the Tuner */ |
| a6f6fb9c MCC |
2329 | if (dev->board.tuner_gpio) |
| 2330 | cx231xx_gpio_set(dev, dev->board.tuner_gpio); | |
| 64fbf444 | 2331 | |
| 84b5dbf3 MCC |
2332 | if (dev->cx231xx_reset_analog_tuner) |
| 2333 | dev->cx231xx_reset_analog_tuner(dev); | |
| 2334 | } | |
| 64fbf444 | 2335 | |
| 84b5dbf3 MCC |
2336 | break; |
| 2337 | ||
| 2338 | case POLARIS_AVMODE_DIGITAL: | |
| 84b5dbf3 MCC |
2339 | if (!(tmp & PWR_TUNER_EN)) { |
| 2340 | tmp |= (PWR_TUNER_EN); | |
| 2341 | value[0] = (u8) tmp; | |
| 2342 | value[1] = (u8) (tmp >> 8); | |
| 2343 | value[2] = (u8) (tmp >> 16); | |
| 2344 | value[3] = (u8) (tmp >> 24); | |
| cde4362f MCC |
2345 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 2346 | PWR_CTL_EN, value, 4); | |
| 84b5dbf3 MCC |
2347 | msleep(PWR_SLEEP_INTERVAL); |
| 2348 | } | |
| 2349 | if (!(tmp & PWR_AV_EN)) { | |
| 2350 | tmp |= PWR_AV_EN; | |
| 2351 | value[0] = (u8) tmp; | |
| 2352 | value[1] = (u8) (tmp >> 8); | |
| 2353 | value[2] = (u8) (tmp >> 16); | |
| 2354 | value[3] = (u8) (tmp >> 24); | |
| cde4362f MCC |
2355 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 2356 | PWR_CTL_EN, value, 4); | |
| 84b5dbf3 MCC |
2357 | msleep(PWR_SLEEP_INTERVAL); |
| 2358 | } | |
| 2359 | if (!(tmp & PWR_ISO_EN)) { | |
| 2360 | tmp |= PWR_ISO_EN; | |
| 2361 | value[0] = (u8) tmp; | |
| 2362 | value[1] = (u8) (tmp >> 8); | |
| 2363 | value[2] = (u8) (tmp >> 16); | |
| 2364 | value[3] = (u8) (tmp >> 24); | |
| cde4362f MCC |
2365 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 2366 | PWR_CTL_EN, value, 4); | |
| 84b5dbf3 MCC |
2367 | msleep(PWR_SLEEP_INTERVAL); |
| 2368 | } | |
| 2369 | ||
| cc355753 | 2370 | tmp &= (~PWR_AV_MODE); |
| 84b5dbf3 MCC |
2371 | tmp |= POLARIS_AVMODE_DIGITAL | I2C_DEMOD_EN; |
| 2372 | value[0] = (u8) tmp; | |
| 2373 | value[1] = (u8) (tmp >> 8); | |
| 2374 | value[2] = (u8) (tmp >> 16); | |
| 2375 | value[3] = (u8) (tmp >> 24); | |
| cde4362f MCC |
2376 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 2377 | PWR_CTL_EN, value, 4); | |
| 84b5dbf3 MCC |
2378 | msleep(PWR_SLEEP_INTERVAL); |
| 2379 | ||
| 2380 | if (!(tmp & PWR_DEMOD_EN)) { | |
| 2381 | tmp |= PWR_DEMOD_EN; | |
| 2382 | value[0] = (u8) tmp; | |
| 2383 | value[1] = (u8) (tmp >> 8); | |
| 2384 | value[2] = (u8) (tmp >> 16); | |
| 2385 | value[3] = (u8) (tmp >> 24); | |
| cde4362f MCC |
2386 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 2387 | PWR_CTL_EN, value, 4); | |
| 84b5dbf3 MCC |
2388 | msleep(PWR_SLEEP_INTERVAL); |
| 2389 | } | |
| 2390 | ||
| a6f6fb9c MCC |
2391 | if (dev->board.tuner_type != TUNER_ABSENT) { |
| 2392 | /* | |
| 2393 | * Enable tuner | |
| 2394 | * Hauppauge Exeter seems to need to do something different! | |
| 2395 | */ | |
| 2396 | if (dev->model == CX231XX_BOARD_HAUPPAUGE_EXETER) | |
| 2397 | cx231xx_enable_i2c_port_3(dev, false); | |
| 2398 | else | |
| 2399 | cx231xx_enable_i2c_port_3(dev, true); | |
| 84b5dbf3 | 2400 | |
| 64fbf444 | 2401 | /* reset the Tuner */ |
| a6f6fb9c MCC |
2402 | if (dev->board.tuner_gpio) |
| 2403 | cx231xx_gpio_set(dev, dev->board.tuner_gpio); | |
| 1a50fdde | 2404 | |
| 84b5dbf3 MCC |
2405 | if (dev->cx231xx_reset_analog_tuner) |
| 2406 | dev->cx231xx_reset_analog_tuner(dev); | |
| 2407 | } | |
| 2408 | break; | |
| 2409 | ||
| 2410 | default: | |
| 2411 | break; | |
| 2412 | } | |
| 2413 | ||
| 2414 | msleep(PWR_SLEEP_INTERVAL); | |
| 2415 | ||
| cde4362f MCC |
2416 | /* For power saving, only enable Pwr_resetout_n |
| 2417 | when digital TV is selected. */ | |
| 84b5dbf3 MCC |
2418 | if (mode == POLARIS_AVMODE_DIGITAL) { |
| 2419 | tmp |= PWR_RESETOUT_EN; | |
| 2420 | value[0] = (u8) tmp; | |
| 2421 | value[1] = (u8) (tmp >> 8); | |
| 2422 | value[2] = (u8) (tmp >> 16); | |
| 2423 | value[3] = (u8) (tmp >> 24); | |
| cde4362f MCC |
2424 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, |
| 2425 | PWR_CTL_EN, value, 4); | |
| 84b5dbf3 MCC |
2426 | msleep(PWR_SLEEP_INTERVAL); |
| 2427 | } | |
| 2428 | ||
| ecc67d10 SD |
2429 | /* update power control for afe */ |
| 2430 | status = cx231xx_afe_update_power_control(dev, mode); | |
| 84b5dbf3 | 2431 | |
| ecc67d10 SD |
2432 | /* update power control for i2s_blk */ |
| 2433 | status = cx231xx_i2s_blk_update_power_control(dev, mode); | |
| 84b5dbf3 | 2434 | |
| cde4362f MCC |
2435 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, |
| 2436 | 4); | |
| 84b5dbf3 MCC |
2437 | |
| 2438 | return status; | |
| e0d3bafd SD |
2439 | } |
| 2440 | ||
| 2441 | int cx231xx_power_suspend(struct cx231xx *dev) | |
| 2442 | { | |
| 84b5dbf3 MCC |
2443 | u8 value[4] = { 0, 0, 0, 0 }; |
| 2444 | u32 tmp = 0; | |
| 2445 | int status = 0; | |
| e0d3bafd | 2446 | |
| cde4362f MCC |
2447 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, |
| 2448 | value, 4); | |
| 84b5dbf3 MCC |
2449 | if (status > 0) |
| 2450 | return status; | |
| e0d3bafd | 2451 | |
| 84b5dbf3 MCC |
2452 | tmp = *((u32 *) value); |
| 2453 | tmp &= (~PWR_MODE_MASK); | |
| e0d3bafd | 2454 | |
| 84b5dbf3 MCC |
2455 | value[0] = (u8) tmp; |
| 2456 | value[1] = (u8) (tmp >> 8); | |
| 2457 | value[2] = (u8) (tmp >> 16); | |
| 2458 | value[3] = (u8) (tmp >> 24); | |
| cde4362f MCC |
2459 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, |
| 2460 | value, 4); | |
| e0d3bafd | 2461 | |
| 84b5dbf3 | 2462 | return status; |
| e0d3bafd SD |
2463 | } |
| 2464 | ||
| cde4362f MCC |
2465 | /****************************************************************************** |
| 2466 | * S T R E A M C O N T R O L functions * | |
| 2467 | ******************************************************************************/ | |
| e0d3bafd SD |
2468 | int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask) |
| 2469 | { | |
| 84b5dbf3 MCC |
2470 | u8 value[4] = { 0x0, 0x0, 0x0, 0x0 }; |
| 2471 | u32 tmp = 0; | |
| 2472 | int status = 0; | |
| e0d3bafd | 2473 | |
| 84b5dbf3 | 2474 | cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask); |
| cde4362f MCC |
2475 | status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, |
| 2476 | value, 4); | |
| 84b5dbf3 MCC |
2477 | if (status < 0) |
| 2478 | return status; | |
| e0d3bafd | 2479 | |
| 84b5dbf3 MCC |
2480 | tmp = *((u32 *) value); |
| 2481 | tmp |= ep_mask; | |
| 2482 | value[0] = (u8) tmp; | |
| 2483 | value[1] = (u8) (tmp >> 8); | |
| 2484 | value[2] = (u8) (tmp >> 16); | |
| 2485 | value[3] = (u8) (tmp >> 24); | |
| e0d3bafd | 2486 | |
| cde4362f MCC |
2487 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, |
| 2488 | value, 4); | |
| e0d3bafd | 2489 | |
| 84b5dbf3 | 2490 | return status; |
| e0d3bafd SD |
2491 | } |
| 2492 | ||
| 2493 | int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask) | |
| 2494 | { | |
| 84b5dbf3 MCC |
2495 | u8 value[4] = { 0x0, 0x0, 0x0, 0x0 }; |
| 2496 | u32 tmp = 0; | |
| 2497 | int status = 0; | |
| e0d3bafd | 2498 | |
| 84b5dbf3 MCC |
2499 | cx231xx_info("cx231xx_stop_stream():: ep_mask = %x\n", ep_mask); |
| 2500 | status = | |
| 2501 | cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4); | |
| 2502 | if (status < 0) | |
| 2503 | return status; | |
| e0d3bafd | 2504 | |
| 84b5dbf3 MCC |
2505 | tmp = *((u32 *) value); |
| 2506 | tmp &= (~ep_mask); | |
| 2507 | value[0] = (u8) tmp; | |
| 2508 | value[1] = (u8) (tmp >> 8); | |
| 2509 | value[2] = (u8) (tmp >> 16); | |
| 2510 | value[3] = (u8) (tmp >> 24); | |
| e0d3bafd | 2511 | |
| cde4362f MCC |
2512 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, |
| 2513 | value, 4); | |
| e0d3bafd | 2514 | |
| 84b5dbf3 | 2515 | return status; |
| e0d3bafd SD |
2516 | } |
| 2517 | ||
| 2518 | int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type) | |
| 2519 | { | |
| 84b5dbf3 | 2520 | int status = 0; |
| 64fbf444 PB |
2521 | u32 value = 0; |
| 2522 | u8 val[4] = { 0, 0, 0, 0 }; | |
| e0d3bafd | 2523 | |
| 84b5dbf3 MCC |
2524 | if (dev->udev->speed == USB_SPEED_HIGH) { |
| 2525 | switch (media_type) { | |
| 6e4f574b | 2526 | case 81: /* audio */ |
| 84b5dbf3 MCC |
2527 | cx231xx_info("%s: Audio enter HANC\n", __func__); |
| 2528 | status = | |
| 2529 | cx231xx_mode_register(dev, TS_MODE_REG, 0x9300); | |
| 2530 | break; | |
| 2531 | ||
| 2532 | case 2: /* vbi */ | |
| 2533 | cx231xx_info("%s: set vanc registers\n", __func__); | |
| 2534 | status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300); | |
| 2535 | break; | |
| 2536 | ||
| 2537 | case 3: /* sliced cc */ | |
| 2538 | cx231xx_info("%s: set hanc registers\n", __func__); | |
| 2539 | status = | |
| 2540 | cx231xx_mode_register(dev, TS_MODE_REG, 0x1300); | |
| 2541 | break; | |
| 2542 | ||
| 2543 | case 0: /* video */ | |
| 2544 | cx231xx_info("%s: set video registers\n", __func__); | |
| 2545 | status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100); | |
| 2546 | break; | |
| 2547 | ||
| 2548 | case 4: /* ts1 */ | |
| 64fbf444 PB |
2549 | cx231xx_info("%s: set ts1 registers", __func__); |
| 2550 | ||
| 2f861387 | 2551 | if (dev->board.has_417) { |
| 64fbf444 PB |
2552 | cx231xx_info(" MPEG\n"); |
| 2553 | value &= 0xFFFFFFFC; | |
| 2554 | value |= 0x3; | |
| 2555 | ||
| 2556 | status = cx231xx_mode_register(dev, TS_MODE_REG, value); | |
| 2557 | ||
| 2558 | val[0] = 0x04; | |
| 2559 | val[1] = 0xA3; | |
| 2560 | val[2] = 0x3B; | |
| 2561 | val[3] = 0x00; | |
| 2562 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, | |
| 2563 | TS1_CFG_REG, val, 4); | |
| 2564 | ||
| 2565 | val[0] = 0x00; | |
| 2566 | val[1] = 0x08; | |
| 2567 | val[2] = 0x00; | |
| 2568 | val[3] = 0x08; | |
| 2569 | status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, | |
| 2570 | TS1_LENGTH_REG, val, 4); | |
| 2571 | ||
| 2572 | } else { | |
| 2573 | cx231xx_info(" BDA\n"); | |
| 84b5dbf3 | 2574 | status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101); |
| 64fbf444 PB |
2575 | status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x010); |
| 2576 | } | |
| 84b5dbf3 | 2577 | break; |
| 64fbf444 | 2578 | |
| 84b5dbf3 | 2579 | case 6: /* ts1 parallel mode */ |
| 25985edc | 2580 | cx231xx_info("%s: set ts1 parallel mode registers\n", |
| 84b5dbf3 MCC |
2581 | __func__); |
| 2582 | status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100); | |
| 2583 | status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400); | |
| 2584 | break; | |
| 2585 | } | |
| 2586 | } else { | |
| 2587 | status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101); | |
| 2588 | } | |
| e0d3bafd | 2589 | |
| 84b5dbf3 MCC |
2590 | return status; |
| 2591 | } | |
| e0d3bafd SD |
2592 | |
| 2593 | int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type) | |
| 2594 | { | |
| aad40d3d | 2595 | int rc = -1; |
| 84b5dbf3 | 2596 | u32 ep_mask = -1; |
| b9255176 | 2597 | struct pcb_config *pcb_config; |
| 84b5dbf3 MCC |
2598 | |
| 2599 | /* get EP for media type */ | |
| b9255176 | 2600 | pcb_config = (struct pcb_config *)&dev->current_pcb_config; |
| 84b5dbf3 MCC |
2601 | |
| 2602 | if (pcb_config->config_num == 1) { | |
| 2603 | switch (media_type) { | |
| 2604 | case 0: /* Video */ | |
| 2605 | ep_mask = ENABLE_EP4; /* ep4 [00:1000] */ | |
| 2606 | break; | |
| 2607 | case 1: /* Audio */ | |
| 2608 | ep_mask = ENABLE_EP3; /* ep3 [00:0100] */ | |
| 2609 | break; | |
| 2610 | case 2: /* Vbi */ | |
| 2611 | ep_mask = ENABLE_EP5; /* ep5 [01:0000] */ | |
| 2612 | break; | |
| 2613 | case 3: /* Sliced_cc */ | |
| 2614 | ep_mask = ENABLE_EP6; /* ep6 [10:0000] */ | |
| 2615 | break; | |
| 2616 | case 4: /* ts1 */ | |
| 2617 | case 6: /* ts1 parallel mode */ | |
| 2618 | ep_mask = ENABLE_EP1; /* ep1 [00:0001] */ | |
| 2619 | break; | |
| 2620 | case 5: /* ts2 */ | |
| 2621 | ep_mask = ENABLE_EP2; /* ep2 [00:0010] */ | |
| 2622 | break; | |
| 2623 | } | |
| 2624 | ||
| 2625 | } else if (pcb_config->config_num > 1) { | |
| 2626 | switch (media_type) { | |
| 2627 | case 0: /* Video */ | |
| 2628 | ep_mask = ENABLE_EP4; /* ep4 [00:1000] */ | |
| 2629 | break; | |
| 2630 | case 1: /* Audio */ | |
| 2631 | ep_mask = ENABLE_EP3; /* ep3 [00:0100] */ | |
| 2632 | break; | |
| 2633 | case 2: /* Vbi */ | |
| 2634 | ep_mask = ENABLE_EP5; /* ep5 [01:0000] */ | |
| 2635 | break; | |
| 2636 | case 3: /* Sliced_cc */ | |
| 2637 | ep_mask = ENABLE_EP6; /* ep6 [10:0000] */ | |
| 2638 | break; | |
| 2639 | case 4: /* ts1 */ | |
| 2640 | case 6: /* ts1 parallel mode */ | |
| 2641 | ep_mask = ENABLE_EP1; /* ep1 [00:0001] */ | |
| 2642 | break; | |
| 2643 | case 5: /* ts2 */ | |
| 2644 | ep_mask = ENABLE_EP2; /* ep2 [00:0010] */ | |
| 2645 | break; | |
| 2646 | } | |
| 2647 | ||
| 2648 | } | |
| 2649 | ||
| 2650 | if (start) { | |
| 2651 | rc = cx231xx_initialize_stream_xfer(dev, media_type); | |
| 2652 | ||
| cde4362f | 2653 | if (rc < 0) |
| 84b5dbf3 | 2654 | return rc; |
| 84b5dbf3 MCC |
2655 | |
| 2656 | /* enable video capture */ | |
| 2657 | if (ep_mask > 0) | |
| 2658 | rc = cx231xx_start_stream(dev, ep_mask); | |
| 2659 | } else { | |
| 2660 | /* disable video capture */ | |
| 2661 | if (ep_mask > 0) | |
| 2662 | rc = cx231xx_stop_stream(dev, ep_mask); | |
| 2663 | } | |
| 2664 | ||
| b9255176 SD |
2665 | if (dev->mode == CX231XX_ANALOG_MODE) |
| 2666 | ;/* do any in Analog mode */ | |
| 2667 | else | |
| 2668 | ;/* do any in digital mode */ | |
| e0d3bafd SD |
2669 | |
| 2670 | return rc; | |
| 2671 | } | |
| 84b5dbf3 | 2672 | EXPORT_SYMBOL_GPL(cx231xx_capture_start); |
| e0d3bafd | 2673 | |
| cde4362f MCC |
2674 | /***************************************************************************** |
| 2675 | * G P I O B I T control functions * | |
| 2676 | ******************************************************************************/ | |
| 64fbf444 | 2677 | int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val) |
| e0d3bafd | 2678 | { |
| 84b5dbf3 | 2679 | int status = 0; |
| e0d3bafd | 2680 | |
| 84b5dbf3 | 2681 | status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 0); |
| e0d3bafd | 2682 | |
| 84b5dbf3 | 2683 | return status; |
| e0d3bafd SD |
2684 | } |
| 2685 | ||
| 64fbf444 | 2686 | int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val) |
| e0d3bafd | 2687 | { |
| 84b5dbf3 | 2688 | int status = 0; |
| e0d3bafd | 2689 | |
| 84b5dbf3 | 2690 | status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 1); |
| e0d3bafd | 2691 | |
| 84b5dbf3 | 2692 | return status; |
| e0d3bafd SD |
2693 | } |
| 2694 | ||
| 2695 | /* | |
| 2696 | * cx231xx_set_gpio_direction | |
| 2697 | * Sets the direction of the GPIO pin to input or output | |
| 2698 | * | |
| 2699 | * Parameters : | |
| 2700 | * pin_number : The GPIO Pin number to program the direction for | |
| 2701 | * from 0 to 31 | |
| 2702 | * pin_value : The Direction of the GPIO Pin under reference. | |
| 2703 | * 0 = Input direction | |
| 2704 | * 1 = Output direction | |
| 2705 | */ | |
| 2706 | int cx231xx_set_gpio_direction(struct cx231xx *dev, | |
| 84b5dbf3 | 2707 | int pin_number, int pin_value) |
| e0d3bafd SD |
2708 | { |
| 2709 | int status = 0; | |
| 84b5dbf3 | 2710 | u32 value = 0; |
| e0d3bafd | 2711 | |
| 84b5dbf3 | 2712 | /* Check for valid pin_number - if 32 , bail out */ |
| cde4362f | 2713 | if (pin_number >= 32) |
| 84b5dbf3 | 2714 | return -EINVAL; |
| e0d3bafd | 2715 | |
| cde4362f MCC |
2716 | /* input */ |
| 2717 | if (pin_value == 0) | |
| 84b5dbf3 | 2718 | value = dev->gpio_dir & (~(1 << pin_number)); /* clear */ |
| cde4362f | 2719 | else |
| 84b5dbf3 | 2720 | value = dev->gpio_dir | (1 << pin_number); |
| e0d3bafd | 2721 | |
| cde4362f | 2722 | status = cx231xx_set_gpio_bit(dev, value, (u8 *) &dev->gpio_val); |
| e0d3bafd | 2723 | |
| 84b5dbf3 | 2724 | /* cache the value for future */ |
| e0d3bafd SD |
2725 | dev->gpio_dir = value; |
| 2726 | ||
| 84b5dbf3 | 2727 | return status; |
| e0d3bafd SD |
2728 | } |
| 2729 | ||
| e0d3bafd | 2730 | /* |
| 6e4f574b | 2731 | * cx231xx_set_gpio_value |
| e0d3bafd SD |
2732 | * Sets the value of the GPIO pin to Logic high or low. The Pin under |
| 2733 | * reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!! | |
| 2734 | * | |
| 2735 | * Parameters : | |
| 2736 | * pin_number : The GPIO Pin number to program the direction for | |
| 2737 | * pin_value : The value of the GPIO Pin under reference. | |
| 2738 | * 0 = set it to 0 | |
| 2739 | * 1 = set it to 1 | |
| 2740 | */ | |
| 84b5dbf3 | 2741 | int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value) |
| e0d3bafd | 2742 | { |
| 84b5dbf3 MCC |
2743 | int status = 0; |
| 2744 | u32 value = 0; | |
| 2745 | ||
| 2746 | /* Check for valid pin_number - if 0xFF , bail out */ | |
| 2747 | if (pin_number >= 32) | |
| 2748 | return -EINVAL; | |
| 2749 | ||
| 2750 | /* first do a sanity check - if the Pin is not output, make it output */ | |
| 2751 | if ((dev->gpio_dir & (1 << pin_number)) == 0x00) { | |
| 2752 | /* It was in input mode */ | |
| 2753 | value = dev->gpio_dir | (1 << pin_number); | |
| 2754 | dev->gpio_dir = value; | |
| cde4362f MCC |
2755 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, |
| 2756 | (u8 *) &dev->gpio_val); | |
| e0d3bafd | 2757 | value = 0; |
| 84b5dbf3 | 2758 | } |
| e0d3bafd | 2759 | |
| cde4362f | 2760 | if (pin_value == 0) |
| 84b5dbf3 | 2761 | value = dev->gpio_val & (~(1 << pin_number)); |
| cde4362f | 2762 | else |
| 84b5dbf3 | 2763 | value = dev->gpio_val | (1 << pin_number); |
| e0d3bafd | 2764 | |
| 84b5dbf3 MCC |
2765 | /* store the value */ |
| 2766 | dev->gpio_val = value; | |
| e0d3bafd | 2767 | |
| 84b5dbf3 | 2768 | /* toggle bit0 of GP_IO */ |
| cde4362f | 2769 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
| e0d3bafd | 2770 | |
| 84b5dbf3 | 2771 | return status; |
| e0d3bafd SD |
2772 | } |
| 2773 | ||
| cde4362f MCC |
2774 | /***************************************************************************** |
| 2775 | * G P I O I2C related functions * | |
| 2776 | ******************************************************************************/ | |
| e0d3bafd SD |
2777 | int cx231xx_gpio_i2c_start(struct cx231xx *dev) |
| 2778 | { | |
| 2779 | int status = 0; | |
| 2780 | ||
| 2781 | /* set SCL to output 1 ; set SDA to output 1 */ | |
| 84b5dbf3 MCC |
2782 | dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; |
| 2783 | dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; | |
| 2784 | dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; | |
| 2785 | dev->gpio_val |= 1 << dev->board.tuner_sda_gpio; | |
| 2786 | ||
| cde4362f MCC |
2787 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
| 2788 | if (status < 0) | |
| e0d3bafd | 2789 | return -EINVAL; |
| e0d3bafd SD |
2790 | |
| 2791 | /* set SCL to output 1; set SDA to output 0 */ | |
| 84b5dbf3 MCC |
2792 | dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; |
| 2793 | dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); | |
| e0d3bafd | 2794 | |
| cde4362f MCC |
2795 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
| 2796 | if (status < 0) | |
| e0d3bafd | 2797 | return -EINVAL; |
| e0d3bafd | 2798 | |
| 84b5dbf3 MCC |
2799 | /* set SCL to output 0; set SDA to output 0 */ |
| 2800 | dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); | |
| 2801 | dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); | |
| e0d3bafd | 2802 | |
| cde4362f MCC |
2803 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
| 2804 | if (status < 0) | |
| e0d3bafd | 2805 | return -EINVAL; |
| e0d3bafd SD |
2806 | |
| 2807 | return status; | |
| 2808 | } | |
| 2809 | ||
| e0d3bafd SD |
2810 | int cx231xx_gpio_i2c_end(struct cx231xx *dev) |
| 2811 | { | |
| 84b5dbf3 | 2812 | int status = 0; |
| e0d3bafd | 2813 | |
| 84b5dbf3 MCC |
2814 | /* set SCL to output 0; set SDA to output 0 */ |
| 2815 | dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; | |
| 2816 | dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; | |
| e0d3bafd | 2817 | |
| 84b5dbf3 MCC |
2818 | dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); |
| 2819 | dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); | |
| e0d3bafd | 2820 | |
| cde4362f MCC |
2821 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
| 2822 | if (status < 0) | |
| e0d3bafd | 2823 | return -EINVAL; |
| e0d3bafd | 2824 | |
| 84b5dbf3 MCC |
2825 | /* set SCL to output 1; set SDA to output 0 */ |
| 2826 | dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; | |
| 2827 | dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); | |
| e0d3bafd | 2828 | |
| cde4362f MCC |
2829 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
| 2830 | if (status < 0) | |
| e0d3bafd | 2831 | return -EINVAL; |
| e0d3bafd SD |
2832 | |
| 2833 | /* set SCL to input ,release SCL cable control | |
| 2834 | set SDA to input ,release SDA cable control */ | |
| 84b5dbf3 MCC |
2835 | dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio); |
| 2836 | dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); | |
| e0d3bafd | 2837 | |
| 84b5dbf3 | 2838 | status = |
| cde4362f MCC |
2839 | cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
| 2840 | if (status < 0) | |
| e0d3bafd | 2841 | return -EINVAL; |
| cde4362f | 2842 | |
| e0d3bafd SD |
2843 | return status; |
| 2844 | } | |
| 2845 | ||
| e0d3bafd SD |
2846 | int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data) |
| 2847 | { | |
| 84b5dbf3 MCC |
2848 | int status = 0; |
| 2849 | u8 i; | |
| e0d3bafd SD |
2850 | |
| 2851 | /* set SCL to output ; set SDA to output */ | |
| 84b5dbf3 MCC |
2852 | dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; |
| 2853 | dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; | |
| 2854 | ||
| 2855 | for (i = 0; i < 8; i++) { | |
| 2856 | if (((data << i) & 0x80) == 0) { | |
| 2857 | /* set SCL to output 0; set SDA to output 0 */ | |
| 2858 | dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); | |
| 2859 | dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); | |
| cde4362f MCC |
2860 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, |
| 2861 | (u8 *)&dev->gpio_val); | |
| 84b5dbf3 MCC |
2862 | |
| 2863 | /* set SCL to output 1; set SDA to output 0 */ | |
| 2864 | dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; | |
| cde4362f MCC |
2865 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, |
| 2866 | (u8 *)&dev->gpio_val); | |
| 84b5dbf3 MCC |
2867 | |
| 2868 | /* set SCL to output 0; set SDA to output 0 */ | |
| 2869 | dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); | |
| cde4362f MCC |
2870 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, |
| 2871 | (u8 *)&dev->gpio_val); | |
| e0d3bafd | 2872 | } else { |
| 84b5dbf3 MCC |
2873 | /* set SCL to output 0; set SDA to output 1 */ |
| 2874 | dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); | |
| 2875 | dev->gpio_val |= 1 << dev->board.tuner_sda_gpio; | |
| cde4362f MCC |
2876 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, |
| 2877 | (u8 *)&dev->gpio_val); | |
| 84b5dbf3 MCC |
2878 | |
| 2879 | /* set SCL to output 1; set SDA to output 1 */ | |
| 2880 | dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; | |
| cde4362f MCC |
2881 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, |
| 2882 | (u8 *)&dev->gpio_val); | |
| 84b5dbf3 MCC |
2883 | |
| 2884 | /* set SCL to output 0; set SDA to output 1 */ | |
| 2885 | dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); | |
| cde4362f MCC |
2886 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, |
| 2887 | (u8 *)&dev->gpio_val); | |
| 84b5dbf3 | 2888 | } |
| e0d3bafd SD |
2889 | } |
| 2890 | return status; | |
| 2891 | } | |
| 2892 | ||
| 64fbf444 | 2893 | int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf) |
| e0d3bafd SD |
2894 | { |
| 2895 | u8 value = 0; | |
| 84b5dbf3 MCC |
2896 | int status = 0; |
| 2897 | u32 gpio_logic_value = 0; | |
| 2898 | u8 i; | |
| e0d3bafd SD |
2899 | |
| 2900 | /* read byte */ | |
| 84b5dbf3 | 2901 | for (i = 0; i < 8; i++) { /* send write I2c addr */ |
| e0d3bafd SD |
2902 | |
| 2903 | /* set SCL to output 0; set SDA to input */ | |
| 84b5dbf3 | 2904 | dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); |
| cde4362f MCC |
2905 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, |
| 2906 | (u8 *)&dev->gpio_val); | |
| e0d3bafd SD |
2907 | |
| 2908 | /* set SCL to output 1; set SDA to input */ | |
| 84b5dbf3 | 2909 | dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; |
| cde4362f MCC |
2910 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, |
| 2911 | (u8 *)&dev->gpio_val); | |
| e0d3bafd SD |
2912 | |
| 2913 | /* get SDA data bit */ | |
| 2914 | gpio_logic_value = dev->gpio_val; | |
| cde4362f MCC |
2915 | status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, |
| 2916 | (u8 *)&dev->gpio_val); | |
| 2917 | if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0) | |
| 84b5dbf3 | 2918 | value |= (1 << (8 - i - 1)); |
| e0d3bafd SD |
2919 | |
| 2920 | dev->gpio_val = gpio_logic_value; | |
| 2921 | } | |
| 2922 | ||
| 2923 | /* set SCL to output 0,finish the read latest SCL signal. | |
| cde4362f MCC |
2924 | !!!set SDA to input, never to modify SDA direction at |
| 2925 | the same times */ | |
| 84b5dbf3 | 2926 | dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); |
| cde4362f | 2927 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
| e0d3bafd | 2928 | |
| 84b5dbf3 MCC |
2929 | /* store the value */ |
| 2930 | *buf = value & 0xff; | |
| e0d3bafd SD |
2931 | |
| 2932 | return status; | |
| 2933 | } | |
| 2934 | ||
| 2935 | int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev) | |
| 2936 | { | |
| 84b5dbf3 | 2937 | int status = 0; |
| e0d3bafd | 2938 | u32 gpio_logic_value = 0; |
| 84b5dbf3 MCC |
2939 | int nCnt = 10; |
| 2940 | int nInit = nCnt; | |
| e0d3bafd | 2941 | |
| cde4362f MCC |
2942 | /* clock stretch; set SCL to input; set SDA to input; |
| 2943 | get SCL value till SCL = 1 */ | |
| 84b5dbf3 MCC |
2944 | dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); |
| 2945 | dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio); | |
| e0d3bafd SD |
2946 | |
| 2947 | gpio_logic_value = dev->gpio_val; | |
| cde4362f | 2948 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
| e0d3bafd | 2949 | |
| 84b5dbf3 | 2950 | do { |
| e0d3bafd | 2951 | msleep(2); |
| cde4362f MCC |
2952 | status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, |
| 2953 | (u8 *)&dev->gpio_val); | |
| 84b5dbf3 | 2954 | nCnt--; |
| b9255176 SD |
2955 | } while (((dev->gpio_val & |
| 2956 | (1 << dev->board.tuner_scl_gpio)) == 0) && | |
| 2957 | (nCnt > 0)); | |
| 84b5dbf3 | 2958 | |
| cde4362f | 2959 | if (nCnt == 0) |
| b9255176 | 2960 | cx231xx_info("No ACK after %d msec -GPIO I2C failed!", |
| cde4362f | 2961 | nInit * 10); |
| e0d3bafd | 2962 | |
| af901ca1 AGR |
2963 | /* |
| 2964 | * readAck | |
| 2965 | * through clock stretch, slave has given a SCL signal, | |
| 2966 | * so the SDA data can be directly read. | |
| 2967 | */ | |
| cde4362f | 2968 | status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
| e0d3bafd | 2969 | |
| 84b5dbf3 | 2970 | if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) { |
| e0d3bafd | 2971 | dev->gpio_val = gpio_logic_value; |
| 84b5dbf3 | 2972 | dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); |
| e0d3bafd SD |
2973 | status = 0; |
| 2974 | } else { | |
| 2975 | dev->gpio_val = gpio_logic_value; | |
| 84b5dbf3 | 2976 | dev->gpio_val |= (1 << dev->board.tuner_sda_gpio); |
| e0d3bafd SD |
2977 | } |
| 2978 | ||
| cde4362f MCC |
2979 | /* read SDA end, set the SCL to output 0, after this operation, |
| 2980 | SDA direction can be changed. */ | |
| e0d3bafd | 2981 | dev->gpio_val = gpio_logic_value; |
| 84b5dbf3 MCC |
2982 | dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio); |
| 2983 | dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); | |
| cde4362f | 2984 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
| e0d3bafd SD |
2985 | |
| 2986 | return status; | |
| 2987 | } | |
| 2988 | ||
| e0d3bafd SD |
2989 | int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev) |
| 2990 | { | |
| 84b5dbf3 | 2991 | int status = 0; |
| e0d3bafd SD |
2992 | |
| 2993 | /* set SDA to ouput */ | |
| 84b5dbf3 | 2994 | dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; |
| cde4362f | 2995 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
| e0d3bafd SD |
2996 | |
| 2997 | /* set SCL = 0 (output); set SDA = 0 (output) */ | |
| 84b5dbf3 MCC |
2998 | dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); |
| 2999 | dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); | |
| cde4362f | 3000 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
| e0d3bafd SD |
3001 | |
| 3002 | /* set SCL = 1 (output); set SDA = 0 (output) */ | |
| 84b5dbf3 | 3003 | dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; |
| cde4362f | 3004 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
| e0d3bafd SD |
3005 | |
| 3006 | /* set SCL = 0 (output); set SDA = 0 (output) */ | |
| 84b5dbf3 | 3007 | dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); |
| cde4362f | 3008 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
| e0d3bafd SD |
3009 | |
| 3010 | /* set SDA to input,and then the slave will read data from SDA. */ | |
| 84b5dbf3 | 3011 | dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); |
| cde4362f | 3012 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
| e0d3bafd SD |
3013 | |
| 3014 | return status; | |
| 3015 | } | |
| 3016 | ||
| 3017 | int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev) | |
| 3018 | { | |
| 84b5dbf3 | 3019 | int status = 0; |
| e0d3bafd SD |
3020 | |
| 3021 | /* set scl to output ; set sda to input */ | |
| 84b5dbf3 MCC |
3022 | dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; |
| 3023 | dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); | |
| cde4362f | 3024 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
| e0d3bafd SD |
3025 | |
| 3026 | /* set scl to output 0; set sda to input */ | |
| 84b5dbf3 | 3027 | dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); |
| cde4362f | 3028 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
| e0d3bafd SD |
3029 | |
| 3030 | /* set scl to output 1; set sda to input */ | |
| 84b5dbf3 | 3031 | dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; |
| cde4362f | 3032 | status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); |
| e0d3bafd SD |
3033 | |
| 3034 | return status; | |
| 3035 | } | |
| 3036 | ||
| cde4362f MCC |
3037 | /***************************************************************************** |
| 3038 | * G P I O I2C related functions * | |
| 3039 | ******************************************************************************/ | |
| e0d3bafd SD |
3040 | /* cx231xx_gpio_i2c_read |
| 3041 | * Function to read data from gpio based I2C interface | |
| 3042 | */ | |
| 64fbf444 | 3043 | int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len) |
| e0d3bafd | 3044 | { |
| 84b5dbf3 MCC |
3045 | int status = 0; |
| 3046 | int i = 0; | |
| e0d3bafd | 3047 | |
| 84b5dbf3 | 3048 | /* get the lock */ |
| e0d3bafd SD |
3049 | mutex_lock(&dev->gpio_i2c_lock); |
| 3050 | ||
| 3051 | /* start */ | |
| 3052 | status = cx231xx_gpio_i2c_start(dev); | |
| 3053 | ||
| 3054 | /* write dev_addr */ | |
| 84b5dbf3 | 3055 | status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1); |
| e0d3bafd SD |
3056 | |
| 3057 | /* readAck */ | |
| 3058 | status = cx231xx_gpio_i2c_read_ack(dev); | |
| 3059 | ||
| 84b5dbf3 MCC |
3060 | /* read data */ |
| 3061 | for (i = 0; i < len; i++) { | |
| 3062 | /* read data */ | |
| 3063 | buf[i] = 0; | |
| 3064 | status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]); | |
| e0d3bafd | 3065 | |
| 84b5dbf3 MCC |
3066 | if ((i + 1) != len) { |
| 3067 | /* only do write ack if we more length */ | |
| 3068 | status = cx231xx_gpio_i2c_write_ack(dev); | |
| 3069 | } | |
| 3070 | } | |
| e0d3bafd SD |
3071 | |
| 3072 | /* write NAK - inform reads are complete */ | |
| 3073 | status = cx231xx_gpio_i2c_write_nak(dev); | |
| 3074 | ||
| 3075 | /* write end */ | |
| 3076 | status = cx231xx_gpio_i2c_end(dev); | |
| 3077 | ||
| 3078 | /* release the lock */ | |
| 3079 | mutex_unlock(&dev->gpio_i2c_lock); | |
| 3080 | ||
| 3081 | return status; | |
| 3082 | } | |
| 3083 | ||
| e0d3bafd SD |
3084 | /* cx231xx_gpio_i2c_write |
| 3085 | * Function to write data to gpio based I2C interface | |
| 3086 | */ | |
| 64fbf444 | 3087 | int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len) |
| e0d3bafd | 3088 | { |
| 84b5dbf3 MCC |
3089 | int status = 0; |
| 3090 | int i = 0; | |
| e0d3bafd SD |
3091 | |
| 3092 | /* get the lock */ | |
| 3093 | mutex_lock(&dev->gpio_i2c_lock); | |
| 3094 | ||
| 3095 | /* start */ | |
| 3096 | status = cx231xx_gpio_i2c_start(dev); | |
| 3097 | ||
| 3098 | /* write dev_addr */ | |
| 3099 | status = cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1); | |
| 3100 | ||
| 3101 | /* read Ack */ | |
| 84b5dbf3 | 3102 | status = cx231xx_gpio_i2c_read_ack(dev); |
| e0d3bafd | 3103 | |
| 84b5dbf3 | 3104 | for (i = 0; i < len; i++) { |
| e0d3bafd | 3105 | /* Write data */ |
| 84b5dbf3 | 3106 | status = cx231xx_gpio_i2c_write_byte(dev, buf[i]); |
| e0d3bafd | 3107 | |
| 84b5dbf3 MCC |
3108 | /* read Ack */ |
| 3109 | status = cx231xx_gpio_i2c_read_ack(dev); | |
| 3110 | } | |
| e0d3bafd | 3111 | |
| 84b5dbf3 | 3112 | /* write End */ |
| e0d3bafd SD |
3113 | status = cx231xx_gpio_i2c_end(dev); |
| 3114 | ||
| 3115 | /* release the lock */ | |
| 3116 | mutex_unlock(&dev->gpio_i2c_lock); | |
| 3117 | ||
| 3118 | return 0; | |
| 3119 | } |