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Merge branch 'for-linus' of git://git.kernel.dk/linux-2.6-block
[mirror_ubuntu-kernels.git] / drivers / media / video / cx23885 / cx23885-cards.c
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
ST		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/pci.h>
25#include <linux/delay.h>
7b888014 26#include <media/cx25840.h>
d19770e5
ST		 27
28#include "cx23885.h"
90a71b1c 29#include "tuner-xc2028.h"
5a23b076 30#include "netup-init.h"
d19770e5
ST		 31
32/* ------------------------------------------------------------------ */
33/* board config info */
34
35struct cx23885_board cx23885_boards[] = {
36 [CX23885_BOARD_UNKNOWN] = {
37 .name = "UNKNOWN/GENERIC",
c7712613
ST		 38 /* Ensure safe default for unknown boards */
39 .clk_freq = 0,
d19770e5
ST		 40 .input = {{
41 .type = CX23885_VMUX_COMPOSITE1,
42 .vmux = 0,
9c8ced51 43 }, {
d19770e5
ST		 44 .type = CX23885_VMUX_COMPOSITE2,
45 .vmux = 1,
9c8ced51 46 }, {
d19770e5
ST		 47 .type = CX23885_VMUX_COMPOSITE3,
48 .vmux = 2,
9c8ced51 49 }, {
d19770e5
ST		 50 .type = CX23885_VMUX_COMPOSITE4,
51 .vmux = 3,
9c8ced51 52 } },
d19770e5
ST		 53 },
54 [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = {
55 .name = "Hauppauge WinTV-HVR1800lp",
d19770e5
ST		 56 .portc = CX23885_MPEG_DVB,
57 .input = {{
58 .type = CX23885_VMUX_TELEVISION,
59 .vmux = 0,
60 .gpio0 = 0xff00,
9c8ced51 61 }, {
d19770e5
ST		 62 .type = CX23885_VMUX_DEBUG,
63 .vmux = 0,
64 .gpio0 = 0xff01,
9c8ced51 65 }, {
d19770e5
ST		 66 .type = CX23885_VMUX_COMPOSITE1,
67 .vmux = 1,
68 .gpio0 = 0xff02,
9c8ced51 69 }, {
d19770e5
ST		 70 .type = CX23885_VMUX_SVIDEO,
71 .vmux = 2,
72 .gpio0 = 0xff02,
9c8ced51 73 } },
d19770e5
ST		 74 },
75 [CX23885_BOARD_HAUPPAUGE_HVR1800] = {
76 .name = "Hauppauge WinTV-HVR1800",
7b888014 77 .porta = CX23885_ANALOG_VIDEO,
a589b665 78 .portb = CX23885_MPEG_ENCODER,
d19770e5 79 .portc = CX23885_MPEG_DVB,
7b888014
ST		 80 .tuner_type = TUNER_PHILIPS_TDA8290,
81 .tuner_addr = 0x42, /* 0x84 >> 1 */
d19770e5
ST		 82 .input = {{
83 .type = CX23885_VMUX_TELEVISION,
7b888014
ST		 84 .vmux = CX25840_VIN7_CH3 |
85 CX25840_VIN5_CH2 |
86 CX25840_VIN2_CH1,
87 .gpio0 = 0,
9c8ced51 88 }, {
d19770e5 89 .type = CX23885_VMUX_COMPOSITE1,
7b888014
ST		 90 .vmux = CX25840_VIN7_CH3 |
91 CX25840_VIN4_CH2 |
92 CX25840_VIN6_CH1,
93 .gpio0 = 0,
9c8ced51 94 }, {
d19770e5 95 .type = CX23885_VMUX_SVIDEO,
7b888014
ST		 96 .vmux = CX25840_VIN7_CH3 |
97 CX25840_VIN4_CH2 |
98 CX25840_VIN8_CH1 |
99 CX25840_SVIDEO_ON,
100 .gpio0 = 0,
9c8ced51 101 } },
d19770e5 102 },
a77743bc
ST		 103 [CX23885_BOARD_HAUPPAUGE_HVR1250] = {
104 .name = "Hauppauge WinTV-HVR1250",
105 .portc = CX23885_MPEG_DVB,
106 .input = {{
107 .type = CX23885_VMUX_TELEVISION,
108 .vmux = 0,
109 .gpio0 = 0xff00,
9c8ced51 110 }, {
a77743bc
ST		 111 .type = CX23885_VMUX_DEBUG,
112 .vmux = 0,
113 .gpio0 = 0xff01,
9c8ced51 114 }, {
a77743bc
ST		 115 .type = CX23885_VMUX_COMPOSITE1,
116 .vmux = 1,
117 .gpio0 = 0xff02,
9c8ced51 118 }, {
a77743bc
ST		 119 .type = CX23885_VMUX_SVIDEO,
120 .vmux = 2,
121 .gpio0 = 0xff02,
9c8ced51 122 } },
a77743bc 123 },
9bc37caa
MK		 124 [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = {
125 .name = "DViCO FusionHDTV5 Express",
a6a3f140 126 .portb = CX23885_MPEG_DVB,
9bc37caa 127 },
d1987d55
ST		 128 [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = {
129 .name = "Hauppauge WinTV-HVR1500Q",
130 .portc = CX23885_MPEG_DVB,
131 },
07b4a835
MK		 132 [CX23885_BOARD_HAUPPAUGE_HVR1500] = {
133 .name = "Hauppauge WinTV-HVR1500",
134 .portc = CX23885_MPEG_DVB,
135 },
b3ea0166
ST		 136 [CX23885_BOARD_HAUPPAUGE_HVR1200] = {
137 .name = "Hauppauge WinTV-HVR1200",
138 .portc = CX23885_MPEG_DVB,
139 },
a780a31c
ST		 140 [CX23885_BOARD_HAUPPAUGE_HVR1700] = {
141 .name = "Hauppauge WinTV-HVR1700",
142 .portc = CX23885_MPEG_DVB,
143 },
66762373
ST		 144 [CX23885_BOARD_HAUPPAUGE_HVR1400] = {
145 .name = "Hauppauge WinTV-HVR1400",
146 .portc = CX23885_MPEG_DVB,
147 },
335377b7
MK		 148 [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
149 .name = "DViCO FusionHDTV7 Dual Express",
aaadeac8 150 .portb = CX23885_MPEG_DVB,
335377b7
MK		 151 .portc = CX23885_MPEG_DVB,
152 },
aef2d186
ST		 153 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = {
154 .name = "DViCO FusionHDTV DVB-T Dual Express",
155 .portb = CX23885_MPEG_DVB,
156 .portc = CX23885_MPEG_DVB,
157 },
4c56b04a
ST		 158 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = {
159 .name = "Leadtek Winfast PxDVR3200 H",
160 .portc = CX23885_MPEG_DVB,
161 },
9bb1b7e8
IL		 162 [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = {
163 .name = "Compro VideoMate E650F",
164 .portc = CX23885_MPEG_DVB,
165 },
96318d0c
IL		 166 [CX23885_BOARD_TBS_6920] = {
167 .name = "TurboSight TBS 6920",
168 .portb = CX23885_MPEG_DVB,
169 },
579943f5
IL		 170 [CX23885_BOARD_TEVII_S470] = {
171 .name = "TeVii S470",
172 .portb = CX23885_MPEG_DVB,
173 },
c9b8b04b
IL		 174 [CX23885_BOARD_DVBWORLD_2005] = {
175 .name = "DVBWorld DVB-S2 2005",
176 .portb = CX23885_MPEG_DVB,
177 },
5a23b076
IL		 178 [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = {
179 .cimax = 1,
180 .name = "NetUP Dual DVB-S2 CI",
181 .portb = CX23885_MPEG_DVB,
182 .portc = CX23885_MPEG_DVB,
183 },
d19770e5
ST		 184};
185const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
186
187/* ------------------------------------------------------------------ */
188/* PCI subsystem IDs */
189
190struct cx23885_subid cx23885_subids[] = {
191 {
192 .subvendor = 0x0070,
193 .subdevice = 0x3400,
194 .card = CX23885_BOARD_UNKNOWN,
9c8ced51 195 }, {
d19770e5
ST		 196 .subvendor = 0x0070,
197 .subdevice = 0x7600,
198 .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp,
9c8ced51 199 }, {
d19770e5
ST		 200 .subvendor = 0x0070,
201 .subdevice = 0x7800,
202 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
9c8ced51 203 }, {
d19770e5
ST		 204 .subvendor = 0x0070,
205 .subdevice = 0x7801,
206 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
9c8ced51 207 }, {
6ccb8cfb
MK		 208 .subvendor = 0x0070,
209 .subdevice = 0x7809,
210 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
9c8ced51 211 }, {
a77743bc
ST		 212 .subvendor = 0x0070,
213 .subdevice = 0x7911,
214 .card = CX23885_BOARD_HAUPPAUGE_HVR1250,
9c8ced51 215 }, {
9bc37caa
MK		 216 .subvendor = 0x18ac,
217 .subdevice = 0xd500,
218 .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP,
9c8ced51 219 }, {
b00fff0b
MK		 220 .subvendor = 0x0070,
221 .subdevice = 0x7790,
222 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
9c8ced51 223 }, {
d1987d55
ST		 224 .subvendor = 0x0070,
225 .subdevice = 0x7797,
226 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
9c8ced51 227 }, {
b00fff0b
MK		 228 .subvendor = 0x0070,
229 .subdevice = 0x7710,
230 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
9c8ced51 231 }, {
07b4a835
MK		 232 .subvendor = 0x0070,
233 .subdevice = 0x7717,
234 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
b3ea0166
ST		 235 }, {
236 .subvendor = 0x0070,
237 .subdevice = 0x71d1,
238 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
3c3852cd
MK		 239 }, {
240 .subvendor = 0x0070,
241 .subdevice = 0x71d3,
242 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
a780a31c
ST		 243 }, {
244 .subvendor = 0x0070,
245 .subdevice = 0x8101,
246 .card = CX23885_BOARD_HAUPPAUGE_HVR1700,
66762373
ST		 247 }, {
248 .subvendor = 0x0070,
249 .subdevice = 0x8010,
250 .card = CX23885_BOARD_HAUPPAUGE_HVR1400,
9c8ced51 251 }, {
335377b7
MK		 252 .subvendor = 0x18ac,
253 .subdevice = 0xd618,
254 .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP,
9c8ced51 255 }, {
aef2d186
ST		 256 .subvendor = 0x18ac,
257 .subdevice = 0xdb78,
258 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP,
4c56b04a
ST		 259 }, {
260 .subvendor = 0x107d,
261 .subdevice = 0x6681,
262 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H,
9bb1b7e8
IL		 263 }, {
264 .subvendor = 0x185b,
265 .subdevice = 0xe800,
266 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F,
96318d0c
IL		 267 }, {
268 .subvendor = 0x6920,
269 .subdevice = 0x8888,
270 .card = CX23885_BOARD_TBS_6920,
579943f5
IL		 271 }, {
272 .subvendor = 0xd470,
273 .subdevice = 0x9022,
274 .card = CX23885_BOARD_TEVII_S470,
c9b8b04b
IL		 275 }, {
276 .subvendor = 0x0001,
277 .subdevice = 0x2005,
278 .card = CX23885_BOARD_DVBWORLD_2005,
5a23b076
IL		 279 }, {
280 .subvendor = 0x1b55,
281 .subdevice = 0x2a2c,
282 .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
d19770e5
ST		 283 },
284};
285const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
286
287void cx23885_card_list(struct cx23885_dev *dev)
288{
289 int i;
290
291 if (0 == dev->pci->subsystem_vendor &&
292 0 == dev->pci->subsystem_device) {
9c8ced51
ST		 293 printk(KERN_INFO
294 "%s: Board has no valid PCIe Subsystem ID and can't\n"
295 "%s: be autodetected. Pass card=<n> insmod option\n"
296 "%s: to workaround that. Redirect complaints to the\n"
297 "%s: vendor of the TV card. Best regards,\n"
d19770e5
ST		 298 "%s: -- tux\n",
299 dev->name, dev->name, dev->name, dev->name, dev->name);
300 } else {
9c8ced51
ST		 301 printk(KERN_INFO
302 "%s: Your board isn't known (yet) to the driver.\n"
303 "%s: Try to pick one of the existing card configs via\n"
d19770e5
ST		 304 "%s: card=<n> insmod option. Updating to the latest\n"
305 "%s: version might help as well.\n",
306 dev->name, dev->name, dev->name, dev->name);
307 }
9c8ced51 308 printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n",
d19770e5
ST		 309 dev->name);
310 for (i = 0; i < cx23885_bcount; i++)
9c8ced51 311 printk(KERN_INFO "%s: card=%d -> %s\n",
d19770e5
ST		 312 dev->name, i, cx23885_boards[i].name);
313}
314
315static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
316{
317 struct tveeprom tv;
318
9c8ced51
ST		 319 tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv,
320 eeprom_data);
d19770e5 321
d19770e5 322 /* Make sure we support the board model */
9c8ced51 323 switch (tv.model) {
36396c89
MK		 324 case 71009:
325 /* WinTV-HVR1200 (PCIe, Retail, full height)
326 * DVB-T and basic analog */
327 case 71359:
328 /* WinTV-HVR1200 (PCIe, OEM, half height)
329 * DVB-T and basic analog */
330 case 71439:
331 /* WinTV-HVR1200 (PCIe, OEM, half height)
332 * DVB-T and basic analog */
333 case 71449:
334 /* WinTV-HVR1200 (PCIe, OEM, full height)
335 * DVB-T and basic analog */
336 case 71939:
337 /* WinTV-HVR1200 (PCIe, OEM, half height)
338 * DVB-T and basic analog */
339 case 71949:
340 /* WinTV-HVR1200 (PCIe, OEM, full height)
341 * DVB-T and basic analog */
342 case 71959:
343 /* WinTV-HVR1200 (PCIe, OEM, full height)
344 * DVB-T and basic analog */
345 case 71979:
346 /* WinTV-HVR1200 (PCIe, OEM, half height)
347 * DVB-T and basic analog */
348 case 71999:
349 /* WinTV-HVR1200 (PCIe, OEM, full height)
350 * DVB-T and basic analog */
9c8ced51
ST		 351 case 76601:
352 /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual
353 channel ATSC and MPEG2 HW Encoder */
354 case 77001:
355 /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC
356 and Basic analog */
357 case 77011:
358 /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC
359 and Basic analog */
360 case 77041:
361 /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM
362 and Basic analog */
363 case 77051:
364 /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM
365 and Basic analog */
366 case 78011:
367 /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM,
368 Dual channel ATSC and MPEG2 HW Encoder */
369 case 78501:
370 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
371 Dual channel ATSC and MPEG2 HW Encoder */
372 case 78521:
373 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
374 Dual channel ATSC and MPEG2 HW Encoder */
375 case 78531:
376 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM,
377 Dual channel ATSC and MPEG2 HW Encoder */
378 case 78631:
379 /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM,
380 Dual channel ATSC and MPEG2 HW Encoder */
381 case 79001:
382 /* WinTV-HVR1250 (PCIe, Retail, IR, full height,
383 ATSC and Basic analog */
384 case 79101:
385 /* WinTV-HVR1250 (PCIe, Retail, IR, half height,
386 ATSC and Basic analog */
387 case 79561:
388 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
389 ATSC and Basic analog */
390 case 79571:
391 /* WinTV-HVR1250 (PCIe, OEM, No IR, full height,
392 ATSC and Basic analog */
393 case 79671:
394 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
395 ATSC and Basic analog */
66762373
ST		 396 case 80019:
397 /* WinTV-HVR1400 (Express Card, Retail, IR,
398 * DVB-T and Basic analog */
36396c89
MK		 399 case 81509:
400 /* WinTV-HVR1700 (PCIe, OEM, No IR, half height)
401 * DVB-T and MPEG2 HW Encoder */
a780a31c 402 case 81519:
36396c89 403 /* WinTV-HVR1700 (PCIe, OEM, No IR, full height)
a780a31c 404 * DVB-T and MPEG2 HW Encoder */
d19770e5
ST		 405 break;
406 default:
9c8ced51
ST		 407 printk(KERN_WARNING "%s: warning: unknown hauppauge model #%d\n",
408 dev->name, tv.model);
d19770e5
ST		 409 break;
410 }
411
412 printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n",
413 dev->name, tv.model);
414}
415
d7cba043 416int cx23885_tuner_callback(void *priv, int component, int command, int arg)
8c70017f 417{
89ce2216
ST		 418 struct cx23885_tsport *port = priv;
419 struct cx23885_dev *dev = port->dev;
6df51690
ST		 420 u32 bitmask = 0;
421
89ce2216
ST		 422 if (command == XC2028_RESET_CLK)
423 return 0;
424
6df51690
ST		 425 if (command != 0) {
426 printk(KERN_ERR "%s(): Unknown command 0x%x.\n",
427 __func__, command);
428 return -EINVAL;
429 }
8c70017f 430
9c8ced51 431 switch (dev->board) {
90a71b1c
ST		 432 case CX23885_BOARD_HAUPPAUGE_HVR1400:
433 case CX23885_BOARD_HAUPPAUGE_HVR1500:
8c70017f 434 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
4c56b04a 435 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 436 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
90a71b1c 437 /* Tuner Reset Command */
4c56b04a 438 bitmask = 0x04;
6df51690
ST		 439 break;
440 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
aef2d186 441 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
4c56b04a
ST		 442 /* Two identical tuners on two different i2c buses,
443 * we need to reset the correct gpio. */
444 if (port->nr == 0)
445 bitmask = 0x01;
446 else if (port->nr == 1)
447 bitmask = 0x04;
8c70017f
ST		 448 break;
449 }
450
6df51690
ST		 451 if (bitmask) {
452 /* Drive the tuner into reset and back out */
453 cx_clear(GP0_IO, bitmask);
454 mdelay(200);
455 cx_set(GP0_IO, bitmask);
456 }
457
458 return 0;
8c70017f 459}
73c993a8 460
a6a3f140
ST		 461void cx23885_gpio_setup(struct cx23885_dev *dev)
462{
9c8ced51 463 switch (dev->board) {
a6a3f140
ST		 464 case CX23885_BOARD_HAUPPAUGE_HVR1250:
465 /* GPIO-0 cx24227 demodulator reset */
466 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
467 break;
07b4a835
MK		 468 case CX23885_BOARD_HAUPPAUGE_HVR1500:
469 /* GPIO-0 cx24227 demodulator */
470 /* GPIO-2 xc3028 tuner */
471
472 /* Put the parts into reset */
473 cx_set(GP0_IO, 0x00050000);
474 cx_clear(GP0_IO, 0x00000005);
475 msleep(5);
476
477 /* Bring the parts out of reset */
478 cx_set(GP0_IO, 0x00050005);
479 break;
d1987d55
ST		 480 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
481 /* GPIO-0 cx24227 demodulator reset */
482 /* GPIO-2 xc5000 tuner reset */
483 cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
484 break;
a6a3f140
ST		 485 case CX23885_BOARD_HAUPPAUGE_HVR1800:
486 /* GPIO-0 656_CLK */
487 /* GPIO-1 656_D0 */
488 /* GPIO-2 8295A Reset */
489 /* GPIO-3-10 cx23417 data0-7 */
490 /* GPIO-11-14 cx23417 addr0-3 */
491 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
492 /* GPIO-19 IR_RX */
3ba71d21 493
a589b665
ST		 494 /* CX23417 GPIO's */
495 /* EIO15 Zilog Reset */
496 /* EIO14 S5H1409/CX24227 Reset */
497
5206d6ec
ST		 498 /* Force the TDA8295A into reset and back */
499 cx_set(GP0_IO, 0x00040004);
500 mdelay(20);
501 cx_clear(GP0_IO, 0x00000004);
502 mdelay(20);
503 cx_set(GP0_IO, 0x00040004);
504 mdelay(20);
a6a3f140 505 break;
b3ea0166
ST		 506 case CX23885_BOARD_HAUPPAUGE_HVR1200:
507 /* GPIO-0 tda10048 demodulator reset */
508 /* GPIO-2 tda18271 tuner reset */
509
a780a31c
ST		 510 /* Put the parts into reset and back */
511 cx_set(GP0_IO, 0x00050000);
512 mdelay(20);
513 cx_clear(GP0_IO, 0x00000005);
514 mdelay(20);
515 cx_set(GP0_IO, 0x00050005);
516 break;
517 case CX23885_BOARD_HAUPPAUGE_HVR1700:
518 /* GPIO-0 TDA10048 demodulator reset */
519 /* GPIO-2 TDA8295A Reset */
520 /* GPIO-3-10 cx23417 data0-7 */
521 /* GPIO-11-14 cx23417 addr0-3 */
522 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
523
524 /* The following GPIO's are on the interna AVCore (cx25840) */
525 /* GPIO-19 IR_RX */
526 /* GPIO-20 IR_TX 416/DVBT Select */
527 /* GPIO-21 IIS DAT */
528 /* GPIO-22 IIS WCLK */
529 /* GPIO-23 IIS BCLK */
530
66762373
ST		 531 /* Put the parts into reset and back */
532 cx_set(GP0_IO, 0x00050000);
533 mdelay(20);
534 cx_clear(GP0_IO, 0x00000005);
535 mdelay(20);
536 cx_set(GP0_IO, 0x00050005);
537 break;
538 case CX23885_BOARD_HAUPPAUGE_HVR1400:
539 /* GPIO-0 Dibcom7000p demodulator reset */
540 /* GPIO-2 xc3028L tuner reset */
541 /* GPIO-13 LED */
542
b3ea0166
ST		 543 /* Put the parts into reset and back */
544 cx_set(GP0_IO, 0x00050000);
545 mdelay(20);
546 cx_clear(GP0_IO, 0x00000005);
547 mdelay(20);
548 cx_set(GP0_IO, 0x00050005);
549 break;
1ecc5aed
ST		 550 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
551 /* GPIO-0 xc5000 tuner reset i2c bus 0 */
552 /* GPIO-1 s5h1409 demod reset i2c bus 0 */
553 /* GPIO-2 xc5000 tuner reset i2c bus 1 */
554 /* GPIO-3 s5h1409 demod reset i2c bus 0 */
555
aef2d186
ST		 556 /* Put the parts into reset and back */
557 cx_set(GP0_IO, 0x000f0000);
558 mdelay(20);
559 cx_clear(GP0_IO, 0x0000000f);
560 mdelay(20);
561 cx_set(GP0_IO, 0x000f000f);
562 break;
563 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
564 /* GPIO-0 portb xc3028 reset */
565 /* GPIO-1 portb zl10353 reset */
566 /* GPIO-2 portc xc3028 reset */
567 /* GPIO-3 portc zl10353 reset */
568
1ecc5aed
ST		 569 /* Put the parts into reset and back */
570 cx_set(GP0_IO, 0x000f0000);
571 mdelay(20);
572 cx_clear(GP0_IO, 0x0000000f);
573 mdelay(20);
574 cx_set(GP0_IO, 0x000f000f);
575 break;
4c56b04a 576 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 577 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
4c56b04a
ST		 578 /* GPIO-2 xc3028 tuner reset */
579
580 /* The following GPIO's are on the internal AVCore (cx25840) */
581 /* GPIO-? zl10353 demod reset */
582
583 /* Put the parts into reset and back */
584 cx_set(GP0_IO, 0x00040000);
585 mdelay(20);
586 cx_clear(GP0_IO, 0x00000004);
587 mdelay(20);
588 cx_set(GP0_IO, 0x00040004);
589 break;
96318d0c 590 case CX23885_BOARD_TBS_6920:
579943f5 591 case CX23885_BOARD_TEVII_S470:
96318d0c
IL		 592 cx_write(MC417_CTL, 0x00000036);
593 cx_write(MC417_OEN, 0x00001000);
594 cx_write(MC417_RWD, 0x00001800);
595 break;
5a23b076
IL		 596 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
597 /* GPIO-0 INTA from CiMax1
598 GPIO-1 INTB from CiMax2
599 GPIO-2 reset chips
600 GPIO-3 to GPIO-10 data/addr for CA
601 GPIO-11 ~CS0 to CiMax1
602 GPIO-12 ~CS1 to CiMax2
603 GPIO-13 ADL0 load LSB addr
604 GPIO-14 ADL1 load MSB addr
605 GPIO-15 ~RDY from CiMax
606 GPIO-17 ~RD to CiMax
607 GPIO-18 ~WR to CiMax
608 */
609 cx_set(GP0_IO, 0x00040000); /* GPIO as out */
610 /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */
611 cx_clear(GP0_IO, 0x00030004);
612 mdelay(100);/* reset delay */
613 cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */
614 cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */
615 /* GPIO-15 IN as ~ACK, rest as OUT */
616 cx_write(MC417_OEN, 0x00001000);
617 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
618 cx_write(MC417_RWD, 0x0000c300);
619 /* enable irq */
620 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
621 break;
a6a3f140
ST		 622 }
623}
624
625int cx23885_ir_init(struct cx23885_dev *dev)
626{
627 switch (dev->board) {
628 case CX23885_BOARD_HAUPPAUGE_HVR1250:
07b4a835 629 case CX23885_BOARD_HAUPPAUGE_HVR1500:
d1987d55 630 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
a6a3f140 631 case CX23885_BOARD_HAUPPAUGE_HVR1800:
b3ea0166 632 case CX23885_BOARD_HAUPPAUGE_HVR1200:
66762373 633 case CX23885_BOARD_HAUPPAUGE_HVR1400:
a6a3f140
ST		 634 /* FIXME: Implement me */
635 break;
12886871
ST		 636 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
637 request_module("ir-kbd-i2c");
638 break;
a6a3f140
ST		 639 }
640
641 return 0;
642}
643
d19770e5
ST		 644void cx23885_card_setup(struct cx23885_dev *dev)
645{
a6a3f140
ST		 646 struct cx23885_tsport *ts1 = &dev->ts1;
647 struct cx23885_tsport *ts2 = &dev->ts2;
648
d19770e5
ST		 649 static u8 eeprom[256];
650
651 if (dev->i2c_bus[0].i2c_rc == 0) {
652 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
44a6481d
MK		 653 tveeprom_read(&dev->i2c_bus[0].i2c_client,
654 eeprom, sizeof(eeprom));
d19770e5
ST		 655 }
656
657 switch (dev->board) {
a77743bc 658 case CX23885_BOARD_HAUPPAUGE_HVR1250:
07b4a835 659 case CX23885_BOARD_HAUPPAUGE_HVR1500:
d1987d55 660 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
66762373 661 case CX23885_BOARD_HAUPPAUGE_HVR1400:
c88133ec
ST		 662 if (dev->i2c_bus[0].i2c_rc == 0)
663 hauppauge_eeprom(dev, eeprom+0x80);
664 break;
d19770e5
ST		 665 case CX23885_BOARD_HAUPPAUGE_HVR1800:
666 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
b3ea0166 667 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 668 case CX23885_BOARD_HAUPPAUGE_HVR1700:
d19770e5 669 if (dev->i2c_bus[0].i2c_rc == 0)
c88133ec 670 hauppauge_eeprom(dev, eeprom+0xc0);
d19770e5
ST		 671 break;
672 }
a6a3f140
ST		 673
674 switch (dev->board) {
335377b7 675 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
aef2d186 676 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
335377b7
MK		 677 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
678 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
679 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
680 /* break omitted intentionally */
a6a3f140
ST		 681 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
682 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
683 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
684 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
685 break;
a589b665
ST		 686 case CX23885_BOARD_HAUPPAUGE_HVR1800:
687 /* Defaults for VID B - Analog encoder */
688 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
689 ts1->gen_ctrl_val = 0x10e;
690 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
691 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
692
693 /* APB_TSVALERR_POL (active low)*/
694 ts1->vld_misc_val = 0x2000;
695 ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
696
697 /* Defaults for VID C */
698 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
699 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
700 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
96318d0c 701 break;
579943f5 702 case CX23885_BOARD_TEVII_S470:
96318d0c 703 case CX23885_BOARD_TBS_6920:
c9b8b04b 704 case CX23885_BOARD_DVBWORLD_2005:
96318d0c
IL		 705 ts1->gen_ctrl_val = 0x5; /* Parallel */
706 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
707 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
a589b665 708 break;
5a23b076
IL		 709 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
710 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
711 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
712 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
713 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
714 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
715 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
716 break;
a6a3f140 717 case CX23885_BOARD_HAUPPAUGE_HVR1250:
07b4a835 718 case CX23885_BOARD_HAUPPAUGE_HVR1500:
d1987d55 719 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
a6a3f140 720 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
b3ea0166 721 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 722 case CX23885_BOARD_HAUPPAUGE_HVR1700:
66762373 723 case CX23885_BOARD_HAUPPAUGE_HVR1400:
4c56b04a 724 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 725 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
a6a3f140
ST		 726 default:
727 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
728 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
729 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
730 }
731
ce89cfb4
ST		 732 /* Certain boards support analog, or require the avcore to be
733 * loaded, ensure this happens.
734 */
735 switch (dev->board) {
736 case CX23885_BOARD_HAUPPAUGE_HVR1800:
737 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
738 case CX23885_BOARD_HAUPPAUGE_HVR1700:
4c56b04a 739 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 740 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
5a23b076 741 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
e6574f2f
HV		 742 dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
743 &dev->i2c_bus[2].i2c_adap,
0d5a19f1 744 "cx25840", "cx25840", 0x88 >> 1);
cc26b076 745 v4l2_subdev_call(dev->sd_cx25840, core, load_fw);
ce89cfb4
ST		 746 break;
747 }
5a23b076
IL		 748
749 /* AUX-PLL 27MHz CLK */
750 switch (dev->board) {
751 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
752 netup_initialize(dev);
753 break;
754 }
d19770e5
ST		 755}
756
757/* ------------------------------------------------------------------ */
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