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V4L/DVB (12306): cx23885: Add support for ATSC/QAM on Hauppauge HVR-1850
[mirror_ubuntu-hirsute-kernel.git] / drivers / media / video / cx23885 / cx23885-core.c
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
ST		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/init.h>
23#include <linux/list.h>
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/kmod.h>
27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/interrupt.h>
30#include <linux/delay.h>
31#include <asm/div64.h>
32
33#include "cx23885.h"
5a23b076 34#include "cimax2.h"
d19770e5
ST		 35
36MODULE_DESCRIPTION("Driver for cx23885 based TV cards");
6d897616 37MODULE_AUTHOR("Steven Toth <stoth@linuxtv.org>");
d19770e5
ST		 38MODULE_LICENSE("GPL");
39
4513fc69 40static unsigned int debug;
9c8ced51
ST		 41module_param(debug, int, 0644);
42MODULE_PARM_DESC(debug, "enable debug messages");
d19770e5
ST		 43
44static unsigned int card[] = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
45module_param_array(card, int, NULL, 0444);
9c8ced51 46MODULE_PARM_DESC(card, "card type");
d19770e5 47
4513fc69
ST		 48#define dprintk(level, fmt, arg...)\
49 do { if (debug >= level)\
50 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
51 } while (0)
d19770e5
ST		 52
53static unsigned int cx23885_devcount;
54
55static DEFINE_MUTEX(devlist);
7b888014 56LIST_HEAD(cx23885_devlist);
d19770e5
ST		 57
58#define NO_SYNC_LINE (-1U)
59
d19770e5
ST		 60/* FIXME, these allocations will change when
61 * analog arrives. The be reviewed.
62 * CX23887 Assumptions
63 * 1 line = 16 bytes of CDT
64 * cmds size = 80
65 * cdt size = 16 * linesize
66 * iqsize = 64
67 * maxlines = 6
68 *
69 * Address Space:
70 * 0x00000000 0x00008fff FIFO clusters
71 * 0x00010000 0x000104af Channel Management Data Structures
72 * 0x000104b0 0x000104ff Free
73 * 0x00010500 0x000108bf 15 channels * iqsize
74 * 0x000108c0 0x000108ff Free
75 * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
76 * 15 channels * (iqsize + (maxlines * linesize))
77 * 0x00010ea0 0x00010xxx Free
78 */
79
7e994302 80static struct sram_channel cx23885_sram_channels[] = {
d19770e5 81 [SRAM_CH01] = {
69ad6e56
ST		 82 .name = "VID A",
83 .cmds_start = 0x10000,
d8d12b43
ST		 84 .ctrl_start = 0x10380,
85 .cdt = 0x104c0,
69ad6e56
ST		 86 .fifo_start = 0x40,
87 .fifo_size = 0x2800,
d19770e5
ST		 88 .ptr1_reg = DMA1_PTR1,
89 .ptr2_reg = DMA1_PTR2,
90 .cnt1_reg = DMA1_CNT1,
91 .cnt2_reg = DMA1_CNT2,
92 },
93 [SRAM_CH02] = {
94 .name = "ch2",
95 .cmds_start = 0x0,
96 .ctrl_start = 0x0,
97 .cdt = 0x0,
98 .fifo_start = 0x0,
99 .fifo_size = 0x0,
100 .ptr1_reg = DMA2_PTR1,
101 .ptr2_reg = DMA2_PTR2,
102 .cnt1_reg = DMA2_CNT1,
103 .cnt2_reg = DMA2_CNT2,
104 },
105 [SRAM_CH03] = {
69ad6e56
ST		 106 .name = "TS1 B",
107 .cmds_start = 0x100A0,
d8d12b43
ST		 108 .ctrl_start = 0x10400,
109 .cdt = 0x10580,
69ad6e56
ST		 110 .fifo_start = 0x5000,
111 .fifo_size = 0x1000,
d19770e5
ST		 112 .ptr1_reg = DMA3_PTR1,
113 .ptr2_reg = DMA3_PTR2,
114 .cnt1_reg = DMA3_CNT1,
115 .cnt2_reg = DMA3_CNT2,
116 },
117 [SRAM_CH04] = {
118 .name = "ch4",
119 .cmds_start = 0x0,
120 .ctrl_start = 0x0,
121 .cdt = 0x0,
122 .fifo_start = 0x0,
123 .fifo_size = 0x0,
124 .ptr1_reg = DMA4_PTR1,
125 .ptr2_reg = DMA4_PTR2,
126 .cnt1_reg = DMA4_CNT1,
127 .cnt2_reg = DMA4_CNT2,
128 },
129 [SRAM_CH05] = {
130 .name = "ch5",
131 .cmds_start = 0x0,
132 .ctrl_start = 0x0,
133 .cdt = 0x0,
134 .fifo_start = 0x0,
135 .fifo_size = 0x0,
136 .ptr1_reg = DMA5_PTR1,
137 .ptr2_reg = DMA5_PTR2,
138 .cnt1_reg = DMA5_CNT1,
139 .cnt2_reg = DMA5_CNT2,
140 },
141 [SRAM_CH06] = {
142 .name = "TS2 C",
143 .cmds_start = 0x10140,
d8d12b43
ST		 144 .ctrl_start = 0x10440,
145 .cdt = 0x105e0,
d19770e5
ST		 146 .fifo_start = 0x6000,
147 .fifo_size = 0x1000,
148 .ptr1_reg = DMA5_PTR1,
149 .ptr2_reg = DMA5_PTR2,
150 .cnt1_reg = DMA5_CNT1,
151 .cnt2_reg = DMA5_CNT2,
152 },
153 [SRAM_CH07] = {
154 .name = "ch7",
155 .cmds_start = 0x0,
156 .ctrl_start = 0x0,
157 .cdt = 0x0,
158 .fifo_start = 0x0,
159 .fifo_size = 0x0,
160 .ptr1_reg = DMA6_PTR1,
161 .ptr2_reg = DMA6_PTR2,
162 .cnt1_reg = DMA6_CNT1,
163 .cnt2_reg = DMA6_CNT2,
164 },
165 [SRAM_CH08] = {
166 .name = "ch8",
167 .cmds_start = 0x0,
168 .ctrl_start = 0x0,
169 .cdt = 0x0,
170 .fifo_start = 0x0,
171 .fifo_size = 0x0,
172 .ptr1_reg = DMA7_PTR1,
173 .ptr2_reg = DMA7_PTR2,
174 .cnt1_reg = DMA7_CNT1,
175 .cnt2_reg = DMA7_CNT2,
176 },
177 [SRAM_CH09] = {
178 .name = "ch9",
179 .cmds_start = 0x0,
180 .ctrl_start = 0x0,
181 .cdt = 0x0,
182 .fifo_start = 0x0,
183 .fifo_size = 0x0,
184 .ptr1_reg = DMA8_PTR1,
185 .ptr2_reg = DMA8_PTR2,
186 .cnt1_reg = DMA8_CNT1,
187 .cnt2_reg = DMA8_CNT2,
188 },
189};
190
7e994302
ST		 191static struct sram_channel cx23887_sram_channels[] = {
192 [SRAM_CH01] = {
193 .name = "VID A",
194 .cmds_start = 0x10000,
195 .ctrl_start = 0x105b0,
196 .cdt = 0x107b0,
197 .fifo_start = 0x40,
198 .fifo_size = 0x2800,
199 .ptr1_reg = DMA1_PTR1,
200 .ptr2_reg = DMA1_PTR2,
201 .cnt1_reg = DMA1_CNT1,
202 .cnt2_reg = DMA1_CNT2,
203 },
204 [SRAM_CH02] = {
205 .name = "ch2",
206 .cmds_start = 0x0,
207 .ctrl_start = 0x0,
208 .cdt = 0x0,
209 .fifo_start = 0x0,
210 .fifo_size = 0x0,
211 .ptr1_reg = DMA2_PTR1,
212 .ptr2_reg = DMA2_PTR2,
213 .cnt1_reg = DMA2_CNT1,
214 .cnt2_reg = DMA2_CNT2,
215 },
216 [SRAM_CH03] = {
217 .name = "TS1 B",
218 .cmds_start = 0x100A0,
219 .ctrl_start = 0x10630,
220 .cdt = 0x10870,
221 .fifo_start = 0x5000,
222 .fifo_size = 0x1000,
223 .ptr1_reg = DMA3_PTR1,
224 .ptr2_reg = DMA3_PTR2,
225 .cnt1_reg = DMA3_CNT1,
226 .cnt2_reg = DMA3_CNT2,
227 },
228 [SRAM_CH04] = {
229 .name = "ch4",
230 .cmds_start = 0x0,
231 .ctrl_start = 0x0,
232 .cdt = 0x0,
233 .fifo_start = 0x0,
234 .fifo_size = 0x0,
235 .ptr1_reg = DMA4_PTR1,
236 .ptr2_reg = DMA4_PTR2,
237 .cnt1_reg = DMA4_CNT1,
238 .cnt2_reg = DMA4_CNT2,
239 },
240 [SRAM_CH05] = {
241 .name = "ch5",
242 .cmds_start = 0x0,
243 .ctrl_start = 0x0,
244 .cdt = 0x0,
245 .fifo_start = 0x0,
246 .fifo_size = 0x0,
247 .ptr1_reg = DMA5_PTR1,
248 .ptr2_reg = DMA5_PTR2,
249 .cnt1_reg = DMA5_CNT1,
250 .cnt2_reg = DMA5_CNT2,
251 },
252 [SRAM_CH06] = {
253 .name = "TS2 C",
254 .cmds_start = 0x10140,
255 .ctrl_start = 0x10670,
256 .cdt = 0x108d0,
257 .fifo_start = 0x6000,
258 .fifo_size = 0x1000,
259 .ptr1_reg = DMA5_PTR1,
260 .ptr2_reg = DMA5_PTR2,
261 .cnt1_reg = DMA5_CNT1,
262 .cnt2_reg = DMA5_CNT2,
263 },
264 [SRAM_CH07] = {
265 .name = "ch7",
266 .cmds_start = 0x0,
267 .ctrl_start = 0x0,
268 .cdt = 0x0,
269 .fifo_start = 0x0,
270 .fifo_size = 0x0,
271 .ptr1_reg = DMA6_PTR1,
272 .ptr2_reg = DMA6_PTR2,
273 .cnt1_reg = DMA6_CNT1,
274 .cnt2_reg = DMA6_CNT2,
275 },
276 [SRAM_CH08] = {
277 .name = "ch8",
278 .cmds_start = 0x0,
279 .ctrl_start = 0x0,
280 .cdt = 0x0,
281 .fifo_start = 0x0,
282 .fifo_size = 0x0,
283 .ptr1_reg = DMA7_PTR1,
284 .ptr2_reg = DMA7_PTR2,
285 .cnt1_reg = DMA7_CNT1,
286 .cnt2_reg = DMA7_CNT2,
287 },
288 [SRAM_CH09] = {
289 .name = "ch9",
290 .cmds_start = 0x0,
291 .ctrl_start = 0x0,
292 .cdt = 0x0,
293 .fifo_start = 0x0,
294 .fifo_size = 0x0,
295 .ptr1_reg = DMA8_PTR1,
296 .ptr2_reg = DMA8_PTR2,
297 .cnt1_reg = DMA8_CNT1,
298 .cnt2_reg = DMA8_CNT2,
299 },
300};
301
d19770e5
ST		 302static int cx23885_risc_decode(u32 risc)
303{
304 static char *instr[16] = {
b1b81f1d
ST		 305 [RISC_SYNC >> 28] = "sync",
306 [RISC_WRITE >> 28] = "write",
307 [RISC_WRITEC >> 28] = "writec",
308 [RISC_READ >> 28] = "read",
309 [RISC_READC >> 28] = "readc",
310 [RISC_JUMP >> 28] = "jump",
311 [RISC_SKIP >> 28] = "skip",
312 [RISC_WRITERM >> 28] = "writerm",
313 [RISC_WRITECM >> 28] = "writecm",
314 [RISC_WRITECR >> 28] = "writecr",
d19770e5
ST		 315 };
316 static int incr[16] = {
b1b81f1d
ST		 317 [RISC_WRITE >> 28] = 3,
318 [RISC_JUMP >> 28] = 3,
319 [RISC_SKIP >> 28] = 1,
320 [RISC_SYNC >> 28] = 1,
321 [RISC_WRITERM >> 28] = 3,
322 [RISC_WRITECM >> 28] = 3,
323 [RISC_WRITECR >> 28] = 4,
d19770e5
ST		 324 };
325 static char *bits[] = {
326 "12", "13", "14", "resync",
327 "cnt0", "cnt1", "18", "19",
328 "20", "21", "22", "23",
329 "irq1", "irq2", "eol", "sol",
330 };
331 int i;
332
333 printk("0x%08x [ %s", risc,
334 instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
44a6481d 335 for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--)
d19770e5 336 if (risc & (1 << (i + 12)))
44a6481d 337 printk(" %s", bits[i]);
d19770e5
ST		 338 printk(" count=%d ]\n", risc & 0xfff);
339 return incr[risc >> 28] ? incr[risc >> 28] : 1;
340}
341
7b888014 342void cx23885_wakeup(struct cx23885_tsport *port,
39e75cfe 343 struct cx23885_dmaqueue *q, u32 count)
d19770e5
ST		 344{
345 struct cx23885_dev *dev = port->dev;
346 struct cx23885_buffer *buf;
347 int bc;
348
349 for (bc = 0;; bc++) {
350 if (list_empty(&q->active))
351 break;
352 buf = list_entry(q->active.next,
353 struct cx23885_buffer, vb.queue);
2e52f215 354
d19770e5
ST		 355 /* count comes from the hw and is is 16bit wide --
356 * this trick handles wrap-arounds correctly for
357 * up to 32767 buffers in flight... */
358 if ((s16) (count - buf->count) < 0)
359 break;
2e52f215 360
d19770e5 361 do_gettimeofday(&buf->vb.ts);
44a6481d 362 dprintk(2, "[%p/%d] wakeup reg=%d buf=%d\n", buf, buf->vb.i,
d19770e5 363 count, buf->count);
0fc0686e 364 buf->vb.state = VIDEOBUF_DONE;
d19770e5
ST		 365 list_del(&buf->vb.queue);
366 wake_up(&buf->vb.done);
367 }
9c8ced51 368 if (list_empty(&q->active))
d19770e5 369 del_timer(&q->timeout);
9c8ced51 370 else
44a6481d 371 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
d19770e5 372 if (bc != 1)
9c8ced51 373 printk(KERN_WARNING "%s: %d buffers handled (should be 1)\n",
22b4e64f 374 __func__, bc);
d19770e5 375}
d19770e5 376
7b888014 377int cx23885_sram_channel_setup(struct cx23885_dev *dev,
39e75cfe
AB		 378 struct sram_channel *ch,
379 unsigned int bpl, u32 risc)
d19770e5 380{
44a6481d 381 unsigned int i, lines;
d19770e5
ST		 382 u32 cdt;
383
9c8ced51 384 if (ch->cmds_start == 0) {
22b4e64f 385 dprintk(1, "%s() Erasing channel [%s]\n", __func__,
44a6481d 386 ch->name);
d19770e5
ST		 387 cx_write(ch->ptr1_reg, 0);
388 cx_write(ch->ptr2_reg, 0);
389 cx_write(ch->cnt2_reg, 0);
390 cx_write(ch->cnt1_reg, 0);
391 return 0;
392 } else {
22b4e64f 393 dprintk(1, "%s() Configuring channel [%s]\n", __func__,
44a6481d 394 ch->name);
d19770e5
ST		 395 }
396
397 bpl = (bpl + 7) & ~7; /* alignment */
398 cdt = ch->cdt;
399 lines = ch->fifo_size / bpl;
400 if (lines > 6)
401 lines = 6;
402 BUG_ON(lines < 2);
403
86ecc027
AV		 404 cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
405 cx_write(8 + 4, 8);
406 cx_write(8 + 8, 0);
d19770e5
ST		 407
408 /* write CDT */
409 for (i = 0; i < lines; i++) {
22b4e64f 410 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __func__, cdt + 16*i,
44a6481d 411 ch->fifo_start + bpl*i);
d19770e5
ST		 412 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
413 cx_write(cdt + 16*i + 4, 0);
414 cx_write(cdt + 16*i + 8, 0);
415 cx_write(cdt + 16*i + 12, 0);
416 }
417
418 /* write CMDS */
419 if (ch->jumponly)
9c8ced51 420 cx_write(ch->cmds_start + 0, 8);
d19770e5 421 else
9c8ced51 422 cx_write(ch->cmds_start + 0, risc);
d19770e5
ST		 423 cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */
424 cx_write(ch->cmds_start + 8, cdt);
425 cx_write(ch->cmds_start + 12, (lines*16) >> 3);
426 cx_write(ch->cmds_start + 16, ch->ctrl_start);
427 if (ch->jumponly)
9c8ced51 428 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
d19770e5
ST		 429 else
430 cx_write(ch->cmds_start + 20, 64 >> 2);
431 for (i = 24; i < 80; i += 4)
432 cx_write(ch->cmds_start + i, 0);
433
434 /* fill registers */
435 cx_write(ch->ptr1_reg, ch->fifo_start);
436 cx_write(ch->ptr2_reg, cdt);
437 cx_write(ch->cnt2_reg, (lines*16) >> 3);
9c8ced51 438 cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
d19770e5 439
9c8ced51 440 dprintk(2, "[bridge %d] sram setup %s: bpl=%d lines=%d\n",
e133be0f 441 dev->bridge,
d19770e5
ST		 442 ch->name,
443 bpl,
444 lines);
445
446 return 0;
447}
448
7b888014 449void cx23885_sram_channel_dump(struct cx23885_dev *dev,
39e75cfe 450 struct sram_channel *ch)
d19770e5
ST		 451{
452 static char *name[] = {
453 "init risc lo",
454 "init risc hi",
455 "cdt base",
456 "cdt size",
457 "iq base",
458 "iq size",
459 "risc pc lo",
460 "risc pc hi",
461 "iq wr ptr",
462 "iq rd ptr",
463 "cdt current",
464 "pci target lo",
465 "pci target hi",
466 "line / byte",
467 };
468 u32 risc;
44a6481d 469 unsigned int i, j, n;
d19770e5 470
9c8ced51 471 printk(KERN_WARNING "%s: %s - dma channel status dump\n",
d19770e5
ST		 472 dev->name, ch->name);
473 for (i = 0; i < ARRAY_SIZE(name); i++)
9c8ced51 474 printk(KERN_WARNING "%s: cmds: %-15s: 0x%08x\n",
d19770e5
ST		 475 dev->name, name[i],
476 cx_read(ch->cmds_start + 4*i));
477
478 for (i = 0; i < 4; i++) {
44a6481d 479 risc = cx_read(ch->cmds_start + 4 * (i + 14));
9c8ced51 480 printk(KERN_WARNING "%s: risc%d: ", dev->name, i);
d19770e5
ST		 481 cx23885_risc_decode(risc);
482 }
483 for (i = 0; i < (64 >> 2); i += n) {
44a6481d
MK		 484 risc = cx_read(ch->ctrl_start + 4 * i);
485 /* No consideration for bits 63-32 */
486
9c8ced51 487 printk(KERN_WARNING "%s: (0x%08x) iq %x: ", dev->name,
44a6481d 488 ch->ctrl_start + 4 * i, i);
d19770e5
ST		 489 n = cx23885_risc_decode(risc);
490 for (j = 1; j < n; j++) {
44a6481d 491 risc = cx_read(ch->ctrl_start + 4 * (i + j));
9c8ced51 492 printk(KERN_WARNING "%s: iq %x: 0x%08x [ arg #%d ]\n",
d19770e5
ST		 493 dev->name, i+j, risc, j);
494 }
495 }
496
9c8ced51 497 printk(KERN_WARNING "%s: fifo: 0x%08x -> 0x%x\n",
d19770e5 498 dev->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
9c8ced51 499 printk(KERN_WARNING "%s: ctrl: 0x%08x -> 0x%x\n",
44a6481d 500 dev->name, ch->ctrl_start, ch->ctrl_start + 6*16);
9c8ced51 501 printk(KERN_WARNING "%s: ptr1_reg: 0x%08x\n",
d19770e5 502 dev->name, cx_read(ch->ptr1_reg));
9c8ced51 503 printk(KERN_WARNING "%s: ptr2_reg: 0x%08x\n",
d19770e5 504 dev->name, cx_read(ch->ptr2_reg));
9c8ced51 505 printk(KERN_WARNING "%s: cnt1_reg: 0x%08x\n",
d19770e5 506 dev->name, cx_read(ch->cnt1_reg));
9c8ced51 507 printk(KERN_WARNING "%s: cnt2_reg: 0x%08x\n",
d19770e5
ST		 508 dev->name, cx_read(ch->cnt2_reg));
509}
510
39e75cfe
AB		 511static void cx23885_risc_disasm(struct cx23885_tsport *port,
512 struct btcx_riscmem *risc)
d19770e5
ST		 513{
514 struct cx23885_dev *dev = port->dev;
44a6481d 515 unsigned int i, j, n;
d19770e5 516
9c8ced51 517 printk(KERN_INFO "%s: risc disasm: %p [dma=0x%08lx]\n",
d19770e5
ST		 518 dev->name, risc->cpu, (unsigned long)risc->dma);
519 for (i = 0; i < (risc->size >> 2); i += n) {
9c8ced51 520 printk(KERN_INFO "%s: %04d: ", dev->name, i);
86ecc027 521 n = cx23885_risc_decode(le32_to_cpu(risc->cpu[i]));
d19770e5 522 for (j = 1; j < n; j++)
9c8ced51 523 printk(KERN_INFO "%s: %04d: 0x%08x [ arg #%d ]\n",
44a6481d 524 dev->name, i + j, risc->cpu[i + j], j);
86ecc027 525 if (risc->cpu[i] == cpu_to_le32(RISC_JUMP))
d19770e5
ST		 526 break;
527 }
528}
529
39e75cfe 530static void cx23885_shutdown(struct cx23885_dev *dev)
d19770e5
ST		 531{
532 /* disable RISC controller */
533 cx_write(DEV_CNTRL2, 0);
534
535 /* Disable all IR activity */
536 cx_write(IR_CNTRL_REG, 0);
537
538 /* Disable Video A/B activity */
539 cx_write(VID_A_DMA_CTL, 0);
540 cx_write(VID_B_DMA_CTL, 0);
541 cx_write(VID_C_DMA_CTL, 0);
542
543 /* Disable Audio activity */
544 cx_write(AUD_INT_DMA_CTL, 0);
545 cx_write(AUD_EXT_DMA_CTL, 0);
546
547 /* Disable Serial port */
548 cx_write(UART_CTL, 0);
549
550 /* Disable Interrupts */
551 cx_write(PCI_INT_MSK, 0);
552 cx_write(VID_A_INT_MSK, 0);
553 cx_write(VID_B_INT_MSK, 0);
554 cx_write(VID_C_INT_MSK, 0);
555 cx_write(AUDIO_INT_INT_MSK, 0);
556 cx_write(AUDIO_EXT_INT_MSK, 0);
557
558}
559
39e75cfe 560static void cx23885_reset(struct cx23885_dev *dev)
d19770e5 561{
22b4e64f 562 dprintk(1, "%s()\n", __func__);
d19770e5
ST		 563
564 cx23885_shutdown(dev);
565
566 cx_write(PCI_INT_STAT, 0xffffffff);
567 cx_write(VID_A_INT_STAT, 0xffffffff);
568 cx_write(VID_B_INT_STAT, 0xffffffff);
569 cx_write(VID_C_INT_STAT, 0xffffffff);
570 cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
571 cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
572 cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
ecda5966 573 cx_write(PAD_CTRL, 0x00500300);
d19770e5
ST		 574
575 mdelay(100);
576
7b888014
ST		 577 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH01],
578 720*4, 0);
579 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH02], 128, 0);
580 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH03],
581 188*4, 0);
582 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH04], 128, 0);
583 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH05], 128, 0);
584 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH06],
585 188*4, 0);
586 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH07], 128, 0);
587 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH08], 128, 0);
588 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH09], 128, 0);
d19770e5 589
a6a3f140 590 cx23885_gpio_setup(dev);
d19770e5
ST		 591}
592
593
594static int cx23885_pci_quirks(struct cx23885_dev *dev)
595{
22b4e64f 596 dprintk(1, "%s()\n", __func__);
d19770e5 597
2df9a4c2
ST		 598 /* The cx23885 bridge has a weird bug which causes NMI to be asserted
599 * when DMA begins if RDR_TLCTL0 bit4 is not cleared. It does not
600 * occur on the cx23887 bridge.
601 */
9c8ced51 602 if (dev->bridge == CX23885_BRIDGE_885)
d19770e5 603 cx_clear(RDR_TLCTL0, 1 << 4);
4823e9ee 604
d19770e5
ST		 605 return 0;
606}
607
608static int get_resources(struct cx23885_dev *dev)
609{
9c8ced51
ST		 610 if (request_mem_region(pci_resource_start(dev->pci, 0),
611 pci_resource_len(dev->pci, 0),
44a6481d 612 dev->name))
d19770e5
ST		 613 return 0;
614
615 printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx\n",
9c8ced51 616 dev->name, (unsigned long long)pci_resource_start(dev->pci, 0));
d19770e5
ST		 617
618 return -EBUSY;
619}
620
621static void cx23885_timeout(unsigned long data);
7b888014 622int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
39e75cfe 623 u32 reg, u32 mask, u32 value);
d19770e5 624
9c8ced51
ST		 625static int cx23885_init_tsport(struct cx23885_dev *dev,
626 struct cx23885_tsport *port, int portno)
d19770e5 627{
22b4e64f 628 dprintk(1, "%s(portno=%d)\n", __func__, portno);
a6a3f140
ST		 629
630 /* Transport bus init dma queue - Common settings */
631 port->dma_ctl_val = 0x11; /* Enable RISC controller and Fifo */
632 port->ts_int_msk_val = 0x1111; /* TS port bits for RISC */
b1b81f1d
ST		 633 port->vld_misc_val = 0x0;
634 port->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4);
a6a3f140
ST		 635
636 spin_lock_init(&port->slock);
637 port->dev = dev;
638 port->nr = portno;
639
640 INIT_LIST_HEAD(&port->mpegq.active);
641 INIT_LIST_HEAD(&port->mpegq.queued);
642 port->mpegq.timeout.function = cx23885_timeout;
643 port->mpegq.timeout.data = (unsigned long)port;
644 init_timer(&port->mpegq.timeout);
645
d782ffa2 646 mutex_init(&port->frontends.lock);
7bdf84fc 647 INIT_LIST_HEAD(&port->frontends.felist);
d782ffa2
ST		 648 port->frontends.active_fe_id = 0;
649
a739a7e4
ST		 650 /* This should be hardcoded allow a single frontend
651 * attachment to this tsport, keeping the -dvb.c
652 * code clean and safe.
653 */
9c8ced51 654 if (!port->num_frontends)
a739a7e4
ST		 655 port->num_frontends = 1;
656
9c8ced51 657 switch (portno) {
a6a3f140
ST		 658 case 1:
659 port->reg_gpcnt = VID_B_GPCNT;
660 port->reg_gpcnt_ctl = VID_B_GPCNT_CTL;
661 port->reg_dma_ctl = VID_B_DMA_CTL;
662 port->reg_lngth = VID_B_LNGTH;
663 port->reg_hw_sop_ctrl = VID_B_HW_SOP_CTL;
664 port->reg_gen_ctrl = VID_B_GEN_CTL;
665 port->reg_bd_pkt_status = VID_B_BD_PKT_STATUS;
666 port->reg_sop_status = VID_B_SOP_STATUS;
667 port->reg_fifo_ovfl_stat = VID_B_FIFO_OVFL_STAT;
668 port->reg_vld_misc = VID_B_VLD_MISC;
669 port->reg_ts_clk_en = VID_B_TS_CLK_EN;
670 port->reg_src_sel = VID_B_SRC_SEL;
671 port->reg_ts_int_msk = VID_B_INT_MSK;
b1b81f1d 672 port->reg_ts_int_stat = VID_B_INT_STAT;
a6a3f140
ST		 673 port->sram_chno = SRAM_CH03; /* VID_B */
674 port->pci_irqmask = 0x02; /* VID_B bit1 */
675 break;
676 case 2:
677 port->reg_gpcnt = VID_C_GPCNT;
678 port->reg_gpcnt_ctl = VID_C_GPCNT_CTL;
679 port->reg_dma_ctl = VID_C_DMA_CTL;
680 port->reg_lngth = VID_C_LNGTH;
681 port->reg_hw_sop_ctrl = VID_C_HW_SOP_CTL;
682 port->reg_gen_ctrl = VID_C_GEN_CTL;
683 port->reg_bd_pkt_status = VID_C_BD_PKT_STATUS;
684 port->reg_sop_status = VID_C_SOP_STATUS;
685 port->reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
686 port->reg_vld_misc = VID_C_VLD_MISC;
687 port->reg_ts_clk_en = VID_C_TS_CLK_EN;
688 port->reg_src_sel = 0;
689 port->reg_ts_int_msk = VID_C_INT_MSK;
690 port->reg_ts_int_stat = VID_C_INT_STAT;
691 port->sram_chno = SRAM_CH06; /* VID_C */
692 port->pci_irqmask = 0x04; /* VID_C bit2 */
d19770e5 693 break;
a6a3f140
ST		 694 default:
695 BUG();
d19770e5
ST		 696 }
697
a6a3f140
ST		 698 cx23885_risc_stopper(dev->pci, &port->mpegq.stopper,
699 port->reg_dma_ctl, port->dma_ctl_val, 0x00);
700
d19770e5
ST		 701 return 0;
702}
703
0ac5881a
ST		 704static void cx23885_dev_checkrevision(struct cx23885_dev *dev)
705{
706 switch (cx_read(RDR_CFG2) & 0xff) {
707 case 0x00:
708 /* cx23885 */
709 dev->hwrevision = 0xa0;
710 break;
711 case 0x01:
712 /* CX23885-12Z */
713 dev->hwrevision = 0xa1;
714 break;
715 case 0x02:
716 /* CX23885-13Z */
717 dev->hwrevision = 0xb0;
718 break;
719 case 0x03:
720 /* CX23888-22Z */
721 dev->hwrevision = 0xc0;
722 break;
723 case 0x0e:
724 /* CX23887-15Z */
725 dev->hwrevision = 0xc0;
726 case 0x0f:
727 /* CX23887-14Z */
728 dev->hwrevision = 0xb1;
729 break;
730 default:
731 printk(KERN_ERR "%s() New hardware revision found 0x%x\n",
22b4e64f 732 __func__, dev->hwrevision);
0ac5881a
ST		 733 }
734 if (dev->hwrevision)
735 printk(KERN_INFO "%s() Hardware revision = 0x%02x\n",
22b4e64f 736 __func__, dev->hwrevision);
0ac5881a
ST		 737 else
738 printk(KERN_ERR "%s() Hardware revision unknown 0x%x\n",
22b4e64f 739 __func__, dev->hwrevision);
0ac5881a
ST		 740}
741
d19770e5
ST		 742static int cx23885_dev_setup(struct cx23885_dev *dev)
743{
744 int i;
745
746 mutex_init(&dev->lock);
747
748 atomic_inc(&dev->refcount);
749
750 dev->nr = cx23885_devcount++;
579f1163
ST		 751 sprintf(dev->name, "cx23885[%d]", dev->nr);
752
753 mutex_lock(&devlist);
754 list_add_tail(&dev->devlist, &cx23885_devlist);
755 mutex_unlock(&devlist);
756
757 /* Configure the internal memory */
9c8ced51 758 if (dev->pci->device == 0x8880) {
579f1163 759 dev->bridge = CX23885_BRIDGE_887;
c7712613
ST		 760 /* Apply a sensible clock frequency for the PCIe bridge */
761 dev->clk_freq = 25000000;
7e994302 762 dev->sram_channels = cx23887_sram_channels;
579f1163 763 } else
9c8ced51 764 if (dev->pci->device == 0x8852) {
579f1163 765 dev->bridge = CX23885_BRIDGE_885;
c7712613
ST		 766 /* Apply a sensible clock frequency for the PCIe bridge */
767 dev->clk_freq = 28000000;
7e994302 768 dev->sram_channels = cx23885_sram_channels;
579f1163
ST		 769 } else
770 BUG();
771
772 dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
22b4e64f 773 __func__, dev->bridge);
579f1163
ST		 774
775 /* board config */
776 dev->board = UNSET;
777 if (card[dev->nr] < cx23885_bcount)
778 dev->board = card[dev->nr];
779 for (i = 0; UNSET == dev->board && i < cx23885_idcount; i++)
780 if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
781 dev->pci->subsystem_device == cx23885_subids[i].subdevice)
782 dev->board = cx23885_subids[i].card;
783 if (UNSET == dev->board) {
784 dev->board = CX23885_BOARD_UNKNOWN;
785 cx23885_card_list(dev);
786 }
787
c7712613
ST		 788 /* If the user specific a clk freq override, apply it */
789 if (cx23885_boards[dev->board].clk_freq > 0)
790 dev->clk_freq = cx23885_boards[dev->board].clk_freq;
791
d19770e5
ST		 792 dev->pci_bus = dev->pci->bus->number;
793 dev->pci_slot = PCI_SLOT(dev->pci->devfn);
794 dev->pci_irqmask = 0x001f00;
5a23b076
IL		 795 if (cx23885_boards[dev->board].cimax > 0)
796 dev->pci_irqmask |= 0x01800000; /* for CiMaxes */
d19770e5
ST		 797
798 /* External Master 1 Bus */
799 dev->i2c_bus[0].nr = 0;
800 dev->i2c_bus[0].dev = dev;
801 dev->i2c_bus[0].reg_stat = I2C1_STAT;
802 dev->i2c_bus[0].reg_ctrl = I2C1_CTRL;
803 dev->i2c_bus[0].reg_addr = I2C1_ADDR;
804 dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
805 dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
806 dev->i2c_bus[0].i2c_period = (0x9d << 24); /* 100kHz */
807
808 /* External Master 2 Bus */
809 dev->i2c_bus[1].nr = 1;
810 dev->i2c_bus[1].dev = dev;
811 dev->i2c_bus[1].reg_stat = I2C2_STAT;
812 dev->i2c_bus[1].reg_ctrl = I2C2_CTRL;
813 dev->i2c_bus[1].reg_addr = I2C2_ADDR;
814 dev->i2c_bus[1].reg_rdata = I2C2_RDATA;
815 dev->i2c_bus[1].reg_wdata = I2C2_WDATA;
816 dev->i2c_bus[1].i2c_period = (0x9d << 24); /* 100kHz */
817
818 /* Internal Master 3 Bus */
819 dev->i2c_bus[2].nr = 2;
820 dev->i2c_bus[2].dev = dev;
821 dev->i2c_bus[2].reg_stat = I2C3_STAT;
822 dev->i2c_bus[2].reg_ctrl = I2C3_CTRL;
a2129af5 823 dev->i2c_bus[2].reg_addr = I2C3_ADDR;
d19770e5
ST		 824 dev->i2c_bus[2].reg_rdata = I2C3_RDATA;
825 dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
826 dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */
827
b1b81f1d
ST		 828 if ((cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) ||
829 (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER))
a6a3f140 830 cx23885_init_tsport(dev, &dev->ts1, 1);
579f1163 831
b1b81f1d
ST		 832 if ((cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) ||
833 (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER))
a6a3f140 834 cx23885_init_tsport(dev, &dev->ts2, 2);
d19770e5 835
d19770e5
ST		 836 if (get_resources(dev) < 0) {
837 printk(KERN_ERR "CORE %s No more PCIe resources for "
44a6481d
MK		 838 "subsystem: %04x:%04x\n",
839 dev->name, dev->pci->subsystem_vendor,
840 dev->pci->subsystem_device);
d19770e5
ST		 841
842 cx23885_devcount--;
fcf94c89 843 return -ENODEV;
d19770e5
ST		 844 }
845
d19770e5 846 /* PCIe stuff */
9c8ced51
ST		 847 dev->lmmio = ioremap(pci_resource_start(dev->pci, 0),
848 pci_resource_len(dev->pci, 0));
d19770e5
ST		 849
850 dev->bmmio = (u8 __iomem *)dev->lmmio;
851
d19770e5 852 printk(KERN_INFO "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
44a6481d
MK		 853 dev->name, dev->pci->subsystem_vendor,
854 dev->pci->subsystem_device, cx23885_boards[dev->board].name,
855 dev->board, card[dev->nr] == dev->board ?
856 "insmod option" : "autodetected");
d19770e5 857
4823e9ee
ST		 858 cx23885_pci_quirks(dev);
859
7b888014
ST		 860 /* Assume some sensible defaults */
861 dev->tuner_type = cx23885_boards[dev->board].tuner_type;
862 dev->tuner_addr = cx23885_boards[dev->board].tuner_addr;
863 dev->radio_type = cx23885_boards[dev->board].radio_type;
864 dev->radio_addr = cx23885_boards[dev->board].radio_addr;
865
866 dprintk(1, "%s() tuner_type = 0x%x tuner_addr = 0x%x\n",
22b4e64f 867 __func__, dev->tuner_type, dev->tuner_addr);
7b888014 868 dprintk(1, "%s() radio_type = 0x%x radio_addr = 0x%x\n",
22b4e64f 869 __func__, dev->radio_type, dev->radio_addr);
7b888014 870
f659c513
ST		 871 /* The cx23417 encoder has GPIO's that need to be initialised
872 * before DVB, so that demodulators and tuners are out of
873 * reset before DVB uses them.
874 */
875 if ((cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) ||
876 (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER))
877 cx23885_mc417_init(dev);
878
d19770e5
ST		 879 /* init hardware */
880 cx23885_reset(dev);
881
882 cx23885_i2c_register(&dev->i2c_bus[0]);
883 cx23885_i2c_register(&dev->i2c_bus[1]);
884 cx23885_i2c_register(&dev->i2c_bus[2]);
d19770e5 885 cx23885_card_setup(dev);
7c9fc9d5 886 call_all(dev, tuner, s_standby);
d19770e5
ST		 887 cx23885_ir_init(dev);
888
7b888014
ST		 889 if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO) {
890 if (cx23885_video_register(dev) < 0) {
891 printk(KERN_ERR "%s() Failed to register analog "
22b4e64f 892 "video adapters on VID_A\n", __func__);
7b888014
ST		 893 }
894 }
895
896 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
a6a3f140
ST		 897 if (cx23885_dvb_register(&dev->ts1) < 0) {
898 printk(KERN_ERR "%s() Failed to register dvb adapters on VID_B\n",
22b4e64f 899 __func__);
a6a3f140 900 }
b1b81f1d
ST		 901 } else
902 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
903 if (cx23885_417_register(dev) < 0) {
904 printk(KERN_ERR
905 "%s() Failed to register 417 on VID_B\n",
906 __func__);
907 }
579f1163
ST		 908 }
909
7b888014 910 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
a6a3f140 911 if (cx23885_dvb_register(&dev->ts2) < 0) {
b1b81f1d
ST		 912 printk(KERN_ERR
913 "%s() Failed to register dvb on VID_C\n",
914 __func__);
915 }
916 } else
917 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER) {
918 if (cx23885_417_register(dev) < 0) {
919 printk(KERN_ERR
920 "%s() Failed to register 417 on VID_C\n",
22b4e64f 921 __func__);
a6a3f140 922 }
d19770e5
ST		 923 }
924
0ac5881a
ST		 925 cx23885_dev_checkrevision(dev);
926
d19770e5 927 return 0;
d19770e5
ST		 928}
929
39e75cfe 930static void cx23885_dev_unregister(struct cx23885_dev *dev)
d19770e5 931{
9c8ced51
ST		 932 release_mem_region(pci_resource_start(dev->pci, 0),
933 pci_resource_len(dev->pci, 0));
d19770e5
ST		 934
935 if (!atomic_dec_and_test(&dev->refcount))
936 return;
937
7b888014
ST		 938 if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO)
939 cx23885_video_unregister(dev);
940
b1b81f1d 941 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
a6a3f140
ST		 942 cx23885_dvb_unregister(&dev->ts1);
943
b1b81f1d
ST		 944 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
945 cx23885_417_unregister(dev);
946
947 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
a6a3f140
ST		 948 cx23885_dvb_unregister(&dev->ts2);
949
b1b81f1d
ST		 950 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
951 cx23885_417_unregister(dev);
952
d19770e5
ST		 953 cx23885_i2c_unregister(&dev->i2c_bus[2]);
954 cx23885_i2c_unregister(&dev->i2c_bus[1]);
955 cx23885_i2c_unregister(&dev->i2c_bus[0]);
956
957 iounmap(dev->lmmio);
958}
959
9c8ced51 960static __le32 *cx23885_risc_field(__le32 *rp, struct scatterlist *sglist,
44a6481d
MK		 961 unsigned int offset, u32 sync_line,
962 unsigned int bpl, unsigned int padding,
963 unsigned int lines)
d19770e5
ST		 964{
965 struct scatterlist *sg;
44a6481d 966 unsigned int line, todo;
d19770e5
ST		 967
968 /* sync instruction */
969 if (sync_line != NO_SYNC_LINE)
970 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
971
972 /* scan lines */
973 sg = sglist;
974 for (line = 0; line < lines; line++) {
975 while (offset && offset >= sg_dma_len(sg)) {
976 offset -= sg_dma_len(sg);
977 sg++;
978 }
979 if (bpl <= sg_dma_len(sg)-offset) {
980 /* fits into current chunk */
9c8ced51
ST		 981 *(rp++) = cpu_to_le32(RISC_WRITE|RISC_SOL|RISC_EOL|bpl);
982 *(rp++) = cpu_to_le32(sg_dma_address(sg)+offset);
983 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
984 offset += bpl;
d19770e5
ST		 985 } else {
986 /* scanline needs to be split */
987 todo = bpl;
9c8ced51 988 *(rp++) = cpu_to_le32(RISC_WRITE|RISC_SOL|
d19770e5 989 (sg_dma_len(sg)-offset));
9c8ced51
ST		 990 *(rp++) = cpu_to_le32(sg_dma_address(sg)+offset);
991 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
d19770e5
ST		 992 todo -= (sg_dma_len(sg)-offset);
993 offset = 0;
994 sg++;
995 while (todo > sg_dma_len(sg)) {
9c8ced51 996 *(rp++) = cpu_to_le32(RISC_WRITE|
d19770e5 997 sg_dma_len(sg));
9c8ced51
ST		 998 *(rp++) = cpu_to_le32(sg_dma_address(sg));
999 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
d19770e5
ST		 1000 todo -= sg_dma_len(sg);
1001 sg++;
1002 }
9c8ced51
ST		 1003 *(rp++) = cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
1004 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1005 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
d19770e5
ST		 1006 offset += todo;
1007 }
1008 offset += padding;
1009 }
1010
1011 return rp;
1012}
1013
7b888014
ST		 1014int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
1015 struct scatterlist *sglist, unsigned int top_offset,
1016 unsigned int bottom_offset, unsigned int bpl,
1017 unsigned int padding, unsigned int lines)
1018{
1019 u32 instructions, fields;
d8eaa58b 1020 __le32 *rp;
7b888014
ST		 1021 int rc;
1022
1023 fields = 0;
1024 if (UNSET != top_offset)
1025 fields++;
1026 if (UNSET != bottom_offset)
1027 fields++;
1028
1029 /* estimate risc mem: worst case is one write per page border +
1030 one write per scan line + syncs + jump (all 2 dwords). Padding
1031 can cause next bpl to start close to a page border. First DMA
1032 region may be smaller than PAGE_SIZE */
1033 /* write and jump need and extra dword */
9c8ced51
ST		 1034 instructions = fields * (1 + ((bpl + padding) * lines)
1035 / PAGE_SIZE + lines);
7b888014 1036 instructions += 2;
9c8ced51
ST		 1037 rc = btcx_riscmem_alloc(pci, risc, instructions*12);
1038 if (rc < 0)
7b888014
ST		 1039 return rc;
1040
1041 /* write risc instructions */
1042 rp = risc->cpu;
1043 if (UNSET != top_offset)
1044 rp = cx23885_risc_field(rp, sglist, top_offset, 0,
1045 bpl, padding, lines);
1046 if (UNSET != bottom_offset)
1047 rp = cx23885_risc_field(rp, sglist, bottom_offset, 0x200,
1048 bpl, padding, lines);
1049
1050 /* save pointer to jmp instruction address */
1051 risc->jmp = rp;
9c8ced51 1052 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
7b888014
ST		 1053 return 0;
1054}
d19770e5 1055
39e75cfe
AB		 1056static int cx23885_risc_databuffer(struct pci_dev *pci,
1057 struct btcx_riscmem *risc,
1058 struct scatterlist *sglist,
1059 unsigned int bpl,
1060 unsigned int lines)
d19770e5
ST		 1061{
1062 u32 instructions;
d8eaa58b 1063 __le32 *rp;
d19770e5
ST		 1064 int rc;
1065
1066 /* estimate risc mem: worst case is one write per page border +
1067 one write per scan line + syncs + jump (all 2 dwords). Here
1068 there is no padding and no sync. First DMA region may be smaller
1069 than PAGE_SIZE */
1070 /* Jump and write need an extra dword */
1071 instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
1072 instructions += 1;
1073
9c8ced51
ST		 1074 rc = btcx_riscmem_alloc(pci, risc, instructions*12);
1075 if (rc < 0)
d19770e5
ST		 1076 return rc;
1077
1078 /* write risc instructions */
1079 rp = risc->cpu;
1080 rp = cx23885_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines);
1081
1082 /* save pointer to jmp instruction address */
1083 risc->jmp = rp;
9c8ced51 1084 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
d19770e5
ST		 1085 return 0;
1086}
1087
7b888014 1088int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
39e75cfe 1089 u32 reg, u32 mask, u32 value)
d19770e5 1090{
d8eaa58b 1091 __le32 *rp;
d19770e5
ST		 1092 int rc;
1093
9c8ced51
ST		 1094 rc = btcx_riscmem_alloc(pci, risc, 4*16);
1095 if (rc < 0)
d19770e5
ST		 1096 return rc;
1097
1098 /* write risc instructions */
1099 rp = risc->cpu;
d19770e5
ST		 1100 *(rp++) = cpu_to_le32(RISC_WRITECR | RISC_IRQ2);
1101 *(rp++) = cpu_to_le32(reg);
1102 *(rp++) = cpu_to_le32(value);
1103 *(rp++) = cpu_to_le32(mask);
1104 *(rp++) = cpu_to_le32(RISC_JUMP);
1105 *(rp++) = cpu_to_le32(risc->dma);
1106 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1107 return 0;
1108}
1109
1110void cx23885_free_buffer(struct videobuf_queue *q, struct cx23885_buffer *buf)
1111{
409d84f8
TP		 1112 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
1113
d19770e5 1114 BUG_ON(in_interrupt());
44a6481d 1115 videobuf_waiton(&buf->vb, 0, 0);
409d84f8
TP		 1116 videobuf_dma_unmap(q, dma);
1117 videobuf_dma_free(dma);
a920e42f 1118 btcx_riscmem_free(to_pci_dev(q->dev), &buf->risc);
0fc0686e 1119 buf->vb.state = VIDEOBUF_NEEDS_INIT;
d19770e5
ST		 1120}
1121
7b888014
ST		 1122static void cx23885_tsport_reg_dump(struct cx23885_tsport *port)
1123{
1124 struct cx23885_dev *dev = port->dev;
1125
22b4e64f
HH		 1126 dprintk(1, "%s() Register Dump\n", __func__);
1127 dprintk(1, "%s() DEV_CNTRL2 0x%08X\n", __func__,
7b888014 1128 cx_read(DEV_CNTRL2));
22b4e64f 1129 dprintk(1, "%s() PCI_INT_MSK 0x%08X\n", __func__,
7b888014 1130 cx_read(PCI_INT_MSK));
22b4e64f 1131 dprintk(1, "%s() AUD_INT_INT_MSK 0x%08X\n", __func__,
7b888014 1132 cx_read(AUDIO_INT_INT_MSK));
22b4e64f 1133 dprintk(1, "%s() AUD_INT_DMA_CTL 0x%08X\n", __func__,
7b888014 1134 cx_read(AUD_INT_DMA_CTL));
22b4e64f 1135 dprintk(1, "%s() AUD_EXT_INT_MSK 0x%08X\n", __func__,
7b888014 1136 cx_read(AUDIO_EXT_INT_MSK));
22b4e64f 1137 dprintk(1, "%s() AUD_EXT_DMA_CTL 0x%08X\n", __func__,
7b888014 1138 cx_read(AUD_EXT_DMA_CTL));
22b4e64f 1139 dprintk(1, "%s() PAD_CTRL 0x%08X\n", __func__,
7b888014 1140 cx_read(PAD_CTRL));
22b4e64f 1141 dprintk(1, "%s() ALT_PIN_OUT_SEL 0x%08X\n", __func__,
7b888014 1142 cx_read(ALT_PIN_OUT_SEL));
22b4e64f 1143 dprintk(1, "%s() GPIO2 0x%08X\n", __func__,
7b888014 1144 cx_read(GPIO2));
22b4e64f 1145 dprintk(1, "%s() gpcnt(0x%08X) 0x%08X\n", __func__,
7b888014 1146 port->reg_gpcnt, cx_read(port->reg_gpcnt));
22b4e64f 1147 dprintk(1, "%s() gpcnt_ctl(0x%08X) 0x%08x\n", __func__,
7b888014 1148 port->reg_gpcnt_ctl, cx_read(port->reg_gpcnt_ctl));
22b4e64f 1149 dprintk(1, "%s() dma_ctl(0x%08X) 0x%08x\n", __func__,
7b888014 1150 port->reg_dma_ctl, cx_read(port->reg_dma_ctl));
7b913908
ST		 1151 if (port->reg_src_sel)
1152 dprintk(1, "%s() src_sel(0x%08X) 0x%08x\n", __func__,
1153 port->reg_src_sel, cx_read(port->reg_src_sel));
22b4e64f 1154 dprintk(1, "%s() lngth(0x%08X) 0x%08x\n", __func__,
7b888014 1155 port->reg_lngth, cx_read(port->reg_lngth));
22b4e64f 1156 dprintk(1, "%s() hw_sop_ctrl(0x%08X) 0x%08x\n", __func__,
7b888014 1157 port->reg_hw_sop_ctrl, cx_read(port->reg_hw_sop_ctrl));
22b4e64f 1158 dprintk(1, "%s() gen_ctrl(0x%08X) 0x%08x\n", __func__,
7b888014 1159 port->reg_gen_ctrl, cx_read(port->reg_gen_ctrl));
22b4e64f 1160 dprintk(1, "%s() bd_pkt_status(0x%08X) 0x%08x\n", __func__,
7b888014 1161 port->reg_bd_pkt_status, cx_read(port->reg_bd_pkt_status));
22b4e64f 1162 dprintk(1, "%s() sop_status(0x%08X) 0x%08x\n", __func__,
7b888014 1163 port->reg_sop_status, cx_read(port->reg_sop_status));
22b4e64f 1164 dprintk(1, "%s() fifo_ovfl_stat(0x%08X) 0x%08x\n", __func__,
7b888014 1165 port->reg_fifo_ovfl_stat, cx_read(port->reg_fifo_ovfl_stat));
22b4e64f 1166 dprintk(1, "%s() vld_misc(0x%08X) 0x%08x\n", __func__,
7b888014 1167 port->reg_vld_misc, cx_read(port->reg_vld_misc));
22b4e64f 1168 dprintk(1, "%s() ts_clk_en(0x%08X) 0x%08x\n", __func__,
7b888014 1169 port->reg_ts_clk_en, cx_read(port->reg_ts_clk_en));
22b4e64f 1170 dprintk(1, "%s() ts_int_msk(0x%08X) 0x%08x\n", __func__,
7b888014
ST		 1171 port->reg_ts_int_msk, cx_read(port->reg_ts_int_msk));
1172}
1173
d19770e5 1174static int cx23885_start_dma(struct cx23885_tsport *port,
44a6481d
MK		 1175 struct cx23885_dmaqueue *q,
1176 struct cx23885_buffer *buf)
d19770e5
ST		 1177{
1178 struct cx23885_dev *dev = port->dev;
a589b665 1179 u32 reg;
d19770e5 1180
22b4e64f 1181 dprintk(1, "%s() w: %d, h: %d, f: %d\n", __func__,
44a6481d 1182 buf->vb.width, buf->vb.height, buf->vb.field);
d19770e5 1183
d8d12b43
ST		 1184 /* Stop the fifo and risc engine for this port */
1185 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1186
d19770e5
ST		 1187 /* setup fifo + format */
1188 cx23885_sram_channel_setup(dev,
9c8ced51 1189 &dev->sram_channels[port->sram_chno],
44a6481d 1190 port->ts_packet_size, buf->risc.dma);
9c8ced51
ST		 1191 if (debug > 5) {
1192 cx23885_sram_channel_dump(dev,
1193 &dev->sram_channels[port->sram_chno]);
d19770e5 1194 cx23885_risc_disasm(port, &buf->risc);
3328e4fb 1195 }
d19770e5
ST		 1196
1197 /* write TS length to chip */
1198 cx_write(port->reg_lngth, buf->vb.width);
1199
9c8ced51
ST		 1200 if ((!(cx23885_boards[dev->board].portb & CX23885_MPEG_DVB)) &&
1201 (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB))) {
1202 printk("%s() Unsupported .portb/c (0x%08x)/(0x%08x)\n",
22b4e64f 1203 __func__,
661c7e44 1204 cx23885_boards[dev->board].portb,
9c8ced51 1205 cx23885_boards[dev->board].portc);
d19770e5
ST		 1206 return -EINVAL;
1207 }
1208
a589b665
ST		 1209 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1210 cx23885_av_clk(dev, 0);
1211
d19770e5
ST		 1212 udelay(100);
1213
579f1163 1214 /* If the port supports SRC SELECT, configure it */
9c8ced51 1215 if (port->reg_src_sel)
579f1163
ST		 1216 cx_write(port->reg_src_sel, port->src_sel_val);
1217
b1b81f1d 1218 cx_write(port->reg_hw_sop_ctrl, port->hw_sop_ctrl_val);
d19770e5 1219 cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
b1b81f1d 1220 cx_write(port->reg_vld_misc, port->vld_misc_val);
d19770e5
ST		 1221 cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
1222 udelay(100);
1223
9c8ced51 1224 /* NOTE: this is 2 (reserved) for portb, does it matter? */
d19770e5
ST		 1225 /* reset counter to zero */
1226 cx_write(port->reg_gpcnt_ctl, 3);
1227 q->count = 1;
1228
52ce27bf
ST		 1229 /* Set VIDB pins to input */
1230 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
1231 reg = cx_read(PAD_CTRL);
1232 reg &= ~0x3; /* Clear TS1_OE & TS1_SOP_OE */
1233 cx_write(PAD_CTRL, reg);
1234 }
1235
1236 /* Set VIDC pins to input */
1237 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
1238 reg = cx_read(PAD_CTRL);
1239 reg &= ~0x4; /* Clear TS2_SOP_OE */
1240 cx_write(PAD_CTRL, reg);
1241 }
1242
1243 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
a589b665
ST		 1244
1245 reg = cx_read(PAD_CTRL);
1246 reg = reg & ~0x1; /* Clear TS1_OE */
1247
1248 /* FIXME, bit 2 writing here is questionable */
1249 /* set TS1_SOP_OE and TS1_OE_HI */
1250 reg = reg | 0xa;
1251 cx_write(PAD_CTRL, reg);
1252
1253 /* FIXME and these two registers should be documented. */
1254 cx_write(CLK_DELAY, cx_read(CLK_DELAY) | 0x80000011);
1255 cx_write(ALT_PIN_OUT_SEL, 0x10100045);
1256 }
1257
9c8ced51 1258 switch (dev->bridge) {
d19770e5 1259 case CX23885_BRIDGE_885:
3bd40659 1260 case CX23885_BRIDGE_887:
d19770e5 1261 /* enable irqs */
9c8ced51 1262 dprintk(1, "%s() enabling TS int's and DMA\n", __func__);
d19770e5
ST		 1263 cx_set(port->reg_ts_int_msk, port->ts_int_msk_val);
1264 cx_set(port->reg_dma_ctl, port->dma_ctl_val);
1265 cx_set(PCI_INT_MSK, dev->pci_irqmask | port->pci_irqmask);
1266 break;
d19770e5 1267 default:
579f1163 1268 BUG();
d19770e5
ST		 1269 }
1270
d19770e5
ST		 1271 cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
1272
a589b665
ST		 1273 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1274 cx23885_av_clk(dev, 1);
1275
7b888014
ST		 1276 if (debug > 4)
1277 cx23885_tsport_reg_dump(port);
1278
d19770e5
ST		 1279 return 0;
1280}
1281
1282static int cx23885_stop_dma(struct cx23885_tsport *port)
1283{
1284 struct cx23885_dev *dev = port->dev;
a589b665
ST		 1285 u32 reg;
1286
22b4e64f 1287 dprintk(1, "%s()\n", __func__);
d19770e5
ST		 1288
1289 /* Stop interrupts and DMA */
1290 cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
1291 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1292
52ce27bf 1293 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
a589b665
ST		 1294
1295 reg = cx_read(PAD_CTRL);
1296
1297 /* Set TS1_OE */
1298 reg = reg | 0x1;
1299
1300 /* clear TS1_SOP_OE and TS1_OE_HI */
1301 reg = reg & ~0xa;
1302 cx_write(PAD_CTRL, reg);
1303 cx_write(port->reg_src_sel, 0);
1304 cx_write(port->reg_gen_ctrl, 8);
1305
1306 }
1307
1308 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1309 cx23885_av_clk(dev, 0);
1310
d19770e5
ST		 1311 return 0;
1312}
1313
7b888014 1314int cx23885_restart_queue(struct cx23885_tsport *port,
d19770e5
ST		 1315 struct cx23885_dmaqueue *q)
1316{
1317 struct cx23885_dev *dev = port->dev;
1318 struct cx23885_buffer *buf;
d19770e5 1319
22b4e64f 1320 dprintk(5, "%s()\n", __func__);
9c8ced51 1321 if (list_empty(&q->active)) {
44a6481d
MK		 1322 struct cx23885_buffer *prev;
1323 prev = NULL;
d19770e5 1324
22b4e64f 1325 dprintk(5, "%s() queue is empty\n", __func__);
d19770e5 1326
44a6481d
MK		 1327 for (;;) {
1328 if (list_empty(&q->queued))
1329 return 0;
1330 buf = list_entry(q->queued.next, struct cx23885_buffer,
1331 vb.queue);
1332 if (NULL == prev) {
1333 list_del(&buf->vb.queue);
1334 list_add_tail(&buf->vb.queue, &q->active);
1335 cx23885_start_dma(port, q, buf);
0fc0686e 1336 buf->vb.state = VIDEOBUF_ACTIVE;
44a6481d
MK		 1337 buf->count = q->count++;
1338 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
9c8ced51 1339 dprintk(5, "[%p/%d] restart_queue - f/active\n",
44a6481d
MK		 1340 buf, buf->vb.i);
1341
1342 } else if (prev->vb.width == buf->vb.width &&
1343 prev->vb.height == buf->vb.height &&
1344 prev->fmt == buf->fmt) {
1345 list_del(&buf->vb.queue);
1346 list_add_tail(&buf->vb.queue, &q->active);
0fc0686e 1347 buf->vb.state = VIDEOBUF_ACTIVE;
44a6481d
MK		 1348 buf->count = q->count++;
1349 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
9c8ced51
ST		 1350 /* 64 bit bits 63-32 */
1351 prev->risc.jmp[2] = cpu_to_le32(0);
1352 dprintk(5, "[%p/%d] restart_queue - m/active\n",
44a6481d
MK		 1353 buf, buf->vb.i);
1354 } else {
1355 return 0;
1356 }
1357 prev = buf;
1358 }
d19770e5
ST		 1359 return 0;
1360 }
1361
1362 buf = list_entry(q->active.next, struct cx23885_buffer, vb.queue);
44a6481d 1363 dprintk(2, "restart_queue [%p/%d]: restart dma\n",
d19770e5
ST		 1364 buf, buf->vb.i);
1365 cx23885_start_dma(port, q, buf);
a991f44b 1366 list_for_each_entry(buf, &q->active, vb.queue)
d19770e5 1367 buf->count = q->count++;
44a6481d 1368 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
d19770e5
ST		 1369 return 0;
1370}
1371
1372/* ------------------------------------------------------------------ */
1373
1374int cx23885_buf_prepare(struct videobuf_queue *q, struct cx23885_tsport *port,
1375 struct cx23885_buffer *buf, enum v4l2_field field)
1376{
1377 struct cx23885_dev *dev = port->dev;
1378 int size = port->ts_packet_size * port->ts_packet_count;
1379 int rc;
1380
22b4e64f 1381 dprintk(1, "%s: %p\n", __func__, buf);
d19770e5
ST		 1382 if (0 != buf->vb.baddr && buf->vb.bsize < size)
1383 return -EINVAL;
1384
0fc0686e 1385 if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
d19770e5
ST		 1386 buf->vb.width = port->ts_packet_size;
1387 buf->vb.height = port->ts_packet_count;
1388 buf->vb.size = size;
1389 buf->vb.field = field /*V4L2_FIELD_TOP*/;
1390
9c8ced51
ST		 1391 rc = videobuf_iolock(q, &buf->vb, NULL);
1392 if (0 != rc)
d19770e5
ST		 1393 goto fail;
1394 cx23885_risc_databuffer(dev->pci, &buf->risc,
409d84f8
TP		 1395 videobuf_to_dma(&buf->vb)->sglist,
1396 buf->vb.width, buf->vb.height);
d19770e5 1397 }
0fc0686e 1398 buf->vb.state = VIDEOBUF_PREPARED;
d19770e5
ST		 1399 return 0;
1400
1401 fail:
44a6481d 1402 cx23885_free_buffer(q, buf);
d19770e5
ST		 1403 return rc;
1404}
1405
1406void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
1407{
1408 struct cx23885_buffer *prev;
1409 struct cx23885_dev *dev = port->dev;
1410 struct cx23885_dmaqueue *cx88q = &port->mpegq;
1411
1412 /* add jump to stopper */
1413 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
1414 buf->risc.jmp[1] = cpu_to_le32(cx88q->stopper.dma);
1415 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
1416
1417 if (list_empty(&cx88q->active)) {
9c8ced51 1418 dprintk(1, "queue is empty - first active\n");
44a6481d 1419 list_add_tail(&buf->vb.queue, &cx88q->active);
d19770e5 1420 cx23885_start_dma(port, cx88q, buf);
0fc0686e 1421 buf->vb.state = VIDEOBUF_ACTIVE;
d19770e5 1422 buf->count = cx88q->count++;
44a6481d
MK		 1423 mod_timer(&cx88q->timeout, jiffies + BUFFER_TIMEOUT);
1424 dprintk(1, "[%p/%d] %s - first active\n",
22b4e64f 1425 buf, buf->vb.i, __func__);
d19770e5 1426 } else {
9c8ced51 1427 dprintk(1, "queue is not empty - append to active\n");
44a6481d
MK		 1428 prev = list_entry(cx88q->active.prev, struct cx23885_buffer,
1429 vb.queue);
1430 list_add_tail(&buf->vb.queue, &cx88q->active);
0fc0686e 1431 buf->vb.state = VIDEOBUF_ACTIVE;
d19770e5
ST		 1432 buf->count = cx88q->count++;
1433 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1434 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
9c8ced51 1435 dprintk(1, "[%p/%d] %s - append to active\n",
22b4e64f 1436 buf, buf->vb.i, __func__);
d19770e5
ST		 1437 }
1438}
1439
1440/* ----------------------------------------------------------- */
1441
44a6481d
MK		 1442static void do_cancel_buffers(struct cx23885_tsport *port, char *reason,
1443 int restart)
d19770e5
ST		 1444{
1445 struct cx23885_dev *dev = port->dev;
1446 struct cx23885_dmaqueue *q = &port->mpegq;
1447 struct cx23885_buffer *buf;
1448 unsigned long flags;
1449
44a6481d 1450 spin_lock_irqsave(&port->slock, flags);
d19770e5 1451 while (!list_empty(&q->active)) {
44a6481d
MK		 1452 buf = list_entry(q->active.next, struct cx23885_buffer,
1453 vb.queue);
d19770e5 1454 list_del(&buf->vb.queue);
0fc0686e 1455 buf->vb.state = VIDEOBUF_ERROR;
d19770e5 1456 wake_up(&buf->vb.done);
44a6481d 1457 dprintk(1, "[%p/%d] %s - dma=0x%08lx\n",
d19770e5
ST		 1458 buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
1459 }
44a6481d 1460 if (restart) {
9c8ced51 1461 dprintk(1, "restarting queue\n");
d19770e5
ST		 1462 cx23885_restart_queue(port, q);
1463 }
44a6481d 1464 spin_unlock_irqrestore(&port->slock, flags);
d19770e5
ST		 1465}
1466
b1b81f1d
ST		 1467void cx23885_cancel_buffers(struct cx23885_tsport *port)
1468{
1469 struct cx23885_dev *dev = port->dev;
1470 struct cx23885_dmaqueue *q = &port->mpegq;
1471
26d2e854 1472 dprintk(1, "%s()\n", __func__);
b1b81f1d
ST		 1473 del_timer_sync(&q->timeout);
1474 cx23885_stop_dma(port);
1475 do_cancel_buffers(port, "cancel", 0);
1476}
d19770e5
ST		 1477
1478static void cx23885_timeout(unsigned long data)
1479{
1480 struct cx23885_tsport *port = (struct cx23885_tsport *)data;
1481 struct cx23885_dev *dev = port->dev;
1482
9c8ced51 1483 dprintk(1, "%s()\n", __func__);
d19770e5
ST		 1484
1485 if (debug > 5)
9c8ced51
ST		 1486 cx23885_sram_channel_dump(dev,
1487 &dev->sram_channels[port->sram_chno]);
3328e4fb 1488
d19770e5
ST		 1489 cx23885_stop_dma(port);
1490 do_cancel_buffers(port, "timeout", 1);
1491}
1492
b1b81f1d
ST		 1493int cx23885_irq_417(struct cx23885_dev *dev, u32 status)
1494{
1495 /* FIXME: port1 assumption here. */
1496 struct cx23885_tsport *port = &dev->ts1;
1497 int count = 0;
1498 int handled = 0;
1499
1500 if (status == 0)
1501 return handled;
1502
1503 count = cx_read(port->reg_gpcnt);
1504 dprintk(7, "status: 0x%08x mask: 0x%08x count: 0x%x\n",
1505 status, cx_read(port->reg_ts_int_msk), count);
1506
1507 if ((status & VID_B_MSK_BAD_PKT) ||
1508 (status & VID_B_MSK_OPC_ERR) ||
1509 (status & VID_B_MSK_VBI_OPC_ERR) ||
1510 (status & VID_B_MSK_SYNC) ||
1511 (status & VID_B_MSK_VBI_SYNC) ||
1512 (status & VID_B_MSK_OF) ||
1513 (status & VID_B_MSK_VBI_OF)) {
1514 printk(KERN_ERR "%s: V4L mpeg risc op code error, status "
1515 "= 0x%x\n", dev->name, status);
1516 if (status & VID_B_MSK_BAD_PKT)
1517 dprintk(1, " VID_B_MSK_BAD_PKT\n");
1518 if (status & VID_B_MSK_OPC_ERR)
1519 dprintk(1, " VID_B_MSK_OPC_ERR\n");
1520 if (status & VID_B_MSK_VBI_OPC_ERR)
1521 dprintk(1, " VID_B_MSK_VBI_OPC_ERR\n");
1522 if (status & VID_B_MSK_SYNC)
1523 dprintk(1, " VID_B_MSK_SYNC\n");
1524 if (status & VID_B_MSK_VBI_SYNC)
1525 dprintk(1, " VID_B_MSK_VBI_SYNC\n");
1526 if (status & VID_B_MSK_OF)
1527 dprintk(1, " VID_B_MSK_OF\n");
1528 if (status & VID_B_MSK_VBI_OF)
1529 dprintk(1, " VID_B_MSK_VBI_OF\n");
1530
1531 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1532 cx23885_sram_channel_dump(dev,
1533 &dev->sram_channels[port->sram_chno]);
1534 cx23885_417_check_encoder(dev);
1535 } else if (status & VID_B_MSK_RISCI1) {
1536 dprintk(7, " VID_B_MSK_RISCI1\n");
1537 spin_lock(&port->slock);
1538 cx23885_wakeup(port, &port->mpegq, count);
1539 spin_unlock(&port->slock);
1540 } else if (status & VID_B_MSK_RISCI2) {
1541 dprintk(7, " VID_B_MSK_RISCI2\n");
1542 spin_lock(&port->slock);
1543 cx23885_restart_queue(port, &port->mpegq);
1544 spin_unlock(&port->slock);
1545 }
1546 if (status) {
1547 cx_write(port->reg_ts_int_stat, status);
1548 handled = 1;
1549 }
1550
1551 return handled;
1552}
1553
a6a3f140
ST		 1554static int cx23885_irq_ts(struct cx23885_tsport *port, u32 status)
1555{
1556 struct cx23885_dev *dev = port->dev;
1557 int handled = 0;
1558 u32 count;
1559
b1b81f1d
ST		 1560 if ((status & VID_BC_MSK_OPC_ERR) ||
1561 (status & VID_BC_MSK_BAD_PKT) ||
1562 (status & VID_BC_MSK_SYNC) ||
9c8ced51
ST		 1563 (status & VID_BC_MSK_OF)) {
1564
a6a3f140 1565 if (status & VID_BC_MSK_OPC_ERR)
9c8ced51
ST		 1566 dprintk(7, " (VID_BC_MSK_OPC_ERR 0x%08x)\n",
1567 VID_BC_MSK_OPC_ERR);
1568
a6a3f140 1569 if (status & VID_BC_MSK_BAD_PKT)
9c8ced51
ST		 1570 dprintk(7, " (VID_BC_MSK_BAD_PKT 0x%08x)\n",
1571 VID_BC_MSK_BAD_PKT);
1572
a6a3f140 1573 if (status & VID_BC_MSK_SYNC)
9c8ced51
ST		 1574 dprintk(7, " (VID_BC_MSK_SYNC 0x%08x)\n",
1575 VID_BC_MSK_SYNC);
1576
a6a3f140 1577 if (status & VID_BC_MSK_OF)
9c8ced51
ST		 1578 dprintk(7, " (VID_BC_MSK_OF 0x%08x)\n",
1579 VID_BC_MSK_OF);
a6a3f140
ST		 1580
1581 printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
1582
1583 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
b1b81f1d
ST		 1584 cx23885_sram_channel_dump(dev,
1585 &dev->sram_channels[port->sram_chno]);
a6a3f140
ST		 1586
1587 } else if (status & VID_BC_MSK_RISCI1) {
1588
1589 dprintk(7, " (RISCI1 0x%08x)\n", VID_BC_MSK_RISCI1);
1590
1591 spin_lock(&port->slock);
1592 count = cx_read(port->reg_gpcnt);
1593 cx23885_wakeup(port, &port->mpegq, count);
1594 spin_unlock(&port->slock);
1595
1596 } else if (status & VID_BC_MSK_RISCI2) {
1597
1598 dprintk(7, " (RISCI2 0x%08x)\n", VID_BC_MSK_RISCI2);
1599
1600 spin_lock(&port->slock);
1601 cx23885_restart_queue(port, &port->mpegq);
1602 spin_unlock(&port->slock);
1603
1604 }
1605 if (status) {
1606 cx_write(port->reg_ts_int_stat, status);
1607 handled = 1;
1608 }
1609
1610 return handled;
1611}
1612
03121f05 1613static irqreturn_t cx23885_irq(int irq, void *dev_id)
d19770e5
ST		 1614{
1615 struct cx23885_dev *dev = dev_id;
a6a3f140
ST		 1616 struct cx23885_tsport *ts1 = &dev->ts1;
1617 struct cx23885_tsport *ts2 = &dev->ts2;
d19770e5 1618 u32 pci_status, pci_mask;
7b888014 1619 u32 vida_status, vida_mask;
6f074abb 1620 u32 ts1_status, ts1_mask;
d19770e5 1621 u32 ts2_status, ts2_mask;
7b888014 1622 int vida_count = 0, ts1_count = 0, ts2_count = 0, handled = 0;
d19770e5
ST		 1623
1624 pci_status = cx_read(PCI_INT_STAT);
1625 pci_mask = cx_read(PCI_INT_MSK);
7b888014
ST		 1626 vida_status = cx_read(VID_A_INT_STAT);
1627 vida_mask = cx_read(VID_A_INT_MSK);
6f074abb
ST		 1628 ts1_status = cx_read(VID_B_INT_STAT);
1629 ts1_mask = cx_read(VID_B_INT_MSK);
d19770e5
ST		 1630 ts2_status = cx_read(VID_C_INT_STAT);
1631 ts2_mask = cx_read(VID_C_INT_MSK);
1632
9c8ced51 1633 if ((pci_status == 0) && (ts2_status == 0) && (ts1_status == 0))
d19770e5
ST		 1634 goto out;
1635
7b888014 1636 vida_count = cx_read(VID_A_GPCNT);
a6a3f140
ST		 1637 ts1_count = cx_read(ts1->reg_gpcnt);
1638 ts2_count = cx_read(ts2->reg_gpcnt);
7b888014
ST		 1639 dprintk(7, "pci_status: 0x%08x pci_mask: 0x%08x\n",
1640 pci_status, pci_mask);
1641 dprintk(7, "vida_status: 0x%08x vida_mask: 0x%08x count: 0x%x\n",
1642 vida_status, vida_mask, vida_count);
1643 dprintk(7, "ts1_status: 0x%08x ts1_mask: 0x%08x count: 0x%x\n",
1644 ts1_status, ts1_mask, ts1_count);
1645 dprintk(7, "ts2_status: 0x%08x ts2_mask: 0x%08x count: 0x%x\n",
1646 ts2_status, ts2_mask, ts2_count);
d19770e5 1647
9c8ced51
ST		 1648 if ((pci_status & PCI_MSK_RISC_RD) ||
1649 (pci_status & PCI_MSK_RISC_WR) ||
1650 (pci_status & PCI_MSK_AL_RD) ||
1651 (pci_status & PCI_MSK_AL_WR) ||
1652 (pci_status & PCI_MSK_APB_DMA) ||
1653 (pci_status & PCI_MSK_VID_C) ||
1654 (pci_status & PCI_MSK_VID_B) ||
1655 (pci_status & PCI_MSK_VID_A) ||
1656 (pci_status & PCI_MSK_AUD_INT) ||
5a23b076
IL		 1657 (pci_status & PCI_MSK_AUD_EXT) ||
1658 (pci_status & PCI_MSK_GPIO0) ||
1659 (pci_status & PCI_MSK_GPIO1)) {
d19770e5
ST		 1660
1661 if (pci_status & PCI_MSK_RISC_RD)
9c8ced51
ST		 1662 dprintk(7, " (PCI_MSK_RISC_RD 0x%08x)\n",
1663 PCI_MSK_RISC_RD);
1664
d19770e5 1665 if (pci_status & PCI_MSK_RISC_WR)
9c8ced51
ST		 1666 dprintk(7, " (PCI_MSK_RISC_WR 0x%08x)\n",
1667 PCI_MSK_RISC_WR);
1668
d19770e5 1669 if (pci_status & PCI_MSK_AL_RD)
9c8ced51
ST		 1670 dprintk(7, " (PCI_MSK_AL_RD 0x%08x)\n",
1671 PCI_MSK_AL_RD);
1672
d19770e5 1673 if (pci_status & PCI_MSK_AL_WR)
9c8ced51
ST		 1674 dprintk(7, " (PCI_MSK_AL_WR 0x%08x)\n",
1675 PCI_MSK_AL_WR);
1676
d19770e5 1677 if (pci_status & PCI_MSK_APB_DMA)
9c8ced51
ST		 1678 dprintk(7, " (PCI_MSK_APB_DMA 0x%08x)\n",
1679 PCI_MSK_APB_DMA);
1680
d19770e5 1681 if (pci_status & PCI_MSK_VID_C)
9c8ced51
ST		 1682 dprintk(7, " (PCI_MSK_VID_C 0x%08x)\n",
1683 PCI_MSK_VID_C);
1684
d19770e5 1685 if (pci_status & PCI_MSK_VID_B)
9c8ced51
ST		 1686 dprintk(7, " (PCI_MSK_VID_B 0x%08x)\n",
1687 PCI_MSK_VID_B);
1688
d19770e5 1689 if (pci_status & PCI_MSK_VID_A)
9c8ced51
ST		 1690 dprintk(7, " (PCI_MSK_VID_A 0x%08x)\n",
1691 PCI_MSK_VID_A);
1692
d19770e5 1693 if (pci_status & PCI_MSK_AUD_INT)
9c8ced51
ST		 1694 dprintk(7, " (PCI_MSK_AUD_INT 0x%08x)\n",
1695 PCI_MSK_AUD_INT);
1696
d19770e5 1697 if (pci_status & PCI_MSK_AUD_EXT)
9c8ced51
ST		 1698 dprintk(7, " (PCI_MSK_AUD_EXT 0x%08x)\n",
1699 PCI_MSK_AUD_EXT);
d19770e5 1700
5a23b076
IL		 1701 if (pci_status & PCI_MSK_GPIO0)
1702 dprintk(7, " (PCI_MSK_GPIO0 0x%08x)\n",
1703 PCI_MSK_GPIO0);
1704
1705 if (pci_status & PCI_MSK_GPIO1)
1706 dprintk(7, " (PCI_MSK_GPIO1 0x%08x)\n",
1707 PCI_MSK_GPIO1);
d19770e5
ST		 1708 }
1709
afd96668 1710 if (cx23885_boards[dev->board].cimax > 0 &&
a26ccc9d
ST		 1711 ((pci_status & PCI_MSK_GPIO0) ||
1712 (pci_status & PCI_MSK_GPIO1))) {
1713
1714 if (cx23885_boards[dev->board].cimax > 0)
1715 handled += netup_ci_slot_status(dev, pci_status);
1716
1717 }
5a23b076 1718
7b888014
ST		 1719 if (ts1_status) {
1720 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
1721 handled += cx23885_irq_ts(ts1, ts1_status);
b1b81f1d
ST		 1722 else
1723 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1724 handled += cx23885_irq_417(dev, ts1_status);
7b888014
ST		 1725 }
1726
1727 if (ts2_status) {
1728 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
1729 handled += cx23885_irq_ts(ts2, ts2_status);
b1b81f1d
ST		 1730 else
1731 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
1732 handled += cx23885_irq_417(dev, ts2_status);
7b888014 1733 }
6f074abb 1734
7b888014
ST		 1735 if (vida_status)
1736 handled += cx23885_video_irq(dev, vida_status);
6f074abb
ST		 1737
1738 if (handled)
1739 cx_write(PCI_INT_STAT, pci_status);
d19770e5
ST		 1740out:
1741 return IRQ_RETVAL(handled);
1742}
1743
6de72bd6 1744static inline int encoder_on_portb(struct cx23885_dev *dev)
6f8bee9b
ST		 1745{
1746 return cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER;
1747}
1748
6de72bd6 1749static inline int encoder_on_portc(struct cx23885_dev *dev)
6f8bee9b
ST		 1750{
1751 return cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER;
1752}
1753
1754/* Mask represents 32 different GPIOs, GPIO's are split into multiple
1755 * registers depending on the board configuration (and whether the
1756 * 417 encoder (wi it's own GPIO's) are present. Each GPIO bit will
1757 * be pushed into the correct hardware register, regardless of the
1758 * physical location. Certain registers are shared so we sanity check
1759 * and report errors if we think we're tampering with a GPIo that might
1760 * be assigned to the encoder (and used for the host bus).
1761 *
1762 * GPIO 2 thru 0 - On the cx23885 bridge
1763 * GPIO 18 thru 3 - On the cx23417 host bus interface
1764 * GPIO 23 thru 19 - On the cx25840 a/v core
1765 */
1766void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask)
1767{
1768 if (mask & 0x7)
1769 cx_set(GP0_IO, mask & 0x7);
1770
1771 if (mask & 0x0007fff8) {
1772 if (encoder_on_portb(dev) || encoder_on_portc(dev))
1773 printk(KERN_ERR
1774 "%s: Setting GPIO on encoder ports\n",
1775 dev->name);
1776 cx_set(MC417_RWD, (mask & 0x0007fff8) >> 3);
1777 }
1778
1779 /* TODO: 23-19 */
1780 if (mask & 0x00f80000)
1781 printk(KERN_INFO "%s: Unsupported\n", dev->name);
1782}
1783
1784void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask)
1785{
1786 if (mask & 0x00000007)
1787 cx_clear(GP0_IO, mask & 0x7);
1788
1789 if (mask & 0x0007fff8) {
1790 if (encoder_on_portb(dev) || encoder_on_portc(dev))
1791 printk(KERN_ERR
1792 "%s: Clearing GPIO moving on encoder ports\n",
1793 dev->name);
1794 cx_clear(MC417_RWD, (mask & 0x7fff8) >> 3);
1795 }
1796
1797 /* TODO: 23-19 */
1798 if (mask & 0x00f80000)
1799 printk(KERN_INFO "%s: Unsupported\n", dev->name);
1800}
1801
1802void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput)
1803{
1804 if ((mask & 0x00000007) && asoutput)
1805 cx_set(GP0_IO, (mask & 0x7) << 16);
1806 else if ((mask & 0x00000007) && !asoutput)
1807 cx_clear(GP0_IO, (mask & 0x7) << 16);
1808
1809 if (mask & 0x0007fff8) {
1810 if (encoder_on_portb(dev) || encoder_on_portc(dev))
1811 printk(KERN_ERR
1812 "%s: Enabling GPIO on encoder ports\n",
1813 dev->name);
1814 }
1815
1816 /* MC417_OEN is active low for output, write 1 for an input */
1817 if ((mask & 0x0007fff8) && asoutput)
1818 cx_clear(MC417_OEN, (mask & 0x7fff8) >> 3);
1819
1820 else if ((mask & 0x0007fff8) && !asoutput)
1821 cx_set(MC417_OEN, (mask & 0x7fff8) >> 3);
1822
1823 /* TODO: 23-19 */
1824}
1825
d19770e5 1826static int __devinit cx23885_initdev(struct pci_dev *pci_dev,
44a6481d 1827 const struct pci_device_id *pci_id)
d19770e5
ST		 1828{
1829 struct cx23885_dev *dev;
1830 int err;
1831
44a6481d 1832 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
d19770e5
ST		 1833 if (NULL == dev)
1834 return -ENOMEM;
1835
c0714f6c
HV		 1836 err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev);
1837 if (err < 0)
1838 goto fail_free;
1839
d19770e5
ST		 1840 /* pci init */
1841 dev->pci = pci_dev;
1842 if (pci_enable_device(pci_dev)) {
1843 err = -EIO;
c0714f6c 1844 goto fail_unreg;
d19770e5
ST		 1845 }
1846
1847 if (cx23885_dev_setup(dev) < 0) {
1848 err = -EINVAL;
c0714f6c 1849 goto fail_unreg;
d19770e5
ST		 1850 }
1851
1852 /* print pci info */
1853 pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1854 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
1855 printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
1856 "latency: %d, mmio: 0x%llx\n", dev->name,
1857 pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
a589b665
ST		 1858 dev->pci_lat,
1859 (unsigned long long)pci_resource_start(pci_dev, 0));
d19770e5
ST		 1860
1861 pci_set_master(pci_dev);
1862 if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1863 printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1864 err = -EIO;
1865 goto fail_irq;
1866 }
1867
44a6481d
MK		 1868 err = request_irq(pci_dev->irq, cx23885_irq,
1869 IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
d19770e5
ST		 1870 if (err < 0) {
1871 printk(KERN_ERR "%s: can't get IRQ %d\n",
1872 dev->name, pci_dev->irq);
1873 goto fail_irq;
1874 }
1875
afd96668
HV		 1876 switch (dev->board) {
1877 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1878 cx_set(PCI_INT_MSK, 0x01800000); /* for NetUP */
1879 break;
1880 }
5a23b076 1881
d19770e5
ST		 1882 return 0;
1883
1884fail_irq:
1885 cx23885_dev_unregister(dev);
c0714f6c
HV		 1886fail_unreg:
1887 v4l2_device_unregister(&dev->v4l2_dev);
d19770e5
ST		 1888fail_free:
1889 kfree(dev);
1890 return err;
1891}
1892
1893static void __devexit cx23885_finidev(struct pci_dev *pci_dev)
1894{
c0714f6c
HV		 1895 struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
1896 struct cx23885_dev *dev = to_cx23885(v4l2_dev);
d19770e5
ST		 1897
1898 cx23885_shutdown(dev);
1899
1900 pci_disable_device(pci_dev);
1901
1902 /* unregister stuff */
1903 free_irq(pci_dev->irq, dev);
d19770e5
ST		 1904
1905 mutex_lock(&devlist);
1906 list_del(&dev->devlist);
1907 mutex_unlock(&devlist);
1908
1909 cx23885_dev_unregister(dev);
c0714f6c 1910 v4l2_device_unregister(v4l2_dev);
d19770e5
ST		 1911 kfree(dev);
1912}
1913
1914static struct pci_device_id cx23885_pci_tbl[] = {
1915 {
1916 /* CX23885 */
1917 .vendor = 0x14f1,
1918 .device = 0x8852,
1919 .subvendor = PCI_ANY_ID,
1920 .subdevice = PCI_ANY_ID,
9c8ced51 1921 }, {
d19770e5
ST		 1922 /* CX23887 Rev 2 */
1923 .vendor = 0x14f1,
1924 .device = 0x8880,
1925 .subvendor = PCI_ANY_ID,
1926 .subdevice = PCI_ANY_ID,
9c8ced51 1927 }, {
d19770e5
ST		 1928 /* --- end of list --- */
1929 }
1930};
1931MODULE_DEVICE_TABLE(pci, cx23885_pci_tbl);
1932
1933static struct pci_driver cx23885_pci_driver = {
1934 .name = "cx23885",
1935 .id_table = cx23885_pci_tbl,
1936 .probe = cx23885_initdev,
1937 .remove = __devexit_p(cx23885_finidev),
1938 /* TODO */
1939 .suspend = NULL,
1940 .resume = NULL,
1941};
1942
1943static int cx23885_init(void)
1944{
1945 printk(KERN_INFO "cx23885 driver version %d.%d.%d loaded\n",
047646bf
ST		 1946 (CX23885_VERSION_CODE >> 16) & 0xff,
1947 (CX23885_VERSION_CODE >> 8) & 0xff,
1948 CX23885_VERSION_CODE & 0xff);
d19770e5
ST		 1949#ifdef SNAPSHOT
1950 printk(KERN_INFO "cx23885: snapshot date %04d-%02d-%02d\n",
1951 SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
1952#endif
1953 return pci_register_driver(&cx23885_pci_driver);
1954}
1955
1956static void cx23885_fini(void)
1957{
1958 pci_unregister_driver(&cx23885_pci_driver);
1959}
1960
1961module_init(cx23885_init);
1962module_exit(cx23885_fini);
1963
1964/* ----------------------------------------------------------- */
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