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[media] cx23885: Enable audio line in support from the back panel
[mirror_ubuntu-artful-kernel.git] / drivers / media / video / cx25840 / cx25840-core.c
CommitLineData
bd985160
HV		 1/* cx25840 - Conexant CX25840 audio/video decoder driver
2 *
3 * Copyright (C) 2004 Ulf Eklund
4 *
25985edc 5 * Based on the saa7115 driver and on the first version of Chris Kennedy's
bd985160
HV		 6 * cx25840 driver.
7 *
8 * Changes by Tyler Trafford <tatrafford@comcast.net>
9 * - cleanup/rewrite for V4L2 API (2005)
10 *
11 * VBI support by Hans Verkuil <hverkuil@xs4all.nl>.
12 *
3e3bf277
CN		 13 * NTSC sliced VBI support by Christopher Neufeld <television@cneufeld.ca>
14 * with additional fixes by Hans Verkuil <hverkuil@xs4all.nl>.
15 *
6d897616 16 * CX23885 support by Steven Toth <stoth@linuxtv.org>.
f234081b 17 *
52fd3dda
AW		 18 * CX2388[578] IRQ handling, IO Pin mux configuration and other small fixes are
19 * Copyright (C) 2010 Andy Walls <awalls@md.metrocast.net>
20 *
bd985160
HV		 21 * This program is free software; you can redistribute it and/or
22 * modify it under the terms of the GNU General Public License
23 * as published by the Free Software Foundation; either version 2
24 * of the License, or (at your option) any later version.
25 *
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
30 *
31 * You should have received a copy of the GNU General Public License
32 * along with this program; if not, write to the Free Software
33 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
34 */
35
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/slab.h>
40#include <linux/videodev2.h>
41#include <linux/i2c.h>
f61b48f7 42#include <linux/delay.h>
bd985160 43#include <media/v4l2-common.h>
3434eb7e 44#include <media/v4l2-chip-ident.h>
31bc09b5 45#include <media/cx25840.h>
bd985160 46
31bc09b5 47#include "cx25840-core.h"
bd985160
HV		 48
49MODULE_DESCRIPTION("Conexant CX25840 audio/video decoder driver");
1f4b3365 50MODULE_AUTHOR("Ulf Eklund, Chris Kennedy, Hans Verkuil, Tyler Trafford");
bd985160
HV		 51MODULE_LICENSE("GPL");
52
52fd3dda
AW		 53#define CX25840_VID_INT_STAT_REG 0x410
54#define CX25840_VID_INT_STAT_BITS 0x0000ffff
55#define CX25840_VID_INT_MASK_BITS 0xffff0000
56#define CX25840_VID_INT_MASK_SHFT 16
57#define CX25840_VID_INT_MASK_REG 0x412
58
59#define CX23885_AUD_MC_INT_MASK_REG 0x80c
60#define CX23885_AUD_MC_INT_STAT_BITS 0xffff0000
61#define CX23885_AUD_MC_INT_CTRL_BITS 0x0000ffff
62#define CX23885_AUD_MC_INT_STAT_SHFT 16
63
64#define CX25840_AUD_INT_CTRL_REG 0x812
65#define CX25840_AUD_INT_STAT_REG 0x813
66
67#define CX23885_PIN_CTRL_IRQ_REG 0x123
68#define CX23885_PIN_CTRL_IRQ_IR_STAT 0x40
69#define CX23885_PIN_CTRL_IRQ_AUD_STAT 0x20
70#define CX23885_PIN_CTRL_IRQ_VID_STAT 0x10
71
72#define CX25840_IR_STATS_REG 0x210
73#define CX25840_IR_IRQEN_REG 0x214
74
fe0d3dff 75static int cx25840_debug;
bd985160 76
b5fc7144 77module_param_named(debug,cx25840_debug, int, 0644);
bd985160 78
fac9e899 79MODULE_PARM_DESC(debug, "Debugging messages [0=Off (default) 1=On]");
bd985160 80
bd985160
HV		 81
82/* ----------------------------------------------------------------------- */
83
84int cx25840_write(struct i2c_client *client, u16 addr, u8 value)
85{
86 u8 buffer[3];
87 buffer[0] = addr >> 8;
88 buffer[1] = addr & 0xff;
89 buffer[2] = value;
90 return i2c_master_send(client, buffer, 3);
91}
92
93int cx25840_write4(struct i2c_client *client, u16 addr, u32 value)
94{
95 u8 buffer[6];
96 buffer[0] = addr >> 8;
97 buffer[1] = addr & 0xff;
4a56eb3f
HV		 98 buffer[2] = value & 0xff;
99 buffer[3] = (value >> 8) & 0xff;
100 buffer[4] = (value >> 16) & 0xff;
101 buffer[5] = value >> 24;
bd985160
HV		 102 return i2c_master_send(client, buffer, 6);
103}
104
105u8 cx25840_read(struct i2c_client * client, u16 addr)
106{
5f272644
AW		 107 struct i2c_msg msgs[2];
108 u8 tx_buf[2], rx_buf[1];
109
110 /* Write register address */
111 tx_buf[0] = addr >> 8;
112 tx_buf[1] = addr & 0xff;
113 msgs[0].addr = client->addr;
114 msgs[0].flags = 0;
115 msgs[0].len = 2;
116 msgs[0].buf = (char *) tx_buf;
117
118 /* Read data from register */
119 msgs[1].addr = client->addr;
120 msgs[1].flags = I2C_M_RD;
121 msgs[1].len = 1;
122 msgs[1].buf = (char *) rx_buf;
123
124 if (i2c_transfer(client->adapter, msgs, 2) < 2)
bd985160
HV		 125 return 0;
126
5f272644 127 return rx_buf[0];
bd985160
HV		 128}
129
130u32 cx25840_read4(struct i2c_client * client, u16 addr)
131{
5f272644
AW		 132 struct i2c_msg msgs[2];
133 u8 tx_buf[2], rx_buf[4];
134
135 /* Write register address */
136 tx_buf[0] = addr >> 8;
137 tx_buf[1] = addr & 0xff;
138 msgs[0].addr = client->addr;
139 msgs[0].flags = 0;
140 msgs[0].len = 2;
141 msgs[0].buf = (char *) tx_buf;
142
143 /* Read data from registers */
144 msgs[1].addr = client->addr;
145 msgs[1].flags = I2C_M_RD;
146 msgs[1].len = 4;
147 msgs[1].buf = (char *) rx_buf;
148
149 if (i2c_transfer(client->adapter, msgs, 2) < 2)
bd985160
HV		 150 return 0;
151
5f272644
AW		 152 return (rx_buf[3] << 24) | (rx_buf[2] << 16) | (rx_buf[1] << 8) |
153 rx_buf[0];
bd985160
HV		 154}
155
e2b8cf4c 156int cx25840_and_or(struct i2c_client *client, u16 addr, unsigned and_mask,
bd985160
HV		 157 u8 or_value)
158{
159 return cx25840_write(client, addr,
160 (cx25840_read(client, addr) & and_mask) |
161 or_value);
162}
163
52fd3dda
AW		 164int cx25840_and_or4(struct i2c_client *client, u16 addr, u32 and_mask,
165 u32 or_value)
166{
167 return cx25840_write4(client, addr,
168 (cx25840_read4(client, addr) & and_mask) |
169 or_value);
170}
171
bd985160
HV		 172/* ----------------------------------------------------------------------- */
173
a8bbf12a
HV		 174static int set_input(struct i2c_client *client, enum cx25840_video_input vid_input,
175 enum cx25840_audio_input aud_input);
bd985160
HV		 176
177/* ----------------------------------------------------------------------- */
178
d06d5777
AW		 179static int cx23885_s_io_pin_config(struct v4l2_subdev *sd, size_t n,
180 struct v4l2_subdev_io_pin_config *p)
181{
182 struct i2c_client *client = v4l2_get_subdevdata(sd);
183 int i;
184 u32 pin_ctrl;
185 u8 gpio_oe, gpio_data, strength;
186
187 pin_ctrl = cx25840_read4(client, 0x120);
188 gpio_oe = cx25840_read(client, 0x160);
189 gpio_data = cx25840_read(client, 0x164);
190
191 for (i = 0; i < n; i++) {
192 strength = p[i].strength;
193 if (strength > CX25840_PIN_DRIVE_FAST)
194 strength = CX25840_PIN_DRIVE_FAST;
195
196 switch (p[i].pin) {
197 case CX23885_PIN_IRQ_N_GPIO16:
198 if (p[i].function != CX23885_PAD_IRQ_N) {
199 /* GPIO16 */
200 pin_ctrl &= ~(0x1 << 25);
201 } else {
202 /* IRQ_N */
203 if (p[i].flags &
204 (V4L2_SUBDEV_IO_PIN_DISABLE |
205 V4L2_SUBDEV_IO_PIN_INPUT)) {
206 pin_ctrl &= ~(0x1 << 25);
207 } else {
208 pin_ctrl |= (0x1 << 25);
209 }
210 if (p[i].flags &
211 V4L2_SUBDEV_IO_PIN_ACTIVE_LOW) {
212 pin_ctrl &= ~(0x1 << 24);
213 } else {
214 pin_ctrl |= (0x1 << 24);
215 }
216 }
217 break;
218 case CX23885_PIN_IR_RX_GPIO19:
219 if (p[i].function != CX23885_PAD_GPIO19) {
220 /* IR_RX */
221 gpio_oe |= (0x1 << 0);
222 pin_ctrl &= ~(0x3 << 18);
223 pin_ctrl |= (strength << 18);
224 } else {
225 /* GPIO19 */
226 gpio_oe &= ~(0x1 << 0);
227 if (p[i].flags & V4L2_SUBDEV_IO_PIN_SET_VALUE) {
228 gpio_data &= ~(0x1 << 0);
229 gpio_data |= ((p[i].value & 0x1) << 0);
230 }
231 pin_ctrl &= ~(0x3 << 12);
232 pin_ctrl |= (strength << 12);
233 }
234 break;
235 case CX23885_PIN_IR_TX_GPIO20:
236 if (p[i].function != CX23885_PAD_GPIO20) {
237 /* IR_TX */
238 gpio_oe |= (0x1 << 1);
239 if (p[i].flags & V4L2_SUBDEV_IO_PIN_DISABLE)
240 pin_ctrl &= ~(0x1 << 10);
241 else
242 pin_ctrl |= (0x1 << 10);
243 pin_ctrl &= ~(0x3 << 18);
244 pin_ctrl |= (strength << 18);
245 } else {
246 /* GPIO20 */
247 gpio_oe &= ~(0x1 << 1);
248 if (p[i].flags & V4L2_SUBDEV_IO_PIN_SET_VALUE) {
249 gpio_data &= ~(0x1 << 1);
250 gpio_data |= ((p[i].value & 0x1) << 1);
251 }
252 pin_ctrl &= ~(0x3 << 12);
253 pin_ctrl |= (strength << 12);
254 }
255 break;
256 case CX23885_PIN_I2S_SDAT_GPIO21:
257 if (p[i].function != CX23885_PAD_GPIO21) {
258 /* I2S_SDAT */
259 /* TODO: Input or Output config */
260 gpio_oe |= (0x1 << 2);
261 pin_ctrl &= ~(0x3 << 22);
262 pin_ctrl |= (strength << 22);
263 } else {
264 /* GPIO21 */
265 gpio_oe &= ~(0x1 << 2);
266 if (p[i].flags & V4L2_SUBDEV_IO_PIN_SET_VALUE) {
267 gpio_data &= ~(0x1 << 2);
268 gpio_data |= ((p[i].value & 0x1) << 2);
269 }
270 pin_ctrl &= ~(0x3 << 12);
271 pin_ctrl |= (strength << 12);
272 }
273 break;
274 case CX23885_PIN_I2S_WCLK_GPIO22:
275 if (p[i].function != CX23885_PAD_GPIO22) {
276 /* I2S_WCLK */
277 /* TODO: Input or Output config */
278 gpio_oe |= (0x1 << 3);
279 pin_ctrl &= ~(0x3 << 22);
280 pin_ctrl |= (strength << 22);
281 } else {
282 /* GPIO22 */
283 gpio_oe &= ~(0x1 << 3);
284 if (p[i].flags & V4L2_SUBDEV_IO_PIN_SET_VALUE) {
285 gpio_data &= ~(0x1 << 3);
286 gpio_data |= ((p[i].value & 0x1) << 3);
287 }
288 pin_ctrl &= ~(0x3 << 12);
289 pin_ctrl |= (strength << 12);
290 }
291 break;
292 case CX23885_PIN_I2S_BCLK_GPIO23:
293 if (p[i].function != CX23885_PAD_GPIO23) {
294 /* I2S_BCLK */
295 /* TODO: Input or Output config */
296 gpio_oe |= (0x1 << 4);
297 pin_ctrl &= ~(0x3 << 22);
298 pin_ctrl |= (strength << 22);
299 } else {
300 /* GPIO23 */
301 gpio_oe &= ~(0x1 << 4);
302 if (p[i].flags & V4L2_SUBDEV_IO_PIN_SET_VALUE) {
303 gpio_data &= ~(0x1 << 4);
304 gpio_data |= ((p[i].value & 0x1) << 4);
305 }
306 pin_ctrl &= ~(0x3 << 12);
307 pin_ctrl |= (strength << 12);
308 }
309 break;
310 }
311 }
312
313 cx25840_write(client, 0x164, gpio_data);
314 cx25840_write(client, 0x160, gpio_oe);
315 cx25840_write4(client, 0x120, pin_ctrl);
316 return 0;
317}
318
319static int common_s_io_pin_config(struct v4l2_subdev *sd, size_t n,
320 struct v4l2_subdev_io_pin_config *pincfg)
321{
322 struct cx25840_state *state = to_state(sd);
323
324 if (is_cx2388x(state))
325 return cx23885_s_io_pin_config(sd, n, pincfg);
326 return 0;
327}
328
329/* ----------------------------------------------------------------------- */
330
d92c20e0 331static void init_dll1(struct i2c_client *client)
bd985160
HV		 332{
333 /* This is the Hauppauge sequence used to
334 * initialize the Delay Lock Loop 1 (ADC DLL). */
335 cx25840_write(client, 0x159, 0x23);
336 cx25840_write(client, 0x15a, 0x87);
337 cx25840_write(client, 0x15b, 0x06);
38051450 338 udelay(10);
bd985160 339 cx25840_write(client, 0x159, 0xe1);
38051450 340 udelay(10);
bd985160
HV		 341 cx25840_write(client, 0x15a, 0x86);
342 cx25840_write(client, 0x159, 0xe0);
343 cx25840_write(client, 0x159, 0xe1);
344 cx25840_write(client, 0x15b, 0x10);
345}
346
d92c20e0 347static void init_dll2(struct i2c_client *client)
bd985160
HV		 348{
349 /* This is the Hauppauge sequence used to
350 * initialize the Delay Lock Loop 2 (ADC DLL). */
351 cx25840_write(client, 0x15d, 0xe3);
352 cx25840_write(client, 0x15e, 0x86);
353 cx25840_write(client, 0x15f, 0x06);
38051450 354 udelay(10);
bd985160
HV		 355 cx25840_write(client, 0x15d, 0xe1);
356 cx25840_write(client, 0x15d, 0xe0);
357 cx25840_write(client, 0x15d, 0xe1);
358}
359
e2b8cf4c
HV		 360static void cx25836_initialize(struct i2c_client *client)
361{
362 /* reset configuration is described on page 3-77 of the CX25836 datasheet */
363 /* 2. */
364 cx25840_and_or(client, 0x000, ~0x01, 0x01);
365 cx25840_and_or(client, 0x000, ~0x01, 0x00);
366 /* 3a. */
367 cx25840_and_or(client, 0x15a, ~0x70, 0x00);
368 /* 3b. */
369 cx25840_and_or(client, 0x15b, ~0x1e, 0x06);
370 /* 3c. */
371 cx25840_and_or(client, 0x159, ~0x02, 0x02);
372 /* 3d. */
38051450 373 udelay(10);
e2b8cf4c
HV		 374 /* 3e. */
375 cx25840_and_or(client, 0x159, ~0x02, 0x00);
376 /* 3f. */
377 cx25840_and_or(client, 0x159, ~0xc0, 0xc0);
378 /* 3g. */
379 cx25840_and_or(client, 0x159, ~0x01, 0x00);
380 cx25840_and_or(client, 0x159, ~0x01, 0x01);
381 /* 3h. */
382 cx25840_and_or(client, 0x15b, ~0x1e, 0x10);
383}
384
21340ae0
HV		 385static void cx25840_work_handler(struct work_struct *work)
386{
387 struct cx25840_state *state = container_of(work, struct cx25840_state, fw_work);
388 cx25840_loadfw(state->c);
389 wake_up(&state->fw_wait);
390}
391
89fc4eb9 392static void cx25840_initialize(struct i2c_client *client)
bd985160 393{
21340ae0 394 DEFINE_WAIT(wait);
9357b31c 395 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
21340ae0 396 struct workqueue_struct *q;
bd985160
HV		 397
398 /* datasheet startup in numbered steps, refer to page 3-77 */
399 /* 2. */
400 cx25840_and_or(client, 0x803, ~0x10, 0x00);
401 /* The default of this register should be 4, but I get 0 instead.
402 * Set this register to 4 manually. */
403 cx25840_write(client, 0x000, 0x04);
404 /* 3. */
405 init_dll1(client);
406 init_dll2(client);
407 cx25840_write(client, 0x136, 0x0a);
408 /* 4. */
409 cx25840_write(client, 0x13c, 0x01);
410 cx25840_write(client, 0x13c, 0x00);
411 /* 5. */
21340ae0
HV		 412 /* Do the firmware load in a work handler to prevent.
413 Otherwise the kernel is blocked waiting for the
414 bit-banging i2c interface to finish uploading the
415 firmware. */
416 INIT_WORK(&state->fw_work, cx25840_work_handler);
417 init_waitqueue_head(&state->fw_wait);
418 q = create_singlethread_workqueue("cx25840_fw");
419 prepare_to_wait(&state->fw_wait, &wait, TASK_UNINTERRUPTIBLE);
420 queue_work(q, &state->fw_work);
421 schedule();
422 finish_wait(&state->fw_wait, &wait);
423 destroy_workqueue(q);
424
bd985160
HV		 425 /* 6. */
426 cx25840_write(client, 0x115, 0x8c);
427 cx25840_write(client, 0x116, 0x07);
428 cx25840_write(client, 0x118, 0x02);
429 /* 7. */
430 cx25840_write(client, 0x4a5, 0x80);
431 cx25840_write(client, 0x4a5, 0x00);
432 cx25840_write(client, 0x402, 0x00);
433 /* 8. */
73dcddc5
HV		 434 cx25840_and_or(client, 0x401, ~0x18, 0);
435 cx25840_and_or(client, 0x4a2, ~0x10, 0x10);
436 /* steps 8c and 8d are done in change_input() */
bd985160
HV		 437 /* 10. */
438 cx25840_write(client, 0x8d3, 0x1f);
439 cx25840_write(client, 0x8e3, 0x03);
440
cb5aa1c6 441 cx25840_std_setup(client);
bd985160
HV		 442
443 /* trial and error says these are needed to get audio */
444 cx25840_write(client, 0x914, 0xa0);
445 cx25840_write(client, 0x918, 0xa0);
446 cx25840_write(client, 0x919, 0x01);
447
25985edc 448 /* stereo preferred */
bd985160
HV		 449 cx25840_write(client, 0x809, 0x04);
450 /* AC97 shift */
451 cx25840_write(client, 0x8cf, 0x0f);
452
a8bbf12a
HV		 453 /* (re)set input */
454 set_input(client, state->vid_input, state->aud_input);
bd985160
HV		 455
456 /* start microcontroller */
457 cx25840_and_or(client, 0x803, ~0x10, 0x10);
458}
459
f234081b
ST		 460static void cx23885_initialize(struct i2c_client *client)
461{
462 DEFINE_WAIT(wait);
9357b31c 463 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
f234081b
ST		 464 struct workqueue_struct *q;
465
e283d780
AW		 466 /*
467 * Come out of digital power down
468 * The CX23888, at least, needs this, otherwise registers aside from
469 * 0x0-0x2 can't be read or written.
470 */
471 cx25840_write(client, 0x000, 0);
472
f234081b
ST		 473 /* Internal Reset */
474 cx25840_and_or(client, 0x102, ~0x01, 0x01);
475 cx25840_and_or(client, 0x102, ~0x01, 0x00);
476
477 /* Stop microcontroller */
478 cx25840_and_or(client, 0x803, ~0x10, 0x00);
479
480 /* DIF in reset? */
481 cx25840_write(client, 0x398, 0);
482
e283d780
AW		 483 /*
484 * Trust the default xtal, no division
485 * '885: 28.636363... MHz
486 * '887: 25.000000 MHz
487 * '888: 50.000000 MHz
488 */
f234081b
ST		 489 cx25840_write(client, 0x2, 0x76);
490
e283d780 491 /* Power up all the PLL's and DLL */
f234081b
ST		 492 cx25840_write(client, 0x1, 0x40);
493
e283d780
AW		 494 /* Sys PLL */
495 switch (state->id) {
496 case V4L2_IDENT_CX23888_AV:
497 /*
498 * 50.0 MHz * (0xb + 0xe8ba26/0x2000000)/4 = 5 * 28.636363 MHz
499 * 572.73 MHz before post divide
500 */
501 cx25840_write4(client, 0x11c, 0x00e8ba26);
502 cx25840_write4(client, 0x118, 0x0000040b);
503 break;
504 case V4L2_IDENT_CX23887_AV:
505 /*
506 * 25.0 MHz * (0x16 + 0x1d1744c/0x2000000)/4 = 5 * 28.636363 MHz
507 * 572.73 MHz before post divide
508 */
509 cx25840_write4(client, 0x11c, 0x01d1744c);
510 cx25840_write4(client, 0x118, 0x00000416);
511 break;
512 case V4L2_IDENT_CX23885_AV:
513 default:
514 /*
515 * 28.636363 MHz * (0x14 + 0x0/0x2000000)/4 = 5 * 28.636363 MHz
516 * 572.73 MHz before post divide
517 */
518 cx25840_write4(client, 0x11c, 0x00000000);
519 cx25840_write4(client, 0x118, 0x00000414);
520 break;
521 }
f234081b
ST		 522
523 /* Disable DIF bypass */
524 cx25840_write4(client, 0x33c, 0x00000001);
525
526 /* DIF Src phase inc */
527 cx25840_write4(client, 0x340, 0x0df7df83);
528
e283d780
AW		 529 /*
530 * Vid PLL
531 * Setup for a BT.656 pixel clock of 13.5 Mpixels/second
532 *
533 * 28.636363 MHz * (0xf + 0x02be2c9/0x2000000)/4 = 8 * 13.5 MHz
534 * 432.0 MHz before post divide
535 */
536 cx25840_write4(client, 0x10c, 0x002be2c9);
537 cx25840_write4(client, 0x108, 0x0000040f);
f234081b
ST		 538
539 /* Luma */
540 cx25840_write4(client, 0x414, 0x00107d12);
541
542 /* Chroma */
543 cx25840_write4(client, 0x420, 0x3d008282);
544
e283d780
AW		 545 /*
546 * Aux PLL
547 * Initial setup for audio sample clock:
548 * 48 ksps, 16 bits/sample, x160 multiplier = 122.88 MHz
25985edc 549 * Initial I2S output/master clock(?):
e283d780
AW		 550 * 48 ksps, 16 bits/sample, x16 multiplier = 12.288 MHz
551 */
552 switch (state->id) {
553 case V4L2_IDENT_CX23888_AV:
554 /*
555 * 50.0 MHz * (0x7 + 0x0bedfa4/0x2000000)/3 = 122.88 MHz
556 * 368.64 MHz before post divide
557 * 122.88 MHz / 0xa = 12.288 MHz
558 */
559 cx25840_write4(client, 0x114, 0x00bedfa4);
560 cx25840_write4(client, 0x110, 0x000a0307);
561 break;
562 case V4L2_IDENT_CX23887_AV:
563 /*
564 * 25.0 MHz * (0xe + 0x17dbf48/0x2000000)/3 = 122.88 MHz
565 * 368.64 MHz before post divide
566 * 122.88 MHz / 0xa = 12.288 MHz
567 */
568 cx25840_write4(client, 0x114, 0x017dbf48);
569 cx25840_write4(client, 0x110, 0x000a030e);
570 break;
571 case V4L2_IDENT_CX23885_AV:
572 default:
573 /*
574 * 28.636363 MHz * (0xc + 0x1bf0c9e/0x2000000)/3 = 122.88 MHz
575 * 368.64 MHz before post divide
576 * 122.88 MHz / 0xa = 12.288 MHz
577 */
578 cx25840_write4(client, 0x114, 0x01bf0c9e);
579 cx25840_write4(client, 0x110, 0x000a030c);
580 break;
581 };
f234081b
ST		 582
583 /* ADC2 input select */
584 cx25840_write(client, 0x102, 0x10);
585
586 /* VIN1 & VIN5 */
587 cx25840_write(client, 0x103, 0x11);
588
589 /* Enable format auto detect */
590 cx25840_write(client, 0x400, 0);
591 /* Fast subchroma lock */
592 /* White crush, Chroma AGC & Chroma Killer enabled */
593 cx25840_write(client, 0x401, 0xe8);
594
595 /* Select AFE clock pad output source */
596 cx25840_write(client, 0x144, 0x05);
597
f3d6f633
ST		 598 /* Drive GPIO2 direction and values for HVR1700
599 * where an onboard mux selects the output of demodulator
600 * vs the 417. Failure to set this results in no DTV.
601 * It's safe to set this across all Hauppauge boards
602 * currently, regardless of the board type.
603 */
604 cx25840_write(client, 0x160, 0x1d);
605 cx25840_write(client, 0x164, 0x00);
606
f234081b
ST		 607 /* Do the firmware load in a work handler to prevent.
608 Otherwise the kernel is blocked waiting for the
609 bit-banging i2c interface to finish uploading the
610 firmware. */
611 INIT_WORK(&state->fw_work, cx25840_work_handler);
612 init_waitqueue_head(&state->fw_wait);
613 q = create_singlethread_workqueue("cx25840_fw");
614 prepare_to_wait(&state->fw_wait, &wait, TASK_UNINTERRUPTIBLE);
615 queue_work(q, &state->fw_work);
616 schedule();
617 finish_wait(&state->fw_wait, &wait);
618 destroy_workqueue(q);
619
cb5aa1c6 620 cx25840_std_setup(client);
f234081b
ST		 621
622 /* (re)set input */
623 set_input(client, state->vid_input, state->aud_input);
624
625 /* start microcontroller */
626 cx25840_and_or(client, 0x803, ~0x10, 0x10);
52fd3dda
AW		 627
628 /* Disable and clear video interrupts - we don't use them */
629 cx25840_write4(client, CX25840_VID_INT_STAT_REG, 0xffffffff);
630
631 /* Disable and clear audio interrupts - we don't use them */
632 cx25840_write(client, CX25840_AUD_INT_CTRL_REG, 0xff);
633 cx25840_write(client, CX25840_AUD_INT_STAT_REG, 0xff);
f234081b
ST		 634}
635
bd985160
HV		 636/* ----------------------------------------------------------------------- */
637
149783b5
SD		 638static void cx231xx_initialize(struct i2c_client *client)
639{
640 DEFINE_WAIT(wait);
641 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
642 struct workqueue_struct *q;
643
644 /* Internal Reset */
645 cx25840_and_or(client, 0x102, ~0x01, 0x01);
646 cx25840_and_or(client, 0x102, ~0x01, 0x00);
647
648 /* Stop microcontroller */
649 cx25840_and_or(client, 0x803, ~0x10, 0x00);
650
651 /* DIF in reset? */
652 cx25840_write(client, 0x398, 0);
653
654 /* Trust the default xtal, no division */
655 /* This changes for the cx23888 products */
656 cx25840_write(client, 0x2, 0x76);
657
658 /* Bring down the regulator for AUX clk */
659 cx25840_write(client, 0x1, 0x40);
660
661 /* Disable DIF bypass */
662 cx25840_write4(client, 0x33c, 0x00000001);
663
664 /* DIF Src phase inc */
665 cx25840_write4(client, 0x340, 0x0df7df83);
666
149783b5
SD		 667 /* Luma */
668 cx25840_write4(client, 0x414, 0x00107d12);
669
670 /* Chroma */
671 cx25840_write4(client, 0x420, 0x3d008282);
672
149783b5
SD		 673 /* ADC2 input select */
674 cx25840_write(client, 0x102, 0x10);
675
676 /* VIN1 & VIN5 */
677 cx25840_write(client, 0x103, 0x11);
678
679 /* Enable format auto detect */
680 cx25840_write(client, 0x400, 0);
681 /* Fast subchroma lock */
682 /* White crush, Chroma AGC & Chroma Killer enabled */
683 cx25840_write(client, 0x401, 0xe8);
684
149783b5
SD		 685 /* Do the firmware load in a work handler to prevent.
686 Otherwise the kernel is blocked waiting for the
687 bit-banging i2c interface to finish uploading the
688 firmware. */
689 INIT_WORK(&state->fw_work, cx25840_work_handler);
690 init_waitqueue_head(&state->fw_wait);
691 q = create_singlethread_workqueue("cx25840_fw");
692 prepare_to_wait(&state->fw_wait, &wait, TASK_UNINTERRUPTIBLE);
693 queue_work(q, &state->fw_work);
694 schedule();
695 finish_wait(&state->fw_wait, &wait);
696 destroy_workqueue(q);
697
698 cx25840_std_setup(client);
699
700 /* (re)set input */
701 set_input(client, state->vid_input, state->aud_input);
702
703 /* start microcontroller */
704 cx25840_and_or(client, 0x803, ~0x10, 0x10);
99d38909
ST		 705
706 /* CC raw enable */
707 cx25840_write(client, 0x404, 0x0b);
708
709 /* CC on */
710 cx25840_write(client, 0x42f, 0x66);
711 cx25840_write4(client, 0x474, 0x1e1e601a);
149783b5
SD		 712}
713
714/* ----------------------------------------------------------------------- */
715
cb5aa1c6
HV		 716void cx25840_std_setup(struct i2c_client *client)
717{
9357b31c 718 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
cb5aa1c6
HV		 719 v4l2_std_id std = state->std;
720 int hblank, hactive, burst, vblank, vactive, sc;
721 int vblank656, src_decimation;
722 int luma_lpf, uv_lpf, comb;
723 u32 pll_int, pll_frac, pll_post;
724
725 /* datasheet startup, step 8d */
726 if (std & ~V4L2_STD_NTSC)
727 cx25840_write(client, 0x49f, 0x11);
728 else
729 cx25840_write(client, 0x49f, 0x14);
730
731 if (std & V4L2_STD_625_50) {
732 hblank = 132;
733 hactive = 720;
734 burst = 93;
735 vblank = 36;
736 vactive = 580;
737 vblank656 = 40;
738 src_decimation = 0x21f;
739 luma_lpf = 2;
740
741 if (std & V4L2_STD_SECAM) {
742 uv_lpf = 0;
743 comb = 0;
744 sc = 0x0a425f;
745 } else if (std == V4L2_STD_PAL_Nc) {
746 uv_lpf = 1;
747 comb = 0x20;
748 sc = 556453;
749 } else {
750 uv_lpf = 1;
751 comb = 0x20;
752 sc = 688739;
753 }
754 } else {
755 hactive = 720;
756 hblank = 122;
757 vactive = 487;
758 luma_lpf = 1;
759 uv_lpf = 1;
760
761 src_decimation = 0x21f;
762 if (std == V4L2_STD_PAL_60) {
763 vblank = 26;
764 vblank656 = 26;
765 burst = 0x5b;
766 luma_lpf = 2;
767 comb = 0x20;
768 sc = 688739;
769 } else if (std == V4L2_STD_PAL_M) {
770 vblank = 20;
771 vblank656 = 24;
772 burst = 0x61;
773 comb = 0x20;
774 sc = 555452;
775 } else {
776 vblank = 26;
777 vblank656 = 26;
778 burst = 0x5b;
779 comb = 0x66;
780 sc = 556063;
781 }
782 }
783
784 /* DEBUG: Displays configured PLL frequency */
2a03f034 785 if (!is_cx231xx(state)) {
95b14fb2
MCC		 786 pll_int = cx25840_read(client, 0x108);
787 pll_frac = cx25840_read4(client, 0x10c) & 0x1ffffff;
788 pll_post = cx25840_read(client, 0x109);
cb5aa1c6 789 v4l_dbg(1, cx25840_debug, client,
95b14fb2
MCC		 790 "PLL regs = int: %u, frac: %u, post: %u\n",
791 pll_int, pll_frac, pll_post);
792
793 if (pll_post) {
794 int fin, fsc;
795 int pll = (28636363L * ((((u64)pll_int) << 25L) + pll_frac)) >> 25L;
796
797 pll /= pll_post;
798 v4l_dbg(1, cx25840_debug, client, "PLL = %d.%06d MHz\n",
799 pll / 1000000, pll % 1000000);
800 v4l_dbg(1, cx25840_debug, client, "PLL/8 = %d.%06d MHz\n",
801 pll / 8000000, (pll / 8) % 1000000);
802
803 fin = ((u64)src_decimation * pll) >> 12;
804 v4l_dbg(1, cx25840_debug, client,
805 "ADC Sampling freq = %d.%06d MHz\n",
806 fin / 1000000, fin % 1000000);
807
808 fsc = (((u64)sc) * pll) >> 24L;
809 v4l_dbg(1, cx25840_debug, client,
810 "Chroma sub-carrier freq = %d.%06d MHz\n",
811 fsc / 1000000, fsc % 1000000);
812
813 v4l_dbg(1, cx25840_debug, client, "hblank %i, hactive %i, "
814 "vblank %i, vactive %i, vblank656 %i, src_dec %i, "
815 "burst 0x%02x, luma_lpf %i, uv_lpf %i, comb 0x%02x, "
816 "sc 0x%06x\n",
817 hblank, hactive, vblank, vactive, vblank656,
818 src_decimation, burst, luma_lpf, uv_lpf, comb, sc);
819 }
cb5aa1c6
HV		 820 }
821
822 /* Sets horizontal blanking delay and active lines */
823 cx25840_write(client, 0x470, hblank);
824 cx25840_write(client, 0x471,
825 0xff & (((hblank >> 8) & 0x3) | (hactive << 4)));
826 cx25840_write(client, 0x472, hactive >> 4);
827
828 /* Sets burst gate delay */
829 cx25840_write(client, 0x473, burst);
830
831 /* Sets vertical blanking delay and active duration */
832 cx25840_write(client, 0x474, vblank);
833 cx25840_write(client, 0x475,
834 0xff & (((vblank >> 8) & 0x3) | (vactive << 4)));
835 cx25840_write(client, 0x476, vactive >> 4);
836 cx25840_write(client, 0x477, vblank656);
837
838 /* Sets src decimation rate */
839 cx25840_write(client, 0x478, 0xff & src_decimation);
840 cx25840_write(client, 0x479, 0xff & (src_decimation >> 8));
841
842 /* Sets Luma and UV Low pass filters */
843 cx25840_write(client, 0x47a, luma_lpf << 6 | ((uv_lpf << 4) & 0x30));
844
845 /* Enables comb filters */
846 cx25840_write(client, 0x47b, comb);
847
848 /* Sets SC Step*/
849 cx25840_write(client, 0x47c, sc);
850 cx25840_write(client, 0x47d, 0xff & sc >> 8);
851 cx25840_write(client, 0x47e, 0xff & sc >> 16);
852
853 /* Sets VBI parameters */
854 if (std & V4L2_STD_625_50) {
855 cx25840_write(client, 0x47f, 0x01);
856 state->vbi_line_offset = 5;
857 } else {
858 cx25840_write(client, 0x47f, 0x00);
859 state->vbi_line_offset = 8;
860 }
861}
862
863/* ----------------------------------------------------------------------- */
864
bd985160
HV		 865static void input_change(struct i2c_client *client)
866{
9357b31c 867 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
081b496a 868 v4l2_std_id std = state->std;
bd985160 869
73dcddc5
HV		 870 /* Follow step 8c and 8d of section 3.16 in the cx25840 datasheet */
871 if (std & V4L2_STD_SECAM) {
872 cx25840_write(client, 0x402, 0);
873 }
874 else {
875 cx25840_write(client, 0x402, 0x04);
876 cx25840_write(client, 0x49f, (std & V4L2_STD_NTSC) ? 0x14 : 0x11);
877 }
878 cx25840_and_or(client, 0x401, ~0x60, 0);
879 cx25840_and_or(client, 0x401, ~0x60, 0x60);
5af79f86
SB		 880
881 /* Don't write into audio registers on cx2583x chips */
882 if (is_cx2583x(state))
883 return;
884
82677618 885 cx25840_and_or(client, 0x810, ~0x01, 1);
73dcddc5 886
39c4ad6a
HV		 887 if (state->radio) {
888 cx25840_write(client, 0x808, 0xf9);
889 cx25840_write(client, 0x80b, 0x00);
890 }
891 else if (std & V4L2_STD_525_60) {
d97a11e0
HV		 892 /* Certain Hauppauge PVR150 models have a hardware bug
893 that causes audio to drop out. For these models the
894 audio standard must be set explicitly.
895 To be precise: it affects cards with tuner models
896 85, 99 and 112 (model numbers from tveeprom). */
897 int hw_fix = state->pvr150_workaround;
898
899 if (std == V4L2_STD_NTSC_M_JP) {
f95006f8 900 /* Japan uses EIAJ audio standard */
d97a11e0
HV		 901 cx25840_write(client, 0x808, hw_fix ? 0x2f : 0xf7);
902 } else if (std == V4L2_STD_NTSC_M_KR) {
903 /* South Korea uses A2 audio standard */
904 cx25840_write(client, 0x808, hw_fix ? 0x3f : 0xf8);
f95006f8
HV		 905 } else {
906 /* Others use the BTSC audio standard */
d97a11e0 907 cx25840_write(client, 0x808, hw_fix ? 0x1f : 0xf6);
f95006f8 908 }
bd985160 909 cx25840_write(client, 0x80b, 0x00);
839e4a4a 910 } else if (std & V4L2_STD_PAL) {
3c3099d5 911 /* Autodetect audio standard and audio system */
839e4a4a 912 cx25840_write(client, 0x808, 0xff);
25985edc 913 /* Since system PAL-L is pretty much non-existent and
3c3099d5
AP		 914 not used by any public broadcast network, force
915 6.5 MHz carrier to be interpreted as System DK,
916 this avoids DK audio detection instability */
917 cx25840_write(client, 0x80b, 0x00);
839e4a4a 918 } else if (std & V4L2_STD_SECAM) {
3c3099d5 919 /* Autodetect audio standard and audio system */
839e4a4a 920 cx25840_write(client, 0x808, 0xff);
3c3099d5
AP		 921 /* If only one of SECAM-DK / SECAM-L is required, then force
922 6.5MHz carrier, else autodetect it */
923 if ((std & V4L2_STD_SECAM_DK) &&
924 !(std & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC))) {
925 /* 6.5 MHz carrier to be interpreted as System DK */
926 cx25840_write(client, 0x80b, 0x00);
927 } else if (!(std & V4L2_STD_SECAM_DK) &&
928 (std & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC))) {
929 /* 6.5 MHz carrier to be interpreted as System L */
930 cx25840_write(client, 0x80b, 0x08);
931 } else {
932 /* 6.5 MHz carrier to be autodetected */
933 cx25840_write(client, 0x80b, 0x10);
934 }
bd985160
HV		 935 }
936
82677618 937 cx25840_and_or(client, 0x810, ~0x01, 0);
bd985160
HV		 938}
939
a8bbf12a
HV		 940static int set_input(struct i2c_client *client, enum cx25840_video_input vid_input,
941 enum cx25840_audio_input aud_input)
bd985160 942{
9357b31c 943 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
a8bbf12a
HV		 944 u8 is_composite = (vid_input >= CX25840_COMPOSITE1 &&
945 vid_input <= CX25840_COMPOSITE8);
fb29ab96
DW		 946 u8 is_component = (vid_input & CX25840_COMPONENT_ON) ==
947 CX25840_COMPONENT_ON;
948 int luma = vid_input & 0xf0;
949 int chroma = vid_input & 0xf00;
a8bbf12a 950 u8 reg;
bd985160 951
f234081b
ST		 952 v4l_dbg(1, cx25840_debug, client,
953 "decoder set video input %d, audio input %d\n",
954 vid_input, aud_input);
bd985160 955
f234081b
ST		 956 if (vid_input >= CX25840_VIN1_CH1) {
957 v4l_dbg(1, cx25840_debug, client, "vid_input 0x%x\n",
958 vid_input);
959 reg = vid_input & 0xff;
10e43d90
KK		 960 is_composite = !is_component &&
961 ((vid_input & CX25840_SVIDEO_ON) != CX25840_SVIDEO_ON);
f234081b
ST		 962
963 v4l_dbg(1, cx25840_debug, client, "mux cfg 0x%x comp=%d\n",
964 reg, is_composite);
fb29ab96 965 } else if (is_composite) {
a8bbf12a
HV		 966 reg = 0xf0 + (vid_input - CX25840_COMPOSITE1);
967 } else {
a8bbf12a 968 if ((vid_input & ~0xff0) ||
45270a15 969 luma < CX25840_SVIDEO_LUMA1 || luma > CX25840_SVIDEO_LUMA8 ||
a8bbf12a 970 chroma < CX25840_SVIDEO_CHROMA4 || chroma > CX25840_SVIDEO_CHROMA8) {
f234081b
ST		 971 v4l_err(client, "0x%04x is not a valid video input!\n",
972 vid_input);
a8bbf12a 973 return -EINVAL;
bd985160 974 }
a8bbf12a
HV		 975 reg = 0xf0 + ((luma - CX25840_SVIDEO_LUMA1) >> 4);
976 if (chroma >= CX25840_SVIDEO_CHROMA7) {
977 reg &= 0x3f;
978 reg |= (chroma - CX25840_SVIDEO_CHROMA7) >> 2;
bd985160 979 } else {
a8bbf12a
HV		 980 reg &= 0xcf;
981 reg |= (chroma - CX25840_SVIDEO_CHROMA4) >> 4;
bd985160 982 }
a8bbf12a 983 }
bd985160 984
f234081b
ST		 985 /* The caller has previously prepared the correct routing
986 * configuration in reg (for the cx23885) so we have no
987 * need to attempt to flip bits for earlier av decoders.
988 */
2a03f034 989 if (!is_cx2388x(state) && !is_cx231xx(state)) {
f234081b
ST		 990 switch (aud_input) {
991 case CX25840_AUDIO_SERIAL:
992 /* do nothing, use serial audio input */
993 break;
994 case CX25840_AUDIO4: reg &= ~0x30; break;
995 case CX25840_AUDIO5: reg &= ~0x30; reg |= 0x10; break;
996 case CX25840_AUDIO6: reg &= ~0x30; reg |= 0x20; break;
997 case CX25840_AUDIO7: reg &= ~0xc0; break;
998 case CX25840_AUDIO8: reg &= ~0xc0; reg |= 0x40; break;
bd985160 999
f234081b
ST		 1000 default:
1001 v4l_err(client, "0x%04x is not a valid audio input!\n",
1002 aud_input);
1003 return -EINVAL;
1004 }
bd985160
HV		 1005 }
1006
a8bbf12a 1007 cx25840_write(client, 0x103, reg);
f234081b 1008
fb29ab96
DW		 1009 /* Set INPUT_MODE to Composite, S-Video or Component */
1010 if (is_component)
1011 cx25840_and_or(client, 0x401, ~0x6, 0x6);
1012 else
1013 cx25840_and_or(client, 0x401, ~0x6, is_composite ? 0 : 0x02);
f234081b 1014
2a03f034 1015 if (!is_cx2388x(state) && !is_cx231xx(state)) {
f234081b
ST		 1016 /* Set CH_SEL_ADC2 to 1 if input comes from CH3 */
1017 cx25840_and_or(client, 0x102, ~0x2, (reg & 0x80) == 0 ? 2 : 0);
1018 /* Set DUAL_MODE_ADC2 to 1 if input comes from both CH2&CH3 */
1019 if ((reg & 0xc0) != 0xc0 && (reg & 0x30) != 0x30)
1020 cx25840_and_or(client, 0x102, ~0x4, 4);
1021 else
1022 cx25840_and_or(client, 0x102, ~0x4, 0);
1023 } else {
fb29ab96
DW		 1024 /* Set DUAL_MODE_ADC2 to 1 if component*/
1025 cx25840_and_or(client, 0x102, ~0x4, is_component ? 0x4 : 0x0);
1026 if (is_composite) {
f234081b
ST		 1027 /* ADC2 input select channel 2 */
1028 cx25840_and_or(client, 0x102, ~0x2, 0);
fb29ab96
DW		 1029 } else if (!is_component) {
1030 /* S-Video */
1031 if (chroma >= CX25840_SVIDEO_CHROMA7) {
1032 /* ADC2 input select channel 3 */
1033 cx25840_and_or(client, 0x102, ~0x2, 2);
1034 } else {
1035 /* ADC2 input select channel 2 */
1036 cx25840_and_or(client, 0x102, ~0x2, 0);
1037 }
1038 }
f234081b 1039 }
a8bbf12a
HV		 1040
1041 state->vid_input = vid_input;
1042 state->aud_input = aud_input;
5af79f86
SB		 1043 cx25840_audio_set_path(client);
1044 input_change(client);
f234081b 1045
2a03f034 1046 if (is_cx2388x(state)) {
f234081b
ST		 1047 /* Audio channel 1 src : Parallel 1 */
1048 cx25840_write(client, 0x124, 0x03);
1049
1050 /* Select AFE clock pad output source */
1051 cx25840_write(client, 0x144, 0x05);
1052
1053 /* I2S_IN_CTL: I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1 */
1054 cx25840_write(client, 0x914, 0xa0);
1055
149783b5
SD		 1056 /* I2S_OUT_CTL:
1057 * I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1
1058 * I2S_OUT_MASTER_MODE = Master
1059 */
1060 cx25840_write(client, 0x918, 0xa0);
1061 cx25840_write(client, 0x919, 0x01);
2a03f034 1062 } else if (is_cx231xx(state)) {
149783b5
SD		 1063 /* Audio channel 1 src : Parallel 1 */
1064 cx25840_write(client, 0x124, 0x03);
1065
1066 /* I2S_IN_CTL: I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1 */
1067 cx25840_write(client, 0x914, 0xa0);
1068
f234081b
ST		 1069 /* I2S_OUT_CTL:
1070 * I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1
1071 * I2S_OUT_MASTER_MODE = Master
1072 */
1073 cx25840_write(client, 0x918, 0xa0);
1074 cx25840_write(client, 0x919, 0x01);
2ccdd9a5
ST		 1075 }
1076
1077 if (is_cx2388x(state) && (aud_input == CX25840_AUDIO7)) {
1078 /* Configure audio from LR1 or LR2 input */
1079 cx25840_write4(client, 0x910, 0);
1080 cx25840_write4(client, 0x8d0, 0x63073);
1081 } else
1082 if (is_cx2388x(state) && (aud_input == CX25840_AUDIO8)) {
1083 /* Configure audio from tuner/sif input */
1084 cx25840_write4(client, 0x910, 0x12b000c9);
1085 cx25840_write4(client, 0x8d0, 0x1f063870);
f234081b
ST		 1086 }
1087
bd985160
HV		 1088 return 0;
1089}
1090
1091/* ----------------------------------------------------------------------- */
1092
081b496a 1093static int set_v4lstd(struct i2c_client *client)
bd985160 1094{
9357b31c 1095 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
081b496a
HV		 1096 u8 fmt = 0; /* zero is autodetect */
1097 u8 pal_m = 0;
468a0a54
MCC		 1098
1099 /* First tests should be against specific std */
081b496a
HV		 1100 if (state->std == V4L2_STD_NTSC_M_JP) {
1101 fmt = 0x2;
1102 } else if (state->std == V4L2_STD_NTSC_443) {
1103 fmt = 0x3;
1104 } else if (state->std == V4L2_STD_PAL_M) {
1105 pal_m = 1;
1106 fmt = 0x5;
1107 } else if (state->std == V4L2_STD_PAL_N) {
1108 fmt = 0x6;
1109 } else if (state->std == V4L2_STD_PAL_Nc) {
1110 fmt = 0x7;
1111 } else if (state->std == V4L2_STD_PAL_60) {
1112 fmt = 0x8;
468a0a54
MCC		 1113 } else {
1114 /* Then, test against generic ones */
081b496a
HV		 1115 if (state->std & V4L2_STD_NTSC)
1116 fmt = 0x1;
1117 else if (state->std & V4L2_STD_PAL)
1118 fmt = 0x4;
1119 else if (state->std & V4L2_STD_SECAM)
1120 fmt = 0xc;
bd985160
HV		 1121 }
1122
839e4a4a
MCC		 1123 v4l_dbg(1, cx25840_debug, client, "changing video std to fmt %i\n",fmt);
1124
73dcddc5
HV		 1125 /* Follow step 9 of section 3.16 in the cx25840 datasheet.
1126 Without this PAL may display a vertical ghosting effect.
1127 This happens for example with the Yuan MPC622. */
1128 if (fmt >= 4 && fmt < 8) {
1129 /* Set format to NTSC-M */
1130 cx25840_and_or(client, 0x400, ~0xf, 1);
1131 /* Turn off LCOMB */
1132 cx25840_and_or(client, 0x47b, ~6, 0);
1133 }
bd985160 1134 cx25840_and_or(client, 0x400, ~0xf, fmt);
081b496a 1135 cx25840_and_or(client, 0x403, ~0x3, pal_m);
cb5aa1c6 1136 cx25840_std_setup(client);
2a03f034 1137 if (!is_cx2583x(state))
081b496a 1138 input_change(client);
bd985160
HV		 1139 return 0;
1140}
1141
bd985160
HV		 1142/* ----------------------------------------------------------------------- */
1143
e34e658b 1144static int cx25840_s_ctrl(struct v4l2_ctrl *ctrl)
bd985160 1145{
e34e658b 1146 struct v4l2_subdev *sd = to_sd(ctrl);
9357b31c 1147 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160
HV		 1148
1149 switch (ctrl->id) {
bd985160 1150 case V4L2_CID_BRIGHTNESS:
e34e658b 1151 cx25840_write(client, 0x414, ctrl->val - 128);
bd985160
HV		 1152 break;
1153
1154 case V4L2_CID_CONTRAST:
e34e658b 1155 cx25840_write(client, 0x415, ctrl->val << 1);
bd985160
HV		 1156 break;
1157
1158 case V4L2_CID_SATURATION:
e34e658b
HV		 1159 cx25840_write(client, 0x420, ctrl->val << 1);
1160 cx25840_write(client, 0x421, ctrl->val << 1);
bd985160
HV		 1161 break;
1162
1163 case V4L2_CID_HUE:
e34e658b 1164 cx25840_write(client, 0x422, ctrl->val);
bd985160
HV		 1165 break;
1166
bd985160
HV		 1167 default:
1168 return -EINVAL;
1169 }
1170
1171 return 0;
1172}
1173
1174/* ----------------------------------------------------------------------- */
1175
96fd004f 1176static int cx25840_s_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *fmt)
bd985160 1177{
9357b31c
HV		 1178 struct cx25840_state *state = to_state(sd);
1179 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160 1180 int HSC, VSC, Vsrc, Hsrc, filter, Vlines;
081b496a 1181 int is_50Hz = !(state->std & V4L2_STD_525_60);
bd985160 1182
96fd004f
HV		 1183 if (fmt->code != V4L2_MBUS_FMT_FIXED)
1184 return -EINVAL;
bd985160 1185
96fd004f
HV		 1186 fmt->field = V4L2_FIELD_INTERLACED;
1187 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
bd985160 1188
96fd004f
HV		 1189 Vsrc = (cx25840_read(client, 0x476) & 0x3f) << 4;
1190 Vsrc |= (cx25840_read(client, 0x475) & 0xf0) >> 4;
bd985160 1191
96fd004f
HV		 1192 Hsrc = (cx25840_read(client, 0x472) & 0x3f) << 4;
1193 Hsrc |= (cx25840_read(client, 0x471) & 0xf0) >> 4;
bd985160 1194
96fd004f 1195 Vlines = fmt->height + (is_50Hz ? 4 : 7);
bd985160 1196
96fd004f
HV		 1197 if ((fmt->width * 16 < Hsrc) || (Hsrc < fmt->width) ||
1198 (Vlines * 8 < Vsrc) || (Vsrc < Vlines)) {
1199 v4l_err(client, "%dx%d is not a valid size!\n",
1200 fmt->width, fmt->height);
1201 return -ERANGE;
1202 }
bd985160 1203
96fd004f
HV		 1204 HSC = (Hsrc * (1 << 20)) / fmt->width - (1 << 20);
1205 VSC = (1 << 16) - (Vsrc * (1 << 9) / Vlines - (1 << 9));
1206 VSC &= 0x1fff;
1207
1208 if (fmt->width >= 385)
1209 filter = 0;
1210 else if (fmt->width > 192)
1211 filter = 1;
1212 else if (fmt->width > 96)
1213 filter = 2;
1214 else
1215 filter = 3;
1216
1217 v4l_dbg(1, cx25840_debug, client, "decoder set size %dx%d -> scale %ux%u\n",
1218 fmt->width, fmt->height, HSC, VSC);
1219
1220 /* HSCALE=HSC */
1221 cx25840_write(client, 0x418, HSC & 0xff);
1222 cx25840_write(client, 0x419, (HSC >> 8) & 0xff);
1223 cx25840_write(client, 0x41a, HSC >> 16);
1224 /* VSCALE=VSC */
1225 cx25840_write(client, 0x41c, VSC & 0xff);
1226 cx25840_write(client, 0x41d, VSC >> 8);
1227 /* VS_INTRLACE=1 VFILT=filter */
1228 cx25840_write(client, 0x41e, 0x8 | filter);
1229 return 0;
1230}
1231
bd985160
HV		 1232/* ----------------------------------------------------------------------- */
1233
1a39275a
HV		 1234static void log_video_status(struct i2c_client *client)
1235{
1236 static const char *const fmt_strs[] = {
1237 "0x0",
1238 "NTSC-M", "NTSC-J", "NTSC-4.43",
1239 "PAL-BDGHI", "PAL-M", "PAL-N", "PAL-Nc", "PAL-60",
1240 "0x9", "0xA", "0xB",
1241 "SECAM",
1242 "0xD", "0xE", "0xF"
1243 };
1244
9357b31c 1245 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
1a39275a
HV		 1246 u8 vidfmt_sel = cx25840_read(client, 0x400) & 0xf;
1247 u8 gen_stat1 = cx25840_read(client, 0x40d);
1248 u8 gen_stat2 = cx25840_read(client, 0x40e);
1249 int vid_input = state->vid_input;
1250
1251 v4l_info(client, "Video signal: %spresent\n",
1252 (gen_stat2 & 0x20) ? "" : "not ");
1253 v4l_info(client, "Detected format: %s\n",
1254 fmt_strs[gen_stat1 & 0xf]);
1255
1256 v4l_info(client, "Specified standard: %s\n",
1257 vidfmt_sel ? fmt_strs[vidfmt_sel] : "automatic detection");
1258
1259 if (vid_input >= CX25840_COMPOSITE1 &&
1260 vid_input <= CX25840_COMPOSITE8) {
1261 v4l_info(client, "Specified video input: Composite %d\n",
1262 vid_input - CX25840_COMPOSITE1 + 1);
1263 } else {
1264 v4l_info(client, "Specified video input: S-Video (Luma In%d, Chroma In%d)\n",
1265 (vid_input & 0xf0) >> 4, (vid_input & 0xf00) >> 8);
1266 }
1267
1268 v4l_info(client, "Specified audioclock freq: %d Hz\n", state->audclk_freq);
1269}
1270
1271/* ----------------------------------------------------------------------- */
1272
1273static void log_audio_status(struct i2c_client *client)
1274{
9357b31c 1275 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
1a39275a
HV		 1276 u8 download_ctl = cx25840_read(client, 0x803);
1277 u8 mod_det_stat0 = cx25840_read(client, 0x804);
1278 u8 mod_det_stat1 = cx25840_read(client, 0x805);
1279 u8 audio_config = cx25840_read(client, 0x808);
1280 u8 pref_mode = cx25840_read(client, 0x809);
1281 u8 afc0 = cx25840_read(client, 0x80b);
1282 u8 mute_ctl = cx25840_read(client, 0x8d3);
1283 int aud_input = state->aud_input;
1284 char *p;
1285
1286 switch (mod_det_stat0) {
1287 case 0x00: p = "mono"; break;
1288 case 0x01: p = "stereo"; break;
1289 case 0x02: p = "dual"; break;
1290 case 0x04: p = "tri"; break;
1291 case 0x10: p = "mono with SAP"; break;
1292 case 0x11: p = "stereo with SAP"; break;
1293 case 0x12: p = "dual with SAP"; break;
1294 case 0x14: p = "tri with SAP"; break;
1295 case 0xfe: p = "forced mode"; break;
1296 default: p = "not defined";
1297 }
1298 v4l_info(client, "Detected audio mode: %s\n", p);
1299
1300 switch (mod_det_stat1) {
1301 case 0x00: p = "not defined"; break;
1302 case 0x01: p = "EIAJ"; break;
1303 case 0x02: p = "A2-M"; break;
1304 case 0x03: p = "A2-BG"; break;
1305 case 0x04: p = "A2-DK1"; break;
1306 case 0x05: p = "A2-DK2"; break;
1307 case 0x06: p = "A2-DK3"; break;
1308 case 0x07: p = "A1 (6.0 MHz FM Mono)"; break;
1309 case 0x08: p = "AM-L"; break;
1310 case 0x09: p = "NICAM-BG"; break;
1311 case 0x0a: p = "NICAM-DK"; break;
1312 case 0x0b: p = "NICAM-I"; break;
1313 case 0x0c: p = "NICAM-L"; break;
1314 case 0x0d: p = "BTSC/EIAJ/A2-M Mono (4.5 MHz FMMono)"; break;
1315 case 0x0e: p = "IF FM Radio"; break;
1316 case 0x0f: p = "BTSC"; break;
1317 case 0x10: p = "high-deviation FM"; break;
1318 case 0x11: p = "very high-deviation FM"; break;
1319 case 0xfd: p = "unknown audio standard"; break;
1320 case 0xfe: p = "forced audio standard"; break;
1321 case 0xff: p = "no detected audio standard"; break;
1322 default: p = "not defined";
1323 }
1324 v4l_info(client, "Detected audio standard: %s\n", p);
1a39275a
HV		 1325 v4l_info(client, "Audio microcontroller: %s\n",
1326 (download_ctl & 0x10) ?
1327 ((mute_ctl & 0x2) ? "detecting" : "running") : "stopped");
1328
1329 switch (audio_config >> 4) {
1330 case 0x00: p = "undefined"; break;
1331 case 0x01: p = "BTSC"; break;
1332 case 0x02: p = "EIAJ"; break;
1333 case 0x03: p = "A2-M"; break;
1334 case 0x04: p = "A2-BG"; break;
1335 case 0x05: p = "A2-DK1"; break;
1336 case 0x06: p = "A2-DK2"; break;
1337 case 0x07: p = "A2-DK3"; break;
1338 case 0x08: p = "A1 (6.0 MHz FM Mono)"; break;
1339 case 0x09: p = "AM-L"; break;
1340 case 0x0a: p = "NICAM-BG"; break;
1341 case 0x0b: p = "NICAM-DK"; break;
1342 case 0x0c: p = "NICAM-I"; break;
1343 case 0x0d: p = "NICAM-L"; break;
1344 case 0x0e: p = "FM radio"; break;
1345 case 0x0f: p = "automatic detection"; break;
1346 default: p = "undefined";
1347 }
1348 v4l_info(client, "Configured audio standard: %s\n", p);
1349
1350 if ((audio_config >> 4) < 0xF) {
1351 switch (audio_config & 0xF) {
1352 case 0x00: p = "MONO1 (LANGUAGE A/Mono L+R channel for BTSC, EIAJ, A2)"; break;
1353 case 0x01: p = "MONO2 (LANGUAGE B)"; break;
1354 case 0x02: p = "MONO3 (STEREO forced MONO)"; break;
1355 case 0x03: p = "MONO4 (NICAM ANALOG-Language C/Analog Fallback)"; break;
1356 case 0x04: p = "STEREO"; break;
1357 case 0x05: p = "DUAL1 (AB)"; break;
1358 case 0x06: p = "DUAL2 (AC) (FM)"; break;
1359 case 0x07: p = "DUAL3 (BC) (FM)"; break;
1360 case 0x08: p = "DUAL4 (AC) (AM)"; break;
1361 case 0x09: p = "DUAL5 (BC) (AM)"; break;
1362 case 0x0a: p = "SAP"; break;
1363 default: p = "undefined";
1364 }
1365 v4l_info(client, "Configured audio mode: %s\n", p);
1366 } else {
1367 switch (audio_config & 0xF) {
1368 case 0x00: p = "BG"; break;
1369 case 0x01: p = "DK1"; break;
1370 case 0x02: p = "DK2"; break;
1371 case 0x03: p = "DK3"; break;
1372 case 0x04: p = "I"; break;
1373 case 0x05: p = "L"; break;
1374 case 0x06: p = "BTSC"; break;
1375 case 0x07: p = "EIAJ"; break;
1376 case 0x08: p = "A2-M"; break;
1377 case 0x09: p = "FM Radio"; break;
1378 case 0x0f: p = "automatic standard and mode detection"; break;
1379 default: p = "undefined";
1380 }
1381 v4l_info(client, "Configured audio system: %s\n", p);
1382 }
1383
1384 if (aud_input) {
1385 v4l_info(client, "Specified audio input: Tuner (In%d)\n", aud_input);
1386 } else {
1387 v4l_info(client, "Specified audio input: External\n");
1388 }
1389
1390 switch (pref_mode & 0xf) {
1391 case 0: p = "mono/language A"; break;
1392 case 1: p = "language B"; break;
1393 case 2: p = "language C"; break;
1394 case 3: p = "analog fallback"; break;
1395 case 4: p = "stereo"; break;
1396 case 5: p = "language AC"; break;
1397 case 6: p = "language BC"; break;
1398 case 7: p = "language AB"; break;
1399 default: p = "undefined";
1400 }
1401 v4l_info(client, "Preferred audio mode: %s\n", p);
1402
1403 if ((audio_config & 0xf) == 0xf) {
1404 switch ((afc0 >> 3) & 0x3) {
1405 case 0: p = "system DK"; break;
1406 case 1: p = "system L"; break;
1407 case 2: p = "autodetect"; break;
1408 default: p = "undefined";
1409 }
1410 v4l_info(client, "Selected 65 MHz format: %s\n", p);
1411
1412 switch (afc0 & 0x7) {
1413 case 0: p = "chroma"; break;
1414 case 1: p = "BTSC"; break;
1415 case 2: p = "EIAJ"; break;
1416 case 3: p = "A2-M"; break;
1417 case 4: p = "autodetect"; break;
1418 default: p = "undefined";
1419 }
1420 v4l_info(client, "Selected 45 MHz format: %s\n", p);
1421 }
1422}
1423
1424/* ----------------------------------------------------------------------- */
1425
cc26b076 1426/* This load_fw operation must be called to load the driver's firmware.
6ca187ab
HV		 1427 Without this the audio standard detection will fail and you will
1428 only get mono.
1429
1430 Since loading the firmware is often problematic when the driver is
1431 compiled into the kernel I recommend postponing calling this function
1432 until the first open of the video device. Another reason for
1433 postponing it is that loading this firmware takes a long time (seconds)
1434 due to the slow i2c bus speed. So it will speed up the boot process if
1435 you can avoid loading the fw as long as the video device isn't used. */
cc26b076 1436static int cx25840_load_fw(struct v4l2_subdev *sd)
bd985160 1437{
9357b31c
HV		 1438 struct cx25840_state *state = to_state(sd);
1439 struct i2c_client *client = v4l2_get_subdevdata(sd);
c976bc82
HV		 1440
1441 if (!state->is_initialized) {
cc26b076 1442 /* initialize and load firmware */
c976bc82 1443 state->is_initialized = 1;
2a03f034 1444 if (is_cx2583x(state))
c976bc82 1445 cx25836_initialize(client);
2a03f034 1446 else if (is_cx2388x(state))
f234081b 1447 cx23885_initialize(client);
2a03f034 1448 else if (is_cx231xx(state))
149783b5 1449 cx231xx_initialize(client);
c976bc82 1450 else
89fc4eb9 1451 cx25840_initialize(client);
c976bc82 1452 }
9357b31c
HV		 1453 return 0;
1454}
c976bc82 1455
bd985160 1456#ifdef CONFIG_VIDEO_ADV_DEBUG
aecde8b5 1457static int cx25840_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
9357b31c
HV		 1458{
1459 struct i2c_client *client = v4l2_get_subdevdata(sd);
f234081b 1460
aecde8b5 1461 if (!v4l2_chip_match_i2c_client(client, &reg->match))
9357b31c
HV		 1462 return -EINVAL;
1463 if (!capable(CAP_SYS_ADMIN))
1464 return -EPERM;
aecde8b5 1465 reg->size = 1;
9357b31c
HV		 1466 reg->val = cx25840_read(client, reg->reg & 0x0fff);
1467 return 0;
1468}
1469
aecde8b5 1470static int cx25840_s_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
9357b31c
HV		 1471{
1472 struct i2c_client *client = v4l2_get_subdevdata(sd);
1473
aecde8b5 1474 if (!v4l2_chip_match_i2c_client(client, &reg->match))
9357b31c
HV		 1475 return -EINVAL;
1476 if (!capable(CAP_SYS_ADMIN))
1477 return -EPERM;
1478 cx25840_write(client, reg->reg & 0x0fff, reg->val & 0xff);
1479 return 0;
1480}
bd985160
HV		 1481#endif
1482
3ccc646b
AW		 1483static int cx25840_s_audio_stream(struct v4l2_subdev *sd, int enable)
1484{
1485 struct cx25840_state *state = to_state(sd);
1486 struct i2c_client *client = v4l2_get_subdevdata(sd);
1487 u8 v;
1488
1489 if (is_cx2583x(state) || is_cx2388x(state) || is_cx231xx(state))
1490 return 0;
1491
1492 v4l_dbg(1, cx25840_debug, client, "%s audio output\n",
1493 enable ? "enable" : "disable");
1494
1495 if (enable) {
1496 v = cx25840_read(client, 0x115) | 0x80;
1497 cx25840_write(client, 0x115, v);
1498 v = cx25840_read(client, 0x116) | 0x03;
1499 cx25840_write(client, 0x116, v);
1500 } else {
1501 v = cx25840_read(client, 0x115) & ~(0x80);
1502 cx25840_write(client, 0x115, v);
1503 v = cx25840_read(client, 0x116) & ~(0x03);
1504 cx25840_write(client, 0x116, v);
1505 }
1506 return 0;
1507}
1508
9357b31c
HV		 1509static int cx25840_s_stream(struct v4l2_subdev *sd, int enable)
1510{
1511 struct cx25840_state *state = to_state(sd);
1512 struct i2c_client *client = v4l2_get_subdevdata(sd);
3ccc646b 1513 u8 v;
bd985160 1514
3ccc646b 1515 v4l_dbg(1, cx25840_debug, client, "%s video output\n",
9357b31c
HV		 1516 enable ? "enable" : "disable");
1517 if (enable) {
2a03f034 1518 if (is_cx2388x(state) || is_cx231xx(state)) {
3ccc646b 1519 v = cx25840_read(client, 0x421) | 0x0b;
f234081b
ST		 1520 cx25840_write(client, 0x421, v);
1521 } else {
3ccc646b
AW		 1522 v = cx25840_read(client, 0x115) | 0x0c;
1523 cx25840_write(client, 0x115, v);
1524 v = cx25840_read(client, 0x116) | 0x04;
1525 cx25840_write(client, 0x116, v);
f234081b 1526 }
9357b31c 1527 } else {
2a03f034 1528 if (is_cx2388x(state) || is_cx231xx(state)) {
3ccc646b 1529 v = cx25840_read(client, 0x421) & ~(0x0b);
f234081b
ST		 1530 cx25840_write(client, 0x421, v);
1531 } else {
3ccc646b
AW		 1532 v = cx25840_read(client, 0x115) & ~(0x0c);
1533 cx25840_write(client, 0x115, v);
1534 v = cx25840_read(client, 0x116) & ~(0x04);
1535 cx25840_write(client, 0x116, v);
f234081b 1536 }
9357b31c
HV		 1537 }
1538 return 0;
1539}
bd985160 1540
9357b31c
HV		 1541static int cx25840_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
1542{
1543 struct cx25840_state *state = to_state(sd);
1544 struct i2c_client *client = v4l2_get_subdevdata(sd);
d92c20e0 1545
9357b31c
HV		 1546 if (state->radio == 0 && state->std == std)
1547 return 0;
1548 state->radio = 0;
1549 state->std = std;
1550 return set_v4lstd(client);
1551}
e2b8cf4c 1552
9357b31c
HV		 1553static int cx25840_s_radio(struct v4l2_subdev *sd)
1554{
1555 struct cx25840_state *state = to_state(sd);
d92c20e0 1556
9357b31c
HV		 1557 state->radio = 1;
1558 return 0;
1559}
bd985160 1560
5325b427
HV		 1561static int cx25840_s_video_routing(struct v4l2_subdev *sd,
1562 u32 input, u32 output, u32 config)
9357b31c
HV		 1563{
1564 struct cx25840_state *state = to_state(sd);
1565 struct i2c_client *client = v4l2_get_subdevdata(sd);
3faeeae4 1566
5325b427 1567 return set_input(client, input, state->aud_input);
9357b31c 1568}
bd985160 1569
5325b427
HV		 1570static int cx25840_s_audio_routing(struct v4l2_subdev *sd,
1571 u32 input, u32 output, u32 config)
9357b31c
HV		 1572{
1573 struct cx25840_state *state = to_state(sd);
1574 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160 1575
5325b427 1576 return set_input(client, state->vid_input, input);
9357b31c 1577}
bd985160 1578
9357b31c
HV		 1579static int cx25840_s_frequency(struct v4l2_subdev *sd, struct v4l2_frequency *freq)
1580{
9357b31c 1581 struct i2c_client *client = v4l2_get_subdevdata(sd);
a8bbf12a 1582
5af79f86 1583 input_change(client);
9357b31c
HV		 1584 return 0;
1585}
a8bbf12a 1586
9357b31c
HV		 1587static int cx25840_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1588{
1589 struct cx25840_state *state = to_state(sd);
1590 struct i2c_client *client = v4l2_get_subdevdata(sd);
1591 u8 vpres = cx25840_read(client, 0x40e) & 0x20;
1592 u8 mode;
1593 int val = 0;
bd985160 1594
9357b31c
HV		 1595 if (state->radio)
1596 return 0;
bd985160 1597
9357b31c 1598 vt->signal = vpres ? 0xffff : 0x0;
2a03f034 1599 if (is_cx2583x(state))
9357b31c 1600 return 0;
3faeeae4 1601
9357b31c
HV		 1602 vt->capability |=
1603 V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 |
1604 V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP;
e2b8cf4c 1605
9357b31c 1606 mode = cx25840_read(client, 0x804);
bd985160 1607
9357b31c
HV		 1608 /* get rxsubchans and audmode */
1609 if ((mode & 0xf) == 1)
1610 val |= V4L2_TUNER_SUB_STEREO;
1611 else
1612 val |= V4L2_TUNER_SUB_MONO;
bd985160 1613
9357b31c
HV		 1614 if (mode == 2 || mode == 4)
1615 val = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
bd985160 1616
9357b31c
HV		 1617 if (mode & 0x10)
1618 val |= V4L2_TUNER_SUB_SAP;
bd985160 1619
9357b31c
HV		 1620 vt->rxsubchans = val;
1621 vt->audmode = state->audmode;
1622 return 0;
1623}
bd985160 1624
9357b31c
HV		 1625static int cx25840_s_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1626{
1627 struct cx25840_state *state = to_state(sd);
1628 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160 1629
2a03f034 1630 if (state->radio || is_cx2583x(state))
9357b31c 1631 return 0;
8a4b275f 1632
9357b31c 1633 switch (vt->audmode) {
bd985160 1634 case V4L2_TUNER_MODE_MONO:
8a4b275f
HV		 1635 /* mono -> mono
1636 stereo -> mono
1637 bilingual -> lang1 */
bd985160
HV		 1638 cx25840_and_or(client, 0x809, ~0xf, 0x00);
1639 break;
301e22d6 1640 case V4L2_TUNER_MODE_STEREO:
8a4b275f
HV		 1641 case V4L2_TUNER_MODE_LANG1:
1642 /* mono -> mono
1643 stereo -> stereo
1644 bilingual -> lang1 */
bd985160
HV		 1645 cx25840_and_or(client, 0x809, ~0xf, 0x04);
1646 break;
301e22d6 1647 case V4L2_TUNER_MODE_LANG1_LANG2:
8a4b275f
HV		 1648 /* mono -> mono
1649 stereo -> stereo
1650 bilingual -> lang1/lang2 */
1651 cx25840_and_or(client, 0x809, ~0xf, 0x07);
1652 break;
bd985160 1653 case V4L2_TUNER_MODE_LANG2:
8a4b275f 1654 /* mono -> mono
301e22d6 1655 stereo -> stereo
8a4b275f 1656 bilingual -> lang2 */
bd985160
HV		 1657 cx25840_and_or(client, 0x809, ~0xf, 0x01);
1658 break;
8a4b275f
HV		 1659 default:
1660 return -EINVAL;
9357b31c
HV		 1661 }
1662 state->audmode = vt->audmode;
1663 return 0;
1664}
bd985160 1665
9357b31c
HV		 1666static int cx25840_reset(struct v4l2_subdev *sd, u32 val)
1667{
1668 struct cx25840_state *state = to_state(sd);
1669 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160 1670
2a03f034 1671 if (is_cx2583x(state))
9357b31c 1672 cx25836_initialize(client);
2a03f034 1673 else if (is_cx2388x(state))
9357b31c 1674 cx23885_initialize(client);
2a03f034 1675 else if (is_cx231xx(state))
149783b5 1676 cx231xx_initialize(client);
9357b31c
HV		 1677 else
1678 cx25840_initialize(client);
1679 return 0;
1680}
bd985160 1681
aecde8b5 1682static int cx25840_g_chip_ident(struct v4l2_subdev *sd, struct v4l2_dbg_chip_ident *chip)
9357b31c
HV		 1683{
1684 struct cx25840_state *state = to_state(sd);
1685 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160 1686
9357b31c
HV		 1687 return v4l2_chip_ident_i2c_client(client, chip, state->id, state->rev);
1688}
bd985160 1689
9357b31c
HV		 1690static int cx25840_log_status(struct v4l2_subdev *sd)
1691{
1692 struct cx25840_state *state = to_state(sd);
1693 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160 1694
9357b31c 1695 log_video_status(client);
2a03f034 1696 if (!is_cx2583x(state))
9357b31c 1697 log_audio_status(client);
52fd3dda 1698 cx25840_ir_log_status(sd);
e34e658b 1699 v4l2_ctrl_handler_log_status(&state->hdl, sd->name);
3faeeae4 1700 return 0;
bd985160
HV		 1701}
1702
52fd3dda
AW		 1703static int cx23885_irq_handler(struct v4l2_subdev *sd, u32 status,
1704 bool *handled)
1705{
1706 struct cx25840_state *state = to_state(sd);
1707 struct i2c_client *c = v4l2_get_subdevdata(sd);
1708 u8 irq_stat, aud_stat, aud_en, ir_stat, ir_en;
1709 u32 vid_stat, aud_mc_stat;
1710 bool block_handled;
1711 int ret = 0;
1712
1713 irq_stat = cx25840_read(c, CX23885_PIN_CTRL_IRQ_REG);
1714 v4l_dbg(2, cx25840_debug, c, "AV Core IRQ status (entry): %s %s %s\n",
1715 irq_stat & CX23885_PIN_CTRL_IRQ_IR_STAT ? "ir" : " ",
1716 irq_stat & CX23885_PIN_CTRL_IRQ_AUD_STAT ? "aud" : " ",
1717 irq_stat & CX23885_PIN_CTRL_IRQ_VID_STAT ? "vid" : " ");
1718
1719 if ((is_cx23885(state) || is_cx23887(state))) {
1720 ir_stat = cx25840_read(c, CX25840_IR_STATS_REG);
1721 ir_en = cx25840_read(c, CX25840_IR_IRQEN_REG);
1722 v4l_dbg(2, cx25840_debug, c,
1723 "AV Core ir IRQ status: %#04x disables: %#04x\n",
1724 ir_stat, ir_en);
1725 if (irq_stat & CX23885_PIN_CTRL_IRQ_IR_STAT) {
1726 block_handled = false;
1727 ret = cx25840_ir_irq_handler(sd,
1728 status, &block_handled);
1729 if (block_handled)
1730 *handled = true;
1731 }
1732 }
1733
1734 aud_stat = cx25840_read(c, CX25840_AUD_INT_STAT_REG);
1735 aud_en = cx25840_read(c, CX25840_AUD_INT_CTRL_REG);
1736 v4l_dbg(2, cx25840_debug, c,
1737 "AV Core audio IRQ status: %#04x disables: %#04x\n",
1738 aud_stat, aud_en);
1739 aud_mc_stat = cx25840_read4(c, CX23885_AUD_MC_INT_MASK_REG);
1740 v4l_dbg(2, cx25840_debug, c,
1741 "AV Core audio MC IRQ status: %#06x enables: %#06x\n",
1742 aud_mc_stat >> CX23885_AUD_MC_INT_STAT_SHFT,
1743 aud_mc_stat & CX23885_AUD_MC_INT_CTRL_BITS);
1744 if (irq_stat & CX23885_PIN_CTRL_IRQ_AUD_STAT) {
1745 if (aud_stat) {
1746 cx25840_write(c, CX25840_AUD_INT_STAT_REG, aud_stat);
1747 *handled = true;
1748 }
1749 }
1750
1751 vid_stat = cx25840_read4(c, CX25840_VID_INT_STAT_REG);
1752 v4l_dbg(2, cx25840_debug, c,
1753 "AV Core video IRQ status: %#06x disables: %#06x\n",
1754 vid_stat & CX25840_VID_INT_STAT_BITS,
1755 vid_stat >> CX25840_VID_INT_MASK_SHFT);
1756 if (irq_stat & CX23885_PIN_CTRL_IRQ_VID_STAT) {
1757 if (vid_stat & CX25840_VID_INT_STAT_BITS) {
1758 cx25840_write4(c, CX25840_VID_INT_STAT_REG, vid_stat);
1759 *handled = true;
1760 }
1761 }
1762
1763 irq_stat = cx25840_read(c, CX23885_PIN_CTRL_IRQ_REG);
1764 v4l_dbg(2, cx25840_debug, c, "AV Core IRQ status (exit): %s %s %s\n",
1765 irq_stat & CX23885_PIN_CTRL_IRQ_IR_STAT ? "ir" : " ",
1766 irq_stat & CX23885_PIN_CTRL_IRQ_AUD_STAT ? "aud" : " ",
1767 irq_stat & CX23885_PIN_CTRL_IRQ_VID_STAT ? "vid" : " ");
1768
1769 return ret;
1770}
1771
1772static int cx25840_irq_handler(struct v4l2_subdev *sd, u32 status,
1773 bool *handled)
1774{
1775 struct cx25840_state *state = to_state(sd);
1776
1777 *handled = false;
1778
1779 /* Only support the CX2388[578] AV Core for now */
1780 if (is_cx2388x(state))
1781 return cx23885_irq_handler(sd, status, handled);
1782
1783 return -ENODEV;
1784}
1785
9357b31c
HV		 1786/* ----------------------------------------------------------------------- */
1787
e34e658b
HV		 1788static const struct v4l2_ctrl_ops cx25840_ctrl_ops = {
1789 .s_ctrl = cx25840_s_ctrl,
1790};
1791
9357b31c
HV		 1792static const struct v4l2_subdev_core_ops cx25840_core_ops = {
1793 .log_status = cx25840_log_status,
1794 .g_chip_ident = cx25840_g_chip_ident,
e34e658b
HV		 1795 .g_ctrl = v4l2_subdev_g_ctrl,
1796 .s_ctrl = v4l2_subdev_s_ctrl,
1797 .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
1798 .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
1799 .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
1800 .queryctrl = v4l2_subdev_queryctrl,
1801 .querymenu = v4l2_subdev_querymenu,
f41737ec 1802 .s_std = cx25840_s_std,
9357b31c 1803 .reset = cx25840_reset,
cc26b076 1804 .load_fw = cx25840_load_fw,
d06d5777 1805 .s_io_pin_config = common_s_io_pin_config,
9357b31c
HV		 1806#ifdef CONFIG_VIDEO_ADV_DEBUG
1807 .g_register = cx25840_g_register,
1808 .s_register = cx25840_s_register,
1809#endif
52fd3dda 1810 .interrupt_service_routine = cx25840_irq_handler,
9357b31c
HV		 1811};
1812
1813static const struct v4l2_subdev_tuner_ops cx25840_tuner_ops = {
1814 .s_frequency = cx25840_s_frequency,
9357b31c
HV		 1815 .s_radio = cx25840_s_radio,
1816 .g_tuner = cx25840_g_tuner,
1817 .s_tuner = cx25840_s_tuner,
1818};
1819
1820static const struct v4l2_subdev_audio_ops cx25840_audio_ops = {
1821 .s_clock_freq = cx25840_s_clock_freq,
1822 .s_routing = cx25840_s_audio_routing,
3ccc646b 1823 .s_stream = cx25840_s_audio_stream,
9357b31c
HV		 1824};
1825
1826static const struct v4l2_subdev_video_ops cx25840_video_ops = {
1827 .s_routing = cx25840_s_video_routing,
96fd004f 1828 .s_mbus_fmt = cx25840_s_mbus_fmt,
9357b31c
HV		 1829 .s_stream = cx25840_s_stream,
1830};
1831
32cd527f
HV		 1832static const struct v4l2_subdev_vbi_ops cx25840_vbi_ops = {
1833 .decode_vbi_line = cx25840_decode_vbi_line,
5393db43
HV		 1834 .s_raw_fmt = cx25840_s_raw_fmt,
1835 .s_sliced_fmt = cx25840_s_sliced_fmt,
1836 .g_sliced_fmt = cx25840_g_sliced_fmt,
32cd527f
HV		 1837};
1838
9357b31c
HV		 1839static const struct v4l2_subdev_ops cx25840_ops = {
1840 .core = &cx25840_core_ops,
1841 .tuner = &cx25840_tuner_ops,
1842 .audio = &cx25840_audio_ops,
1843 .video = &cx25840_video_ops,
32cd527f 1844 .vbi = &cx25840_vbi_ops,
52fd3dda 1845 .ir = &cx25840_ir_ops,
9357b31c
HV		 1846};
1847
bd985160
HV		 1848/* ----------------------------------------------------------------------- */
1849
c7dd1ecd
AW		 1850static u32 get_cx2388x_ident(struct i2c_client *client)
1851{
1852 u32 ret;
1853
1854 /* Come out of digital power down */
1855 cx25840_write(client, 0x000, 0);
1856
8c2d7821
ST		 1857 /* Detecting whether the part is cx23885/7/8 is more
1858 * difficult than it needs to be. No ID register. Instead we
1859 * probe certain registers indicated in the datasheets to look
1860 * for specific defaults that differ between the silicon designs. */
1861
1862 /* It's either 885/7 if the IR Tx Clk Divider register exists */
c7dd1ecd 1863 if (cx25840_read4(client, 0x204) & 0xffff) {
8c2d7821
ST		 1864 /* CX23885 returns bogus repetitive byte values for the DIF,
1865 * which doesn't exist for it. (Ex. 8a8a8a8a or 31313131) */
1866 ret = cx25840_read4(client, 0x300);
1867 if (((ret & 0xffff0000) >> 16) == (ret & 0xffff)) {
1868 /* No DIF */
1869 ret = V4L2_IDENT_CX23885_AV;
1870 } else {
1871 /* CX23887 has a broken DIF, but the registers
25985edc 1872 * appear valid (but unused), good enough to detect. */
8c2d7821
ST		 1873 ret = V4L2_IDENT_CX23887_AV;
1874 }
c7dd1ecd
AW		 1875 } else if (cx25840_read4(client, 0x300) & 0x0fffffff) {
1876 /* DIF PLL Freq Word reg exists; chip must be a CX23888 */
1877 ret = V4L2_IDENT_CX23888_AV;
1878 } else {
8c2d7821 1879 v4l_err(client, "Unable to detect h/w, assuming cx23887\n");
c7dd1ecd
AW		 1880 ret = V4L2_IDENT_CX23887_AV;
1881 }
1882
1883 /* Back into digital power down */
1884 cx25840_write(client, 0x000, 2);
1885 return ret;
1886}
1887
d2653e92
JD		 1888static int cx25840_probe(struct i2c_client *client,
1889 const struct i2c_device_id *did)
bd985160 1890{
bd985160 1891 struct cx25840_state *state;
9357b31c 1892 struct v4l2_subdev *sd;
e34e658b 1893 int default_volume;
c7dd1ecd 1894 u32 id = V4L2_IDENT_NONE;
bd985160
HV		 1895 u16 device_id;
1896
188f3457
HV		 1897 /* Check if the adapter supports the needed features */
1898 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1899 return -EIO;
1900
21340ae0 1901 v4l_dbg(1, cx25840_debug, client, "detecting cx25840 client on address 0x%x\n", client->addr << 1);
bd985160
HV		 1902
1903 device_id = cx25840_read(client, 0x101) << 8;
1904 device_id |= cx25840_read(client, 0x100);
f234081b 1905 v4l_dbg(1, cx25840_debug, client, "device_id = 0x%04x\n", device_id);
bd985160
HV		 1906
1907 /* The high byte of the device ID should be
e2b8cf4c
HV		 1908 * 0x83 for the cx2583x and 0x84 for the cx2584x */
1909 if ((device_id & 0xff00) == 0x8300) {
1910 id = V4L2_IDENT_CX25836 + ((device_id >> 4) & 0xf) - 6;
c7dd1ecd 1911 } else if ((device_id & 0xff00) == 0x8400) {
e2b8cf4c 1912 id = V4L2_IDENT_CX25840 + ((device_id >> 4) & 0xf);
00ca7324 1913 } else if (device_id == 0x0000) {
c7dd1ecd 1914 id = get_cx2388x_ident(client);
149783b5 1915 } else if ((device_id & 0xfff0) == 0x5A30) {
c7dd1ecd
AW		 1916 /* The CX23100 (0x5A3C = 23100) doesn't have an A/V decoder */
1917 id = V4L2_IDENT_CX2310X_AV;
1918 } else if ((device_id & 0xff) == (device_id >> 8)) {
1919 v4l_err(client,
1920 "likely a confused/unresponsive cx2388[578] A/V decoder"
1921 " found @ 0x%x (%s)\n",
1922 client->addr << 1, client->adapter->name);
1923 v4l_err(client, "A method to reset it from the cx25840 driver"
1924 " software is not known at this time\n");
1925 return -ENODEV;
1926 } else {
b5fc7144 1927 v4l_dbg(1, cx25840_debug, client, "cx25840 not found\n");
188f3457 1928 return -ENODEV;
bd985160
HV		 1929 }
1930
21340ae0 1931 state = kzalloc(sizeof(struct cx25840_state), GFP_KERNEL);
9357b31c 1932 if (state == NULL)
21340ae0 1933 return -ENOMEM;
21340ae0 1934
9357b31c
HV		 1935 sd = &state->sd;
1936 v4l2_i2c_subdev_init(sd, client, &cx25840_ops);
e34e658b 1937
c7dd1ecd
AW		 1938 switch (id) {
1939 case V4L2_IDENT_CX23885_AV:
c7dd1ecd
AW		 1940 v4l_info(client, "cx23885 A/V decoder found @ 0x%x (%s)\n",
1941 client->addr << 1, client->adapter->name);
1942 break;
1943 case V4L2_IDENT_CX23887_AV:
c7dd1ecd
AW		 1944 v4l_info(client, "cx23887 A/V decoder found @ 0x%x (%s)\n",
1945 client->addr << 1, client->adapter->name);
1946 break;
1947 case V4L2_IDENT_CX23888_AV:
c7dd1ecd
AW		 1948 v4l_info(client, "cx23888 A/V decoder found @ 0x%x (%s)\n",
1949 client->addr << 1, client->adapter->name);
1950 break;
1951 case V4L2_IDENT_CX2310X_AV:
c7dd1ecd
AW		 1952 v4l_info(client, "cx%d A/V decoder found @ 0x%x (%s)\n",
1953 device_id, client->addr << 1, client->adapter->name);
1954 break;
1955 case V4L2_IDENT_CX25840:
1956 case V4L2_IDENT_CX25841:
1957 case V4L2_IDENT_CX25842:
1958 case V4L2_IDENT_CX25843:
1959 /* Note: revision '(device_id & 0x0f) == 2' was never built. The
1960 marking skips from 0x1 == 22 to 0x3 == 23. */
1961 v4l_info(client, "cx25%3x-2%x found @ 0x%x (%s)\n",
1962 (device_id & 0xfff0) >> 4,
1963 (device_id & 0x0f) < 3 ? (device_id & 0x0f) + 1
1964 : (device_id & 0x0f),
1965 client->addr << 1, client->adapter->name);
1966 break;
1967 case V4L2_IDENT_CX25836:
1968 case V4L2_IDENT_CX25837:
c7dd1ecd
AW		 1969 default:
1970 v4l_info(client, "cx25%3x-%x found @ 0x%x (%s)\n",
1971 (device_id & 0xfff0) >> 4, device_id & 0x0f,
1972 client->addr << 1, client->adapter->name);
1973 break;
1974 }
bd985160 1975
21340ae0 1976 state->c = client;
a8bbf12a
HV		 1977 state->vid_input = CX25840_COMPOSITE7;
1978 state->aud_input = CX25840_AUDIO8;
3578d3dd 1979 state->audclk_freq = 48000;
8a4b275f 1980 state->audmode = V4L2_TUNER_MODE_LANG1;
3e3bf277 1981 state->vbi_line_offset = 8;
e2b8cf4c 1982 state->id = id;
3434eb7e 1983 state->rev = device_id;
e34e658b
HV		 1984 v4l2_ctrl_handler_init(&state->hdl, 9);
1985 v4l2_ctrl_new_std(&state->hdl, &cx25840_ctrl_ops,
1986 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
1987 v4l2_ctrl_new_std(&state->hdl, &cx25840_ctrl_ops,
1988 V4L2_CID_CONTRAST, 0, 127, 1, 64);
1989 v4l2_ctrl_new_std(&state->hdl, &cx25840_ctrl_ops,
1990 V4L2_CID_SATURATION, 0, 127, 1, 64);
1991 v4l2_ctrl_new_std(&state->hdl, &cx25840_ctrl_ops,
1992 V4L2_CID_HUE, -128, 127, 1, 0);
1993 if (!is_cx2583x(state)) {
f23b7952
AW		 1994 default_volume = cx25840_read(client, 0x8d4);
1995 /*
1996 * Enforce the legacy PVR-350/MSP3400 to PVR-150/CX25843 volume
1997 * scale mapping limits to avoid -ERANGE errors when
1998 * initializing the volume control
1999 */
2000 if (default_volume > 228) {
2001 /* Bottom out at -96 dB, v4l2 vol range 0x2e00-0x2fff */
2002 default_volume = 228;
2003 cx25840_write(client, 0x8d4, 228);
2004 }
2005 else if (default_volume < 20) {
2006 /* Top out at + 8 dB, v4l2 vol range 0xfe00-0xffff */
2007 default_volume = 20;
2008 cx25840_write(client, 0x8d4, 20);
2009 }
2010 default_volume = (((228 - default_volume) >> 1) + 23) << 9;
e34e658b
HV		 2011
2012 state->volume = v4l2_ctrl_new_std(&state->hdl,
2013 &cx25840_audio_ctrl_ops, V4L2_CID_AUDIO_VOLUME,
fc00a1d9 2014 0, 65535, 65535 / 100, default_volume);
e34e658b
HV		 2015 state->mute = v4l2_ctrl_new_std(&state->hdl,
2016 &cx25840_audio_ctrl_ops, V4L2_CID_AUDIO_MUTE,
2017 0, 1, 1, 0);
2018 v4l2_ctrl_new_std(&state->hdl, &cx25840_audio_ctrl_ops,
2019 V4L2_CID_AUDIO_BALANCE,
2020 0, 65535, 65535 / 100, 32768);
2021 v4l2_ctrl_new_std(&state->hdl, &cx25840_audio_ctrl_ops,
2022 V4L2_CID_AUDIO_BASS,
2023 0, 65535, 65535 / 100, 32768);
2024 v4l2_ctrl_new_std(&state->hdl, &cx25840_audio_ctrl_ops,
2025 V4L2_CID_AUDIO_TREBLE,
2026 0, 65535, 65535 / 100, 32768);
2027 }
2028 sd->ctrl_handler = &state->hdl;
2029 if (state->hdl.error) {
2030 int err = state->hdl.error;
2031
2032 v4l2_ctrl_handler_free(&state->hdl);
2033 kfree(state);
2034 return err;
2035 }
1e6406b8
SB		 2036 if (!is_cx2583x(state))
2037 v4l2_ctrl_cluster(2, &state->volume);
e34e658b 2038 v4l2_ctrl_handler_setup(&state->hdl);
f234081b 2039
3c7c9370
HV		 2040 if (client->dev.platform_data) {
2041 struct cx25840_platform_data *pdata = client->dev.platform_data;
2042
2043 state->pvr150_workaround = pdata->pvr150_workaround;
2044 }
2045
52fd3dda 2046 cx25840_ir_probe(sd);
bd985160
HV		 2047 return 0;
2048}
2049
1a39275a 2050static int cx25840_remove(struct i2c_client *client)
bd985160 2051{
9357b31c 2052 struct v4l2_subdev *sd = i2c_get_clientdata(client);
e34e658b 2053 struct cx25840_state *state = to_state(sd);
9357b31c 2054
52fd3dda 2055 cx25840_ir_remove(sd);
9357b31c 2056 v4l2_device_unregister_subdev(sd);
e34e658b
HV		 2057 v4l2_ctrl_handler_free(&state->hdl);
2058 kfree(state);
bd985160
HV		 2059 return 0;
2060}
2061
af294867
JD		 2062static const struct i2c_device_id cx25840_id[] = {
2063 { "cx25840", 0 },
2064 { }
2065};
2066MODULE_DEVICE_TABLE(i2c, cx25840_id);
2067
ad62cdfe
HV		 2068static struct i2c_driver cx25840_driver = {
2069 .driver = {
2070 .owner = THIS_MODULE,
2071 .name = "cx25840",
2072 },
2073 .probe = cx25840_probe,
2074 .remove = cx25840_remove,
2075 .id_table = cx25840_id,
bd985160 2076};
ad62cdfe
HV		 2077
2078static __init int init_cx25840(void)
2079{
2080 return i2c_add_driver(&cx25840_driver);
2081}
2082
2083static __exit void exit_cx25840(void)
2084{
2085 i2c_del_driver(&cx25840_driver);
2086}
2087
2088module_init(init_cx25840);
2089module_exit(exit_cx25840);
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