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V4L/DVB (12345): em28xx: fix audio VIDIOC_S_CTRL adjustments on devices without ac97
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bd985160
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1/* cx25840 - Conexant CX25840 audio/video decoder driver
2 *
3 * Copyright (C) 2004 Ulf Eklund
4 *
5 * Based on the saa7115 driver and on the first verison of Chris Kennedy's
6 * cx25840 driver.
7 *
8 * Changes by Tyler Trafford <tatrafford@comcast.net>
9 * - cleanup/rewrite for V4L2 API (2005)
10 *
11 * VBI support by Hans Verkuil <hverkuil@xs4all.nl>.
12 *
3e3bf277
CN
13 * NTSC sliced VBI support by Christopher Neufeld <television@cneufeld.ca>
14 * with additional fixes by Hans Verkuil <hverkuil@xs4all.nl>.
15 *
6d897616 16 * CX23885 support by Steven Toth <stoth@linuxtv.org>.
f234081b 17 *
bd985160
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18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version 2
21 * of the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
31 */
32
33
34#include <linux/kernel.h>
35#include <linux/module.h>
36#include <linux/slab.h>
37#include <linux/videodev2.h>
38#include <linux/i2c.h>
f61b48f7 39#include <linux/delay.h>
bd985160 40#include <media/v4l2-common.h>
3434eb7e 41#include <media/v4l2-chip-ident.h>
b6198ade 42#include <media/v4l2-i2c-drv.h>
31bc09b5 43#include <media/cx25840.h>
bd985160 44
31bc09b5 45#include "cx25840-core.h"
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HV
46
47MODULE_DESCRIPTION("Conexant CX25840 audio/video decoder driver");
1f4b3365 48MODULE_AUTHOR("Ulf Eklund, Chris Kennedy, Hans Verkuil, Tyler Trafford");
bd985160
HV
49MODULE_LICENSE("GPL");
50
fe0d3dff 51static int cx25840_debug;
bd985160 52
b5fc7144 53module_param_named(debug,cx25840_debug, int, 0644);
bd985160 54
fac9e899 55MODULE_PARM_DESC(debug, "Debugging messages [0=Off (default) 1=On]");
bd985160 56
bd985160
HV
57
58/* ----------------------------------------------------------------------- */
59
60int cx25840_write(struct i2c_client *client, u16 addr, u8 value)
61{
62 u8 buffer[3];
63 buffer[0] = addr >> 8;
64 buffer[1] = addr & 0xff;
65 buffer[2] = value;
66 return i2c_master_send(client, buffer, 3);
67}
68
69int cx25840_write4(struct i2c_client *client, u16 addr, u32 value)
70{
71 u8 buffer[6];
72 buffer[0] = addr >> 8;
73 buffer[1] = addr & 0xff;
4a56eb3f
HV
74 buffer[2] = value & 0xff;
75 buffer[3] = (value >> 8) & 0xff;
76 buffer[4] = (value >> 16) & 0xff;
77 buffer[5] = value >> 24;
bd985160
HV
78 return i2c_master_send(client, buffer, 6);
79}
80
81u8 cx25840_read(struct i2c_client * client, u16 addr)
82{
83 u8 buffer[2];
84 buffer[0] = addr >> 8;
85 buffer[1] = addr & 0xff;
86
87 if (i2c_master_send(client, buffer, 2) < 2)
88 return 0;
89
90 if (i2c_master_recv(client, buffer, 1) < 1)
91 return 0;
92
93 return buffer[0];
94}
95
96u32 cx25840_read4(struct i2c_client * client, u16 addr)
97{
98 u8 buffer[4];
99 buffer[0] = addr >> 8;
100 buffer[1] = addr & 0xff;
101
102 if (i2c_master_send(client, buffer, 2) < 2)
103 return 0;
104
105 if (i2c_master_recv(client, buffer, 4) < 4)
106 return 0;
107
17531c16
HV
108 return (buffer[3] << 24) | (buffer[2] << 16) |
109 (buffer[1] << 8) | buffer[0];
bd985160
HV
110}
111
e2b8cf4c 112int cx25840_and_or(struct i2c_client *client, u16 addr, unsigned and_mask,
bd985160
HV
113 u8 or_value)
114{
115 return cx25840_write(client, addr,
116 (cx25840_read(client, addr) & and_mask) |
117 or_value);
118}
119
120/* ----------------------------------------------------------------------- */
121
a8bbf12a
HV
122static int set_input(struct i2c_client *client, enum cx25840_video_input vid_input,
123 enum cx25840_audio_input aud_input);
bd985160
HV
124
125/* ----------------------------------------------------------------------- */
126
d92c20e0 127static void init_dll1(struct i2c_client *client)
bd985160
HV
128{
129 /* This is the Hauppauge sequence used to
130 * initialize the Delay Lock Loop 1 (ADC DLL). */
131 cx25840_write(client, 0x159, 0x23);
132 cx25840_write(client, 0x15a, 0x87);
133 cx25840_write(client, 0x15b, 0x06);
38051450 134 udelay(10);
bd985160 135 cx25840_write(client, 0x159, 0xe1);
38051450 136 udelay(10);
bd985160
HV
137 cx25840_write(client, 0x15a, 0x86);
138 cx25840_write(client, 0x159, 0xe0);
139 cx25840_write(client, 0x159, 0xe1);
140 cx25840_write(client, 0x15b, 0x10);
141}
142
d92c20e0 143static void init_dll2(struct i2c_client *client)
bd985160
HV
144{
145 /* This is the Hauppauge sequence used to
146 * initialize the Delay Lock Loop 2 (ADC DLL). */
147 cx25840_write(client, 0x15d, 0xe3);
148 cx25840_write(client, 0x15e, 0x86);
149 cx25840_write(client, 0x15f, 0x06);
38051450 150 udelay(10);
bd985160
HV
151 cx25840_write(client, 0x15d, 0xe1);
152 cx25840_write(client, 0x15d, 0xe0);
153 cx25840_write(client, 0x15d, 0xe1);
154}
155
e2b8cf4c
HV
156static void cx25836_initialize(struct i2c_client *client)
157{
158 /* reset configuration is described on page 3-77 of the CX25836 datasheet */
159 /* 2. */
160 cx25840_and_or(client, 0x000, ~0x01, 0x01);
161 cx25840_and_or(client, 0x000, ~0x01, 0x00);
162 /* 3a. */
163 cx25840_and_or(client, 0x15a, ~0x70, 0x00);
164 /* 3b. */
165 cx25840_and_or(client, 0x15b, ~0x1e, 0x06);
166 /* 3c. */
167 cx25840_and_or(client, 0x159, ~0x02, 0x02);
168 /* 3d. */
38051450 169 udelay(10);
e2b8cf4c
HV
170 /* 3e. */
171 cx25840_and_or(client, 0x159, ~0x02, 0x00);
172 /* 3f. */
173 cx25840_and_or(client, 0x159, ~0xc0, 0xc0);
174 /* 3g. */
175 cx25840_and_or(client, 0x159, ~0x01, 0x00);
176 cx25840_and_or(client, 0x159, ~0x01, 0x01);
177 /* 3h. */
178 cx25840_and_or(client, 0x15b, ~0x1e, 0x10);
179}
180
21340ae0
HV
181static void cx25840_work_handler(struct work_struct *work)
182{
183 struct cx25840_state *state = container_of(work, struct cx25840_state, fw_work);
184 cx25840_loadfw(state->c);
185 wake_up(&state->fw_wait);
186}
187
89fc4eb9 188static void cx25840_initialize(struct i2c_client *client)
bd985160 189{
21340ae0 190 DEFINE_WAIT(wait);
9357b31c 191 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
21340ae0 192 struct workqueue_struct *q;
bd985160
HV
193
194 /* datasheet startup in numbered steps, refer to page 3-77 */
195 /* 2. */
196 cx25840_and_or(client, 0x803, ~0x10, 0x00);
197 /* The default of this register should be 4, but I get 0 instead.
198 * Set this register to 4 manually. */
199 cx25840_write(client, 0x000, 0x04);
200 /* 3. */
201 init_dll1(client);
202 init_dll2(client);
203 cx25840_write(client, 0x136, 0x0a);
204 /* 4. */
205 cx25840_write(client, 0x13c, 0x01);
206 cx25840_write(client, 0x13c, 0x00);
207 /* 5. */
21340ae0
HV
208 /* Do the firmware load in a work handler to prevent.
209 Otherwise the kernel is blocked waiting for the
210 bit-banging i2c interface to finish uploading the
211 firmware. */
212 INIT_WORK(&state->fw_work, cx25840_work_handler);
213 init_waitqueue_head(&state->fw_wait);
214 q = create_singlethread_workqueue("cx25840_fw");
215 prepare_to_wait(&state->fw_wait, &wait, TASK_UNINTERRUPTIBLE);
216 queue_work(q, &state->fw_work);
217 schedule();
218 finish_wait(&state->fw_wait, &wait);
219 destroy_workqueue(q);
220
bd985160
HV
221 /* 6. */
222 cx25840_write(client, 0x115, 0x8c);
223 cx25840_write(client, 0x116, 0x07);
224 cx25840_write(client, 0x118, 0x02);
225 /* 7. */
226 cx25840_write(client, 0x4a5, 0x80);
227 cx25840_write(client, 0x4a5, 0x00);
228 cx25840_write(client, 0x402, 0x00);
229 /* 8. */
73dcddc5
HV
230 cx25840_and_or(client, 0x401, ~0x18, 0);
231 cx25840_and_or(client, 0x4a2, ~0x10, 0x10);
232 /* steps 8c and 8d are done in change_input() */
bd985160
HV
233 /* 10. */
234 cx25840_write(client, 0x8d3, 0x1f);
235 cx25840_write(client, 0x8e3, 0x03);
236
cb5aa1c6 237 cx25840_std_setup(client);
bd985160
HV
238
239 /* trial and error says these are needed to get audio */
240 cx25840_write(client, 0x914, 0xa0);
241 cx25840_write(client, 0x918, 0xa0);
242 cx25840_write(client, 0x919, 0x01);
243
244 /* stereo prefered */
245 cx25840_write(client, 0x809, 0x04);
246 /* AC97 shift */
247 cx25840_write(client, 0x8cf, 0x0f);
248
a8bbf12a
HV
249 /* (re)set input */
250 set_input(client, state->vid_input, state->aud_input);
bd985160
HV
251
252 /* start microcontroller */
253 cx25840_and_or(client, 0x803, ~0x10, 0x10);
254}
255
f234081b
ST
256static void cx23885_initialize(struct i2c_client *client)
257{
258 DEFINE_WAIT(wait);
9357b31c 259 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
f234081b
ST
260 struct workqueue_struct *q;
261
262 /* Internal Reset */
263 cx25840_and_or(client, 0x102, ~0x01, 0x01);
264 cx25840_and_or(client, 0x102, ~0x01, 0x00);
265
266 /* Stop microcontroller */
267 cx25840_and_or(client, 0x803, ~0x10, 0x00);
268
269 /* DIF in reset? */
270 cx25840_write(client, 0x398, 0);
271
272 /* Trust the default xtal, no division */
273 /* This changes for the cx23888 products */
274 cx25840_write(client, 0x2, 0x76);
275
276 /* Bring down the regulator for AUX clk */
277 cx25840_write(client, 0x1, 0x40);
278
279 /* Sys PLL frac */
280 cx25840_write4(client, 0x11c, 0x01d1744c);
281
282 /* Sys PLL int */
283 cx25840_write4(client, 0x118, 0x00000416);
284
285 /* Disable DIF bypass */
286 cx25840_write4(client, 0x33c, 0x00000001);
287
288 /* DIF Src phase inc */
289 cx25840_write4(client, 0x340, 0x0df7df83);
290
291 /* Vid PLL frac */
292 cx25840_write4(client, 0x10c, 0x01b6db7b);
293
294 /* Vid PLL int */
295 cx25840_write4(client, 0x108, 0x00000512);
296
297 /* Luma */
298 cx25840_write4(client, 0x414, 0x00107d12);
299
300 /* Chroma */
301 cx25840_write4(client, 0x420, 0x3d008282);
302
303 /* Aux PLL frac */
304 cx25840_write4(client, 0x114, 0x017dbf48);
305
306 /* Aux PLL int */
307 cx25840_write4(client, 0x110, 0x000a030e);
308
309 /* ADC2 input select */
310 cx25840_write(client, 0x102, 0x10);
311
312 /* VIN1 & VIN5 */
313 cx25840_write(client, 0x103, 0x11);
314
315 /* Enable format auto detect */
316 cx25840_write(client, 0x400, 0);
317 /* Fast subchroma lock */
318 /* White crush, Chroma AGC & Chroma Killer enabled */
319 cx25840_write(client, 0x401, 0xe8);
320
321 /* Select AFE clock pad output source */
322 cx25840_write(client, 0x144, 0x05);
323
324 /* Do the firmware load in a work handler to prevent.
325 Otherwise the kernel is blocked waiting for the
326 bit-banging i2c interface to finish uploading the
327 firmware. */
328 INIT_WORK(&state->fw_work, cx25840_work_handler);
329 init_waitqueue_head(&state->fw_wait);
330 q = create_singlethread_workqueue("cx25840_fw");
331 prepare_to_wait(&state->fw_wait, &wait, TASK_UNINTERRUPTIBLE);
332 queue_work(q, &state->fw_work);
333 schedule();
334 finish_wait(&state->fw_wait, &wait);
335 destroy_workqueue(q);
336
cb5aa1c6 337 cx25840_std_setup(client);
f234081b
ST
338
339 /* (re)set input */
340 set_input(client, state->vid_input, state->aud_input);
341
342 /* start microcontroller */
343 cx25840_and_or(client, 0x803, ~0x10, 0x10);
344}
345
bd985160
HV
346/* ----------------------------------------------------------------------- */
347
149783b5
SD
348static void cx231xx_initialize(struct i2c_client *client)
349{
350 DEFINE_WAIT(wait);
351 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
352 struct workqueue_struct *q;
353
354 /* Internal Reset */
355 cx25840_and_or(client, 0x102, ~0x01, 0x01);
356 cx25840_and_or(client, 0x102, ~0x01, 0x00);
357
358 /* Stop microcontroller */
359 cx25840_and_or(client, 0x803, ~0x10, 0x00);
360
361 /* DIF in reset? */
362 cx25840_write(client, 0x398, 0);
363
364 /* Trust the default xtal, no division */
365 /* This changes for the cx23888 products */
366 cx25840_write(client, 0x2, 0x76);
367
368 /* Bring down the regulator for AUX clk */
369 cx25840_write(client, 0x1, 0x40);
370
371 /* Disable DIF bypass */
372 cx25840_write4(client, 0x33c, 0x00000001);
373
374 /* DIF Src phase inc */
375 cx25840_write4(client, 0x340, 0x0df7df83);
376
149783b5
SD
377 /* Luma */
378 cx25840_write4(client, 0x414, 0x00107d12);
379
380 /* Chroma */
381 cx25840_write4(client, 0x420, 0x3d008282);
382
149783b5
SD
383 /* ADC2 input select */
384 cx25840_write(client, 0x102, 0x10);
385
386 /* VIN1 & VIN5 */
387 cx25840_write(client, 0x103, 0x11);
388
389 /* Enable format auto detect */
390 cx25840_write(client, 0x400, 0);
391 /* Fast subchroma lock */
392 /* White crush, Chroma AGC & Chroma Killer enabled */
393 cx25840_write(client, 0x401, 0xe8);
394
149783b5
SD
395 /* Do the firmware load in a work handler to prevent.
396 Otherwise the kernel is blocked waiting for the
397 bit-banging i2c interface to finish uploading the
398 firmware. */
399 INIT_WORK(&state->fw_work, cx25840_work_handler);
400 init_waitqueue_head(&state->fw_wait);
401 q = create_singlethread_workqueue("cx25840_fw");
402 prepare_to_wait(&state->fw_wait, &wait, TASK_UNINTERRUPTIBLE);
403 queue_work(q, &state->fw_work);
404 schedule();
405 finish_wait(&state->fw_wait, &wait);
406 destroy_workqueue(q);
407
408 cx25840_std_setup(client);
409
410 /* (re)set input */
411 set_input(client, state->vid_input, state->aud_input);
412
413 /* start microcontroller */
414 cx25840_and_or(client, 0x803, ~0x10, 0x10);
415}
416
417/* ----------------------------------------------------------------------- */
418
cb5aa1c6
HV
419void cx25840_std_setup(struct i2c_client *client)
420{
9357b31c 421 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
cb5aa1c6
HV
422 v4l2_std_id std = state->std;
423 int hblank, hactive, burst, vblank, vactive, sc;
424 int vblank656, src_decimation;
425 int luma_lpf, uv_lpf, comb;
426 u32 pll_int, pll_frac, pll_post;
427
428 /* datasheet startup, step 8d */
429 if (std & ~V4L2_STD_NTSC)
430 cx25840_write(client, 0x49f, 0x11);
431 else
432 cx25840_write(client, 0x49f, 0x14);
433
434 if (std & V4L2_STD_625_50) {
435 hblank = 132;
436 hactive = 720;
437 burst = 93;
438 vblank = 36;
439 vactive = 580;
440 vblank656 = 40;
441 src_decimation = 0x21f;
442 luma_lpf = 2;
443
444 if (std & V4L2_STD_SECAM) {
445 uv_lpf = 0;
446 comb = 0;
447 sc = 0x0a425f;
448 } else if (std == V4L2_STD_PAL_Nc) {
449 uv_lpf = 1;
450 comb = 0x20;
451 sc = 556453;
452 } else {
453 uv_lpf = 1;
454 comb = 0x20;
455 sc = 688739;
456 }
457 } else {
458 hactive = 720;
459 hblank = 122;
460 vactive = 487;
461 luma_lpf = 1;
462 uv_lpf = 1;
463
464 src_decimation = 0x21f;
465 if (std == V4L2_STD_PAL_60) {
466 vblank = 26;
467 vblank656 = 26;
468 burst = 0x5b;
469 luma_lpf = 2;
470 comb = 0x20;
471 sc = 688739;
472 } else if (std == V4L2_STD_PAL_M) {
473 vblank = 20;
474 vblank656 = 24;
475 burst = 0x61;
476 comb = 0x20;
477 sc = 555452;
478 } else {
479 vblank = 26;
480 vblank656 = 26;
481 burst = 0x5b;
482 comb = 0x66;
483 sc = 556063;
484 }
485 }
486
487 /* DEBUG: Displays configured PLL frequency */
95b14fb2
MCC
488 if (!state->is_cx231xx) {
489 pll_int = cx25840_read(client, 0x108);
490 pll_frac = cx25840_read4(client, 0x10c) & 0x1ffffff;
491 pll_post = cx25840_read(client, 0x109);
cb5aa1c6 492 v4l_dbg(1, cx25840_debug, client,
95b14fb2
MCC
493 "PLL regs = int: %u, frac: %u, post: %u\n",
494 pll_int, pll_frac, pll_post);
495
496 if (pll_post) {
497 int fin, fsc;
498 int pll = (28636363L * ((((u64)pll_int) << 25L) + pll_frac)) >> 25L;
499
500 pll /= pll_post;
501 v4l_dbg(1, cx25840_debug, client, "PLL = %d.%06d MHz\n",
502 pll / 1000000, pll % 1000000);
503 v4l_dbg(1, cx25840_debug, client, "PLL/8 = %d.%06d MHz\n",
504 pll / 8000000, (pll / 8) % 1000000);
505
506 fin = ((u64)src_decimation * pll) >> 12;
507 v4l_dbg(1, cx25840_debug, client,
508 "ADC Sampling freq = %d.%06d MHz\n",
509 fin / 1000000, fin % 1000000);
510
511 fsc = (((u64)sc) * pll) >> 24L;
512 v4l_dbg(1, cx25840_debug, client,
513 "Chroma sub-carrier freq = %d.%06d MHz\n",
514 fsc / 1000000, fsc % 1000000);
515
516 v4l_dbg(1, cx25840_debug, client, "hblank %i, hactive %i, "
517 "vblank %i, vactive %i, vblank656 %i, src_dec %i, "
518 "burst 0x%02x, luma_lpf %i, uv_lpf %i, comb 0x%02x, "
519 "sc 0x%06x\n",
520 hblank, hactive, vblank, vactive, vblank656,
521 src_decimation, burst, luma_lpf, uv_lpf, comb, sc);
522 }
cb5aa1c6
HV
523 }
524
525 /* Sets horizontal blanking delay and active lines */
526 cx25840_write(client, 0x470, hblank);
527 cx25840_write(client, 0x471,
528 0xff & (((hblank >> 8) & 0x3) | (hactive << 4)));
529 cx25840_write(client, 0x472, hactive >> 4);
530
531 /* Sets burst gate delay */
532 cx25840_write(client, 0x473, burst);
533
534 /* Sets vertical blanking delay and active duration */
535 cx25840_write(client, 0x474, vblank);
536 cx25840_write(client, 0x475,
537 0xff & (((vblank >> 8) & 0x3) | (vactive << 4)));
538 cx25840_write(client, 0x476, vactive >> 4);
539 cx25840_write(client, 0x477, vblank656);
540
541 /* Sets src decimation rate */
542 cx25840_write(client, 0x478, 0xff & src_decimation);
543 cx25840_write(client, 0x479, 0xff & (src_decimation >> 8));
544
545 /* Sets Luma and UV Low pass filters */
546 cx25840_write(client, 0x47a, luma_lpf << 6 | ((uv_lpf << 4) & 0x30));
547
548 /* Enables comb filters */
549 cx25840_write(client, 0x47b, comb);
550
551 /* Sets SC Step*/
552 cx25840_write(client, 0x47c, sc);
553 cx25840_write(client, 0x47d, 0xff & sc >> 8);
554 cx25840_write(client, 0x47e, 0xff & sc >> 16);
555
556 /* Sets VBI parameters */
557 if (std & V4L2_STD_625_50) {
558 cx25840_write(client, 0x47f, 0x01);
559 state->vbi_line_offset = 5;
560 } else {
561 cx25840_write(client, 0x47f, 0x00);
562 state->vbi_line_offset = 8;
563 }
564}
565
566/* ----------------------------------------------------------------------- */
567
bd985160
HV
568static void input_change(struct i2c_client *client)
569{
9357b31c 570 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
081b496a 571 v4l2_std_id std = state->std;
bd985160 572
73dcddc5
HV
573 /* Follow step 8c and 8d of section 3.16 in the cx25840 datasheet */
574 if (std & V4L2_STD_SECAM) {
575 cx25840_write(client, 0x402, 0);
576 }
577 else {
578 cx25840_write(client, 0x402, 0x04);
579 cx25840_write(client, 0x49f, (std & V4L2_STD_NTSC) ? 0x14 : 0x11);
580 }
581 cx25840_and_or(client, 0x401, ~0x60, 0);
582 cx25840_and_or(client, 0x401, ~0x60, 0x60);
82677618 583 cx25840_and_or(client, 0x810, ~0x01, 1);
73dcddc5 584
39c4ad6a
HV
585 if (state->radio) {
586 cx25840_write(client, 0x808, 0xf9);
587 cx25840_write(client, 0x80b, 0x00);
588 }
589 else if (std & V4L2_STD_525_60) {
d97a11e0
HV
590 /* Certain Hauppauge PVR150 models have a hardware bug
591 that causes audio to drop out. For these models the
592 audio standard must be set explicitly.
593 To be precise: it affects cards with tuner models
594 85, 99 and 112 (model numbers from tveeprom). */
595 int hw_fix = state->pvr150_workaround;
596
597 if (std == V4L2_STD_NTSC_M_JP) {
f95006f8 598 /* Japan uses EIAJ audio standard */
d97a11e0
HV
599 cx25840_write(client, 0x808, hw_fix ? 0x2f : 0xf7);
600 } else if (std == V4L2_STD_NTSC_M_KR) {
601 /* South Korea uses A2 audio standard */
602 cx25840_write(client, 0x808, hw_fix ? 0x3f : 0xf8);
f95006f8
HV
603 } else {
604 /* Others use the BTSC audio standard */
d97a11e0 605 cx25840_write(client, 0x808, hw_fix ? 0x1f : 0xf6);
f95006f8 606 }
bd985160 607 cx25840_write(client, 0x80b, 0x00);
839e4a4a
MCC
608 } else if (std & V4L2_STD_PAL) {
609 /* Follow tuner change procedure for PAL */
610 cx25840_write(client, 0x808, 0xff);
611 cx25840_write(client, 0x80b, 0x10);
612 } else if (std & V4L2_STD_SECAM) {
613 /* Select autodetect for SECAM */
614 cx25840_write(client, 0x808, 0xff);
615 cx25840_write(client, 0x80b, 0x10);
bd985160
HV
616 }
617
82677618 618 cx25840_and_or(client, 0x810, ~0x01, 0);
bd985160
HV
619}
620
a8bbf12a
HV
621static int set_input(struct i2c_client *client, enum cx25840_video_input vid_input,
622 enum cx25840_audio_input aud_input)
bd985160 623{
9357b31c 624 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
a8bbf12a
HV
625 u8 is_composite = (vid_input >= CX25840_COMPOSITE1 &&
626 vid_input <= CX25840_COMPOSITE8);
627 u8 reg;
bd985160 628
f234081b
ST
629 v4l_dbg(1, cx25840_debug, client,
630 "decoder set video input %d, audio input %d\n",
631 vid_input, aud_input);
bd985160 632
f234081b
ST
633 if (vid_input >= CX25840_VIN1_CH1) {
634 v4l_dbg(1, cx25840_debug, client, "vid_input 0x%x\n",
635 vid_input);
636 reg = vid_input & 0xff;
637 if ((vid_input & CX25840_SVIDEO_ON) == CX25840_SVIDEO_ON)
638 is_composite = 0;
639 else
640 is_composite = 1;
641
642 v4l_dbg(1, cx25840_debug, client, "mux cfg 0x%x comp=%d\n",
643 reg, is_composite);
644 } else
a8bbf12a
HV
645 if (is_composite) {
646 reg = 0xf0 + (vid_input - CX25840_COMPOSITE1);
647 } else {
648 int luma = vid_input & 0xf0;
649 int chroma = vid_input & 0xf00;
bd985160 650
a8bbf12a 651 if ((vid_input & ~0xff0) ||
45270a15 652 luma < CX25840_SVIDEO_LUMA1 || luma > CX25840_SVIDEO_LUMA8 ||
a8bbf12a 653 chroma < CX25840_SVIDEO_CHROMA4 || chroma > CX25840_SVIDEO_CHROMA8) {
f234081b
ST
654 v4l_err(client, "0x%04x is not a valid video input!\n",
655 vid_input);
a8bbf12a 656 return -EINVAL;
bd985160 657 }
a8bbf12a
HV
658 reg = 0xf0 + ((luma - CX25840_SVIDEO_LUMA1) >> 4);
659 if (chroma >= CX25840_SVIDEO_CHROMA7) {
660 reg &= 0x3f;
661 reg |= (chroma - CX25840_SVIDEO_CHROMA7) >> 2;
bd985160 662 } else {
a8bbf12a
HV
663 reg &= 0xcf;
664 reg |= (chroma - CX25840_SVIDEO_CHROMA4) >> 4;
bd985160 665 }
a8bbf12a 666 }
bd985160 667
f234081b
ST
668 /* The caller has previously prepared the correct routing
669 * configuration in reg (for the cx23885) so we have no
670 * need to attempt to flip bits for earlier av decoders.
671 */
149783b5 672 if (!state->is_cx23885 && !state->is_cx231xx) {
f234081b
ST
673 switch (aud_input) {
674 case CX25840_AUDIO_SERIAL:
675 /* do nothing, use serial audio input */
676 break;
677 case CX25840_AUDIO4: reg &= ~0x30; break;
678 case CX25840_AUDIO5: reg &= ~0x30; reg |= 0x10; break;
679 case CX25840_AUDIO6: reg &= ~0x30; reg |= 0x20; break;
680 case CX25840_AUDIO7: reg &= ~0xc0; break;
681 case CX25840_AUDIO8: reg &= ~0xc0; reg |= 0x40; break;
bd985160 682
f234081b
ST
683 default:
684 v4l_err(client, "0x%04x is not a valid audio input!\n",
685 aud_input);
686 return -EINVAL;
687 }
bd985160
HV
688 }
689
a8bbf12a 690 cx25840_write(client, 0x103, reg);
f234081b 691
a8bbf12a
HV
692 /* Set INPUT_MODE to Composite (0) or S-Video (1) */
693 cx25840_and_or(client, 0x401, ~0x6, is_composite ? 0 : 0x02);
f234081b 694
149783b5 695 if (!state->is_cx23885 && !state->is_cx231xx) {
f234081b
ST
696 /* Set CH_SEL_ADC2 to 1 if input comes from CH3 */
697 cx25840_and_or(client, 0x102, ~0x2, (reg & 0x80) == 0 ? 2 : 0);
698 /* Set DUAL_MODE_ADC2 to 1 if input comes from both CH2&CH3 */
699 if ((reg & 0xc0) != 0xc0 && (reg & 0x30) != 0x30)
700 cx25840_and_or(client, 0x102, ~0x4, 4);
701 else
702 cx25840_and_or(client, 0x102, ~0x4, 0);
703 } else {
704 if (is_composite)
705 /* ADC2 input select channel 2 */
706 cx25840_and_or(client, 0x102, ~0x2, 0);
707 else
708 /* ADC2 input select channel 3 */
709 cx25840_and_or(client, 0x102, ~0x2, 2);
710 }
a8bbf12a
HV
711
712 state->vid_input = vid_input;
713 state->aud_input = aud_input;
e2b8cf4c
HV
714 if (!state->is_cx25836) {
715 cx25840_audio_set_path(client);
716 input_change(client);
717 }
f234081b
ST
718
719 if (state->is_cx23885) {
720 /* Audio channel 1 src : Parallel 1 */
721 cx25840_write(client, 0x124, 0x03);
722
723 /* Select AFE clock pad output source */
724 cx25840_write(client, 0x144, 0x05);
725
726 /* I2S_IN_CTL: I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1 */
727 cx25840_write(client, 0x914, 0xa0);
728
149783b5
SD
729 /* I2S_OUT_CTL:
730 * I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1
731 * I2S_OUT_MASTER_MODE = Master
732 */
733 cx25840_write(client, 0x918, 0xa0);
734 cx25840_write(client, 0x919, 0x01);
735 } else if (state->is_cx231xx) {
736 /* Audio channel 1 src : Parallel 1 */
737 cx25840_write(client, 0x124, 0x03);
738
739 /* I2S_IN_CTL: I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1 */
740 cx25840_write(client, 0x914, 0xa0);
741
f234081b
ST
742 /* I2S_OUT_CTL:
743 * I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1
744 * I2S_OUT_MASTER_MODE = Master
745 */
746 cx25840_write(client, 0x918, 0xa0);
747 cx25840_write(client, 0x919, 0x01);
748 }
749
bd985160
HV
750 return 0;
751}
752
753/* ----------------------------------------------------------------------- */
754
081b496a 755static int set_v4lstd(struct i2c_client *client)
bd985160 756{
9357b31c 757 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
081b496a
HV
758 u8 fmt = 0; /* zero is autodetect */
759 u8 pal_m = 0;
468a0a54
MCC
760
761 /* First tests should be against specific std */
081b496a
HV
762 if (state->std == V4L2_STD_NTSC_M_JP) {
763 fmt = 0x2;
764 } else if (state->std == V4L2_STD_NTSC_443) {
765 fmt = 0x3;
766 } else if (state->std == V4L2_STD_PAL_M) {
767 pal_m = 1;
768 fmt = 0x5;
769 } else if (state->std == V4L2_STD_PAL_N) {
770 fmt = 0x6;
771 } else if (state->std == V4L2_STD_PAL_Nc) {
772 fmt = 0x7;
773 } else if (state->std == V4L2_STD_PAL_60) {
774 fmt = 0x8;
468a0a54
MCC
775 } else {
776 /* Then, test against generic ones */
081b496a
HV
777 if (state->std & V4L2_STD_NTSC)
778 fmt = 0x1;
779 else if (state->std & V4L2_STD_PAL)
780 fmt = 0x4;
781 else if (state->std & V4L2_STD_SECAM)
782 fmt = 0xc;
bd985160
HV
783 }
784
839e4a4a
MCC
785 v4l_dbg(1, cx25840_debug, client, "changing video std to fmt %i\n",fmt);
786
73dcddc5
HV
787 /* Follow step 9 of section 3.16 in the cx25840 datasheet.
788 Without this PAL may display a vertical ghosting effect.
789 This happens for example with the Yuan MPC622. */
790 if (fmt >= 4 && fmt < 8) {
791 /* Set format to NTSC-M */
792 cx25840_and_or(client, 0x400, ~0xf, 1);
793 /* Turn off LCOMB */
794 cx25840_and_or(client, 0x47b, ~6, 0);
795 }
bd985160 796 cx25840_and_or(client, 0x400, ~0xf, fmt);
081b496a 797 cx25840_and_or(client, 0x403, ~0x3, pal_m);
cb5aa1c6 798 cx25840_std_setup(client);
081b496a
HV
799 if (!state->is_cx25836)
800 input_change(client);
bd985160
HV
801 return 0;
802}
803
bd985160
HV
804/* ----------------------------------------------------------------------- */
805
9357b31c 806static int cx25840_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
bd985160 807{
95b14fb2 808 struct cx25840_state *state = to_state(sd);
9357b31c 809 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160
HV
810
811 switch (ctrl->id) {
a8bbf12a
HV
812 case CX25840_CID_ENABLE_PVR150_WORKAROUND:
813 state->pvr150_workaround = ctrl->value;
814 set_input(client, state->vid_input, state->aud_input);
bd985160
HV
815 break;
816
817 case V4L2_CID_BRIGHTNESS:
818 if (ctrl->value < 0 || ctrl->value > 255) {
fac9e899 819 v4l_err(client, "invalid brightness setting %d\n",
bd985160
HV
820 ctrl->value);
821 return -ERANGE;
822 }
823
824 cx25840_write(client, 0x414, ctrl->value - 128);
825 break;
826
827 case V4L2_CID_CONTRAST:
828 if (ctrl->value < 0 || ctrl->value > 127) {
fac9e899 829 v4l_err(client, "invalid contrast setting %d\n",
bd985160
HV
830 ctrl->value);
831 return -ERANGE;
832 }
833
834 cx25840_write(client, 0x415, ctrl->value << 1);
835 break;
836
837 case V4L2_CID_SATURATION:
838 if (ctrl->value < 0 || ctrl->value > 127) {
fac9e899 839 v4l_err(client, "invalid saturation setting %d\n",
bd985160
HV
840 ctrl->value);
841 return -ERANGE;
842 }
843
844 cx25840_write(client, 0x420, ctrl->value << 1);
845 cx25840_write(client, 0x421, ctrl->value << 1);
846 break;
847
848 case V4L2_CID_HUE:
de6476f5 849 if (ctrl->value < -128 || ctrl->value > 127) {
fac9e899 850 v4l_err(client, "invalid hue setting %d\n", ctrl->value);
bd985160
HV
851 return -ERANGE;
852 }
853
854 cx25840_write(client, 0x422, ctrl->value);
855 break;
856
857 case V4L2_CID_AUDIO_VOLUME:
858 case V4L2_CID_AUDIO_BASS:
859 case V4L2_CID_AUDIO_TREBLE:
860 case V4L2_CID_AUDIO_BALANCE:
861 case V4L2_CID_AUDIO_MUTE:
e2b8cf4c
HV
862 if (state->is_cx25836)
863 return -EINVAL;
df1d5ed8 864 return cx25840_audio_s_ctrl(sd, ctrl);
3faeeae4
HV
865
866 default:
867 return -EINVAL;
bd985160
HV
868 }
869
870 return 0;
871}
872
9357b31c 873static int cx25840_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
bd985160 874{
95b14fb2 875 struct cx25840_state *state = to_state(sd);
9357b31c 876 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160
HV
877
878 switch (ctrl->id) {
a8bbf12a
HV
879 case CX25840_CID_ENABLE_PVR150_WORKAROUND:
880 ctrl->value = state->pvr150_workaround;
bd985160
HV
881 break;
882 case V4L2_CID_BRIGHTNESS:
0de71224 883 ctrl->value = (s8)cx25840_read(client, 0x414) + 128;
bd985160
HV
884 break;
885 case V4L2_CID_CONTRAST:
886 ctrl->value = cx25840_read(client, 0x415) >> 1;
887 break;
888 case V4L2_CID_SATURATION:
889 ctrl->value = cx25840_read(client, 0x420) >> 1;
890 break;
891 case V4L2_CID_HUE:
c5099a64 892 ctrl->value = (s8)cx25840_read(client, 0x422);
bd985160
HV
893 break;
894 case V4L2_CID_AUDIO_VOLUME:
895 case V4L2_CID_AUDIO_BASS:
896 case V4L2_CID_AUDIO_TREBLE:
897 case V4L2_CID_AUDIO_BALANCE:
898 case V4L2_CID_AUDIO_MUTE:
e2b8cf4c
HV
899 if (state->is_cx25836)
900 return -EINVAL;
df1d5ed8 901 return cx25840_audio_g_ctrl(sd, ctrl);
bd985160
HV
902 default:
903 return -EINVAL;
904 }
905
906 return 0;
907}
908
909/* ----------------------------------------------------------------------- */
910
9357b31c 911static int cx25840_g_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt)
bd985160
HV
912{
913 switch (fmt->type) {
914 case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
df1d5ed8 915 return cx25840_vbi_g_fmt(sd, fmt);
bd985160
HV
916 default:
917 return -EINVAL;
918 }
bd985160
HV
919 return 0;
920}
921
9357b31c 922static int cx25840_s_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt)
bd985160 923{
9357b31c
HV
924 struct cx25840_state *state = to_state(sd);
925 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160
HV
926 struct v4l2_pix_format *pix;
927 int HSC, VSC, Vsrc, Hsrc, filter, Vlines;
081b496a 928 int is_50Hz = !(state->std & V4L2_STD_525_60);
bd985160
HV
929
930 switch (fmt->type) {
931 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
932 pix = &(fmt->fmt.pix);
933
934 Vsrc = (cx25840_read(client, 0x476) & 0x3f) << 4;
935 Vsrc |= (cx25840_read(client, 0x475) & 0xf0) >> 4;
936
937 Hsrc = (cx25840_read(client, 0x472) & 0x3f) << 4;
938 Hsrc |= (cx25840_read(client, 0x471) & 0xf0) >> 4;
939
ba70d59b 940 Vlines = pix->height + (is_50Hz ? 4 : 7);
bd985160
HV
941
942 if ((pix->width * 16 < Hsrc) || (Hsrc < pix->width) ||
943 (Vlines * 8 < Vsrc) || (Vsrc < Vlines)) {
fac9e899 944 v4l_err(client, "%dx%d is not a valid size!\n",
bd985160
HV
945 pix->width, pix->height);
946 return -ERANGE;
947 }
948
949 HSC = (Hsrc * (1 << 20)) / pix->width - (1 << 20);
950 VSC = (1 << 16) - (Vsrc * (1 << 9) / Vlines - (1 << 9));
951 VSC &= 0x1fff;
952
953 if (pix->width >= 385)
954 filter = 0;
955 else if (pix->width > 192)
956 filter = 1;
957 else if (pix->width > 96)
958 filter = 2;
959 else
960 filter = 3;
961
b5fc7144 962 v4l_dbg(1, cx25840_debug, client, "decoder set size %dx%d -> scale %ux%u\n",
bd985160
HV
963 pix->width, pix->height, HSC, VSC);
964
965 /* HSCALE=HSC */
966 cx25840_write(client, 0x418, HSC & 0xff);
967 cx25840_write(client, 0x419, (HSC >> 8) & 0xff);
968 cx25840_write(client, 0x41a, HSC >> 16);
969 /* VSCALE=VSC */
970 cx25840_write(client, 0x41c, VSC & 0xff);
971 cx25840_write(client, 0x41d, VSC >> 8);
972 /* VS_INTRLACE=1 VFILT=filter */
973 cx25840_write(client, 0x41e, 0x8 | filter);
974 break;
975
976 case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
df1d5ed8 977 return cx25840_vbi_s_fmt(sd, fmt);
bd985160
HV
978
979 case V4L2_BUF_TYPE_VBI_CAPTURE:
df1d5ed8 980 return cx25840_vbi_s_fmt(sd, fmt);
bd985160
HV
981
982 default:
983 return -EINVAL;
984 }
985
986 return 0;
987}
988
989/* ----------------------------------------------------------------------- */
990
1a39275a
HV
991static void log_video_status(struct i2c_client *client)
992{
993 static const char *const fmt_strs[] = {
994 "0x0",
995 "NTSC-M", "NTSC-J", "NTSC-4.43",
996 "PAL-BDGHI", "PAL-M", "PAL-N", "PAL-Nc", "PAL-60",
997 "0x9", "0xA", "0xB",
998 "SECAM",
999 "0xD", "0xE", "0xF"
1000 };
1001
9357b31c 1002 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
1a39275a
HV
1003 u8 vidfmt_sel = cx25840_read(client, 0x400) & 0xf;
1004 u8 gen_stat1 = cx25840_read(client, 0x40d);
1005 u8 gen_stat2 = cx25840_read(client, 0x40e);
1006 int vid_input = state->vid_input;
1007
1008 v4l_info(client, "Video signal: %spresent\n",
1009 (gen_stat2 & 0x20) ? "" : "not ");
1010 v4l_info(client, "Detected format: %s\n",
1011 fmt_strs[gen_stat1 & 0xf]);
1012
1013 v4l_info(client, "Specified standard: %s\n",
1014 vidfmt_sel ? fmt_strs[vidfmt_sel] : "automatic detection");
1015
1016 if (vid_input >= CX25840_COMPOSITE1 &&
1017 vid_input <= CX25840_COMPOSITE8) {
1018 v4l_info(client, "Specified video input: Composite %d\n",
1019 vid_input - CX25840_COMPOSITE1 + 1);
1020 } else {
1021 v4l_info(client, "Specified video input: S-Video (Luma In%d, Chroma In%d)\n",
1022 (vid_input & 0xf0) >> 4, (vid_input & 0xf00) >> 8);
1023 }
1024
1025 v4l_info(client, "Specified audioclock freq: %d Hz\n", state->audclk_freq);
1026}
1027
1028/* ----------------------------------------------------------------------- */
1029
1030static void log_audio_status(struct i2c_client *client)
1031{
9357b31c 1032 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
1a39275a
HV
1033 u8 download_ctl = cx25840_read(client, 0x803);
1034 u8 mod_det_stat0 = cx25840_read(client, 0x804);
1035 u8 mod_det_stat1 = cx25840_read(client, 0x805);
1036 u8 audio_config = cx25840_read(client, 0x808);
1037 u8 pref_mode = cx25840_read(client, 0x809);
1038 u8 afc0 = cx25840_read(client, 0x80b);
1039 u8 mute_ctl = cx25840_read(client, 0x8d3);
1040 int aud_input = state->aud_input;
1041 char *p;
1042
1043 switch (mod_det_stat0) {
1044 case 0x00: p = "mono"; break;
1045 case 0x01: p = "stereo"; break;
1046 case 0x02: p = "dual"; break;
1047 case 0x04: p = "tri"; break;
1048 case 0x10: p = "mono with SAP"; break;
1049 case 0x11: p = "stereo with SAP"; break;
1050 case 0x12: p = "dual with SAP"; break;
1051 case 0x14: p = "tri with SAP"; break;
1052 case 0xfe: p = "forced mode"; break;
1053 default: p = "not defined";
1054 }
1055 v4l_info(client, "Detected audio mode: %s\n", p);
1056
1057 switch (mod_det_stat1) {
1058 case 0x00: p = "not defined"; break;
1059 case 0x01: p = "EIAJ"; break;
1060 case 0x02: p = "A2-M"; break;
1061 case 0x03: p = "A2-BG"; break;
1062 case 0x04: p = "A2-DK1"; break;
1063 case 0x05: p = "A2-DK2"; break;
1064 case 0x06: p = "A2-DK3"; break;
1065 case 0x07: p = "A1 (6.0 MHz FM Mono)"; break;
1066 case 0x08: p = "AM-L"; break;
1067 case 0x09: p = "NICAM-BG"; break;
1068 case 0x0a: p = "NICAM-DK"; break;
1069 case 0x0b: p = "NICAM-I"; break;
1070 case 0x0c: p = "NICAM-L"; break;
1071 case 0x0d: p = "BTSC/EIAJ/A2-M Mono (4.5 MHz FMMono)"; break;
1072 case 0x0e: p = "IF FM Radio"; break;
1073 case 0x0f: p = "BTSC"; break;
1074 case 0x10: p = "high-deviation FM"; break;
1075 case 0x11: p = "very high-deviation FM"; break;
1076 case 0xfd: p = "unknown audio standard"; break;
1077 case 0xfe: p = "forced audio standard"; break;
1078 case 0xff: p = "no detected audio standard"; break;
1079 default: p = "not defined";
1080 }
1081 v4l_info(client, "Detected audio standard: %s\n", p);
1082 v4l_info(client, "Audio muted: %s\n",
1083 (state->unmute_volume >= 0) ? "yes" : "no");
1084 v4l_info(client, "Audio microcontroller: %s\n",
1085 (download_ctl & 0x10) ?
1086 ((mute_ctl & 0x2) ? "detecting" : "running") : "stopped");
1087
1088 switch (audio_config >> 4) {
1089 case 0x00: p = "undefined"; break;
1090 case 0x01: p = "BTSC"; break;
1091 case 0x02: p = "EIAJ"; break;
1092 case 0x03: p = "A2-M"; break;
1093 case 0x04: p = "A2-BG"; break;
1094 case 0x05: p = "A2-DK1"; break;
1095 case 0x06: p = "A2-DK2"; break;
1096 case 0x07: p = "A2-DK3"; break;
1097 case 0x08: p = "A1 (6.0 MHz FM Mono)"; break;
1098 case 0x09: p = "AM-L"; break;
1099 case 0x0a: p = "NICAM-BG"; break;
1100 case 0x0b: p = "NICAM-DK"; break;
1101 case 0x0c: p = "NICAM-I"; break;
1102 case 0x0d: p = "NICAM-L"; break;
1103 case 0x0e: p = "FM radio"; break;
1104 case 0x0f: p = "automatic detection"; break;
1105 default: p = "undefined";
1106 }
1107 v4l_info(client, "Configured audio standard: %s\n", p);
1108
1109 if ((audio_config >> 4) < 0xF) {
1110 switch (audio_config & 0xF) {
1111 case 0x00: p = "MONO1 (LANGUAGE A/Mono L+R channel for BTSC, EIAJ, A2)"; break;
1112 case 0x01: p = "MONO2 (LANGUAGE B)"; break;
1113 case 0x02: p = "MONO3 (STEREO forced MONO)"; break;
1114 case 0x03: p = "MONO4 (NICAM ANALOG-Language C/Analog Fallback)"; break;
1115 case 0x04: p = "STEREO"; break;
1116 case 0x05: p = "DUAL1 (AB)"; break;
1117 case 0x06: p = "DUAL2 (AC) (FM)"; break;
1118 case 0x07: p = "DUAL3 (BC) (FM)"; break;
1119 case 0x08: p = "DUAL4 (AC) (AM)"; break;
1120 case 0x09: p = "DUAL5 (BC) (AM)"; break;
1121 case 0x0a: p = "SAP"; break;
1122 default: p = "undefined";
1123 }
1124 v4l_info(client, "Configured audio mode: %s\n", p);
1125 } else {
1126 switch (audio_config & 0xF) {
1127 case 0x00: p = "BG"; break;
1128 case 0x01: p = "DK1"; break;
1129 case 0x02: p = "DK2"; break;
1130 case 0x03: p = "DK3"; break;
1131 case 0x04: p = "I"; break;
1132 case 0x05: p = "L"; break;
1133 case 0x06: p = "BTSC"; break;
1134 case 0x07: p = "EIAJ"; break;
1135 case 0x08: p = "A2-M"; break;
1136 case 0x09: p = "FM Radio"; break;
1137 case 0x0f: p = "automatic standard and mode detection"; break;
1138 default: p = "undefined";
1139 }
1140 v4l_info(client, "Configured audio system: %s\n", p);
1141 }
1142
1143 if (aud_input) {
1144 v4l_info(client, "Specified audio input: Tuner (In%d)\n", aud_input);
1145 } else {
1146 v4l_info(client, "Specified audio input: External\n");
1147 }
1148
1149 switch (pref_mode & 0xf) {
1150 case 0: p = "mono/language A"; break;
1151 case 1: p = "language B"; break;
1152 case 2: p = "language C"; break;
1153 case 3: p = "analog fallback"; break;
1154 case 4: p = "stereo"; break;
1155 case 5: p = "language AC"; break;
1156 case 6: p = "language BC"; break;
1157 case 7: p = "language AB"; break;
1158 default: p = "undefined";
1159 }
1160 v4l_info(client, "Preferred audio mode: %s\n", p);
1161
1162 if ((audio_config & 0xf) == 0xf) {
1163 switch ((afc0 >> 3) & 0x3) {
1164 case 0: p = "system DK"; break;
1165 case 1: p = "system L"; break;
1166 case 2: p = "autodetect"; break;
1167 default: p = "undefined";
1168 }
1169 v4l_info(client, "Selected 65 MHz format: %s\n", p);
1170
1171 switch (afc0 & 0x7) {
1172 case 0: p = "chroma"; break;
1173 case 1: p = "BTSC"; break;
1174 case 2: p = "EIAJ"; break;
1175 case 3: p = "A2-M"; break;
1176 case 4: p = "autodetect"; break;
1177 default: p = "undefined";
1178 }
1179 v4l_info(client, "Selected 45 MHz format: %s\n", p);
1180 }
1181}
1182
1183/* ----------------------------------------------------------------------- */
1184
cc26b076 1185/* This load_fw operation must be called to load the driver's firmware.
6ca187ab
HV
1186 Without this the audio standard detection will fail and you will
1187 only get mono.
1188
1189 Since loading the firmware is often problematic when the driver is
1190 compiled into the kernel I recommend postponing calling this function
1191 until the first open of the video device. Another reason for
1192 postponing it is that loading this firmware takes a long time (seconds)
1193 due to the slow i2c bus speed. So it will speed up the boot process if
1194 you can avoid loading the fw as long as the video device isn't used. */
cc26b076 1195static int cx25840_load_fw(struct v4l2_subdev *sd)
bd985160 1196{
9357b31c
HV
1197 struct cx25840_state *state = to_state(sd);
1198 struct i2c_client *client = v4l2_get_subdevdata(sd);
c976bc82
HV
1199
1200 if (!state->is_initialized) {
cc26b076 1201 /* initialize and load firmware */
c976bc82
HV
1202 state->is_initialized = 1;
1203 if (state->is_cx25836)
1204 cx25836_initialize(client);
f234081b
ST
1205 else if (state->is_cx23885)
1206 cx23885_initialize(client);
95b14fb2 1207 else if (state->is_cx231xx)
149783b5 1208 cx231xx_initialize(client);
c976bc82 1209 else
89fc4eb9 1210 cx25840_initialize(client);
c976bc82 1211 }
9357b31c
HV
1212 return 0;
1213}
c976bc82 1214
bd985160 1215#ifdef CONFIG_VIDEO_ADV_DEBUG
aecde8b5 1216static int cx25840_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
9357b31c
HV
1217{
1218 struct i2c_client *client = v4l2_get_subdevdata(sd);
f234081b 1219
aecde8b5 1220 if (!v4l2_chip_match_i2c_client(client, &reg->match))
9357b31c
HV
1221 return -EINVAL;
1222 if (!capable(CAP_SYS_ADMIN))
1223 return -EPERM;
aecde8b5 1224 reg->size = 1;
9357b31c
HV
1225 reg->val = cx25840_read(client, reg->reg & 0x0fff);
1226 return 0;
1227}
1228
aecde8b5 1229static int cx25840_s_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
9357b31c
HV
1230{
1231 struct i2c_client *client = v4l2_get_subdevdata(sd);
1232
aecde8b5 1233 if (!v4l2_chip_match_i2c_client(client, &reg->match))
9357b31c
HV
1234 return -EINVAL;
1235 if (!capable(CAP_SYS_ADMIN))
1236 return -EPERM;
1237 cx25840_write(client, reg->reg & 0x0fff, reg->val & 0xff);
1238 return 0;
1239}
bd985160
HV
1240#endif
1241
9357b31c
HV
1242static int cx25840_s_stream(struct v4l2_subdev *sd, int enable)
1243{
1244 struct cx25840_state *state = to_state(sd);
1245 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160 1246
9357b31c
HV
1247 v4l_dbg(1, cx25840_debug, client, "%s output\n",
1248 enable ? "enable" : "disable");
1249 if (enable) {
149783b5 1250 if (state->is_cx23885 || state->is_cx231xx) {
f234081b
ST
1251 u8 v = (cx25840_read(client, 0x421) | 0x0b);
1252 cx25840_write(client, 0x421, v);
1253 } else {
1254 cx25840_write(client, 0x115,
9357b31c 1255 state->is_cx25836 ? 0x0c : 0x8c);
f234081b 1256 cx25840_write(client, 0x116,
9357b31c 1257 state->is_cx25836 ? 0x04 : 0x07);
f234081b 1258 }
9357b31c 1259 } else {
149783b5 1260 if (state->is_cx23885 || state->is_cx231xx) {
f234081b
ST
1261 u8 v = cx25840_read(client, 0x421) & ~(0x0b);
1262 cx25840_write(client, 0x421, v);
1263 } else {
1264 cx25840_write(client, 0x115, 0x00);
1265 cx25840_write(client, 0x116, 0x00);
1266 }
9357b31c
HV
1267 }
1268 return 0;
1269}
bd985160 1270
9357b31c
HV
1271static int cx25840_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc)
1272{
1273 struct cx25840_state *state = to_state(sd);
bd985160 1274
9357b31c
HV
1275 switch (qc->id) {
1276 case V4L2_CID_BRIGHTNESS:
10afbef1 1277 return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128);
9357b31c
HV
1278 case V4L2_CID_CONTRAST:
1279 case V4L2_CID_SATURATION:
10afbef1 1280 return v4l2_ctrl_query_fill(qc, 0, 127, 1, 64);
9357b31c 1281 case V4L2_CID_HUE:
10afbef1 1282 return v4l2_ctrl_query_fill(qc, -128, 127, 1, 0);
9357b31c
HV
1283 default:
1284 break;
1285 }
1286 if (state->is_cx25836)
1287 return -EINVAL;
bd985160 1288
9357b31c
HV
1289 switch (qc->id) {
1290 case V4L2_CID_AUDIO_VOLUME:
1291 return v4l2_ctrl_query_fill(qc, 0, 65535,
1292 65535 / 100, state->default_volume);
1293 case V4L2_CID_AUDIO_MUTE:
10afbef1 1294 return v4l2_ctrl_query_fill(qc, 0, 1, 1, 0);
9357b31c
HV
1295 case V4L2_CID_AUDIO_BALANCE:
1296 case V4L2_CID_AUDIO_BASS:
1297 case V4L2_CID_AUDIO_TREBLE:
10afbef1 1298 return v4l2_ctrl_query_fill(qc, 0, 65535, 65535 / 100, 32768);
9357b31c
HV
1299 default:
1300 return -EINVAL;
1301 }
1302 return -EINVAL;
1303}
bd985160 1304
9357b31c
HV
1305static int cx25840_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
1306{
1307 struct cx25840_state *state = to_state(sd);
1308 struct i2c_client *client = v4l2_get_subdevdata(sd);
d92c20e0 1309
9357b31c
HV
1310 if (state->radio == 0 && state->std == std)
1311 return 0;
1312 state->radio = 0;
1313 state->std = std;
1314 return set_v4lstd(client);
1315}
e2b8cf4c 1316
9357b31c
HV
1317static int cx25840_s_radio(struct v4l2_subdev *sd)
1318{
1319 struct cx25840_state *state = to_state(sd);
d92c20e0 1320
9357b31c
HV
1321 state->radio = 1;
1322 return 0;
1323}
bd985160 1324
5325b427
HV
1325static int cx25840_s_video_routing(struct v4l2_subdev *sd,
1326 u32 input, u32 output, u32 config)
9357b31c
HV
1327{
1328 struct cx25840_state *state = to_state(sd);
1329 struct i2c_client *client = v4l2_get_subdevdata(sd);
3faeeae4 1330
5325b427 1331 return set_input(client, input, state->aud_input);
9357b31c 1332}
bd985160 1333
5325b427
HV
1334static int cx25840_s_audio_routing(struct v4l2_subdev *sd,
1335 u32 input, u32 output, u32 config)
9357b31c
HV
1336{
1337 struct cx25840_state *state = to_state(sd);
1338 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160 1339
9357b31c
HV
1340 if (state->is_cx25836)
1341 return -EINVAL;
5325b427 1342 return set_input(client, state->vid_input, input);
9357b31c 1343}
bd985160 1344
9357b31c
HV
1345static int cx25840_s_frequency(struct v4l2_subdev *sd, struct v4l2_frequency *freq)
1346{
1347 struct cx25840_state *state = to_state(sd);
1348 struct i2c_client *client = v4l2_get_subdevdata(sd);
a8bbf12a 1349
9357b31c
HV
1350 if (!state->is_cx25836)
1351 input_change(client);
1352 return 0;
1353}
a8bbf12a 1354
9357b31c
HV
1355static int cx25840_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1356{
1357 struct cx25840_state *state = to_state(sd);
1358 struct i2c_client *client = v4l2_get_subdevdata(sd);
1359 u8 vpres = cx25840_read(client, 0x40e) & 0x20;
1360 u8 mode;
1361 int val = 0;
bd985160 1362
9357b31c
HV
1363 if (state->radio)
1364 return 0;
bd985160 1365
9357b31c
HV
1366 vt->signal = vpres ? 0xffff : 0x0;
1367 if (state->is_cx25836)
1368 return 0;
3faeeae4 1369
9357b31c
HV
1370 vt->capability |=
1371 V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 |
1372 V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP;
e2b8cf4c 1373
9357b31c 1374 mode = cx25840_read(client, 0x804);
bd985160 1375
9357b31c
HV
1376 /* get rxsubchans and audmode */
1377 if ((mode & 0xf) == 1)
1378 val |= V4L2_TUNER_SUB_STEREO;
1379 else
1380 val |= V4L2_TUNER_SUB_MONO;
bd985160 1381
9357b31c
HV
1382 if (mode == 2 || mode == 4)
1383 val = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
bd985160 1384
9357b31c
HV
1385 if (mode & 0x10)
1386 val |= V4L2_TUNER_SUB_SAP;
bd985160 1387
9357b31c
HV
1388 vt->rxsubchans = val;
1389 vt->audmode = state->audmode;
1390 return 0;
1391}
bd985160 1392
9357b31c
HV
1393static int cx25840_s_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1394{
1395 struct cx25840_state *state = to_state(sd);
1396 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160 1397
9357b31c
HV
1398 if (state->radio || state->is_cx25836)
1399 return 0;
8a4b275f 1400
9357b31c 1401 switch (vt->audmode) {
bd985160 1402 case V4L2_TUNER_MODE_MONO:
8a4b275f
HV
1403 /* mono -> mono
1404 stereo -> mono
1405 bilingual -> lang1 */
bd985160
HV
1406 cx25840_and_or(client, 0x809, ~0xf, 0x00);
1407 break;
301e22d6 1408 case V4L2_TUNER_MODE_STEREO:
8a4b275f
HV
1409 case V4L2_TUNER_MODE_LANG1:
1410 /* mono -> mono
1411 stereo -> stereo
1412 bilingual -> lang1 */
bd985160
HV
1413 cx25840_and_or(client, 0x809, ~0xf, 0x04);
1414 break;
301e22d6 1415 case V4L2_TUNER_MODE_LANG1_LANG2:
8a4b275f
HV
1416 /* mono -> mono
1417 stereo -> stereo
1418 bilingual -> lang1/lang2 */
1419 cx25840_and_or(client, 0x809, ~0xf, 0x07);
1420 break;
bd985160 1421 case V4L2_TUNER_MODE_LANG2:
8a4b275f 1422 /* mono -> mono
301e22d6 1423 stereo -> stereo
8a4b275f 1424 bilingual -> lang2 */
bd985160
HV
1425 cx25840_and_or(client, 0x809, ~0xf, 0x01);
1426 break;
8a4b275f
HV
1427 default:
1428 return -EINVAL;
9357b31c
HV
1429 }
1430 state->audmode = vt->audmode;
1431 return 0;
1432}
bd985160 1433
9357b31c
HV
1434static int cx25840_reset(struct v4l2_subdev *sd, u32 val)
1435{
1436 struct cx25840_state *state = to_state(sd);
1437 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160 1438
9357b31c
HV
1439 if (state->is_cx25836)
1440 cx25836_initialize(client);
1441 else if (state->is_cx23885)
1442 cx23885_initialize(client);
149783b5
SD
1443 else if (state->is_cx231xx)
1444 cx231xx_initialize(client);
9357b31c
HV
1445 else
1446 cx25840_initialize(client);
1447 return 0;
1448}
bd985160 1449
aecde8b5 1450static int cx25840_g_chip_ident(struct v4l2_subdev *sd, struct v4l2_dbg_chip_ident *chip)
9357b31c
HV
1451{
1452 struct cx25840_state *state = to_state(sd);
1453 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160 1454
9357b31c
HV
1455 return v4l2_chip_ident_i2c_client(client, chip, state->id, state->rev);
1456}
bd985160 1457
9357b31c
HV
1458static int cx25840_log_status(struct v4l2_subdev *sd)
1459{
1460 struct cx25840_state *state = to_state(sd);
1461 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160 1462
9357b31c
HV
1463 log_video_status(client);
1464 if (!state->is_cx25836)
1465 log_audio_status(client);
3faeeae4 1466 return 0;
bd985160
HV
1467}
1468
9357b31c
HV
1469/* ----------------------------------------------------------------------- */
1470
1471static const struct v4l2_subdev_core_ops cx25840_core_ops = {
1472 .log_status = cx25840_log_status,
1473 .g_chip_ident = cx25840_g_chip_ident,
1474 .g_ctrl = cx25840_g_ctrl,
1475 .s_ctrl = cx25840_s_ctrl,
1476 .queryctrl = cx25840_queryctrl,
f41737ec 1477 .s_std = cx25840_s_std,
9357b31c 1478 .reset = cx25840_reset,
cc26b076 1479 .load_fw = cx25840_load_fw,
9357b31c
HV
1480#ifdef CONFIG_VIDEO_ADV_DEBUG
1481 .g_register = cx25840_g_register,
1482 .s_register = cx25840_s_register,
1483#endif
1484};
1485
1486static const struct v4l2_subdev_tuner_ops cx25840_tuner_ops = {
1487 .s_frequency = cx25840_s_frequency,
9357b31c
HV
1488 .s_radio = cx25840_s_radio,
1489 .g_tuner = cx25840_g_tuner,
1490 .s_tuner = cx25840_s_tuner,
1491};
1492
1493static const struct v4l2_subdev_audio_ops cx25840_audio_ops = {
1494 .s_clock_freq = cx25840_s_clock_freq,
1495 .s_routing = cx25840_s_audio_routing,
1496};
1497
1498static const struct v4l2_subdev_video_ops cx25840_video_ops = {
1499 .s_routing = cx25840_s_video_routing,
1500 .g_fmt = cx25840_g_fmt,
1501 .s_fmt = cx25840_s_fmt,
1502 .decode_vbi_line = cx25840_decode_vbi_line,
1503 .s_stream = cx25840_s_stream,
1504};
1505
1506static const struct v4l2_subdev_ops cx25840_ops = {
1507 .core = &cx25840_core_ops,
1508 .tuner = &cx25840_tuner_ops,
1509 .audio = &cx25840_audio_ops,
1510 .video = &cx25840_video_ops,
1511};
1512
bd985160
HV
1513/* ----------------------------------------------------------------------- */
1514
d2653e92
JD
1515static int cx25840_probe(struct i2c_client *client,
1516 const struct i2c_device_id *did)
bd985160 1517{
bd985160 1518 struct cx25840_state *state;
9357b31c 1519 struct v4l2_subdev *sd;
3434eb7e 1520 u32 id;
bd985160
HV
1521 u16 device_id;
1522
188f3457
HV
1523 /* Check if the adapter supports the needed features */
1524 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1525 return -EIO;
1526
21340ae0 1527 v4l_dbg(1, cx25840_debug, client, "detecting cx25840 client on address 0x%x\n", client->addr << 1);
bd985160
HV
1528
1529 device_id = cx25840_read(client, 0x101) << 8;
1530 device_id |= cx25840_read(client, 0x100);
f234081b 1531 v4l_dbg(1, cx25840_debug, client, "device_id = 0x%04x\n", device_id);
bd985160
HV
1532
1533 /* The high byte of the device ID should be
e2b8cf4c
HV
1534 * 0x83 for the cx2583x and 0x84 for the cx2584x */
1535 if ((device_id & 0xff00) == 0x8300) {
1536 id = V4L2_IDENT_CX25836 + ((device_id >> 4) & 0xf) - 6;
e2b8cf4c
HV
1537 }
1538 else if ((device_id & 0xff00) == 0x8400) {
1539 id = V4L2_IDENT_CX25840 + ((device_id >> 4) & 0xf);
00ca7324 1540 } else if (device_id == 0x0000) {
f234081b 1541 id = V4L2_IDENT_CX25836 + ((device_id >> 4) & 0xf) - 6;
00ca7324 1542 } else if (device_id == 0x1313) {
f234081b 1543 id = V4L2_IDENT_CX25836 + ((device_id >> 4) & 0xf) - 6;
149783b5
SD
1544 } else if ((device_id & 0xfff0) == 0x5A30) {
1545 id = V4L2_IDENT_CX25840 + ((device_id >> 4) & 0xf);
e2b8cf4c
HV
1546 }
1547 else {
b5fc7144 1548 v4l_dbg(1, cx25840_debug, client, "cx25840 not found\n");
188f3457 1549 return -ENODEV;
bd985160
HV
1550 }
1551
21340ae0 1552 state = kzalloc(sizeof(struct cx25840_state), GFP_KERNEL);
9357b31c 1553 if (state == NULL)
21340ae0 1554 return -ENOMEM;
21340ae0 1555
9357b31c
HV
1556 sd = &state->sd;
1557 v4l2_i2c_subdev_init(sd, client, &cx25840_ops);
b7a01e72
HV
1558 /* Note: revision '(device_id & 0x0f) == 2' was never built. The
1559 marking skips from 0x1 == 22 to 0x3 == 23. */
fac9e899 1560 v4l_info(client, "cx25%3x-2%x found @ 0x%x (%s)\n",
bd985160 1561 (device_id & 0xfff0) >> 4,
b7a01e72 1562 (device_id & 0x0f) < 3 ? (device_id & 0x0f) + 1 : (device_id & 0x0f),
21340ae0 1563 client->addr << 1, client->adapter->name);
bd985160 1564
21340ae0
HV
1565 state->c = client;
1566 state->is_cx25836 = ((device_id & 0xff00) == 0x8300);
f234081b 1567 state->is_cx23885 = (device_id == 0x0000) || (device_id == 0x1313);
95b14fb2 1568 state->is_cx231xx = (device_id == 0x5a3e);
a8bbf12a
HV
1569 state->vid_input = CX25840_COMPOSITE7;
1570 state->aud_input = CX25840_AUDIO8;
3578d3dd 1571 state->audclk_freq = 48000;
a8bbf12a 1572 state->pvr150_workaround = 0;
8a4b275f 1573 state->audmode = V4L2_TUNER_MODE_LANG1;
87410dab 1574 state->unmute_volume = -1;
ca130eef
HV
1575 state->default_volume = 228 - cx25840_read(client, 0x8d4);
1576 state->default_volume = ((state->default_volume / 2) + 23) << 9;
3e3bf277 1577 state->vbi_line_offset = 8;
e2b8cf4c 1578 state->id = id;
3434eb7e 1579 state->rev = device_id;
f234081b 1580
2770b7d7
ST
1581 if (state->is_cx23885) {
1582 /* Drive GPIO2 direction and values */
1583 cx25840_write(client, 0x160, 0x1d);
1584 cx25840_write(client, 0x164, 0x00);
1585 }
1586
bd985160
HV
1587 return 0;
1588}
1589
1a39275a 1590static int cx25840_remove(struct i2c_client *client)
bd985160 1591{
9357b31c
HV
1592 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1593
1594 v4l2_device_unregister_subdev(sd);
1595 kfree(to_state(sd));
bd985160
HV
1596 return 0;
1597}
1598
af294867
JD
1599static const struct i2c_device_id cx25840_id[] = {
1600 { "cx25840", 0 },
1601 { }
1602};
1603MODULE_DEVICE_TABLE(i2c, cx25840_id);
1604
1a39275a
HV
1605static struct v4l2_i2c_driver_data v4l2_i2c_data = {
1606 .name = "cx25840",
1a39275a
HV
1607 .probe = cx25840_probe,
1608 .remove = cx25840_remove,
af294867 1609 .id_table = cx25840_id,
bd985160 1610};