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V4L/DVB: V4L: vpfe_capture: Return 0 from suspend/resume
[mirror_ubuntu-artful-kernel.git] / drivers / media / video / davinci / dm644x_ccdc.c
CommitLineData
5f15fbb6
MK		 1/*
2 * Copyright (C) 2006-2009 Texas Instruments Inc
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 *
18 * CCDC hardware module for DM6446
19 * ------------------------------
20 *
21 * This module is for configuring CCD controller of DM6446 VPFE to capture
22 * Raw yuv or Bayer RGB data from a decoder. CCDC has several modules
23 * such as Defect Pixel Correction, Color Space Conversion etc to
24 * pre-process the Raw Bayer RGB data, before writing it to SDRAM. This
25 * module also allows application to configure individual
26 * module parameters through VPFE_CMD_S_CCDC_RAW_PARAMS IOCTL.
27 * To do so, application includes dm644x_ccdc.h and vpfe_capture.h header
28 * files. The setparams() API is called by vpfe_capture driver
29 * to configure module parameters. This file is named DM644x so that other
30 * variants such DM6443 may be supported using the same module.
31 *
32 * TODO: Test Raw bayer parameter settings and bayer capture
33 * Split module parameter structure to module specific ioctl structs
34 * investigate if enum used for user space type definition
35 * to be replaced by #defines or integer
36 */
37#include <linux/platform_device.h>
38#include <linux/uaccess.h>
39#include <linux/videodev2.h>
5a0e3ad6 40#include <linux/gfp.h>
8d1b5946
MK		 41#include <linux/clk.h>
42#include <linux/err.h>
43
5f15fbb6
MK		 44#include <media/davinci/dm644x_ccdc.h>
45#include <media/davinci/vpss.h>
8d1b5946 46
5f15fbb6
MK		 47#include "dm644x_ccdc_regs.h"
48#include "ccdc_hw_device.h"
49
50MODULE_LICENSE("GPL");
51MODULE_DESCRIPTION("CCDC Driver for DM6446");
52MODULE_AUTHOR("Texas Instruments");
53
8d1b5946
MK		 54static struct ccdc_oper_config {
55 struct device *dev;
56 /* CCDC interface type */
57 enum vpfe_hw_if_type if_type;
58 /* Raw Bayer configuration */
59 struct ccdc_params_raw bayer;
60 /* YCbCr configuration */
61 struct ccdc_params_ycbcr ycbcr;
62 /* Master clock */
63 struct clk *mclk;
64 /* slave clock */
65 struct clk *sclk;
66 /* ccdc base address */
67 void __iomem *base_addr;
68} ccdc_cfg = {
69 /* Raw configurations */
70 .bayer = {
71 .pix_fmt = CCDC_PIXFMT_RAW,
72 .frm_fmt = CCDC_FRMFMT_PROGRESSIVE,
73 .win = CCDC_WIN_VGA,
74 .fid_pol = VPFE_PINPOL_POSITIVE,
75 .vd_pol = VPFE_PINPOL_POSITIVE,
76 .hd_pol = VPFE_PINPOL_POSITIVE,
77 .config_params = {
78 .data_sz = CCDC_DATA_10BITS,
79 },
80 },
81 .ycbcr = {
82 .pix_fmt = CCDC_PIXFMT_YCBCR_8BIT,
83 .frm_fmt = CCDC_FRMFMT_INTERLACED,
84 .win = CCDC_WIN_PAL,
85 .fid_pol = VPFE_PINPOL_POSITIVE,
86 .vd_pol = VPFE_PINPOL_POSITIVE,
87 .hd_pol = VPFE_PINPOL_POSITIVE,
88 .bt656_enable = 1,
89 .pix_order = CCDC_PIXORDER_CBYCRY,
90 .buf_type = CCDC_BUFTYPE_FLD_INTERLEAVED
5f15fbb6 91 },
5f15fbb6
MK		 92};
93
94#define CCDC_MAX_RAW_YUV_FORMATS 2
95
96/* Raw Bayer formats */
97static u32 ccdc_raw_bayer_pix_formats[] =
98 {V4L2_PIX_FMT_SBGGR8, V4L2_PIX_FMT_SBGGR16};
99
100/* Raw YUV formats */
101static u32 ccdc_raw_yuv_pix_formats[] =
102 {V4L2_PIX_FMT_UYVY, V4L2_PIX_FMT_YUYV};
103
5f15fbb6
MK		 104/* register access routines */
105static inline u32 regr(u32 offset)
106{
8d1b5946 107 return __raw_readl(ccdc_cfg.base_addr + offset);
5f15fbb6
MK		 108}
109
110static inline void regw(u32 val, u32 offset)
111{
8d1b5946 112 __raw_writel(val, ccdc_cfg.base_addr + offset);
5f15fbb6
MK		 113}
114
115static void ccdc_enable(int flag)
116{
117 regw(flag, CCDC_PCR);
118}
119
120static void ccdc_enable_vport(int flag)
121{
122 if (flag)
123 /* enable video port */
124 regw(CCDC_ENABLE_VIDEO_PORT, CCDC_FMTCFG);
125 else
126 regw(CCDC_DISABLE_VIDEO_PORT, CCDC_FMTCFG);
127}
128
129/*
130 * ccdc_setwin()
131 * This function will configure the window size
132 * to be capture in CCDC reg
133 */
134void ccdc_setwin(struct v4l2_rect *image_win,
135 enum ccdc_frmfmt frm_fmt,
136 int ppc)
137{
138 int horz_start, horz_nr_pixels;
139 int vert_start, vert_nr_lines;
140 int val = 0, mid_img = 0;
141
8d1b5946 142 dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_setwin...");
5f15fbb6
MK		 143 /*
144 * ppc - per pixel count. indicates how many pixels per cell
145 * output to SDRAM. example, for ycbcr, it is one y and one c, so 2.
146 * raw capture this is 1
147 */
148 horz_start = image_win->left << (ppc - 1);
149 horz_nr_pixels = (image_win->width << (ppc - 1)) - 1;
150 regw((horz_start << CCDC_HORZ_INFO_SPH_SHIFT) | horz_nr_pixels,
151 CCDC_HORZ_INFO);
152
153 vert_start = image_win->top;
154
155 if (frm_fmt == CCDC_FRMFMT_INTERLACED) {
156 vert_nr_lines = (image_win->height >> 1) - 1;
157 vert_start >>= 1;
158 /* Since first line doesn't have any data */
159 vert_start += 1;
160 /* configure VDINT0 */
161 val = (vert_start << CCDC_VDINT_VDINT0_SHIFT);
162 regw(val, CCDC_VDINT);
163
164 } else {
165 /* Since first line doesn't have any data */
166 vert_start += 1;
167 vert_nr_lines = image_win->height - 1;
168 /*
169 * configure VDINT0 and VDINT1. VDINT1 will be at half
170 * of image height
171 */
172 mid_img = vert_start + (image_win->height / 2);
173 val = (vert_start << CCDC_VDINT_VDINT0_SHIFT) |
174 (mid_img & CCDC_VDINT_VDINT1_MASK);
175 regw(val, CCDC_VDINT);
176
177 }
178 regw((vert_start << CCDC_VERT_START_SLV0_SHIFT) | vert_start,
179 CCDC_VERT_START);
180 regw(vert_nr_lines, CCDC_VERT_LINES);
8d1b5946 181 dev_dbg(ccdc_cfg.dev, "\nEnd of ccdc_setwin...");
5f15fbb6
MK		 182}
183
184static void ccdc_readregs(void)
185{
186 unsigned int val = 0;
187
188 val = regr(CCDC_ALAW);
8d1b5946 189 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to ALAW...\n", val);
5f15fbb6 190 val = regr(CCDC_CLAMP);
8d1b5946 191 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to CLAMP...\n", val);
5f15fbb6 192 val = regr(CCDC_DCSUB);
8d1b5946 193 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to DCSUB...\n", val);
5f15fbb6 194 val = regr(CCDC_BLKCMP);
8d1b5946 195 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to BLKCMP...\n", val);
5f15fbb6 196 val = regr(CCDC_FPC_ADDR);
8d1b5946 197 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FPC_ADDR...\n", val);
5f15fbb6 198 val = regr(CCDC_FPC);
8d1b5946 199 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FPC...\n", val);
5f15fbb6 200 val = regr(CCDC_FMTCFG);
8d1b5946 201 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FMTCFG...\n", val);
5f15fbb6 202 val = regr(CCDC_COLPTN);
8d1b5946 203 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to COLPTN...\n", val);
5f15fbb6 204 val = regr(CCDC_FMT_HORZ);
8d1b5946 205 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FMT_HORZ...\n", val);
5f15fbb6 206 val = regr(CCDC_FMT_VERT);
8d1b5946 207 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FMT_VERT...\n", val);
5f15fbb6 208 val = regr(CCDC_HSIZE_OFF);
8d1b5946 209 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to HSIZE_OFF...\n", val);
5f15fbb6 210 val = regr(CCDC_SDOFST);
8d1b5946 211 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to SDOFST...\n", val);
5f15fbb6 212 val = regr(CCDC_VP_OUT);
8d1b5946 213 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to VP_OUT...\n", val);
5f15fbb6 214 val = regr(CCDC_SYN_MODE);
8d1b5946 215 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to SYN_MODE...\n", val);
5f15fbb6 216 val = regr(CCDC_HORZ_INFO);
8d1b5946 217 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to HORZ_INFO...\n", val);
5f15fbb6 218 val = regr(CCDC_VERT_START);
8d1b5946 219 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to VERT_START...\n", val);
5f15fbb6 220 val = regr(CCDC_VERT_LINES);
8d1b5946 221 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to VERT_LINES...\n", val);
5f15fbb6
MK		 222}
223
224static int validate_ccdc_param(struct ccdc_config_params_raw *ccdcparam)
225{
226 if (ccdcparam->alaw.enable) {
227 if ((ccdcparam->alaw.gama_wd > CCDC_GAMMA_BITS_09_0) ||
228 (ccdcparam->alaw.gama_wd < CCDC_GAMMA_BITS_15_6) ||
229 (ccdcparam->alaw.gama_wd < ccdcparam->data_sz)) {
8d1b5946 230 dev_dbg(ccdc_cfg.dev, "\nInvalid data line select");
5f15fbb6
MK		 231 return -1;
232 }
233 }
234 return 0;
235}
236
237static int ccdc_update_raw_params(struct ccdc_config_params_raw *raw_params)
238{
239 struct ccdc_config_params_raw *config_params =
8d1b5946 240 &ccdc_cfg.bayer.config_params;
5f15fbb6
MK		 241 unsigned int *fpc_virtaddr = NULL;
242 unsigned int *fpc_physaddr = NULL;
243
244 memcpy(config_params, raw_params, sizeof(*raw_params));
245 /*
246 * allocate memory for fault pixel table and copy the user
247 * values to the table
248 */
249 if (!config_params->fault_pxl.enable)
250 return 0;
251
252 fpc_physaddr = (unsigned int *)config_params->fault_pxl.fpc_table_addr;
253 fpc_virtaddr = (unsigned int *)phys_to_virt(
254 (unsigned long)fpc_physaddr);
255 /*
256 * Allocate memory for FPC table if current
257 * FPC table buffer is not big enough to
258 * accomodate FPC Number requested
259 */
260 if (raw_params->fault_pxl.fp_num != config_params->fault_pxl.fp_num) {
261 if (fpc_physaddr != NULL) {
262 free_pages((unsigned long)fpc_physaddr,
263 get_order
264 (config_params->fault_pxl.fp_num *
265 FP_NUM_BYTES));
266 }
267
268 /* Allocate memory for FPC table */
269 fpc_virtaddr =
270 (unsigned int *)__get_free_pages(GFP_KERNEL | GFP_DMA,
271 get_order(raw_params->
272 fault_pxl.fp_num *
273 FP_NUM_BYTES));
274
275 if (fpc_virtaddr == NULL) {
8d1b5946 276 dev_dbg(ccdc_cfg.dev,
5f15fbb6
MK		 277 "\nUnable to allocate memory for FPC");
278 return -EFAULT;
279 }
280 fpc_physaddr =
281 (unsigned int *)virt_to_phys((void *)fpc_virtaddr);
282 }
283
284 /* Copy number of fault pixels and FPC table */
285 config_params->fault_pxl.fp_num = raw_params->fault_pxl.fp_num;
286 if (copy_from_user(fpc_virtaddr,
287 (void __user *)raw_params->fault_pxl.fpc_table_addr,
288 config_params->fault_pxl.fp_num * FP_NUM_BYTES)) {
8d1b5946 289 dev_dbg(ccdc_cfg.dev, "\n copy_from_user failed");
5f15fbb6
MK		 290 return -EFAULT;
291 }
292 config_params->fault_pxl.fpc_table_addr = (unsigned int)fpc_physaddr;
293 return 0;
294}
295
296static int ccdc_close(struct device *dev)
297{
298 struct ccdc_config_params_raw *config_params =
8d1b5946 299 &ccdc_cfg.bayer.config_params;
5f15fbb6
MK		 300 unsigned int *fpc_physaddr = NULL, *fpc_virtaddr = NULL;
301
302 fpc_physaddr = (unsigned int *)config_params->fault_pxl.fpc_table_addr;
303
304 if (fpc_physaddr != NULL) {
305 fpc_virtaddr = (unsigned int *)
306 phys_to_virt((unsigned long)fpc_physaddr);
307 free_pages((unsigned long)fpc_virtaddr,
308 get_order(config_params->fault_pxl.fp_num *
309 FP_NUM_BYTES));
310 }
311 return 0;
312}
313
314/*
315 * ccdc_restore_defaults()
316 * This function will write defaults to all CCDC registers
317 */
318static void ccdc_restore_defaults(void)
319{
320 int i;
321
322 /* disable CCDC */
323 ccdc_enable(0);
324 /* set all registers to default value */
325 for (i = 4; i <= 0x94; i += 4)
326 regw(0, i);
327 regw(CCDC_NO_CULLING, CCDC_CULLING);
328 regw(CCDC_GAMMA_BITS_11_2, CCDC_ALAW);
329}
330
331static int ccdc_open(struct device *device)
332{
5f15fbb6 333 ccdc_restore_defaults();
8d1b5946 334 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
5f15fbb6
MK		 335 ccdc_enable_vport(1);
336 return 0;
337}
338
339static void ccdc_sbl_reset(void)
340{
341 vpss_clear_wbl_overflow(VPSS_PCR_CCDC_WBL_O);
342}
343
344/* Parameter operations */
345static int ccdc_set_params(void __user *params)
346{
347 struct ccdc_config_params_raw ccdc_raw_params;
348 int x;
349
8d1b5946 350 if (ccdc_cfg.if_type != VPFE_RAW_BAYER)
5f15fbb6
MK		 351 return -EINVAL;
352
353 x = copy_from_user(&ccdc_raw_params, params, sizeof(ccdc_raw_params));
354 if (x) {
8d1b5946 355 dev_dbg(ccdc_cfg.dev, "ccdc_set_params: error in copying"
5f15fbb6
MK		 356 "ccdc params, %d\n", x);
357 return -EFAULT;
358 }
359
360 if (!validate_ccdc_param(&ccdc_raw_params)) {
361 if (!ccdc_update_raw_params(&ccdc_raw_params))
362 return 0;
363 }
364 return -EINVAL;
365}
366
367/*
368 * ccdc_config_ycbcr()
369 * This function will configure CCDC for YCbCr video capture
370 */
371void ccdc_config_ycbcr(void)
372{
8d1b5946 373 struct ccdc_params_ycbcr *params = &ccdc_cfg.ycbcr;
5f15fbb6
MK		 374 u32 syn_mode;
375
8d1b5946 376 dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_config_ycbcr...");
5f15fbb6
MK		 377 /*
378 * first restore the CCDC registers to default values
379 * This is important since we assume default values to be set in
380 * a lot of registers that we didn't touch
381 */
382 ccdc_restore_defaults();
383
384 /*
385 * configure pixel format, frame format, configure video frame
386 * format, enable output to SDRAM, enable internal timing generator
387 * and 8bit pack mode
388 */
389 syn_mode = (((params->pix_fmt & CCDC_SYN_MODE_INPMOD_MASK) <<
390 CCDC_SYN_MODE_INPMOD_SHIFT) |
391 ((params->frm_fmt & CCDC_SYN_FLDMODE_MASK) <<
392 CCDC_SYN_FLDMODE_SHIFT) | CCDC_VDHDEN_ENABLE |
393 CCDC_WEN_ENABLE | CCDC_DATA_PACK_ENABLE);
394
395 /* setup BT.656 sync mode */
396 if (params->bt656_enable) {
397 regw(CCDC_REC656IF_BT656_EN, CCDC_REC656IF);
398
399 /*
400 * configure the FID, VD, HD pin polarity,
401 * fld,hd pol positive, vd negative, 8-bit data
402 */
21aa300e
VH		 403 syn_mode |= CCDC_SYN_MODE_VD_POL_NEGATIVE;
404 if (ccdc_cfg.if_type == VPFE_BT656_10BIT)
405 syn_mode |= CCDC_SYN_MODE_10BITS;
406 else
407 syn_mode |= CCDC_SYN_MODE_8BITS;
5f15fbb6
MK		 408 } else {
409 /* y/c external sync mode */
410 syn_mode |= (((params->fid_pol & CCDC_FID_POL_MASK) <<
411 CCDC_FID_POL_SHIFT) |
412 ((params->hd_pol & CCDC_HD_POL_MASK) <<
413 CCDC_HD_POL_SHIFT) |
414 ((params->vd_pol & CCDC_VD_POL_MASK) <<
415 CCDC_VD_POL_SHIFT));
416 }
417 regw(syn_mode, CCDC_SYN_MODE);
418
419 /* configure video window */
420 ccdc_setwin(&params->win, params->frm_fmt, 2);
421
422 /*
423 * configure the order of y cb cr in SDRAM, and disable latch
424 * internal register on vsync
425 */
21aa300e
VH		 426 if (ccdc_cfg.if_type == VPFE_BT656_10BIT)
427 regw((params->pix_order << CCDC_CCDCFG_Y8POS_SHIFT) |
428 CCDC_LATCH_ON_VSYNC_DISABLE | CCDC_CCDCFG_BW656_10BIT,
429 CCDC_CCDCFG);
430 else
431 regw((params->pix_order << CCDC_CCDCFG_Y8POS_SHIFT) |
432 CCDC_LATCH_ON_VSYNC_DISABLE, CCDC_CCDCFG);
5f15fbb6
MK		 433
434 /*
435 * configure the horizontal line offset. This should be a
436 * on 32 byte bondary. So clear LSB 5 bits
437 */
438 regw(((params->win.width * 2 + 31) & ~0x1f), CCDC_HSIZE_OFF);
439
440 /* configure the memory line offset */
441 if (params->buf_type == CCDC_BUFTYPE_FLD_INTERLEAVED)
442 /* two fields are interleaved in memory */
443 regw(CCDC_SDOFST_FIELD_INTERLEAVED, CCDC_SDOFST);
444
445 ccdc_sbl_reset();
8d1b5946 446 dev_dbg(ccdc_cfg.dev, "\nEnd of ccdc_config_ycbcr...\n");
5f15fbb6
MK		 447}
448
449static void ccdc_config_black_clamp(struct ccdc_black_clamp *bclamp)
450{
451 u32 val;
452
453 if (!bclamp->enable) {
454 /* configure DCSub */
455 val = (bclamp->dc_sub) & CCDC_BLK_DC_SUB_MASK;
456 regw(val, CCDC_DCSUB);
8d1b5946 457 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to DCSUB...\n", val);
5f15fbb6 458 regw(CCDC_CLAMP_DEFAULT_VAL, CCDC_CLAMP);
8d1b5946 459 dev_dbg(ccdc_cfg.dev, "\nWriting 0x0000 to CLAMP...\n");
5f15fbb6
MK		 460 return;
461 }
462 /*
463 * Configure gain, Start pixel, No of line to be avg,
464 * No of pixel/line to be avg, & Enable the Black clamping
465 */
466 val = ((bclamp->sgain & CCDC_BLK_SGAIN_MASK) |
467 ((bclamp->start_pixel & CCDC_BLK_ST_PXL_MASK) <<
468 CCDC_BLK_ST_PXL_SHIFT) |
469 ((bclamp->sample_ln & CCDC_BLK_SAMPLE_LINE_MASK) <<
470 CCDC_BLK_SAMPLE_LINE_SHIFT) |
471 ((bclamp->sample_pixel & CCDC_BLK_SAMPLE_LN_MASK) <<
472 CCDC_BLK_SAMPLE_LN_SHIFT) | CCDC_BLK_CLAMP_ENABLE);
473 regw(val, CCDC_CLAMP);
8d1b5946 474 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to CLAMP...\n", val);
5f15fbb6
MK		 475 /* If Black clamping is enable then make dcsub 0 */
476 regw(CCDC_DCSUB_DEFAULT_VAL, CCDC_DCSUB);
8d1b5946 477 dev_dbg(ccdc_cfg.dev, "\nWriting 0x00000000 to DCSUB...\n");
5f15fbb6
MK		 478}
479
480static void ccdc_config_black_compense(struct ccdc_black_compensation *bcomp)
481{
482 u32 val;
483
484 val = ((bcomp->b & CCDC_BLK_COMP_MASK) |
485 ((bcomp->gb & CCDC_BLK_COMP_MASK) <<
486 CCDC_BLK_COMP_GB_COMP_SHIFT) |
487 ((bcomp->gr & CCDC_BLK_COMP_MASK) <<
488 CCDC_BLK_COMP_GR_COMP_SHIFT) |
489 ((bcomp->r & CCDC_BLK_COMP_MASK) <<
490 CCDC_BLK_COMP_R_COMP_SHIFT));
491 regw(val, CCDC_BLKCMP);
492}
493
494static void ccdc_config_fpc(struct ccdc_fault_pixel *fpc)
495{
496 u32 val;
497
498 /* Initially disable FPC */
499 val = CCDC_FPC_DISABLE;
500 regw(val, CCDC_FPC);
501
502 if (!fpc->enable)
503 return;
504
505 /* Configure Fault pixel if needed */
506 regw(fpc->fpc_table_addr, CCDC_FPC_ADDR);
8d1b5946 507 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to FPC_ADDR...\n",
5f15fbb6
MK		 508 (fpc->fpc_table_addr));
509 /* Write the FPC params with FPC disable */
510 val = fpc->fp_num & CCDC_FPC_FPC_NUM_MASK;
511 regw(val, CCDC_FPC);
512
8d1b5946 513 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to FPC...\n", val);
5f15fbb6
MK		 514 /* read the FPC register */
515 val = regr(CCDC_FPC) | CCDC_FPC_ENABLE;
516 regw(val, CCDC_FPC);
8d1b5946 517 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to FPC...\n", val);
5f15fbb6
MK		 518}
519
520/*
521 * ccdc_config_raw()
522 * This function will configure CCDC for Raw capture mode
523 */
524void ccdc_config_raw(void)
525{
8d1b5946 526 struct ccdc_params_raw *params = &ccdc_cfg.bayer;
5f15fbb6 527 struct ccdc_config_params_raw *config_params =
8d1b5946 528 &ccdc_cfg.bayer.config_params;
5f15fbb6
MK		 529 unsigned int syn_mode = 0;
530 unsigned int val;
531
8d1b5946 532 dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_config_raw...");
5f15fbb6
MK		 533
534 /* Reset CCDC */
535 ccdc_restore_defaults();
536
537 /* Disable latching function registers on VSYNC */
538 regw(CCDC_LATCH_ON_VSYNC_DISABLE, CCDC_CCDCFG);
539
540 /*
541 * Configure the vertical sync polarity(SYN_MODE.VDPOL),
542 * horizontal sync polarity (SYN_MODE.HDPOL), frame id polarity
543 * (SYN_MODE.FLDPOL), frame format(progressive or interlace),
544 * data size(SYNMODE.DATSIZ), &pixel format (Input mode), output
545 * SDRAM, enable internal timing generator
546 */
547 syn_mode =
548 (((params->vd_pol & CCDC_VD_POL_MASK) << CCDC_VD_POL_SHIFT) |
549 ((params->hd_pol & CCDC_HD_POL_MASK) << CCDC_HD_POL_SHIFT) |
550 ((params->fid_pol & CCDC_FID_POL_MASK) << CCDC_FID_POL_SHIFT) |
551 ((params->frm_fmt & CCDC_FRM_FMT_MASK) << CCDC_FRM_FMT_SHIFT) |
552 ((config_params->data_sz & CCDC_DATA_SZ_MASK) <<
553 CCDC_DATA_SZ_SHIFT) |
554 ((params->pix_fmt & CCDC_PIX_FMT_MASK) << CCDC_PIX_FMT_SHIFT) |
555 CCDC_WEN_ENABLE | CCDC_VDHDEN_ENABLE);
556
557 /* Enable and configure aLaw register if needed */
558 if (config_params->alaw.enable) {
559 val = ((config_params->alaw.gama_wd &
560 CCDC_ALAW_GAMA_WD_MASK) | CCDC_ALAW_ENABLE);
561 regw(val, CCDC_ALAW);
8d1b5946 562 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to ALAW...\n", val);
5f15fbb6
MK		 563 }
564
565 /* Configure video window */
566 ccdc_setwin(&params->win, params->frm_fmt, CCDC_PPC_RAW);
567
568 /* Configure Black Clamp */
569 ccdc_config_black_clamp(&config_params->blk_clamp);
570
571 /* Configure Black level compensation */
572 ccdc_config_black_compense(&config_params->blk_comp);
573
574 /* Configure Fault Pixel Correction */
575 ccdc_config_fpc(&config_params->fault_pxl);
576
577 /* If data size is 8 bit then pack the data */
578 if ((config_params->data_sz == CCDC_DATA_8BITS) ||
579 config_params->alaw.enable)
580 syn_mode |= CCDC_DATA_PACK_ENABLE;
581
582#ifdef CONFIG_DM644X_VIDEO_PORT_ENABLE
583 /* enable video port */
584 val = CCDC_ENABLE_VIDEO_PORT;
585#else
586 /* disable video port */
587 val = CCDC_DISABLE_VIDEO_PORT;
588#endif
589
590 if (config_params->data_sz == CCDC_DATA_8BITS)
591 val |= (CCDC_DATA_10BITS & CCDC_FMTCFG_VPIN_MASK)
592 << CCDC_FMTCFG_VPIN_SHIFT;
593 else
594 val |= (config_params->data_sz & CCDC_FMTCFG_VPIN_MASK)
595 << CCDC_FMTCFG_VPIN_SHIFT;
596 /* Write value in FMTCFG */
597 regw(val, CCDC_FMTCFG);
598
8d1b5946 599 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to FMTCFG...\n", val);
5f15fbb6
MK		 600 /* Configure the color pattern according to mt9t001 sensor */
601 regw(CCDC_COLPTN_VAL, CCDC_COLPTN);
602
8d1b5946 603 dev_dbg(ccdc_cfg.dev, "\nWriting 0xBB11BB11 to COLPTN...\n");
5f15fbb6
MK		 604 /*
605 * Configure Data formatter(Video port) pixel selection
606 * (FMT_HORZ, FMT_VERT)
607 */
608 val = ((params->win.left & CCDC_FMT_HORZ_FMTSPH_MASK) <<
609 CCDC_FMT_HORZ_FMTSPH_SHIFT) |
610 (params->win.width & CCDC_FMT_HORZ_FMTLNH_MASK);
611 regw(val, CCDC_FMT_HORZ);
612
8d1b5946 613 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to FMT_HORZ...\n", val);
5f15fbb6
MK		 614 val = (params->win.top & CCDC_FMT_VERT_FMTSLV_MASK)
615 << CCDC_FMT_VERT_FMTSLV_SHIFT;
616 if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE)
617 val |= (params->win.height) & CCDC_FMT_VERT_FMTLNV_MASK;
618 else
619 val |= (params->win.height >> 1) & CCDC_FMT_VERT_FMTLNV_MASK;
620
8d1b5946 621 dev_dbg(ccdc_cfg.dev, "\nparams->win.height 0x%x ...\n",
5f15fbb6
MK		 622 params->win.height);
623 regw(val, CCDC_FMT_VERT);
624
8d1b5946 625 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to FMT_VERT...\n", val);
5f15fbb6 626
8d1b5946 627 dev_dbg(ccdc_cfg.dev, "\nbelow regw(val, FMT_VERT)...");
5f15fbb6
MK		 628
629 /*
630 * Configure Horizontal offset register. If pack 8 is enabled then
631 * 1 pixel will take 1 byte
632 */
633 if ((config_params->data_sz == CCDC_DATA_8BITS) ||
634 config_params->alaw.enable)
635 regw((params->win.width + CCDC_32BYTE_ALIGN_VAL) &
636 CCDC_HSIZE_OFF_MASK, CCDC_HSIZE_OFF);
637 else
638 /* else one pixel will take 2 byte */
639 regw(((params->win.width * CCDC_TWO_BYTES_PER_PIXEL) +
640 CCDC_32BYTE_ALIGN_VAL) & CCDC_HSIZE_OFF_MASK,
641 CCDC_HSIZE_OFF);
642
643 /* Set value for SDOFST */
644 if (params->frm_fmt == CCDC_FRMFMT_INTERLACED) {
645 if (params->image_invert_enable) {
646 /* For intelace inverse mode */
647 regw(CCDC_INTERLACED_IMAGE_INVERT, CCDC_SDOFST);
8d1b5946 648 dev_dbg(ccdc_cfg.dev, "\nWriting 0x4B6D to SDOFST..\n");
5f15fbb6
MK		 649 }
650
651 else {
652 /* For intelace non inverse mode */
653 regw(CCDC_INTERLACED_NO_IMAGE_INVERT, CCDC_SDOFST);
8d1b5946 654 dev_dbg(ccdc_cfg.dev, "\nWriting 0x0249 to SDOFST..\n");
5f15fbb6
MK		 655 }
656 } else if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE) {
657 regw(CCDC_PROGRESSIVE_NO_IMAGE_INVERT, CCDC_SDOFST);
8d1b5946 658 dev_dbg(ccdc_cfg.dev, "\nWriting 0x0000 to SDOFST...\n");
5f15fbb6
MK		 659 }
660
661 /*
662 * Configure video port pixel selection (VPOUT)
663 * Here -1 is to make the height value less than FMT_VERT.FMTLNV
664 */
665 if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE)
666 val = (((params->win.height - 1) & CCDC_VP_OUT_VERT_NUM_MASK))
667 << CCDC_VP_OUT_VERT_NUM_SHIFT;
668 else
669 val =
670 ((((params->win.height >> CCDC_INTERLACED_HEIGHT_SHIFT) -
671 1) & CCDC_VP_OUT_VERT_NUM_MASK)) <<
672 CCDC_VP_OUT_VERT_NUM_SHIFT;
673
674 val |= ((((params->win.width))) & CCDC_VP_OUT_HORZ_NUM_MASK)
675 << CCDC_VP_OUT_HORZ_NUM_SHIFT;
676 val |= (params->win.left) & CCDC_VP_OUT_HORZ_ST_MASK;
677 regw(val, CCDC_VP_OUT);
678
8d1b5946 679 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to VP_OUT...\n", val);
5f15fbb6 680 regw(syn_mode, CCDC_SYN_MODE);
8d1b5946 681 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to SYN_MODE...\n", syn_mode);
5f15fbb6
MK		 682
683 ccdc_sbl_reset();
8d1b5946 684 dev_dbg(ccdc_cfg.dev, "\nend of ccdc_config_raw...");
5f15fbb6
MK		 685 ccdc_readregs();
686}
687
688static int ccdc_configure(void)
689{
8d1b5946 690 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
5f15fbb6
MK		 691 ccdc_config_raw();
692 else
693 ccdc_config_ycbcr();
694 return 0;
695}
696
697static int ccdc_set_buftype(enum ccdc_buftype buf_type)
698{
8d1b5946
MK		 699 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
700 ccdc_cfg.bayer.buf_type = buf_type;
5f15fbb6 701 else
8d1b5946 702 ccdc_cfg.ycbcr.buf_type = buf_type;
5f15fbb6
MK		 703 return 0;
704}
705
706static enum ccdc_buftype ccdc_get_buftype(void)
707{
8d1b5946
MK		 708 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
709 return ccdc_cfg.bayer.buf_type;
710 return ccdc_cfg.ycbcr.buf_type;
5f15fbb6
MK		 711}
712
713static int ccdc_enum_pix(u32 *pix, int i)
714{
715 int ret = -EINVAL;
8d1b5946 716 if (ccdc_cfg.if_type == VPFE_RAW_BAYER) {
5f15fbb6
MK		 717 if (i < ARRAY_SIZE(ccdc_raw_bayer_pix_formats)) {
718 *pix = ccdc_raw_bayer_pix_formats[i];
719 ret = 0;
720 }
721 } else {
722 if (i < ARRAY_SIZE(ccdc_raw_yuv_pix_formats)) {
723 *pix = ccdc_raw_yuv_pix_formats[i];
724 ret = 0;
725 }
726 }
727 return ret;
728}
729
730static int ccdc_set_pixel_format(u32 pixfmt)
731{
8d1b5946
MK		 732 if (ccdc_cfg.if_type == VPFE_RAW_BAYER) {
733 ccdc_cfg.bayer.pix_fmt = CCDC_PIXFMT_RAW;
5f15fbb6 734 if (pixfmt == V4L2_PIX_FMT_SBGGR8)
8d1b5946 735 ccdc_cfg.bayer.config_params.alaw.enable = 1;
5f15fbb6
MK		 736 else if (pixfmt != V4L2_PIX_FMT_SBGGR16)
737 return -EINVAL;
738 } else {
739 if (pixfmt == V4L2_PIX_FMT_YUYV)
8d1b5946 740 ccdc_cfg.ycbcr.pix_order = CCDC_PIXORDER_YCBYCR;
5f15fbb6 741 else if (pixfmt == V4L2_PIX_FMT_UYVY)
8d1b5946 742 ccdc_cfg.ycbcr.pix_order = CCDC_PIXORDER_CBYCRY;
5f15fbb6
MK		 743 else
744 return -EINVAL;
745 }
746 return 0;
747}
748
749static u32 ccdc_get_pixel_format(void)
750{
8d1b5946 751 struct ccdc_a_law *alaw = &ccdc_cfg.bayer.config_params.alaw;
5f15fbb6
MK		 752 u32 pixfmt;
753
8d1b5946 754 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
5f15fbb6
MK		 755 if (alaw->enable)
756 pixfmt = V4L2_PIX_FMT_SBGGR8;
757 else
758 pixfmt = V4L2_PIX_FMT_SBGGR16;
759 else {
8d1b5946 760 if (ccdc_cfg.ycbcr.pix_order == CCDC_PIXORDER_YCBYCR)
5f15fbb6
MK		 761 pixfmt = V4L2_PIX_FMT_YUYV;
762 else
763 pixfmt = V4L2_PIX_FMT_UYVY;
764 }
765 return pixfmt;
766}
767
768static int ccdc_set_image_window(struct v4l2_rect *win)
769{
8d1b5946
MK		 770 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
771 ccdc_cfg.bayer.win = *win;
5f15fbb6 772 else
8d1b5946 773 ccdc_cfg.ycbcr.win = *win;
5f15fbb6
MK		 774 return 0;
775}
776
777static void ccdc_get_image_window(struct v4l2_rect *win)
778{
8d1b5946
MK		 779 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
780 *win = ccdc_cfg.bayer.win;
5f15fbb6 781 else
8d1b5946 782 *win = ccdc_cfg.ycbcr.win;
5f15fbb6
MK		 783}
784
785static unsigned int ccdc_get_line_length(void)
786{
787 struct ccdc_config_params_raw *config_params =
8d1b5946 788 &ccdc_cfg.bayer.config_params;
5f15fbb6
MK		 789 unsigned int len;
790
8d1b5946 791 if (ccdc_cfg.if_type == VPFE_RAW_BAYER) {
5f15fbb6
MK		 792 if ((config_params->alaw.enable) ||
793 (config_params->data_sz == CCDC_DATA_8BITS))
8d1b5946 794 len = ccdc_cfg.bayer.win.width;
5f15fbb6 795 else
8d1b5946 796 len = ccdc_cfg.bayer.win.width * 2;
5f15fbb6 797 } else
8d1b5946 798 len = ccdc_cfg.ycbcr.win.width * 2;
5f15fbb6
MK		 799 return ALIGN(len, 32);
800}
801
802static int ccdc_set_frame_format(enum ccdc_frmfmt frm_fmt)
803{
8d1b5946
MK		 804 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
805 ccdc_cfg.bayer.frm_fmt = frm_fmt;
5f15fbb6 806 else
8d1b5946 807 ccdc_cfg.ycbcr.frm_fmt = frm_fmt;
5f15fbb6
MK		 808 return 0;
809}
810
811static enum ccdc_frmfmt ccdc_get_frame_format(void)
812{
8d1b5946
MK		 813 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
814 return ccdc_cfg.bayer.frm_fmt;
5f15fbb6 815 else
8d1b5946 816 return ccdc_cfg.ycbcr.frm_fmt;
5f15fbb6
MK		 817}
818
819static int ccdc_getfid(void)
820{
821 return (regr(CCDC_SYN_MODE) >> 15) & 1;
822}
823
824/* misc operations */
825static inline void ccdc_setfbaddr(unsigned long addr)
826{
827 regw(addr & 0xffffffe0, CCDC_SDR_ADDR);
828}
829
830static int ccdc_set_hw_if_params(struct vpfe_hw_if_param *params)
831{
8d1b5946 832 ccdc_cfg.if_type = params->if_type;
5f15fbb6
MK		 833
834 switch (params->if_type) {
835 case VPFE_BT656:
836 case VPFE_YCBCR_SYNC_16:
837 case VPFE_YCBCR_SYNC_8:
21aa300e 838 case VPFE_BT656_10BIT:
8d1b5946
MK		 839 ccdc_cfg.ycbcr.vd_pol = params->vdpol;
840 ccdc_cfg.ycbcr.hd_pol = params->hdpol;
5f15fbb6
MK		 841 break;
842 default:
843 /* TODO add support for raw bayer here */
844 return -EINVAL;
845 }
846 return 0;
847}
848
849static struct ccdc_hw_device ccdc_hw_dev = {
850 .name = "DM6446 CCDC",
851 .owner = THIS_MODULE,
852 .hw_ops = {
853 .open = ccdc_open,
854 .close = ccdc_close,
5f15fbb6
MK		 855 .reset = ccdc_sbl_reset,
856 .enable = ccdc_enable,
857 .set_hw_if_params = ccdc_set_hw_if_params,
858 .set_params = ccdc_set_params,
859 .configure = ccdc_configure,
860 .set_buftype = ccdc_set_buftype,
861 .get_buftype = ccdc_get_buftype,
862 .enum_pix = ccdc_enum_pix,
863 .set_pixel_format = ccdc_set_pixel_format,
864 .get_pixel_format = ccdc_get_pixel_format,
865 .set_frame_format = ccdc_set_frame_format,
866 .get_frame_format = ccdc_get_frame_format,
867 .set_image_window = ccdc_set_image_window,
868 .get_image_window = ccdc_get_image_window,
869 .get_line_length = ccdc_get_line_length,
870 .setfbaddr = ccdc_setfbaddr,
871 .getfid = ccdc_getfid,
872 },
873};
874
8d1b5946 875static int __init dm644x_ccdc_probe(struct platform_device *pdev)
5f15fbb6 876{
8d1b5946
MK		 877 struct resource *res;
878 int status = 0;
879
880 /*
881 * first try to register with vpfe. If not correct platform, then we
882 * don't have to iomap
883 */
884 status = vpfe_register_ccdc_device(&ccdc_hw_dev);
885 if (status < 0)
886 return status;
887
888 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
889 if (!res) {
890 status = -ENODEV;
891 goto fail_nores;
892 }
893
894 res = request_mem_region(res->start, resource_size(res), res->name);
895 if (!res) {
896 status = -EBUSY;
897 goto fail_nores;
898 }
899
900 ccdc_cfg.base_addr = ioremap_nocache(res->start, resource_size(res));
901 if (!ccdc_cfg.base_addr) {
902 status = -ENOMEM;
903 goto fail_nomem;
904 }
905
906 /* Get and enable Master clock */
907 ccdc_cfg.mclk = clk_get(&pdev->dev, "master");
908 if (IS_ERR(ccdc_cfg.mclk)) {
909 status = PTR_ERR(ccdc_cfg.mclk);
910 goto fail_nomap;
911 }
912 if (clk_enable(ccdc_cfg.mclk)) {
913 status = -ENODEV;
914 goto fail_mclk;
915 }
916
917 /* Get and enable Slave clock */
918 ccdc_cfg.sclk = clk_get(&pdev->dev, "slave");
919 if (IS_ERR(ccdc_cfg.sclk)) {
920 status = PTR_ERR(ccdc_cfg.sclk);
921 goto fail_mclk;
922 }
923 if (clk_enable(ccdc_cfg.sclk)) {
924 status = -ENODEV;
925 goto fail_sclk;
926 }
927 ccdc_cfg.dev = &pdev->dev;
928 printk(KERN_NOTICE "%s is registered with vpfe.\n", ccdc_hw_dev.name);
5f15fbb6 929 return 0;
8d1b5946
MK		 930fail_sclk:
931 clk_put(ccdc_cfg.sclk);
932fail_mclk:
933 clk_put(ccdc_cfg.mclk);
934fail_nomap:
935 iounmap(ccdc_cfg.base_addr);
936fail_nomem:
937 release_mem_region(res->start, resource_size(res));
938fail_nores:
939 vpfe_unregister_ccdc_device(&ccdc_hw_dev);
940 return status;
5f15fbb6
MK		 941}
942
8d1b5946 943static int dm644x_ccdc_remove(struct platform_device *pdev)
5f15fbb6 944{
8d1b5946
MK		 945 struct resource *res;
946
947 clk_put(ccdc_cfg.mclk);
948 clk_put(ccdc_cfg.sclk);
949 iounmap(ccdc_cfg.base_addr);
950 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
951 if (res)
952 release_mem_region(res->start, resource_size(res));
5f15fbb6 953 vpfe_unregister_ccdc_device(&ccdc_hw_dev);
8d1b5946
MK		 954 return 0;
955}
956
957static struct platform_driver dm644x_ccdc_driver = {
958 .driver = {
959 .name = "dm644x_ccdc",
960 .owner = THIS_MODULE,
961 },
962 .remove = __devexit_p(dm644x_ccdc_remove),
963 .probe = dm644x_ccdc_probe,
964};
965
966static int __init dm644x_ccdc_init(void)
967{
968 return platform_driver_register(&dm644x_ccdc_driver);
969}
970
971static void __exit dm644x_ccdc_exit(void)
972{
973 platform_driver_unregister(&dm644x_ccdc_driver);
5f15fbb6
MK		 974}
975
976module_init(dm644x_ccdc_init);
977module_exit(dm644x_ccdc_exit);
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