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Commit | Line | Data |
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a6c2ba28 | 1 | /* |
3acf2809 | 2 | em28xx-core.c - driver for Empia EM2800/EM2820/2840 USB video capture devices |
a6c2ba28 | 3 | |
f7abcd38 MCC |
4 | Copyright (C) 2005 Ludovico Cavedon <cavedon@sssup.it> |
5 | Markus Rechberger <mrechberger@gmail.com> | |
2e7c6dc3 | 6 | Mauro Carvalho Chehab <mchehab@infradead.org> |
f7abcd38 | 7 | Sascha Sommer <saschasommer@freenet.de> |
a6c2ba28 | 8 | |
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
22 | */ | |
23 | ||
24 | #include <linux/init.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/module.h> | |
a6c2ba28 | 27 | #include <linux/usb.h> |
28 | #include <linux/vmalloc.h> | |
29 | ||
f7abcd38 | 30 | #include "em28xx.h" |
a6c2ba28 | 31 | |
32 | /* #define ENABLE_DEBUG_ISOC_FRAMES */ | |
33 | ||
ff699e6b | 34 | static unsigned int core_debug; |
a6c2ba28 | 35 | module_param(core_debug,int,0644); |
36 | MODULE_PARM_DESC(core_debug,"enable debug messages [core]"); | |
37 | ||
3acf2809 | 38 | #define em28xx_coredbg(fmt, arg...) do {\ |
4ac97914 MCC |
39 | if (core_debug) \ |
40 | printk(KERN_INFO "%s %s :"fmt, \ | |
d80e134d | 41 | dev->name, __func__ , ##arg); } while (0) |
a6c2ba28 | 42 | |
ff699e6b | 43 | static unsigned int reg_debug; |
a6c2ba28 | 44 | module_param(reg_debug,int,0644); |
45 | MODULE_PARM_DESC(reg_debug,"enable debug messages [URB reg]"); | |
46 | ||
3acf2809 | 47 | #define em28xx_regdbg(fmt, arg...) do {\ |
4ac97914 MCC |
48 | if (reg_debug) \ |
49 | printk(KERN_INFO "%s %s :"fmt, \ | |
d80e134d | 50 | dev->name, __func__ , ##arg); } while (0) |
a6c2ba28 | 51 | |
3acf2809 | 52 | static int alt = EM28XX_PINOUT; |
a6c2ba28 | 53 | module_param(alt, int, 0644); |
54 | MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint"); | |
55 | ||
579f72e4 AT |
56 | /* FIXME */ |
57 | #define em28xx_isocdbg(fmt, arg...) do {\ | |
58 | if (core_debug) \ | |
59 | printk(KERN_INFO "%s %s :"fmt, \ | |
60 | dev->name, __func__ , ##arg); } while (0) | |
61 | ||
a6c2ba28 | 62 | /* |
3acf2809 | 63 | * em28xx_read_reg_req() |
a6c2ba28 | 64 | * reads data from the usb device specifying bRequest |
65 | */ | |
3acf2809 | 66 | int em28xx_read_reg_req_len(struct em28xx *dev, u8 req, u16 reg, |
a6c2ba28 | 67 | char *buf, int len) |
68 | { | |
69 | int ret, byte; | |
70 | ||
9f38724a | 71 | if (dev->state & DEV_DISCONNECTED) |
c4a98793 MCC |
72 | return -ENODEV; |
73 | ||
74 | if (len > URB_MAX_CTRL_SIZE) | |
75 | return -EINVAL; | |
9f38724a | 76 | |
3acf2809 | 77 | em28xx_regdbg("req=%02x, reg=%02x ", req, reg); |
a6c2ba28 | 78 | |
f2a2e491 | 79 | mutex_lock(&dev->ctrl_urb_lock); |
a6c2ba28 | 80 | ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0), req, |
81 | USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, | |
c4a98793 MCC |
82 | 0x0000, reg, dev->urb_buf, len, HZ); |
83 | if (ret < 0) { | |
84 | if (reg_debug) | |
85 | printk(" failed!\n"); | |
f2a2e491 | 86 | mutex_unlock(&dev->ctrl_urb_lock); |
c4a98793 MCC |
87 | return ret; |
88 | } | |
89 | ||
90 | if (len) | |
91 | memcpy(buf, dev->urb_buf, len); | |
a6c2ba28 | 92 | |
f2a2e491 MCC |
93 | mutex_unlock(&dev->ctrl_urb_lock); |
94 | ||
6ea54d93 | 95 | if (reg_debug) { |
c4a98793 | 96 | printk("%02x values: ", ret); |
6ea54d93 | 97 | for (byte = 0; byte < len; byte++) |
82ac4f87 | 98 | printk(" %02x", (unsigned char)buf[byte]); |
82ac4f87 | 99 | printk("\n"); |
a6c2ba28 | 100 | } |
101 | ||
102 | return ret; | |
103 | } | |
104 | ||
105 | /* | |
3acf2809 | 106 | * em28xx_read_reg_req() |
a6c2ba28 | 107 | * reads data from the usb device specifying bRequest |
108 | */ | |
3acf2809 | 109 | int em28xx_read_reg_req(struct em28xx *dev, u8 req, u16 reg) |
a6c2ba28 | 110 | { |
111 | u8 val; | |
112 | int ret; | |
113 | ||
9f38724a MR |
114 | if (dev->state & DEV_DISCONNECTED) |
115 | return(-ENODEV); | |
116 | ||
3acf2809 | 117 | em28xx_regdbg("req=%02x, reg=%02x:", req, reg); |
a6c2ba28 | 118 | |
f2a2e491 | 119 | mutex_lock(&dev->ctrl_urb_lock); |
a6c2ba28 | 120 | ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0), req, |
121 | USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, | |
c4a98793 | 122 | 0x0000, reg, dev->urb_buf, 1, HZ); |
f2a2e491 MCC |
123 | val = dev->urb_buf[0]; |
124 | mutex_unlock(&dev->ctrl_urb_lock); | |
125 | ||
c4a98793 MCC |
126 | if (ret < 0) { |
127 | printk(" failed!\n"); | |
128 | return ret; | |
129 | } | |
a6c2ba28 | 130 | |
c4a98793 MCC |
131 | if (reg_debug) |
132 | printk("%02x\n", (unsigned char) val); | |
a6c2ba28 | 133 | |
134 | return val; | |
135 | } | |
136 | ||
3acf2809 | 137 | int em28xx_read_reg(struct em28xx *dev, u16 reg) |
a6c2ba28 | 138 | { |
3acf2809 | 139 | return em28xx_read_reg_req(dev, USB_REQ_GET_STATUS, reg); |
a6c2ba28 | 140 | } |
141 | ||
142 | /* | |
3acf2809 | 143 | * em28xx_write_regs_req() |
a6c2ba28 | 144 | * sends data to the usb device, specifying bRequest |
145 | */ | |
3acf2809 | 146 | int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf, |
a6c2ba28 | 147 | int len) |
148 | { | |
149 | int ret; | |
150 | ||
9f38724a | 151 | if (dev->state & DEV_DISCONNECTED) |
c67ec53f MCC |
152 | return -ENODEV; |
153 | ||
c4a98793 | 154 | if ((len < 1) || (len > URB_MAX_CTRL_SIZE)) |
c67ec53f | 155 | return -EINVAL; |
9f38724a | 156 | |
3acf2809 | 157 | em28xx_regdbg("req=%02x reg=%02x:", req, reg); |
a6c2ba28 | 158 | if (reg_debug) { |
159 | int i; | |
160 | for (i = 0; i < len; ++i) | |
82ac4f87 MCC |
161 | printk(" %02x", (unsigned char)buf[i]); |
162 | printk("\n"); | |
a6c2ba28 | 163 | } |
164 | ||
f2a2e491 | 165 | mutex_lock(&dev->ctrl_urb_lock); |
c4a98793 | 166 | memcpy(dev->urb_buf, buf, len); |
a6c2ba28 | 167 | ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0), req, |
168 | USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, | |
c4a98793 | 169 | 0x0000, reg, dev->urb_buf, len, HZ); |
f2a2e491 | 170 | mutex_unlock(&dev->ctrl_urb_lock); |
c4a98793 | 171 | |
89b329ef MCC |
172 | if (dev->wait_after_write) |
173 | msleep(dev->wait_after_write); | |
174 | ||
a6c2ba28 | 175 | return ret; |
176 | } | |
177 | ||
3acf2809 | 178 | int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len) |
a6c2ba28 | 179 | { |
c67ec53f MCC |
180 | int rc; |
181 | ||
182 | rc = em28xx_write_regs_req(dev, USB_REQ_GET_STATUS, reg, buf, len); | |
183 | ||
184 | /* Stores GPO/GPIO values at the cache, if changed | |
185 | Only write values should be stored, since input on a GPIO | |
186 | register will return the input bits. | |
187 | Not sure what happens on reading GPO register. | |
188 | */ | |
189 | if (rc >= 0) { | |
190 | if (reg == EM2880_R04_GPO) | |
191 | dev->reg_gpo = buf[0]; | |
192 | else if (reg == EM28XX_R08_GPIO) | |
193 | dev->reg_gpio = buf[0]; | |
194 | } | |
195 | ||
196 | return rc; | |
a6c2ba28 | 197 | } |
198 | ||
199 | /* | |
3acf2809 | 200 | * em28xx_write_reg_bits() |
a6c2ba28 | 201 | * sets only some bits (specified by bitmask) of a register, by first reading |
202 | * the actual value | |
203 | */ | |
532fe652 | 204 | static int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val, |
a6c2ba28 | 205 | u8 bitmask) |
206 | { | |
207 | int oldval; | |
208 | u8 newval; | |
6ea54d93 | 209 | |
c67ec53f MCC |
210 | /* Uses cache for gpo/gpio registers */ |
211 | if (reg == EM2880_R04_GPO) | |
212 | oldval = dev->reg_gpo; | |
213 | else if (reg == EM28XX_R08_GPIO) | |
214 | oldval = dev->reg_gpio; | |
215 | else | |
216 | oldval = em28xx_read_reg(dev, reg); | |
6ea54d93 DSL |
217 | |
218 | if (oldval < 0) | |
a6c2ba28 | 219 | return oldval; |
6ea54d93 | 220 | |
a6c2ba28 | 221 | newval = (((u8) oldval) & ~bitmask) | (val & bitmask); |
c67ec53f | 222 | |
3acf2809 | 223 | return em28xx_write_regs(dev, reg, &newval, 1); |
a6c2ba28 | 224 | } |
225 | ||
226 | /* | |
3acf2809 | 227 | * em28xx_write_ac97() |
a6c2ba28 | 228 | * write a 16 bit value to the specified AC97 address (LSB first!) |
229 | */ | |
539c96d0 | 230 | static int em28xx_write_ac97(struct em28xx *dev, u8 reg, u8 *val) |
a6c2ba28 | 231 | { |
00b8730f | 232 | int ret, i; |
a6c2ba28 | 233 | u8 addr = reg & 0x7f; |
6ea54d93 | 234 | |
41facaa4 | 235 | ret = em28xx_write_regs(dev, EM28XX_R40_AC97LSB, val, 2); |
6ea54d93 | 236 | if (ret < 0) |
a6c2ba28 | 237 | return ret; |
6ea54d93 | 238 | |
41facaa4 | 239 | ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1); |
6ea54d93 | 240 | if (ret < 0) |
a6c2ba28 | 241 | return ret; |
00b8730f MCC |
242 | |
243 | /* Wait up to 50 ms for AC97 command to complete */ | |
244 | for (i = 0; i < 10; i++) { | |
41facaa4 | 245 | ret = em28xx_read_reg(dev, EM28XX_R43_AC97BUSY); |
6ea54d93 | 246 | if (ret < 0) |
00b8730f | 247 | return ret; |
6ea54d93 | 248 | |
46cb57e6 | 249 | if (!(ret & 0x01)) |
00b8730f MCC |
250 | return 0; |
251 | msleep(5); | |
a6c2ba28 | 252 | } |
6ea54d93 | 253 | em28xx_warn("AC97 command still being executed: not handled properly!\n"); |
a6c2ba28 | 254 | return 0; |
255 | } | |
256 | ||
00b8730f | 257 | static int em28xx_set_audio_source(struct em28xx *dev) |
539c96d0 MCC |
258 | { |
259 | static char *enable = "\x08\x08"; | |
260 | static char *disable = "\x08\x88"; | |
261 | char *video = enable, *line = disable; | |
1685a6fe | 262 | int ret; |
539c96d0 MCC |
263 | u8 input; |
264 | ||
265 | if (dev->is_em2800) { | |
266 | if (dev->ctl_ainput) | |
267 | input = EM2800_AUDIO_SRC_LINE; | |
268 | else | |
269 | input = EM2800_AUDIO_SRC_TUNER; | |
270 | ||
41facaa4 | 271 | ret = em28xx_write_regs(dev, EM2800_R08_AUDIOSRC, &input, 1); |
539c96d0 MCC |
272 | if (ret < 0) |
273 | return ret; | |
274 | } | |
275 | ||
276 | if (dev->has_msp34xx) | |
277 | input = EM28XX_AUDIO_SRC_TUNER; | |
278 | else { | |
279 | switch (dev->ctl_ainput) { | |
280 | case EM28XX_AMUX_VIDEO: | |
281 | input = EM28XX_AUDIO_SRC_TUNER; | |
539c96d0 MCC |
282 | break; |
283 | case EM28XX_AMUX_LINE_IN: | |
284 | input = EM28XX_AUDIO_SRC_LINE; | |
3f9b46c1 DH |
285 | video = disable; |
286 | line = enable; | |
539c96d0 MCC |
287 | break; |
288 | case EM28XX_AMUX_AC97_VIDEO: | |
289 | input = EM28XX_AUDIO_SRC_LINE; | |
290 | break; | |
291 | case EM28XX_AMUX_AC97_LINE_IN: | |
292 | input = EM28XX_AUDIO_SRC_LINE; | |
293 | video = disable; | |
294 | line = enable; | |
295 | break; | |
296 | } | |
297 | } | |
298 | ||
41facaa4 | 299 | ret = em28xx_write_reg_bits(dev, EM28XX_R0E_AUDIOSRC, input, 0xc0); |
539c96d0 MCC |
300 | if (ret < 0) |
301 | return ret; | |
00b8730f | 302 | msleep(5); |
539c96d0 | 303 | |
7463dda2 MCC |
304 | /* Sets AC97 mixer registers |
305 | This is seems to be needed, even for non-ac97 configs | |
306 | */ | |
41facaa4 | 307 | ret = em28xx_write_ac97(dev, EM28XX_R14_VIDEO_AC97, video); |
539c96d0 MCC |
308 | if (ret < 0) |
309 | return ret; | |
310 | ||
41facaa4 | 311 | ret = em28xx_write_ac97(dev, EM28XX_R10_LINE_IN_AC97, line); |
539c96d0 MCC |
312 | |
313 | return ret; | |
314 | } | |
315 | ||
3acf2809 | 316 | int em28xx_audio_analog_set(struct em28xx *dev) |
a6c2ba28 | 317 | { |
539c96d0 | 318 | int ret; |
a6c2ba28 | 319 | char s[2] = { 0x00, 0x00 }; |
3abee53e | 320 | u8 xclk = 0x07; |
539c96d0 | 321 | |
a6c2ba28 | 322 | s[0] |= 0x1f - dev->volume; |
323 | s[1] |= 0x1f - dev->volume; | |
539c96d0 | 324 | |
00b8730f MCC |
325 | /* Mute */ |
326 | s[1] |= 0x80; | |
41facaa4 | 327 | ret = em28xx_write_ac97(dev, EM28XX_R02_MASTER_AC97, s); |
00b8730f | 328 | |
539c96d0 MCC |
329 | if (ret < 0) |
330 | return ret; | |
331 | ||
3abee53e MCC |
332 | if (dev->has_12mhz_i2s) |
333 | xclk |= 0x20; | |
334 | ||
335 | if (!dev->mute) | |
336 | xclk |= 0x80; | |
337 | ||
41facaa4 | 338 | ret = em28xx_write_reg_bits(dev, EM28XX_R0F_XCLK, xclk, 0xa7); |
539c96d0 MCC |
339 | if (ret < 0) |
340 | return ret; | |
3abee53e | 341 | msleep(10); |
539c96d0 MCC |
342 | |
343 | /* Selects the proper audio input */ | |
344 | ret = em28xx_set_audio_source(dev); | |
a6c2ba28 | 345 | |
00b8730f MCC |
346 | /* Unmute device */ |
347 | if (!dev->mute) | |
348 | s[1] &= ~0x80; | |
41facaa4 | 349 | ret = em28xx_write_ac97(dev, EM28XX_R02_MASTER_AC97, s); |
00b8730f | 350 | |
539c96d0 MCC |
351 | return ret; |
352 | } | |
353 | EXPORT_SYMBOL_GPL(em28xx_audio_analog_set); | |
a6c2ba28 | 354 | |
3acf2809 | 355 | int em28xx_colorlevels_set_default(struct em28xx *dev) |
a6c2ba28 | 356 | { |
41facaa4 MCC |
357 | em28xx_write_regs(dev, EM28XX_R20_YGAIN, "\x10", 1); /* contrast */ |
358 | em28xx_write_regs(dev, EM28XX_R21_YOFFSET, "\x00", 1); /* brightness */ | |
359 | em28xx_write_regs(dev, EM28XX_R22_UVGAIN, "\x10", 1); /* saturation */ | |
360 | em28xx_write_regs(dev, EM28XX_R23_UOFFSET, "\x00", 1); | |
361 | em28xx_write_regs(dev, EM28XX_R24_VOFFSET, "\x00", 1); | |
362 | em28xx_write_regs(dev, EM28XX_R25_SHARPNESS, "\x00", 1); | |
363 | ||
364 | em28xx_write_regs(dev, EM28XX_R14_GAMMA, "\x20", 1); | |
365 | em28xx_write_regs(dev, EM28XX_R15_RGAIN, "\x20", 1); | |
366 | em28xx_write_regs(dev, EM28XX_R16_GGAIN, "\x20", 1); | |
367 | em28xx_write_regs(dev, EM28XX_R17_BGAIN, "\x20", 1); | |
368 | em28xx_write_regs(dev, EM28XX_R18_ROFFSET, "\x00", 1); | |
369 | em28xx_write_regs(dev, EM28XX_R19_GOFFSET, "\x00", 1); | |
370 | return em28xx_write_regs(dev, EM28XX_R1A_BOFFSET, "\x00", 1); | |
a6c2ba28 | 371 | } |
372 | ||
3acf2809 | 373 | int em28xx_capture_start(struct em28xx *dev, int start) |
a6c2ba28 | 374 | { |
ee6e3a86 | 375 | int rc; |
a6c2ba28 | 376 | /* FIXME: which is the best order? */ |
377 | /* video registers are sampled by VREF */ | |
41facaa4 | 378 | rc = em28xx_write_reg_bits(dev, EM28XX_R0C_USBSUSP, |
ee6e3a86 MCC |
379 | start ? 0x10 : 0x00, 0x10); |
380 | if (rc < 0) | |
381 | return rc; | |
382 | ||
383 | if (!start) { | |
384 | /* disable video capture */ | |
41facaa4 | 385 | rc = em28xx_write_regs(dev, EM28XX_R12_VINENABLE, "\x27", 1); |
102a0b08 | 386 | return rc; |
ee6e3a86 MCC |
387 | } |
388 | ||
a6c2ba28 | 389 | /* enable video capture */ |
ee6e3a86 | 390 | rc = em28xx_write_regs_req(dev, 0x00, 0x48, "\x00", 1); |
102a0b08 | 391 | |
ee6e3a86 | 392 | if (dev->mode == EM28XX_ANALOG_MODE) |
41facaa4 | 393 | rc = em28xx_write_regs(dev, EM28XX_R12_VINENABLE, "\x67", 1); |
ee6e3a86 | 394 | else |
41facaa4 | 395 | rc = em28xx_write_regs(dev, EM28XX_R12_VINENABLE, "\x37", 1); |
ee6e3a86 | 396 | |
6ea54d93 | 397 | msleep(6); |
ee6e3a86 MCC |
398 | |
399 | return rc; | |
a6c2ba28 | 400 | } |
401 | ||
3acf2809 | 402 | int em28xx_outfmt_set_yuv422(struct em28xx *dev) |
a6c2ba28 | 403 | { |
41facaa4 MCC |
404 | em28xx_write_regs(dev, EM28XX_R27_OUTFMT, "\x34", 1); |
405 | em28xx_write_regs(dev, EM28XX_R10_VINMODE, "\x10", 1); | |
406 | return em28xx_write_regs(dev, EM28XX_R11_VINCTRL, "\x11", 1); | |
a6c2ba28 | 407 | } |
408 | ||
adcb0fa2 AB |
409 | static int em28xx_accumulator_set(struct em28xx *dev, u8 xmin, u8 xmax, |
410 | u8 ymin, u8 ymax) | |
a6c2ba28 | 411 | { |
6ea54d93 DSL |
412 | em28xx_coredbg("em28xx Scale: (%d,%d)-(%d,%d)\n", |
413 | xmin, ymin, xmax, ymax); | |
a6c2ba28 | 414 | |
41facaa4 MCC |
415 | em28xx_write_regs(dev, EM28XX_R28_XMIN, &xmin, 1); |
416 | em28xx_write_regs(dev, EM28XX_R29_XMAX, &xmax, 1); | |
417 | em28xx_write_regs(dev, EM28XX_R2A_YMIN, &ymin, 1); | |
418 | return em28xx_write_regs(dev, EM28XX_R2B_YMAX, &ymax, 1); | |
a6c2ba28 | 419 | } |
420 | ||
adcb0fa2 | 421 | static int em28xx_capture_area_set(struct em28xx *dev, u8 hstart, u8 vstart, |
a6c2ba28 | 422 | u16 width, u16 height) |
423 | { | |
424 | u8 cwidth = width; | |
425 | u8 cheight = height; | |
426 | u8 overflow = (height >> 7 & 0x02) | (width >> 8 & 0x01); | |
427 | ||
6ea54d93 DSL |
428 | em28xx_coredbg("em28xx Area Set: (%d,%d)\n", |
429 | (width | (overflow & 2) << 7), | |
a6c2ba28 | 430 | (height | (overflow & 1) << 8)); |
431 | ||
41facaa4 MCC |
432 | em28xx_write_regs(dev, EM28XX_R1C_HSTART, &hstart, 1); |
433 | em28xx_write_regs(dev, EM28XX_R1D_VSTART, &vstart, 1); | |
434 | em28xx_write_regs(dev, EM28XX_R1E_CWIDTH, &cwidth, 1); | |
435 | em28xx_write_regs(dev, EM28XX_R1F_CHEIGHT, &cheight, 1); | |
436 | return em28xx_write_regs(dev, EM28XX_R1B_OFLOW, &overflow, 1); | |
a6c2ba28 | 437 | } |
438 | ||
adcb0fa2 | 439 | static int em28xx_scaler_set(struct em28xx *dev, u16 h, u16 v) |
a6c2ba28 | 440 | { |
52c02fcd SS |
441 | u8 mode; |
442 | /* the em2800 scaler only supports scaling down to 50% */ | |
6ea54d93 | 443 | if (dev->is_em2800) |
52c02fcd SS |
444 | mode = (v ? 0x20 : 0x00) | (h ? 0x10 : 0x00); |
445 | else { | |
446 | u8 buf[2]; | |
447 | buf[0] = h; | |
448 | buf[1] = h >> 8; | |
41facaa4 | 449 | em28xx_write_regs(dev, EM28XX_R30_HSCALELOW, (char *)buf, 2); |
52c02fcd SS |
450 | buf[0] = v; |
451 | buf[1] = v >> 8; | |
41facaa4 | 452 | em28xx_write_regs(dev, EM28XX_R32_VSCALELOW, (char *)buf, 2); |
6ea54d93 DSL |
453 | /* it seems that both H and V scalers must be active |
454 | to work correctly */ | |
52c02fcd | 455 | mode = (h || v)? 0x30: 0x00; |
74458e6c | 456 | } |
41facaa4 | 457 | return em28xx_write_reg_bits(dev, EM28XX_R26_COMPR, mode, 0x30); |
a6c2ba28 | 458 | } |
459 | ||
460 | /* FIXME: this only function read values from dev */ | |
3acf2809 | 461 | int em28xx_resolution_set(struct em28xx *dev) |
a6c2ba28 | 462 | { |
463 | int width, height; | |
464 | width = norm_maxw(dev); | |
465 | height = norm_maxh(dev) >> 1; | |
466 | ||
3acf2809 MCC |
467 | em28xx_outfmt_set_yuv422(dev); |
468 | em28xx_accumulator_set(dev, 1, (width - 4) >> 2, 1, (height - 4) >> 2); | |
469 | em28xx_capture_area_set(dev, 0, 0, width >> 2, height >> 2); | |
470 | return em28xx_scaler_set(dev, dev->hscale, dev->vscale); | |
a6c2ba28 | 471 | } |
472 | ||
3acf2809 | 473 | int em28xx_set_alternate(struct em28xx *dev) |
a6c2ba28 | 474 | { |
475 | int errCode, prev_alt = dev->alt; | |
3687e1e6 | 476 | int i; |
44dc733c | 477 | unsigned int min_pkt_size = dev->width * 2 + 4; |
3687e1e6 | 478 | |
2c4a07b2 | 479 | /* When image size is bigger than a certain value, |
3687e1e6 MCC |
480 | the frame size should be increased, otherwise, only |
481 | green screen will be received. | |
482 | */ | |
44dc733c | 483 | if (dev->width * 2 * dev->height > 720 * 240 * 2) |
3687e1e6 MCC |
484 | min_pkt_size *= 2; |
485 | ||
2c4a07b2 SS |
486 | for (i = 0; i < dev->num_alt; i++) { |
487 | /* stop when the selected alt setting offers enough bandwidth */ | |
488 | if (dev->alt_max_pkt_size[i] >= min_pkt_size) { | |
489 | dev->alt = i; | |
3687e1e6 | 490 | break; |
2c4a07b2 SS |
491 | /* otherwise make sure that we end up with the maximum bandwidth |
492 | because the min_pkt_size equation might be wrong... | |
493 | */ | |
494 | } else if (dev->alt_max_pkt_size[i] > | |
495 | dev->alt_max_pkt_size[dev->alt]) | |
496 | dev->alt = i; | |
497 | } | |
a6c2ba28 | 498 | |
499 | if (dev->alt != prev_alt) { | |
3687e1e6 MCC |
500 | em28xx_coredbg("minimum isoc packet size: %u (alt=%d)\n", |
501 | min_pkt_size, dev->alt); | |
a6c2ba28 | 502 | dev->max_pkt_size = dev->alt_max_pkt_size[dev->alt]; |
3687e1e6 MCC |
503 | em28xx_coredbg("setting alternate %d with wMaxPacketSize=%u\n", |
504 | dev->alt, dev->max_pkt_size); | |
a6c2ba28 | 505 | errCode = usb_set_interface(dev->udev, 0, dev->alt); |
506 | if (errCode < 0) { | |
6ea54d93 | 507 | em28xx_errdev("cannot change alternate number to %d (error=%i)\n", |
3687e1e6 | 508 | dev->alt, errCode); |
a6c2ba28 | 509 | return errCode; |
510 | } | |
511 | } | |
512 | return 0; | |
513 | } | |
579f72e4 | 514 | |
c67ec53f MCC |
515 | int em28xx_gpio_set(struct em28xx *dev, struct em28xx_reg_seq *gpio) |
516 | { | |
517 | int rc = 0; | |
518 | ||
519 | if (!gpio) | |
520 | return rc; | |
521 | ||
522 | dev->em28xx_write_regs_req(dev, 0x00, 0x48, "\x00", 1); | |
523 | if (dev->mode == EM28XX_ANALOG_MODE) | |
524 | dev->em28xx_write_regs_req(dev, 0x00, 0x12, "\x67", 1); | |
525 | else | |
526 | dev->em28xx_write_regs_req(dev, 0x00, 0x12, "\x37", 1); | |
527 | msleep(6); | |
528 | ||
529 | /* Send GPIO reset sequences specified at board entry */ | |
530 | while (gpio->sleep >= 0) { | |
531 | if (gpio->reg >= 0) { | |
532 | rc = em28xx_write_reg_bits(dev, | |
533 | gpio->reg, | |
534 | gpio->val, | |
535 | gpio->mask); | |
536 | if (rc < 0) | |
537 | return rc; | |
538 | } | |
539 | if (gpio->sleep > 0) | |
540 | msleep(gpio->sleep); | |
541 | ||
542 | gpio++; | |
543 | } | |
544 | return rc; | |
545 | } | |
546 | ||
547 | int em28xx_set_mode(struct em28xx *dev, enum em28xx_mode set_mode) | |
548 | { | |
549 | if (dev->mode == set_mode) | |
550 | return 0; | |
551 | ||
552 | if (set_mode == EM28XX_MODE_UNDEFINED) { | |
553 | dev->mode = set_mode; | |
554 | return 0; | |
555 | } | |
556 | ||
557 | dev->mode = set_mode; | |
558 | ||
559 | if (dev->mode == EM28XX_DIGITAL_MODE) | |
560 | return em28xx_gpio_set(dev, dev->digital_gpio); | |
561 | else | |
562 | return em28xx_gpio_set(dev, dev->analog_gpio); | |
563 | } | |
564 | EXPORT_SYMBOL_GPL(em28xx_set_mode); | |
565 | ||
579f72e4 AT |
566 | /* ------------------------------------------------------------------ |
567 | URB control | |
568 | ------------------------------------------------------------------*/ | |
569 | ||
570 | /* | |
571 | * IRQ callback, called by URB callback | |
572 | */ | |
573 | static void em28xx_irq_callback(struct urb *urb) | |
574 | { | |
575 | struct em28xx_dmaqueue *dma_q = urb->context; | |
576 | struct em28xx *dev = container_of(dma_q, struct em28xx, vidq); | |
577 | int rc, i; | |
578 | ||
579 | /* Copy data from URB */ | |
580 | spin_lock(&dev->slock); | |
581 | rc = dev->isoc_ctl.isoc_copy(dev, urb); | |
582 | spin_unlock(&dev->slock); | |
583 | ||
584 | /* Reset urb buffers */ | |
585 | for (i = 0; i < urb->number_of_packets; i++) { | |
586 | urb->iso_frame_desc[i].status = 0; | |
587 | urb->iso_frame_desc[i].actual_length = 0; | |
588 | } | |
589 | urb->status = 0; | |
590 | ||
591 | urb->status = usb_submit_urb(urb, GFP_ATOMIC); | |
592 | if (urb->status) { | |
4269a8ee DH |
593 | em28xx_isocdbg("urb resubmit failed (error=%i)\n", |
594 | urb->status); | |
579f72e4 AT |
595 | } |
596 | } | |
597 | ||
598 | /* | |
599 | * Stop and Deallocate URBs | |
600 | */ | |
601 | void em28xx_uninit_isoc(struct em28xx *dev) | |
602 | { | |
603 | struct urb *urb; | |
604 | int i; | |
605 | ||
606 | em28xx_isocdbg("em28xx: called em28xx_uninit_isoc\n"); | |
607 | ||
608 | dev->isoc_ctl.nfields = -1; | |
609 | for (i = 0; i < dev->isoc_ctl.num_bufs; i++) { | |
610 | urb = dev->isoc_ctl.urb[i]; | |
611 | if (urb) { | |
612 | usb_kill_urb(urb); | |
613 | usb_unlink_urb(urb); | |
614 | if (dev->isoc_ctl.transfer_buffer[i]) { | |
615 | usb_buffer_free(dev->udev, | |
6ea54d93 DSL |
616 | urb->transfer_buffer_length, |
617 | dev->isoc_ctl.transfer_buffer[i], | |
618 | urb->transfer_dma); | |
579f72e4 AT |
619 | } |
620 | usb_free_urb(urb); | |
621 | dev->isoc_ctl.urb[i] = NULL; | |
622 | } | |
623 | dev->isoc_ctl.transfer_buffer[i] = NULL; | |
624 | } | |
625 | ||
626 | kfree(dev->isoc_ctl.urb); | |
627 | kfree(dev->isoc_ctl.transfer_buffer); | |
628 | ||
629 | dev->isoc_ctl.urb = NULL; | |
630 | dev->isoc_ctl.transfer_buffer = NULL; | |
631 | dev->isoc_ctl.num_bufs = 0; | |
632 | ||
633 | em28xx_capture_start(dev, 0); | |
634 | } | |
635 | EXPORT_SYMBOL_GPL(em28xx_uninit_isoc); | |
636 | ||
637 | /* | |
638 | * Allocate URBs and start IRQ | |
639 | */ | |
640 | int em28xx_init_isoc(struct em28xx *dev, int max_packets, | |
641 | int num_bufs, int max_pkt_size, | |
c67ec53f | 642 | int (*isoc_copy) (struct em28xx *dev, struct urb *urb)) |
579f72e4 AT |
643 | { |
644 | struct em28xx_dmaqueue *dma_q = &dev->vidq; | |
645 | int i; | |
646 | int sb_size, pipe; | |
647 | struct urb *urb; | |
648 | int j, k; | |
649 | int rc; | |
650 | ||
651 | em28xx_isocdbg("em28xx: called em28xx_prepare_isoc\n"); | |
652 | ||
653 | /* De-allocates all pending stuff */ | |
654 | em28xx_uninit_isoc(dev); | |
655 | ||
656 | dev->isoc_ctl.isoc_copy = isoc_copy; | |
657 | dev->isoc_ctl.num_bufs = num_bufs; | |
658 | ||
659 | dev->isoc_ctl.urb = kzalloc(sizeof(void *)*num_bufs, GFP_KERNEL); | |
660 | if (!dev->isoc_ctl.urb) { | |
661 | em28xx_errdev("cannot alloc memory for usb buffers\n"); | |
662 | return -ENOMEM; | |
663 | } | |
664 | ||
665 | dev->isoc_ctl.transfer_buffer = kzalloc(sizeof(void *)*num_bufs, | |
666 | GFP_KERNEL); | |
094f9b4b | 667 | if (!dev->isoc_ctl.transfer_buffer) { |
579f72e4 AT |
668 | em28xx_errdev("cannot allocate memory for usbtransfer\n"); |
669 | kfree(dev->isoc_ctl.urb); | |
670 | return -ENOMEM; | |
671 | } | |
672 | ||
673 | dev->isoc_ctl.max_pkt_size = max_pkt_size; | |
674 | dev->isoc_ctl.buf = NULL; | |
675 | ||
676 | sb_size = max_packets * dev->isoc_ctl.max_pkt_size; | |
677 | ||
678 | /* allocate urbs and transfer buffers */ | |
679 | for (i = 0; i < dev->isoc_ctl.num_bufs; i++) { | |
680 | urb = usb_alloc_urb(max_packets, GFP_KERNEL); | |
681 | if (!urb) { | |
682 | em28xx_err("cannot alloc isoc_ctl.urb %i\n", i); | |
683 | em28xx_uninit_isoc(dev); | |
684 | return -ENOMEM; | |
685 | } | |
686 | dev->isoc_ctl.urb[i] = urb; | |
687 | ||
688 | dev->isoc_ctl.transfer_buffer[i] = usb_buffer_alloc(dev->udev, | |
689 | sb_size, GFP_KERNEL, &urb->transfer_dma); | |
690 | if (!dev->isoc_ctl.transfer_buffer[i]) { | |
691 | em28xx_err("unable to allocate %i bytes for transfer" | |
692 | " buffer %i%s\n", | |
693 | sb_size, i, | |
694 | in_interrupt()?" while in int":""); | |
695 | em28xx_uninit_isoc(dev); | |
696 | return -ENOMEM; | |
697 | } | |
698 | memset(dev->isoc_ctl.transfer_buffer[i], 0, sb_size); | |
699 | ||
700 | /* FIXME: this is a hack - should be | |
701 | 'desc.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK' | |
702 | should also be using 'desc.bInterval' | |
703 | */ | |
6ea54d93 | 704 | pipe = usb_rcvisocpipe(dev->udev, |
c67ec53f | 705 | dev->mode == EM28XX_ANALOG_MODE ? 0x82 : 0x84); |
6ea54d93 | 706 | |
579f72e4 AT |
707 | usb_fill_int_urb(urb, dev->udev, pipe, |
708 | dev->isoc_ctl.transfer_buffer[i], sb_size, | |
709 | em28xx_irq_callback, dma_q, 1); | |
710 | ||
711 | urb->number_of_packets = max_packets; | |
712 | urb->transfer_flags = URB_ISO_ASAP; | |
713 | ||
714 | k = 0; | |
715 | for (j = 0; j < max_packets; j++) { | |
716 | urb->iso_frame_desc[j].offset = k; | |
717 | urb->iso_frame_desc[j].length = | |
718 | dev->isoc_ctl.max_pkt_size; | |
719 | k += dev->isoc_ctl.max_pkt_size; | |
720 | } | |
721 | } | |
722 | ||
723 | init_waitqueue_head(&dma_q->wq); | |
724 | ||
c67ec53f | 725 | em28xx_capture_start(dev, 1); |
579f72e4 AT |
726 | |
727 | /* submit urbs and enables IRQ */ | |
728 | for (i = 0; i < dev->isoc_ctl.num_bufs; i++) { | |
729 | rc = usb_submit_urb(dev->isoc_ctl.urb[i], GFP_ATOMIC); | |
730 | if (rc) { | |
731 | em28xx_err("submit of urb %i failed (error=%i)\n", i, | |
732 | rc); | |
733 | em28xx_uninit_isoc(dev); | |
734 | return rc; | |
735 | } | |
736 | } | |
737 | ||
738 | return 0; | |
739 | } | |
740 | EXPORT_SYMBOL_GPL(em28xx_init_isoc); |