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[media] b2c2: fix driver's build due to the lack of pci DMA code
[mirror_ubuntu-artful-kernel.git] / drivers / media / video / em28xx / em28xx-core.c
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a6c2ba28 1/*
3acf2809 2 em28xx-core.c - driver for Empia EM2800/EM2820/2840 USB video capture devices
a6c2ba28 3
f7abcd38
MCC		 4 Copyright (C) 2005 Ludovico Cavedon <cavedon@sssup.it>
5 Markus Rechberger <mrechberger@gmail.com>
2e7c6dc3 6 Mauro Carvalho Chehab <mchehab@infradead.org>
f7abcd38 7 Sascha Sommer <saschasommer@freenet.de>
a6c2ba28 8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#include <linux/init.h>
25#include <linux/list.h>
26#include <linux/module.h>
5a0e3ad6 27#include <linux/slab.h>
a6c2ba28 28#include <linux/usb.h>
29#include <linux/vmalloc.h>
67b8d033 30#include <sound/ac97_codec.h>
1a23f81b 31#include <media/v4l2-common.h>
a6c2ba28 32
f7abcd38 33#include "em28xx.h"
a6c2ba28 34
35/* #define ENABLE_DEBUG_ISOC_FRAMES */
36
ff699e6b 37static unsigned int core_debug;
a1a6ee74
NS		 38module_param(core_debug, int, 0644);
39MODULE_PARM_DESC(core_debug, "enable debug messages [core]");
a6c2ba28 40
3acf2809 41#define em28xx_coredbg(fmt, arg...) do {\
4ac97914
MCC		 42 if (core_debug) \
43 printk(KERN_INFO "%s %s :"fmt, \
d80e134d 44 dev->name, __func__ , ##arg); } while (0)
a6c2ba28 45
ff699e6b 46static unsigned int reg_debug;
a1a6ee74
NS		 47module_param(reg_debug, int, 0644);
48MODULE_PARM_DESC(reg_debug, "enable debug messages [URB reg]");
a6c2ba28 49
3acf2809 50#define em28xx_regdbg(fmt, arg...) do {\
4ac97914
MCC		 51 if (reg_debug) \
52 printk(KERN_INFO "%s %s :"fmt, \
d80e134d 53 dev->name, __func__ , ##arg); } while (0)
a6c2ba28 54
fc099f0e 55static int alt;
a6c2ba28 56module_param(alt, int, 0644);
57MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint");
58
da52a55c
DH		 59static unsigned int disable_vbi;
60module_param(disable_vbi, int, 0644);
61MODULE_PARM_DESC(disable_vbi, "disable vbi support");
62
579f72e4
AT		 63/* FIXME */
64#define em28xx_isocdbg(fmt, arg...) do {\
65 if (core_debug) \
66 printk(KERN_INFO "%s %s :"fmt, \
67 dev->name, __func__ , ##arg); } while (0)
68
a6c2ba28 69/*
3acf2809 70 * em28xx_read_reg_req()
a6c2ba28 71 * reads data from the usb device specifying bRequest
72 */
3acf2809 73int em28xx_read_reg_req_len(struct em28xx *dev, u8 req, u16 reg,
a6c2ba28 74 char *buf, int len)
75{
9e5d6760
MCC		 76 int ret;
77 int pipe = usb_rcvctrlpipe(dev->udev, 0);
a6c2ba28 78
9f38724a 79 if (dev->state & DEV_DISCONNECTED)
c4a98793
MCC		 80 return -ENODEV;
81
82 if (len > URB_MAX_CTRL_SIZE)
83 return -EINVAL;
9f38724a 84
9e5d6760 85 if (reg_debug) {
a1a6ee74 86 printk(KERN_DEBUG "(pipe 0x%08x): "
9e5d6760
MCC		 87 "IN: %02x %02x %02x %02x %02x %02x %02x %02x ",
88 pipe,
89 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
90 req, 0, 0,
91 reg & 0xff, reg >> 8,
92 len & 0xff, len >> 8);
93 }
a6c2ba28 94
f2a2e491 95 mutex_lock(&dev->ctrl_urb_lock);
9e5d6760 96 ret = usb_control_msg(dev->udev, pipe, req,
a6c2ba28 97 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
c4a98793
MCC		 98 0x0000, reg, dev->urb_buf, len, HZ);
99 if (ret < 0) {
100 if (reg_debug)
101 printk(" failed!\n");
f2a2e491 102 mutex_unlock(&dev->ctrl_urb_lock);
c4a98793
MCC		 103 return ret;
104 }
105
106 if (len)
107 memcpy(buf, dev->urb_buf, len);
a6c2ba28 108
f2a2e491
MCC		 109 mutex_unlock(&dev->ctrl_urb_lock);
110
6ea54d93 111 if (reg_debug) {
9e5d6760
MCC		 112 int byte;
113
114 printk("<<<");
6ea54d93 115 for (byte = 0; byte < len; byte++)
82ac4f87 116 printk(" %02x", (unsigned char)buf[byte]);
82ac4f87 117 printk("\n");
a6c2ba28 118 }
119
120 return ret;
121}
122
123/*
3acf2809 124 * em28xx_read_reg_req()
a6c2ba28 125 * reads data from the usb device specifying bRequest
126 */
3acf2809 127int em28xx_read_reg_req(struct em28xx *dev, u8 req, u16 reg)
a6c2ba28 128{
a6c2ba28 129 int ret;
9e5d6760 130 u8 val;
a6c2ba28 131
9e5d6760
MCC		 132 ret = em28xx_read_reg_req_len(dev, req, reg, &val, 1);
133 if (ret < 0)
c4a98793 134 return ret;
a6c2ba28 135
136 return val;
137}
138
3acf2809 139int em28xx_read_reg(struct em28xx *dev, u16 reg)
a6c2ba28 140{
3acf2809 141 return em28xx_read_reg_req(dev, USB_REQ_GET_STATUS, reg);
a6c2ba28 142}
37e65dce 143EXPORT_SYMBOL_GPL(em28xx_read_reg);
a6c2ba28 144
145/*
3acf2809 146 * em28xx_write_regs_req()
a6c2ba28 147 * sends data to the usb device, specifying bRequest
148 */
3acf2809 149int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf,
a6c2ba28 150 int len)
151{
152 int ret;
9e5d6760 153 int pipe = usb_sndctrlpipe(dev->udev, 0);
a6c2ba28 154
9f38724a 155 if (dev->state & DEV_DISCONNECTED)
c67ec53f
MCC		 156 return -ENODEV;
157
c4a98793 158 if ((len < 1) || (len > URB_MAX_CTRL_SIZE))
c67ec53f 159 return -EINVAL;
9f38724a 160
a6c2ba28 161 if (reg_debug) {
9e5d6760
MCC		 162 int byte;
163
a1a6ee74 164 printk(KERN_DEBUG "(pipe 0x%08x): "
9e5d6760
MCC		 165 "OUT: %02x %02x %02x %02x %02x %02x %02x %02x >>>",
166 pipe,
167 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
168 req, 0, 0,
169 reg & 0xff, reg >> 8,
170 len & 0xff, len >> 8);
171
172 for (byte = 0; byte < len; byte++)
173 printk(" %02x", (unsigned char)buf[byte]);
82ac4f87 174 printk("\n");
a6c2ba28 175 }
176
f2a2e491 177 mutex_lock(&dev->ctrl_urb_lock);
c4a98793 178 memcpy(dev->urb_buf, buf, len);
9e5d6760 179 ret = usb_control_msg(dev->udev, pipe, req,
a6c2ba28 180 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
c4a98793 181 0x0000, reg, dev->urb_buf, len, HZ);
f2a2e491 182 mutex_unlock(&dev->ctrl_urb_lock);
c4a98793 183
89b329ef
MCC		 184 if (dev->wait_after_write)
185 msleep(dev->wait_after_write);
186
a6c2ba28 187 return ret;
188}
189
3acf2809 190int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len)
a6c2ba28 191{
c67ec53f
MCC		 192 int rc;
193
194 rc = em28xx_write_regs_req(dev, USB_REQ_GET_STATUS, reg, buf, len);
195
196 /* Stores GPO/GPIO values at the cache, if changed
197 Only write values should be stored, since input on a GPIO
198 register will return the input bits.
199 Not sure what happens on reading GPO register.
200 */
201 if (rc >= 0) {
6a1acc3b 202 if (reg == dev->reg_gpo_num)
c67ec53f 203 dev->reg_gpo = buf[0];
6a1acc3b 204 else if (reg == dev->reg_gpio_num)
c67ec53f
MCC		 205 dev->reg_gpio = buf[0];
206 }
207
208 return rc;
a6c2ba28 209}
37e65dce 210EXPORT_SYMBOL_GPL(em28xx_write_regs);
a6c2ba28 211
b6972489
DH		 212/* Write a single register */
213int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val)
214{
215 return em28xx_write_regs(dev, reg, &val, 1);
216}
fec528b7 217EXPORT_SYMBOL_GPL(em28xx_write_reg);
b6972489 218
a6c2ba28 219/*
3acf2809 220 * em28xx_write_reg_bits()
a6c2ba28 221 * sets only some bits (specified by bitmask) of a register, by first reading
222 * the actual value
223 */
1bad429e 224int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val,
a6c2ba28 225 u8 bitmask)
226{
227 int oldval;
228 u8 newval;
6ea54d93 229
c67ec53f 230 /* Uses cache for gpo/gpio registers */
6a1acc3b 231 if (reg == dev->reg_gpo_num)
c67ec53f 232 oldval = dev->reg_gpo;
6a1acc3b 233 else if (reg == dev->reg_gpio_num)
c67ec53f
MCC		 234 oldval = dev->reg_gpio;
235 else
236 oldval = em28xx_read_reg(dev, reg);
6ea54d93
DSL		 237
238 if (oldval < 0)
a6c2ba28 239 return oldval;
6ea54d93 240
a6c2ba28 241 newval = (((u8) oldval) & ~bitmask) | (val & bitmask);
c67ec53f 242
3acf2809 243 return em28xx_write_regs(dev, reg, &newval, 1);
a6c2ba28 244}
37e65dce 245EXPORT_SYMBOL_GPL(em28xx_write_reg_bits);
a6c2ba28 246
35643943
MCC		 247/*
248 * em28xx_is_ac97_ready()
249 * Checks if ac97 is ready
250 */
251static int em28xx_is_ac97_ready(struct em28xx *dev)
252{
253 int ret, i;
254
255 /* Wait up to 50 ms for AC97 command to complete */
256 for (i = 0; i < 10; i++, msleep(5)) {
257 ret = em28xx_read_reg(dev, EM28XX_R43_AC97BUSY);
258 if (ret < 0)
259 return ret;
260
261 if (!(ret & 0x01))
262 return 0;
263 }
264
265 em28xx_warn("AC97 command still being executed: not handled properly!\n");
266 return -EBUSY;
267}
268
269/*
270 * em28xx_read_ac97()
271 * write a 16 bit value to the specified AC97 address (LSB first!)
272 */
531c98e7 273int em28xx_read_ac97(struct em28xx *dev, u8 reg)
35643943
MCC		 274{
275 int ret;
276 u8 addr = (reg & 0x7f) | 0x80;
277 u16 val;
278
279 ret = em28xx_is_ac97_ready(dev);
280 if (ret < 0)
281 return ret;
282
283 ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
284 if (ret < 0)
285 return ret;
286
287 ret = dev->em28xx_read_reg_req_len(dev, 0, EM28XX_R40_AC97LSB,
288 (u8 *)&val, sizeof(val));
289
290 if (ret < 0)
291 return ret;
292 return le16_to_cpu(val);
293}
850d24a5 294EXPORT_SYMBOL_GPL(em28xx_read_ac97);
35643943 295
a6c2ba28 296/*
3acf2809 297 * em28xx_write_ac97()
a6c2ba28 298 * write a 16 bit value to the specified AC97 address (LSB first!)
299 */
531c98e7 300int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val)
a6c2ba28 301{
35643943 302 int ret;
a6c2ba28 303 u8 addr = reg & 0x7f;
35643943
MCC		 304 __le16 value;
305
306 value = cpu_to_le16(val);
307
308 ret = em28xx_is_ac97_ready(dev);
309 if (ret < 0)
310 return ret;
6ea54d93 311
35643943 312 ret = em28xx_write_regs(dev, EM28XX_R40_AC97LSB, (u8 *) &value, 2);
6ea54d93 313 if (ret < 0)
a6c2ba28 314 return ret;
6ea54d93 315
41facaa4 316 ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
6ea54d93 317 if (ret < 0)
a6c2ba28 318 return ret;
00b8730f 319
35643943
MCC		 320 return 0;
321}
850d24a5 322EXPORT_SYMBOL_GPL(em28xx_write_ac97);
6ea54d93 323
0f8a61fc 324struct em28xx_vol_itable {
e879b8eb 325 enum em28xx_amux mux;
5faff789
MCC		 326 u8 reg;
327};
328
0f8a61fc 329static struct em28xx_vol_itable inputs[] = {
67b8d033
EG		 330 { EM28XX_AMUX_VIDEO, AC97_VIDEO },
331 { EM28XX_AMUX_LINE_IN, AC97_LINE },
332 { EM28XX_AMUX_PHONE, AC97_PHONE },
333 { EM28XX_AMUX_MIC, AC97_MIC },
334 { EM28XX_AMUX_CD, AC97_CD },
335 { EM28XX_AMUX_AUX, AC97_AUX },
336 { EM28XX_AMUX_PCM_OUT, AC97_PCM },
5faff789
MCC		 337};
338
339static int set_ac97_input(struct em28xx *dev)
35643943 340{
5faff789
MCC		 341 int ret, i;
342 enum em28xx_amux amux = dev->ctl_ainput;
35643943 343
5faff789
MCC		 344 /* EM28XX_AMUX_VIDEO2 is a special case used to indicate that
345 em28xx should point to LINE IN, while AC97 should use VIDEO
346 */
347 if (amux == EM28XX_AMUX_VIDEO2)
f1990a9c 348 amux = EM28XX_AMUX_VIDEO;
35643943 349
5faff789
MCC		 350 /* Mute all entres but the one that were selected */
351 for (i = 0; i < ARRAY_SIZE(inputs); i++) {
e879b8eb 352 if (amux == inputs[i].mux)
5faff789
MCC		 353 ret = em28xx_write_ac97(dev, inputs[i].reg, 0x0808);
354 else
355 ret = em28xx_write_ac97(dev, inputs[i].reg, 0x8000);
35643943 356
5faff789
MCC		 357 if (ret < 0)
358 em28xx_warn("couldn't setup AC97 register %d\n",
359 inputs[i].reg);
360 }
361 return 0;
a6c2ba28 362}
363
00b8730f 364static int em28xx_set_audio_source(struct em28xx *dev)
539c96d0 365{
1685a6fe 366 int ret;
539c96d0
MCC		 367 u8 input;
368
505b6d0b 369 if (dev->board.is_em2800) {
5faff789 370 if (dev->ctl_ainput == EM28XX_AMUX_VIDEO)
539c96d0 371 input = EM2800_AUDIO_SRC_TUNER;
5faff789
MCC		 372 else
373 input = EM2800_AUDIO_SRC_LINE;
539c96d0 374
41facaa4 375 ret = em28xx_write_regs(dev, EM2800_R08_AUDIOSRC, &input, 1);
539c96d0
MCC		 376 if (ret < 0)
377 return ret;
378 }
379
505b6d0b 380 if (dev->board.has_msp34xx)
539c96d0
MCC		 381 input = EM28XX_AUDIO_SRC_TUNER;
382 else {
383 switch (dev->ctl_ainput) {
384 case EM28XX_AMUX_VIDEO:
385 input = EM28XX_AUDIO_SRC_TUNER;
539c96d0 386 break;
35643943 387 default:
539c96d0 388 input = EM28XX_AUDIO_SRC_LINE;
539c96d0
MCC		 389 break;
390 }
391 }
392
2bd1d9eb
VW		 393 if (dev->board.mute_gpio && dev->mute)
394 em28xx_gpio_set(dev, dev->board.mute_gpio);
395 else
396 em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
397
41facaa4 398 ret = em28xx_write_reg_bits(dev, EM28XX_R0E_AUDIOSRC, input, 0xc0);
539c96d0
MCC		 399 if (ret < 0)
400 return ret;
00b8730f 401 msleep(5);
539c96d0 402
35643943
MCC		 403 switch (dev->audio_mode.ac97) {
404 case EM28XX_NO_AC97:
405 break;
5faff789
MCC		 406 default:
407 ret = set_ac97_input(dev);
35643943 408 }
539c96d0 409
5faff789 410 return ret;
539c96d0
MCC		 411}
412
0f8a61fc
MCC		 413struct em28xx_vol_otable {
414 enum em28xx_aout mux;
415 u8 reg;
416};
417
418static const struct em28xx_vol_otable outputs[] = {
67b8d033
EG		 419 { EM28XX_AOUT_MASTER, AC97_MASTER },
420 { EM28XX_AOUT_LINE, AC97_HEADPHONE },
421 { EM28XX_AOUT_MONO, AC97_MASTER_MONO },
422 { EM28XX_AOUT_LFE, AC97_CENTER_LFE_MASTER },
423 { EM28XX_AOUT_SURR, AC97_SURROUND_MASTER },
35ae6f04
MCC		 424};
425
3acf2809 426int em28xx_audio_analog_set(struct em28xx *dev)
a6c2ba28 427{
35ae6f04 428 int ret, i;
a2070c66 429 u8 xclk;
539c96d0 430
35643943
MCC		 431 if (!dev->audio_mode.has_audio)
432 return 0;
539c96d0 433
5faff789
MCC		 434 /* It is assumed that all devices use master volume for output.
435 It would be possible to use also line output.
436 */
35643943 437 if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
35ae6f04
MCC		 438 /* Mute all outputs */
439 for (i = 0; i < ARRAY_SIZE(outputs); i++) {
e879b8eb 440 ret = em28xx_write_ac97(dev, outputs[i].reg, 0x8000);
35ae6f04
MCC		 441 if (ret < 0)
442 em28xx_warn("couldn't setup AC97 register %d\n",
e879b8eb 443 outputs[i].reg);
35ae6f04 444 }
35643943 445 }
539c96d0 446
505b6d0b 447 xclk = dev->board.xclk & 0x7f;
3abee53e 448 if (!dev->mute)
8ed06fd4 449 xclk |= EM28XX_XCLK_AUDIO_UNMUTE;
3abee53e 450
a2070c66 451 ret = em28xx_write_reg(dev, EM28XX_R0F_XCLK, xclk);
539c96d0
MCC		 452 if (ret < 0)
453 return ret;
3abee53e 454 msleep(10);
539c96d0
MCC		 455
456 /* Selects the proper audio input */
457 ret = em28xx_set_audio_source(dev);
a6c2ba28 458
35643943
MCC		 459 /* Sets volume */
460 if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
461 int vol;
462
67b8d033
EG		 463 em28xx_write_ac97(dev, AC97_POWERDOWN, 0x4200);
464 em28xx_write_ac97(dev, AC97_EXTENDED_STATUS, 0x0031);
465 em28xx_write_ac97(dev, AC97_PCM_LR_ADC_RATE, 0xbb80);
7e4b15e4 466
35643943
MCC		 467 /* LSB: left channel - both channels with the same level */
468 vol = (0x1f - dev->volume) | ((0x1f - dev->volume) << 8);
469
470 /* Mute device, if needed */
471 if (dev->mute)
472 vol |= 0x8000;
473
474 /* Sets volume */
e879b8eb
MCC		 475 for (i = 0; i < ARRAY_SIZE(outputs); i++) {
476 if (dev->ctl_aoutput & outputs[i].mux)
477 ret = em28xx_write_ac97(dev, outputs[i].reg,
478 vol);
479 if (ret < 0)
480 em28xx_warn("couldn't setup AC97 register %d\n",
481 outputs[i].reg);
482 }
8866f9cf
MCC		 483
484 if (dev->ctl_aoutput & EM28XX_AOUT_PCM_IN) {
485 int sel = ac97_return_record_select(dev->ctl_aoutput);
486
a1a6ee74
NS		 487 /* Use the same input for both left and right
488 channels */
8866f9cf
MCC		 489 sel |= (sel << 8);
490
67b8d033 491 em28xx_write_ac97(dev, AC97_REC_SEL, sel);
8866f9cf 492 }
35643943 493 }
00b8730f 494
539c96d0
MCC		 495 return ret;
496}
497EXPORT_SYMBOL_GPL(em28xx_audio_analog_set);
a6c2ba28 498
35643943
MCC		 499int em28xx_audio_setup(struct em28xx *dev)
500{
501 int vid1, vid2, feat, cfg;
16c7bcad 502 u32 vid;
35643943 503
2892bd0d
SK		 504 if (dev->chip_id == CHIP_ID_EM2870 || dev->chip_id == CHIP_ID_EM2874
505 || dev->chip_id == CHIP_ID_EM28174) {
35643943 506 /* Digital only device - don't load any alsa module */
4f83e7b3
MCC		 507 dev->audio_mode.has_audio = false;
508 dev->has_audio_class = false;
509 dev->has_alsa_audio = false;
35643943
MCC		 510 return 0;
511 }
512
4f83e7b3 513 dev->audio_mode.has_audio = true;
35643943
MCC		 514
515 /* See how this device is configured */
516 cfg = em28xx_read_reg(dev, EM28XX_R00_CHIPCFG);
1cdc6392
DH		 517 em28xx_info("Config register raw data: 0x%02x\n", cfg);
518 if (cfg < 0) {
519 /* Register read error? */
35643943 520 cfg = EM28XX_CHIPCFG_AC97; /* Be conservative */
1cdc6392
DH		 521 } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) == 0x00) {
522 /* The device doesn't have vendor audio at all */
4f83e7b3
MCC		 523 dev->has_alsa_audio = false;
524 dev->audio_mode.has_audio = false;
1cdc6392
DH		 525 return 0;
526 } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
527 EM28XX_CHIPCFG_I2S_3_SAMPRATES) {
35643943
MCC		 528 em28xx_info("I2S Audio (3 sample rates)\n");
529 dev->audio_mode.i2s_3rates = 1;
1cdc6392
DH		 530 } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
531 EM28XX_CHIPCFG_I2S_5_SAMPRATES) {
35643943
MCC		 532 em28xx_info("I2S Audio (5 sample rates)\n");
533 dev->audio_mode.i2s_5rates = 1;
534 }
535
de84830e
DH		 536 if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) != EM28XX_CHIPCFG_AC97) {
537 /* Skip the code that does AC97 vendor detection */
35643943
MCC		 538 dev->audio_mode.ac97 = EM28XX_NO_AC97;
539 goto init_audio;
540 }
541
542 dev->audio_mode.ac97 = EM28XX_AC97_OTHER;
543
544 vid1 = em28xx_read_ac97(dev, AC97_VENDOR_ID1);
545 if (vid1 < 0) {
0731160a
MCC		 546 /*
547 * Device likely doesn't support AC97
548 * Note: (some) em2800 devices without eeprom reports 0x91 on
549 * CHIPCFG register, even not having an AC97 chip
550 */
35643943 551 em28xx_warn("AC97 chip type couldn't be determined\n");
0731160a 552 dev->audio_mode.ac97 = EM28XX_NO_AC97;
4f83e7b3
MCC		 553 dev->has_alsa_audio = false;
554 dev->audio_mode.has_audio = false;
35643943
MCC		 555 goto init_audio;
556 }
557
558 vid2 = em28xx_read_ac97(dev, AC97_VENDOR_ID2);
559 if (vid2 < 0)
560 goto init_audio;
561
16c7bcad
MCC		 562 vid = vid1 << 16 | vid2;
563
564 dev->audio_mode.ac97_vendor_id = vid;
565 em28xx_warn("AC97 vendor ID = 0x%08x\n", vid);
35643943
MCC		 566
567 feat = em28xx_read_ac97(dev, AC97_RESET);
568 if (feat < 0)
569 goto init_audio;
570
571 dev->audio_mode.ac97_feat = feat;
572 em28xx_warn("AC97 features = 0x%04x\n", feat);
573
16c7bcad 574 /* Try to identify what audio processor we have */
2a5fc873 575 if (((vid == 0xffffffff) || (vid == 0x83847650)) && (feat == 0x6a90))
35643943 576 dev->audio_mode.ac97 = EM28XX_AC97_EM202;
209acc02
MCC		 577 else if ((vid >> 8) == 0x838476)
578 dev->audio_mode.ac97 = EM28XX_AC97_SIGMATEL;
35643943
MCC		 579
580init_audio:
581 /* Reports detected AC97 processor */
582 switch (dev->audio_mode.ac97) {
583 case EM28XX_NO_AC97:
584 em28xx_info("No AC97 audio processor\n");
585 break;
586 case EM28XX_AC97_EM202:
587 em28xx_info("Empia 202 AC97 audio processor detected\n");
588 break;
209acc02
MCC		 589 case EM28XX_AC97_SIGMATEL:
590 em28xx_info("Sigmatel audio processor detected(stac 97%02x)\n",
591 dev->audio_mode.ac97_vendor_id & 0xff);
592 break;
35643943
MCC		 593 case EM28XX_AC97_OTHER:
594 em28xx_warn("Unknown AC97 audio processor detected!\n");
595 break;
596 default:
597 break;
598 }
599
600 return em28xx_audio_analog_set(dev);
601}
602EXPORT_SYMBOL_GPL(em28xx_audio_setup);
603
3acf2809 604int em28xx_colorlevels_set_default(struct em28xx *dev)
a6c2ba28 605{
2a29a0d7
MCC		 606 em28xx_write_reg(dev, EM28XX_R20_YGAIN, 0x10); /* contrast */
607 em28xx_write_reg(dev, EM28XX_R21_YOFFSET, 0x00); /* brightness */
608 em28xx_write_reg(dev, EM28XX_R22_UVGAIN, 0x10); /* saturation */
609 em28xx_write_reg(dev, EM28XX_R23_UOFFSET, 0x00);
610 em28xx_write_reg(dev, EM28XX_R24_VOFFSET, 0x00);
611 em28xx_write_reg(dev, EM28XX_R25_SHARPNESS, 0x00);
612
613 em28xx_write_reg(dev, EM28XX_R14_GAMMA, 0x20);
614 em28xx_write_reg(dev, EM28XX_R15_RGAIN, 0x20);
615 em28xx_write_reg(dev, EM28XX_R16_GGAIN, 0x20);
616 em28xx_write_reg(dev, EM28XX_R17_BGAIN, 0x20);
617 em28xx_write_reg(dev, EM28XX_R18_ROFFSET, 0x00);
618 em28xx_write_reg(dev, EM28XX_R19_GOFFSET, 0x00);
619 return em28xx_write_reg(dev, EM28XX_R1A_BOFFSET, 0x00);
a6c2ba28 620}
621
3acf2809 622int em28xx_capture_start(struct em28xx *dev, int start)
a6c2ba28 623{
ee6e3a86 624 int rc;
ebef13d4 625
fec528b7
MCC		 626 if (dev->chip_id == CHIP_ID_EM2874 ||
627 dev->chip_id == CHIP_ID_EM2884 ||
628 dev->chip_id == CHIP_ID_EM28174) {
ebef13d4
DH		 629 /* The Transport Stream Enable Register moved in em2874 */
630 if (!start) {
631 rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
632 0x00,
633 EM2874_TS1_CAPTURE_ENABLE);
634 return rc;
635 }
636
637 /* Enable Transport Stream */
638 rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
639 EM2874_TS1_CAPTURE_ENABLE,
640 EM2874_TS1_CAPTURE_ENABLE);
641 return rc;
642 }
643
644
a6c2ba28 645 /* FIXME: which is the best order? */
646 /* video registers are sampled by VREF */
41facaa4 647 rc = em28xx_write_reg_bits(dev, EM28XX_R0C_USBSUSP,
ee6e3a86
MCC		 648 start ? 0x10 : 0x00, 0x10);
649 if (rc < 0)
650 return rc;
651
652 if (!start) {
653 /* disable video capture */
2a29a0d7 654 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x27);
102a0b08 655 return rc;
ee6e3a86
MCC		 656 }
657
d7612c86
MCC		 658 if (dev->board.is_webcam)
659 rc = em28xx_write_reg(dev, 0x13, 0x0c);
660
a6c2ba28 661 /* enable video capture */
2a29a0d7 662 rc = em28xx_write_reg(dev, 0x48, 0x00);
102a0b08 663
ee6e3a86 664 if (dev->mode == EM28XX_ANALOG_MODE)
2a29a0d7 665 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
ee6e3a86 666 else
2a29a0d7 667 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
ee6e3a86 668
6ea54d93 669 msleep(6);
ee6e3a86
MCC		 670
671 return rc;
a6c2ba28 672}
673
da52a55c
DH		 674int em28xx_vbi_supported(struct em28xx *dev)
675{
676 /* Modprobe option to manually disable */
677 if (disable_vbi == 1)
678 return 0;
679
680 if (dev->chip_id == CHIP_ID_EM2860 ||
681 dev->chip_id == CHIP_ID_EM2883)
682 return 1;
683
684 /* Version of em28xx that does not support VBI */
685 return 0;
686}
687
bddcf633 688int em28xx_set_outfmt(struct em28xx *dev)
a6c2ba28 689{
bddcf633 690 int ret;
da52a55c 691 u8 vinctrl;
bddcf633
MCC		 692
693 ret = em28xx_write_reg_bits(dev, EM28XX_R27_OUTFMT,
579d3152 694 dev->format->reg | 0x20, 0xff);
bddcf633 695 if (ret < 0)
02e7804b 696 return ret;
bddcf633 697
579d3152 698 ret = em28xx_write_reg(dev, EM28XX_R10_VINMODE, dev->vinmode);
bddcf633
MCC		 699 if (ret < 0)
700 return ret;
701
da52a55c
DH		 702 vinctrl = dev->vinctl;
703 if (em28xx_vbi_supported(dev) == 1) {
704 vinctrl |= EM28XX_VINCTRL_VBI_RAW;
705 em28xx_write_reg(dev, EM28XX_R34_VBI_START_H, 0x00);
66d9cbad
DH		 706 em28xx_write_reg(dev, EM28XX_R36_VBI_WIDTH, dev->vbi_width/4);
707 em28xx_write_reg(dev, EM28XX_R37_VBI_HEIGHT, dev->vbi_height);
708 if (dev->norm & V4L2_STD_525_60) {
709 /* NTSC */
710 em28xx_write_reg(dev, EM28XX_R35_VBI_START_V, 0x09);
711 } else if (dev->norm & V4L2_STD_625_50) {
712 /* PAL */
713 em28xx_write_reg(dev, EM28XX_R35_VBI_START_V, 0x07);
714 }
da52a55c
DH		 715 }
716
717 return em28xx_write_reg(dev, EM28XX_R11_VINCTRL, vinctrl);
a6c2ba28 718}
719
adcb0fa2
AB		 720static int em28xx_accumulator_set(struct em28xx *dev, u8 xmin, u8 xmax,
721 u8 ymin, u8 ymax)
a6c2ba28 722{
6ea54d93
DSL		 723 em28xx_coredbg("em28xx Scale: (%d,%d)-(%d,%d)\n",
724 xmin, ymin, xmax, ymax);
a6c2ba28 725
41facaa4
MCC		 726 em28xx_write_regs(dev, EM28XX_R28_XMIN, &xmin, 1);
727 em28xx_write_regs(dev, EM28XX_R29_XMAX, &xmax, 1);
728 em28xx_write_regs(dev, EM28XX_R2A_YMIN, &ymin, 1);
729 return em28xx_write_regs(dev, EM28XX_R2B_YMAX, &ymax, 1);
a6c2ba28 730}
731
adcb0fa2 732static int em28xx_capture_area_set(struct em28xx *dev, u8 hstart, u8 vstart,
a6c2ba28 733 u16 width, u16 height)
734{
735 u8 cwidth = width;
736 u8 cheight = height;
737 u8 overflow = (height >> 7 & 0x02) | (width >> 8 & 0x01);
738
6ea54d93
DSL		 739 em28xx_coredbg("em28xx Area Set: (%d,%d)\n",
740 (width | (overflow & 2) << 7),
a6c2ba28 741 (height | (overflow & 1) << 8));
742
41facaa4
MCC		 743 em28xx_write_regs(dev, EM28XX_R1C_HSTART, &hstart, 1);
744 em28xx_write_regs(dev, EM28XX_R1D_VSTART, &vstart, 1);
745 em28xx_write_regs(dev, EM28XX_R1E_CWIDTH, &cwidth, 1);
746 em28xx_write_regs(dev, EM28XX_R1F_CHEIGHT, &cheight, 1);
747 return em28xx_write_regs(dev, EM28XX_R1B_OFLOW, &overflow, 1);
a6c2ba28 748}
749
adcb0fa2 750static int em28xx_scaler_set(struct em28xx *dev, u16 h, u16 v)
a6c2ba28 751{
52c02fcd
SS		 752 u8 mode;
753 /* the em2800 scaler only supports scaling down to 50% */
02e7804b 754
55699964 755 if (dev->board.is_em2800) {
52c02fcd 756 mode = (v ? 0x20 : 0x00) | (h ? 0x10 : 0x00);
02e7804b 757 } else {
52c02fcd 758 u8 buf[2];
02e7804b 759
52c02fcd
SS		 760 buf[0] = h;
761 buf[1] = h >> 8;
41facaa4 762 em28xx_write_regs(dev, EM28XX_R30_HSCALELOW, (char *)buf, 2);
02e7804b 763
52c02fcd
SS		 764 buf[0] = v;
765 buf[1] = v >> 8;
41facaa4 766 em28xx_write_regs(dev, EM28XX_R32_VSCALELOW, (char *)buf, 2);
6ea54d93
DSL		 767 /* it seems that both H and V scalers must be active
768 to work correctly */
a1a6ee74 769 mode = (h || v) ? 0x30 : 0x00;
74458e6c 770 }
41facaa4 771 return em28xx_write_reg_bits(dev, EM28XX_R26_COMPR, mode, 0x30);
a6c2ba28 772}
773
774/* FIXME: this only function read values from dev */
3acf2809 775int em28xx_resolution_set(struct em28xx *dev)
a6c2ba28 776{
777 int width, height;
778 width = norm_maxw(dev);
c2a6b54a
MCC		 779 height = norm_maxh(dev);
780
66d9cbad
DH		 781 /* Properly setup VBI */
782 dev->vbi_width = 720;
783 if (dev->norm & V4L2_STD_525_60)
784 dev->vbi_height = 12;
785 else
786 dev->vbi_height = 18;
787
bddcf633 788 em28xx_set_outfmt(dev);
02e7804b 789
3acf2809 790 em28xx_accumulator_set(dev, 1, (width - 4) >> 2, 1, (height - 4) >> 2);
da52a55c 791
1744feab
DH		 792 /* If we don't set the start position to 2 in VBI mode, we end up
793 with line 20/21 being YUYV encoded instead of being in 8-bit
794 greyscale. The core of the issue is that line 21 (and line 23 for
795 PAL WSS) are inside of active video region, and as a result they
796 get the pixelformatting associated with that area. So by cropping
797 it out, we end up with the same format as the rest of the VBI
798 region */
da52a55c 799 if (em28xx_vbi_supported(dev) == 1)
1744feab 800 em28xx_capture_area_set(dev, 0, 2, width >> 2, height >> 2);
da52a55c
DH		 801 else
802 em28xx_capture_area_set(dev, 0, 0, width >> 2, height >> 2);
02e7804b 803
3acf2809 804 return em28xx_scaler_set(dev, dev->hscale, dev->vscale);
a6c2ba28 805}
806
3acf2809 807int em28xx_set_alternate(struct em28xx *dev)
a6c2ba28 808{
809 int errCode, prev_alt = dev->alt;
3687e1e6 810 int i;
44dc733c 811 unsigned int min_pkt_size = dev->width * 2 + 4;
3687e1e6 812
fc099f0e
MCC		 813 /*
814 * alt = 0 is used only for control messages, so, only values
815 * greater than 0 can be used for streaming.
816 */
817 if (alt && alt < dev->num_alt) {
818 em28xx_coredbg("alternate forced to %d\n", dev->alt);
819 dev->alt = alt;
820 goto set_alt;
821 }
822
2c4a07b2 823 /* When image size is bigger than a certain value,
3687e1e6
MCC		 824 the frame size should be increased, otherwise, only
825 green screen will be received.
826 */
44dc733c 827 if (dev->width * 2 * dev->height > 720 * 240 * 2)
3687e1e6
MCC		 828 min_pkt_size *= 2;
829
2c4a07b2
SS		 830 for (i = 0; i < dev->num_alt; i++) {
831 /* stop when the selected alt setting offers enough bandwidth */
832 if (dev->alt_max_pkt_size[i] >= min_pkt_size) {
833 dev->alt = i;
3687e1e6 834 break;
2c4a07b2
SS		 835 /* otherwise make sure that we end up with the maximum bandwidth
836 because the min_pkt_size equation might be wrong...
837 */
838 } else if (dev->alt_max_pkt_size[i] >
839 dev->alt_max_pkt_size[dev->alt])
840 dev->alt = i;
841 }
a6c2ba28 842
fc099f0e 843set_alt:
a6c2ba28 844 if (dev->alt != prev_alt) {
3687e1e6
MCC		 845 em28xx_coredbg("minimum isoc packet size: %u (alt=%d)\n",
846 min_pkt_size, dev->alt);
a6c2ba28 847 dev->max_pkt_size = dev->alt_max_pkt_size[dev->alt];
3687e1e6
MCC		 848 em28xx_coredbg("setting alternate %d with wMaxPacketSize=%u\n",
849 dev->alt, dev->max_pkt_size);
a6c2ba28 850 errCode = usb_set_interface(dev->udev, 0, dev->alt);
851 if (errCode < 0) {
6ea54d93 852 em28xx_errdev("cannot change alternate number to %d (error=%i)\n",
3687e1e6 853 dev->alt, errCode);
a6c2ba28 854 return errCode;
855 }
856 }
857 return 0;
858}
579f72e4 859
c67ec53f
MCC		 860int em28xx_gpio_set(struct em28xx *dev, struct em28xx_reg_seq *gpio)
861{
862 int rc = 0;
863
864 if (!gpio)
865 return rc;
866
2fe3e2ee
MCC		 867 if (dev->mode != EM28XX_SUSPEND) {
868 em28xx_write_reg(dev, 0x48, 0x00);
869 if (dev->mode == EM28XX_ANALOG_MODE)
870 em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
871 else
872 em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
873 msleep(6);
874 }
c67ec53f
MCC		 875
876 /* Send GPIO reset sequences specified at board entry */
877 while (gpio->sleep >= 0) {
878 if (gpio->reg >= 0) {
879 rc = em28xx_write_reg_bits(dev,
880 gpio->reg,
881 gpio->val,
882 gpio->mask);
883 if (rc < 0)
884 return rc;
885 }
886 if (gpio->sleep > 0)
887 msleep(gpio->sleep);
888
889 gpio++;
890 }
891 return rc;
892}
fec528b7 893EXPORT_SYMBOL_GPL(em28xx_gpio_set);
c67ec53f
MCC		 894
895int em28xx_set_mode(struct em28xx *dev, enum em28xx_mode set_mode)
896{
897 if (dev->mode == set_mode)
898 return 0;
899
2fe3e2ee 900 if (set_mode == EM28XX_SUSPEND) {
c67ec53f 901 dev->mode = set_mode;
2fe3e2ee
MCC		 902
903 /* FIXME: add suspend support for ac97 */
904
905 return em28xx_gpio_set(dev, dev->board.suspend_gpio);
c67ec53f
MCC		 906 }
907
908 dev->mode = set_mode;
909
910 if (dev->mode == EM28XX_DIGITAL_MODE)
f502e861 911 return em28xx_gpio_set(dev, dev->board.dvb_gpio);
c67ec53f 912 else
f502e861 913 return em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
c67ec53f
MCC		 914}
915EXPORT_SYMBOL_GPL(em28xx_set_mode);
916
579f72e4
AT		 917/* ------------------------------------------------------------------
918 URB control
919 ------------------------------------------------------------------*/
920
921/*
922 * IRQ callback, called by URB callback
923 */
924static void em28xx_irq_callback(struct urb *urb)
925{
da52a55c 926 struct em28xx *dev = urb->context;
00d2e7ad 927 int i;
579f72e4 928
aa5a1821
RK		 929 switch (urb->status) {
930 case 0: /* success */
931 case -ETIMEDOUT: /* NAK */
932 break;
933 case -ECONNRESET: /* kill */
934 case -ENOENT:
935 case -ESHUTDOWN:
936 return;
937 default: /* error */
938 em28xx_isocdbg("urb completition error %d.\n", urb->status);
939 break;
940 }
941
579f72e4
AT		 942 /* Copy data from URB */
943 spin_lock(&dev->slock);
00d2e7ad 944 dev->isoc_ctl.isoc_copy(dev, urb);
579f72e4
AT		 945 spin_unlock(&dev->slock);
946
947 /* Reset urb buffers */
948 for (i = 0; i < urb->number_of_packets; i++) {
949 urb->iso_frame_desc[i].status = 0;
950 urb->iso_frame_desc[i].actual_length = 0;
951 }
952 urb->status = 0;
953
954 urb->status = usb_submit_urb(urb, GFP_ATOMIC);
955 if (urb->status) {
4269a8ee
DH		 956 em28xx_isocdbg("urb resubmit failed (error=%i)\n",
957 urb->status);
579f72e4
AT		 958 }
959}
960
961/*
962 * Stop and Deallocate URBs
963 */
86d38d1e 964void em28xx_uninit_isoc(struct em28xx *dev, enum em28xx_mode mode)
579f72e4
AT		 965{
966 struct urb *urb;
86d38d1e 967 struct em28xx_usb_isoc_bufs *isoc_bufs;
579f72e4
AT		 968 int i;
969
86d38d1e
GG		 970 em28xx_isocdbg("em28xx: called em28xx_uninit_isoc in mode %d\n", mode);
971
972 if (mode == EM28XX_DIGITAL_MODE)
973 isoc_bufs = &dev->isoc_ctl.digital_bufs;
974 else
975 isoc_bufs = &dev->isoc_ctl.analog_bufs;
579f72e4 976
86d38d1e
GG		 977 for (i = 0; i < isoc_bufs->num_bufs; i++) {
978 urb = isoc_bufs->urb[i];
579f72e4 979 if (urb) {
9c06210b
RK		 980 if (!irqs_disabled())
981 usb_kill_urb(urb);
982 else
983 usb_unlink_urb(urb);
984
86d38d1e 985 if (isoc_bufs->transfer_buffer[i]) {
997ea58e 986 usb_free_coherent(dev->udev,
6ea54d93 987 urb->transfer_buffer_length,
86d38d1e 988 isoc_bufs->transfer_buffer[i],
6ea54d93 989 urb->transfer_dma);
579f72e4
AT		 990 }
991 usb_free_urb(urb);
86d38d1e 992 isoc_bufs->urb[i] = NULL;
579f72e4 993 }
86d38d1e 994 isoc_bufs->transfer_buffer[i] = NULL;
579f72e4
AT		 995 }
996
86d38d1e
GG		 997 kfree(isoc_bufs->urb);
998 kfree(isoc_bufs->transfer_buffer);
579f72e4 999
86d38d1e
GG		 1000 isoc_bufs->urb = NULL;
1001 isoc_bufs->transfer_buffer = NULL;
1002 isoc_bufs->num_bufs = 0;
579f72e4
AT		 1003
1004 em28xx_capture_start(dev, 0);
1005}
1006EXPORT_SYMBOL_GPL(em28xx_uninit_isoc);
1007
5f5f147f
GG		 1008/*
1009 * Stop URBs
1010 */
1011void em28xx_stop_urbs(struct em28xx *dev)
1012{
1013 int i;
1014 struct urb *urb;
1015 struct em28xx_usb_isoc_bufs *isoc_bufs = &dev->isoc_ctl.digital_bufs;
1016
1017 em28xx_isocdbg("em28xx: called em28xx_stop_urbs\n");
1018
1019 for (i = 0; i < isoc_bufs->num_bufs; i++) {
1020 urb = isoc_bufs->urb[i];
1021 if (urb) {
1022 if (!irqs_disabled())
1023 usb_kill_urb(urb);
1024 else
1025 usb_unlink_urb(urb);
1026 }
1027 }
1028
1029 em28xx_capture_start(dev, 0);
1030}
1031EXPORT_SYMBOL_GPL(em28xx_stop_urbs);
1032
579f72e4 1033/*
86d38d1e 1034 * Allocate URBs
579f72e4 1035 */
86d38d1e
GG		 1036int em28xx_alloc_isoc(struct em28xx *dev, enum em28xx_mode mode,
1037 int max_packets, int num_bufs, int max_pkt_size)
579f72e4 1038{
86d38d1e 1039 struct em28xx_usb_isoc_bufs *isoc_bufs;
579f72e4
AT		 1040 int i;
1041 int sb_size, pipe;
1042 struct urb *urb;
1043 int j, k;
579f72e4 1044
86d38d1e
GG		 1045 em28xx_isocdbg("em28xx: called em28xx_alloc_isoc in mode %d\n", mode);
1046
1047 if (mode == EM28XX_DIGITAL_MODE)
1048 isoc_bufs = &dev->isoc_ctl.digital_bufs;
1049 else
1050 isoc_bufs = &dev->isoc_ctl.analog_bufs;
579f72e4
AT		 1051
1052 /* De-allocates all pending stuff */
86d38d1e 1053 em28xx_uninit_isoc(dev, mode);
579f72e4 1054
86d38d1e 1055 isoc_bufs->num_bufs = num_bufs;
579f72e4 1056
86d38d1e
GG		 1057 isoc_bufs->urb = kzalloc(sizeof(void *)*num_bufs, GFP_KERNEL);
1058 if (!isoc_bufs->urb) {
579f72e4
AT		 1059 em28xx_errdev("cannot alloc memory for usb buffers\n");
1060 return -ENOMEM;
1061 }
1062
86d38d1e
GG		 1063 isoc_bufs->transfer_buffer = kzalloc(sizeof(void *)*num_bufs,
1064 GFP_KERNEL);
1065 if (!isoc_bufs->transfer_buffer) {
42ef4632 1066 em28xx_errdev("cannot allocate memory for usb transfer\n");
86d38d1e 1067 kfree(isoc_bufs->urb);
579f72e4
AT		 1068 return -ENOMEM;
1069 }
1070
86d38d1e
GG		 1071 isoc_bufs->max_pkt_size = max_pkt_size;
1072 isoc_bufs->num_packets = max_packets;
28abf083
DH		 1073 dev->isoc_ctl.vid_buf = NULL;
1074 dev->isoc_ctl.vbi_buf = NULL;
579f72e4 1075
86d38d1e 1076 sb_size = isoc_bufs->num_packets * isoc_bufs->max_pkt_size;
579f72e4
AT		 1077
1078 /* allocate urbs and transfer buffers */
86d38d1e
GG		 1079 for (i = 0; i < isoc_bufs->num_bufs; i++) {
1080 urb = usb_alloc_urb(isoc_bufs->num_packets, GFP_KERNEL);
579f72e4
AT		 1081 if (!urb) {
1082 em28xx_err("cannot alloc isoc_ctl.urb %i\n", i);
86d38d1e 1083 em28xx_uninit_isoc(dev, mode);
579f72e4
AT		 1084 return -ENOMEM;
1085 }
86d38d1e 1086 isoc_bufs->urb[i] = urb;
579f72e4 1087
86d38d1e 1088 isoc_bufs->transfer_buffer[i] = usb_alloc_coherent(dev->udev,
579f72e4 1089 sb_size, GFP_KERNEL, &urb->transfer_dma);
86d38d1e 1090 if (!isoc_bufs->transfer_buffer[i]) {
579f72e4
AT		 1091 em28xx_err("unable to allocate %i bytes for transfer"
1092 " buffer %i%s\n",
1093 sb_size, i,
a1a6ee74 1094 in_interrupt() ? " while in int" : "");
86d38d1e 1095 em28xx_uninit_isoc(dev, mode);
579f72e4
AT		 1096 return -ENOMEM;
1097 }
86d38d1e 1098 memset(isoc_bufs->transfer_buffer[i], 0, sb_size);
579f72e4
AT		 1099
1100 /* FIXME: this is a hack - should be
1101 'desc.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK'
1102 should also be using 'desc.bInterval'
1103 */
6ea54d93 1104 pipe = usb_rcvisocpipe(dev->udev,
86d38d1e 1105 mode == EM28XX_ANALOG_MODE ?
8ab33626 1106 EM28XX_EP_ANALOG : EM28XX_EP_DIGITAL);
6ea54d93 1107
579f72e4 1108 usb_fill_int_urb(urb, dev->udev, pipe,
86d38d1e 1109 isoc_bufs->transfer_buffer[i], sb_size,
da52a55c 1110 em28xx_irq_callback, dev, 1);
579f72e4 1111
86d38d1e 1112 urb->number_of_packets = isoc_bufs->num_packets;
9a4f8201 1113 urb->transfer_flags = URB_ISO_ASAP | URB_NO_TRANSFER_DMA_MAP;
579f72e4
AT		 1114
1115 k = 0;
86d38d1e 1116 for (j = 0; j < isoc_bufs->num_packets; j++) {
579f72e4
AT		 1117 urb->iso_frame_desc[j].offset = k;
1118 urb->iso_frame_desc[j].length =
86d38d1e
GG		 1119 isoc_bufs->max_pkt_size;
1120 k += isoc_bufs->max_pkt_size;
579f72e4
AT		 1121 }
1122 }
1123
86d38d1e
GG		 1124 return 0;
1125}
1126EXPORT_SYMBOL_GPL(em28xx_alloc_isoc);
1127
1128/*
1129 * Allocate URBs and start IRQ
1130 */
1131int em28xx_init_isoc(struct em28xx *dev, enum em28xx_mode mode,
1132 int max_packets, int num_bufs, int max_pkt_size,
1133 int (*isoc_copy) (struct em28xx *dev, struct urb *urb))
1134{
1135 struct em28xx_dmaqueue *dma_q = &dev->vidq;
1136 struct em28xx_dmaqueue *vbi_dma_q = &dev->vbiq;
1137 struct em28xx_usb_isoc_bufs *isoc_bufs;
1138 int i;
1139 int rc;
1140 int alloc;
1141
1142 em28xx_isocdbg("em28xx: called em28xx_init_isoc in mode %d\n", mode);
1143
1144 dev->isoc_ctl.isoc_copy = isoc_copy;
1145
1146 if (mode == EM28XX_DIGITAL_MODE) {
1147 isoc_bufs = &dev->isoc_ctl.digital_bufs;
1148 /* no need to free/alloc isoc buffers in digital mode */
1149 alloc = 0;
1150 } else {
1151 isoc_bufs = &dev->isoc_ctl.analog_bufs;
1152 alloc = 1;
1153 }
1154
1155 if (alloc) {
1156 rc = em28xx_alloc_isoc(dev, mode, max_packets,
1157 num_bufs, max_pkt_size);
1158 if (rc)
1159 return rc;
1160 }
1161
579f72e4 1162 init_waitqueue_head(&dma_q->wq);
28abf083 1163 init_waitqueue_head(&vbi_dma_q->wq);
579f72e4 1164
c67ec53f 1165 em28xx_capture_start(dev, 1);
579f72e4
AT		 1166
1167 /* submit urbs and enables IRQ */
86d38d1e
GG		 1168 for (i = 0; i < isoc_bufs->num_bufs; i++) {
1169 rc = usb_submit_urb(isoc_bufs->urb[i], GFP_ATOMIC);
579f72e4
AT		 1170 if (rc) {
1171 em28xx_err("submit of urb %i failed (error=%i)\n", i,
1172 rc);
86d38d1e 1173 em28xx_uninit_isoc(dev, mode);
579f72e4
AT		 1174 return rc;
1175 }
1176 }
1177
1178 return 0;
1179}
1180EXPORT_SYMBOL_GPL(em28xx_init_isoc);
1a23f81b
MCC		 1181
1182/*
1183 * em28xx_wake_i2c()
1184 * configure i2c attached devices
1185 */
1186void em28xx_wake_i2c(struct em28xx *dev)
1187{
5325b427
HV		 1188 v4l2_device_call_all(&dev->v4l2_dev, 0, core, reset, 0);
1189 v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_routing,
1190 INPUT(dev->ctl_input)->vmux, 0, 0);
f2cf250a 1191 v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_stream, 0);
1a23f81b
MCC		 1192}
1193
1194/*
1195 * Device control list
1196 */
1197
1198static LIST_HEAD(em28xx_devlist);
1199static DEFINE_MUTEX(em28xx_devlist_mutex);
1200
1a23f81b
MCC		 1201/*
1202 * Extension interface
1203 */
1204
1205static LIST_HEAD(em28xx_extension_devlist);
1a23f81b
MCC		 1206
1207int em28xx_register_extension(struct em28xx_ops *ops)
1208{
1209 struct em28xx *dev = NULL;
1210
1211 mutex_lock(&em28xx_devlist_mutex);
1a23f81b
MCC		 1212 list_add_tail(&ops->next, &em28xx_extension_devlist);
1213 list_for_each_entry(dev, &em28xx_devlist, devlist) {
517521e4 1214 ops->init(dev);
1a23f81b 1215 }
1a23f81b 1216 mutex_unlock(&em28xx_devlist_mutex);
76424a0a 1217 printk(KERN_INFO "Em28xx: Initialized (%s) extension\n", ops->name);
1a23f81b
MCC		 1218 return 0;
1219}
1220EXPORT_SYMBOL(em28xx_register_extension);
1221
1222void em28xx_unregister_extension(struct em28xx_ops *ops)
1223{
1224 struct em28xx *dev = NULL;
1225
1226 mutex_lock(&em28xx_devlist_mutex);
1227 list_for_each_entry(dev, &em28xx_devlist, devlist) {
517521e4 1228 ops->fini(dev);
1a23f81b 1229 }
1a23f81b 1230 list_del(&ops->next);
1a23f81b 1231 mutex_unlock(&em28xx_devlist_mutex);
76424a0a 1232 printk(KERN_INFO "Em28xx: Removed (%s) extension\n", ops->name);
1a23f81b
MCC		 1233}
1234EXPORT_SYMBOL(em28xx_unregister_extension);
1235
1236void em28xx_init_extension(struct em28xx *dev)
1237{
6c03e38b 1238 const struct em28xx_ops *ops = NULL;
1a23f81b 1239
5013318c 1240 mutex_lock(&em28xx_devlist_mutex);
6c03e38b
CR		 1241 list_add_tail(&dev->devlist, &em28xx_devlist);
1242 list_for_each_entry(ops, &em28xx_extension_devlist, next) {
1243 if (ops->init)
1244 ops->init(dev);
1a23f81b 1245 }
5013318c 1246 mutex_unlock(&em28xx_devlist_mutex);
1a23f81b
MCC		 1247}
1248
1249void em28xx_close_extension(struct em28xx *dev)
1250{
d7222e7d 1251 const struct em28xx_ops *ops = NULL;
1a23f81b 1252
5013318c 1253 mutex_lock(&em28xx_devlist_mutex);
d7222e7d
CR		 1254 list_for_each_entry(ops, &em28xx_extension_devlist, next) {
1255 if (ops->fini)
1256 ops->fini(dev);
1a23f81b 1257 }
d7222e7d 1258 list_del(&dev->devlist);
5013318c 1259 mutex_unlock(&em28xx_devlist_mutex);
1a23f81b 1260}
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