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V4L/DVB (9756): em28xx: Improve register log format
[mirror_ubuntu-zesty-kernel.git] / drivers / media / video / em28xx / em28xx-core.c
CommitLineData
a6c2ba28 1/*
3acf2809 2 em28xx-core.c - driver for Empia EM2800/EM2820/2840 USB video capture devices
a6c2ba28 3
f7abcd38
MCC		 4 Copyright (C) 2005 Ludovico Cavedon <cavedon@sssup.it>
5 Markus Rechberger <mrechberger@gmail.com>
2e7c6dc3 6 Mauro Carvalho Chehab <mchehab@infradead.org>
f7abcd38 7 Sascha Sommer <saschasommer@freenet.de>
a6c2ba28 8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#include <linux/init.h>
25#include <linux/list.h>
26#include <linux/module.h>
a6c2ba28 27#include <linux/usb.h>
28#include <linux/vmalloc.h>
29
f7abcd38 30#include "em28xx.h"
a6c2ba28 31
32/* #define ENABLE_DEBUG_ISOC_FRAMES */
33
ff699e6b 34static unsigned int core_debug;
a6c2ba28 35module_param(core_debug,int,0644);
36MODULE_PARM_DESC(core_debug,"enable debug messages [core]");
37
3acf2809 38#define em28xx_coredbg(fmt, arg...) do {\
4ac97914
MCC		 39 if (core_debug) \
40 printk(KERN_INFO "%s %s :"fmt, \
d80e134d 41 dev->name, __func__ , ##arg); } while (0)
a6c2ba28 42
ff699e6b 43static unsigned int reg_debug;
a6c2ba28 44module_param(reg_debug,int,0644);
45MODULE_PARM_DESC(reg_debug,"enable debug messages [URB reg]");
46
3acf2809 47#define em28xx_regdbg(fmt, arg...) do {\
4ac97914
MCC		 48 if (reg_debug) \
49 printk(KERN_INFO "%s %s :"fmt, \
d80e134d 50 dev->name, __func__ , ##arg); } while (0)
a6c2ba28 51
3acf2809 52static int alt = EM28XX_PINOUT;
a6c2ba28 53module_param(alt, int, 0644);
54MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint");
55
579f72e4
AT		 56/* FIXME */
57#define em28xx_isocdbg(fmt, arg...) do {\
58 if (core_debug) \
59 printk(KERN_INFO "%s %s :"fmt, \
60 dev->name, __func__ , ##arg); } while (0)
61
a6c2ba28 62/*
3acf2809 63 * em28xx_read_reg_req()
a6c2ba28 64 * reads data from the usb device specifying bRequest
65 */
3acf2809 66int em28xx_read_reg_req_len(struct em28xx *dev, u8 req, u16 reg,
a6c2ba28 67 char *buf, int len)
68{
9e5d6760
MCC		 69 int ret;
70 int pipe = usb_rcvctrlpipe(dev->udev, 0);
a6c2ba28 71
9f38724a 72 if (dev->state & DEV_DISCONNECTED)
c4a98793
MCC		 73 return -ENODEV;
74
75 if (len > URB_MAX_CTRL_SIZE)
76 return -EINVAL;
9f38724a 77
9e5d6760
MCC		 78 if (reg_debug) {
79 printk( KERN_DEBUG "(pipe 0x%08x): "
80 "IN: %02x %02x %02x %02x %02x %02x %02x %02x ",
81 pipe,
82 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
83 req, 0, 0,
84 reg & 0xff, reg >> 8,
85 len & 0xff, len >> 8);
86 }
a6c2ba28 87
f2a2e491 88 mutex_lock(&dev->ctrl_urb_lock);
9e5d6760 89 ret = usb_control_msg(dev->udev, pipe, req,
a6c2ba28 90 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
c4a98793
MCC		 91 0x0000, reg, dev->urb_buf, len, HZ);
92 if (ret < 0) {
93 if (reg_debug)
94 printk(" failed!\n");
f2a2e491 95 mutex_unlock(&dev->ctrl_urb_lock);
c4a98793
MCC		 96 return ret;
97 }
98
99 if (len)
100 memcpy(buf, dev->urb_buf, len);
a6c2ba28 101
f2a2e491
MCC		 102 mutex_unlock(&dev->ctrl_urb_lock);
103
6ea54d93 104 if (reg_debug) {
9e5d6760
MCC		 105 int byte;
106
107 printk("<<<");
6ea54d93 108 for (byte = 0; byte < len; byte++)
82ac4f87 109 printk(" %02x", (unsigned char)buf[byte]);
82ac4f87 110 printk("\n");
a6c2ba28 111 }
112
113 return ret;
114}
115
116/*
3acf2809 117 * em28xx_read_reg_req()
a6c2ba28 118 * reads data from the usb device specifying bRequest
119 */
3acf2809 120int em28xx_read_reg_req(struct em28xx *dev, u8 req, u16 reg)
a6c2ba28 121{
a6c2ba28 122 int ret;
9e5d6760 123 u8 val;
a6c2ba28 124
9e5d6760
MCC		 125 ret = em28xx_read_reg_req_len(dev, req, reg, &val, 1);
126 if (ret < 0)
c4a98793 127 return ret;
a6c2ba28 128
129 return val;
130}
131
3acf2809 132int em28xx_read_reg(struct em28xx *dev, u16 reg)
a6c2ba28 133{
3acf2809 134 return em28xx_read_reg_req(dev, USB_REQ_GET_STATUS, reg);
a6c2ba28 135}
136
137/*
3acf2809 138 * em28xx_write_regs_req()
a6c2ba28 139 * sends data to the usb device, specifying bRequest
140 */
3acf2809 141int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf,
a6c2ba28 142 int len)
143{
144 int ret;
9e5d6760 145 int pipe = usb_sndctrlpipe(dev->udev, 0);
a6c2ba28 146
9f38724a 147 if (dev->state & DEV_DISCONNECTED)
c67ec53f
MCC		 148 return -ENODEV;
149
c4a98793 150 if ((len < 1) || (len > URB_MAX_CTRL_SIZE))
c67ec53f 151 return -EINVAL;
9f38724a 152
a6c2ba28 153 if (reg_debug) {
9e5d6760
MCC		 154 int byte;
155
156 printk( KERN_DEBUG "(pipe 0x%08x): "
157 "OUT: %02x %02x %02x %02x %02x %02x %02x %02x >>>",
158 pipe,
159 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
160 req, 0, 0,
161 reg & 0xff, reg >> 8,
162 len & 0xff, len >> 8);
163
164 for (byte = 0; byte < len; byte++)
165 printk(" %02x", (unsigned char)buf[byte]);
82ac4f87 166 printk("\n");
a6c2ba28 167 }
168
f2a2e491 169 mutex_lock(&dev->ctrl_urb_lock);
c4a98793 170 memcpy(dev->urb_buf, buf, len);
9e5d6760 171 ret = usb_control_msg(dev->udev, pipe, req,
a6c2ba28 172 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
c4a98793 173 0x0000, reg, dev->urb_buf, len, HZ);
f2a2e491 174 mutex_unlock(&dev->ctrl_urb_lock);
c4a98793 175
89b329ef
MCC		 176 if (dev->wait_after_write)
177 msleep(dev->wait_after_write);
178
a6c2ba28 179 return ret;
180}
181
3acf2809 182int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len)
a6c2ba28 183{
c67ec53f
MCC		 184 int rc;
185
186 rc = em28xx_write_regs_req(dev, USB_REQ_GET_STATUS, reg, buf, len);
187
188 /* Stores GPO/GPIO values at the cache, if changed
189 Only write values should be stored, since input on a GPIO
190 register will return the input bits.
191 Not sure what happens on reading GPO register.
192 */
193 if (rc >= 0) {
6a1acc3b 194 if (reg == dev->reg_gpo_num)
c67ec53f 195 dev->reg_gpo = buf[0];
6a1acc3b 196 else if (reg == dev->reg_gpio_num)
c67ec53f
MCC		 197 dev->reg_gpio = buf[0];
198 }
199
200 return rc;
a6c2ba28 201}
202
b6972489
DH		 203/* Write a single register */
204int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val)
205{
206 return em28xx_write_regs(dev, reg, &val, 1);
207}
208
a6c2ba28 209/*
3acf2809 210 * em28xx_write_reg_bits()
a6c2ba28 211 * sets only some bits (specified by bitmask) of a register, by first reading
212 * the actual value
213 */
532fe652 214static int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val,
a6c2ba28 215 u8 bitmask)
216{
217 int oldval;
218 u8 newval;
6ea54d93 219
c67ec53f 220 /* Uses cache for gpo/gpio registers */
6a1acc3b 221 if (reg == dev->reg_gpo_num)
c67ec53f 222 oldval = dev->reg_gpo;
6a1acc3b 223 else if (reg == dev->reg_gpio_num)
c67ec53f
MCC		 224 oldval = dev->reg_gpio;
225 else
226 oldval = em28xx_read_reg(dev, reg);
6ea54d93
DSL		 227
228 if (oldval < 0)
a6c2ba28 229 return oldval;
6ea54d93 230
a6c2ba28 231 newval = (((u8) oldval) & ~bitmask) | (val & bitmask);
c67ec53f 232
3acf2809 233 return em28xx_write_regs(dev, reg, &newval, 1);
a6c2ba28 234}
235
35643943
MCC		 236/*
237 * em28xx_is_ac97_ready()
238 * Checks if ac97 is ready
239 */
240static int em28xx_is_ac97_ready(struct em28xx *dev)
241{
242 int ret, i;
243
244 /* Wait up to 50 ms for AC97 command to complete */
245 for (i = 0; i < 10; i++, msleep(5)) {
246 ret = em28xx_read_reg(dev, EM28XX_R43_AC97BUSY);
247 if (ret < 0)
248 return ret;
249
250 if (!(ret & 0x01))
251 return 0;
252 }
253
254 em28xx_warn("AC97 command still being executed: not handled properly!\n");
255 return -EBUSY;
256}
257
258/*
259 * em28xx_read_ac97()
260 * write a 16 bit value to the specified AC97 address (LSB first!)
261 */
262static int em28xx_read_ac97(struct em28xx *dev, u8 reg)
263{
264 int ret;
265 u8 addr = (reg & 0x7f) | 0x80;
266 u16 val;
267
268 ret = em28xx_is_ac97_ready(dev);
269 if (ret < 0)
270 return ret;
271
272 ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
273 if (ret < 0)
274 return ret;
275
276 ret = dev->em28xx_read_reg_req_len(dev, 0, EM28XX_R40_AC97LSB,
277 (u8 *)&val, sizeof(val));
278
279 if (ret < 0)
280 return ret;
281 return le16_to_cpu(val);
282}
283
a6c2ba28 284/*
3acf2809 285 * em28xx_write_ac97()
a6c2ba28 286 * write a 16 bit value to the specified AC97 address (LSB first!)
287 */
35643943 288static int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val)
a6c2ba28 289{
35643943 290 int ret;
a6c2ba28 291 u8 addr = reg & 0x7f;
35643943
MCC		 292 __le16 value;
293
294 value = cpu_to_le16(val);
295
296 ret = em28xx_is_ac97_ready(dev);
297 if (ret < 0)
298 return ret;
6ea54d93 299
35643943 300 ret = em28xx_write_regs(dev, EM28XX_R40_AC97LSB, (u8 *) &value, 2);
6ea54d93 301 if (ret < 0)
a6c2ba28 302 return ret;
6ea54d93 303
41facaa4 304 ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
6ea54d93 305 if (ret < 0)
a6c2ba28 306 return ret;
00b8730f 307
35643943
MCC		 308 return 0;
309}
6ea54d93 310
e879b8eb
MCC		 311struct em28xx_vol_table {
312 enum em28xx_amux mux;
5faff789
MCC		 313 u8 reg;
314};
315
e879b8eb 316static struct em28xx_vol_table inputs[] = {
5faff789
MCC		 317 { EM28XX_AMUX_VIDEO, AC97_VIDEO_VOL },
318 { EM28XX_AMUX_LINE_IN, AC97_LINEIN_VOL },
319 { EM28XX_AMUX_PHONE, AC97_PHONE_VOL },
320 { EM28XX_AMUX_MIC, AC97_MIC_VOL },
321 { EM28XX_AMUX_CD, AC97_CD_VOL },
322 { EM28XX_AMUX_AUX, AC97_AUX_VOL },
323 { EM28XX_AMUX_PCM_OUT, AC97_PCM_OUT_VOL },
324};
325
326static int set_ac97_input(struct em28xx *dev)
35643943 327{
5faff789
MCC		 328 int ret, i;
329 enum em28xx_amux amux = dev->ctl_ainput;
35643943 330
5faff789
MCC		 331 /* EM28XX_AMUX_VIDEO2 is a special case used to indicate that
332 em28xx should point to LINE IN, while AC97 should use VIDEO
333 */
334 if (amux == EM28XX_AMUX_VIDEO2)
f1990a9c 335 amux = EM28XX_AMUX_VIDEO;
35643943 336
5faff789
MCC		 337 /* Mute all entres but the one that were selected */
338 for (i = 0; i < ARRAY_SIZE(inputs); i++) {
e879b8eb 339 if (amux == inputs[i].mux)
5faff789
MCC		 340 ret = em28xx_write_ac97(dev, inputs[i].reg, 0x0808);
341 else
342 ret = em28xx_write_ac97(dev, inputs[i].reg, 0x8000);
35643943 343
5faff789
MCC		 344 if (ret < 0)
345 em28xx_warn("couldn't setup AC97 register %d\n",
346 inputs[i].reg);
347 }
348 return 0;
a6c2ba28 349}
350
00b8730f 351static int em28xx_set_audio_source(struct em28xx *dev)
539c96d0 352{
1685a6fe 353 int ret;
539c96d0
MCC		 354 u8 input;
355
505b6d0b 356 if (dev->board.is_em2800) {
5faff789 357 if (dev->ctl_ainput == EM28XX_AMUX_VIDEO)
539c96d0 358 input = EM2800_AUDIO_SRC_TUNER;
5faff789
MCC		 359 else
360 input = EM2800_AUDIO_SRC_LINE;
539c96d0 361
41facaa4 362 ret = em28xx_write_regs(dev, EM2800_R08_AUDIOSRC, &input, 1);
539c96d0
MCC		 363 if (ret < 0)
364 return ret;
365 }
366
505b6d0b 367 if (dev->board.has_msp34xx)
539c96d0
MCC		 368 input = EM28XX_AUDIO_SRC_TUNER;
369 else {
370 switch (dev->ctl_ainput) {
371 case EM28XX_AMUX_VIDEO:
372 input = EM28XX_AUDIO_SRC_TUNER;
539c96d0 373 break;
35643943 374 default:
539c96d0 375 input = EM28XX_AUDIO_SRC_LINE;
539c96d0
MCC		 376 break;
377 }
378 }
379
41facaa4 380 ret = em28xx_write_reg_bits(dev, EM28XX_R0E_AUDIOSRC, input, 0xc0);
539c96d0
MCC		 381 if (ret < 0)
382 return ret;
00b8730f 383 msleep(5);
539c96d0 384
35643943
MCC		 385 switch (dev->audio_mode.ac97) {
386 case EM28XX_NO_AC97:
387 break;
5faff789
MCC		 388 default:
389 ret = set_ac97_input(dev);
35643943 390 }
539c96d0 391
5faff789 392 return ret;
539c96d0
MCC		 393}
394
e879b8eb
MCC		 395struct em28xx_vol_table outputs[] = {
396 { EM28XX_AOUT_MASTER, AC97_MASTER_VOL },
397 { EM28XX_AOUT_LINE, AC97_LINE_LEVEL_VOL },
398 { EM28XX_AOUT_MONO, AC97_MASTER_MONO_VOL },
399 { EM28XX_AOUT_LFE, AC97_LFE_MASTER_VOL },
400 { EM28XX_AOUT_SURR, AC97_SURR_MASTER_VOL },
35ae6f04
MCC		 401};
402
3acf2809 403int em28xx_audio_analog_set(struct em28xx *dev)
a6c2ba28 404{
35ae6f04 405 int ret, i;
a2070c66 406 u8 xclk;
539c96d0 407
35643943
MCC		 408 if (!dev->audio_mode.has_audio)
409 return 0;
539c96d0 410
5faff789
MCC		 411 /* It is assumed that all devices use master volume for output.
412 It would be possible to use also line output.
413 */
35643943 414 if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
35ae6f04
MCC		 415 /* Mute all outputs */
416 for (i = 0; i < ARRAY_SIZE(outputs); i++) {
e879b8eb 417 ret = em28xx_write_ac97(dev, outputs[i].reg, 0x8000);
35ae6f04
MCC		 418 if (ret < 0)
419 em28xx_warn("couldn't setup AC97 register %d\n",
e879b8eb 420 outputs[i].reg);
35ae6f04 421 }
35643943 422 }
539c96d0 423
505b6d0b 424 xclk = dev->board.xclk & 0x7f;
3abee53e
MCC		 425 if (!dev->mute)
426 xclk |= 0x80;
427
a2070c66 428 ret = em28xx_write_reg(dev, EM28XX_R0F_XCLK, xclk);
539c96d0
MCC		 429 if (ret < 0)
430 return ret;
3abee53e 431 msleep(10);
539c96d0
MCC		 432
433 /* Selects the proper audio input */
434 ret = em28xx_set_audio_source(dev);
a6c2ba28 435
35643943
MCC		 436 /* Sets volume */
437 if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
438 int vol;
439
440 /* LSB: left channel - both channels with the same level */
441 vol = (0x1f - dev->volume) | ((0x1f - dev->volume) << 8);
442
443 /* Mute device, if needed */
444 if (dev->mute)
445 vol |= 0x8000;
446
447 /* Sets volume */
e879b8eb
MCC		 448 for (i = 0; i < ARRAY_SIZE(outputs); i++) {
449 if (dev->ctl_aoutput & outputs[i].mux)
450 ret = em28xx_write_ac97(dev, outputs[i].reg,
451 vol);
452 if (ret < 0)
453 em28xx_warn("couldn't setup AC97 register %d\n",
454 outputs[i].reg);
455 }
35643943 456 }
00b8730f 457
539c96d0
MCC		 458 return ret;
459}
460EXPORT_SYMBOL_GPL(em28xx_audio_analog_set);
a6c2ba28 461
35643943
MCC		 462int em28xx_audio_setup(struct em28xx *dev)
463{
464 int vid1, vid2, feat, cfg;
16c7bcad 465 u32 vid;
35643943
MCC		 466
467 if (dev->chip_id == CHIP_ID_EM2874) {
468 /* Digital only device - don't load any alsa module */
469 dev->audio_mode.has_audio = 0;
470 dev->has_audio_class = 0;
471 dev->has_alsa_audio = 0;
472 return 0;
473 }
474
475 /* If device doesn't support Usb Audio Class, use vendor class */
476 if (!dev->has_audio_class)
477 dev->has_alsa_audio = 1;
478
479 dev->audio_mode.has_audio = 1;
480
481 /* See how this device is configured */
482 cfg = em28xx_read_reg(dev, EM28XX_R00_CHIPCFG);
483 if (cfg < 0)
484 cfg = EM28XX_CHIPCFG_AC97; /* Be conservative */
485 else
486 em28xx_info("Config register raw data: 0x%02x\n", cfg);
487
488 if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
489 EM28XX_CHIPCFG_I2S_3_SAMPRATES) {
490 em28xx_info("I2S Audio (3 sample rates)\n");
491 dev->audio_mode.i2s_3rates = 1;
492 }
493 if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
494 EM28XX_CHIPCFG_I2S_5_SAMPRATES) {
495 em28xx_info("I2S Audio (5 sample rates)\n");
496 dev->audio_mode.i2s_5rates = 1;
497 }
498
499 if (!(cfg & EM28XX_CHIPCFG_AC97)) {
500 dev->audio_mode.ac97 = EM28XX_NO_AC97;
501 goto init_audio;
502 }
503
504 dev->audio_mode.ac97 = EM28XX_AC97_OTHER;
505
506 vid1 = em28xx_read_ac97(dev, AC97_VENDOR_ID1);
507 if (vid1 < 0) {
508 /* Device likely doesn't support AC97 */
509 em28xx_warn("AC97 chip type couldn't be determined\n");
510 goto init_audio;
511 }
512
513 vid2 = em28xx_read_ac97(dev, AC97_VENDOR_ID2);
514 if (vid2 < 0)
515 goto init_audio;
516
16c7bcad
MCC		 517 vid = vid1 << 16 | vid2;
518
519 dev->audio_mode.ac97_vendor_id = vid;
520 em28xx_warn("AC97 vendor ID = 0x%08x\n", vid);
35643943
MCC		 521
522 feat = em28xx_read_ac97(dev, AC97_RESET);
523 if (feat < 0)
524 goto init_audio;
525
526 dev->audio_mode.ac97_feat = feat;
527 em28xx_warn("AC97 features = 0x%04x\n", feat);
528
16c7bcad
MCC		 529 /* Try to identify what audio processor we have */
530 if ((vid == 0xffffffff) && (feat == 0x6a90))
35643943 531 dev->audio_mode.ac97 = EM28XX_AC97_EM202;
209acc02
MCC		 532 else if ((vid >> 8) == 0x838476)
533 dev->audio_mode.ac97 = EM28XX_AC97_SIGMATEL;
35643943
MCC		 534
535init_audio:
536 /* Reports detected AC97 processor */
537 switch (dev->audio_mode.ac97) {
538 case EM28XX_NO_AC97:
539 em28xx_info("No AC97 audio processor\n");
540 break;
541 case EM28XX_AC97_EM202:
542 em28xx_info("Empia 202 AC97 audio processor detected\n");
543 break;
209acc02
MCC		 544 case EM28XX_AC97_SIGMATEL:
545 em28xx_info("Sigmatel audio processor detected(stac 97%02x)\n",
546 dev->audio_mode.ac97_vendor_id & 0xff);
547 break;
35643943
MCC		 548 case EM28XX_AC97_OTHER:
549 em28xx_warn("Unknown AC97 audio processor detected!\n");
550 break;
551 default:
552 break;
553 }
554
555 return em28xx_audio_analog_set(dev);
556}
557EXPORT_SYMBOL_GPL(em28xx_audio_setup);
558
3acf2809 559int em28xx_colorlevels_set_default(struct em28xx *dev)
a6c2ba28 560{
2a29a0d7
MCC		 561 em28xx_write_reg(dev, EM28XX_R20_YGAIN, 0x10); /* contrast */
562 em28xx_write_reg(dev, EM28XX_R21_YOFFSET, 0x00); /* brightness */
563 em28xx_write_reg(dev, EM28XX_R22_UVGAIN, 0x10); /* saturation */
564 em28xx_write_reg(dev, EM28XX_R23_UOFFSET, 0x00);
565 em28xx_write_reg(dev, EM28XX_R24_VOFFSET, 0x00);
566 em28xx_write_reg(dev, EM28XX_R25_SHARPNESS, 0x00);
567
568 em28xx_write_reg(dev, EM28XX_R14_GAMMA, 0x20);
569 em28xx_write_reg(dev, EM28XX_R15_RGAIN, 0x20);
570 em28xx_write_reg(dev, EM28XX_R16_GGAIN, 0x20);
571 em28xx_write_reg(dev, EM28XX_R17_BGAIN, 0x20);
572 em28xx_write_reg(dev, EM28XX_R18_ROFFSET, 0x00);
573 em28xx_write_reg(dev, EM28XX_R19_GOFFSET, 0x00);
574 return em28xx_write_reg(dev, EM28XX_R1A_BOFFSET, 0x00);
a6c2ba28 575}
576
3acf2809 577int em28xx_capture_start(struct em28xx *dev, int start)
a6c2ba28 578{
ee6e3a86 579 int rc;
ebef13d4
DH		 580
581 if (dev->chip_id == CHIP_ID_EM2874) {
582 /* The Transport Stream Enable Register moved in em2874 */
583 if (!start) {
584 rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
585 0x00,
586 EM2874_TS1_CAPTURE_ENABLE);
587 return rc;
588 }
589
590 /* Enable Transport Stream */
591 rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
592 EM2874_TS1_CAPTURE_ENABLE,
593 EM2874_TS1_CAPTURE_ENABLE);
594 return rc;
595 }
596
597
a6c2ba28 598 /* FIXME: which is the best order? */
599 /* video registers are sampled by VREF */
41facaa4 600 rc = em28xx_write_reg_bits(dev, EM28XX_R0C_USBSUSP,
ee6e3a86
MCC		 601 start ? 0x10 : 0x00, 0x10);
602 if (rc < 0)
603 return rc;
604
605 if (!start) {
606 /* disable video capture */
2a29a0d7 607 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x27);
102a0b08 608 return rc;
ee6e3a86
MCC		 609 }
610
a6c2ba28 611 /* enable video capture */
2a29a0d7 612 rc = em28xx_write_reg(dev, 0x48, 0x00);
102a0b08 613
ee6e3a86 614 if (dev->mode == EM28XX_ANALOG_MODE)
2a29a0d7 615 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
ee6e3a86 616 else
2a29a0d7 617 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
ee6e3a86 618
6ea54d93 619 msleep(6);
ee6e3a86
MCC		 620
621 return rc;
a6c2ba28 622}
623
3acf2809 624int em28xx_outfmt_set_yuv422(struct em28xx *dev)
a6c2ba28 625{
2a29a0d7
MCC		 626 em28xx_write_reg(dev, EM28XX_R27_OUTFMT, 0x34);
627 em28xx_write_reg(dev, EM28XX_R10_VINMODE, 0x10);
628 return em28xx_write_reg(dev, EM28XX_R11_VINCTRL, 0x11);
a6c2ba28 629}
630
adcb0fa2
AB		 631static int em28xx_accumulator_set(struct em28xx *dev, u8 xmin, u8 xmax,
632 u8 ymin, u8 ymax)
a6c2ba28 633{
6ea54d93
DSL		 634 em28xx_coredbg("em28xx Scale: (%d,%d)-(%d,%d)\n",
635 xmin, ymin, xmax, ymax);
a6c2ba28 636
41facaa4
MCC		 637 em28xx_write_regs(dev, EM28XX_R28_XMIN, &xmin, 1);
638 em28xx_write_regs(dev, EM28XX_R29_XMAX, &xmax, 1);
639 em28xx_write_regs(dev, EM28XX_R2A_YMIN, &ymin, 1);
640 return em28xx_write_regs(dev, EM28XX_R2B_YMAX, &ymax, 1);
a6c2ba28 641}
642
adcb0fa2 643static int em28xx_capture_area_set(struct em28xx *dev, u8 hstart, u8 vstart,
a6c2ba28 644 u16 width, u16 height)
645{
646 u8 cwidth = width;
647 u8 cheight = height;
648 u8 overflow = (height >> 7 & 0x02) | (width >> 8 & 0x01);
649
6ea54d93
DSL		 650 em28xx_coredbg("em28xx Area Set: (%d,%d)\n",
651 (width | (overflow & 2) << 7),
a6c2ba28 652 (height | (overflow & 1) << 8));
653
41facaa4
MCC		 654 em28xx_write_regs(dev, EM28XX_R1C_HSTART, &hstart, 1);
655 em28xx_write_regs(dev, EM28XX_R1D_VSTART, &vstart, 1);
656 em28xx_write_regs(dev, EM28XX_R1E_CWIDTH, &cwidth, 1);
657 em28xx_write_regs(dev, EM28XX_R1F_CHEIGHT, &cheight, 1);
658 return em28xx_write_regs(dev, EM28XX_R1B_OFLOW, &overflow, 1);
a6c2ba28 659}
660
adcb0fa2 661static int em28xx_scaler_set(struct em28xx *dev, u16 h, u16 v)
a6c2ba28 662{
52c02fcd
SS		 663 u8 mode;
664 /* the em2800 scaler only supports scaling down to 50% */
505b6d0b 665 if (dev->board.is_em2800)
52c02fcd
SS		 666 mode = (v ? 0x20 : 0x00) | (h ? 0x10 : 0x00);
667 else {
668 u8 buf[2];
669 buf[0] = h;
670 buf[1] = h >> 8;
41facaa4 671 em28xx_write_regs(dev, EM28XX_R30_HSCALELOW, (char *)buf, 2);
52c02fcd
SS		 672 buf[0] = v;
673 buf[1] = v >> 8;
41facaa4 674 em28xx_write_regs(dev, EM28XX_R32_VSCALELOW, (char *)buf, 2);
6ea54d93
DSL		 675 /* it seems that both H and V scalers must be active
676 to work correctly */
52c02fcd 677 mode = (h || v)? 0x30: 0x00;
74458e6c 678 }
41facaa4 679 return em28xx_write_reg_bits(dev, EM28XX_R26_COMPR, mode, 0x30);
a6c2ba28 680}
681
682/* FIXME: this only function read values from dev */
3acf2809 683int em28xx_resolution_set(struct em28xx *dev)
a6c2ba28 684{
685 int width, height;
686 width = norm_maxw(dev);
687 height = norm_maxh(dev) >> 1;
688
3acf2809
MCC		 689 em28xx_outfmt_set_yuv422(dev);
690 em28xx_accumulator_set(dev, 1, (width - 4) >> 2, 1, (height - 4) >> 2);
691 em28xx_capture_area_set(dev, 0, 0, width >> 2, height >> 2);
692 return em28xx_scaler_set(dev, dev->hscale, dev->vscale);
a6c2ba28 693}
694
3acf2809 695int em28xx_set_alternate(struct em28xx *dev)
a6c2ba28 696{
697 int errCode, prev_alt = dev->alt;
3687e1e6 698 int i;
44dc733c 699 unsigned int min_pkt_size = dev->width * 2 + 4;
3687e1e6 700
2c4a07b2 701 /* When image size is bigger than a certain value,
3687e1e6
MCC		 702 the frame size should be increased, otherwise, only
703 green screen will be received.
704 */
44dc733c 705 if (dev->width * 2 * dev->height > 720 * 240 * 2)
3687e1e6
MCC		 706 min_pkt_size *= 2;
707
2c4a07b2
SS		 708 for (i = 0; i < dev->num_alt; i++) {
709 /* stop when the selected alt setting offers enough bandwidth */
710 if (dev->alt_max_pkt_size[i] >= min_pkt_size) {
711 dev->alt = i;
3687e1e6 712 break;
2c4a07b2
SS		 713 /* otherwise make sure that we end up with the maximum bandwidth
714 because the min_pkt_size equation might be wrong...
715 */
716 } else if (dev->alt_max_pkt_size[i] >
717 dev->alt_max_pkt_size[dev->alt])
718 dev->alt = i;
719 }
a6c2ba28 720
721 if (dev->alt != prev_alt) {
3687e1e6
MCC		 722 em28xx_coredbg("minimum isoc packet size: %u (alt=%d)\n",
723 min_pkt_size, dev->alt);
a6c2ba28 724 dev->max_pkt_size = dev->alt_max_pkt_size[dev->alt];
3687e1e6
MCC		 725 em28xx_coredbg("setting alternate %d with wMaxPacketSize=%u\n",
726 dev->alt, dev->max_pkt_size);
a6c2ba28 727 errCode = usb_set_interface(dev->udev, 0, dev->alt);
728 if (errCode < 0) {
6ea54d93 729 em28xx_errdev("cannot change alternate number to %d (error=%i)\n",
3687e1e6 730 dev->alt, errCode);
a6c2ba28 731 return errCode;
732 }
733 }
734 return 0;
735}
579f72e4 736
c67ec53f
MCC		 737int em28xx_gpio_set(struct em28xx *dev, struct em28xx_reg_seq *gpio)
738{
739 int rc = 0;
740
741 if (!gpio)
742 return rc;
743
2fe3e2ee
MCC		 744 if (dev->mode != EM28XX_SUSPEND) {
745 em28xx_write_reg(dev, 0x48, 0x00);
746 if (dev->mode == EM28XX_ANALOG_MODE)
747 em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
748 else
749 em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
750 msleep(6);
751 }
c67ec53f
MCC		 752
753 /* Send GPIO reset sequences specified at board entry */
754 while (gpio->sleep >= 0) {
755 if (gpio->reg >= 0) {
756 rc = em28xx_write_reg_bits(dev,
757 gpio->reg,
758 gpio->val,
759 gpio->mask);
760 if (rc < 0)
761 return rc;
762 }
763 if (gpio->sleep > 0)
764 msleep(gpio->sleep);
765
766 gpio++;
767 }
768 return rc;
769}
770
771int em28xx_set_mode(struct em28xx *dev, enum em28xx_mode set_mode)
772{
773 if (dev->mode == set_mode)
774 return 0;
775
2fe3e2ee 776 if (set_mode == EM28XX_SUSPEND) {
c67ec53f 777 dev->mode = set_mode;
2fe3e2ee
MCC		 778
779 /* FIXME: add suspend support for ac97 */
780
781 return em28xx_gpio_set(dev, dev->board.suspend_gpio);
c67ec53f
MCC		 782 }
783
784 dev->mode = set_mode;
785
786 if (dev->mode == EM28XX_DIGITAL_MODE)
f502e861 787 return em28xx_gpio_set(dev, dev->board.dvb_gpio);
c67ec53f 788 else
f502e861 789 return em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
c67ec53f
MCC		 790}
791EXPORT_SYMBOL_GPL(em28xx_set_mode);
792
579f72e4
AT		 793/* ------------------------------------------------------------------
794 URB control
795 ------------------------------------------------------------------*/
796
797/*
798 * IRQ callback, called by URB callback
799 */
800static void em28xx_irq_callback(struct urb *urb)
801{
802 struct em28xx_dmaqueue *dma_q = urb->context;
803 struct em28xx *dev = container_of(dma_q, struct em28xx, vidq);
804 int rc, i;
805
806 /* Copy data from URB */
807 spin_lock(&dev->slock);
808 rc = dev->isoc_ctl.isoc_copy(dev, urb);
809 spin_unlock(&dev->slock);
810
811 /* Reset urb buffers */
812 for (i = 0; i < urb->number_of_packets; i++) {
813 urb->iso_frame_desc[i].status = 0;
814 urb->iso_frame_desc[i].actual_length = 0;
815 }
816 urb->status = 0;
817
818 urb->status = usb_submit_urb(urb, GFP_ATOMIC);
819 if (urb->status) {
4269a8ee
DH		 820 em28xx_isocdbg("urb resubmit failed (error=%i)\n",
821 urb->status);
579f72e4
AT		 822 }
823}
824
825/*
826 * Stop and Deallocate URBs
827 */
828void em28xx_uninit_isoc(struct em28xx *dev)
829{
830 struct urb *urb;
831 int i;
832
833 em28xx_isocdbg("em28xx: called em28xx_uninit_isoc\n");
834
835 dev->isoc_ctl.nfields = -1;
836 for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
837 urb = dev->isoc_ctl.urb[i];
838 if (urb) {
839 usb_kill_urb(urb);
840 usb_unlink_urb(urb);
841 if (dev->isoc_ctl.transfer_buffer[i]) {
842 usb_buffer_free(dev->udev,
6ea54d93
DSL		 843 urb->transfer_buffer_length,
844 dev->isoc_ctl.transfer_buffer[i],
845 urb->transfer_dma);
579f72e4
AT		 846 }
847 usb_free_urb(urb);
848 dev->isoc_ctl.urb[i] = NULL;
849 }
850 dev->isoc_ctl.transfer_buffer[i] = NULL;
851 }
852
853 kfree(dev->isoc_ctl.urb);
854 kfree(dev->isoc_ctl.transfer_buffer);
855
856 dev->isoc_ctl.urb = NULL;
857 dev->isoc_ctl.transfer_buffer = NULL;
858 dev->isoc_ctl.num_bufs = 0;
859
860 em28xx_capture_start(dev, 0);
861}
862EXPORT_SYMBOL_GPL(em28xx_uninit_isoc);
863
864/*
865 * Allocate URBs and start IRQ
866 */
867int em28xx_init_isoc(struct em28xx *dev, int max_packets,
868 int num_bufs, int max_pkt_size,
c67ec53f 869 int (*isoc_copy) (struct em28xx *dev, struct urb *urb))
579f72e4
AT		 870{
871 struct em28xx_dmaqueue *dma_q = &dev->vidq;
872 int i;
873 int sb_size, pipe;
874 struct urb *urb;
875 int j, k;
876 int rc;
877
878 em28xx_isocdbg("em28xx: called em28xx_prepare_isoc\n");
879
880 /* De-allocates all pending stuff */
881 em28xx_uninit_isoc(dev);
882
883 dev->isoc_ctl.isoc_copy = isoc_copy;
884 dev->isoc_ctl.num_bufs = num_bufs;
885
886 dev->isoc_ctl.urb = kzalloc(sizeof(void *)*num_bufs, GFP_KERNEL);
887 if (!dev->isoc_ctl.urb) {
888 em28xx_errdev("cannot alloc memory for usb buffers\n");
889 return -ENOMEM;
890 }
891
892 dev->isoc_ctl.transfer_buffer = kzalloc(sizeof(void *)*num_bufs,
893 GFP_KERNEL);
094f9b4b 894 if (!dev->isoc_ctl.transfer_buffer) {
579f72e4
AT		 895 em28xx_errdev("cannot allocate memory for usbtransfer\n");
896 kfree(dev->isoc_ctl.urb);
897 return -ENOMEM;
898 }
899
900 dev->isoc_ctl.max_pkt_size = max_pkt_size;
901 dev->isoc_ctl.buf = NULL;
902
903 sb_size = max_packets * dev->isoc_ctl.max_pkt_size;
904
905 /* allocate urbs and transfer buffers */
906 for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
907 urb = usb_alloc_urb(max_packets, GFP_KERNEL);
908 if (!urb) {
909 em28xx_err("cannot alloc isoc_ctl.urb %i\n", i);
910 em28xx_uninit_isoc(dev);
911 return -ENOMEM;
912 }
913 dev->isoc_ctl.urb[i] = urb;
914
915 dev->isoc_ctl.transfer_buffer[i] = usb_buffer_alloc(dev->udev,
916 sb_size, GFP_KERNEL, &urb->transfer_dma);
917 if (!dev->isoc_ctl.transfer_buffer[i]) {
918 em28xx_err("unable to allocate %i bytes for transfer"
919 " buffer %i%s\n",
920 sb_size, i,
921 in_interrupt()?" while in int":"");
922 em28xx_uninit_isoc(dev);
923 return -ENOMEM;
924 }
925 memset(dev->isoc_ctl.transfer_buffer[i], 0, sb_size);
926
927 /* FIXME: this is a hack - should be
928 'desc.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK'
929 should also be using 'desc.bInterval'
930 */
6ea54d93 931 pipe = usb_rcvisocpipe(dev->udev,
c67ec53f 932 dev->mode == EM28XX_ANALOG_MODE ? 0x82 : 0x84);
6ea54d93 933
579f72e4
AT		 934 usb_fill_int_urb(urb, dev->udev, pipe,
935 dev->isoc_ctl.transfer_buffer[i], sb_size,
936 em28xx_irq_callback, dma_q, 1);
937
938 urb->number_of_packets = max_packets;
939 urb->transfer_flags = URB_ISO_ASAP;
940
941 k = 0;
942 for (j = 0; j < max_packets; j++) {
943 urb->iso_frame_desc[j].offset = k;
944 urb->iso_frame_desc[j].length =
945 dev->isoc_ctl.max_pkt_size;
946 k += dev->isoc_ctl.max_pkt_size;
947 }
948 }
949
950 init_waitqueue_head(&dma_q->wq);
951
c67ec53f 952 em28xx_capture_start(dev, 1);
579f72e4
AT		 953
954 /* submit urbs and enables IRQ */
955 for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
956 rc = usb_submit_urb(dev->isoc_ctl.urb[i], GFP_ATOMIC);
957 if (rc) {
958 em28xx_err("submit of urb %i failed (error=%i)\n", i,
959 rc);
960 em28xx_uninit_isoc(dev);
961 return rc;
962 }
963 }
964
965 return 0;
966}
967EXPORT_SYMBOL_GPL(em28xx_init_isoc);
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