]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/media/video/gspca/ov519.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
V4L/DVB: gspca_ov519: add support for the button on ov519 based cams
[mirror_ubuntu-artful-kernel.git] / drivers / media / video / gspca / ov519.c
CommitLineData
6a7eba24
JFM		 1/**
2 * OV519 driver
3 *
4 * Copyright (C) 2008 Jean-Francois Moine (http://moinejf.free.fr)
b46aaa02 5 * Copyright (C) 2009 Hans de Goede <hdegoede@redhat.com>
6a7eba24 6 *
2961e875
RB		 7 * This module is adapted from the ov51x-jpeg package, which itself
8 * was adapted from the ov511 driver.
9 *
10 * Original copyright for the ov511 driver is:
11 *
b46aaa02 12 * Copyright (c) 1999-2006 Mark W. McClelland
2961e875 13 * Support for OV519, OV8610 Copyright (c) 2003 Joerg Heckenbach
b46aaa02
HG		 14 * Many improvements by Bret Wallach <bwallac1@san.rr.com>
15 * Color fixes by by Orion Sky Lawlor <olawlor@acm.org> (2/26/2000)
16 * OV7620 fixes by Charl P. Botha <cpbotha@ieee.org>
17 * Changes by Claudio Matsuoka <claudio@conectiva.com>
2961e875
RB		 18 *
19 * ov51x-jpeg original copyright is:
20 *
21 * Copyright (c) 2004-2007 Romain Beauxis <toots@rastageeks.org>
22 * Support for OV7670 sensors was contributed by Sam Skipsey <aoanla@yahoo.com>
6a7eba24
JFM		 23 *
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License as published by
26 * the Free Software Foundation; either version 2 of the License, or
27 * any later version.
28 *
29 * This program is distributed in the hope that it will be useful,
30 * but WITHOUT ANY WARRANTY; without even the implied warranty of
31 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
32 * GNU General Public License for more details.
33 *
34 * You should have received a copy of the GNU General Public License
35 * along with this program; if not, write to the Free Software
36 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
37 *
38 */
39#define MODULE_NAME "ov519"
40
417a4d26 41#include <linux/input.h>
6a7eba24
JFM		 42#include "gspca.h"
43
6a7eba24
JFM		 44MODULE_AUTHOR("Jean-Francois Moine <http://moinejf.free.fr>");
45MODULE_DESCRIPTION("OV519 USB Camera Driver");
46MODULE_LICENSE("GPL");
47
48/* global parameters */
49static int frame_rate;
50
51/* Number of times to retry a failed I2C transaction. Increase this if you
52 * are getting "Failed to read sensor ID..." */
53static int i2c_detect_tries = 10;
54
55/* ov519 device descriptor */
56struct sd {
57 struct gspca_dev gspca_dev; /* !! must be the first item */
58
92918a53
HG		 59 __u8 packet_nr;
60
49809d6a
HG		 61 char bridge;
62#define BRIDGE_OV511 0
63#define BRIDGE_OV511PLUS 1
64#define BRIDGE_OV518 2
65#define BRIDGE_OV518PLUS 3
66#define BRIDGE_OV519 4
635118d5 67#define BRIDGE_OVFX2 5
a511ba94 68#define BRIDGE_W9968CF 6
9e4d8258
HG		 69#define BRIDGE_MASK 7
70
71 char invert_led;
72#define BRIDGE_INVERT_LED 8
49809d6a 73
417a4d26
HG		 74 char snapshot_pressed;
75 char snapshot_needs_reset;
76
6a7eba24 77 /* Determined by sensor type */
ac40b1fa 78 __u8 sif;
6a7eba24 79
ac40b1fa
JFM		 80 __u8 brightness;
81 __u8 contrast;
82 __u8 colors;
0cd6759d
JFM		 83 __u8 hflip;
84 __u8 vflip;
02ab18b0
HG		 85 __u8 autobrightness;
86 __u8 freq;
79b35902
HG		 87 __u8 quality;
88#define QUALITY_MIN 50
89#define QUALITY_MAX 70
90#define QUALITY_DEF 50
6a7eba24 91
ac40b1fa 92 __u8 stopped; /* Streaming is temporarily paused */
6a7eba24 93
1876bb92
HG		 94 __u8 frame_rate; /* current Framerate */
95 __u8 clockdiv; /* clockdiv override */
6a7eba24
JFM		 96
97 char sensor; /* Type of image sensor chip (SEN_*) */
98#define SEN_UNKNOWN 0
635118d5
HG		 99#define SEN_OV2610 1
100#define SEN_OV3610 2
101#define SEN_OV6620 3
102#define SEN_OV6630 4
103#define SEN_OV66308AF 5
104#define SEN_OV7610 6
105#define SEN_OV7620 7
859cc470
HG		 106#define SEN_OV7620AE 8
107#define SEN_OV7640 9
035d3a3d
HG		 108#define SEN_OV7648 10
109#define SEN_OV7670 11
110#define SEN_OV76BE 12
111#define SEN_OV8610 13
a511ba94
HG		 112
113 u8 sensor_addr;
114 int sensor_width;
115 int sensor_height;
fb1f9020 116 int sensor_reg_cache[256];
79b35902
HG		 117
118 u8 *jpeg_hdr;
6a7eba24
JFM		 119};
120
a511ba94
HG		 121/* Note this is a bit of a hack, but the w9968cf driver needs the code for all
122 the ov sensors which is already present here. When we have the time we
123 really should move the sensor drivers to v4l2 sub drivers. */
124#include "w996Xcf.c"
125
6a7eba24
JFM		 126/* V4L2 controls supported by the driver */
127static int sd_setbrightness(struct gspca_dev *gspca_dev, __s32 val);
128static int sd_getbrightness(struct gspca_dev *gspca_dev, __s32 *val);
129static int sd_setcontrast(struct gspca_dev *gspca_dev, __s32 val);
130static int sd_getcontrast(struct gspca_dev *gspca_dev, __s32 *val);
131static int sd_setcolors(struct gspca_dev *gspca_dev, __s32 val);
132static int sd_getcolors(struct gspca_dev *gspca_dev, __s32 *val);
0cd6759d
JFM		 133static int sd_sethflip(struct gspca_dev *gspca_dev, __s32 val);
134static int sd_gethflip(struct gspca_dev *gspca_dev, __s32 *val);
135static int sd_setvflip(struct gspca_dev *gspca_dev, __s32 val);
136static int sd_getvflip(struct gspca_dev *gspca_dev, __s32 *val);
02ab18b0
HG		 137static int sd_setautobrightness(struct gspca_dev *gspca_dev, __s32 val);
138static int sd_getautobrightness(struct gspca_dev *gspca_dev, __s32 *val);
139static int sd_setfreq(struct gspca_dev *gspca_dev, __s32 val);
140static int sd_getfreq(struct gspca_dev *gspca_dev, __s32 *val);
49809d6a
HG		 141static void setbrightness(struct gspca_dev *gspca_dev);
142static void setcontrast(struct gspca_dev *gspca_dev);
143static void setcolors(struct gspca_dev *gspca_dev);
02ab18b0
HG		 144static void setautobrightness(struct sd *sd);
145static void setfreq(struct sd *sd);
6a7eba24 146
02ab18b0 147static const struct ctrl sd_ctrls[] = {
d02134dd 148#define BRIGHTNESS_IDX 0
6a7eba24
JFM		 149 {
150 {
151 .id = V4L2_CID_BRIGHTNESS,
152 .type = V4L2_CTRL_TYPE_INTEGER,
153 .name = "Brightness",
154 .minimum = 0,
155 .maximum = 255,
156 .step = 1,
594f5b8b
JFM		 157#define BRIGHTNESS_DEF 127
158 .default_value = BRIGHTNESS_DEF,
6a7eba24
JFM		 159 },
160 .set = sd_setbrightness,
161 .get = sd_getbrightness,
162 },
d02134dd 163#define CONTRAST_IDX 1
6a7eba24
JFM		 164 {
165 {
166 .id = V4L2_CID_CONTRAST,
167 .type = V4L2_CTRL_TYPE_INTEGER,
168 .name = "Contrast",
169 .minimum = 0,
170 .maximum = 255,
171 .step = 1,
594f5b8b
JFM		 172#define CONTRAST_DEF 127
173 .default_value = CONTRAST_DEF,
6a7eba24
JFM		 174 },
175 .set = sd_setcontrast,
176 .get = sd_getcontrast,
177 },
d02134dd 178#define COLOR_IDX 2
6a7eba24
JFM		 179 {
180 {
181 .id = V4L2_CID_SATURATION,
182 .type = V4L2_CTRL_TYPE_INTEGER,
594f5b8b 183 .name = "Color",
6a7eba24
JFM		 184 .minimum = 0,
185 .maximum = 255,
186 .step = 1,
594f5b8b
JFM		 187#define COLOR_DEF 127
188 .default_value = COLOR_DEF,
6a7eba24
JFM		 189 },
190 .set = sd_setcolors,
191 .get = sd_getcolors,
192 },
02ab18b0 193/* The flip controls work with ov7670 only */
de00448f 194#define HFLIP_IDX 3
0cd6759d
JFM		 195 {
196 {
197 .id = V4L2_CID_HFLIP,
198 .type = V4L2_CTRL_TYPE_BOOLEAN,
199 .name = "Mirror",
200 .minimum = 0,
201 .maximum = 1,
202 .step = 1,
203#define HFLIP_DEF 0
204 .default_value = HFLIP_DEF,
205 },
206 .set = sd_sethflip,
207 .get = sd_gethflip,
208 },
de00448f 209#define VFLIP_IDX 4
0cd6759d
JFM		 210 {
211 {
212 .id = V4L2_CID_VFLIP,
213 .type = V4L2_CTRL_TYPE_BOOLEAN,
214 .name = "Vflip",
215 .minimum = 0,
216 .maximum = 1,
217 .step = 1,
218#define VFLIP_DEF 0
219 .default_value = VFLIP_DEF,
220 },
221 .set = sd_setvflip,
222 .get = sd_getvflip,
223 },
02ab18b0
HG		 224#define AUTOBRIGHT_IDX 5
225 {
226 {
227 .id = V4L2_CID_AUTOBRIGHTNESS,
228 .type = V4L2_CTRL_TYPE_BOOLEAN,
229 .name = "Auto Brightness",
230 .minimum = 0,
231 .maximum = 1,
232 .step = 1,
233#define AUTOBRIGHT_DEF 1
234 .default_value = AUTOBRIGHT_DEF,
235 },
236 .set = sd_setautobrightness,
237 .get = sd_getautobrightness,
238 },
239#define FREQ_IDX 6
240 {
241 {
242 .id = V4L2_CID_POWER_LINE_FREQUENCY,
243 .type = V4L2_CTRL_TYPE_MENU,
244 .name = "Light frequency filter",
245 .minimum = 0,
246 .maximum = 2, /* 0: 0, 1: 50Hz, 2:60Hz */
247 .step = 1,
248#define FREQ_DEF 0
249 .default_value = FREQ_DEF,
250 },
251 .set = sd_setfreq,
252 .get = sd_getfreq,
253 },
254#define OV7670_FREQ_IDX 7
255 {
256 {
257 .id = V4L2_CID_POWER_LINE_FREQUENCY,
258 .type = V4L2_CTRL_TYPE_MENU,
259 .name = "Light frequency filter",
260 .minimum = 0,
261 .maximum = 3, /* 0: 0, 1: 50Hz, 2:60Hz 3: Auto Hz */
262 .step = 1,
263#define OV7670_FREQ_DEF 3
264 .default_value = OV7670_FREQ_DEF,
265 },
266 .set = sd_setfreq,
267 .get = sd_getfreq,
268 },
6a7eba24
JFM		 269};
270
49809d6a 271static const struct v4l2_pix_format ov519_vga_mode[] = {
c2446b3e
JFM		 272 {320, 240, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
273 .bytesperline = 320,
594f5b8b 274 .sizeimage = 320 * 240 * 3 / 8 + 590,
c2446b3e
JFM		 275 .colorspace = V4L2_COLORSPACE_JPEG,
276 .priv = 1},
277 {640, 480, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
278 .bytesperline = 640,
279 .sizeimage = 640 * 480 * 3 / 8 + 590,
280 .colorspace = V4L2_COLORSPACE_JPEG,
281 .priv = 0},
6a7eba24 282};
49809d6a 283static const struct v4l2_pix_format ov519_sif_mode[] = {
124cc9c0
HG		 284 {160, 120, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
285 .bytesperline = 160,
286 .sizeimage = 160 * 120 * 3 / 8 + 590,
287 .colorspace = V4L2_COLORSPACE_JPEG,
288 .priv = 3},
c2446b3e
JFM		 289 {176, 144, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
290 .bytesperline = 176,
594f5b8b 291 .sizeimage = 176 * 144 * 3 / 8 + 590,
c2446b3e
JFM		 292 .colorspace = V4L2_COLORSPACE_JPEG,
293 .priv = 1},
124cc9c0
HG		 294 {320, 240, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
295 .bytesperline = 320,
296 .sizeimage = 320 * 240 * 3 / 8 + 590,
297 .colorspace = V4L2_COLORSPACE_JPEG,
298 .priv = 2},
c2446b3e
JFM		 299 {352, 288, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
300 .bytesperline = 352,
594f5b8b 301 .sizeimage = 352 * 288 * 3 / 8 + 590,
c2446b3e
JFM		 302 .colorspace = V4L2_COLORSPACE_JPEG,
303 .priv = 0},
6a7eba24
JFM		 304};
305
b282d873
HG		 306/* Note some of the sizeimage values for the ov511 / ov518 may seem
307 larger then necessary, however they need to be this big as the ov511 /
308 ov518 always fills the entire isoc frame, using 0 padding bytes when
309 it doesn't have any data. So with low framerates the amount of data
310 transfered can become quite large (libv4l will remove all the 0 padding
311 in userspace). */
49809d6a
HG		 312static const struct v4l2_pix_format ov518_vga_mode[] = {
313 {320, 240, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
314 .bytesperline = 320,
b282d873 315 .sizeimage = 320 * 240 * 3,
49809d6a
HG		 316 .colorspace = V4L2_COLORSPACE_JPEG,
317 .priv = 1},
318 {640, 480, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
319 .bytesperline = 640,
b282d873 320 .sizeimage = 640 * 480 * 2,
49809d6a
HG		 321 .colorspace = V4L2_COLORSPACE_JPEG,
322 .priv = 0},
323};
324static const struct v4l2_pix_format ov518_sif_mode[] = {
124cc9c0
HG		 325 {160, 120, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
326 .bytesperline = 160,
b282d873 327 .sizeimage = 70000,
124cc9c0
HG		 328 .colorspace = V4L2_COLORSPACE_JPEG,
329 .priv = 3},
49809d6a
HG		 330 {176, 144, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
331 .bytesperline = 176,
b282d873 332 .sizeimage = 70000,
49809d6a
HG		 333 .colorspace = V4L2_COLORSPACE_JPEG,
334 .priv = 1},
124cc9c0
HG		 335 {320, 240, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
336 .bytesperline = 320,
b282d873 337 .sizeimage = 320 * 240 * 3,
124cc9c0
HG		 338 .colorspace = V4L2_COLORSPACE_JPEG,
339 .priv = 2},
49809d6a
HG		 340 {352, 288, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
341 .bytesperline = 352,
b282d873 342 .sizeimage = 352 * 288 * 3,
49809d6a
HG		 343 .colorspace = V4L2_COLORSPACE_JPEG,
344 .priv = 0},
345};
346
1876bb92
HG		 347static const struct v4l2_pix_format ov511_vga_mode[] = {
348 {320, 240, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
349 .bytesperline = 320,
350 .sizeimage = 320 * 240 * 3,
351 .colorspace = V4L2_COLORSPACE_JPEG,
352 .priv = 1},
353 {640, 480, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
354 .bytesperline = 640,
355 .sizeimage = 640 * 480 * 2,
356 .colorspace = V4L2_COLORSPACE_JPEG,
357 .priv = 0},
358};
359static const struct v4l2_pix_format ov511_sif_mode[] = {
360 {160, 120, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
361 .bytesperline = 160,
b282d873 362 .sizeimage = 70000,
1876bb92
HG		 363 .colorspace = V4L2_COLORSPACE_JPEG,
364 .priv = 3},
365 {176, 144, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
366 .bytesperline = 176,
b282d873 367 .sizeimage = 70000,
1876bb92
HG		 368 .colorspace = V4L2_COLORSPACE_JPEG,
369 .priv = 1},
370 {320, 240, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
371 .bytesperline = 320,
372 .sizeimage = 320 * 240 * 3,
373 .colorspace = V4L2_COLORSPACE_JPEG,
374 .priv = 2},
375 {352, 288, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
376 .bytesperline = 352,
377 .sizeimage = 352 * 288 * 3,
378 .colorspace = V4L2_COLORSPACE_JPEG,
379 .priv = 0},
380};
49809d6a 381
635118d5
HG		 382static const struct v4l2_pix_format ovfx2_vga_mode[] = {
383 {320, 240, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
384 .bytesperline = 320,
385 .sizeimage = 320 * 240,
386 .colorspace = V4L2_COLORSPACE_SRGB,
387 .priv = 1},
388 {640, 480, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
389 .bytesperline = 640,
390 .sizeimage = 640 * 480,
391 .colorspace = V4L2_COLORSPACE_SRGB,
392 .priv = 0},
393};
394static const struct v4l2_pix_format ovfx2_cif_mode[] = {
395 {160, 120, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
396 .bytesperline = 160,
397 .sizeimage = 160 * 120,
398 .colorspace = V4L2_COLORSPACE_SRGB,
399 .priv = 3},
400 {176, 144, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
401 .bytesperline = 176,
402 .sizeimage = 176 * 144,
403 .colorspace = V4L2_COLORSPACE_SRGB,
404 .priv = 1},
405 {320, 240, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
406 .bytesperline = 320,
407 .sizeimage = 320 * 240,
408 .colorspace = V4L2_COLORSPACE_SRGB,
409 .priv = 2},
410 {352, 288, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
411 .bytesperline = 352,
412 .sizeimage = 352 * 288,
413 .colorspace = V4L2_COLORSPACE_SRGB,
414 .priv = 0},
415};
416static const struct v4l2_pix_format ovfx2_ov2610_mode[] = {
417 {1600, 1200, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
418 .bytesperline = 1600,
419 .sizeimage = 1600 * 1200,
420 .colorspace = V4L2_COLORSPACE_SRGB},
421};
422static const struct v4l2_pix_format ovfx2_ov3610_mode[] = {
635118d5
HG		 423 {640, 480, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
424 .bytesperline = 640,
425 .sizeimage = 640 * 480,
b46aaa02
HG		 426 .colorspace = V4L2_COLORSPACE_SRGB,
427 .priv = 1},
428 {800, 600, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
429 .bytesperline = 800,
430 .sizeimage = 800 * 600,
431 .colorspace = V4L2_COLORSPACE_SRGB,
432 .priv = 1},
433 {1024, 768, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
434 .bytesperline = 1024,
435 .sizeimage = 1024 * 768,
436 .colorspace = V4L2_COLORSPACE_SRGB,
437 .priv = 1},
438 {1600, 1200, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
439 .bytesperline = 1600,
440 .sizeimage = 1600 * 1200,
441 .colorspace = V4L2_COLORSPACE_SRGB,
442 .priv = 0},
443 {2048, 1536, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
444 .bytesperline = 2048,
445 .sizeimage = 2048 * 1536,
446 .colorspace = V4L2_COLORSPACE_SRGB,
447 .priv = 0},
635118d5
HG		 448};
449
450
49809d6a 451/* Registers common to OV511 / OV518 */
1876bb92 452#define R51x_FIFO_PSIZE 0x30 /* 2 bytes wide w/ OV518(+) */
49809d6a 453#define R51x_SYS_RESET 0x50
1876bb92
HG		 454 /* Reset type flags */
455 #define OV511_RESET_OMNICE 0x08
49809d6a
HG		 456#define R51x_SYS_INIT 0x53
457#define R51x_SYS_SNAP 0x52
458#define R51x_SYS_CUST_ID 0x5F
459#define R51x_COMP_LUT_BEGIN 0x80
460
461/* OV511 Camera interface register numbers */
1876bb92
HG		 462#define R511_CAM_DELAY 0x10
463#define R511_CAM_EDGE 0x11
464#define R511_CAM_PXCNT 0x12
465#define R511_CAM_LNCNT 0x13
466#define R511_CAM_PXDIV 0x14
467#define R511_CAM_LNDIV 0x15
468#define R511_CAM_UV_EN 0x16
469#define R511_CAM_LINE_MODE 0x17
470#define R511_CAM_OPTS 0x18
471
472#define R511_SNAP_FRAME 0x19
473#define R511_SNAP_PXCNT 0x1A
474#define R511_SNAP_LNCNT 0x1B
475#define R511_SNAP_PXDIV 0x1C
476#define R511_SNAP_LNDIV 0x1D
477#define R511_SNAP_UV_EN 0x1E
478#define R511_SNAP_UV_EN 0x1E
479#define R511_SNAP_OPTS 0x1F
480
481#define R511_DRAM_FLOW_CTL 0x20
482#define R511_FIFO_OPTS 0x31
483#define R511_I2C_CTL 0x40
49809d6a 484#define R511_SYS_LED_CTL 0x55 /* OV511+ only */
1876bb92
HG		 485#define R511_COMP_EN 0x78
486#define R511_COMP_LUT_EN 0x79
49809d6a
HG		 487
488/* OV518 Camera interface register numbers */
489#define R518_GPIO_OUT 0x56 /* OV518(+) only */
490#define R518_GPIO_CTL 0x57 /* OV518(+) only */
491
6a7eba24 492/* OV519 Camera interface register numbers */
ac40b1fa
JFM		 493#define OV519_R10_H_SIZE 0x10
494#define OV519_R11_V_SIZE 0x11
495#define OV519_R12_X_OFFSETL 0x12
496#define OV519_R13_X_OFFSETH 0x13
497#define OV519_R14_Y_OFFSETL 0x14
498#define OV519_R15_Y_OFFSETH 0x15
499#define OV519_R16_DIVIDER 0x16
500#define OV519_R20_DFR 0x20
501#define OV519_R25_FORMAT 0x25
6a7eba24
JFM		 502
503/* OV519 System Controller register numbers */
504#define OV519_SYS_RESET1 0x51
505#define OV519_SYS_EN_CLK1 0x54
506
507#define OV519_GPIO_DATA_OUT0 0x71
508#define OV519_GPIO_IO_CTRL0 0x72
509
510#define OV511_ENDPOINT_ADDRESS 1 /* Isoc endpoint number */
511
b46aaa02
HG		 512/*
513 * The FX2 chip does not give us a zero length read at end of frame.
514 * It does, however, give a short read at the end of a frame, if
515 * neccessary, rather than run two frames together.
516 *
517 * By choosing the right bulk transfer size, we are guaranteed to always
518 * get a short read for the last read of each frame. Frame sizes are
519 * always a composite number (width * height, or a multiple) so if we
520 * choose a prime number, we are guaranteed that the last read of a
521 * frame will be short.
522 *
523 * But it isn't that easy: the 2.6 kernel requires a multiple of 4KB,
524 * otherwise EOVERFLOW "babbling" errors occur. I have not been able
525 * to figure out why. [PMiller]
526 *
527 * The constant (13 * 4096) is the largest "prime enough" number less than 64KB.
528 *
529 * It isn't enough to know the number of bytes per frame, in case we
530 * have data dropouts or buffer overruns (even though the FX2 double
531 * buffers, there are some pretty strict real time constraints for
532 * isochronous transfer for larger frame sizes).
533 */
534#define OVFX2_BULK_SIZE (13 * 4096)
535
6a7eba24
JFM		 536/* I2C registers */
537#define R51x_I2C_W_SID 0x41
538#define R51x_I2C_SADDR_3 0x42
539#define R51x_I2C_SADDR_2 0x43
540#define R51x_I2C_R_SID 0x44
541#define R51x_I2C_DATA 0x45
542#define R518_I2C_CTL 0x47 /* OV518(+) only */
b46aaa02 543#define OVFX2_I2C_ADDR 0x00
6a7eba24
JFM		 544
545/* I2C ADDRESSES */
546#define OV7xx0_SID 0x42
229bb7dc 547#define OV_HIRES_SID 0x60 /* OV9xxx / OV2xxx / OV3xxx */
6a7eba24
JFM		 548#define OV8xx0_SID 0xa0
549#define OV6xx0_SID 0xc0
550
551/* OV7610 registers */
552#define OV7610_REG_GAIN 0x00 /* gain setting (5:0) */
49809d6a
HG		 553#define OV7610_REG_BLUE 0x01 /* blue channel balance */
554#define OV7610_REG_RED 0x02 /* red channel balance */
6a7eba24
JFM		 555#define OV7610_REG_SAT 0x03 /* saturation */
556#define OV8610_REG_HUE 0x04 /* 04 reserved */
557#define OV7610_REG_CNT 0x05 /* Y contrast */
558#define OV7610_REG_BRT 0x06 /* Y brightness */
559#define OV7610_REG_COM_C 0x14 /* misc common regs */
560#define OV7610_REG_ID_HIGH 0x1c /* manufacturer ID MSB */
561#define OV7610_REG_ID_LOW 0x1d /* manufacturer ID LSB */
562#define OV7610_REG_COM_I 0x29 /* misc settings */
563
564/* OV7670 registers */
565#define OV7670_REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
566#define OV7670_REG_BLUE 0x01 /* blue gain */
567#define OV7670_REG_RED 0x02 /* red gain */
568#define OV7670_REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
569#define OV7670_REG_COM1 0x04 /* Control 1 */
570#define OV7670_REG_AECHH 0x07 /* AEC MS 5 bits */
571#define OV7670_REG_COM3 0x0c /* Control 3 */
572#define OV7670_REG_COM4 0x0d /* Control 4 */
573#define OV7670_REG_COM5 0x0e /* All "reserved" */
574#define OV7670_REG_COM6 0x0f /* Control 6 */
575#define OV7670_REG_AECH 0x10 /* More bits of AEC value */
576#define OV7670_REG_CLKRC 0x11 /* Clock control */
577#define OV7670_REG_COM7 0x12 /* Control 7 */
578#define OV7670_COM7_FMT_VGA 0x00
579#define OV7670_COM7_YUV 0x00 /* YUV */
580#define OV7670_COM7_FMT_QVGA 0x10 /* QVGA format */
581#define OV7670_COM7_FMT_MASK 0x38
582#define OV7670_COM7_RESET 0x80 /* Register reset */
583#define OV7670_REG_COM8 0x13 /* Control 8 */
584#define OV7670_COM8_AEC 0x01 /* Auto exposure enable */
585#define OV7670_COM8_AWB 0x02 /* White balance enable */
586#define OV7670_COM8_AGC 0x04 /* Auto gain enable */
587#define OV7670_COM8_BFILT 0x20 /* Band filter enable */
588#define OV7670_COM8_AECSTEP 0x40 /* Unlimited AEC step size */
589#define OV7670_COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
590#define OV7670_REG_COM9 0x14 /* Control 9 - gain ceiling */
591#define OV7670_REG_COM10 0x15 /* Control 10 */
592#define OV7670_REG_HSTART 0x17 /* Horiz start high bits */
593#define OV7670_REG_HSTOP 0x18 /* Horiz stop high bits */
594#define OV7670_REG_VSTART 0x19 /* Vert start high bits */
595#define OV7670_REG_VSTOP 0x1a /* Vert stop high bits */
596#define OV7670_REG_MVFP 0x1e /* Mirror / vflip */
0cd6759d 597#define OV7670_MVFP_VFLIP 0x10 /* vertical flip */
6a7eba24
JFM		 598#define OV7670_MVFP_MIRROR 0x20 /* Mirror image */
599#define OV7670_REG_AEW 0x24 /* AGC upper limit */
600#define OV7670_REG_AEB 0x25 /* AGC lower limit */
601#define OV7670_REG_VPT 0x26 /* AGC/AEC fast mode op region */
602#define OV7670_REG_HREF 0x32 /* HREF pieces */
603#define OV7670_REG_TSLB 0x3a /* lots of stuff */
604#define OV7670_REG_COM11 0x3b /* Control 11 */
605#define OV7670_COM11_EXP 0x02
606#define OV7670_COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */
607#define OV7670_REG_COM12 0x3c /* Control 12 */
608#define OV7670_REG_COM13 0x3d /* Control 13 */
609#define OV7670_COM13_GAMMA 0x80 /* Gamma enable */
610#define OV7670_COM13_UVSAT 0x40 /* UV saturation auto adjustment */
611#define OV7670_REG_COM14 0x3e /* Control 14 */
612#define OV7670_REG_EDGE 0x3f /* Edge enhancement factor */
613#define OV7670_REG_COM15 0x40 /* Control 15 */
614#define OV7670_COM15_R00FF 0xc0 /* 00 to FF */
615#define OV7670_REG_COM16 0x41 /* Control 16 */
616#define OV7670_COM16_AWBGAIN 0x08 /* AWB gain enable */
617#define OV7670_REG_BRIGHT 0x55 /* Brightness */
618#define OV7670_REG_CONTRAS 0x56 /* Contrast control */
619#define OV7670_REG_GFIX 0x69 /* Fix gain control */
620#define OV7670_REG_RGB444 0x8c /* RGB 444 control */
621#define OV7670_REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */
622#define OV7670_REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
623#define OV7670_REG_BD50MAX 0xa5 /* 50hz banding step limit */
624#define OV7670_REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
625#define OV7670_REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
626#define OV7670_REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
627#define OV7670_REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
628#define OV7670_REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */
629#define OV7670_REG_BD60MAX 0xab /* 60hz banding step limit */
630
4202f71c
JFM		 631struct ov_regvals {
632 __u8 reg;
633 __u8 val;
634};
635struct ov_i2c_regvals {
636 __u8 reg;
637 __u8 val;
638};
639
635118d5
HG		 640/* Settings for OV2610 camera chip */
641static const struct ov_i2c_regvals norm_2610[] =
642{
b46aaa02 643 { 0x12, 0x80 }, /* reset */
635118d5
HG		 644};
645
646static const struct ov_i2c_regvals norm_3620b[] =
647{
648 /*
649 * From the datasheet: "Note that after writing to register COMH
650 * (0x12) to change the sensor mode, registers related to the
651 * sensor’s cropping window will be reset back to their default
652 * values."
653 *
654 * "wait 4096 external clock ... to make sure the sensor is
655 * stable and ready to access registers" i.e. 160us at 24MHz
656 */
657
658 { 0x12, 0x80 }, /* COMH reset */
659 { 0x12, 0x00 }, /* QXGA, master */
660
661 /*
662 * 11 CLKRC "Clock Rate Control"
663 * [7] internal frequency doublers: on
664 * [6] video port mode: master
665 * [5:0] clock divider: 1
666 */
667 { 0x11, 0x80 },
668
669 /*
670 * 13 COMI "Common Control I"
671 * = 192 (0xC0) 11000000
672 * COMI[7] "AEC speed selection"
673 * = 1 (0x01) 1....... "Faster AEC correction"
674 * COMI[6] "AEC speed step selection"
675 * = 1 (0x01) .1...... "Big steps, fast"
676 * COMI[5] "Banding filter on off"
677 * = 0 (0x00) ..0..... "Off"
678 * COMI[4] "Banding filter option"
679 * = 0 (0x00) ...0.... "Main clock is 48 MHz and
680 * the PLL is ON"
681 * COMI[3] "Reserved"
682 * = 0 (0x00) ....0...
683 * COMI[2] "AGC auto manual control selection"
684 * = 0 (0x00) .....0.. "Manual"
685 * COMI[1] "AWB auto manual control selection"
686 * = 0 (0x00) ......0. "Manual"
687 * COMI[0] "Exposure control"
688 * = 0 (0x00) .......0 "Manual"
689 */
690 { 0x13, 0xC0 },
691
692 /*
693 * 09 COMC "Common Control C"
694 * = 8 (0x08) 00001000
695 * COMC[7:5] "Reserved"
696 * = 0 (0x00) 000.....
697 * COMC[4] "Sleep Mode Enable"
698 * = 0 (0x00) ...0.... "Normal mode"
699 * COMC[3:2] "Sensor sampling reset timing selection"
700 * = 2 (0x02) ....10.. "Longer reset time"
701 * COMC[1:0] "Output drive current select"
702 * = 0 (0x00) ......00 "Weakest"
703 */
704 { 0x09, 0x08 },
705
706 /*
707 * 0C COMD "Common Control D"
708 * = 8 (0x08) 00001000
709 * COMD[7] "Reserved"
710 * = 0 (0x00) 0.......
711 * COMD[6] "Swap MSB and LSB at the output port"
712 * = 0 (0x00) .0...... "False"
713 * COMD[5:3] "Reserved"
714 * = 1 (0x01) ..001...
715 * COMD[2] "Output Average On Off"
716 * = 0 (0x00) .....0.. "Output Normal"
717 * COMD[1] "Sensor precharge voltage selection"
718 * = 0 (0x00) ......0. "Selects internal
719 * reference precharge
720 * voltage"
721 * COMD[0] "Snapshot option"
722 * = 0 (0x00) .......0 "Enable live video output
723 * after snapshot sequence"
724 */
725 { 0x0c, 0x08 },
726
727 /*
728 * 0D COME "Common Control E"
729 * = 161 (0xA1) 10100001
730 * COME[7] "Output average option"
731 * = 1 (0x01) 1....... "Output average of 4 pixels"
732 * COME[6] "Anti-blooming control"
733 * = 0 (0x00) .0...... "Off"
734 * COME[5:3] "Reserved"
735 * = 4 (0x04) ..100...
736 * COME[2] "Clock output power down pin status"
737 * = 0 (0x00) .....0.. "Tri-state data output pin
738 * on power down"
739 * COME[1] "Data output pin status selection at power down"
740 * = 0 (0x00) ......0. "Tri-state VSYNC, PCLK,
741 * HREF, and CHSYNC pins on
742 * power down"
743 * COME[0] "Auto zero circuit select"
744 * = 1 (0x01) .......1 "On"
745 */
746 { 0x0d, 0xA1 },
747
748 /*
749 * 0E COMF "Common Control F"
750 * = 112 (0x70) 01110000
751 * COMF[7] "System clock selection"
752 * = 0 (0x00) 0....... "Use 24 MHz system clock"
753 * COMF[6:4] "Reserved"
754 * = 7 (0x07) .111....
755 * COMF[3] "Manual auto negative offset canceling selection"
756 * = 0 (0x00) ....0... "Auto detect negative
757 * offset and cancel it"
758 * COMF[2:0] "Reserved"
759 * = 0 (0x00) .....000
760 */
761 { 0x0e, 0x70 },
762
763 /*
764 * 0F COMG "Common Control G"
765 * = 66 (0x42) 01000010
766 * COMG[7] "Optical black output selection"
767 * = 0 (0x00) 0....... "Disable"
768 * COMG[6] "Black level calibrate selection"
769 * = 1 (0x01) .1...... "Use optical black pixels
770 * to calibrate"
771 * COMG[5:4] "Reserved"
772 * = 0 (0x00) ..00....
773 * COMG[3] "Channel offset adjustment"
774 * = 0 (0x00) ....0... "Disable offset adjustment"
775 * COMG[2] "ADC black level calibration option"
776 * = 0 (0x00) .....0.. "Use B/G line and G/R
777 * line to calibrate each
778 * channel's black level"
779 * COMG[1] "Reserved"
780 * = 1 (0x01) ......1.
781 * COMG[0] "ADC black level calibration enable"
782 * = 0 (0x00) .......0 "Disable"
783 */
784 { 0x0f, 0x42 },
785
786 /*
787 * 14 COMJ "Common Control J"
788 * = 198 (0xC6) 11000110
789 * COMJ[7:6] "AGC gain ceiling"
790 * = 3 (0x03) 11...... "8x"
791 * COMJ[5:4] "Reserved"
792 * = 0 (0x00) ..00....
793 * COMJ[3] "Auto banding filter"
794 * = 0 (0x00) ....0... "Banding filter is always
795 * on off depending on
796 * COMI[5] setting"
797 * COMJ[2] "VSYNC drop option"
798 * = 1 (0x01) .....1.. "SYNC is dropped if frame
799 * data is dropped"
800 * COMJ[1] "Frame data drop"
801 * = 1 (0x01) ......1. "Drop frame data if
802 * exposure is not within
803 * tolerance. In AEC mode,
804 * data is normally dropped
805 * when data is out of
806 * range."
807 * COMJ[0] "Reserved"
808 * = 0 (0x00) .......0
809 */
810 { 0x14, 0xC6 },
811
812 /*
813 * 15 COMK "Common Control K"
814 * = 2 (0x02) 00000010
815 * COMK[7] "CHSYNC pin output swap"
816 * = 0 (0x00) 0....... "CHSYNC"
817 * COMK[6] "HREF pin output swap"
818 * = 0 (0x00) .0...... "HREF"
819 * COMK[5] "PCLK output selection"
820 * = 0 (0x00) ..0..... "PCLK always output"
821 * COMK[4] "PCLK edge selection"
822 * = 0 (0x00) ...0.... "Data valid on falling edge"
823 * COMK[3] "HREF output polarity"
824 * = 0 (0x00) ....0... "positive"
825 * COMK[2] "Reserved"
826 * = 0 (0x00) .....0..
827 * COMK[1] "VSYNC polarity"
828 * = 1 (0x01) ......1. "negative"
829 * COMK[0] "HSYNC polarity"
830 * = 0 (0x00) .......0 "positive"
831 */
832 { 0x15, 0x02 },
833
834 /*
835 * 33 CHLF "Current Control"
836 * = 9 (0x09) 00001001
837 * CHLF[7:6] "Sensor current control"
838 * = 0 (0x00) 00......
839 * CHLF[5] "Sensor current range control"
840 * = 0 (0x00) ..0..... "normal range"
841 * CHLF[4] "Sensor current"
842 * = 0 (0x00) ...0.... "normal current"
843 * CHLF[3] "Sensor buffer current control"
844 * = 1 (0x01) ....1... "half current"
845 * CHLF[2] "Column buffer current control"
846 * = 0 (0x00) .....0.. "normal current"
847 * CHLF[1] "Analog DSP current control"
848 * = 0 (0x00) ......0. "normal current"
849 * CHLF[1] "ADC current control"
850 * = 0 (0x00) ......0. "normal current"
851 */
852 { 0x33, 0x09 },
853
854 /*
855 * 34 VBLM "Blooming Control"
856 * = 80 (0x50) 01010000
857 * VBLM[7] "Hard soft reset switch"
858 * = 0 (0x00) 0....... "Hard reset"
859 * VBLM[6:4] "Blooming voltage selection"
860 * = 5 (0x05) .101....
861 * VBLM[3:0] "Sensor current control"
862 * = 0 (0x00) ....0000
863 */
864 { 0x34, 0x50 },
865
866 /*
867 * 36 VCHG "Sensor Precharge Voltage Control"
868 * = 0 (0x00) 00000000
869 * VCHG[7] "Reserved"
870 * = 0 (0x00) 0.......
871 * VCHG[6:4] "Sensor precharge voltage control"
872 * = 0 (0x00) .000....
873 * VCHG[3:0] "Sensor array common reference"
874 * = 0 (0x00) ....0000
875 */
876 { 0x36, 0x00 },
877
878 /*
879 * 37 ADC "ADC Reference Control"
880 * = 4 (0x04) 00000100
881 * ADC[7:4] "Reserved"
882 * = 0 (0x00) 0000....
883 * ADC[3] "ADC input signal range"
884 * = 0 (0x00) ....0... "Input signal 1.0x"
885 * ADC[2:0] "ADC range control"
886 * = 4 (0x04) .....100
887 */
888 { 0x37, 0x04 },
889
890 /*
891 * 38 ACOM "Analog Common Ground"
892 * = 82 (0x52) 01010010
893 * ACOM[7] "Analog gain control"
894 * = 0 (0x00) 0....... "Gain 1x"
895 * ACOM[6] "Analog black level calibration"
896 * = 1 (0x01) .1...... "On"
897 * ACOM[5:0] "Reserved"
898 * = 18 (0x12) ..010010
899 */
900 { 0x38, 0x52 },
901
902 /*
903 * 3A FREFA "Internal Reference Adjustment"
904 * = 0 (0x00) 00000000
905 * FREFA[7:0] "Range"
906 * = 0 (0x00) 00000000
907 */
908 { 0x3a, 0x00 },
909
910 /*
911 * 3C FVOPT "Internal Reference Adjustment"
912 * = 31 (0x1F) 00011111
913 * FVOPT[7:0] "Range"
914 * = 31 (0x1F) 00011111
915 */
916 { 0x3c, 0x1F },
917
918 /*
919 * 44 Undocumented = 0 (0x00) 00000000
920 * 44[7:0] "It's a secret"
921 * = 0 (0x00) 00000000
922 */
923 { 0x44, 0x00 },
924
925 /*
926 * 40 Undocumented = 0 (0x00) 00000000
927 * 40[7:0] "It's a secret"
928 * = 0 (0x00) 00000000
929 */
930 { 0x40, 0x00 },
931
932 /*
933 * 41 Undocumented = 0 (0x00) 00000000
934 * 41[7:0] "It's a secret"
935 * = 0 (0x00) 00000000
936 */
937 { 0x41, 0x00 },
938
939 /*
940 * 42 Undocumented = 0 (0x00) 00000000
941 * 42[7:0] "It's a secret"
942 * = 0 (0x00) 00000000
943 */
944 { 0x42, 0x00 },
945
946 /*
947 * 43 Undocumented = 0 (0x00) 00000000
948 * 43[7:0] "It's a secret"
949 * = 0 (0x00) 00000000
950 */
951 { 0x43, 0x00 },
952
953 /*
954 * 45 Undocumented = 128 (0x80) 10000000
955 * 45[7:0] "It's a secret"
956 * = 128 (0x80) 10000000
957 */
958 { 0x45, 0x80 },
959
960 /*
961 * 48 Undocumented = 192 (0xC0) 11000000
962 * 48[7:0] "It's a secret"
963 * = 192 (0xC0) 11000000
964 */
965 { 0x48, 0xC0 },
966
967 /*
968 * 49 Undocumented = 25 (0x19) 00011001
969 * 49[7:0] "It's a secret"
970 * = 25 (0x19) 00011001
971 */
972 { 0x49, 0x19 },
973
974 /*
975 * 4B Undocumented = 128 (0x80) 10000000
976 * 4B[7:0] "It's a secret"
977 * = 128 (0x80) 10000000
978 */
979 { 0x4B, 0x80 },
980
981 /*
982 * 4D Undocumented = 196 (0xC4) 11000100
983 * 4D[7:0] "It's a secret"
984 * = 196 (0xC4) 11000100
985 */
986 { 0x4D, 0xC4 },
987
988 /*
989 * 35 VREF "Reference Voltage Control"
990 * = 76 (0x4C) 01001100
991 * VREF[7:5] "Column high reference control"
992 * = 2 (0x02) 010..... "higher voltage"
993 * VREF[4:2] "Column low reference control"
994 * = 3 (0x03) ...011.. "Highest voltage"
995 * VREF[1:0] "Reserved"
996 * = 0 (0x00) ......00
997 */
998 { 0x35, 0x4C },
999
1000 /*
1001 * 3D Undocumented = 0 (0x00) 00000000
1002 * 3D[7:0] "It's a secret"
1003 * = 0 (0x00) 00000000
1004 */
1005 { 0x3D, 0x00 },
1006
1007 /*
1008 * 3E Undocumented = 0 (0x00) 00000000
1009 * 3E[7:0] "It's a secret"
1010 * = 0 (0x00) 00000000
1011 */
1012 { 0x3E, 0x00 },
1013
1014 /*
1015 * 3B FREFB "Internal Reference Adjustment"
1016 * = 24 (0x18) 00011000
1017 * FREFB[7:0] "Range"
1018 * = 24 (0x18) 00011000
1019 */
1020 { 0x3b, 0x18 },
1021
1022 /*
1023 * 33 CHLF "Current Control"
1024 * = 25 (0x19) 00011001
1025 * CHLF[7:6] "Sensor current control"
1026 * = 0 (0x00) 00......
1027 * CHLF[5] "Sensor current range control"
1028 * = 0 (0x00) ..0..... "normal range"
1029 * CHLF[4] "Sensor current"
1030 * = 1 (0x01) ...1.... "double current"
1031 * CHLF[3] "Sensor buffer current control"
1032 * = 1 (0x01) ....1... "half current"
1033 * CHLF[2] "Column buffer current control"
1034 * = 0 (0x00) .....0.. "normal current"
1035 * CHLF[1] "Analog DSP current control"
1036 * = 0 (0x00) ......0. "normal current"
1037 * CHLF[1] "ADC current control"
1038 * = 0 (0x00) ......0. "normal current"
1039 */
1040 { 0x33, 0x19 },
1041
1042 /*
1043 * 34 VBLM "Blooming Control"
1044 * = 90 (0x5A) 01011010
1045 * VBLM[7] "Hard soft reset switch"
1046 * = 0 (0x00) 0....... "Hard reset"
1047 * VBLM[6:4] "Blooming voltage selection"
1048 * = 5 (0x05) .101....
1049 * VBLM[3:0] "Sensor current control"
1050 * = 10 (0x0A) ....1010
1051 */
1052 { 0x34, 0x5A },
1053
1054 /*
1055 * 3B FREFB "Internal Reference Adjustment"
1056 * = 0 (0x00) 00000000
1057 * FREFB[7:0] "Range"
1058 * = 0 (0x00) 00000000
1059 */
1060 { 0x3b, 0x00 },
1061
1062 /*
1063 * 33 CHLF "Current Control"
1064 * = 9 (0x09) 00001001
1065 * CHLF[7:6] "Sensor current control"
1066 * = 0 (0x00) 00......
1067 * CHLF[5] "Sensor current range control"
1068 * = 0 (0x00) ..0..... "normal range"
1069 * CHLF[4] "Sensor current"
1070 * = 0 (0x00) ...0.... "normal current"
1071 * CHLF[3] "Sensor buffer current control"
1072 * = 1 (0x01) ....1... "half current"
1073 * CHLF[2] "Column buffer current control"
1074 * = 0 (0x00) .....0.. "normal current"
1075 * CHLF[1] "Analog DSP current control"
1076 * = 0 (0x00) ......0. "normal current"
1077 * CHLF[1] "ADC current control"
1078 * = 0 (0x00) ......0. "normal current"
1079 */
1080 { 0x33, 0x09 },
1081
1082 /*
1083 * 34 VBLM "Blooming Control"
1084 * = 80 (0x50) 01010000
1085 * VBLM[7] "Hard soft reset switch"
1086 * = 0 (0x00) 0....... "Hard reset"
1087 * VBLM[6:4] "Blooming voltage selection"
1088 * = 5 (0x05) .101....
1089 * VBLM[3:0] "Sensor current control"
1090 * = 0 (0x00) ....0000
1091 */
1092 { 0x34, 0x50 },
1093
1094 /*
1095 * 12 COMH "Common Control H"
1096 * = 64 (0x40) 01000000
1097 * COMH[7] "SRST"
1098 * = 0 (0x00) 0....... "No-op"
1099 * COMH[6:4] "Resolution selection"
1100 * = 4 (0x04) .100.... "XGA"
1101 * COMH[3] "Master slave selection"
1102 * = 0 (0x00) ....0... "Master mode"
1103 * COMH[2] "Internal B/R channel option"
1104 * = 0 (0x00) .....0.. "B/R use same channel"
1105 * COMH[1] "Color bar test pattern"
1106 * = 0 (0x00) ......0. "Off"
1107 * COMH[0] "Reserved"
1108 * = 0 (0x00) .......0
1109 */
1110 { 0x12, 0x40 },
1111
1112 /*
1113 * 17 HREFST "Horizontal window start"
1114 * = 31 (0x1F) 00011111
1115 * HREFST[7:0] "Horizontal window start, 8 MSBs"
1116 * = 31 (0x1F) 00011111
1117 */
1118 { 0x17, 0x1F },
1119
1120 /*
1121 * 18 HREFEND "Horizontal window end"
1122 * = 95 (0x5F) 01011111
1123 * HREFEND[7:0] "Horizontal Window End, 8 MSBs"
1124 * = 95 (0x5F) 01011111
1125 */
1126 { 0x18, 0x5F },
1127
1128 /*
1129 * 19 VSTRT "Vertical window start"
1130 * = 0 (0x00) 00000000
1131 * VSTRT[7:0] "Vertical Window Start, 8 MSBs"
1132 * = 0 (0x00) 00000000
1133 */
1134 { 0x19, 0x00 },
1135
1136 /*
1137 * 1A VEND "Vertical window end"
1138 * = 96 (0x60) 01100000
1139 * VEND[7:0] "Vertical Window End, 8 MSBs"
1140 * = 96 (0x60) 01100000
1141 */
1142 { 0x1a, 0x60 },
1143
1144 /*
1145 * 32 COMM "Common Control M"
1146 * = 18 (0x12) 00010010
1147 * COMM[7:6] "Pixel clock divide option"
1148 * = 0 (0x00) 00...... "/1"
1149 * COMM[5:3] "Horizontal window end position, 3 LSBs"
1150 * = 2 (0x02) ..010...
1151 * COMM[2:0] "Horizontal window start position, 3 LSBs"
1152 * = 2 (0x02) .....010
1153 */
1154 { 0x32, 0x12 },
1155
1156 /*
1157 * 03 COMA "Common Control A"
1158 * = 74 (0x4A) 01001010
1159 * COMA[7:4] "AWB Update Threshold"
1160 * = 4 (0x04) 0100....
1161 * COMA[3:2] "Vertical window end line control 2 LSBs"
1162 * = 2 (0x02) ....10..
1163 * COMA[1:0] "Vertical window start line control 2 LSBs"
1164 * = 2 (0x02) ......10
1165 */
1166 { 0x03, 0x4A },
1167
1168 /*
1169 * 11 CLKRC "Clock Rate Control"
1170 * = 128 (0x80) 10000000
1171 * CLKRC[7] "Internal frequency doublers on off seclection"
1172 * = 1 (0x01) 1....... "On"
1173 * CLKRC[6] "Digital video master slave selection"
1174 * = 0 (0x00) .0...... "Master mode, sensor
1175 * provides PCLK"
1176 * CLKRC[5:0] "Clock divider { CLK = PCLK/(1+CLKRC[5:0]) }"
1177 * = 0 (0x00) ..000000
1178 */
1179 { 0x11, 0x80 },
1180
1181 /*
1182 * 12 COMH "Common Control H"
1183 * = 0 (0x00) 00000000
1184 * COMH[7] "SRST"
1185 * = 0 (0x00) 0....... "No-op"
1186 * COMH[6:4] "Resolution selection"
1187 * = 0 (0x00) .000.... "QXGA"
1188 * COMH[3] "Master slave selection"
1189 * = 0 (0x00) ....0... "Master mode"
1190 * COMH[2] "Internal B/R channel option"
1191 * = 0 (0x00) .....0.. "B/R use same channel"
1192 * COMH[1] "Color bar test pattern"
1193 * = 0 (0x00) ......0. "Off"
1194 * COMH[0] "Reserved"
1195 * = 0 (0x00) .......0
1196 */
1197 { 0x12, 0x00 },
1198
1199 /*
1200 * 12 COMH "Common Control H"
1201 * = 64 (0x40) 01000000
1202 * COMH[7] "SRST"
1203 * = 0 (0x00) 0....... "No-op"
1204 * COMH[6:4] "Resolution selection"
1205 * = 4 (0x04) .100.... "XGA"
1206 * COMH[3] "Master slave selection"
1207 * = 0 (0x00) ....0... "Master mode"
1208 * COMH[2] "Internal B/R channel option"
1209 * = 0 (0x00) .....0.. "B/R use same channel"
1210 * COMH[1] "Color bar test pattern"
1211 * = 0 (0x00) ......0. "Off"
1212 * COMH[0] "Reserved"
1213 * = 0 (0x00) .......0
1214 */
1215 { 0x12, 0x40 },
1216
1217 /*
1218 * 17 HREFST "Horizontal window start"
1219 * = 31 (0x1F) 00011111
1220 * HREFST[7:0] "Horizontal window start, 8 MSBs"
1221 * = 31 (0x1F) 00011111
1222 */
1223 { 0x17, 0x1F },
1224
1225 /*
1226 * 18 HREFEND "Horizontal window end"
1227 * = 95 (0x5F) 01011111
1228 * HREFEND[7:0] "Horizontal Window End, 8 MSBs"
1229 * = 95 (0x5F) 01011111
1230 */
1231 { 0x18, 0x5F },
1232
1233 /*
1234 * 19 VSTRT "Vertical window start"
1235 * = 0 (0x00) 00000000
1236 * VSTRT[7:0] "Vertical Window Start, 8 MSBs"
1237 * = 0 (0x00) 00000000
1238 */
1239 { 0x19, 0x00 },
1240
1241 /*
1242 * 1A VEND "Vertical window end"
1243 * = 96 (0x60) 01100000
1244 * VEND[7:0] "Vertical Window End, 8 MSBs"
1245 * = 96 (0x60) 01100000
1246 */
1247 { 0x1a, 0x60 },
1248
1249 /*
1250 * 32 COMM "Common Control M"
1251 * = 18 (0x12) 00010010
1252 * COMM[7:6] "Pixel clock divide option"
1253 * = 0 (0x00) 00...... "/1"
1254 * COMM[5:3] "Horizontal window end position, 3 LSBs"
1255 * = 2 (0x02) ..010...
1256 * COMM[2:0] "Horizontal window start position, 3 LSBs"
1257 * = 2 (0x02) .....010
1258 */
1259 { 0x32, 0x12 },
1260
1261 /*
1262 * 03 COMA "Common Control A"
1263 * = 74 (0x4A) 01001010
1264 * COMA[7:4] "AWB Update Threshold"
1265 * = 4 (0x04) 0100....
1266 * COMA[3:2] "Vertical window end line control 2 LSBs"
1267 * = 2 (0x02) ....10..
1268 * COMA[1:0] "Vertical window start line control 2 LSBs"
1269 * = 2 (0x02) ......10
1270 */
1271 { 0x03, 0x4A },
1272
1273 /*
1274 * 02 RED "Red Gain Control"
1275 * = 175 (0xAF) 10101111
1276 * RED[7] "Action"
1277 * = 1 (0x01) 1....... "gain = 1/(1+bitrev([6:0]))"
1278 * RED[6:0] "Value"
1279 * = 47 (0x2F) .0101111
1280 */
1281 { 0x02, 0xAF },
1282
1283 /*
1284 * 2D ADDVSL "VSYNC Pulse Width"
1285 * = 210 (0xD2) 11010010
1286 * ADDVSL[7:0] "VSYNC pulse width, LSB"
1287 * = 210 (0xD2) 11010010
1288 */
1289 { 0x2d, 0xD2 },
1290
1291 /*
1292 * 00 GAIN = 24 (0x18) 00011000
1293 * GAIN[7:6] "Reserved"
1294 * = 0 (0x00) 00......
1295 * GAIN[5] "Double"
1296 * = 0 (0x00) ..0..... "False"
1297 * GAIN[4] "Double"
1298 * = 1 (0x01) ...1.... "True"
1299 * GAIN[3:0] "Range"
1300 * = 8 (0x08) ....1000
1301 */
1302 { 0x00, 0x18 },
1303
1304 /*
1305 * 01 BLUE "Blue Gain Control"
1306 * = 240 (0xF0) 11110000
1307 * BLUE[7] "Action"
1308 * = 1 (0x01) 1....... "gain = 1/(1+bitrev([6:0]))"
1309 * BLUE[6:0] "Value"
1310 * = 112 (0x70) .1110000
1311 */
1312 { 0x01, 0xF0 },
1313
1314 /*
1315 * 10 AEC "Automatic Exposure Control"
1316 * = 10 (0x0A) 00001010
1317 * AEC[7:0] "Automatic Exposure Control, 8 MSBs"
1318 * = 10 (0x0A) 00001010
1319 */
1320 { 0x10, 0x0A },
1321
1322 { 0xE1, 0x67 },
1323 { 0xE3, 0x03 },
1324 { 0xE4, 0x26 },
1325 { 0xE5, 0x3E },
1326 { 0xF8, 0x01 },
1327 { 0xFF, 0x01 },
1328};
1329
4202f71c
JFM		 1330static const struct ov_i2c_regvals norm_6x20[] = {
1331 { 0x12, 0x80 }, /* reset */
1332 { 0x11, 0x01 },
1333 { 0x03, 0x60 },
1334 { 0x05, 0x7f }, /* For when autoadjust is off */
1335 { 0x07, 0xa8 },
1336 /* The ratio of 0x0c and 0x0d controls the white point */
1337 { 0x0c, 0x24 },
1338 { 0x0d, 0x24 },
1339 { 0x0f, 0x15 }, /* COMS */
1340 { 0x10, 0x75 }, /* AEC Exposure time */
1341 { 0x12, 0x24 }, /* Enable AGC */
1342 { 0x14, 0x04 },
1343 /* 0x16: 0x06 helps frame stability with moving objects */
1344 { 0x16, 0x06 },
1345/* { 0x20, 0x30 }, * Aperture correction enable */
1346 { 0x26, 0xb2 }, /* BLC enable */
1347 /* 0x28: 0x05 Selects RGB format if RGB on */
1348 { 0x28, 0x05 },
1349 { 0x2a, 0x04 }, /* Disable framerate adjust */
1350/* { 0x2b, 0xac }, * Framerate; Set 2a[7] first */
ae49c404 1351 { 0x2d, 0x85 },
4202f71c
JFM		 1352 { 0x33, 0xa0 }, /* Color Processing Parameter */
1353 { 0x34, 0xd2 }, /* Max A/D range */
1354 { 0x38, 0x8b },
1355 { 0x39, 0x40 },
1356
1357 { 0x3c, 0x39 }, /* Enable AEC mode changing */
1358 { 0x3c, 0x3c }, /* Change AEC mode */
1359 { 0x3c, 0x24 }, /* Disable AEC mode changing */
1360
1361 { 0x3d, 0x80 },
1362 /* These next two registers (0x4a, 0x4b) are undocumented.
1363 * They control the color balance */
1364 { 0x4a, 0x80 },
1365 { 0x4b, 0x80 },
1366 { 0x4d, 0xd2 }, /* This reduces noise a bit */
1367 { 0x4e, 0xc1 },
1368 { 0x4f, 0x04 },
1369/* Do 50-53 have any effect? */
1370/* Toggle 0x12[2] off and on here? */
1371};
1372
1373static const struct ov_i2c_regvals norm_6x30[] = {
1374 { 0x12, 0x80 }, /* Reset */
1375 { 0x00, 0x1f }, /* Gain */
1376 { 0x01, 0x99 }, /* Blue gain */
1377 { 0x02, 0x7c }, /* Red gain */
1378 { 0x03, 0xc0 }, /* Saturation */
1379 { 0x05, 0x0a }, /* Contrast */
1380 { 0x06, 0x95 }, /* Brightness */
1381 { 0x07, 0x2d }, /* Sharpness */
1382 { 0x0c, 0x20 },
1383 { 0x0d, 0x20 },
02ab18b0 1384 { 0x0e, 0xa0 }, /* Was 0x20, bit7 enables a 2x gain which we need */
4202f71c
JFM		 1385 { 0x0f, 0x05 },
1386 { 0x10, 0x9a },
1387 { 0x11, 0x00 }, /* Pixel clock = fastest */
1388 { 0x12, 0x24 }, /* Enable AGC and AWB */
1389 { 0x13, 0x21 },
1390 { 0x14, 0x80 },
1391 { 0x15, 0x01 },
1392 { 0x16, 0x03 },
1393 { 0x17, 0x38 },
1394 { 0x18, 0xea },
1395 { 0x19, 0x04 },
1396 { 0x1a, 0x93 },
1397 { 0x1b, 0x00 },
1398 { 0x1e, 0xc4 },
1399 { 0x1f, 0x04 },
1400 { 0x20, 0x20 },
1401 { 0x21, 0x10 },
1402 { 0x22, 0x88 },
1403 { 0x23, 0xc0 }, /* Crystal circuit power level */
1404 { 0x25, 0x9a }, /* Increase AEC black ratio */
1405 { 0x26, 0xb2 }, /* BLC enable */
1406 { 0x27, 0xa2 },
1407 { 0x28, 0x00 },
1408 { 0x29, 0x00 },
1409 { 0x2a, 0x84 }, /* 60 Hz power */
1410 { 0x2b, 0xa8 }, /* 60 Hz power */
1411 { 0x2c, 0xa0 },
1412 { 0x2d, 0x95 }, /* Enable auto-brightness */
1413 { 0x2e, 0x88 },
1414 { 0x33, 0x26 },
1415 { 0x34, 0x03 },
1416 { 0x36, 0x8f },
1417 { 0x37, 0x80 },
1418 { 0x38, 0x83 },
1419 { 0x39, 0x80 },
1420 { 0x3a, 0x0f },
1421 { 0x3b, 0x3c },
1422 { 0x3c, 0x1a },
1423 { 0x3d, 0x80 },
1424 { 0x3e, 0x80 },
1425 { 0x3f, 0x0e },
1426 { 0x40, 0x00 }, /* White bal */
1427 { 0x41, 0x00 }, /* White bal */
1428 { 0x42, 0x80 },
1429 { 0x43, 0x3f }, /* White bal */
1430 { 0x44, 0x80 },
1431 { 0x45, 0x20 },
1432 { 0x46, 0x20 },
1433 { 0x47, 0x80 },
1434 { 0x48, 0x7f },
1435 { 0x49, 0x00 },
1436 { 0x4a, 0x00 },
1437 { 0x4b, 0x80 },
1438 { 0x4c, 0xd0 },
1439 { 0x4d, 0x10 }, /* U = 0.563u, V = 0.714v */
1440 { 0x4e, 0x40 },
1441 { 0x4f, 0x07 }, /* UV avg., col. killer: max */
1442 { 0x50, 0xff },
1443 { 0x54, 0x23 }, /* Max AGC gain: 18dB */
1444 { 0x55, 0xff },
1445 { 0x56, 0x12 },
1446 { 0x57, 0x81 },
1447 { 0x58, 0x75 },
1448 { 0x59, 0x01 }, /* AGC dark current comp.: +1 */
1449 { 0x5a, 0x2c },
1450 { 0x5b, 0x0f }, /* AWB chrominance levels */
1451 { 0x5c, 0x10 },
1452 { 0x3d, 0x80 },
1453 { 0x27, 0xa6 },
1454 { 0x12, 0x20 }, /* Toggle AWB */
1455 { 0x12, 0x24 },
1456};
1457
1458/* Lawrence Glaister <lg@jfm.bc.ca> reports:
1459 *
1460 * Register 0x0f in the 7610 has the following effects:
1461 *
1462 * 0x85 (AEC method 1): Best overall, good contrast range
1463 * 0x45 (AEC method 2): Very overexposed
1464 * 0xa5 (spec sheet default): Ok, but the black level is
1465 * shifted resulting in loss of contrast
1466 * 0x05 (old driver setting): very overexposed, too much
1467 * contrast
1468 */
1469static const struct ov_i2c_regvals norm_7610[] = {
1470 { 0x10, 0xff },
1471 { 0x16, 0x06 },
1472 { 0x28, 0x24 },
1473 { 0x2b, 0xac },
1474 { 0x12, 0x00 },
1475 { 0x38, 0x81 },
1476 { 0x28, 0x24 }, /* 0c */
1477 { 0x0f, 0x85 }, /* lg's setting */
1478 { 0x15, 0x01 },
1479 { 0x20, 0x1c },
1480 { 0x23, 0x2a },
1481 { 0x24, 0x10 },
1482 { 0x25, 0x8a },
1483 { 0x26, 0xa2 },
1484 { 0x27, 0xc2 },
1485 { 0x2a, 0x04 },
1486 { 0x2c, 0xfe },
1487 { 0x2d, 0x93 },
1488 { 0x30, 0x71 },
1489 { 0x31, 0x60 },
1490 { 0x32, 0x26 },
1491 { 0x33, 0x20 },
1492 { 0x34, 0x48 },
1493 { 0x12, 0x24 },
1494 { 0x11, 0x01 },
1495 { 0x0c, 0x24 },
1496 { 0x0d, 0x24 },
1497};
1498
1499static const struct ov_i2c_regvals norm_7620[] = {
a511ba94 1500 { 0x12, 0x80 }, /* reset */
4202f71c
JFM		 1501 { 0x00, 0x00 }, /* gain */
1502 { 0x01, 0x80 }, /* blue gain */
1503 { 0x02, 0x80 }, /* red gain */
1504 { 0x03, 0xc0 }, /* OV7670_REG_VREF */
1505 { 0x06, 0x60 },
1506 { 0x07, 0x00 },
1507 { 0x0c, 0x24 },
1508 { 0x0c, 0x24 },
1509 { 0x0d, 0x24 },
1510 { 0x11, 0x01 },
1511 { 0x12, 0x24 },
1512 { 0x13, 0x01 },
1513 { 0x14, 0x84 },
1514 { 0x15, 0x01 },
1515 { 0x16, 0x03 },
1516 { 0x17, 0x2f },
1517 { 0x18, 0xcf },
1518 { 0x19, 0x06 },
1519 { 0x1a, 0xf5 },
1520 { 0x1b, 0x00 },
1521 { 0x20, 0x18 },
1522 { 0x21, 0x80 },
1523 { 0x22, 0x80 },
1524 { 0x23, 0x00 },
1525 { 0x26, 0xa2 },
1526 { 0x27, 0xea },
b282d873 1527 { 0x28, 0x22 }, /* Was 0x20, bit1 enables a 2x gain which we need */
4202f71c
JFM		 1528 { 0x29, 0x00 },
1529 { 0x2a, 0x10 },
1530 { 0x2b, 0x00 },
1531 { 0x2c, 0x88 },
1532 { 0x2d, 0x91 },
1533 { 0x2e, 0x80 },
1534 { 0x2f, 0x44 },
1535 { 0x60, 0x27 },
1536 { 0x61, 0x02 },
1537 { 0x62, 0x5f },
1538 { 0x63, 0xd5 },
1539 { 0x64, 0x57 },
1540 { 0x65, 0x83 },
1541 { 0x66, 0x55 },
1542 { 0x67, 0x92 },
1543 { 0x68, 0xcf },
1544 { 0x69, 0x76 },
1545 { 0x6a, 0x22 },
1546 { 0x6b, 0x00 },
1547 { 0x6c, 0x02 },
1548 { 0x6d, 0x44 },
1549 { 0x6e, 0x80 },
1550 { 0x6f, 0x1d },
1551 { 0x70, 0x8b },
1552 { 0x71, 0x00 },
1553 { 0x72, 0x14 },
1554 { 0x73, 0x54 },
1555 { 0x74, 0x00 },
1556 { 0x75, 0x8e },
1557 { 0x76, 0x00 },
1558 { 0x77, 0xff },
1559 { 0x78, 0x80 },
1560 { 0x79, 0x80 },
1561 { 0x7a, 0x80 },
1562 { 0x7b, 0xe2 },
1563 { 0x7c, 0x00 },
1564};
1565
1566/* 7640 and 7648. The defaults should be OK for most registers. */
1567static const struct ov_i2c_regvals norm_7640[] = {
1568 { 0x12, 0x80 },
1569 { 0x12, 0x14 },
1570};
1571
1572/* 7670. Defaults taken from OmniVision provided data,
1573* as provided by Jonathan Corbet of OLPC */
1574static const struct ov_i2c_regvals norm_7670[] = {
1575 { OV7670_REG_COM7, OV7670_COM7_RESET },
1576 { OV7670_REG_TSLB, 0x04 }, /* OV */
1577 { OV7670_REG_COM7, OV7670_COM7_FMT_VGA }, /* VGA */
1578 { OV7670_REG_CLKRC, 0x01 },
1579/*
1580 * Set the hardware window. These values from OV don't entirely
1581 * make sense - hstop is less than hstart. But they work...
1582 */
1583 { OV7670_REG_HSTART, 0x13 },
1584 { OV7670_REG_HSTOP, 0x01 },
1585 { OV7670_REG_HREF, 0xb6 },
1586 { OV7670_REG_VSTART, 0x02 },
1587 { OV7670_REG_VSTOP, 0x7a },
1588 { OV7670_REG_VREF, 0x0a },
1589
ac40b1fa
JFM		 1590 { OV7670_REG_COM3, 0x00 },
1591 { OV7670_REG_COM14, 0x00 },
4202f71c
JFM		 1592/* Mystery scaling numbers */
1593 { 0x70, 0x3a },
1594 { 0x71, 0x35 },
1595 { 0x72, 0x11 },
1596 { 0x73, 0xf0 },
1597 { 0xa2, 0x02 },
1598/* { OV7670_REG_COM10, 0x0 }, */
1599
1600/* Gamma curve values */
1601 { 0x7a, 0x20 },
1602 { 0x7b, 0x10 },
1603 { 0x7c, 0x1e },
1604 { 0x7d, 0x35 },
1605 { 0x7e, 0x5a },
1606 { 0x7f, 0x69 },
1607 { 0x80, 0x76 },
1608 { 0x81, 0x80 },
1609 { 0x82, 0x88 },
1610 { 0x83, 0x8f },
1611 { 0x84, 0x96 },
1612 { 0x85, 0xa3 },
1613 { 0x86, 0xaf },
1614 { 0x87, 0xc4 },
1615 { 0x88, 0xd7 },
1616 { 0x89, 0xe8 },
1617
1618/* AGC and AEC parameters. Note we start by disabling those features,
1619 then turn them only after tweaking the values. */
1620 { OV7670_REG_COM8, OV7670_COM8_FASTAEC
1621 | OV7670_COM8_AECSTEP
1622 | OV7670_COM8_BFILT },
ac40b1fa
JFM		 1623 { OV7670_REG_GAIN, 0x00 },
1624 { OV7670_REG_AECH, 0x00 },
4202f71c
JFM		 1625 { OV7670_REG_COM4, 0x40 }, /* magic reserved bit */
1626 { OV7670_REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */
1627 { OV7670_REG_BD50MAX, 0x05 },
1628 { OV7670_REG_BD60MAX, 0x07 },
1629 { OV7670_REG_AEW, 0x95 },
1630 { OV7670_REG_AEB, 0x33 },
1631 { OV7670_REG_VPT, 0xe3 },
1632 { OV7670_REG_HAECC1, 0x78 },
1633 { OV7670_REG_HAECC2, 0x68 },
1634 { 0xa1, 0x03 }, /* magic */
1635 { OV7670_REG_HAECC3, 0xd8 },
1636 { OV7670_REG_HAECC4, 0xd8 },
1637 { OV7670_REG_HAECC5, 0xf0 },
1638 { OV7670_REG_HAECC6, 0x90 },
1639 { OV7670_REG_HAECC7, 0x94 },
1640 { OV7670_REG_COM8, OV7670_COM8_FASTAEC
1641 | OV7670_COM8_AECSTEP
1642 | OV7670_COM8_BFILT
1643 | OV7670_COM8_AGC
1644 | OV7670_COM8_AEC },
1645
1646/* Almost all of these are magic "reserved" values. */
1647 { OV7670_REG_COM5, 0x61 },
1648 { OV7670_REG_COM6, 0x4b },
1649 { 0x16, 0x02 },
1650 { OV7670_REG_MVFP, 0x07 },
1651 { 0x21, 0x02 },
1652 { 0x22, 0x91 },
1653 { 0x29, 0x07 },
1654 { 0x33, 0x0b },
1655 { 0x35, 0x0b },
1656 { 0x37, 0x1d },
1657 { 0x38, 0x71 },
1658 { 0x39, 0x2a },
1659 { OV7670_REG_COM12, 0x78 },
1660 { 0x4d, 0x40 },
1661 { 0x4e, 0x20 },
ac40b1fa 1662 { OV7670_REG_GFIX, 0x00 },
4202f71c
JFM		 1663 { 0x6b, 0x4a },
1664 { 0x74, 0x10 },
1665 { 0x8d, 0x4f },
ac40b1fa
JFM		 1666 { 0x8e, 0x00 },
1667 { 0x8f, 0x00 },
1668 { 0x90, 0x00 },
1669 { 0x91, 0x00 },
1670 { 0x96, 0x00 },
1671 { 0x9a, 0x00 },
4202f71c
JFM		 1672 { 0xb0, 0x84 },
1673 { 0xb1, 0x0c },
1674 { 0xb2, 0x0e },
1675 { 0xb3, 0x82 },
1676 { 0xb8, 0x0a },
1677
1678/* More reserved magic, some of which tweaks white balance */
1679 { 0x43, 0x0a },
1680 { 0x44, 0xf0 },
1681 { 0x45, 0x34 },
1682 { 0x46, 0x58 },
1683 { 0x47, 0x28 },
1684 { 0x48, 0x3a },
1685 { 0x59, 0x88 },
1686 { 0x5a, 0x88 },
1687 { 0x5b, 0x44 },
1688 { 0x5c, 0x67 },
1689 { 0x5d, 0x49 },
1690 { 0x5e, 0x0e },
1691 { 0x6c, 0x0a },
1692 { 0x6d, 0x55 },
1693 { 0x6e, 0x11 },
1694 { 0x6f, 0x9f },
1695 /* "9e for advance AWB" */
1696 { 0x6a, 0x40 },
1697 { OV7670_REG_BLUE, 0x40 },
1698 { OV7670_REG_RED, 0x60 },
1699 { OV7670_REG_COM8, OV7670_COM8_FASTAEC
1700 | OV7670_COM8_AECSTEP
1701 | OV7670_COM8_BFILT
1702 | OV7670_COM8_AGC
1703 | OV7670_COM8_AEC
1704 | OV7670_COM8_AWB },
1705
1706/* Matrix coefficients */
1707 { 0x4f, 0x80 },
1708 { 0x50, 0x80 },
ac40b1fa 1709 { 0x51, 0x00 },
4202f71c
JFM		 1710 { 0x52, 0x22 },
1711 { 0x53, 0x5e },
1712 { 0x54, 0x80 },
1713 { 0x58, 0x9e },
1714
1715 { OV7670_REG_COM16, OV7670_COM16_AWBGAIN },
ac40b1fa 1716 { OV7670_REG_EDGE, 0x00 },
4202f71c
JFM		 1717 { 0x75, 0x05 },
1718 { 0x76, 0xe1 },
ac40b1fa 1719 { 0x4c, 0x00 },
4202f71c
JFM		 1720 { 0x77, 0x01 },
1721 { OV7670_REG_COM13, OV7670_COM13_GAMMA
1722 | OV7670_COM13_UVSAT
1723 | 2}, /* was 3 */
1724 { 0x4b, 0x09 },
1725 { 0xc9, 0x60 },
1726 { OV7670_REG_COM16, 0x38 },
1727 { 0x56, 0x40 },
1728
1729 { 0x34, 0x11 },
1730 { OV7670_REG_COM11, OV7670_COM11_EXP|OV7670_COM11_HZAUTO },
1731 { 0xa4, 0x88 },
ac40b1fa 1732 { 0x96, 0x00 },
4202f71c
JFM		 1733 { 0x97, 0x30 },
1734 { 0x98, 0x20 },
1735 { 0x99, 0x30 },
1736 { 0x9a, 0x84 },
1737 { 0x9b, 0x29 },
1738 { 0x9c, 0x03 },
1739 { 0x9d, 0x4c },
1740 { 0x9e, 0x3f },
1741 { 0x78, 0x04 },
1742
1743/* Extra-weird stuff. Some sort of multiplexor register */
1744 { 0x79, 0x01 },
1745 { 0xc8, 0xf0 },
1746 { 0x79, 0x0f },
1747 { 0xc8, 0x00 },
1748 { 0x79, 0x10 },
1749 { 0xc8, 0x7e },
1750 { 0x79, 0x0a },
1751 { 0xc8, 0x80 },
1752 { 0x79, 0x0b },
1753 { 0xc8, 0x01 },
1754 { 0x79, 0x0c },
1755 { 0xc8, 0x0f },
1756 { 0x79, 0x0d },
1757 { 0xc8, 0x20 },
1758 { 0x79, 0x09 },
1759 { 0xc8, 0x80 },
1760 { 0x79, 0x02 },
1761 { 0xc8, 0xc0 },
1762 { 0x79, 0x03 },
1763 { 0xc8, 0x40 },
1764 { 0x79, 0x05 },
1765 { 0xc8, 0x30 },
1766 { 0x79, 0x26 },
1767};
1768
1769static const struct ov_i2c_regvals norm_8610[] = {
1770 { 0x12, 0x80 },
1771 { 0x00, 0x00 },
1772 { 0x01, 0x80 },
1773 { 0x02, 0x80 },
1774 { 0x03, 0xc0 },
1775 { 0x04, 0x30 },
1776 { 0x05, 0x30 }, /* was 0x10, new from windrv 090403 */
1777 { 0x06, 0x70 }, /* was 0x80, new from windrv 090403 */
1778 { 0x0a, 0x86 },
1779 { 0x0b, 0xb0 },
1780 { 0x0c, 0x20 },
1781 { 0x0d, 0x20 },
1782 { 0x11, 0x01 },
1783 { 0x12, 0x25 },
1784 { 0x13, 0x01 },
1785 { 0x14, 0x04 },
1786 { 0x15, 0x01 }, /* Lin and Win think different about UV order */
1787 { 0x16, 0x03 },
1788 { 0x17, 0x38 }, /* was 0x2f, new from windrv 090403 */
1789 { 0x18, 0xea }, /* was 0xcf, new from windrv 090403 */
1790 { 0x19, 0x02 }, /* was 0x06, new from windrv 090403 */
1791 { 0x1a, 0xf5 },
1792 { 0x1b, 0x00 },
1793 { 0x20, 0xd0 }, /* was 0x90, new from windrv 090403 */
1794 { 0x23, 0xc0 }, /* was 0x00, new from windrv 090403 */
1795 { 0x24, 0x30 }, /* was 0x1d, new from windrv 090403 */
1796 { 0x25, 0x50 }, /* was 0x57, new from windrv 090403 */
1797 { 0x26, 0xa2 },
1798 { 0x27, 0xea },
1799 { 0x28, 0x00 },
1800 { 0x29, 0x00 },
1801 { 0x2a, 0x80 },
1802 { 0x2b, 0xc8 }, /* was 0xcc, new from windrv 090403 */
1803 { 0x2c, 0xac },
1804 { 0x2d, 0x45 }, /* was 0xd5, new from windrv 090403 */
1805 { 0x2e, 0x80 },
1806 { 0x2f, 0x14 }, /* was 0x01, new from windrv 090403 */
1807 { 0x4c, 0x00 },
1808 { 0x4d, 0x30 }, /* was 0x10, new from windrv 090403 */
1809 { 0x60, 0x02 }, /* was 0x01, new from windrv 090403 */
1810 { 0x61, 0x00 }, /* was 0x09, new from windrv 090403 */
1811 { 0x62, 0x5f }, /* was 0xd7, new from windrv 090403 */
1812 { 0x63, 0xff },
1813 { 0x64, 0x53 }, /* new windrv 090403 says 0x57,
1814 * maybe thats wrong */
1815 { 0x65, 0x00 },
1816 { 0x66, 0x55 },
1817 { 0x67, 0xb0 },
1818 { 0x68, 0xc0 }, /* was 0xaf, new from windrv 090403 */
1819 { 0x69, 0x02 },
1820 { 0x6a, 0x22 },
1821 { 0x6b, 0x00 },
1822 { 0x6c, 0x99 }, /* was 0x80, old windrv says 0x00, but
1823 * deleting bit7 colors the first images red */
1824 { 0x6d, 0x11 }, /* was 0x00, new from windrv 090403 */
1825 { 0x6e, 0x11 }, /* was 0x00, new from windrv 090403 */
1826 { 0x6f, 0x01 },
1827 { 0x70, 0x8b },
1828 { 0x71, 0x00 },
1829 { 0x72, 0x14 },
1830 { 0x73, 0x54 },
1831 { 0x74, 0x00 },/* 0x60? - was 0x00, new from windrv 090403 */
1832 { 0x75, 0x0e },
1833 { 0x76, 0x02 }, /* was 0x02, new from windrv 090403 */
1834 { 0x77, 0xff },
1835 { 0x78, 0x80 },
1836 { 0x79, 0x80 },
1837 { 0x7a, 0x80 },
1838 { 0x7b, 0x10 }, /* was 0x13, new from windrv 090403 */
1839 { 0x7c, 0x00 },
1840 { 0x7d, 0x08 }, /* was 0x09, new from windrv 090403 */
1841 { 0x7e, 0x08 }, /* was 0xc0, new from windrv 090403 */
1842 { 0x7f, 0xfb },
1843 { 0x80, 0x28 },
1844 { 0x81, 0x00 },
1845 { 0x82, 0x23 },
1846 { 0x83, 0x0b },
1847 { 0x84, 0x00 },
1848 { 0x85, 0x62 }, /* was 0x61, new from windrv 090403 */
1849 { 0x86, 0xc9 },
1850 { 0x87, 0x00 },
1851 { 0x88, 0x00 },
1852 { 0x89, 0x01 },
1853 { 0x12, 0x20 },
1854 { 0x12, 0x25 }, /* was 0x24, new from windrv 090403 */
1855};
1856
6a7eba24
JFM		 1857static unsigned char ov7670_abs_to_sm(unsigned char v)
1858{
1859 if (v > 127)
1860 return v & 0x7f;
1861 return (128 - v) | 0x80;
1862}
1863
1864/* Write a OV519 register */
a511ba94 1865static int reg_w(struct sd *sd, __u16 index, __u16 value)
6a7eba24 1866{
a511ba94 1867 int ret, req = 0;
b46aaa02
HG		 1868
1869 switch (sd->bridge) {
1870 case BRIDGE_OV511:
1871 case BRIDGE_OV511PLUS:
1872 req = 2;
1873 break;
1874 case BRIDGE_OVFX2:
a511ba94
HG		 1875 req = 0x0a;
1876 /* fall through */
1877 case BRIDGE_W9968CF:
b46aaa02
HG		 1878 ret = usb_control_msg(sd->gspca_dev.dev,
1879 usb_sndctrlpipe(sd->gspca_dev.dev, 0),
a511ba94 1880 req,
b46aaa02 1881 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
a511ba94 1882 value, index, NULL, 0, 500);
b46aaa02
HG		 1883 goto leave;
1884 default:
1885 req = 1;
1886 }
6a7eba24 1887
739570bb 1888 sd->gspca_dev.usb_buf[0] = value;
6a7eba24
JFM		 1889 ret = usb_control_msg(sd->gspca_dev.dev,
1890 usb_sndctrlpipe(sd->gspca_dev.dev, 0),
49809d6a 1891 req,
6a7eba24
JFM		 1892 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
1893 0, index,
739570bb 1894 sd->gspca_dev.usb_buf, 1, 500);
b46aaa02 1895leave:
a511ba94
HG		 1896 if (ret < 0) {
1897 PDEBUG(D_ERR, "Write reg 0x%04x -> [0x%02x] failed",
1898 value, index);
1899 return ret;
1900 }
1901
1902 PDEBUG(D_USBO, "Write reg 0x%04x -> [0x%02x]", value, index);
1903 return 0;
6a7eba24
JFM		 1904}
1905
a511ba94 1906/* Read from a OV519 register, note not valid for the w9968cf!! */
6a7eba24
JFM		 1907/* returns: negative is error, pos or zero is data */
1908static int reg_r(struct sd *sd, __u16 index)
1909{
1910 int ret;
b46aaa02
HG		 1911 int req;
1912
1913 switch (sd->bridge) {
1914 case BRIDGE_OV511:
1915 case BRIDGE_OV511PLUS:
1916 req = 3;
1917 break;
1918 case BRIDGE_OVFX2:
1919 req = 0x0b;
1920 break;
1921 default:
1922 req = 1;
1923 }
6a7eba24
JFM		 1924
1925 ret = usb_control_msg(sd->gspca_dev.dev,
1926 usb_rcvctrlpipe(sd->gspca_dev.dev, 0),
49809d6a 1927 req,
6a7eba24 1928 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
739570bb 1929 0, index, sd->gspca_dev.usb_buf, 1, 500);
6a7eba24 1930
a511ba94 1931 if (ret >= 0) {
739570bb 1932 ret = sd->gspca_dev.usb_buf[0];
a511ba94
HG		 1933 PDEBUG(D_USBI, "Read reg [0x%02X] -> 0x%04X", index, ret);
1934 } else
6a7eba24 1935 PDEBUG(D_ERR, "Read reg [0x%02x] failed", index);
a511ba94 1936
6a7eba24
JFM		 1937 return ret;
1938}
1939
1940/* Read 8 values from a OV519 register */
1941static int reg_r8(struct sd *sd,
a5ae2062 1942 __u16 index)
6a7eba24
JFM		 1943{
1944 int ret;
6a7eba24
JFM		 1945
1946 ret = usb_control_msg(sd->gspca_dev.dev,
1947 usb_rcvctrlpipe(sd->gspca_dev.dev, 0),
1948 1, /* REQ_IO */
1949 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
739570bb 1950 0, index, sd->gspca_dev.usb_buf, 8, 500);
6a7eba24
JFM		 1951
1952 if (ret >= 0)
739570bb 1953 ret = sd->gspca_dev.usb_buf[0];
6a7eba24
JFM		 1954 else
1955 PDEBUG(D_ERR, "Read reg 8 [0x%02x] failed", index);
a511ba94 1956
6a7eba24
JFM		 1957 return ret;
1958}
1959
1960/*
1961 * Writes bits at positions specified by mask to an OV51x reg. Bits that are in
1962 * the same position as 1's in "mask" are cleared and set to "value". Bits
1963 * that are in the same position as 0's in "mask" are preserved, regardless
1964 * of their respective state in "value".
1965 */
1966static int reg_w_mask(struct sd *sd,
1967 __u16 index,
1968 __u8 value,
1969 __u8 mask)
1970{
1971 int ret;
1972 __u8 oldval;
1973
1974 if (mask != 0xff) {
1975 value &= mask; /* Enforce mask on value */
1976 ret = reg_r(sd, index);
1977 if (ret < 0)
1978 return ret;
1979
1980 oldval = ret & ~mask; /* Clear the masked bits */
1981 value |= oldval; /* Set the desired bits */
1982 }
1983 return reg_w(sd, index, value);
1984}
1985
49809d6a
HG		 1986/*
1987 * Writes multiple (n) byte value to a single register. Only valid with certain
1988 * registers (0x30 and 0xc4 - 0xce).
1989 */
1990static int ov518_reg_w32(struct sd *sd, __u16 index, u32 value, int n)
1991{
1992 int ret;
1993
83955556 1994 *((__le32 *) sd->gspca_dev.usb_buf) = __cpu_to_le32(value);
49809d6a
HG		 1995
1996 ret = usb_control_msg(sd->gspca_dev.dev,
1997 usb_sndctrlpipe(sd->gspca_dev.dev, 0),
1998 1 /* REG_IO */,
1999 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
2000 0, index,
2001 sd->gspca_dev.usb_buf, n, 500);
a511ba94 2002 if (ret < 0) {
49809d6a 2003 PDEBUG(D_ERR, "Write reg32 [%02x] %08x failed", index, value);
a511ba94
HG		 2004 return ret;
2005 }
2006
2007 return 0;
49809d6a
HG		 2008}
2009
1876bb92
HG		 2010static int ov511_i2c_w(struct sd *sd, __u8 reg, __u8 value)
2011{
2012 int rc, retries;
2013
2014 PDEBUG(D_USBO, "i2c 0x%02x -> [0x%02x]", value, reg);
2015
2016 /* Three byte write cycle */
2017 for (retries = 6; ; ) {
2018 /* Select camera register */
2019 rc = reg_w(sd, R51x_I2C_SADDR_3, reg);
2020 if (rc < 0)
2021 return rc;
2022
2023 /* Write "value" to I2C data port of OV511 */
2024 rc = reg_w(sd, R51x_I2C_DATA, value);
2025 if (rc < 0)
2026 return rc;
2027
2028 /* Initiate 3-byte write cycle */
2029 rc = reg_w(sd, R511_I2C_CTL, 0x01);
2030 if (rc < 0)
2031 return rc;
2032
83955556 2033 do {
1876bb92 2034 rc = reg_r(sd, R511_I2C_CTL);
83955556 2035 } while (rc > 0 && ((rc & 1) == 0)); /* Retry until idle */
1876bb92
HG		 2036
2037 if (rc < 0)
2038 return rc;
2039
2040 if ((rc & 2) == 0) /* Ack? */
2041 break;
2042 if (--retries < 0) {
2043 PDEBUG(D_USBO, "i2c write retries exhausted");
2044 return -1;
2045 }
2046 }
2047
2048 return 0;
2049}
2050
2051static int ov511_i2c_r(struct sd *sd, __u8 reg)
2052{
2053 int rc, value, retries;
2054
2055 /* Two byte write cycle */
2056 for (retries = 6; ; ) {
2057 /* Select camera register */
2058 rc = reg_w(sd, R51x_I2C_SADDR_2, reg);
2059 if (rc < 0)
2060 return rc;
2061
2062 /* Initiate 2-byte write cycle */
2063 rc = reg_w(sd, R511_I2C_CTL, 0x03);
2064 if (rc < 0)
2065 return rc;
2066
83955556 2067 do {
1876bb92 2068 rc = reg_r(sd, R511_I2C_CTL);
83955556 2069 } while (rc > 0 && ((rc & 1) == 0)); /* Retry until idle */
1876bb92
HG		 2070
2071 if (rc < 0)
2072 return rc;
2073
2074 if ((rc & 2) == 0) /* Ack? */
2075 break;
2076
2077 /* I2C abort */
2078 reg_w(sd, R511_I2C_CTL, 0x10);
2079
2080 if (--retries < 0) {
2081 PDEBUG(D_USBI, "i2c write retries exhausted");
2082 return -1;
2083 }
2084 }
2085
2086 /* Two byte read cycle */
2087 for (retries = 6; ; ) {
2088 /* Initiate 2-byte read cycle */
2089 rc = reg_w(sd, R511_I2C_CTL, 0x05);
2090 if (rc < 0)
2091 return rc;
2092
83955556 2093 do {
1876bb92 2094 rc = reg_r(sd, R511_I2C_CTL);
83955556 2095 } while (rc > 0 && ((rc & 1) == 0)); /* Retry until idle */
1876bb92
HG		 2096
2097 if (rc < 0)
2098 return rc;
2099
2100 if ((rc & 2) == 0) /* Ack? */
2101 break;
2102
2103 /* I2C abort */
2104 rc = reg_w(sd, R511_I2C_CTL, 0x10);
2105 if (rc < 0)
2106 return rc;
2107
2108 if (--retries < 0) {
2109 PDEBUG(D_USBI, "i2c read retries exhausted");
2110 return -1;
2111 }
2112 }
2113
2114 value = reg_r(sd, R51x_I2C_DATA);
2115
2116 PDEBUG(D_USBI, "i2c [0x%02X] -> 0x%02X", reg, value);
2117
2118 /* This is needed to make i2c_w() work */
2119 rc = reg_w(sd, R511_I2C_CTL, 0x05);
2120 if (rc < 0)
2121 return rc;
2122
2123 return value;
2124}
49809d6a 2125
6a7eba24
JFM		 2126/*
2127 * The OV518 I2C I/O procedure is different, hence, this function.
2128 * This is normally only called from i2c_w(). Note that this function
2129 * always succeeds regardless of whether the sensor is present and working.
2130 */
1876bb92 2131static int ov518_i2c_w(struct sd *sd,
6a7eba24
JFM		 2132 __u8 reg,
2133 __u8 value)
2134{
2135 int rc;
2136
2137 PDEBUG(D_USBO, "i2c 0x%02x -> [0x%02x]", value, reg);
2138
2139 /* Select camera register */
2140 rc = reg_w(sd, R51x_I2C_SADDR_3, reg);
2141 if (rc < 0)
2142 return rc;
2143
2144 /* Write "value" to I2C data port of OV511 */
2145 rc = reg_w(sd, R51x_I2C_DATA, value);
2146 if (rc < 0)
2147 return rc;
2148
2149 /* Initiate 3-byte write cycle */
2150 rc = reg_w(sd, R518_I2C_CTL, 0x01);
ac40b1fa
JFM		 2151 if (rc < 0)
2152 return rc;
6a7eba24
JFM		 2153
2154 /* wait for write complete */
2155 msleep(4);
6a7eba24
JFM		 2156 return reg_r8(sd, R518_I2C_CTL);
2157}
2158
2159/*
2160 * returns: negative is error, pos or zero is data
2161 *
2162 * The OV518 I2C I/O procedure is different, hence, this function.
2163 * This is normally only called from i2c_r(). Note that this function
2164 * always succeeds regardless of whether the sensor is present and working.
2165 */
1876bb92 2166static int ov518_i2c_r(struct sd *sd, __u8 reg)
6a7eba24
JFM		 2167{
2168 int rc, value;
2169
2170 /* Select camera register */
2171 rc = reg_w(sd, R51x_I2C_SADDR_2, reg);
2172 if (rc < 0)
2173 return rc;
2174
2175 /* Initiate 2-byte write cycle */
2176 rc = reg_w(sd, R518_I2C_CTL, 0x03);
2177 if (rc < 0)
2178 return rc;
2179
2180 /* Initiate 2-byte read cycle */
2181 rc = reg_w(sd, R518_I2C_CTL, 0x05);
2182 if (rc < 0)
2183 return rc;
2184 value = reg_r(sd, R51x_I2C_DATA);
2185 PDEBUG(D_USBI, "i2c [0x%02X] -> 0x%02X", reg, value);
2186 return value;
2187}
2188
b46aaa02
HG		 2189static int ovfx2_i2c_w(struct sd *sd, __u8 reg, __u8 value)
2190{
2191 int ret;
2192
2193 ret = usb_control_msg(sd->gspca_dev.dev,
2194 usb_sndctrlpipe(sd->gspca_dev.dev, 0),
2195 0x02,
2196 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
2197 (__u16)value, (__u16)reg, NULL, 0, 500);
2198
a511ba94 2199 if (ret < 0) {
b46aaa02 2200 PDEBUG(D_ERR, "i2c 0x%02x -> [0x%02x] failed", value, reg);
a511ba94
HG		 2201 return ret;
2202 }
b46aaa02 2203
a511ba94
HG		 2204 PDEBUG(D_USBO, "i2c 0x%02x -> [0x%02x]", value, reg);
2205 return 0;
b46aaa02
HG		 2206}
2207
2208static int ovfx2_i2c_r(struct sd *sd, __u8 reg)
2209{
2210 int ret;
2211
2212 ret = usb_control_msg(sd->gspca_dev.dev,
2213 usb_rcvctrlpipe(sd->gspca_dev.dev, 0),
2214 0x03,
2215 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
2216 0, (__u16)reg, sd->gspca_dev.usb_buf, 1, 500);
2217
2218 if (ret >= 0) {
2219 ret = sd->gspca_dev.usb_buf[0];
2220 PDEBUG(D_USBI, "i2c [0x%02X] -> 0x%02X", reg, ret);
2221 } else
2222 PDEBUG(D_ERR, "i2c read [0x%02x] failed", reg);
2223
2224 return ret;
2225}
2226
1876bb92
HG		 2227static int i2c_w(struct sd *sd, __u8 reg, __u8 value)
2228{
fb1f9020
HG		 2229 int ret = -1;
2230
2231 if (sd->sensor_reg_cache[reg] == value)
2232 return 0;
2233
1876bb92
HG		 2234 switch (sd->bridge) {
2235 case BRIDGE_OV511:
2236 case BRIDGE_OV511PLUS:
fb1f9020
HG		 2237 ret = ov511_i2c_w(sd, reg, value);
2238 break;
1876bb92
HG		 2239 case BRIDGE_OV518:
2240 case BRIDGE_OV518PLUS:
2241 case BRIDGE_OV519:
fb1f9020
HG		 2242 ret = ov518_i2c_w(sd, reg, value);
2243 break;
b46aaa02 2244 case BRIDGE_OVFX2:
fb1f9020
HG		 2245 ret = ovfx2_i2c_w(sd, reg, value);
2246 break;
a511ba94 2247 case BRIDGE_W9968CF:
fb1f9020
HG		 2248 ret = w9968cf_i2c_w(sd, reg, value);
2249 break;
1876bb92 2250 }
fb1f9020
HG		 2251
2252 if (ret >= 0) {
2253 /* Up on sensor reset empty the register cache */
2254 if (reg == 0x12 && (value & 0x80))
2255 memset(sd->sensor_reg_cache, -1,
2256 sizeof(sd->sensor_reg_cache));
2257 else
2258 sd->sensor_reg_cache[reg] = value;
2259 }
2260
2261 return ret;
1876bb92
HG		 2262}
2263
2264static int i2c_r(struct sd *sd, __u8 reg)
2265{
8394bcf3 2266 int ret = -1;
fb1f9020
HG		 2267
2268 if (sd->sensor_reg_cache[reg] != -1)
2269 return sd->sensor_reg_cache[reg];
2270
1876bb92
HG		 2271 switch (sd->bridge) {
2272 case BRIDGE_OV511:
2273 case BRIDGE_OV511PLUS:
fb1f9020
HG		 2274 ret = ov511_i2c_r(sd, reg);
2275 break;
1876bb92
HG		 2276 case BRIDGE_OV518:
2277 case BRIDGE_OV518PLUS:
2278 case BRIDGE_OV519:
fb1f9020
HG		 2279 ret = ov518_i2c_r(sd, reg);
2280 break;
b46aaa02 2281 case BRIDGE_OVFX2:
fb1f9020
HG		 2282 ret = ovfx2_i2c_r(sd, reg);
2283 break;
a511ba94 2284 case BRIDGE_W9968CF:
fb1f9020
HG		 2285 ret = w9968cf_i2c_r(sd, reg);
2286 break;
1876bb92 2287 }
fb1f9020
HG		 2288
2289 if (ret >= 0)
2290 sd->sensor_reg_cache[reg] = ret;
2291
2292 return ret;
1876bb92
HG		 2293}
2294
6a7eba24
JFM		 2295/* Writes bits at positions specified by mask to an I2C reg. Bits that are in
2296 * the same position as 1's in "mask" are cleared and set to "value". Bits
2297 * that are in the same position as 0's in "mask" are preserved, regardless
2298 * of their respective state in "value".
2299 */
2300static int i2c_w_mask(struct sd *sd,
2301 __u8 reg,
2302 __u8 value,
2303 __u8 mask)
2304{
2305 int rc;
2306 __u8 oldval;
2307
2308 value &= mask; /* Enforce mask on value */
2309 rc = i2c_r(sd, reg);
2310 if (rc < 0)
2311 return rc;
2312 oldval = rc & ~mask; /* Clear the masked bits */
2313 value |= oldval; /* Set the desired bits */
2314 return i2c_w(sd, reg, value);
2315}
2316
2317/* Temporarily stops OV511 from functioning. Must do this before changing
2318 * registers while the camera is streaming */
2319static inline int ov51x_stop(struct sd *sd)
2320{
2321 PDEBUG(D_STREAM, "stopping");
2322 sd->stopped = 1;
49809d6a
HG		 2323 switch (sd->bridge) {
2324 case BRIDGE_OV511:
2325 case BRIDGE_OV511PLUS:
2326 return reg_w(sd, R51x_SYS_RESET, 0x3d);
2327 case BRIDGE_OV518:
2328 case BRIDGE_OV518PLUS:
2329 return reg_w_mask(sd, R51x_SYS_RESET, 0x3a, 0x3a);
2330 case BRIDGE_OV519:
2331 return reg_w(sd, OV519_SYS_RESET1, 0x0f);
b46aaa02
HG		 2332 case BRIDGE_OVFX2:
2333 return reg_w_mask(sd, 0x0f, 0x00, 0x02);
a511ba94 2334 case BRIDGE_W9968CF:
79b35902 2335 return reg_w(sd, 0x3c, 0x0a05); /* stop USB transfer */
49809d6a
HG		 2336 }
2337
2338 return 0;
6a7eba24
JFM		 2339}
2340
2341/* Restarts OV511 after ov511_stop() is called. Has no effect if it is not
2342 * actually stopped (for performance). */
2343static inline int ov51x_restart(struct sd *sd)
2344{
49809d6a
HG		 2345 int rc;
2346
6a7eba24
JFM		 2347 PDEBUG(D_STREAM, "restarting");
2348 if (!sd->stopped)
2349 return 0;
2350 sd->stopped = 0;
2351
2352 /* Reinitialize the stream */
49809d6a
HG		 2353 switch (sd->bridge) {
2354 case BRIDGE_OV511:
2355 case BRIDGE_OV511PLUS:
2356 return reg_w(sd, R51x_SYS_RESET, 0x00);
2357 case BRIDGE_OV518:
2358 case BRIDGE_OV518PLUS:
2359 rc = reg_w(sd, 0x2f, 0x80);
2360 if (rc < 0)
2361 return rc;
2362 return reg_w(sd, R51x_SYS_RESET, 0x00);
2363 case BRIDGE_OV519:
2364 return reg_w(sd, OV519_SYS_RESET1, 0x00);
b46aaa02
HG		 2365 case BRIDGE_OVFX2:
2366 return reg_w_mask(sd, 0x0f, 0x02, 0x02);
a511ba94
HG		 2367 case BRIDGE_W9968CF:
2368 return reg_w(sd, 0x3c, 0x8a05); /* USB FIFO enable */
49809d6a
HG		 2369 }
2370
2371 return 0;
6a7eba24
JFM		 2372}
2373
229bb7dc
HG		 2374static int ov51x_set_slave_ids(struct sd *sd, __u8 slave);
2375
6a7eba24
JFM		 2376/* This does an initial reset of an OmniVision sensor and ensures that I2C
2377 * is synchronized. Returns <0 on failure.
2378 */
229bb7dc 2379static int init_ov_sensor(struct sd *sd, __u8 slave)
6a7eba24 2380{
ac40b1fa 2381 int i;
6a7eba24 2382
229bb7dc
HG		 2383 if (ov51x_set_slave_ids(sd, slave) < 0)
2384 return -EIO;
2385
6a7eba24
JFM		 2386 /* Reset the sensor */
2387 if (i2c_w(sd, 0x12, 0x80) < 0)
2388 return -EIO;
2389
2390 /* Wait for it to initialize */
2391 msleep(150);
2392
ac40b1fa 2393 for (i = 0; i < i2c_detect_tries; i++) {
6a7eba24
JFM		 2394 if (i2c_r(sd, OV7610_REG_ID_HIGH) == 0x7f &&
2395 i2c_r(sd, OV7610_REG_ID_LOW) == 0xa2) {
ac40b1fa
JFM		 2396 PDEBUG(D_PROBE, "I2C synced in %d attempt(s)", i);
2397 return 0;
6a7eba24
JFM		 2398 }
2399
2400 /* Reset the sensor */
2401 if (i2c_w(sd, 0x12, 0x80) < 0)
2402 return -EIO;
2403 /* Wait for it to initialize */
2404 msleep(150);
2405 /* Dummy read to sync I2C */
2406 if (i2c_r(sd, 0x00) < 0)
2407 return -EIO;
2408 }
ac40b1fa 2409 return -EIO;
6a7eba24
JFM		 2410}
2411
6a7eba24
JFM		 2412/* Set the read and write slave IDs. The "slave" argument is the write slave,
2413 * and the read slave will be set to (slave + 1).
2414 * This should not be called from outside the i2c I/O functions.
2415 * Sets I2C read and write slave IDs. Returns <0 for error
2416 */
2417static int ov51x_set_slave_ids(struct sd *sd,
2418 __u8 slave)
2419{
2420 int rc;
2421
a511ba94
HG		 2422 switch (sd->bridge) {
2423 case BRIDGE_OVFX2:
b46aaa02 2424 return reg_w(sd, OVFX2_I2C_ADDR, slave);
a511ba94
HG		 2425 case BRIDGE_W9968CF:
2426 sd->sensor_addr = slave;
2427 return 0;
2428 }
b46aaa02 2429
6a7eba24
JFM		 2430 rc = reg_w(sd, R51x_I2C_W_SID, slave);
2431 if (rc < 0)
2432 return rc;
2433 return reg_w(sd, R51x_I2C_R_SID, slave + 1);
2434}
2435
6a7eba24 2436static int write_regvals(struct sd *sd,
a5ae2062 2437 const struct ov_regvals *regvals,
6a7eba24
JFM		 2438 int n)
2439{
2440 int rc;
2441
2442 while (--n >= 0) {
2443 rc = reg_w(sd, regvals->reg, regvals->val);
2444 if (rc < 0)
2445 return rc;
2446 regvals++;
2447 }
2448 return 0;
2449}
2450
2451static int write_i2c_regvals(struct sd *sd,
a5ae2062 2452 const struct ov_i2c_regvals *regvals,
6a7eba24
JFM		 2453 int n)
2454{
2455 int rc;
2456
2457 while (--n >= 0) {
2458 rc = i2c_w(sd, regvals->reg, regvals->val);
2459 if (rc < 0)
2460 return rc;
2461 regvals++;
2462 }
2463 return 0;
2464}
2465
2466/****************************************************************************
2467 *
2468 * OV511 and sensor configuration
2469 *
2470 ***************************************************************************/
2471
635118d5
HG		 2472/* This initializes the OV2x10 / OV3610 / OV3620 */
2473static int ov_hires_configure(struct sd *sd)
2474{
2475 int high, low;
2476
2477 if (sd->bridge != BRIDGE_OVFX2) {
2478 PDEBUG(D_ERR, "error hires sensors only supported with ovfx2");
2479 return -1;
2480 }
2481
2482 PDEBUG(D_PROBE, "starting ov hires configuration");
2483
2484 /* Detect sensor (sub)type */
2485 high = i2c_r(sd, 0x0a);
2486 low = i2c_r(sd, 0x0b);
2487 /* info("%x, %x", high, low); */
2488 if (high == 0x96 && low == 0x40) {
2489 PDEBUG(D_PROBE, "Sensor is an OV2610");
2490 sd->sensor = SEN_OV2610;
2491 } else if (high == 0x36 && (low & 0x0f) == 0x00) {
2492 PDEBUG(D_PROBE, "Sensor is an OV3610");
2493 sd->sensor = SEN_OV3610;
2494 } else {
2495 PDEBUG(D_ERR, "Error unknown sensor type: 0x%02x%02x",
2496 high, low);
2497 return -1;
2498 }
2499
2500 /* Set sensor-specific vars */
2501 return 0;
2502}
2503
2504
6a7eba24
JFM		 2505/* This initializes the OV8110, OV8610 sensor. The OV8110 uses
2506 * the same register settings as the OV8610, since they are very similar.
2507 */
2508static int ov8xx0_configure(struct sd *sd)
2509{
2510 int rc;
6a7eba24
JFM		 2511
2512 PDEBUG(D_PROBE, "starting ov8xx0 configuration");
2513
6a7eba24
JFM		 2514 /* Detect sensor (sub)type */
2515 rc = i2c_r(sd, OV7610_REG_COM_I);
2516 if (rc < 0) {
2517 PDEBUG(D_ERR, "Error detecting sensor type");
2518 return -1;
2519 }
2520 if ((rc & 3) == 1) {
6a7eba24
JFM		 2521 sd->sensor = SEN_OV8610;
2522 } else {
2523 PDEBUG(D_ERR, "Unknown image sensor version: %d", rc & 3);
2524 return -1;
2525 }
6a7eba24
JFM		 2526
2527 /* Set sensor-specific vars */
6a7eba24
JFM		 2528 return 0;
2529}
2530
2531/* This initializes the OV7610, OV7620, or OV76BE sensor. The OV76BE uses
2532 * the same register settings as the OV7610, since they are very similar.
2533 */
2534static int ov7xx0_configure(struct sd *sd)
2535{
2536 int rc, high, low;
2537
6a7eba24
JFM		 2538
2539 PDEBUG(D_PROBE, "starting OV7xx0 configuration");
2540
6a7eba24
JFM		 2541 /* Detect sensor (sub)type */
2542 rc = i2c_r(sd, OV7610_REG_COM_I);
2543
2544 /* add OV7670 here
2545 * it appears to be wrongly detected as a 7610 by default */
2546 if (rc < 0) {
2547 PDEBUG(D_ERR, "Error detecting sensor type");
2548 return -1;
2549 }
2550 if ((rc & 3) == 3) {
2551 /* quick hack to make OV7670s work */
2552 high = i2c_r(sd, 0x0a);
2553 low = i2c_r(sd, 0x0b);
2554 /* info("%x, %x", high, low); */
2555 if (high == 0x76 && low == 0x73) {
2556 PDEBUG(D_PROBE, "Sensor is an OV7670");
2557 sd->sensor = SEN_OV7670;
2558 } else {
2559 PDEBUG(D_PROBE, "Sensor is an OV7610");
2560 sd->sensor = SEN_OV7610;
2561 }
2562 } else if ((rc & 3) == 1) {
2563 /* I don't know what's different about the 76BE yet. */
b282d873 2564 if (i2c_r(sd, 0x15) & 1) {
6a7eba24 2565 PDEBUG(D_PROBE, "Sensor is an OV7620AE");
859cc470 2566 sd->sensor = SEN_OV7620AE;
b282d873 2567 } else {
6a7eba24 2568 PDEBUG(D_PROBE, "Sensor is an OV76BE");
b282d873
HG		 2569 sd->sensor = SEN_OV76BE;
2570 }
6a7eba24
JFM		 2571 } else if ((rc & 3) == 0) {
2572 /* try to read product id registers */
2573 high = i2c_r(sd, 0x0a);
2574 if (high < 0) {
2575 PDEBUG(D_ERR, "Error detecting camera chip PID");
2576 return high;
2577 }
2578 low = i2c_r(sd, 0x0b);
2579 if (low < 0) {
2580 PDEBUG(D_ERR, "Error detecting camera chip VER");
2581 return low;
2582 }
2583 if (high == 0x76) {
594f5b8b
JFM		 2584 switch (low) {
2585 case 0x30:
6a7eba24 2586 PDEBUG(D_PROBE, "Sensor is an OV7630/OV7635");
4202f71c
JFM		 2587 PDEBUG(D_ERR,
2588 "7630 is not supported by this driver");
2589 return -1;
594f5b8b 2590 case 0x40:
6a7eba24
JFM		 2591 PDEBUG(D_PROBE, "Sensor is an OV7645");
2592 sd->sensor = SEN_OV7640; /* FIXME */
594f5b8b
JFM		 2593 break;
2594 case 0x45:
6a7eba24
JFM		 2595 PDEBUG(D_PROBE, "Sensor is an OV7645B");
2596 sd->sensor = SEN_OV7640; /* FIXME */
594f5b8b
JFM		 2597 break;
2598 case 0x48:
6a7eba24 2599 PDEBUG(D_PROBE, "Sensor is an OV7648");
035d3a3d 2600 sd->sensor = SEN_OV7648;
594f5b8b
JFM		 2601 break;
2602 default:
2603 PDEBUG(D_PROBE, "Unknown sensor: 0x76%x", low);
6a7eba24
JFM		 2604 return -1;
2605 }
2606 } else {
2607 PDEBUG(D_PROBE, "Sensor is an OV7620");
2608 sd->sensor = SEN_OV7620;
2609 }
2610 } else {
2611 PDEBUG(D_ERR, "Unknown image sensor version: %d", rc & 3);
2612 return -1;
2613 }
2614
6a7eba24 2615 /* Set sensor-specific vars */
6a7eba24
JFM		 2616 return 0;
2617}
2618
2619/* This initializes the OV6620, OV6630, OV6630AE, or OV6630AF sensor. */
2620static int ov6xx0_configure(struct sd *sd)
2621{
2622 int rc;
4202f71c 2623 PDEBUG(D_PROBE, "starting OV6xx0 configuration");
6a7eba24
JFM		 2624
2625 /* Detect sensor (sub)type */
2626 rc = i2c_r(sd, OV7610_REG_COM_I);
2627 if (rc < 0) {
2628 PDEBUG(D_ERR, "Error detecting sensor type");
2629 return -1;
2630 }
2631
2632 /* Ugh. The first two bits are the version bits, but
2633 * the entire register value must be used. I guess OVT
2634 * underestimated how many variants they would make. */
594f5b8b
JFM		 2635 switch (rc) {
2636 case 0x00:
6a7eba24
JFM		 2637 sd->sensor = SEN_OV6630;
2638 PDEBUG(D_ERR,
2639 "WARNING: Sensor is an OV66308. Your camera may have");
2640 PDEBUG(D_ERR, "been misdetected in previous driver versions.");
594f5b8b
JFM		 2641 break;
2642 case 0x01:
6a7eba24 2643 sd->sensor = SEN_OV6620;
7d971373 2644 PDEBUG(D_PROBE, "Sensor is an OV6620");
594f5b8b
JFM		 2645 break;
2646 case 0x02:
6a7eba24
JFM		 2647 sd->sensor = SEN_OV6630;
2648 PDEBUG(D_PROBE, "Sensor is an OV66308AE");
594f5b8b
JFM		 2649 break;
2650 case 0x03:
7d971373 2651 sd->sensor = SEN_OV66308AF;
6a7eba24 2652 PDEBUG(D_PROBE, "Sensor is an OV66308AF");
594f5b8b
JFM		 2653 break;
2654 case 0x90:
6a7eba24
JFM		 2655 sd->sensor = SEN_OV6630;
2656 PDEBUG(D_ERR,
2657 "WARNING: Sensor is an OV66307. Your camera may have");
2658 PDEBUG(D_ERR, "been misdetected in previous driver versions.");
594f5b8b
JFM		 2659 break;
2660 default:
6a7eba24
JFM		 2661 PDEBUG(D_ERR, "FATAL: Unknown sensor version: 0x%02x", rc);
2662 return -1;
2663 }
2664
2665 /* Set sensor-specific vars */
594f5b8b 2666 sd->sif = 1;
6a7eba24 2667
6a7eba24
JFM		 2668 return 0;
2669}
2670
2671/* Turns on or off the LED. Only has an effect with OV511+/OV518(+)/OV519 */
2672static void ov51x_led_control(struct sd *sd, int on)
2673{
9e4d8258
HG		 2674 if (sd->invert_led)
2675 on = !on;
2676
49809d6a
HG		 2677 switch (sd->bridge) {
2678 /* OV511 has no LED control */
2679 case BRIDGE_OV511PLUS:
2680 reg_w(sd, R511_SYS_LED_CTL, on ? 1 : 0);
2681 break;
2682 case BRIDGE_OV518:
2683 case BRIDGE_OV518PLUS:
2684 reg_w_mask(sd, R518_GPIO_OUT, on ? 0x02 : 0x00, 0x02);
2685 break;
2686 case BRIDGE_OV519:
2687 reg_w_mask(sd, OV519_GPIO_DATA_OUT0, !on, 1); /* 0 / 1 */
2688 break;
2689 }
6a7eba24
JFM		 2690}
2691
417a4d26
HG		 2692static void sd_reset_snapshot(struct gspca_dev *gspca_dev)
2693{
2694 struct sd *sd = (struct sd *) gspca_dev;
2695
2696 if (!sd->snapshot_needs_reset)
2697 return;
2698
2699 /* Note it is important that we clear sd->snapshot_needs_reset,
2700 before actually clearing the snapshot state in the bridge
2701 otherwise we might race with the pkt_scan interrupt handler */
2702 sd->snapshot_needs_reset = 0;
2703
2704 switch (sd->bridge) {
2705 case BRIDGE_OV519:
2706 reg_w(sd, R51x_SYS_RESET, 0x40);
2707 reg_w(sd, R51x_SYS_RESET, 0x00);
2708 break;
2709 }
2710}
2711
1876bb92 2712static int ov51x_upload_quan_tables(struct sd *sd)
49809d6a 2713{
1876bb92
HG		 2714 const unsigned char yQuanTable511[] = {
2715 0, 1, 1, 2, 2, 3, 3, 4,
2716 1, 1, 1, 2, 2, 3, 4, 4,
2717 1, 1, 2, 2, 3, 4, 4, 4,
2718 2, 2, 2, 3, 4, 4, 4, 4,
2719 2, 2, 3, 4, 4, 5, 5, 5,
2720 3, 3, 4, 4, 5, 5, 5, 5,
2721 3, 4, 4, 4, 5, 5, 5, 5,
2722 4, 4, 4, 4, 5, 5, 5, 5
2723 };
2724
2725 const unsigned char uvQuanTable511[] = {
2726 0, 2, 2, 3, 4, 4, 4, 4,
2727 2, 2, 2, 4, 4, 4, 4, 4,
2728 2, 2, 3, 4, 4, 4, 4, 4,
2729 3, 4, 4, 4, 4, 4, 4, 4,
2730 4, 4, 4, 4, 4, 4, 4, 4,
2731 4, 4, 4, 4, 4, 4, 4, 4,
2732 4, 4, 4, 4, 4, 4, 4, 4,
2733 4, 4, 4, 4, 4, 4, 4, 4
2734 };
2735
2736 /* OV518 quantization tables are 8x4 (instead of 8x8) */
49809d6a
HG		 2737 const unsigned char yQuanTable518[] = {
2738 5, 4, 5, 6, 6, 7, 7, 7,
2739 5, 5, 5, 5, 6, 7, 7, 7,
2740 6, 6, 6, 6, 7, 7, 7, 8,
2741 7, 7, 6, 7, 7, 7, 8, 8
2742 };
2743
2744 const unsigned char uvQuanTable518[] = {
2745 6, 6, 6, 7, 7, 7, 7, 7,
2746 6, 6, 6, 7, 7, 7, 7, 7,
2747 6, 6, 6, 7, 7, 7, 7, 8,
2748 7, 7, 7, 7, 7, 7, 8, 8
2749 };
2750
1876bb92 2751 const unsigned char *pYTable, *pUVTable;
49809d6a 2752 unsigned char val0, val1;
1876bb92 2753 int i, size, rc, reg = R51x_COMP_LUT_BEGIN;
49809d6a
HG		 2754
2755 PDEBUG(D_PROBE, "Uploading quantization tables");
2756
1876bb92
HG		 2757 if (sd->bridge == BRIDGE_OV511 || sd->bridge == BRIDGE_OV511PLUS) {
2758 pYTable = yQuanTable511;
2759 pUVTable = uvQuanTable511;
2760 size = 32;
2761 } else {
2762 pYTable = yQuanTable518;
2763 pUVTable = uvQuanTable518;
2764 size = 16;
2765 }
2766
2767 for (i = 0; i < size; i++) {
49809d6a
HG		 2768 val0 = *pYTable++;
2769 val1 = *pYTable++;
2770 val0 &= 0x0f;
2771 val1 &= 0x0f;
2772 val0 |= val1 << 4;
2773 rc = reg_w(sd, reg, val0);
2774 if (rc < 0)
2775 return rc;
2776
2777 val0 = *pUVTable++;
2778 val1 = *pUVTable++;
2779 val0 &= 0x0f;
2780 val1 &= 0x0f;
2781 val0 |= val1 << 4;
1876bb92 2782 rc = reg_w(sd, reg + size, val0);
49809d6a
HG		 2783 if (rc < 0)
2784 return rc;
2785
2786 reg++;
2787 }
2788
2789 return 0;
2790}
2791
1876bb92
HG		 2792/* This initializes the OV511/OV511+ and the sensor */
2793static int ov511_configure(struct gspca_dev *gspca_dev)
2794{
2795 struct sd *sd = (struct sd *) gspca_dev;
2796 int rc;
2797
2798 /* For 511 and 511+ */
2799 const struct ov_regvals init_511[] = {
2800 { R51x_SYS_RESET, 0x7f },
2801 { R51x_SYS_INIT, 0x01 },
2802 { R51x_SYS_RESET, 0x7f },
2803 { R51x_SYS_INIT, 0x01 },
2804 { R51x_SYS_RESET, 0x3f },
2805 { R51x_SYS_INIT, 0x01 },
2806 { R51x_SYS_RESET, 0x3d },
2807 };
2808
2809 const struct ov_regvals norm_511[] = {
2810 { R511_DRAM_FLOW_CTL, 0x01 },
2811 { R51x_SYS_SNAP, 0x00 },
2812 { R51x_SYS_SNAP, 0x02 },
2813 { R51x_SYS_SNAP, 0x00 },
2814 { R511_FIFO_OPTS, 0x1f },
2815 { R511_COMP_EN, 0x00 },
2816 { R511_COMP_LUT_EN, 0x03 },
2817 };
2818
2819 const struct ov_regvals norm_511_p[] = {
2820 { R511_DRAM_FLOW_CTL, 0xff },
2821 { R51x_SYS_SNAP, 0x00 },
2822 { R51x_SYS_SNAP, 0x02 },
2823 { R51x_SYS_SNAP, 0x00 },
2824 { R511_FIFO_OPTS, 0xff },
2825 { R511_COMP_EN, 0x00 },
2826 { R511_COMP_LUT_EN, 0x03 },
2827 };
2828
2829 const struct ov_regvals compress_511[] = {
2830 { 0x70, 0x1f },
2831 { 0x71, 0x05 },
2832 { 0x72, 0x06 },
2833 { 0x73, 0x06 },
2834 { 0x74, 0x14 },
2835 { 0x75, 0x03 },
2836 { 0x76, 0x04 },
2837 { 0x77, 0x04 },
2838 };
2839
2840 PDEBUG(D_PROBE, "Device custom id %x", reg_r(sd, R51x_SYS_CUST_ID));
2841
2842 rc = write_regvals(sd, init_511, ARRAY_SIZE(init_511));
2843 if (rc < 0)
2844 return rc;
2845
2846 switch (sd->bridge) {
2847 case BRIDGE_OV511:
2848 rc = write_regvals(sd, norm_511, ARRAY_SIZE(norm_511));
2849 if (rc < 0)
2850 return rc;
2851 break;
2852 case BRIDGE_OV511PLUS:
2853 rc = write_regvals(sd, norm_511_p, ARRAY_SIZE(norm_511_p));
2854 if (rc < 0)
2855 return rc;
2856 break;
2857 }
2858
2859 /* Init compression */
2860 rc = write_regvals(sd, compress_511, ARRAY_SIZE(compress_511));
2861 if (rc < 0)
2862 return rc;
2863
2864 rc = ov51x_upload_quan_tables(sd);
2865 if (rc < 0) {
2866 PDEBUG(D_ERR, "Error uploading quantization tables");
2867 return rc;
2868 }
2869
2870 return 0;
2871}
2872
49809d6a
HG		 2873/* This initializes the OV518/OV518+ and the sensor */
2874static int ov518_configure(struct gspca_dev *gspca_dev)
6a7eba24
JFM		 2875{
2876 struct sd *sd = (struct sd *) gspca_dev;
49809d6a
HG		 2877 int rc;
2878
2879 /* For 518 and 518+ */
e080fcd9 2880 const struct ov_regvals init_518[] = {
49809d6a
HG		 2881 { R51x_SYS_RESET, 0x40 },
2882 { R51x_SYS_INIT, 0xe1 },
2883 { R51x_SYS_RESET, 0x3e },
2884 { R51x_SYS_INIT, 0xe1 },
2885 { R51x_SYS_RESET, 0x00 },
2886 { R51x_SYS_INIT, 0xe1 },
2887 { 0x46, 0x00 },
2888 { 0x5d, 0x03 },
2889 };
2890
e080fcd9 2891 const struct ov_regvals norm_518[] = {
49809d6a
HG		 2892 { R51x_SYS_SNAP, 0x02 }, /* Reset */
2893 { R51x_SYS_SNAP, 0x01 }, /* Enable */
2894 { 0x31, 0x0f },
2895 { 0x5d, 0x03 },
2896 { 0x24, 0x9f },
2897 { 0x25, 0x90 },
2898 { 0x20, 0x00 },
2899 { 0x51, 0x04 },
2900 { 0x71, 0x19 },
2901 { 0x2f, 0x80 },
2902 };
2903
e080fcd9 2904 const struct ov_regvals norm_518_p[] = {
49809d6a
HG		 2905 { R51x_SYS_SNAP, 0x02 }, /* Reset */
2906 { R51x_SYS_SNAP, 0x01 }, /* Enable */
2907 { 0x31, 0x0f },
2908 { 0x5d, 0x03 },
2909 { 0x24, 0x9f },
2910 { 0x25, 0x90 },
2911 { 0x20, 0x60 },
2912 { 0x51, 0x02 },
2913 { 0x71, 0x19 },
2914 { 0x40, 0xff },
2915 { 0x41, 0x42 },
2916 { 0x46, 0x00 },
2917 { 0x33, 0x04 },
2918 { 0x21, 0x19 },
2919 { 0x3f, 0x10 },
2920 { 0x2f, 0x80 },
2921 };
2922
2923 /* First 5 bits of custom ID reg are a revision ID on OV518 */
2924 PDEBUG(D_PROBE, "Device revision %d",
2925 0x1F & reg_r(sd, R51x_SYS_CUST_ID));
2926
2927 rc = write_regvals(sd, init_518, ARRAY_SIZE(init_518));
2928 if (rc < 0)
2929 return rc;
2930
2931 /* Set LED GPIO pin to output mode */
2932 rc = reg_w_mask(sd, R518_GPIO_CTL, 0x00, 0x02);
2933 if (rc < 0)
2934 return rc;
6a7eba24 2935
49809d6a
HG		 2936 switch (sd->bridge) {
2937 case BRIDGE_OV518:
2938 rc = write_regvals(sd, norm_518, ARRAY_SIZE(norm_518));
2939 if (rc < 0)
2940 return rc;
2941 break;
2942 case BRIDGE_OV518PLUS:
2943 rc = write_regvals(sd, norm_518_p, ARRAY_SIZE(norm_518_p));
2944 if (rc < 0)
2945 return rc;
2946 break;
2947 }
2948
1876bb92 2949 rc = ov51x_upload_quan_tables(sd);
49809d6a
HG		 2950 if (rc < 0) {
2951 PDEBUG(D_ERR, "Error uploading quantization tables");
2952 return rc;
2953 }
2954
2955 rc = reg_w(sd, 0x2f, 0x80);
2956 if (rc < 0)
2957 return rc;
2958
2959 return 0;
2960}
2961
2962static int ov519_configure(struct sd *sd)
2963{
a5ae2062 2964 static const struct ov_regvals init_519[] = {
6a7eba24 2965 { 0x5a, 0x6d }, /* EnableSystem */
6a7eba24
JFM		 2966 { 0x53, 0x9b },
2967 { 0x54, 0xff }, /* set bit2 to enable jpeg */
2968 { 0x5d, 0x03 },
2969 { 0x49, 0x01 },
2970 { 0x48, 0x00 },
2971 /* Set LED pin to output mode. Bit 4 must be cleared or sensor
2972 * detection will fail. This deserves further investigation. */
2973 { OV519_GPIO_IO_CTRL0, 0xee },
2974 { 0x51, 0x0f }, /* SetUsbInit */
2975 { 0x51, 0x00 },
2976 { 0x22, 0x00 },
2977 /* windows reads 0x55 at this point*/
2978 };
2979
49809d6a
HG		 2980 return write_regvals(sd, init_519, ARRAY_SIZE(init_519));
2981}
2982
b46aaa02
HG		 2983static int ovfx2_configure(struct sd *sd)
2984{
2985 static const struct ov_regvals init_fx2[] = {
2986 { 0x00, 0x60 },
2987 { 0x02, 0x01 },
2988 { 0x0f, 0x1d },
2989 { 0xe9, 0x82 },
2990 { 0xea, 0xc7 },
2991 { 0xeb, 0x10 },
2992 { 0xec, 0xf6 },
2993 };
2994
2995 sd->stopped = 1;
2996
2997 return write_regvals(sd, init_fx2, ARRAY_SIZE(init_fx2));
2998}
2999
49809d6a
HG		 3000/* this function is called at probe time */
3001static int sd_config(struct gspca_dev *gspca_dev,
3002 const struct usb_device_id *id)
3003{
3004 struct sd *sd = (struct sd *) gspca_dev;
b46aaa02 3005 struct cam *cam = &gspca_dev->cam;
49809d6a
HG		 3006 int ret = 0;
3007
9e4d8258
HG		 3008 sd->bridge = id->driver_info & BRIDGE_MASK;
3009 sd->invert_led = id->driver_info & BRIDGE_INVERT_LED;
49809d6a
HG		 3010
3011 switch (sd->bridge) {
1876bb92
HG		 3012 case BRIDGE_OV511:
3013 case BRIDGE_OV511PLUS:
3014 ret = ov511_configure(gspca_dev);
3015 break;
49809d6a
HG		 3016 case BRIDGE_OV518:
3017 case BRIDGE_OV518PLUS:
3018 ret = ov518_configure(gspca_dev);
3019 break;
3020 case BRIDGE_OV519:
3021 ret = ov519_configure(sd);
3022 break;
b46aaa02
HG		 3023 case BRIDGE_OVFX2:
3024 ret = ovfx2_configure(sd);
3025 cam->bulk_size = OVFX2_BULK_SIZE;
3026 cam->bulk_nurbs = MAX_NURBS;
3027 cam->bulk = 1;
3028 break;
a511ba94
HG		 3029 case BRIDGE_W9968CF:
3030 ret = w9968cf_configure(sd);
3031 cam->reverse_alts = 1;
3032 break;
49809d6a
HG		 3033 }
3034
3035 if (ret)
6a7eba24 3036 goto error;
49809d6a 3037
6a7eba24
JFM		 3038 ov51x_led_control(sd, 0); /* turn LED off */
3039
6a7eba24
JFM		 3040 /* The OV519 must be more aggressive about sensor detection since
3041 * I2C write will never fail if the sensor is not present. We have
3042 * to try to initialize the sensor to detect its presence */
229bb7dc
HG		 3043
3044 /* Test for 76xx */
3045 if (init_ov_sensor(sd, OV7xx0_SID) >= 0) {
4202f71c
JFM		 3046 if (ov7xx0_configure(sd) < 0) {
3047 PDEBUG(D_ERR, "Failed to configure OV7xx0");
3048 goto error;
3049 }
229bb7dc
HG		 3050 /* Test for 6xx0 */
3051 } else if (init_ov_sensor(sd, OV6xx0_SID) >= 0) {
3052 if (ov6xx0_configure(sd) < 0) {
3053 PDEBUG(D_ERR, "Failed to configure OV6xx0");
3054 goto error;
3055 }
3056 /* Test for 8xx0 */
3057 } else if (init_ov_sensor(sd, OV8xx0_SID) >= 0) {
3058 if (ov8xx0_configure(sd) < 0) {
3059 PDEBUG(D_ERR, "Failed to configure OV8xx0");
6a7eba24 3060 goto error;
6a7eba24 3061 }
635118d5
HG		 3062 /* Test for 3xxx / 2xxx */
3063 } else if (init_ov_sensor(sd, OV_HIRES_SID) >= 0) {
3064 if (ov_hires_configure(sd) < 0) {
3065 PDEBUG(D_ERR, "Failed to configure high res OV");
3066 goto error;
3067 }
229bb7dc
HG		 3068 } else {
3069 PDEBUG(D_ERR, "Can't determine sensor slave IDs");
3070 goto error;
6a7eba24
JFM		 3071 }
3072
49809d6a 3073 switch (sd->bridge) {
1876bb92
HG		 3074 case BRIDGE_OV511:
3075 case BRIDGE_OV511PLUS:
3076 if (!sd->sif) {
3077 cam->cam_mode = ov511_vga_mode;
3078 cam->nmodes = ARRAY_SIZE(ov511_vga_mode);
3079 } else {
3080 cam->cam_mode = ov511_sif_mode;
3081 cam->nmodes = ARRAY_SIZE(ov511_sif_mode);
3082 }
3083 break;
49809d6a
HG		 3084 case BRIDGE_OV518:
3085 case BRIDGE_OV518PLUS:
3086 if (!sd->sif) {
3087 cam->cam_mode = ov518_vga_mode;
3088 cam->nmodes = ARRAY_SIZE(ov518_vga_mode);
3089 } else {
3090 cam->cam_mode = ov518_sif_mode;
3091 cam->nmodes = ARRAY_SIZE(ov518_sif_mode);
3092 }
3093 break;
3094 case BRIDGE_OV519:
3095 if (!sd->sif) {
3096 cam->cam_mode = ov519_vga_mode;
3097 cam->nmodes = ARRAY_SIZE(ov519_vga_mode);
3098 } else {
3099 cam->cam_mode = ov519_sif_mode;
3100 cam->nmodes = ARRAY_SIZE(ov519_sif_mode);
3101 }
3102 break;
635118d5
HG		 3103 case BRIDGE_OVFX2:
3104 if (sd->sensor == SEN_OV2610) {
3105 cam->cam_mode = ovfx2_ov2610_mode;
3106 cam->nmodes = ARRAY_SIZE(ovfx2_ov2610_mode);
3107 } else if (sd->sensor == SEN_OV3610) {
3108 cam->cam_mode = ovfx2_ov3610_mode;
3109 cam->nmodes = ARRAY_SIZE(ovfx2_ov3610_mode);
3110 } else if (!sd->sif) {
3111 cam->cam_mode = ov519_vga_mode;
3112 cam->nmodes = ARRAY_SIZE(ov519_vga_mode);
3113 } else {
3114 cam->cam_mode = ov519_sif_mode;
3115 cam->nmodes = ARRAY_SIZE(ov519_sif_mode);
3116 }
3117 break;
a511ba94
HG		 3118 case BRIDGE_W9968CF:
3119 cam->cam_mode = w9968cf_vga_mode;
3120 cam->nmodes = ARRAY_SIZE(w9968cf_vga_mode);
79b35902
HG		 3121 if (sd->sif)
3122 cam->nmodes--;
a511ba94
HG		 3123
3124 /* w9968cf needs initialisation once the sensor is known */
3125 if (w9968cf_init(sd) < 0)
3126 goto error;
3127 break;
6a7eba24 3128 }
594f5b8b 3129 sd->brightness = BRIGHTNESS_DEF;
f5cee95c
HG		 3130 if (sd->sensor == SEN_OV6630 || sd->sensor == SEN_OV66308AF)
3131 sd->contrast = 200; /* The default is too low for the ov6630 */
3132 else
3133 sd->contrast = CONTRAST_DEF;
594f5b8b 3134 sd->colors = COLOR_DEF;
0cd6759d
JFM		 3135 sd->hflip = HFLIP_DEF;
3136 sd->vflip = VFLIP_DEF;
02ab18b0
HG		 3137 sd->autobrightness = AUTOBRIGHT_DEF;
3138 if (sd->sensor == SEN_OV7670) {
3139 sd->freq = OV7670_FREQ_DEF;
3140 gspca_dev->ctrl_dis = 1 << FREQ_IDX;
3141 } else {
3142 sd->freq = FREQ_DEF;
3143 gspca_dev->ctrl_dis = (1 << HFLIP_IDX) | (1 << VFLIP_IDX) |
3144 (1 << OV7670_FREQ_IDX);
3145 }
79b35902 3146 sd->quality = QUALITY_DEF;
035d3a3d 3147 if (sd->sensor == SEN_OV7640 ||
d02134dd
HG		 3148 sd->sensor == SEN_OV7648)
3149 gspca_dev->ctrl_dis |= (1 << AUTOBRIGHT_IDX) |
3150 (1 << CONTRAST_IDX);
3151 if (sd->sensor == SEN_OV7670)
02ab18b0
HG		 3152 gspca_dev->ctrl_dis |= 1 << AUTOBRIGHT_IDX;
3153 /* OV8610 Frequency filter control should work but needs testing */
3154 if (sd->sensor == SEN_OV8610)
3155 gspca_dev->ctrl_dis |= 1 << FREQ_IDX;
635118d5
HG		 3156 /* No controls for the OV2610/OV3610 */
3157 if (sd->sensor == SEN_OV2610 || sd->sensor == SEN_OV3610)
3158 gspca_dev->ctrl_dis |= 0xFF;
02ab18b0 3159
6a7eba24
JFM		 3160 return 0;
3161error:
3162 PDEBUG(D_ERR, "OV519 Config failed");
3163 return -EBUSY;
3164}
3165
012d6b02
JFM		 3166/* this function is called at probe and resume time */
3167static int sd_init(struct gspca_dev *gspca_dev)
6a7eba24 3168{
4202f71c
JFM		 3169 struct sd *sd = (struct sd *) gspca_dev;
3170
3171 /* initialize the sensor */
3172 switch (sd->sensor) {
635118d5
HG		 3173 case SEN_OV2610:
3174 if (write_i2c_regvals(sd, norm_2610, ARRAY_SIZE(norm_2610)))
3175 return -EIO;
3176 /* Enable autogain, autoexpo, awb, bandfilter */
3177 if (i2c_w_mask(sd, 0x13, 0x27, 0x27) < 0)
3178 return -EIO;
3179 break;
3180 case SEN_OV3610:
3181 if (write_i2c_regvals(sd, norm_3620b, ARRAY_SIZE(norm_3620b)))
3182 return -EIO;
3183 /* Enable autogain, autoexpo, awb, bandfilter */
3184 if (i2c_w_mask(sd, 0x13, 0x27, 0x27) < 0)
3185 return -EIO;
3186 break;
4202f71c
JFM		 3187 case SEN_OV6620:
3188 if (write_i2c_regvals(sd, norm_6x20, ARRAY_SIZE(norm_6x20)))
3189 return -EIO;
3190 break;
3191 case SEN_OV6630:
7d971373 3192 case SEN_OV66308AF:
4202f71c
JFM		 3193 if (write_i2c_regvals(sd, norm_6x30, ARRAY_SIZE(norm_6x30)))
3194 return -EIO;
3195 break;
3196 default:
3197/* case SEN_OV7610: */
3198/* case SEN_OV76BE: */
3199 if (write_i2c_regvals(sd, norm_7610, ARRAY_SIZE(norm_7610)))
3200 return -EIO;
ae49c404
HG		 3201 if (i2c_w_mask(sd, 0x0e, 0x00, 0x40))
3202 return -EIO;
4202f71c
JFM		 3203 break;
3204 case SEN_OV7620:
859cc470 3205 case SEN_OV7620AE:
4202f71c
JFM		 3206 if (write_i2c_regvals(sd, norm_7620, ARRAY_SIZE(norm_7620)))
3207 return -EIO;
3208 break;
3209 case SEN_OV7640:
035d3a3d 3210 case SEN_OV7648:
4202f71c
JFM		 3211 if (write_i2c_regvals(sd, norm_7640, ARRAY_SIZE(norm_7640)))
3212 return -EIO;
3213 break;
3214 case SEN_OV7670:
3215 if (write_i2c_regvals(sd, norm_7670, ARRAY_SIZE(norm_7670)))
3216 return -EIO;
3217 break;
3218 case SEN_OV8610:
3219 if (write_i2c_regvals(sd, norm_8610, ARRAY_SIZE(norm_8610)))
3220 return -EIO;
3221 break;
3222 }
6a7eba24
JFM		 3223 return 0;
3224}
3225
1876bb92
HG		 3226/* Set up the OV511/OV511+ with the given image parameters.
3227 *
3228 * Do not put any sensor-specific code in here (including I2C I/O functions)
3229 */
3230static int ov511_mode_init_regs(struct sd *sd)
3231{
3232 int hsegs, vsegs, packet_size, fps, needed;
3233 int interlaced = 0;
3234 struct usb_host_interface *alt;
3235 struct usb_interface *intf;
3236
3237 intf = usb_ifnum_to_if(sd->gspca_dev.dev, sd->gspca_dev.iface);
3238 alt = usb_altnum_to_altsetting(intf, sd->gspca_dev.alt);
3239 if (!alt) {
3240 PDEBUG(D_ERR, "Couldn't get altsetting");
3241 return -EIO;
3242 }
3243
3244 packet_size = le16_to_cpu(alt->endpoint[0].desc.wMaxPacketSize);
3245 reg_w(sd, R51x_FIFO_PSIZE, packet_size >> 5);
3246
3247 reg_w(sd, R511_CAM_UV_EN, 0x01);
3248 reg_w(sd, R511_SNAP_UV_EN, 0x01);
3249 reg_w(sd, R511_SNAP_OPTS, 0x03);
3250
3251 /* Here I'm assuming that snapshot size == image size.
3252 * I hope that's always true. --claudio
3253 */
3254 hsegs = (sd->gspca_dev.width >> 3) - 1;
3255 vsegs = (sd->gspca_dev.height >> 3) - 1;
3256
3257 reg_w(sd, R511_CAM_PXCNT, hsegs);
3258 reg_w(sd, R511_CAM_LNCNT, vsegs);
3259 reg_w(sd, R511_CAM_PXDIV, 0x00);
3260 reg_w(sd, R511_CAM_LNDIV, 0x00);
3261
3262 /* YUV420, low pass filter on */
3263 reg_w(sd, R511_CAM_OPTS, 0x03);
3264
3265 /* Snapshot additions */
3266 reg_w(sd, R511_SNAP_PXCNT, hsegs);
3267 reg_w(sd, R511_SNAP_LNCNT, vsegs);
3268 reg_w(sd, R511_SNAP_PXDIV, 0x00);
3269 reg_w(sd, R511_SNAP_LNDIV, 0x00);
3270
3271 /******** Set the framerate ********/
3272 if (frame_rate > 0)
3273 sd->frame_rate = frame_rate;
3274
3275 switch (sd->sensor) {
3276 case SEN_OV6620:
3277 /* No framerate control, doesn't like higher rates yet */
3278 sd->clockdiv = 3;
3279 break;
3280
3281 /* Note once the FIXME's in mode_init_ov_sensor_regs() are fixed
3282 for more sensors we need to do this for them too */
3283 case SEN_OV7620:
859cc470 3284 case SEN_OV7620AE:
1876bb92 3285 case SEN_OV7640:
035d3a3d 3286 case SEN_OV7648:
b282d873 3287 case SEN_OV76BE:
1876bb92
HG		 3288 if (sd->gspca_dev.width == 320)
3289 interlaced = 1;
3290 /* Fall through */
3291 case SEN_OV6630:
1876bb92
HG		 3292 case SEN_OV7610:
3293 case SEN_OV7670:
3294 switch (sd->frame_rate) {
3295 case 30:
3296 case 25:
3297 /* Not enough bandwidth to do 640x480 @ 30 fps */
3298 if (sd->gspca_dev.width != 640) {
3299 sd->clockdiv = 0;
3300 break;
3301 }
3302 /* Fall through for 640x480 case */
3303 default:
3304/* case 20: */
3305/* case 15: */
3306 sd->clockdiv = 1;
3307 break;
3308 case 10:
3309 sd->clockdiv = 2;
3310 break;
3311 case 5:
3312 sd->clockdiv = 5;
3313 break;
3314 }
3315 if (interlaced) {
3316 sd->clockdiv = (sd->clockdiv + 1) * 2 - 1;
3317 /* Higher then 10 does not work */
3318 if (sd->clockdiv > 10)
3319 sd->clockdiv = 10;
3320 }
3321 break;
3322
3323 case SEN_OV8610:
3324 /* No framerate control ?? */
3325 sd->clockdiv = 0;
3326 break;
3327 }
3328
3329 /* Check if we have enough bandwidth to disable compression */
3330 fps = (interlaced ? 60 : 30) / (sd->clockdiv + 1) + 1;
3331 needed = fps * sd->gspca_dev.width * sd->gspca_dev.height * 3 / 2;
3332 /* 1400 is a conservative estimate of the max nr of isoc packets/sec */
3333 if (needed > 1400 * packet_size) {
3334 /* Enable Y and UV quantization and compression */
3335 reg_w(sd, R511_COMP_EN, 0x07);
3336 reg_w(sd, R511_COMP_LUT_EN, 0x03);
3337 } else {
3338 reg_w(sd, R511_COMP_EN, 0x06);
3339 reg_w(sd, R511_COMP_LUT_EN, 0x00);
3340 }
3341
3342 reg_w(sd, R51x_SYS_RESET, OV511_RESET_OMNICE);
3343 reg_w(sd, R51x_SYS_RESET, 0);
3344
3345 return 0;
3346}
3347
49809d6a
HG		 3348/* Sets up the OV518/OV518+ with the given image parameters
3349 *
3350 * OV518 needs a completely different approach, until we can figure out what
3351 * the individual registers do. Also, only 15 FPS is supported now.
3352 *
3353 * Do not put any sensor-specific code in here (including I2C I/O functions)
3354 */
3355static int ov518_mode_init_regs(struct sd *sd)
3356{
b282d873
HG		 3357 int hsegs, vsegs, packet_size;
3358 struct usb_host_interface *alt;
3359 struct usb_interface *intf;
3360
3361 intf = usb_ifnum_to_if(sd->gspca_dev.dev, sd->gspca_dev.iface);
3362 alt = usb_altnum_to_altsetting(intf, sd->gspca_dev.alt);
3363 if (!alt) {
3364 PDEBUG(D_ERR, "Couldn't get altsetting");
3365 return -EIO;
3366 }
3367
3368 packet_size = le16_to_cpu(alt->endpoint[0].desc.wMaxPacketSize);
3369 ov518_reg_w32(sd, R51x_FIFO_PSIZE, packet_size & ~7, 2);
49809d6a
HG		 3370
3371 /******** Set the mode ********/
3372
3373 reg_w(sd, 0x2b, 0);
3374 reg_w(sd, 0x2c, 0);
3375 reg_w(sd, 0x2d, 0);
3376 reg_w(sd, 0x2e, 0);
3377 reg_w(sd, 0x3b, 0);
3378 reg_w(sd, 0x3c, 0);
3379 reg_w(sd, 0x3d, 0);
3380 reg_w(sd, 0x3e, 0);
3381
3382 if (sd->bridge == BRIDGE_OV518) {
3383 /* Set 8-bit (YVYU) input format */
3384 reg_w_mask(sd, 0x20, 0x08, 0x08);
3385
3386 /* Set 12-bit (4:2:0) output format */
3387 reg_w_mask(sd, 0x28, 0x80, 0xf0);
3388 reg_w_mask(sd, 0x38, 0x80, 0xf0);
3389 } else {
3390 reg_w(sd, 0x28, 0x80);
3391 reg_w(sd, 0x38, 0x80);
3392 }
3393
3394 hsegs = sd->gspca_dev.width / 16;
3395 vsegs = sd->gspca_dev.height / 4;
3396
3397 reg_w(sd, 0x29, hsegs);
3398 reg_w(sd, 0x2a, vsegs);
3399
3400 reg_w(sd, 0x39, hsegs);
3401 reg_w(sd, 0x3a, vsegs);
3402
3403 /* Windows driver does this here; who knows why */
3404 reg_w(sd, 0x2f, 0x80);
3405
b282d873
HG		 3406 /******** Set the framerate ********/
3407 sd->clockdiv = 1;
49809d6a
HG		 3408
3409 /* Mode independent, but framerate dependent, regs */
b282d873
HG		 3410 /* 0x51: Clock divider; Only works on some cams which use 2 crystals */
3411 reg_w(sd, 0x51, 0x04);
49809d6a
HG		 3412 reg_w(sd, 0x22, 0x18);
3413 reg_w(sd, 0x23, 0xff);
3414
b282d873
HG		 3415 if (sd->bridge == BRIDGE_OV518PLUS) {
3416 switch (sd->sensor) {
859cc470 3417 case SEN_OV7620AE:
b282d873
HG		 3418 if (sd->gspca_dev.width == 320) {
3419 reg_w(sd, 0x20, 0x00);
3420 reg_w(sd, 0x21, 0x19);
3421 } else {
3422 reg_w(sd, 0x20, 0x60);
3423 reg_w(sd, 0x21, 0x1f);
3424 }
3425 break;
859cc470
HG		 3426 case SEN_OV7620:
3427 reg_w(sd, 0x20, 0x00);
3428 reg_w(sd, 0x21, 0x19);
3429 break;
b282d873
HG		 3430 default:
3431 reg_w(sd, 0x21, 0x19);
3432 }
3433 } else
49809d6a
HG		 3434 reg_w(sd, 0x71, 0x17); /* Compression-related? */
3435
3436 /* FIXME: Sensor-specific */
3437 /* Bit 5 is what matters here. Of course, it is "reserved" */
3438 i2c_w(sd, 0x54, 0x23);
3439
3440 reg_w(sd, 0x2f, 0x80);
3441
3442 if (sd->bridge == BRIDGE_OV518PLUS) {
3443 reg_w(sd, 0x24, 0x94);
3444 reg_w(sd, 0x25, 0x90);
3445 ov518_reg_w32(sd, 0xc4, 400, 2); /* 190h */
3446 ov518_reg_w32(sd, 0xc6, 540, 2); /* 21ch */
3447 ov518_reg_w32(sd, 0xc7, 540, 2); /* 21ch */
3448 ov518_reg_w32(sd, 0xc8, 108, 2); /* 6ch */
3449 ov518_reg_w32(sd, 0xca, 131098, 3); /* 2001ah */
3450 ov518_reg_w32(sd, 0xcb, 532, 2); /* 214h */
3451 ov518_reg_w32(sd, 0xcc, 2400, 2); /* 960h */
3452 ov518_reg_w32(sd, 0xcd, 32, 2); /* 20h */
3453 ov518_reg_w32(sd, 0xce, 608, 2); /* 260h */
3454 } else {
3455 reg_w(sd, 0x24, 0x9f);
3456 reg_w(sd, 0x25, 0x90);
3457 ov518_reg_w32(sd, 0xc4, 400, 2); /* 190h */
3458 ov518_reg_w32(sd, 0xc6, 381, 2); /* 17dh */
3459 ov518_reg_w32(sd, 0xc7, 381, 2); /* 17dh */
3460 ov518_reg_w32(sd, 0xc8, 128, 2); /* 80h */
3461 ov518_reg_w32(sd, 0xca, 183331, 3); /* 2cc23h */
3462 ov518_reg_w32(sd, 0xcb, 746, 2); /* 2eah */
3463 ov518_reg_w32(sd, 0xcc, 1750, 2); /* 6d6h */
3464 ov518_reg_w32(sd, 0xcd, 45, 2); /* 2dh */
3465 ov518_reg_w32(sd, 0xce, 851, 2); /* 353h */
3466 }
3467
3468 reg_w(sd, 0x2f, 0x80);
3469
3470 return 0;
3471}
3472
3473
6a7eba24
JFM		 3474/* Sets up the OV519 with the given image parameters
3475 *
3476 * OV519 needs a completely different approach, until we can figure out what
3477 * the individual registers do.
3478 *
3479 * Do not put any sensor-specific code in here (including I2C I/O functions)
3480 */
594f5b8b 3481static int ov519_mode_init_regs(struct sd *sd)
6a7eba24 3482{
a5ae2062 3483 static const struct ov_regvals mode_init_519_ov7670[] = {
6a7eba24
JFM		 3484 { 0x5d, 0x03 }, /* Turn off suspend mode */
3485 { 0x53, 0x9f }, /* was 9b in 1.65-1.08 */
3486 { 0x54, 0x0f }, /* bit2 (jpeg enable) */
3487 { 0xa2, 0x20 }, /* a2-a5 are undocumented */
3488 { 0xa3, 0x18 },
3489 { 0xa4, 0x04 },
3490 { 0xa5, 0x28 },
3491 { 0x37, 0x00 }, /* SetUsbInit */
3492 { 0x55, 0x02 }, /* 4.096 Mhz audio clock */
3493 /* Enable both fields, YUV Input, disable defect comp (why?) */
3494 { 0x20, 0x0c },
3495 { 0x21, 0x38 },
3496 { 0x22, 0x1d },
3497 { 0x17, 0x50 }, /* undocumented */
3498 { 0x37, 0x00 }, /* undocumented */
3499 { 0x40, 0xff }, /* I2C timeout counter */
3500 { 0x46, 0x00 }, /* I2C clock prescaler */
3501 { 0x59, 0x04 }, /* new from windrv 090403 */
3502 { 0xff, 0x00 }, /* undocumented */
3503 /* windows reads 0x55 at this point, why? */
3504 };
3505
a5ae2062 3506 static const struct ov_regvals mode_init_519[] = {
6a7eba24
JFM		 3507 { 0x5d, 0x03 }, /* Turn off suspend mode */
3508 { 0x53, 0x9f }, /* was 9b in 1.65-1.08 */
3509 { 0x54, 0x0f }, /* bit2 (jpeg enable) */
3510 { 0xa2, 0x20 }, /* a2-a5 are undocumented */
3511 { 0xa3, 0x18 },
3512 { 0xa4, 0x04 },
3513 { 0xa5, 0x28 },
3514 { 0x37, 0x00 }, /* SetUsbInit */
3515 { 0x55, 0x02 }, /* 4.096 Mhz audio clock */
3516 /* Enable both fields, YUV Input, disable defect comp (why?) */
3517 { 0x22, 0x1d },
3518 { 0x17, 0x50 }, /* undocumented */
3519 { 0x37, 0x00 }, /* undocumented */
3520 { 0x40, 0xff }, /* I2C timeout counter */
3521 { 0x46, 0x00 }, /* I2C clock prescaler */
3522 { 0x59, 0x04 }, /* new from windrv 090403 */
3523 { 0xff, 0x00 }, /* undocumented */
3524 /* windows reads 0x55 at this point, why? */
3525 };
3526
6a7eba24
JFM		 3527 /******** Set the mode ********/
3528 if (sd->sensor != SEN_OV7670) {
3529 if (write_regvals(sd, mode_init_519,
a5ae2062 3530 ARRAY_SIZE(mode_init_519)))
6a7eba24 3531 return -EIO;
035d3a3d
HG		 3532 if (sd->sensor == SEN_OV7640 ||
3533 sd->sensor == SEN_OV7648) {
594f5b8b 3534 /* Select 8-bit input mode */
ac40b1fa 3535 reg_w_mask(sd, OV519_R20_DFR, 0x10, 0x10);
594f5b8b 3536 }
6a7eba24
JFM		 3537 } else {
3538 if (write_regvals(sd, mode_init_519_ov7670,
a5ae2062 3539 ARRAY_SIZE(mode_init_519_ov7670)))
6a7eba24
JFM		 3540 return -EIO;
3541 }
3542
ac40b1fa
JFM		 3543 reg_w(sd, OV519_R10_H_SIZE, sd->gspca_dev.width >> 4);
3544 reg_w(sd, OV519_R11_V_SIZE, sd->gspca_dev.height >> 3);
80142efa
HG		 3545 if (sd->sensor == SEN_OV7670 &&
3546 sd->gspca_dev.cam.cam_mode[sd->gspca_dev.curr_mode].priv)
3547 reg_w(sd, OV519_R12_X_OFFSETL, 0x04);
035d3a3d
HG		 3548 else if (sd->sensor == SEN_OV7648 &&
3549 sd->gspca_dev.cam.cam_mode[sd->gspca_dev.curr_mode].priv)
3550 reg_w(sd, OV519_R12_X_OFFSETL, 0x01);
80142efa
HG		 3551 else
3552 reg_w(sd, OV519_R12_X_OFFSETL, 0x00);
ac40b1fa
JFM		 3553 reg_w(sd, OV519_R13_X_OFFSETH, 0x00);
3554 reg_w(sd, OV519_R14_Y_OFFSETL, 0x00);
3555 reg_w(sd, OV519_R15_Y_OFFSETH, 0x00);
3556 reg_w(sd, OV519_R16_DIVIDER, 0x00);
3557 reg_w(sd, OV519_R25_FORMAT, 0x03); /* YUV422 */
6a7eba24
JFM		 3558 reg_w(sd, 0x26, 0x00); /* Undocumented */
3559
3560 /******** Set the framerate ********/
3561 if (frame_rate > 0)
3562 sd->frame_rate = frame_rate;
3563
3564/* FIXME: These are only valid at the max resolution. */
3565 sd->clockdiv = 0;
594f5b8b
JFM		 3566 switch (sd->sensor) {
3567 case SEN_OV7640:
035d3a3d 3568 case SEN_OV7648:
6a7eba24 3569 switch (sd->frame_rate) {
53e74515
JFM		 3570 default:
3571/* case 30: */
6a7eba24
JFM		 3572 reg_w(sd, 0xa4, 0x0c);
3573 reg_w(sd, 0x23, 0xff);
3574 break;
3575 case 25:
3576 reg_w(sd, 0xa4, 0x0c);
3577 reg_w(sd, 0x23, 0x1f);
3578 break;
3579 case 20:
3580 reg_w(sd, 0xa4, 0x0c);
3581 reg_w(sd, 0x23, 0x1b);
3582 break;
53e74515 3583 case 15:
6a7eba24
JFM		 3584 reg_w(sd, 0xa4, 0x04);
3585 reg_w(sd, 0x23, 0xff);
3586 sd->clockdiv = 1;
3587 break;
3588 case 10:
3589 reg_w(sd, 0xa4, 0x04);
3590 reg_w(sd, 0x23, 0x1f);
3591 sd->clockdiv = 1;
3592 break;
3593 case 5:
3594 reg_w(sd, 0xa4, 0x04);
3595 reg_w(sd, 0x23, 0x1b);
3596 sd->clockdiv = 1;
3597 break;
3598 }
594f5b8b
JFM		 3599 break;
3600 case SEN_OV8610:
6a7eba24
JFM		 3601 switch (sd->frame_rate) {
3602 default: /* 15 fps */
3603/* case 15: */
3604 reg_w(sd, 0xa4, 0x06);
3605 reg_w(sd, 0x23, 0xff);
3606 break;
3607 case 10:
3608 reg_w(sd, 0xa4, 0x06);
3609 reg_w(sd, 0x23, 0x1f);
3610 break;
3611 case 5:
3612 reg_w(sd, 0xa4, 0x06);
3613 reg_w(sd, 0x23, 0x1b);
3614 break;
3615 }
594f5b8b
JFM		 3616 break;
3617 case SEN_OV7670: /* guesses, based on 7640 */
6a7eba24
JFM		 3618 PDEBUG(D_STREAM, "Setting framerate to %d fps",
3619 (sd->frame_rate == 0) ? 15 : sd->frame_rate);
594f5b8b 3620 reg_w(sd, 0xa4, 0x10);
6a7eba24
JFM		 3621 switch (sd->frame_rate) {
3622 case 30:
6a7eba24
JFM		 3623 reg_w(sd, 0x23, 0xff);
3624 break;
3625 case 20:
6a7eba24
JFM		 3626 reg_w(sd, 0x23, 0x1b);
3627 break;
594f5b8b
JFM		 3628 default:
3629/* case 15: */
6a7eba24
JFM		 3630 reg_w(sd, 0x23, 0xff);
3631 sd->clockdiv = 1;
3632 break;
3633 }
594f5b8b 3634 break;
6a7eba24 3635 }
6a7eba24
JFM		 3636 return 0;
3637}
3638
594f5b8b 3639static int mode_init_ov_sensor_regs(struct sd *sd)
6a7eba24 3640{
594f5b8b 3641 struct gspca_dev *gspca_dev;
ebbb5c3e
HG		 3642 int qvga, xstart, xend, ystart, yend;
3643 __u8 v;
594f5b8b
JFM		 3644
3645 gspca_dev = &sd->gspca_dev;
124cc9c0 3646 qvga = gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].priv & 1;
6a7eba24
JFM		 3647
3648 /******** Mode (VGA/QVGA) and sensor specific regs ********/
3649 switch (sd->sensor) {
635118d5
HG		 3650 case SEN_OV2610:
3651 i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
3652 i2c_w_mask(sd, 0x28, qvga ? 0x00 : 0x20, 0x20);
3653 i2c_w(sd, 0x24, qvga ? 0x20 : 0x3a);
3654 i2c_w(sd, 0x25, qvga ? 0x30 : 0x60);
3655 i2c_w_mask(sd, 0x2d, qvga ? 0x40 : 0x00, 0x40);
3656 i2c_w_mask(sd, 0x67, qvga ? 0xf0 : 0x90, 0xf0);
3657 i2c_w_mask(sd, 0x74, qvga ? 0x20 : 0x00, 0x20);
3658 return 0;
ebbb5c3e 3659 case SEN_OV3610:
635118d5
HG		 3660 if (qvga) {
3661 xstart = (1040 - gspca_dev->width) / 2 + (0x1f << 4);
b46aaa02 3662 ystart = (776 - gspca_dev->height) / 2;
635118d5 3663 } else {
b46aaa02 3664 xstart = (2076 - gspca_dev->width) / 2 + (0x10 << 4);
635118d5
HG		 3665 ystart = (1544 - gspca_dev->height) / 2;
3666 }
3667 xend = xstart + gspca_dev->width;
3668 yend = ystart + gspca_dev->height;
3669 /* Writing to the COMH register resets the other windowing regs
3670 to their default values, so we must do this first. */
3671 i2c_w_mask(sd, 0x12, qvga ? 0x40 : 0x00, 0xf0);
3672 i2c_w_mask(sd, 0x32,
3673 (((xend >> 1) & 7) << 3) | ((xstart >> 1) & 7),
3674 0x3f);
3675 i2c_w_mask(sd, 0x03,
3676 (((yend >> 1) & 3) << 2) | ((ystart >> 1) & 3),
3677 0x0f);
3678 i2c_w(sd, 0x17, xstart >> 4);
3679 i2c_w(sd, 0x18, xend >> 4);
3680 i2c_w(sd, 0x19, ystart >> 3);
3681 i2c_w(sd, 0x1a, yend >> 3);
3682 return 0;
6a7eba24
JFM		 3683 case SEN_OV8610:
3684 /* For OV8610 qvga means qsvga */
3685 i2c_w_mask(sd, OV7610_REG_COM_C, qvga ? (1 << 5) : 0, 1 << 5);
ebbb5c3e
HG		 3686 i2c_w_mask(sd, 0x13, 0x00, 0x20); /* Select 16 bit data bus */
3687 i2c_w_mask(sd, 0x12, 0x04, 0x06); /* AWB: 1 Test pattern: 0 */
3688 i2c_w_mask(sd, 0x2d, 0x00, 0x40); /* from windrv 090403 */
3689 i2c_w_mask(sd, 0x28, 0x20, 0x20); /* progressive mode on */
6a7eba24
JFM		 3690 break;
3691 case SEN_OV7610:
3692 i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
ebbb5c3e
HG		 3693 i2c_w(sd, 0x35, qvga?0x1e:0x9e);
3694 i2c_w_mask(sd, 0x13, 0x00, 0x20); /* Select 16 bit data bus */
3695 i2c_w_mask(sd, 0x12, 0x04, 0x06); /* AWB: 1 Test pattern: 0 */
6a7eba24
JFM		 3696 break;
3697 case SEN_OV7620:
859cc470 3698 case SEN_OV7620AE:
b282d873 3699 case SEN_OV76BE:
6a7eba24
JFM		 3700 i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
3701 i2c_w_mask(sd, 0x28, qvga ? 0x00 : 0x20, 0x20);
3702 i2c_w(sd, 0x24, qvga ? 0x20 : 0x3a);
3703 i2c_w(sd, 0x25, qvga ? 0x30 : 0x60);
3704 i2c_w_mask(sd, 0x2d, qvga ? 0x40 : 0x00, 0x40);
b282d873 3705 i2c_w_mask(sd, 0x67, qvga ? 0xb0 : 0x90, 0xf0);
6a7eba24 3706 i2c_w_mask(sd, 0x74, qvga ? 0x20 : 0x00, 0x20);
ebbb5c3e
HG		 3707 i2c_w_mask(sd, 0x13, 0x00, 0x20); /* Select 16 bit data bus */
3708 i2c_w_mask(sd, 0x12, 0x04, 0x06); /* AWB: 1 Test pattern: 0 */
3709 if (sd->sensor == SEN_OV76BE)
3710 i2c_w(sd, 0x35, qvga ? 0x1e : 0x9e);
6a7eba24 3711 break;
6a7eba24 3712 case SEN_OV7640:
035d3a3d 3713 case SEN_OV7648:
6a7eba24
JFM		 3714 i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
3715 i2c_w_mask(sd, 0x28, qvga ? 0x00 : 0x20, 0x20);
8d0082fa
HG		 3716 /* Setting this undocumented bit in qvga mode removes a very
3717 annoying vertical shaking of the image */
035d3a3d 3718 i2c_w_mask(sd, 0x2d, qvga ? 0x40 : 0x00, 0x40);
8d0082fa 3719 /* Unknown */
035d3a3d 3720 i2c_w_mask(sd, 0x67, qvga ? 0xf0 : 0x90, 0xf0);
8d0082fa 3721 /* Allow higher automatic gain (to allow higher framerates) */
035d3a3d 3722 i2c_w_mask(sd, 0x74, qvga ? 0x20 : 0x00, 0x20);
ebbb5c3e 3723 i2c_w_mask(sd, 0x12, 0x04, 0x04); /* AWB: 1 */
6a7eba24
JFM		 3724 break;
3725 case SEN_OV7670:
3726 /* set COM7_FMT_VGA or COM7_FMT_QVGA
3727 * do we need to set anything else?
3728 * HSTART etc are set in set_ov_sensor_window itself */
3729 i2c_w_mask(sd, OV7670_REG_COM7,
3730 qvga ? OV7670_COM7_FMT_QVGA : OV7670_COM7_FMT_VGA,
3731 OV7670_COM7_FMT_MASK);
ebbb5c3e
HG		 3732 i2c_w_mask(sd, 0x13, 0x00, 0x20); /* Select 16 bit data bus */
3733 i2c_w_mask(sd, OV7670_REG_COM8, OV7670_COM8_AWB,
3734 OV7670_COM8_AWB);
3735 if (qvga) { /* QVGA from ov7670.c by
3736 * Jonathan Corbet */
3737 xstart = 164;
3738 xend = 28;
3739 ystart = 14;
3740 yend = 494;
3741 } else { /* VGA */
3742 xstart = 158;
3743 xend = 14;
3744 ystart = 10;
3745 yend = 490;
3746 }
3747 /* OV7670 hardware window registers are split across
3748 * multiple locations */
3749 i2c_w(sd, OV7670_REG_HSTART, xstart >> 3);
3750 i2c_w(sd, OV7670_REG_HSTOP, xend >> 3);
3751 v = i2c_r(sd, OV7670_REG_HREF);
3752 v = (v & 0xc0) | ((xend & 0x7) << 3) | (xstart & 0x07);
3753 msleep(10); /* need to sleep between read and write to
3754 * same reg! */
3755 i2c_w(sd, OV7670_REG_HREF, v);
3756
3757 i2c_w(sd, OV7670_REG_VSTART, ystart >> 2);
3758 i2c_w(sd, OV7670_REG_VSTOP, yend >> 2);
3759 v = i2c_r(sd, OV7670_REG_VREF);
3760 v = (v & 0xc0) | ((yend & 0x3) << 2) | (ystart & 0x03);
3761 msleep(10); /* need to sleep between read and write to
3762 * same reg! */
3763 i2c_w(sd, OV7670_REG_VREF, v);
6a7eba24
JFM		 3764 break;
3765 case SEN_OV6620:
ebbb5c3e
HG		 3766 i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
3767 i2c_w_mask(sd, 0x13, 0x00, 0x20); /* Select 16 bit data bus */
3768 i2c_w_mask(sd, 0x12, 0x04, 0x06); /* AWB: 1 Test pattern: 0 */
3769 break;
6a7eba24 3770 case SEN_OV6630:
7d971373 3771 case SEN_OV66308AF:
6a7eba24 3772 i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
ebbb5c3e 3773 i2c_w_mask(sd, 0x12, 0x04, 0x06); /* AWB: 1 Test pattern: 0 */
6a7eba24
JFM		 3774 break;
3775 default:
3776 return -EINVAL;
3777 }
3778
6a7eba24 3779 /******** Clock programming ********/
ae49c404 3780 i2c_w(sd, 0x11, sd->clockdiv);
6a7eba24 3781
6a7eba24
JFM		 3782 return 0;
3783}
3784
594f5b8b 3785static void sethvflip(struct sd *sd)
0cd6759d 3786{
594f5b8b
JFM		 3787 if (sd->sensor != SEN_OV7670)
3788 return;
0cd6759d
JFM		 3789 if (sd->gspca_dev.streaming)
3790 ov51x_stop(sd);
3791 i2c_w_mask(sd, OV7670_REG_MVFP,
594f5b8b
JFM		 3792 OV7670_MVFP_MIRROR * sd->hflip
3793 | OV7670_MVFP_VFLIP * sd->vflip,
3794 OV7670_MVFP_MIRROR | OV7670_MVFP_VFLIP);
0cd6759d
JFM		 3795 if (sd->gspca_dev.streaming)
3796 ov51x_restart(sd);
3797}
3798
594f5b8b 3799static int set_ov_sensor_window(struct sd *sd)
6a7eba24 3800{
594f5b8b 3801 struct gspca_dev *gspca_dev;
124cc9c0 3802 int qvga, crop;
6a7eba24 3803 int hwsbase, hwebase, vwsbase, vwebase, hwscale, vwscale;
ebbb5c3e 3804 int ret;
6a7eba24 3805
635118d5 3806 /* mode setup is fully handled in mode_init_ov_sensor_regs for these */
ebbb5c3e
HG		 3807 if (sd->sensor == SEN_OV2610 || sd->sensor == SEN_OV3610 ||
3808 sd->sensor == SEN_OV7670)
635118d5
HG		 3809 return mode_init_ov_sensor_regs(sd);
3810
594f5b8b 3811 gspca_dev = &sd->gspca_dev;
124cc9c0
HG		 3812 qvga = gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].priv & 1;
3813 crop = gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].priv & 2;
594f5b8b 3814
6a7eba24
JFM		 3815 /* The different sensor ICs handle setting up of window differently.
3816 * IF YOU SET IT WRONG, YOU WILL GET ALL ZERO ISOC DATA FROM OV51x!! */
3817 switch (sd->sensor) {
3818 case SEN_OV8610:
3819 hwsbase = 0x1e;
3820 hwebase = 0x1e;
3821 vwsbase = 0x02;
3822 vwebase = 0x02;
3823 break;
3824 case SEN_OV7610:
3825 case SEN_OV76BE:
3826 hwsbase = 0x38;
3827 hwebase = 0x3a;
3828 vwsbase = vwebase = 0x05;
3829 break;
3830 case SEN_OV6620:
3831 case SEN_OV6630:
7d971373 3832 case SEN_OV66308AF:
6a7eba24
JFM		 3833 hwsbase = 0x38;
3834 hwebase = 0x3a;
3835 vwsbase = 0x05;
3836 vwebase = 0x06;
7d971373 3837 if (sd->sensor == SEN_OV66308AF && qvga)
49809d6a 3838 /* HDG: this fixes U and V getting swapped */
7d971373 3839 hwsbase++;
124cc9c0
HG		 3840 if (crop) {
3841 hwsbase += 8;
3842 hwebase += 8;
3843 vwsbase += 11;
3844 vwebase += 11;
3845 }
6a7eba24
JFM		 3846 break;
3847 case SEN_OV7620:
859cc470 3848 case SEN_OV7620AE:
6a7eba24
JFM		 3849 hwsbase = 0x2f; /* From 7620.SET (spec is wrong) */
3850 hwebase = 0x2f;
3851 vwsbase = vwebase = 0x05;
3852 break;
3853 case SEN_OV7640:
035d3a3d 3854 case SEN_OV7648:
6a7eba24
JFM		 3855 hwsbase = 0x1a;
3856 hwebase = 0x1a;
3857 vwsbase = vwebase = 0x03;
3858 break;
6a7eba24
JFM		 3859 default:
3860 return -EINVAL;
3861 }
3862
3863 switch (sd->sensor) {
3864 case SEN_OV6620:
3865 case SEN_OV6630:
7d971373 3866 case SEN_OV66308AF:
594f5b8b 3867 if (qvga) { /* QCIF */
6a7eba24
JFM		 3868 hwscale = 0;
3869 vwscale = 0;
3870 } else { /* CIF */
3871 hwscale = 1;
3872 vwscale = 1; /* The datasheet says 0;
3873 * it's wrong */
3874 }
3875 break;
3876 case SEN_OV8610:
594f5b8b 3877 if (qvga) { /* QSVGA */
6a7eba24
JFM		 3878 hwscale = 1;
3879 vwscale = 1;
3880 } else { /* SVGA */
3881 hwscale = 2;
3882 vwscale = 2;
3883 }
3884 break;
3885 default: /* SEN_OV7xx0 */
594f5b8b 3886 if (qvga) { /* QVGA */
6a7eba24
JFM		 3887 hwscale = 1;
3888 vwscale = 0;
3889 } else { /* VGA */
3890 hwscale = 2;
3891 vwscale = 1;
3892 }
3893 }
3894
594f5b8b 3895 ret = mode_init_ov_sensor_regs(sd);
6a7eba24
JFM		 3896 if (ret < 0)
3897 return ret;
3898
ebbb5c3e 3899 i2c_w(sd, 0x17, hwsbase);
a511ba94 3900 i2c_w(sd, 0x18, hwebase + (sd->sensor_width >> hwscale));
ebbb5c3e 3901 i2c_w(sd, 0x19, vwsbase);
a511ba94 3902 i2c_w(sd, 0x1a, vwebase + (sd->sensor_height >> vwscale));
6a7eba24 3903
6a7eba24
JFM		 3904 return 0;
3905}
3906
6a7eba24 3907/* -- start the camera -- */
72ab97ce 3908static int sd_start(struct gspca_dev *gspca_dev)
6a7eba24
JFM		 3909{
3910 struct sd *sd = (struct sd *) gspca_dev;
49809d6a 3911 int ret = 0;
6a7eba24 3912
a511ba94
HG		 3913 /* Default for most bridges, allow bridge_mode_init_regs to override */
3914 sd->sensor_width = sd->gspca_dev.width;
3915 sd->sensor_height = sd->gspca_dev.height;
3916
49809d6a 3917 switch (sd->bridge) {
1876bb92
HG		 3918 case BRIDGE_OV511:
3919 case BRIDGE_OV511PLUS:
3920 ret = ov511_mode_init_regs(sd);
3921 break;
49809d6a
HG		 3922 case BRIDGE_OV518:
3923 case BRIDGE_OV518PLUS:
3924 ret = ov518_mode_init_regs(sd);
3925 break;
3926 case BRIDGE_OV519:
3927 ret = ov519_mode_init_regs(sd);
3928 break;
b46aaa02 3929 /* case BRIDGE_OVFX2: nothing to do */
a511ba94
HG		 3930 case BRIDGE_W9968CF:
3931 ret = w9968cf_mode_init_regs(sd);
3932 break;
49809d6a 3933 }
6a7eba24
JFM		 3934 if (ret < 0)
3935 goto out;
49809d6a 3936
594f5b8b 3937 ret = set_ov_sensor_window(sd);
6a7eba24
JFM		 3938 if (ret < 0)
3939 goto out;
3940
49809d6a
HG		 3941 setcontrast(gspca_dev);
3942 setbrightness(gspca_dev);
3943 setcolors(gspca_dev);
02ab18b0
HG		 3944 sethvflip(sd);
3945 setautobrightness(sd);
3946 setfreq(sd);
49809d6a 3947
417a4d26
HG		 3948 /* Force clear snapshot state in case the snapshot button was
3949 pressed while we weren't streaming */
3950 sd->snapshot_needs_reset = 1;
3951 sd_reset_snapshot(gspca_dev);
3952 sd->snapshot_pressed = 0;
3953
594f5b8b 3954 ret = ov51x_restart(sd);
6a7eba24
JFM		 3955 if (ret < 0)
3956 goto out;
6a7eba24 3957 ov51x_led_control(sd, 1);
72ab97ce 3958 return 0;
6a7eba24
JFM		 3959out:
3960 PDEBUG(D_ERR, "camera start error:%d", ret);
72ab97ce 3961 return ret;
6a7eba24
JFM		 3962}
3963
3964static void sd_stopN(struct gspca_dev *gspca_dev)
3965{
ac40b1fa
JFM		 3966 struct sd *sd = (struct sd *) gspca_dev;
3967
3968 ov51x_stop(sd);
3969 ov51x_led_control(sd, 0);
6a7eba24
JFM		 3970}
3971
79b35902
HG		 3972static void sd_stop0(struct gspca_dev *gspca_dev)
3973{
3974 struct sd *sd = (struct sd *) gspca_dev;
3975
3976 if (sd->bridge == BRIDGE_W9968CF)
3977 w9968cf_stop0(sd);
3978}
3979
1876bb92 3980static void ov511_pkt_scan(struct gspca_dev *gspca_dev,
76dd272b
JFM		 3981 u8 *in, /* isoc packet */
3982 int len) /* iso packet length */
1876bb92
HG		 3983{
3984 struct sd *sd = (struct sd *) gspca_dev;
3985
3986 /* SOF/EOF packets have 1st to 8th bytes zeroed and the 9th
3987 * byte non-zero. The EOF packet has image width/height in the
3988 * 10th and 11th bytes. The 9th byte is given as follows:
3989 *
3990 * bit 7: EOF
3991 * 6: compression enabled
3992 * 5: 422/420/400 modes
3993 * 4: 422/420/400 modes
3994 * 3: 1
3995 * 2: snapshot button on
3996 * 1: snapshot frame
3997 * 0: even/odd field
3998 */
3999 if (!(in[0] | in[1] | in[2] | in[3] | in[4] | in[5] | in[6] | in[7]) &&
4000 (in[8] & 0x08)) {
4001 if (in[8] & 0x80) {
4002 /* Frame end */
4003 if ((in[9] + 1) * 8 != gspca_dev->width ||
4004 (in[10] + 1) * 8 != gspca_dev->height) {
4005 PDEBUG(D_ERR, "Invalid frame size, got: %dx%d,"
4006 " requested: %dx%d\n",
4007 (in[9] + 1) * 8, (in[10] + 1) * 8,
4008 gspca_dev->width, gspca_dev->height);
4009 gspca_dev->last_packet_type = DISCARD_PACKET;
4010 return;
4011 }
4012 /* Add 11 byte footer to frame, might be usefull */
76dd272b 4013 gspca_frame_add(gspca_dev, LAST_PACKET, in, 11);
1876bb92
HG		 4014 return;
4015 } else {
4016 /* Frame start */
76dd272b 4017 gspca_frame_add(gspca_dev, FIRST_PACKET, in, 0);
1876bb92
HG		 4018 sd->packet_nr = 0;
4019 }
4020 }
4021
4022 /* Ignore the packet number */
4023 len--;
4024
4025 /* intermediate packet */
76dd272b 4026 gspca_frame_add(gspca_dev, INTER_PACKET, in, len);
1876bb92
HG		 4027}
4028
49809d6a 4029static void ov518_pkt_scan(struct gspca_dev *gspca_dev,
76dd272b 4030 u8 *data, /* isoc packet */
49809d6a
HG		 4031 int len) /* iso packet length */
4032{
92918a53 4033 struct sd *sd = (struct sd *) gspca_dev;
49809d6a
HG		 4034
4035 /* A false positive here is likely, until OVT gives me
4036 * the definitive SOF/EOF format */
4037 if ((!(data[0] | data[1] | data[2] | data[3] | data[5])) && data[6]) {
76dd272b
JFM		 4038 gspca_frame_add(gspca_dev, LAST_PACKET, NULL, 0);
4039 gspca_frame_add(gspca_dev, FIRST_PACKET, NULL, 0);
92918a53
HG		 4040 sd->packet_nr = 0;
4041 }
4042
4043 if (gspca_dev->last_packet_type == DISCARD_PACKET)
4044 return;
4045
4046 /* Does this device use packet numbers ? */
4047 if (len & 7) {
4048 len--;
4049 if (sd->packet_nr == data[len])
4050 sd->packet_nr++;
4051 /* The last few packets of the frame (which are all 0's
4052 except that they may contain part of the footer), are
4053 numbered 0 */
4054 else if (sd->packet_nr == 0 || data[len]) {
4055 PDEBUG(D_ERR, "Invalid packet nr: %d (expect: %d)",
4056 (int)data[len], (int)sd->packet_nr);
4057 gspca_dev->last_packet_type = DISCARD_PACKET;
4058 return;
4059 }
49809d6a
HG		 4060 }
4061
4062 /* intermediate packet */
76dd272b 4063 gspca_frame_add(gspca_dev, INTER_PACKET, data, len);
49809d6a
HG		 4064}
4065
417a4d26
HG		 4066static void ov519_handle_button(struct gspca_dev *gspca_dev, u8 state)
4067{
4068 struct sd *sd = (struct sd *) gspca_dev;
4069
4070 /* This should never happen, but better to check */
4071 if (state != 0 && state != 1)
4072 return;
4073
4074 /* We may need to reset the button state multiple times, as resetting
4075 does not work as long as the button stays pressed, so always set
4076 snapshot_needs_reset (instead of only on a state change to 1). */
4077 if (state)
4078 sd->snapshot_needs_reset = 1;
4079
4080 if (sd->snapshot_pressed != state) {
4081#ifdef CONFIG_INPUT
4082 input_report_key(gspca_dev->input_dev, KEY_CAMERA, state);
4083 input_sync(gspca_dev->input_dev);
4084#endif
4085
4086 sd->snapshot_pressed = state;
4087 }
4088}
4089
49809d6a 4090static void ov519_pkt_scan(struct gspca_dev *gspca_dev,
76dd272b 4091 u8 *data, /* isoc packet */
6a7eba24
JFM		 4092 int len) /* iso packet length */
4093{
4094 /* Header of ov519 is 16 bytes:
4095 * Byte Value Description
4096 * 0 0xff magic
4097 * 1 0xff magic
4098 * 2 0xff magic
4099 * 3 0xXX 0x50 = SOF, 0x51 = EOF
4100 * 9 0xXX 0x01 initial frame without data,
4101 * 0x00 standard frame with image
4102 * 14 Lo in EOF: length of image data / 8
4103 * 15 Hi
4104 */
4105
4106 if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff) {
4107 switch (data[3]) {
4108 case 0x50: /* start of frame */
417a4d26
HG		 4109 /* Don't check the button state here, as the state
4110 usually (always ?) changes at EOF and checking it
4111 here leads to unnecessary snapshot state resets. */
6a7eba24
JFM		 4112#define HDRSZ 16
4113 data += HDRSZ;
4114 len -= HDRSZ;
4115#undef HDRSZ
4116 if (data[0] == 0xff || data[1] == 0xd8)
76dd272b 4117 gspca_frame_add(gspca_dev, FIRST_PACKET,
6a7eba24
JFM		 4118 data, len);
4119 else
4120 gspca_dev->last_packet_type = DISCARD_PACKET;
4121 return;
4122 case 0x51: /* end of frame */
417a4d26 4123 ov519_handle_button(gspca_dev, data[11]);
6a7eba24
JFM		 4124 if (data[9] != 0)
4125 gspca_dev->last_packet_type = DISCARD_PACKET;
76dd272b
JFM		 4126 gspca_frame_add(gspca_dev, LAST_PACKET,
4127 NULL, 0);
6a7eba24
JFM		 4128 return;
4129 }
4130 }
4131
4132 /* intermediate packet */
76dd272b 4133 gspca_frame_add(gspca_dev, INTER_PACKET, data, len);
6a7eba24
JFM		 4134}
4135
b46aaa02 4136static void ovfx2_pkt_scan(struct gspca_dev *gspca_dev,
76dd272b 4137 u8 *data, /* isoc packet */
b46aaa02
HG		 4138 int len) /* iso packet length */
4139{
4140 /* A short read signals EOF */
4141 if (len < OVFX2_BULK_SIZE) {
76dd272b
JFM		 4142 gspca_frame_add(gspca_dev, LAST_PACKET, data, len);
4143 gspca_frame_add(gspca_dev, FIRST_PACKET, NULL, 0);
b46aaa02
HG		 4144 return;
4145 }
76dd272b 4146 gspca_frame_add(gspca_dev, INTER_PACKET, data, len);
b46aaa02
HG		 4147}
4148
49809d6a 4149static void sd_pkt_scan(struct gspca_dev *gspca_dev,
76dd272b 4150 u8 *data, /* isoc packet */
49809d6a
HG		 4151 int len) /* iso packet length */
4152{
4153 struct sd *sd = (struct sd *) gspca_dev;
4154
4155 switch (sd->bridge) {
4156 case BRIDGE_OV511:
4157 case BRIDGE_OV511PLUS:
76dd272b 4158 ov511_pkt_scan(gspca_dev, data, len);
49809d6a
HG		 4159 break;
4160 case BRIDGE_OV518:
4161 case BRIDGE_OV518PLUS:
76dd272b 4162 ov518_pkt_scan(gspca_dev, data, len);
49809d6a
HG		 4163 break;
4164 case BRIDGE_OV519:
76dd272b 4165 ov519_pkt_scan(gspca_dev, data, len);
49809d6a 4166 break;
b46aaa02 4167 case BRIDGE_OVFX2:
76dd272b 4168 ovfx2_pkt_scan(gspca_dev, data, len);
b46aaa02 4169 break;
a511ba94 4170 case BRIDGE_W9968CF:
76dd272b 4171 w9968cf_pkt_scan(gspca_dev, data, len);
a511ba94 4172 break;
49809d6a
HG		 4173 }
4174}
4175
6a7eba24
JFM		 4176/* -- management routines -- */
4177
4178static void setbrightness(struct gspca_dev *gspca_dev)
4179{
4180 struct sd *sd = (struct sd *) gspca_dev;
4181 int val;
6a7eba24
JFM		 4182
4183 val = sd->brightness;
6a7eba24
JFM		 4184 switch (sd->sensor) {
4185 case SEN_OV8610:
4186 case SEN_OV7610:
4187 case SEN_OV76BE:
4188 case SEN_OV6620:
4189 case SEN_OV6630:
7d971373 4190 case SEN_OV66308AF:
6a7eba24 4191 case SEN_OV7640:
035d3a3d 4192 case SEN_OV7648:
6a7eba24
JFM		 4193 i2c_w(sd, OV7610_REG_BRT, val);
4194 break;
4195 case SEN_OV7620:
859cc470 4196 case SEN_OV7620AE:
6a7eba24 4197 /* 7620 doesn't like manual changes when in auto mode */
02ab18b0 4198 if (!sd->autobrightness)
6a7eba24
JFM		 4199 i2c_w(sd, OV7610_REG_BRT, val);
4200 break;
4201 case SEN_OV7670:
594f5b8b 4202/*win trace
6a7eba24
JFM		 4203 * i2c_w_mask(sd, OV7670_REG_COM8, 0, OV7670_COM8_AEC); */
4204 i2c_w(sd, OV7670_REG_BRIGHT, ov7670_abs_to_sm(val));
4205 break;
4206 }
6a7eba24
JFM		 4207}
4208
4209static void setcontrast(struct gspca_dev *gspca_dev)
4210{
4211 struct sd *sd = (struct sd *) gspca_dev;
4212 int val;
6a7eba24
JFM		 4213
4214 val = sd->contrast;
6a7eba24
JFM		 4215 switch (sd->sensor) {
4216 case SEN_OV7610:
4217 case SEN_OV6620:
4218 i2c_w(sd, OV7610_REG_CNT, val);
4219 break;
4220 case SEN_OV6630:
7d971373 4221 case SEN_OV66308AF:
6a7eba24 4222 i2c_w_mask(sd, OV7610_REG_CNT, val >> 4, 0x0f);
49809d6a 4223 break;
6a7eba24 4224 case SEN_OV8610: {
a5ae2062 4225 static const __u8 ctab[] = {
6a7eba24
JFM		 4226 0x03, 0x09, 0x0b, 0x0f, 0x53, 0x6f, 0x35, 0x7f
4227 };
4228
4229 /* Use Y gamma control instead. Bit 0 enables it. */
4230 i2c_w(sd, 0x64, ctab[val >> 5]);
4231 break;
4232 }
859cc470
HG		 4233 case SEN_OV7620:
4234 case SEN_OV7620AE: {
a5ae2062 4235 static const __u8 ctab[] = {
6a7eba24
JFM		 4236 0x01, 0x05, 0x09, 0x11, 0x15, 0x35, 0x37, 0x57,
4237 0x5b, 0xa5, 0xa7, 0xc7, 0xc9, 0xcf, 0xef, 0xff
4238 };
4239
4240 /* Use Y gamma control instead. Bit 0 enables it. */
4241 i2c_w(sd, 0x64, ctab[val >> 4]);
4242 break;
4243 }
6a7eba24
JFM		 4244 case SEN_OV7670:
4245 /* check that this isn't just the same as ov7610 */
4246 i2c_w(sd, OV7670_REG_CONTRAS, val >> 1);
4247 break;
4248 }
6a7eba24
JFM		 4249}
4250
4251static void setcolors(struct gspca_dev *gspca_dev)
4252{
4253 struct sd *sd = (struct sd *) gspca_dev;
4254 int val;
6a7eba24
JFM		 4255
4256 val = sd->colors;
6a7eba24
JFM		 4257 switch (sd->sensor) {
4258 case SEN_OV8610:
4259 case SEN_OV7610:
4260 case SEN_OV76BE:
4261 case SEN_OV6620:
4262 case SEN_OV6630:
7d971373 4263 case SEN_OV66308AF:
6a7eba24
JFM		 4264 i2c_w(sd, OV7610_REG_SAT, val);
4265 break;
4266 case SEN_OV7620:
859cc470 4267 case SEN_OV7620AE:
6a7eba24
JFM		 4268 /* Use UV gamma control instead. Bits 0 & 7 are reserved. */
4269/* rc = ov_i2c_write(sd->dev, 0x62, (val >> 9) & 0x7e);
4270 if (rc < 0)
4271 goto out; */
4272 i2c_w(sd, OV7610_REG_SAT, val);
4273 break;
4274 case SEN_OV7640:
035d3a3d 4275 case SEN_OV7648:
6a7eba24
JFM		 4276 i2c_w(sd, OV7610_REG_SAT, val & 0xf0);
4277 break;
4278 case SEN_OV7670:
4279 /* supported later once I work out how to do it
4280 * transparently fail now! */
4281 /* set REG_COM13 values for UV sat auto mode */
4282 break;
4283 }
6a7eba24
JFM		 4284}
4285
02ab18b0
HG		 4286static void setautobrightness(struct sd *sd)
4287{
035d3a3d
HG		 4288 if (sd->sensor == SEN_OV7640 || sd->sensor == SEN_OV7648 ||
4289 sd->sensor == SEN_OV7670 ||
635118d5 4290 sd->sensor == SEN_OV2610 || sd->sensor == SEN_OV3610)
02ab18b0
HG		 4291 return;
4292
4293 i2c_w_mask(sd, 0x2d, sd->autobrightness ? 0x10 : 0x00, 0x10);
4294}
4295
4296static void setfreq(struct sd *sd)
4297{
635118d5
HG		 4298 if (sd->sensor == SEN_OV2610 || sd->sensor == SEN_OV3610)
4299 return;
4300
02ab18b0
HG		 4301 if (sd->sensor == SEN_OV7670) {
4302 switch (sd->freq) {
4303 case 0: /* Banding filter disabled */
4304 i2c_w_mask(sd, OV7670_REG_COM8, 0, OV7670_COM8_BFILT);
4305 break;
4306 case 1: /* 50 hz */
4307 i2c_w_mask(sd, OV7670_REG_COM8, OV7670_COM8_BFILT,
4308 OV7670_COM8_BFILT);
4309 i2c_w_mask(sd, OV7670_REG_COM11, 0x08, 0x18);
4310 break;
4311 case 2: /* 60 hz */
4312 i2c_w_mask(sd, OV7670_REG_COM8, OV7670_COM8_BFILT,
4313 OV7670_COM8_BFILT);
4314 i2c_w_mask(sd, OV7670_REG_COM11, 0x00, 0x18);
4315 break;
4316 case 3: /* Auto hz */
4317 i2c_w_mask(sd, OV7670_REG_COM8, OV7670_COM8_BFILT,
4318 OV7670_COM8_BFILT);
4319 i2c_w_mask(sd, OV7670_REG_COM11, OV7670_COM11_HZAUTO,
4320 0x18);
4321 break;
4322 }
4323 } else {
4324 switch (sd->freq) {
4325 case 0: /* Banding filter disabled */
4326 i2c_w_mask(sd, 0x2d, 0x00, 0x04);
4327 i2c_w_mask(sd, 0x2a, 0x00, 0x80);
4328 break;
4329 case 1: /* 50 hz (filter on and framerate adj) */
4330 i2c_w_mask(sd, 0x2d, 0x04, 0x04);
4331 i2c_w_mask(sd, 0x2a, 0x80, 0x80);
4332 /* 20 fps -> 16.667 fps */
4333 if (sd->sensor == SEN_OV6620 ||
7d971373
HG		 4334 sd->sensor == SEN_OV6630 ||
4335 sd->sensor == SEN_OV66308AF)
02ab18b0
HG		 4336 i2c_w(sd, 0x2b, 0x5e);
4337 else
4338 i2c_w(sd, 0x2b, 0xac);
4339 break;
4340 case 2: /* 60 hz (filter on, ...) */
4341 i2c_w_mask(sd, 0x2d, 0x04, 0x04);
4342 if (sd->sensor == SEN_OV6620 ||
7d971373
HG		 4343 sd->sensor == SEN_OV6630 ||
4344 sd->sensor == SEN_OV66308AF) {
02ab18b0
HG		 4345 /* 20 fps -> 15 fps */
4346 i2c_w_mask(sd, 0x2a, 0x80, 0x80);
4347 i2c_w(sd, 0x2b, 0xa8);
4348 } else {
4349 /* no framerate adj. */
4350 i2c_w_mask(sd, 0x2a, 0x00, 0x80);
4351 }
4352 break;
4353 }
4354 }
4355}
4356
6a7eba24
JFM		 4357static int sd_setbrightness(struct gspca_dev *gspca_dev, __s32 val)
4358{
4359 struct sd *sd = (struct sd *) gspca_dev;
4360
4361 sd->brightness = val;
ac40b1fa
JFM		 4362 if (gspca_dev->streaming)
4363 setbrightness(gspca_dev);
6a7eba24
JFM		 4364 return 0;
4365}
4366
4367static int sd_getbrightness(struct gspca_dev *gspca_dev, __s32 *val)
4368{
4369 struct sd *sd = (struct sd *) gspca_dev;
4370
4371 *val = sd->brightness;
4372 return 0;
4373}
4374
4375static int sd_setcontrast(struct gspca_dev *gspca_dev, __s32 val)
4376{
4377 struct sd *sd = (struct sd *) gspca_dev;
4378
4379 sd->contrast = val;
ac40b1fa
JFM		 4380 if (gspca_dev->streaming)
4381 setcontrast(gspca_dev);
6a7eba24
JFM		 4382 return 0;
4383}
4384
4385static int sd_getcontrast(struct gspca_dev *gspca_dev, __s32 *val)
4386{
4387 struct sd *sd = (struct sd *) gspca_dev;
4388
4389 *val = sd->contrast;
4390 return 0;
4391}
4392
4393static int sd_setcolors(struct gspca_dev *gspca_dev, __s32 val)
4394{
4395 struct sd *sd = (struct sd *) gspca_dev;
4396
4397 sd->colors = val;
ac40b1fa
JFM		 4398 if (gspca_dev->streaming)
4399 setcolors(gspca_dev);
6a7eba24
JFM		 4400 return 0;
4401}
4402
4403static int sd_getcolors(struct gspca_dev *gspca_dev, __s32 *val)
4404{
4405 struct sd *sd = (struct sd *) gspca_dev;
4406
4407 *val = sd->colors;
4408 return 0;
4409}
4410
0cd6759d
JFM		 4411static int sd_sethflip(struct gspca_dev *gspca_dev, __s32 val)
4412{
4413 struct sd *sd = (struct sd *) gspca_dev;
4414
4415 sd->hflip = val;
ac40b1fa
JFM		 4416 if (gspca_dev->streaming)
4417 sethvflip(sd);
0cd6759d
JFM		 4418 return 0;
4419}
4420
4421static int sd_gethflip(struct gspca_dev *gspca_dev, __s32 *val)
4422{
4423 struct sd *sd = (struct sd *) gspca_dev;
4424
4425 *val = sd->hflip;
4426 return 0;
4427}
4428
4429static int sd_setvflip(struct gspca_dev *gspca_dev, __s32 val)
4430{
4431 struct sd *sd = (struct sd *) gspca_dev;
4432
4433 sd->vflip = val;
ac40b1fa
JFM		 4434 if (gspca_dev->streaming)
4435 sethvflip(sd);
0cd6759d
JFM		 4436 return 0;
4437}
4438
4439static int sd_getvflip(struct gspca_dev *gspca_dev, __s32 *val)
4440{
4441 struct sd *sd = (struct sd *) gspca_dev;
4442
4443 *val = sd->vflip;
4444 return 0;
4445}
4446
02ab18b0
HG		 4447static int sd_setautobrightness(struct gspca_dev *gspca_dev, __s32 val)
4448{
4449 struct sd *sd = (struct sd *) gspca_dev;
4450
4451 sd->autobrightness = val;
4452 if (gspca_dev->streaming)
4453 setautobrightness(sd);
4454 return 0;
4455}
4456
4457static int sd_getautobrightness(struct gspca_dev *gspca_dev, __s32 *val)
4458{
4459 struct sd *sd = (struct sd *) gspca_dev;
4460
4461 *val = sd->autobrightness;
4462 return 0;
4463}
4464
4465static int sd_setfreq(struct gspca_dev *gspca_dev, __s32 val)
4466{
4467 struct sd *sd = (struct sd *) gspca_dev;
4468
4469 sd->freq = val;
a511ba94 4470 if (gspca_dev->streaming) {
02ab18b0 4471 setfreq(sd);
a511ba94
HG		 4472 /* Ugly but necessary */
4473 if (sd->bridge == BRIDGE_W9968CF)
4474 w9968cf_set_crop_window(sd);
4475 }
02ab18b0
HG		 4476 return 0;
4477}
4478
4479static int sd_getfreq(struct gspca_dev *gspca_dev, __s32 *val)
4480{
4481 struct sd *sd = (struct sd *) gspca_dev;
4482
4483 *val = sd->freq;
4484 return 0;
4485}
4486
4487static int sd_querymenu(struct gspca_dev *gspca_dev,
4488 struct v4l2_querymenu *menu)
4489{
4490 struct sd *sd = (struct sd *) gspca_dev;
4491
4492 switch (menu->id) {
4493 case V4L2_CID_POWER_LINE_FREQUENCY:
4494 switch (menu->index) {
4495 case 0: /* V4L2_CID_POWER_LINE_FREQUENCY_DISABLED */
4496 strcpy((char *) menu->name, "NoFliker");
4497 return 0;
4498 case 1: /* V4L2_CID_POWER_LINE_FREQUENCY_50HZ */
4499 strcpy((char *) menu->name, "50 Hz");
4500 return 0;
4501 case 2: /* V4L2_CID_POWER_LINE_FREQUENCY_60HZ */
4502 strcpy((char *) menu->name, "60 Hz");
4503 return 0;
4504 case 3:
4505 if (sd->sensor != SEN_OV7670)
4506 return -EINVAL;
4507
4508 strcpy((char *) menu->name, "Automatic");
4509 return 0;
4510 }
4511 break;
4512 }
4513 return -EINVAL;
4514}
4515
79b35902
HG		 4516static int sd_get_jcomp(struct gspca_dev *gspca_dev,
4517 struct v4l2_jpegcompression *jcomp)
4518{
4519 struct sd *sd = (struct sd *) gspca_dev;
4520
4521 if (sd->bridge != BRIDGE_W9968CF)
4522 return -EINVAL;
4523
4524 memset(jcomp, 0, sizeof *jcomp);
4525 jcomp->quality = sd->quality;
4526 jcomp->jpeg_markers = V4L2_JPEG_MARKER_DHT | V4L2_JPEG_MARKER_DQT |
4527 V4L2_JPEG_MARKER_DRI;
4528 return 0;
4529}
4530
4531static int sd_set_jcomp(struct gspca_dev *gspca_dev,
4532 struct v4l2_jpegcompression *jcomp)
4533{
4534 struct sd *sd = (struct sd *) gspca_dev;
4535
4536 if (sd->bridge != BRIDGE_W9968CF)
4537 return -EINVAL;
4538
4539 if (gspca_dev->streaming)
4540 return -EBUSY;
4541
4542 if (jcomp->quality < QUALITY_MIN)
4543 sd->quality = QUALITY_MIN;
4544 else if (jcomp->quality > QUALITY_MAX)
4545 sd->quality = QUALITY_MAX;
4546 else
4547 sd->quality = jcomp->quality;
4548
4549 /* Return resulting jcomp params to app */
4550 sd_get_jcomp(gspca_dev, jcomp);
4551
4552 return 0;
4553}
4554
6a7eba24 4555/* sub-driver description */
a5ae2062 4556static const struct sd_desc sd_desc = {
6a7eba24
JFM		 4557 .name = MODULE_NAME,
4558 .ctrls = sd_ctrls,
4559 .nctrls = ARRAY_SIZE(sd_ctrls),
4560 .config = sd_config,
012d6b02 4561 .init = sd_init,
6a7eba24
JFM		 4562 .start = sd_start,
4563 .stopN = sd_stopN,
79b35902 4564 .stop0 = sd_stop0,
6a7eba24 4565 .pkt_scan = sd_pkt_scan,
417a4d26 4566 .dq_callback = sd_reset_snapshot,
02ab18b0 4567 .querymenu = sd_querymenu,
79b35902
HG		 4568 .get_jcomp = sd_get_jcomp,
4569 .set_jcomp = sd_set_jcomp,
417a4d26
HG		 4570#ifdef CONFIG_INPUT
4571 .other_input = 1,
4572#endif
6a7eba24
JFM		 4573};
4574
4575/* -- module initialisation -- */
a5ae2062 4576static const __devinitdata struct usb_device_id device_table[] = {
a511ba94 4577 {USB_DEVICE(0x041e, 0x4003), .driver_info = BRIDGE_W9968CF },
49809d6a
HG		 4578 {USB_DEVICE(0x041e, 0x4052), .driver_info = BRIDGE_OV519 },
4579 {USB_DEVICE(0x041e, 0x405f), .driver_info = BRIDGE_OV519 },
4580 {USB_DEVICE(0x041e, 0x4060), .driver_info = BRIDGE_OV519 },
4581 {USB_DEVICE(0x041e, 0x4061), .driver_info = BRIDGE_OV519 },
9e4d8258
HG		 4582 {USB_DEVICE(0x041e, 0x4064),
4583 .driver_info = BRIDGE_OV519 | BRIDGE_INVERT_LED },
518c8df7 4584 {USB_DEVICE(0x041e, 0x4067), .driver_info = BRIDGE_OV519 },
9e4d8258
HG		 4585 {USB_DEVICE(0x041e, 0x4068),
4586 .driver_info = BRIDGE_OV519 | BRIDGE_INVERT_LED },
49809d6a
HG		 4587 {USB_DEVICE(0x045e, 0x028c), .driver_info = BRIDGE_OV519 },
4588 {USB_DEVICE(0x054c, 0x0154), .driver_info = BRIDGE_OV519 },
98184f78
HG		 4589 {USB_DEVICE(0x054c, 0x0155),
4590 .driver_info = BRIDGE_OV519 | BRIDGE_INVERT_LED },
1876bb92 4591 {USB_DEVICE(0x05a9, 0x0511), .driver_info = BRIDGE_OV511 },
49809d6a
HG		 4592 {USB_DEVICE(0x05a9, 0x0518), .driver_info = BRIDGE_OV518 },
4593 {USB_DEVICE(0x05a9, 0x0519), .driver_info = BRIDGE_OV519 },
4594 {USB_DEVICE(0x05a9, 0x0530), .driver_info = BRIDGE_OV519 },
b46aaa02 4595 {USB_DEVICE(0x05a9, 0x2800), .driver_info = BRIDGE_OVFX2 },
49809d6a
HG		 4596 {USB_DEVICE(0x05a9, 0x4519), .driver_info = BRIDGE_OV519 },
4597 {USB_DEVICE(0x05a9, 0x8519), .driver_info = BRIDGE_OV519 },
1876bb92 4598 {USB_DEVICE(0x05a9, 0xa511), .driver_info = BRIDGE_OV511PLUS },
49809d6a 4599 {USB_DEVICE(0x05a9, 0xa518), .driver_info = BRIDGE_OV518PLUS },
1876bb92 4600 {USB_DEVICE(0x0813, 0x0002), .driver_info = BRIDGE_OV511PLUS },
b46aaa02
HG		 4601 {USB_DEVICE(0x0b62, 0x0059), .driver_info = BRIDGE_OVFX2 },
4602 {USB_DEVICE(0x0e96, 0xc001), .driver_info = BRIDGE_OVFX2 },
a511ba94 4603 {USB_DEVICE(0x1046, 0x9967), .driver_info = BRIDGE_W9968CF },
b46aaa02 4604 {USB_DEVICE(0x8020, 0xEF04), .driver_info = BRIDGE_OVFX2 },
6a7eba24
JFM		 4605 {}
4606};
ac40b1fa 4607
6a7eba24
JFM		 4608MODULE_DEVICE_TABLE(usb, device_table);
4609
4610/* -- device connect -- */
4611static int sd_probe(struct usb_interface *intf,
4612 const struct usb_device_id *id)
4613{
4614 return gspca_dev_probe(intf, id, &sd_desc, sizeof(struct sd),
4615 THIS_MODULE);
4616}
4617
4618static struct usb_driver sd_driver = {
4619 .name = MODULE_NAME,
4620 .id_table = device_table,
4621 .probe = sd_probe,
4622 .disconnect = gspca_disconnect,
6a709749
JFM		 4623#ifdef CONFIG_PM
4624 .suspend = gspca_suspend,
4625 .resume = gspca_resume,
4626#endif
6a7eba24
JFM		 4627};
4628
4629/* -- module insert / remove -- */
4630static int __init sd_mod_init(void)
4631{
f69e9529
AK		 4632 int ret;
4633 ret = usb_register(&sd_driver);
4634 if (ret < 0)
e6b14849 4635 return ret;
10b0e96e 4636 PDEBUG(D_PROBE, "registered");
6a7eba24
JFM		 4637 return 0;
4638}
4639static void __exit sd_mod_exit(void)
4640{
4641 usb_deregister(&sd_driver);
4642 PDEBUG(D_PROBE, "deregistered");
4643}
4644
4645module_init(sd_mod_init);
4646module_exit(sd_mod_exit);
4647
4648module_param(frame_rate, int, 0644);
4649MODULE_PARM_DESC(frame_rate, "Frame rate (5, 10, 15, 20 or 30 fps)");
Ubuntu Artful kernel mirror