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V4L/DVB: gspca_main: Fix a compile error when CONFIG_INPUT is not set
[mirror_ubuntu-artful-kernel.git] / drivers / media / video / gspca / ov519.c
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6a7eba24
JFM		 1/**
2 * OV519 driver
3 *
4 * Copyright (C) 2008 Jean-Francois Moine (http://moinejf.free.fr)
b46aaa02 5 * Copyright (C) 2009 Hans de Goede <hdegoede@redhat.com>
6a7eba24 6 *
2961e875
RB		 7 * This module is adapted from the ov51x-jpeg package, which itself
8 * was adapted from the ov511 driver.
9 *
10 * Original copyright for the ov511 driver is:
11 *
b46aaa02 12 * Copyright (c) 1999-2006 Mark W. McClelland
2961e875 13 * Support for OV519, OV8610 Copyright (c) 2003 Joerg Heckenbach
b46aaa02
HG		 14 * Many improvements by Bret Wallach <bwallac1@san.rr.com>
15 * Color fixes by by Orion Sky Lawlor <olawlor@acm.org> (2/26/2000)
16 * OV7620 fixes by Charl P. Botha <cpbotha@ieee.org>
17 * Changes by Claudio Matsuoka <claudio@conectiva.com>
2961e875
RB		 18 *
19 * ov51x-jpeg original copyright is:
20 *
21 * Copyright (c) 2004-2007 Romain Beauxis <toots@rastageeks.org>
22 * Support for OV7670 sensors was contributed by Sam Skipsey <aoanla@yahoo.com>
6a7eba24
JFM		 23 *
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License as published by
26 * the Free Software Foundation; either version 2 of the License, or
27 * any later version.
28 *
29 * This program is distributed in the hope that it will be useful,
30 * but WITHOUT ANY WARRANTY; without even the implied warranty of
31 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
32 * GNU General Public License for more details.
33 *
34 * You should have received a copy of the GNU General Public License
35 * along with this program; if not, write to the Free Software
36 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
37 *
38 */
39#define MODULE_NAME "ov519"
40
41#include "gspca.h"
42
6a7eba24
JFM		 43MODULE_AUTHOR("Jean-Francois Moine <http://moinejf.free.fr>");
44MODULE_DESCRIPTION("OV519 USB Camera Driver");
45MODULE_LICENSE("GPL");
46
47/* global parameters */
48static int frame_rate;
49
50/* Number of times to retry a failed I2C transaction. Increase this if you
51 * are getting "Failed to read sensor ID..." */
52static int i2c_detect_tries = 10;
53
54/* ov519 device descriptor */
55struct sd {
56 struct gspca_dev gspca_dev; /* !! must be the first item */
57
92918a53
HG		 58 __u8 packet_nr;
59
49809d6a
HG		 60 char bridge;
61#define BRIDGE_OV511 0
62#define BRIDGE_OV511PLUS 1
63#define BRIDGE_OV518 2
64#define BRIDGE_OV518PLUS 3
65#define BRIDGE_OV519 4
635118d5 66#define BRIDGE_OVFX2 5
a511ba94 67#define BRIDGE_W9968CF 6
9e4d8258
HG		 68#define BRIDGE_MASK 7
69
70 char invert_led;
71#define BRIDGE_INVERT_LED 8
49809d6a 72
6a7eba24 73 /* Determined by sensor type */
ac40b1fa 74 __u8 sif;
6a7eba24 75
ac40b1fa
JFM		 76 __u8 brightness;
77 __u8 contrast;
78 __u8 colors;
0cd6759d
JFM		 79 __u8 hflip;
80 __u8 vflip;
02ab18b0
HG		 81 __u8 autobrightness;
82 __u8 freq;
79b35902
HG		 83 __u8 quality;
84#define QUALITY_MIN 50
85#define QUALITY_MAX 70
86#define QUALITY_DEF 50
6a7eba24 87
ac40b1fa 88 __u8 stopped; /* Streaming is temporarily paused */
6a7eba24 89
1876bb92
HG		 90 __u8 frame_rate; /* current Framerate */
91 __u8 clockdiv; /* clockdiv override */
6a7eba24
JFM		 92
93 char sensor; /* Type of image sensor chip (SEN_*) */
94#define SEN_UNKNOWN 0
635118d5
HG		 95#define SEN_OV2610 1
96#define SEN_OV3610 2
97#define SEN_OV6620 3
98#define SEN_OV6630 4
99#define SEN_OV66308AF 5
100#define SEN_OV7610 6
101#define SEN_OV7620 7
859cc470
HG		 102#define SEN_OV7620AE 8
103#define SEN_OV7640 9
035d3a3d
HG		 104#define SEN_OV7648 10
105#define SEN_OV7670 11
106#define SEN_OV76BE 12
107#define SEN_OV8610 13
a511ba94
HG		 108
109 u8 sensor_addr;
110 int sensor_width;
111 int sensor_height;
fb1f9020 112 int sensor_reg_cache[256];
79b35902
HG		 113
114 u8 *jpeg_hdr;
6a7eba24
JFM		 115};
116
a511ba94
HG		 117/* Note this is a bit of a hack, but the w9968cf driver needs the code for all
118 the ov sensors which is already present here. When we have the time we
119 really should move the sensor drivers to v4l2 sub drivers. */
120#include "w996Xcf.c"
121
6a7eba24
JFM		 122/* V4L2 controls supported by the driver */
123static int sd_setbrightness(struct gspca_dev *gspca_dev, __s32 val);
124static int sd_getbrightness(struct gspca_dev *gspca_dev, __s32 *val);
125static int sd_setcontrast(struct gspca_dev *gspca_dev, __s32 val);
126static int sd_getcontrast(struct gspca_dev *gspca_dev, __s32 *val);
127static int sd_setcolors(struct gspca_dev *gspca_dev, __s32 val);
128static int sd_getcolors(struct gspca_dev *gspca_dev, __s32 *val);
0cd6759d
JFM		 129static int sd_sethflip(struct gspca_dev *gspca_dev, __s32 val);
130static int sd_gethflip(struct gspca_dev *gspca_dev, __s32 *val);
131static int sd_setvflip(struct gspca_dev *gspca_dev, __s32 val);
132static int sd_getvflip(struct gspca_dev *gspca_dev, __s32 *val);
02ab18b0
HG		 133static int sd_setautobrightness(struct gspca_dev *gspca_dev, __s32 val);
134static int sd_getautobrightness(struct gspca_dev *gspca_dev, __s32 *val);
135static int sd_setfreq(struct gspca_dev *gspca_dev, __s32 val);
136static int sd_getfreq(struct gspca_dev *gspca_dev, __s32 *val);
49809d6a
HG		 137static void setbrightness(struct gspca_dev *gspca_dev);
138static void setcontrast(struct gspca_dev *gspca_dev);
139static void setcolors(struct gspca_dev *gspca_dev);
02ab18b0
HG		 140static void setautobrightness(struct sd *sd);
141static void setfreq(struct sd *sd);
6a7eba24 142
02ab18b0 143static const struct ctrl sd_ctrls[] = {
d02134dd 144#define BRIGHTNESS_IDX 0
6a7eba24
JFM		 145 {
146 {
147 .id = V4L2_CID_BRIGHTNESS,
148 .type = V4L2_CTRL_TYPE_INTEGER,
149 .name = "Brightness",
150 .minimum = 0,
151 .maximum = 255,
152 .step = 1,
594f5b8b
JFM		 153#define BRIGHTNESS_DEF 127
154 .default_value = BRIGHTNESS_DEF,
6a7eba24
JFM		 155 },
156 .set = sd_setbrightness,
157 .get = sd_getbrightness,
158 },
d02134dd 159#define CONTRAST_IDX 1
6a7eba24
JFM		 160 {
161 {
162 .id = V4L2_CID_CONTRAST,
163 .type = V4L2_CTRL_TYPE_INTEGER,
164 .name = "Contrast",
165 .minimum = 0,
166 .maximum = 255,
167 .step = 1,
594f5b8b
JFM		 168#define CONTRAST_DEF 127
169 .default_value = CONTRAST_DEF,
6a7eba24
JFM		 170 },
171 .set = sd_setcontrast,
172 .get = sd_getcontrast,
173 },
d02134dd 174#define COLOR_IDX 2
6a7eba24
JFM		 175 {
176 {
177 .id = V4L2_CID_SATURATION,
178 .type = V4L2_CTRL_TYPE_INTEGER,
594f5b8b 179 .name = "Color",
6a7eba24
JFM		 180 .minimum = 0,
181 .maximum = 255,
182 .step = 1,
594f5b8b
JFM		 183#define COLOR_DEF 127
184 .default_value = COLOR_DEF,
6a7eba24
JFM		 185 },
186 .set = sd_setcolors,
187 .get = sd_getcolors,
188 },
02ab18b0 189/* The flip controls work with ov7670 only */
de00448f 190#define HFLIP_IDX 3
0cd6759d
JFM		 191 {
192 {
193 .id = V4L2_CID_HFLIP,
194 .type = V4L2_CTRL_TYPE_BOOLEAN,
195 .name = "Mirror",
196 .minimum = 0,
197 .maximum = 1,
198 .step = 1,
199#define HFLIP_DEF 0
200 .default_value = HFLIP_DEF,
201 },
202 .set = sd_sethflip,
203 .get = sd_gethflip,
204 },
de00448f 205#define VFLIP_IDX 4
0cd6759d
JFM		 206 {
207 {
208 .id = V4L2_CID_VFLIP,
209 .type = V4L2_CTRL_TYPE_BOOLEAN,
210 .name = "Vflip",
211 .minimum = 0,
212 .maximum = 1,
213 .step = 1,
214#define VFLIP_DEF 0
215 .default_value = VFLIP_DEF,
216 },
217 .set = sd_setvflip,
218 .get = sd_getvflip,
219 },
02ab18b0
HG		 220#define AUTOBRIGHT_IDX 5
221 {
222 {
223 .id = V4L2_CID_AUTOBRIGHTNESS,
224 .type = V4L2_CTRL_TYPE_BOOLEAN,
225 .name = "Auto Brightness",
226 .minimum = 0,
227 .maximum = 1,
228 .step = 1,
229#define AUTOBRIGHT_DEF 1
230 .default_value = AUTOBRIGHT_DEF,
231 },
232 .set = sd_setautobrightness,
233 .get = sd_getautobrightness,
234 },
235#define FREQ_IDX 6
236 {
237 {
238 .id = V4L2_CID_POWER_LINE_FREQUENCY,
239 .type = V4L2_CTRL_TYPE_MENU,
240 .name = "Light frequency filter",
241 .minimum = 0,
242 .maximum = 2, /* 0: 0, 1: 50Hz, 2:60Hz */
243 .step = 1,
244#define FREQ_DEF 0
245 .default_value = FREQ_DEF,
246 },
247 .set = sd_setfreq,
248 .get = sd_getfreq,
249 },
250#define OV7670_FREQ_IDX 7
251 {
252 {
253 .id = V4L2_CID_POWER_LINE_FREQUENCY,
254 .type = V4L2_CTRL_TYPE_MENU,
255 .name = "Light frequency filter",
256 .minimum = 0,
257 .maximum = 3, /* 0: 0, 1: 50Hz, 2:60Hz 3: Auto Hz */
258 .step = 1,
259#define OV7670_FREQ_DEF 3
260 .default_value = OV7670_FREQ_DEF,
261 },
262 .set = sd_setfreq,
263 .get = sd_getfreq,
264 },
6a7eba24
JFM		 265};
266
49809d6a 267static const struct v4l2_pix_format ov519_vga_mode[] = {
c2446b3e
JFM		 268 {320, 240, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
269 .bytesperline = 320,
594f5b8b 270 .sizeimage = 320 * 240 * 3 / 8 + 590,
c2446b3e
JFM		 271 .colorspace = V4L2_COLORSPACE_JPEG,
272 .priv = 1},
273 {640, 480, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
274 .bytesperline = 640,
275 .sizeimage = 640 * 480 * 3 / 8 + 590,
276 .colorspace = V4L2_COLORSPACE_JPEG,
277 .priv = 0},
6a7eba24 278};
49809d6a 279static const struct v4l2_pix_format ov519_sif_mode[] = {
124cc9c0
HG		 280 {160, 120, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
281 .bytesperline = 160,
282 .sizeimage = 160 * 120 * 3 / 8 + 590,
283 .colorspace = V4L2_COLORSPACE_JPEG,
284 .priv = 3},
c2446b3e
JFM		 285 {176, 144, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
286 .bytesperline = 176,
594f5b8b 287 .sizeimage = 176 * 144 * 3 / 8 + 590,
c2446b3e
JFM		 288 .colorspace = V4L2_COLORSPACE_JPEG,
289 .priv = 1},
124cc9c0
HG		 290 {320, 240, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
291 .bytesperline = 320,
292 .sizeimage = 320 * 240 * 3 / 8 + 590,
293 .colorspace = V4L2_COLORSPACE_JPEG,
294 .priv = 2},
c2446b3e
JFM		 295 {352, 288, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
296 .bytesperline = 352,
594f5b8b 297 .sizeimage = 352 * 288 * 3 / 8 + 590,
c2446b3e
JFM		 298 .colorspace = V4L2_COLORSPACE_JPEG,
299 .priv = 0},
6a7eba24
JFM		 300};
301
b282d873
HG		 302/* Note some of the sizeimage values for the ov511 / ov518 may seem
303 larger then necessary, however they need to be this big as the ov511 /
304 ov518 always fills the entire isoc frame, using 0 padding bytes when
305 it doesn't have any data. So with low framerates the amount of data
306 transfered can become quite large (libv4l will remove all the 0 padding
307 in userspace). */
49809d6a
HG		 308static const struct v4l2_pix_format ov518_vga_mode[] = {
309 {320, 240, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
310 .bytesperline = 320,
b282d873 311 .sizeimage = 320 * 240 * 3,
49809d6a
HG		 312 .colorspace = V4L2_COLORSPACE_JPEG,
313 .priv = 1},
314 {640, 480, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
315 .bytesperline = 640,
b282d873 316 .sizeimage = 640 * 480 * 2,
49809d6a
HG		 317 .colorspace = V4L2_COLORSPACE_JPEG,
318 .priv = 0},
319};
320static const struct v4l2_pix_format ov518_sif_mode[] = {
124cc9c0
HG		 321 {160, 120, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
322 .bytesperline = 160,
b282d873 323 .sizeimage = 70000,
124cc9c0
HG		 324 .colorspace = V4L2_COLORSPACE_JPEG,
325 .priv = 3},
49809d6a
HG		 326 {176, 144, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
327 .bytesperline = 176,
b282d873 328 .sizeimage = 70000,
49809d6a
HG		 329 .colorspace = V4L2_COLORSPACE_JPEG,
330 .priv = 1},
124cc9c0
HG		 331 {320, 240, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
332 .bytesperline = 320,
b282d873 333 .sizeimage = 320 * 240 * 3,
124cc9c0
HG		 334 .colorspace = V4L2_COLORSPACE_JPEG,
335 .priv = 2},
49809d6a
HG		 336 {352, 288, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
337 .bytesperline = 352,
b282d873 338 .sizeimage = 352 * 288 * 3,
49809d6a
HG		 339 .colorspace = V4L2_COLORSPACE_JPEG,
340 .priv = 0},
341};
342
1876bb92
HG		 343static const struct v4l2_pix_format ov511_vga_mode[] = {
344 {320, 240, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
345 .bytesperline = 320,
346 .sizeimage = 320 * 240 * 3,
347 .colorspace = V4L2_COLORSPACE_JPEG,
348 .priv = 1},
349 {640, 480, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
350 .bytesperline = 640,
351 .sizeimage = 640 * 480 * 2,
352 .colorspace = V4L2_COLORSPACE_JPEG,
353 .priv = 0},
354};
355static const struct v4l2_pix_format ov511_sif_mode[] = {
356 {160, 120, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
357 .bytesperline = 160,
b282d873 358 .sizeimage = 70000,
1876bb92
HG		 359 .colorspace = V4L2_COLORSPACE_JPEG,
360 .priv = 3},
361 {176, 144, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
362 .bytesperline = 176,
b282d873 363 .sizeimage = 70000,
1876bb92
HG		 364 .colorspace = V4L2_COLORSPACE_JPEG,
365 .priv = 1},
366 {320, 240, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
367 .bytesperline = 320,
368 .sizeimage = 320 * 240 * 3,
369 .colorspace = V4L2_COLORSPACE_JPEG,
370 .priv = 2},
371 {352, 288, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
372 .bytesperline = 352,
373 .sizeimage = 352 * 288 * 3,
374 .colorspace = V4L2_COLORSPACE_JPEG,
375 .priv = 0},
376};
49809d6a 377
635118d5
HG		 378static const struct v4l2_pix_format ovfx2_vga_mode[] = {
379 {320, 240, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
380 .bytesperline = 320,
381 .sizeimage = 320 * 240,
382 .colorspace = V4L2_COLORSPACE_SRGB,
383 .priv = 1},
384 {640, 480, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
385 .bytesperline = 640,
386 .sizeimage = 640 * 480,
387 .colorspace = V4L2_COLORSPACE_SRGB,
388 .priv = 0},
389};
390static const struct v4l2_pix_format ovfx2_cif_mode[] = {
391 {160, 120, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
392 .bytesperline = 160,
393 .sizeimage = 160 * 120,
394 .colorspace = V4L2_COLORSPACE_SRGB,
395 .priv = 3},
396 {176, 144, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
397 .bytesperline = 176,
398 .sizeimage = 176 * 144,
399 .colorspace = V4L2_COLORSPACE_SRGB,
400 .priv = 1},
401 {320, 240, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
402 .bytesperline = 320,
403 .sizeimage = 320 * 240,
404 .colorspace = V4L2_COLORSPACE_SRGB,
405 .priv = 2},
406 {352, 288, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
407 .bytesperline = 352,
408 .sizeimage = 352 * 288,
409 .colorspace = V4L2_COLORSPACE_SRGB,
410 .priv = 0},
411};
412static const struct v4l2_pix_format ovfx2_ov2610_mode[] = {
413 {1600, 1200, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
414 .bytesperline = 1600,
415 .sizeimage = 1600 * 1200,
416 .colorspace = V4L2_COLORSPACE_SRGB},
417};
418static const struct v4l2_pix_format ovfx2_ov3610_mode[] = {
635118d5
HG		 419 {640, 480, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
420 .bytesperline = 640,
421 .sizeimage = 640 * 480,
b46aaa02
HG		 422 .colorspace = V4L2_COLORSPACE_SRGB,
423 .priv = 1},
424 {800, 600, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
425 .bytesperline = 800,
426 .sizeimage = 800 * 600,
427 .colorspace = V4L2_COLORSPACE_SRGB,
428 .priv = 1},
429 {1024, 768, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
430 .bytesperline = 1024,
431 .sizeimage = 1024 * 768,
432 .colorspace = V4L2_COLORSPACE_SRGB,
433 .priv = 1},
434 {1600, 1200, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
435 .bytesperline = 1600,
436 .sizeimage = 1600 * 1200,
437 .colorspace = V4L2_COLORSPACE_SRGB,
438 .priv = 0},
439 {2048, 1536, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
440 .bytesperline = 2048,
441 .sizeimage = 2048 * 1536,
442 .colorspace = V4L2_COLORSPACE_SRGB,
443 .priv = 0},
635118d5
HG		 444};
445
446
49809d6a 447/* Registers common to OV511 / OV518 */
1876bb92 448#define R51x_FIFO_PSIZE 0x30 /* 2 bytes wide w/ OV518(+) */
49809d6a 449#define R51x_SYS_RESET 0x50
1876bb92
HG		 450 /* Reset type flags */
451 #define OV511_RESET_OMNICE 0x08
49809d6a
HG		 452#define R51x_SYS_INIT 0x53
453#define R51x_SYS_SNAP 0x52
454#define R51x_SYS_CUST_ID 0x5F
455#define R51x_COMP_LUT_BEGIN 0x80
456
457/* OV511 Camera interface register numbers */
1876bb92
HG		 458#define R511_CAM_DELAY 0x10
459#define R511_CAM_EDGE 0x11
460#define R511_CAM_PXCNT 0x12
461#define R511_CAM_LNCNT 0x13
462#define R511_CAM_PXDIV 0x14
463#define R511_CAM_LNDIV 0x15
464#define R511_CAM_UV_EN 0x16
465#define R511_CAM_LINE_MODE 0x17
466#define R511_CAM_OPTS 0x18
467
468#define R511_SNAP_FRAME 0x19
469#define R511_SNAP_PXCNT 0x1A
470#define R511_SNAP_LNCNT 0x1B
471#define R511_SNAP_PXDIV 0x1C
472#define R511_SNAP_LNDIV 0x1D
473#define R511_SNAP_UV_EN 0x1E
474#define R511_SNAP_UV_EN 0x1E
475#define R511_SNAP_OPTS 0x1F
476
477#define R511_DRAM_FLOW_CTL 0x20
478#define R511_FIFO_OPTS 0x31
479#define R511_I2C_CTL 0x40
49809d6a 480#define R511_SYS_LED_CTL 0x55 /* OV511+ only */
1876bb92
HG		 481#define R511_COMP_EN 0x78
482#define R511_COMP_LUT_EN 0x79
49809d6a
HG		 483
484/* OV518 Camera interface register numbers */
485#define R518_GPIO_OUT 0x56 /* OV518(+) only */
486#define R518_GPIO_CTL 0x57 /* OV518(+) only */
487
6a7eba24 488/* OV519 Camera interface register numbers */
ac40b1fa
JFM		 489#define OV519_R10_H_SIZE 0x10
490#define OV519_R11_V_SIZE 0x11
491#define OV519_R12_X_OFFSETL 0x12
492#define OV519_R13_X_OFFSETH 0x13
493#define OV519_R14_Y_OFFSETL 0x14
494#define OV519_R15_Y_OFFSETH 0x15
495#define OV519_R16_DIVIDER 0x16
496#define OV519_R20_DFR 0x20
497#define OV519_R25_FORMAT 0x25
6a7eba24
JFM		 498
499/* OV519 System Controller register numbers */
500#define OV519_SYS_RESET1 0x51
501#define OV519_SYS_EN_CLK1 0x54
502
503#define OV519_GPIO_DATA_OUT0 0x71
504#define OV519_GPIO_IO_CTRL0 0x72
505
506#define OV511_ENDPOINT_ADDRESS 1 /* Isoc endpoint number */
507
b46aaa02
HG		 508/*
509 * The FX2 chip does not give us a zero length read at end of frame.
510 * It does, however, give a short read at the end of a frame, if
511 * neccessary, rather than run two frames together.
512 *
513 * By choosing the right bulk transfer size, we are guaranteed to always
514 * get a short read for the last read of each frame. Frame sizes are
515 * always a composite number (width * height, or a multiple) so if we
516 * choose a prime number, we are guaranteed that the last read of a
517 * frame will be short.
518 *
519 * But it isn't that easy: the 2.6 kernel requires a multiple of 4KB,
520 * otherwise EOVERFLOW "babbling" errors occur. I have not been able
521 * to figure out why. [PMiller]
522 *
523 * The constant (13 * 4096) is the largest "prime enough" number less than 64KB.
524 *
525 * It isn't enough to know the number of bytes per frame, in case we
526 * have data dropouts or buffer overruns (even though the FX2 double
527 * buffers, there are some pretty strict real time constraints for
528 * isochronous transfer for larger frame sizes).
529 */
530#define OVFX2_BULK_SIZE (13 * 4096)
531
6a7eba24
JFM		 532/* I2C registers */
533#define R51x_I2C_W_SID 0x41
534#define R51x_I2C_SADDR_3 0x42
535#define R51x_I2C_SADDR_2 0x43
536#define R51x_I2C_R_SID 0x44
537#define R51x_I2C_DATA 0x45
538#define R518_I2C_CTL 0x47 /* OV518(+) only */
b46aaa02 539#define OVFX2_I2C_ADDR 0x00
6a7eba24
JFM		 540
541/* I2C ADDRESSES */
542#define OV7xx0_SID 0x42
229bb7dc 543#define OV_HIRES_SID 0x60 /* OV9xxx / OV2xxx / OV3xxx */
6a7eba24
JFM		 544#define OV8xx0_SID 0xa0
545#define OV6xx0_SID 0xc0
546
547/* OV7610 registers */
548#define OV7610_REG_GAIN 0x00 /* gain setting (5:0) */
49809d6a
HG		 549#define OV7610_REG_BLUE 0x01 /* blue channel balance */
550#define OV7610_REG_RED 0x02 /* red channel balance */
6a7eba24
JFM		 551#define OV7610_REG_SAT 0x03 /* saturation */
552#define OV8610_REG_HUE 0x04 /* 04 reserved */
553#define OV7610_REG_CNT 0x05 /* Y contrast */
554#define OV7610_REG_BRT 0x06 /* Y brightness */
555#define OV7610_REG_COM_C 0x14 /* misc common regs */
556#define OV7610_REG_ID_HIGH 0x1c /* manufacturer ID MSB */
557#define OV7610_REG_ID_LOW 0x1d /* manufacturer ID LSB */
558#define OV7610_REG_COM_I 0x29 /* misc settings */
559
560/* OV7670 registers */
561#define OV7670_REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
562#define OV7670_REG_BLUE 0x01 /* blue gain */
563#define OV7670_REG_RED 0x02 /* red gain */
564#define OV7670_REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
565#define OV7670_REG_COM1 0x04 /* Control 1 */
566#define OV7670_REG_AECHH 0x07 /* AEC MS 5 bits */
567#define OV7670_REG_COM3 0x0c /* Control 3 */
568#define OV7670_REG_COM4 0x0d /* Control 4 */
569#define OV7670_REG_COM5 0x0e /* All "reserved" */
570#define OV7670_REG_COM6 0x0f /* Control 6 */
571#define OV7670_REG_AECH 0x10 /* More bits of AEC value */
572#define OV7670_REG_CLKRC 0x11 /* Clock control */
573#define OV7670_REG_COM7 0x12 /* Control 7 */
574#define OV7670_COM7_FMT_VGA 0x00
575#define OV7670_COM7_YUV 0x00 /* YUV */
576#define OV7670_COM7_FMT_QVGA 0x10 /* QVGA format */
577#define OV7670_COM7_FMT_MASK 0x38
578#define OV7670_COM7_RESET 0x80 /* Register reset */
579#define OV7670_REG_COM8 0x13 /* Control 8 */
580#define OV7670_COM8_AEC 0x01 /* Auto exposure enable */
581#define OV7670_COM8_AWB 0x02 /* White balance enable */
582#define OV7670_COM8_AGC 0x04 /* Auto gain enable */
583#define OV7670_COM8_BFILT 0x20 /* Band filter enable */
584#define OV7670_COM8_AECSTEP 0x40 /* Unlimited AEC step size */
585#define OV7670_COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
586#define OV7670_REG_COM9 0x14 /* Control 9 - gain ceiling */
587#define OV7670_REG_COM10 0x15 /* Control 10 */
588#define OV7670_REG_HSTART 0x17 /* Horiz start high bits */
589#define OV7670_REG_HSTOP 0x18 /* Horiz stop high bits */
590#define OV7670_REG_VSTART 0x19 /* Vert start high bits */
591#define OV7670_REG_VSTOP 0x1a /* Vert stop high bits */
592#define OV7670_REG_MVFP 0x1e /* Mirror / vflip */
0cd6759d 593#define OV7670_MVFP_VFLIP 0x10 /* vertical flip */
6a7eba24
JFM		 594#define OV7670_MVFP_MIRROR 0x20 /* Mirror image */
595#define OV7670_REG_AEW 0x24 /* AGC upper limit */
596#define OV7670_REG_AEB 0x25 /* AGC lower limit */
597#define OV7670_REG_VPT 0x26 /* AGC/AEC fast mode op region */
598#define OV7670_REG_HREF 0x32 /* HREF pieces */
599#define OV7670_REG_TSLB 0x3a /* lots of stuff */
600#define OV7670_REG_COM11 0x3b /* Control 11 */
601#define OV7670_COM11_EXP 0x02
602#define OV7670_COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */
603#define OV7670_REG_COM12 0x3c /* Control 12 */
604#define OV7670_REG_COM13 0x3d /* Control 13 */
605#define OV7670_COM13_GAMMA 0x80 /* Gamma enable */
606#define OV7670_COM13_UVSAT 0x40 /* UV saturation auto adjustment */
607#define OV7670_REG_COM14 0x3e /* Control 14 */
608#define OV7670_REG_EDGE 0x3f /* Edge enhancement factor */
609#define OV7670_REG_COM15 0x40 /* Control 15 */
610#define OV7670_COM15_R00FF 0xc0 /* 00 to FF */
611#define OV7670_REG_COM16 0x41 /* Control 16 */
612#define OV7670_COM16_AWBGAIN 0x08 /* AWB gain enable */
613#define OV7670_REG_BRIGHT 0x55 /* Brightness */
614#define OV7670_REG_CONTRAS 0x56 /* Contrast control */
615#define OV7670_REG_GFIX 0x69 /* Fix gain control */
616#define OV7670_REG_RGB444 0x8c /* RGB 444 control */
617#define OV7670_REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */
618#define OV7670_REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
619#define OV7670_REG_BD50MAX 0xa5 /* 50hz banding step limit */
620#define OV7670_REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
621#define OV7670_REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
622#define OV7670_REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
623#define OV7670_REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
624#define OV7670_REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */
625#define OV7670_REG_BD60MAX 0xab /* 60hz banding step limit */
626
4202f71c
JFM		 627struct ov_regvals {
628 __u8 reg;
629 __u8 val;
630};
631struct ov_i2c_regvals {
632 __u8 reg;
633 __u8 val;
634};
635
635118d5
HG		 636/* Settings for OV2610 camera chip */
637static const struct ov_i2c_regvals norm_2610[] =
638{
b46aaa02 639 { 0x12, 0x80 }, /* reset */
635118d5
HG		 640};
641
642static const struct ov_i2c_regvals norm_3620b[] =
643{
644 /*
645 * From the datasheet: "Note that after writing to register COMH
646 * (0x12) to change the sensor mode, registers related to the
647 * sensor’s cropping window will be reset back to their default
648 * values."
649 *
650 * "wait 4096 external clock ... to make sure the sensor is
651 * stable and ready to access registers" i.e. 160us at 24MHz
652 */
653
654 { 0x12, 0x80 }, /* COMH reset */
655 { 0x12, 0x00 }, /* QXGA, master */
656
657 /*
658 * 11 CLKRC "Clock Rate Control"
659 * [7] internal frequency doublers: on
660 * [6] video port mode: master
661 * [5:0] clock divider: 1
662 */
663 { 0x11, 0x80 },
664
665 /*
666 * 13 COMI "Common Control I"
667 * = 192 (0xC0) 11000000
668 * COMI[7] "AEC speed selection"
669 * = 1 (0x01) 1....... "Faster AEC correction"
670 * COMI[6] "AEC speed step selection"
671 * = 1 (0x01) .1...... "Big steps, fast"
672 * COMI[5] "Banding filter on off"
673 * = 0 (0x00) ..0..... "Off"
674 * COMI[4] "Banding filter option"
675 * = 0 (0x00) ...0.... "Main clock is 48 MHz and
676 * the PLL is ON"
677 * COMI[3] "Reserved"
678 * = 0 (0x00) ....0...
679 * COMI[2] "AGC auto manual control selection"
680 * = 0 (0x00) .....0.. "Manual"
681 * COMI[1] "AWB auto manual control selection"
682 * = 0 (0x00) ......0. "Manual"
683 * COMI[0] "Exposure control"
684 * = 0 (0x00) .......0 "Manual"
685 */
686 { 0x13, 0xC0 },
687
688 /*
689 * 09 COMC "Common Control C"
690 * = 8 (0x08) 00001000
691 * COMC[7:5] "Reserved"
692 * = 0 (0x00) 000.....
693 * COMC[4] "Sleep Mode Enable"
694 * = 0 (0x00) ...0.... "Normal mode"
695 * COMC[3:2] "Sensor sampling reset timing selection"
696 * = 2 (0x02) ....10.. "Longer reset time"
697 * COMC[1:0] "Output drive current select"
698 * = 0 (0x00) ......00 "Weakest"
699 */
700 { 0x09, 0x08 },
701
702 /*
703 * 0C COMD "Common Control D"
704 * = 8 (0x08) 00001000
705 * COMD[7] "Reserved"
706 * = 0 (0x00) 0.......
707 * COMD[6] "Swap MSB and LSB at the output port"
708 * = 0 (0x00) .0...... "False"
709 * COMD[5:3] "Reserved"
710 * = 1 (0x01) ..001...
711 * COMD[2] "Output Average On Off"
712 * = 0 (0x00) .....0.. "Output Normal"
713 * COMD[1] "Sensor precharge voltage selection"
714 * = 0 (0x00) ......0. "Selects internal
715 * reference precharge
716 * voltage"
717 * COMD[0] "Snapshot option"
718 * = 0 (0x00) .......0 "Enable live video output
719 * after snapshot sequence"
720 */
721 { 0x0c, 0x08 },
722
723 /*
724 * 0D COME "Common Control E"
725 * = 161 (0xA1) 10100001
726 * COME[7] "Output average option"
727 * = 1 (0x01) 1....... "Output average of 4 pixels"
728 * COME[6] "Anti-blooming control"
729 * = 0 (0x00) .0...... "Off"
730 * COME[5:3] "Reserved"
731 * = 4 (0x04) ..100...
732 * COME[2] "Clock output power down pin status"
733 * = 0 (0x00) .....0.. "Tri-state data output pin
734 * on power down"
735 * COME[1] "Data output pin status selection at power down"
736 * = 0 (0x00) ......0. "Tri-state VSYNC, PCLK,
737 * HREF, and CHSYNC pins on
738 * power down"
739 * COME[0] "Auto zero circuit select"
740 * = 1 (0x01) .......1 "On"
741 */
742 { 0x0d, 0xA1 },
743
744 /*
745 * 0E COMF "Common Control F"
746 * = 112 (0x70) 01110000
747 * COMF[7] "System clock selection"
748 * = 0 (0x00) 0....... "Use 24 MHz system clock"
749 * COMF[6:4] "Reserved"
750 * = 7 (0x07) .111....
751 * COMF[3] "Manual auto negative offset canceling selection"
752 * = 0 (0x00) ....0... "Auto detect negative
753 * offset and cancel it"
754 * COMF[2:0] "Reserved"
755 * = 0 (0x00) .....000
756 */
757 { 0x0e, 0x70 },
758
759 /*
760 * 0F COMG "Common Control G"
761 * = 66 (0x42) 01000010
762 * COMG[7] "Optical black output selection"
763 * = 0 (0x00) 0....... "Disable"
764 * COMG[6] "Black level calibrate selection"
765 * = 1 (0x01) .1...... "Use optical black pixels
766 * to calibrate"
767 * COMG[5:4] "Reserved"
768 * = 0 (0x00) ..00....
769 * COMG[3] "Channel offset adjustment"
770 * = 0 (0x00) ....0... "Disable offset adjustment"
771 * COMG[2] "ADC black level calibration option"
772 * = 0 (0x00) .....0.. "Use B/G line and G/R
773 * line to calibrate each
774 * channel's black level"
775 * COMG[1] "Reserved"
776 * = 1 (0x01) ......1.
777 * COMG[0] "ADC black level calibration enable"
778 * = 0 (0x00) .......0 "Disable"
779 */
780 { 0x0f, 0x42 },
781
782 /*
783 * 14 COMJ "Common Control J"
784 * = 198 (0xC6) 11000110
785 * COMJ[7:6] "AGC gain ceiling"
786 * = 3 (0x03) 11...... "8x"
787 * COMJ[5:4] "Reserved"
788 * = 0 (0x00) ..00....
789 * COMJ[3] "Auto banding filter"
790 * = 0 (0x00) ....0... "Banding filter is always
791 * on off depending on
792 * COMI[5] setting"
793 * COMJ[2] "VSYNC drop option"
794 * = 1 (0x01) .....1.. "SYNC is dropped if frame
795 * data is dropped"
796 * COMJ[1] "Frame data drop"
797 * = 1 (0x01) ......1. "Drop frame data if
798 * exposure is not within
799 * tolerance. In AEC mode,
800 * data is normally dropped
801 * when data is out of
802 * range."
803 * COMJ[0] "Reserved"
804 * = 0 (0x00) .......0
805 */
806 { 0x14, 0xC6 },
807
808 /*
809 * 15 COMK "Common Control K"
810 * = 2 (0x02) 00000010
811 * COMK[7] "CHSYNC pin output swap"
812 * = 0 (0x00) 0....... "CHSYNC"
813 * COMK[6] "HREF pin output swap"
814 * = 0 (0x00) .0...... "HREF"
815 * COMK[5] "PCLK output selection"
816 * = 0 (0x00) ..0..... "PCLK always output"
817 * COMK[4] "PCLK edge selection"
818 * = 0 (0x00) ...0.... "Data valid on falling edge"
819 * COMK[3] "HREF output polarity"
820 * = 0 (0x00) ....0... "positive"
821 * COMK[2] "Reserved"
822 * = 0 (0x00) .....0..
823 * COMK[1] "VSYNC polarity"
824 * = 1 (0x01) ......1. "negative"
825 * COMK[0] "HSYNC polarity"
826 * = 0 (0x00) .......0 "positive"
827 */
828 { 0x15, 0x02 },
829
830 /*
831 * 33 CHLF "Current Control"
832 * = 9 (0x09) 00001001
833 * CHLF[7:6] "Sensor current control"
834 * = 0 (0x00) 00......
835 * CHLF[5] "Sensor current range control"
836 * = 0 (0x00) ..0..... "normal range"
837 * CHLF[4] "Sensor current"
838 * = 0 (0x00) ...0.... "normal current"
839 * CHLF[3] "Sensor buffer current control"
840 * = 1 (0x01) ....1... "half current"
841 * CHLF[2] "Column buffer current control"
842 * = 0 (0x00) .....0.. "normal current"
843 * CHLF[1] "Analog DSP current control"
844 * = 0 (0x00) ......0. "normal current"
845 * CHLF[1] "ADC current control"
846 * = 0 (0x00) ......0. "normal current"
847 */
848 { 0x33, 0x09 },
849
850 /*
851 * 34 VBLM "Blooming Control"
852 * = 80 (0x50) 01010000
853 * VBLM[7] "Hard soft reset switch"
854 * = 0 (0x00) 0....... "Hard reset"
855 * VBLM[6:4] "Blooming voltage selection"
856 * = 5 (0x05) .101....
857 * VBLM[3:0] "Sensor current control"
858 * = 0 (0x00) ....0000
859 */
860 { 0x34, 0x50 },
861
862 /*
863 * 36 VCHG "Sensor Precharge Voltage Control"
864 * = 0 (0x00) 00000000
865 * VCHG[7] "Reserved"
866 * = 0 (0x00) 0.......
867 * VCHG[6:4] "Sensor precharge voltage control"
868 * = 0 (0x00) .000....
869 * VCHG[3:0] "Sensor array common reference"
870 * = 0 (0x00) ....0000
871 */
872 { 0x36, 0x00 },
873
874 /*
875 * 37 ADC "ADC Reference Control"
876 * = 4 (0x04) 00000100
877 * ADC[7:4] "Reserved"
878 * = 0 (0x00) 0000....
879 * ADC[3] "ADC input signal range"
880 * = 0 (0x00) ....0... "Input signal 1.0x"
881 * ADC[2:0] "ADC range control"
882 * = 4 (0x04) .....100
883 */
884 { 0x37, 0x04 },
885
886 /*
887 * 38 ACOM "Analog Common Ground"
888 * = 82 (0x52) 01010010
889 * ACOM[7] "Analog gain control"
890 * = 0 (0x00) 0....... "Gain 1x"
891 * ACOM[6] "Analog black level calibration"
892 * = 1 (0x01) .1...... "On"
893 * ACOM[5:0] "Reserved"
894 * = 18 (0x12) ..010010
895 */
896 { 0x38, 0x52 },
897
898 /*
899 * 3A FREFA "Internal Reference Adjustment"
900 * = 0 (0x00) 00000000
901 * FREFA[7:0] "Range"
902 * = 0 (0x00) 00000000
903 */
904 { 0x3a, 0x00 },
905
906 /*
907 * 3C FVOPT "Internal Reference Adjustment"
908 * = 31 (0x1F) 00011111
909 * FVOPT[7:0] "Range"
910 * = 31 (0x1F) 00011111
911 */
912 { 0x3c, 0x1F },
913
914 /*
915 * 44 Undocumented = 0 (0x00) 00000000
916 * 44[7:0] "It's a secret"
917 * = 0 (0x00) 00000000
918 */
919 { 0x44, 0x00 },
920
921 /*
922 * 40 Undocumented = 0 (0x00) 00000000
923 * 40[7:0] "It's a secret"
924 * = 0 (0x00) 00000000
925 */
926 { 0x40, 0x00 },
927
928 /*
929 * 41 Undocumented = 0 (0x00) 00000000
930 * 41[7:0] "It's a secret"
931 * = 0 (0x00) 00000000
932 */
933 { 0x41, 0x00 },
934
935 /*
936 * 42 Undocumented = 0 (0x00) 00000000
937 * 42[7:0] "It's a secret"
938 * = 0 (0x00) 00000000
939 */
940 { 0x42, 0x00 },
941
942 /*
943 * 43 Undocumented = 0 (0x00) 00000000
944 * 43[7:0] "It's a secret"
945 * = 0 (0x00) 00000000
946 */
947 { 0x43, 0x00 },
948
949 /*
950 * 45 Undocumented = 128 (0x80) 10000000
951 * 45[7:0] "It's a secret"
952 * = 128 (0x80) 10000000
953 */
954 { 0x45, 0x80 },
955
956 /*
957 * 48 Undocumented = 192 (0xC0) 11000000
958 * 48[7:0] "It's a secret"
959 * = 192 (0xC0) 11000000
960 */
961 { 0x48, 0xC0 },
962
963 /*
964 * 49 Undocumented = 25 (0x19) 00011001
965 * 49[7:0] "It's a secret"
966 * = 25 (0x19) 00011001
967 */
968 { 0x49, 0x19 },
969
970 /*
971 * 4B Undocumented = 128 (0x80) 10000000
972 * 4B[7:0] "It's a secret"
973 * = 128 (0x80) 10000000
974 */
975 { 0x4B, 0x80 },
976
977 /*
978 * 4D Undocumented = 196 (0xC4) 11000100
979 * 4D[7:0] "It's a secret"
980 * = 196 (0xC4) 11000100
981 */
982 { 0x4D, 0xC4 },
983
984 /*
985 * 35 VREF "Reference Voltage Control"
986 * = 76 (0x4C) 01001100
987 * VREF[7:5] "Column high reference control"
988 * = 2 (0x02) 010..... "higher voltage"
989 * VREF[4:2] "Column low reference control"
990 * = 3 (0x03) ...011.. "Highest voltage"
991 * VREF[1:0] "Reserved"
992 * = 0 (0x00) ......00
993 */
994 { 0x35, 0x4C },
995
996 /*
997 * 3D Undocumented = 0 (0x00) 00000000
998 * 3D[7:0] "It's a secret"
999 * = 0 (0x00) 00000000
1000 */
1001 { 0x3D, 0x00 },
1002
1003 /*
1004 * 3E Undocumented = 0 (0x00) 00000000
1005 * 3E[7:0] "It's a secret"
1006 * = 0 (0x00) 00000000
1007 */
1008 { 0x3E, 0x00 },
1009
1010 /*
1011 * 3B FREFB "Internal Reference Adjustment"
1012 * = 24 (0x18) 00011000
1013 * FREFB[7:0] "Range"
1014 * = 24 (0x18) 00011000
1015 */
1016 { 0x3b, 0x18 },
1017
1018 /*
1019 * 33 CHLF "Current Control"
1020 * = 25 (0x19) 00011001
1021 * CHLF[7:6] "Sensor current control"
1022 * = 0 (0x00) 00......
1023 * CHLF[5] "Sensor current range control"
1024 * = 0 (0x00) ..0..... "normal range"
1025 * CHLF[4] "Sensor current"
1026 * = 1 (0x01) ...1.... "double current"
1027 * CHLF[3] "Sensor buffer current control"
1028 * = 1 (0x01) ....1... "half current"
1029 * CHLF[2] "Column buffer current control"
1030 * = 0 (0x00) .....0.. "normal current"
1031 * CHLF[1] "Analog DSP current control"
1032 * = 0 (0x00) ......0. "normal current"
1033 * CHLF[1] "ADC current control"
1034 * = 0 (0x00) ......0. "normal current"
1035 */
1036 { 0x33, 0x19 },
1037
1038 /*
1039 * 34 VBLM "Blooming Control"
1040 * = 90 (0x5A) 01011010
1041 * VBLM[7] "Hard soft reset switch"
1042 * = 0 (0x00) 0....... "Hard reset"
1043 * VBLM[6:4] "Blooming voltage selection"
1044 * = 5 (0x05) .101....
1045 * VBLM[3:0] "Sensor current control"
1046 * = 10 (0x0A) ....1010
1047 */
1048 { 0x34, 0x5A },
1049
1050 /*
1051 * 3B FREFB "Internal Reference Adjustment"
1052 * = 0 (0x00) 00000000
1053 * FREFB[7:0] "Range"
1054 * = 0 (0x00) 00000000
1055 */
1056 { 0x3b, 0x00 },
1057
1058 /*
1059 * 33 CHLF "Current Control"
1060 * = 9 (0x09) 00001001
1061 * CHLF[7:6] "Sensor current control"
1062 * = 0 (0x00) 00......
1063 * CHLF[5] "Sensor current range control"
1064 * = 0 (0x00) ..0..... "normal range"
1065 * CHLF[4] "Sensor current"
1066 * = 0 (0x00) ...0.... "normal current"
1067 * CHLF[3] "Sensor buffer current control"
1068 * = 1 (0x01) ....1... "half current"
1069 * CHLF[2] "Column buffer current control"
1070 * = 0 (0x00) .....0.. "normal current"
1071 * CHLF[1] "Analog DSP current control"
1072 * = 0 (0x00) ......0. "normal current"
1073 * CHLF[1] "ADC current control"
1074 * = 0 (0x00) ......0. "normal current"
1075 */
1076 { 0x33, 0x09 },
1077
1078 /*
1079 * 34 VBLM "Blooming Control"
1080 * = 80 (0x50) 01010000
1081 * VBLM[7] "Hard soft reset switch"
1082 * = 0 (0x00) 0....... "Hard reset"
1083 * VBLM[6:4] "Blooming voltage selection"
1084 * = 5 (0x05) .101....
1085 * VBLM[3:0] "Sensor current control"
1086 * = 0 (0x00) ....0000
1087 */
1088 { 0x34, 0x50 },
1089
1090 /*
1091 * 12 COMH "Common Control H"
1092 * = 64 (0x40) 01000000
1093 * COMH[7] "SRST"
1094 * = 0 (0x00) 0....... "No-op"
1095 * COMH[6:4] "Resolution selection"
1096 * = 4 (0x04) .100.... "XGA"
1097 * COMH[3] "Master slave selection"
1098 * = 0 (0x00) ....0... "Master mode"
1099 * COMH[2] "Internal B/R channel option"
1100 * = 0 (0x00) .....0.. "B/R use same channel"
1101 * COMH[1] "Color bar test pattern"
1102 * = 0 (0x00) ......0. "Off"
1103 * COMH[0] "Reserved"
1104 * = 0 (0x00) .......0
1105 */
1106 { 0x12, 0x40 },
1107
1108 /*
1109 * 17 HREFST "Horizontal window start"
1110 * = 31 (0x1F) 00011111
1111 * HREFST[7:0] "Horizontal window start, 8 MSBs"
1112 * = 31 (0x1F) 00011111
1113 */
1114 { 0x17, 0x1F },
1115
1116 /*
1117 * 18 HREFEND "Horizontal window end"
1118 * = 95 (0x5F) 01011111
1119 * HREFEND[7:0] "Horizontal Window End, 8 MSBs"
1120 * = 95 (0x5F) 01011111
1121 */
1122 { 0x18, 0x5F },
1123
1124 /*
1125 * 19 VSTRT "Vertical window start"
1126 * = 0 (0x00) 00000000
1127 * VSTRT[7:0] "Vertical Window Start, 8 MSBs"
1128 * = 0 (0x00) 00000000
1129 */
1130 { 0x19, 0x00 },
1131
1132 /*
1133 * 1A VEND "Vertical window end"
1134 * = 96 (0x60) 01100000
1135 * VEND[7:0] "Vertical Window End, 8 MSBs"
1136 * = 96 (0x60) 01100000
1137 */
1138 { 0x1a, 0x60 },
1139
1140 /*
1141 * 32 COMM "Common Control M"
1142 * = 18 (0x12) 00010010
1143 * COMM[7:6] "Pixel clock divide option"
1144 * = 0 (0x00) 00...... "/1"
1145 * COMM[5:3] "Horizontal window end position, 3 LSBs"
1146 * = 2 (0x02) ..010...
1147 * COMM[2:0] "Horizontal window start position, 3 LSBs"
1148 * = 2 (0x02) .....010
1149 */
1150 { 0x32, 0x12 },
1151
1152 /*
1153 * 03 COMA "Common Control A"
1154 * = 74 (0x4A) 01001010
1155 * COMA[7:4] "AWB Update Threshold"
1156 * = 4 (0x04) 0100....
1157 * COMA[3:2] "Vertical window end line control 2 LSBs"
1158 * = 2 (0x02) ....10..
1159 * COMA[1:0] "Vertical window start line control 2 LSBs"
1160 * = 2 (0x02) ......10
1161 */
1162 { 0x03, 0x4A },
1163
1164 /*
1165 * 11 CLKRC "Clock Rate Control"
1166 * = 128 (0x80) 10000000
1167 * CLKRC[7] "Internal frequency doublers on off seclection"
1168 * = 1 (0x01) 1....... "On"
1169 * CLKRC[6] "Digital video master slave selection"
1170 * = 0 (0x00) .0...... "Master mode, sensor
1171 * provides PCLK"
1172 * CLKRC[5:0] "Clock divider { CLK = PCLK/(1+CLKRC[5:0]) }"
1173 * = 0 (0x00) ..000000
1174 */
1175 { 0x11, 0x80 },
1176
1177 /*
1178 * 12 COMH "Common Control H"
1179 * = 0 (0x00) 00000000
1180 * COMH[7] "SRST"
1181 * = 0 (0x00) 0....... "No-op"
1182 * COMH[6:4] "Resolution selection"
1183 * = 0 (0x00) .000.... "QXGA"
1184 * COMH[3] "Master slave selection"
1185 * = 0 (0x00) ....0... "Master mode"
1186 * COMH[2] "Internal B/R channel option"
1187 * = 0 (0x00) .....0.. "B/R use same channel"
1188 * COMH[1] "Color bar test pattern"
1189 * = 0 (0x00) ......0. "Off"
1190 * COMH[0] "Reserved"
1191 * = 0 (0x00) .......0
1192 */
1193 { 0x12, 0x00 },
1194
1195 /*
1196 * 12 COMH "Common Control H"
1197 * = 64 (0x40) 01000000
1198 * COMH[7] "SRST"
1199 * = 0 (0x00) 0....... "No-op"
1200 * COMH[6:4] "Resolution selection"
1201 * = 4 (0x04) .100.... "XGA"
1202 * COMH[3] "Master slave selection"
1203 * = 0 (0x00) ....0... "Master mode"
1204 * COMH[2] "Internal B/R channel option"
1205 * = 0 (0x00) .....0.. "B/R use same channel"
1206 * COMH[1] "Color bar test pattern"
1207 * = 0 (0x00) ......0. "Off"
1208 * COMH[0] "Reserved"
1209 * = 0 (0x00) .......0
1210 */
1211 { 0x12, 0x40 },
1212
1213 /*
1214 * 17 HREFST "Horizontal window start"
1215 * = 31 (0x1F) 00011111
1216 * HREFST[7:0] "Horizontal window start, 8 MSBs"
1217 * = 31 (0x1F) 00011111
1218 */
1219 { 0x17, 0x1F },
1220
1221 /*
1222 * 18 HREFEND "Horizontal window end"
1223 * = 95 (0x5F) 01011111
1224 * HREFEND[7:0] "Horizontal Window End, 8 MSBs"
1225 * = 95 (0x5F) 01011111
1226 */
1227 { 0x18, 0x5F },
1228
1229 /*
1230 * 19 VSTRT "Vertical window start"
1231 * = 0 (0x00) 00000000
1232 * VSTRT[7:0] "Vertical Window Start, 8 MSBs"
1233 * = 0 (0x00) 00000000
1234 */
1235 { 0x19, 0x00 },
1236
1237 /*
1238 * 1A VEND "Vertical window end"
1239 * = 96 (0x60) 01100000
1240 * VEND[7:0] "Vertical Window End, 8 MSBs"
1241 * = 96 (0x60) 01100000
1242 */
1243 { 0x1a, 0x60 },
1244
1245 /*
1246 * 32 COMM "Common Control M"
1247 * = 18 (0x12) 00010010
1248 * COMM[7:6] "Pixel clock divide option"
1249 * = 0 (0x00) 00...... "/1"
1250 * COMM[5:3] "Horizontal window end position, 3 LSBs"
1251 * = 2 (0x02) ..010...
1252 * COMM[2:0] "Horizontal window start position, 3 LSBs"
1253 * = 2 (0x02) .....010
1254 */
1255 { 0x32, 0x12 },
1256
1257 /*
1258 * 03 COMA "Common Control A"
1259 * = 74 (0x4A) 01001010
1260 * COMA[7:4] "AWB Update Threshold"
1261 * = 4 (0x04) 0100....
1262 * COMA[3:2] "Vertical window end line control 2 LSBs"
1263 * = 2 (0x02) ....10..
1264 * COMA[1:0] "Vertical window start line control 2 LSBs"
1265 * = 2 (0x02) ......10
1266 */
1267 { 0x03, 0x4A },
1268
1269 /*
1270 * 02 RED "Red Gain Control"
1271 * = 175 (0xAF) 10101111
1272 * RED[7] "Action"
1273 * = 1 (0x01) 1....... "gain = 1/(1+bitrev([6:0]))"
1274 * RED[6:0] "Value"
1275 * = 47 (0x2F) .0101111
1276 */
1277 { 0x02, 0xAF },
1278
1279 /*
1280 * 2D ADDVSL "VSYNC Pulse Width"
1281 * = 210 (0xD2) 11010010
1282 * ADDVSL[7:0] "VSYNC pulse width, LSB"
1283 * = 210 (0xD2) 11010010
1284 */
1285 { 0x2d, 0xD2 },
1286
1287 /*
1288 * 00 GAIN = 24 (0x18) 00011000
1289 * GAIN[7:6] "Reserved"
1290 * = 0 (0x00) 00......
1291 * GAIN[5] "Double"
1292 * = 0 (0x00) ..0..... "False"
1293 * GAIN[4] "Double"
1294 * = 1 (0x01) ...1.... "True"
1295 * GAIN[3:0] "Range"
1296 * = 8 (0x08) ....1000
1297 */
1298 { 0x00, 0x18 },
1299
1300 /*
1301 * 01 BLUE "Blue Gain Control"
1302 * = 240 (0xF0) 11110000
1303 * BLUE[7] "Action"
1304 * = 1 (0x01) 1....... "gain = 1/(1+bitrev([6:0]))"
1305 * BLUE[6:0] "Value"
1306 * = 112 (0x70) .1110000
1307 */
1308 { 0x01, 0xF0 },
1309
1310 /*
1311 * 10 AEC "Automatic Exposure Control"
1312 * = 10 (0x0A) 00001010
1313 * AEC[7:0] "Automatic Exposure Control, 8 MSBs"
1314 * = 10 (0x0A) 00001010
1315 */
1316 { 0x10, 0x0A },
1317
1318 { 0xE1, 0x67 },
1319 { 0xE3, 0x03 },
1320 { 0xE4, 0x26 },
1321 { 0xE5, 0x3E },
1322 { 0xF8, 0x01 },
1323 { 0xFF, 0x01 },
1324};
1325
4202f71c
JFM		 1326static const struct ov_i2c_regvals norm_6x20[] = {
1327 { 0x12, 0x80 }, /* reset */
1328 { 0x11, 0x01 },
1329 { 0x03, 0x60 },
1330 { 0x05, 0x7f }, /* For when autoadjust is off */
1331 { 0x07, 0xa8 },
1332 /* The ratio of 0x0c and 0x0d controls the white point */
1333 { 0x0c, 0x24 },
1334 { 0x0d, 0x24 },
1335 { 0x0f, 0x15 }, /* COMS */
1336 { 0x10, 0x75 }, /* AEC Exposure time */
1337 { 0x12, 0x24 }, /* Enable AGC */
1338 { 0x14, 0x04 },
1339 /* 0x16: 0x06 helps frame stability with moving objects */
1340 { 0x16, 0x06 },
1341/* { 0x20, 0x30 }, * Aperture correction enable */
1342 { 0x26, 0xb2 }, /* BLC enable */
1343 /* 0x28: 0x05 Selects RGB format if RGB on */
1344 { 0x28, 0x05 },
1345 { 0x2a, 0x04 }, /* Disable framerate adjust */
1346/* { 0x2b, 0xac }, * Framerate; Set 2a[7] first */
ae49c404 1347 { 0x2d, 0x85 },
4202f71c
JFM		 1348 { 0x33, 0xa0 }, /* Color Processing Parameter */
1349 { 0x34, 0xd2 }, /* Max A/D range */
1350 { 0x38, 0x8b },
1351 { 0x39, 0x40 },
1352
1353 { 0x3c, 0x39 }, /* Enable AEC mode changing */
1354 { 0x3c, 0x3c }, /* Change AEC mode */
1355 { 0x3c, 0x24 }, /* Disable AEC mode changing */
1356
1357 { 0x3d, 0x80 },
1358 /* These next two registers (0x4a, 0x4b) are undocumented.
1359 * They control the color balance */
1360 { 0x4a, 0x80 },
1361 { 0x4b, 0x80 },
1362 { 0x4d, 0xd2 }, /* This reduces noise a bit */
1363 { 0x4e, 0xc1 },
1364 { 0x4f, 0x04 },
1365/* Do 50-53 have any effect? */
1366/* Toggle 0x12[2] off and on here? */
1367};
1368
1369static const struct ov_i2c_regvals norm_6x30[] = {
1370 { 0x12, 0x80 }, /* Reset */
1371 { 0x00, 0x1f }, /* Gain */
1372 { 0x01, 0x99 }, /* Blue gain */
1373 { 0x02, 0x7c }, /* Red gain */
1374 { 0x03, 0xc0 }, /* Saturation */
1375 { 0x05, 0x0a }, /* Contrast */
1376 { 0x06, 0x95 }, /* Brightness */
1377 { 0x07, 0x2d }, /* Sharpness */
1378 { 0x0c, 0x20 },
1379 { 0x0d, 0x20 },
02ab18b0 1380 { 0x0e, 0xa0 }, /* Was 0x20, bit7 enables a 2x gain which we need */
4202f71c
JFM		 1381 { 0x0f, 0x05 },
1382 { 0x10, 0x9a },
1383 { 0x11, 0x00 }, /* Pixel clock = fastest */
1384 { 0x12, 0x24 }, /* Enable AGC and AWB */
1385 { 0x13, 0x21 },
1386 { 0x14, 0x80 },
1387 { 0x15, 0x01 },
1388 { 0x16, 0x03 },
1389 { 0x17, 0x38 },
1390 { 0x18, 0xea },
1391 { 0x19, 0x04 },
1392 { 0x1a, 0x93 },
1393 { 0x1b, 0x00 },
1394 { 0x1e, 0xc4 },
1395 { 0x1f, 0x04 },
1396 { 0x20, 0x20 },
1397 { 0x21, 0x10 },
1398 { 0x22, 0x88 },
1399 { 0x23, 0xc0 }, /* Crystal circuit power level */
1400 { 0x25, 0x9a }, /* Increase AEC black ratio */
1401 { 0x26, 0xb2 }, /* BLC enable */
1402 { 0x27, 0xa2 },
1403 { 0x28, 0x00 },
1404 { 0x29, 0x00 },
1405 { 0x2a, 0x84 }, /* 60 Hz power */
1406 { 0x2b, 0xa8 }, /* 60 Hz power */
1407 { 0x2c, 0xa0 },
1408 { 0x2d, 0x95 }, /* Enable auto-brightness */
1409 { 0x2e, 0x88 },
1410 { 0x33, 0x26 },
1411 { 0x34, 0x03 },
1412 { 0x36, 0x8f },
1413 { 0x37, 0x80 },
1414 { 0x38, 0x83 },
1415 { 0x39, 0x80 },
1416 { 0x3a, 0x0f },
1417 { 0x3b, 0x3c },
1418 { 0x3c, 0x1a },
1419 { 0x3d, 0x80 },
1420 { 0x3e, 0x80 },
1421 { 0x3f, 0x0e },
1422 { 0x40, 0x00 }, /* White bal */
1423 { 0x41, 0x00 }, /* White bal */
1424 { 0x42, 0x80 },
1425 { 0x43, 0x3f }, /* White bal */
1426 { 0x44, 0x80 },
1427 { 0x45, 0x20 },
1428 { 0x46, 0x20 },
1429 { 0x47, 0x80 },
1430 { 0x48, 0x7f },
1431 { 0x49, 0x00 },
1432 { 0x4a, 0x00 },
1433 { 0x4b, 0x80 },
1434 { 0x4c, 0xd0 },
1435 { 0x4d, 0x10 }, /* U = 0.563u, V = 0.714v */
1436 { 0x4e, 0x40 },
1437 { 0x4f, 0x07 }, /* UV avg., col. killer: max */
1438 { 0x50, 0xff },
1439 { 0x54, 0x23 }, /* Max AGC gain: 18dB */
1440 { 0x55, 0xff },
1441 { 0x56, 0x12 },
1442 { 0x57, 0x81 },
1443 { 0x58, 0x75 },
1444 { 0x59, 0x01 }, /* AGC dark current comp.: +1 */
1445 { 0x5a, 0x2c },
1446 { 0x5b, 0x0f }, /* AWB chrominance levels */
1447 { 0x5c, 0x10 },
1448 { 0x3d, 0x80 },
1449 { 0x27, 0xa6 },
1450 { 0x12, 0x20 }, /* Toggle AWB */
1451 { 0x12, 0x24 },
1452};
1453
1454/* Lawrence Glaister <lg@jfm.bc.ca> reports:
1455 *
1456 * Register 0x0f in the 7610 has the following effects:
1457 *
1458 * 0x85 (AEC method 1): Best overall, good contrast range
1459 * 0x45 (AEC method 2): Very overexposed
1460 * 0xa5 (spec sheet default): Ok, but the black level is
1461 * shifted resulting in loss of contrast
1462 * 0x05 (old driver setting): very overexposed, too much
1463 * contrast
1464 */
1465static const struct ov_i2c_regvals norm_7610[] = {
1466 { 0x10, 0xff },
1467 { 0x16, 0x06 },
1468 { 0x28, 0x24 },
1469 { 0x2b, 0xac },
1470 { 0x12, 0x00 },
1471 { 0x38, 0x81 },
1472 { 0x28, 0x24 }, /* 0c */
1473 { 0x0f, 0x85 }, /* lg's setting */
1474 { 0x15, 0x01 },
1475 { 0x20, 0x1c },
1476 { 0x23, 0x2a },
1477 { 0x24, 0x10 },
1478 { 0x25, 0x8a },
1479 { 0x26, 0xa2 },
1480 { 0x27, 0xc2 },
1481 { 0x2a, 0x04 },
1482 { 0x2c, 0xfe },
1483 { 0x2d, 0x93 },
1484 { 0x30, 0x71 },
1485 { 0x31, 0x60 },
1486 { 0x32, 0x26 },
1487 { 0x33, 0x20 },
1488 { 0x34, 0x48 },
1489 { 0x12, 0x24 },
1490 { 0x11, 0x01 },
1491 { 0x0c, 0x24 },
1492 { 0x0d, 0x24 },
1493};
1494
1495static const struct ov_i2c_regvals norm_7620[] = {
a511ba94 1496 { 0x12, 0x80 }, /* reset */
4202f71c
JFM		 1497 { 0x00, 0x00 }, /* gain */
1498 { 0x01, 0x80 }, /* blue gain */
1499 { 0x02, 0x80 }, /* red gain */
1500 { 0x03, 0xc0 }, /* OV7670_REG_VREF */
1501 { 0x06, 0x60 },
1502 { 0x07, 0x00 },
1503 { 0x0c, 0x24 },
1504 { 0x0c, 0x24 },
1505 { 0x0d, 0x24 },
1506 { 0x11, 0x01 },
1507 { 0x12, 0x24 },
1508 { 0x13, 0x01 },
1509 { 0x14, 0x84 },
1510 { 0x15, 0x01 },
1511 { 0x16, 0x03 },
1512 { 0x17, 0x2f },
1513 { 0x18, 0xcf },
1514 { 0x19, 0x06 },
1515 { 0x1a, 0xf5 },
1516 { 0x1b, 0x00 },
1517 { 0x20, 0x18 },
1518 { 0x21, 0x80 },
1519 { 0x22, 0x80 },
1520 { 0x23, 0x00 },
1521 { 0x26, 0xa2 },
1522 { 0x27, 0xea },
b282d873 1523 { 0x28, 0x22 }, /* Was 0x20, bit1 enables a 2x gain which we need */
4202f71c
JFM		 1524 { 0x29, 0x00 },
1525 { 0x2a, 0x10 },
1526 { 0x2b, 0x00 },
1527 { 0x2c, 0x88 },
1528 { 0x2d, 0x91 },
1529 { 0x2e, 0x80 },
1530 { 0x2f, 0x44 },
1531 { 0x60, 0x27 },
1532 { 0x61, 0x02 },
1533 { 0x62, 0x5f },
1534 { 0x63, 0xd5 },
1535 { 0x64, 0x57 },
1536 { 0x65, 0x83 },
1537 { 0x66, 0x55 },
1538 { 0x67, 0x92 },
1539 { 0x68, 0xcf },
1540 { 0x69, 0x76 },
1541 { 0x6a, 0x22 },
1542 { 0x6b, 0x00 },
1543 { 0x6c, 0x02 },
1544 { 0x6d, 0x44 },
1545 { 0x6e, 0x80 },
1546 { 0x6f, 0x1d },
1547 { 0x70, 0x8b },
1548 { 0x71, 0x00 },
1549 { 0x72, 0x14 },
1550 { 0x73, 0x54 },
1551 { 0x74, 0x00 },
1552 { 0x75, 0x8e },
1553 { 0x76, 0x00 },
1554 { 0x77, 0xff },
1555 { 0x78, 0x80 },
1556 { 0x79, 0x80 },
1557 { 0x7a, 0x80 },
1558 { 0x7b, 0xe2 },
1559 { 0x7c, 0x00 },
1560};
1561
1562/* 7640 and 7648. The defaults should be OK for most registers. */
1563static const struct ov_i2c_regvals norm_7640[] = {
1564 { 0x12, 0x80 },
1565 { 0x12, 0x14 },
1566};
1567
1568/* 7670. Defaults taken from OmniVision provided data,
1569* as provided by Jonathan Corbet of OLPC */
1570static const struct ov_i2c_regvals norm_7670[] = {
1571 { OV7670_REG_COM7, OV7670_COM7_RESET },
1572 { OV7670_REG_TSLB, 0x04 }, /* OV */
1573 { OV7670_REG_COM7, OV7670_COM7_FMT_VGA }, /* VGA */
1574 { OV7670_REG_CLKRC, 0x01 },
1575/*
1576 * Set the hardware window. These values from OV don't entirely
1577 * make sense - hstop is less than hstart. But they work...
1578 */
1579 { OV7670_REG_HSTART, 0x13 },
1580 { OV7670_REG_HSTOP, 0x01 },
1581 { OV7670_REG_HREF, 0xb6 },
1582 { OV7670_REG_VSTART, 0x02 },
1583 { OV7670_REG_VSTOP, 0x7a },
1584 { OV7670_REG_VREF, 0x0a },
1585
ac40b1fa
JFM		 1586 { OV7670_REG_COM3, 0x00 },
1587 { OV7670_REG_COM14, 0x00 },
4202f71c
JFM		 1588/* Mystery scaling numbers */
1589 { 0x70, 0x3a },
1590 { 0x71, 0x35 },
1591 { 0x72, 0x11 },
1592 { 0x73, 0xf0 },
1593 { 0xa2, 0x02 },
1594/* { OV7670_REG_COM10, 0x0 }, */
1595
1596/* Gamma curve values */
1597 { 0x7a, 0x20 },
1598 { 0x7b, 0x10 },
1599 { 0x7c, 0x1e },
1600 { 0x7d, 0x35 },
1601 { 0x7e, 0x5a },
1602 { 0x7f, 0x69 },
1603 { 0x80, 0x76 },
1604 { 0x81, 0x80 },
1605 { 0x82, 0x88 },
1606 { 0x83, 0x8f },
1607 { 0x84, 0x96 },
1608 { 0x85, 0xa3 },
1609 { 0x86, 0xaf },
1610 { 0x87, 0xc4 },
1611 { 0x88, 0xd7 },
1612 { 0x89, 0xe8 },
1613
1614/* AGC and AEC parameters. Note we start by disabling those features,
1615 then turn them only after tweaking the values. */
1616 { OV7670_REG_COM8, OV7670_COM8_FASTAEC
1617 | OV7670_COM8_AECSTEP
1618 | OV7670_COM8_BFILT },
ac40b1fa
JFM		 1619 { OV7670_REG_GAIN, 0x00 },
1620 { OV7670_REG_AECH, 0x00 },
4202f71c
JFM		 1621 { OV7670_REG_COM4, 0x40 }, /* magic reserved bit */
1622 { OV7670_REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */
1623 { OV7670_REG_BD50MAX, 0x05 },
1624 { OV7670_REG_BD60MAX, 0x07 },
1625 { OV7670_REG_AEW, 0x95 },
1626 { OV7670_REG_AEB, 0x33 },
1627 { OV7670_REG_VPT, 0xe3 },
1628 { OV7670_REG_HAECC1, 0x78 },
1629 { OV7670_REG_HAECC2, 0x68 },
1630 { 0xa1, 0x03 }, /* magic */
1631 { OV7670_REG_HAECC3, 0xd8 },
1632 { OV7670_REG_HAECC4, 0xd8 },
1633 { OV7670_REG_HAECC5, 0xf0 },
1634 { OV7670_REG_HAECC6, 0x90 },
1635 { OV7670_REG_HAECC7, 0x94 },
1636 { OV7670_REG_COM8, OV7670_COM8_FASTAEC
1637 | OV7670_COM8_AECSTEP
1638 | OV7670_COM8_BFILT
1639 | OV7670_COM8_AGC
1640 | OV7670_COM8_AEC },
1641
1642/* Almost all of these are magic "reserved" values. */
1643 { OV7670_REG_COM5, 0x61 },
1644 { OV7670_REG_COM6, 0x4b },
1645 { 0x16, 0x02 },
1646 { OV7670_REG_MVFP, 0x07 },
1647 { 0x21, 0x02 },
1648 { 0x22, 0x91 },
1649 { 0x29, 0x07 },
1650 { 0x33, 0x0b },
1651 { 0x35, 0x0b },
1652 { 0x37, 0x1d },
1653 { 0x38, 0x71 },
1654 { 0x39, 0x2a },
1655 { OV7670_REG_COM12, 0x78 },
1656 { 0x4d, 0x40 },
1657 { 0x4e, 0x20 },
ac40b1fa 1658 { OV7670_REG_GFIX, 0x00 },
4202f71c
JFM		 1659 { 0x6b, 0x4a },
1660 { 0x74, 0x10 },
1661 { 0x8d, 0x4f },
ac40b1fa
JFM		 1662 { 0x8e, 0x00 },
1663 { 0x8f, 0x00 },
1664 { 0x90, 0x00 },
1665 { 0x91, 0x00 },
1666 { 0x96, 0x00 },
1667 { 0x9a, 0x00 },
4202f71c
JFM		 1668 { 0xb0, 0x84 },
1669 { 0xb1, 0x0c },
1670 { 0xb2, 0x0e },
1671 { 0xb3, 0x82 },
1672 { 0xb8, 0x0a },
1673
1674/* More reserved magic, some of which tweaks white balance */
1675 { 0x43, 0x0a },
1676 { 0x44, 0xf0 },
1677 { 0x45, 0x34 },
1678 { 0x46, 0x58 },
1679 { 0x47, 0x28 },
1680 { 0x48, 0x3a },
1681 { 0x59, 0x88 },
1682 { 0x5a, 0x88 },
1683 { 0x5b, 0x44 },
1684 { 0x5c, 0x67 },
1685 { 0x5d, 0x49 },
1686 { 0x5e, 0x0e },
1687 { 0x6c, 0x0a },
1688 { 0x6d, 0x55 },
1689 { 0x6e, 0x11 },
1690 { 0x6f, 0x9f },
1691 /* "9e for advance AWB" */
1692 { 0x6a, 0x40 },
1693 { OV7670_REG_BLUE, 0x40 },
1694 { OV7670_REG_RED, 0x60 },
1695 { OV7670_REG_COM8, OV7670_COM8_FASTAEC
1696 | OV7670_COM8_AECSTEP
1697 | OV7670_COM8_BFILT
1698 | OV7670_COM8_AGC
1699 | OV7670_COM8_AEC
1700 | OV7670_COM8_AWB },
1701
1702/* Matrix coefficients */
1703 { 0x4f, 0x80 },
1704 { 0x50, 0x80 },
ac40b1fa 1705 { 0x51, 0x00 },
4202f71c
JFM		 1706 { 0x52, 0x22 },
1707 { 0x53, 0x5e },
1708 { 0x54, 0x80 },
1709 { 0x58, 0x9e },
1710
1711 { OV7670_REG_COM16, OV7670_COM16_AWBGAIN },
ac40b1fa 1712 { OV7670_REG_EDGE, 0x00 },
4202f71c
JFM		 1713 { 0x75, 0x05 },
1714 { 0x76, 0xe1 },
ac40b1fa 1715 { 0x4c, 0x00 },
4202f71c
JFM		 1716 { 0x77, 0x01 },
1717 { OV7670_REG_COM13, OV7670_COM13_GAMMA
1718 | OV7670_COM13_UVSAT
1719 | 2}, /* was 3 */
1720 { 0x4b, 0x09 },
1721 { 0xc9, 0x60 },
1722 { OV7670_REG_COM16, 0x38 },
1723 { 0x56, 0x40 },
1724
1725 { 0x34, 0x11 },
1726 { OV7670_REG_COM11, OV7670_COM11_EXP|OV7670_COM11_HZAUTO },
1727 { 0xa4, 0x88 },
ac40b1fa 1728 { 0x96, 0x00 },
4202f71c
JFM		 1729 { 0x97, 0x30 },
1730 { 0x98, 0x20 },
1731 { 0x99, 0x30 },
1732 { 0x9a, 0x84 },
1733 { 0x9b, 0x29 },
1734 { 0x9c, 0x03 },
1735 { 0x9d, 0x4c },
1736 { 0x9e, 0x3f },
1737 { 0x78, 0x04 },
1738
1739/* Extra-weird stuff. Some sort of multiplexor register */
1740 { 0x79, 0x01 },
1741 { 0xc8, 0xf0 },
1742 { 0x79, 0x0f },
1743 { 0xc8, 0x00 },
1744 { 0x79, 0x10 },
1745 { 0xc8, 0x7e },
1746 { 0x79, 0x0a },
1747 { 0xc8, 0x80 },
1748 { 0x79, 0x0b },
1749 { 0xc8, 0x01 },
1750 { 0x79, 0x0c },
1751 { 0xc8, 0x0f },
1752 { 0x79, 0x0d },
1753 { 0xc8, 0x20 },
1754 { 0x79, 0x09 },
1755 { 0xc8, 0x80 },
1756 { 0x79, 0x02 },
1757 { 0xc8, 0xc0 },
1758 { 0x79, 0x03 },
1759 { 0xc8, 0x40 },
1760 { 0x79, 0x05 },
1761 { 0xc8, 0x30 },
1762 { 0x79, 0x26 },
1763};
1764
1765static const struct ov_i2c_regvals norm_8610[] = {
1766 { 0x12, 0x80 },
1767 { 0x00, 0x00 },
1768 { 0x01, 0x80 },
1769 { 0x02, 0x80 },
1770 { 0x03, 0xc0 },
1771 { 0x04, 0x30 },
1772 { 0x05, 0x30 }, /* was 0x10, new from windrv 090403 */
1773 { 0x06, 0x70 }, /* was 0x80, new from windrv 090403 */
1774 { 0x0a, 0x86 },
1775 { 0x0b, 0xb0 },
1776 { 0x0c, 0x20 },
1777 { 0x0d, 0x20 },
1778 { 0x11, 0x01 },
1779 { 0x12, 0x25 },
1780 { 0x13, 0x01 },
1781 { 0x14, 0x04 },
1782 { 0x15, 0x01 }, /* Lin and Win think different about UV order */
1783 { 0x16, 0x03 },
1784 { 0x17, 0x38 }, /* was 0x2f, new from windrv 090403 */
1785 { 0x18, 0xea }, /* was 0xcf, new from windrv 090403 */
1786 { 0x19, 0x02 }, /* was 0x06, new from windrv 090403 */
1787 { 0x1a, 0xf5 },
1788 { 0x1b, 0x00 },
1789 { 0x20, 0xd0 }, /* was 0x90, new from windrv 090403 */
1790 { 0x23, 0xc0 }, /* was 0x00, new from windrv 090403 */
1791 { 0x24, 0x30 }, /* was 0x1d, new from windrv 090403 */
1792 { 0x25, 0x50 }, /* was 0x57, new from windrv 090403 */
1793 { 0x26, 0xa2 },
1794 { 0x27, 0xea },
1795 { 0x28, 0x00 },
1796 { 0x29, 0x00 },
1797 { 0x2a, 0x80 },
1798 { 0x2b, 0xc8 }, /* was 0xcc, new from windrv 090403 */
1799 { 0x2c, 0xac },
1800 { 0x2d, 0x45 }, /* was 0xd5, new from windrv 090403 */
1801 { 0x2e, 0x80 },
1802 { 0x2f, 0x14 }, /* was 0x01, new from windrv 090403 */
1803 { 0x4c, 0x00 },
1804 { 0x4d, 0x30 }, /* was 0x10, new from windrv 090403 */
1805 { 0x60, 0x02 }, /* was 0x01, new from windrv 090403 */
1806 { 0x61, 0x00 }, /* was 0x09, new from windrv 090403 */
1807 { 0x62, 0x5f }, /* was 0xd7, new from windrv 090403 */
1808 { 0x63, 0xff },
1809 { 0x64, 0x53 }, /* new windrv 090403 says 0x57,
1810 * maybe thats wrong */
1811 { 0x65, 0x00 },
1812 { 0x66, 0x55 },
1813 { 0x67, 0xb0 },
1814 { 0x68, 0xc0 }, /* was 0xaf, new from windrv 090403 */
1815 { 0x69, 0x02 },
1816 { 0x6a, 0x22 },
1817 { 0x6b, 0x00 },
1818 { 0x6c, 0x99 }, /* was 0x80, old windrv says 0x00, but
1819 * deleting bit7 colors the first images red */
1820 { 0x6d, 0x11 }, /* was 0x00, new from windrv 090403 */
1821 { 0x6e, 0x11 }, /* was 0x00, new from windrv 090403 */
1822 { 0x6f, 0x01 },
1823 { 0x70, 0x8b },
1824 { 0x71, 0x00 },
1825 { 0x72, 0x14 },
1826 { 0x73, 0x54 },
1827 { 0x74, 0x00 },/* 0x60? - was 0x00, new from windrv 090403 */
1828 { 0x75, 0x0e },
1829 { 0x76, 0x02 }, /* was 0x02, new from windrv 090403 */
1830 { 0x77, 0xff },
1831 { 0x78, 0x80 },
1832 { 0x79, 0x80 },
1833 { 0x7a, 0x80 },
1834 { 0x7b, 0x10 }, /* was 0x13, new from windrv 090403 */
1835 { 0x7c, 0x00 },
1836 { 0x7d, 0x08 }, /* was 0x09, new from windrv 090403 */
1837 { 0x7e, 0x08 }, /* was 0xc0, new from windrv 090403 */
1838 { 0x7f, 0xfb },
1839 { 0x80, 0x28 },
1840 { 0x81, 0x00 },
1841 { 0x82, 0x23 },
1842 { 0x83, 0x0b },
1843 { 0x84, 0x00 },
1844 { 0x85, 0x62 }, /* was 0x61, new from windrv 090403 */
1845 { 0x86, 0xc9 },
1846 { 0x87, 0x00 },
1847 { 0x88, 0x00 },
1848 { 0x89, 0x01 },
1849 { 0x12, 0x20 },
1850 { 0x12, 0x25 }, /* was 0x24, new from windrv 090403 */
1851};
1852
6a7eba24
JFM		 1853static unsigned char ov7670_abs_to_sm(unsigned char v)
1854{
1855 if (v > 127)
1856 return v & 0x7f;
1857 return (128 - v) | 0x80;
1858}
1859
1860/* Write a OV519 register */
a511ba94 1861static int reg_w(struct sd *sd, __u16 index, __u16 value)
6a7eba24 1862{
a511ba94 1863 int ret, req = 0;
b46aaa02
HG		 1864
1865 switch (sd->bridge) {
1866 case BRIDGE_OV511:
1867 case BRIDGE_OV511PLUS:
1868 req = 2;
1869 break;
1870 case BRIDGE_OVFX2:
a511ba94
HG		 1871 req = 0x0a;
1872 /* fall through */
1873 case BRIDGE_W9968CF:
b46aaa02
HG		 1874 ret = usb_control_msg(sd->gspca_dev.dev,
1875 usb_sndctrlpipe(sd->gspca_dev.dev, 0),
a511ba94 1876 req,
b46aaa02 1877 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
a511ba94 1878 value, index, NULL, 0, 500);
b46aaa02
HG		 1879 goto leave;
1880 default:
1881 req = 1;
1882 }
6a7eba24 1883
739570bb 1884 sd->gspca_dev.usb_buf[0] = value;
6a7eba24
JFM		 1885 ret = usb_control_msg(sd->gspca_dev.dev,
1886 usb_sndctrlpipe(sd->gspca_dev.dev, 0),
49809d6a 1887 req,
6a7eba24
JFM		 1888 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
1889 0, index,
739570bb 1890 sd->gspca_dev.usb_buf, 1, 500);
b46aaa02 1891leave:
a511ba94
HG		 1892 if (ret < 0) {
1893 PDEBUG(D_ERR, "Write reg 0x%04x -> [0x%02x] failed",
1894 value, index);
1895 return ret;
1896 }
1897
1898 PDEBUG(D_USBO, "Write reg 0x%04x -> [0x%02x]", value, index);
1899 return 0;
6a7eba24
JFM		 1900}
1901
a511ba94 1902/* Read from a OV519 register, note not valid for the w9968cf!! */
6a7eba24
JFM		 1903/* returns: negative is error, pos or zero is data */
1904static int reg_r(struct sd *sd, __u16 index)
1905{
1906 int ret;
b46aaa02
HG		 1907 int req;
1908
1909 switch (sd->bridge) {
1910 case BRIDGE_OV511:
1911 case BRIDGE_OV511PLUS:
1912 req = 3;
1913 break;
1914 case BRIDGE_OVFX2:
1915 req = 0x0b;
1916 break;
1917 default:
1918 req = 1;
1919 }
6a7eba24
JFM		 1920
1921 ret = usb_control_msg(sd->gspca_dev.dev,
1922 usb_rcvctrlpipe(sd->gspca_dev.dev, 0),
49809d6a 1923 req,
6a7eba24 1924 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
739570bb 1925 0, index, sd->gspca_dev.usb_buf, 1, 500);
6a7eba24 1926
a511ba94 1927 if (ret >= 0) {
739570bb 1928 ret = sd->gspca_dev.usb_buf[0];
a511ba94
HG		 1929 PDEBUG(D_USBI, "Read reg [0x%02X] -> 0x%04X", index, ret);
1930 } else
6a7eba24 1931 PDEBUG(D_ERR, "Read reg [0x%02x] failed", index);
a511ba94 1932
6a7eba24
JFM		 1933 return ret;
1934}
1935
1936/* Read 8 values from a OV519 register */
1937static int reg_r8(struct sd *sd,
a5ae2062 1938 __u16 index)
6a7eba24
JFM		 1939{
1940 int ret;
6a7eba24
JFM		 1941
1942 ret = usb_control_msg(sd->gspca_dev.dev,
1943 usb_rcvctrlpipe(sd->gspca_dev.dev, 0),
1944 1, /* REQ_IO */
1945 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
739570bb 1946 0, index, sd->gspca_dev.usb_buf, 8, 500);
6a7eba24
JFM		 1947
1948 if (ret >= 0)
739570bb 1949 ret = sd->gspca_dev.usb_buf[0];
6a7eba24
JFM		 1950 else
1951 PDEBUG(D_ERR, "Read reg 8 [0x%02x] failed", index);
a511ba94 1952
6a7eba24
JFM		 1953 return ret;
1954}
1955
1956/*
1957 * Writes bits at positions specified by mask to an OV51x reg. Bits that are in
1958 * the same position as 1's in "mask" are cleared and set to "value". Bits
1959 * that are in the same position as 0's in "mask" are preserved, regardless
1960 * of their respective state in "value".
1961 */
1962static int reg_w_mask(struct sd *sd,
1963 __u16 index,
1964 __u8 value,
1965 __u8 mask)
1966{
1967 int ret;
1968 __u8 oldval;
1969
1970 if (mask != 0xff) {
1971 value &= mask; /* Enforce mask on value */
1972 ret = reg_r(sd, index);
1973 if (ret < 0)
1974 return ret;
1975
1976 oldval = ret & ~mask; /* Clear the masked bits */
1977 value |= oldval; /* Set the desired bits */
1978 }
1979 return reg_w(sd, index, value);
1980}
1981
49809d6a
HG		 1982/*
1983 * Writes multiple (n) byte value to a single register. Only valid with certain
1984 * registers (0x30 and 0xc4 - 0xce).
1985 */
1986static int ov518_reg_w32(struct sd *sd, __u16 index, u32 value, int n)
1987{
1988 int ret;
1989
83955556 1990 *((__le32 *) sd->gspca_dev.usb_buf) = __cpu_to_le32(value);
49809d6a
HG		 1991
1992 ret = usb_control_msg(sd->gspca_dev.dev,
1993 usb_sndctrlpipe(sd->gspca_dev.dev, 0),
1994 1 /* REG_IO */,
1995 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
1996 0, index,
1997 sd->gspca_dev.usb_buf, n, 500);
a511ba94 1998 if (ret < 0) {
49809d6a 1999 PDEBUG(D_ERR, "Write reg32 [%02x] %08x failed", index, value);
a511ba94
HG		 2000 return ret;
2001 }
2002
2003 return 0;
49809d6a
HG		 2004}
2005
1876bb92
HG		 2006static int ov511_i2c_w(struct sd *sd, __u8 reg, __u8 value)
2007{
2008 int rc, retries;
2009
2010 PDEBUG(D_USBO, "i2c 0x%02x -> [0x%02x]", value, reg);
2011
2012 /* Three byte write cycle */
2013 for (retries = 6; ; ) {
2014 /* Select camera register */
2015 rc = reg_w(sd, R51x_I2C_SADDR_3, reg);
2016 if (rc < 0)
2017 return rc;
2018
2019 /* Write "value" to I2C data port of OV511 */
2020 rc = reg_w(sd, R51x_I2C_DATA, value);
2021 if (rc < 0)
2022 return rc;
2023
2024 /* Initiate 3-byte write cycle */
2025 rc = reg_w(sd, R511_I2C_CTL, 0x01);
2026 if (rc < 0)
2027 return rc;
2028
83955556 2029 do {
1876bb92 2030 rc = reg_r(sd, R511_I2C_CTL);
83955556 2031 } while (rc > 0 && ((rc & 1) == 0)); /* Retry until idle */
1876bb92
HG		 2032
2033 if (rc < 0)
2034 return rc;
2035
2036 if ((rc & 2) == 0) /* Ack? */
2037 break;
2038 if (--retries < 0) {
2039 PDEBUG(D_USBO, "i2c write retries exhausted");
2040 return -1;
2041 }
2042 }
2043
2044 return 0;
2045}
2046
2047static int ov511_i2c_r(struct sd *sd, __u8 reg)
2048{
2049 int rc, value, retries;
2050
2051 /* Two byte write cycle */
2052 for (retries = 6; ; ) {
2053 /* Select camera register */
2054 rc = reg_w(sd, R51x_I2C_SADDR_2, reg);
2055 if (rc < 0)
2056 return rc;
2057
2058 /* Initiate 2-byte write cycle */
2059 rc = reg_w(sd, R511_I2C_CTL, 0x03);
2060 if (rc < 0)
2061 return rc;
2062
83955556 2063 do {
1876bb92 2064 rc = reg_r(sd, R511_I2C_CTL);
83955556 2065 } while (rc > 0 && ((rc & 1) == 0)); /* Retry until idle */
1876bb92
HG		 2066
2067 if (rc < 0)
2068 return rc;
2069
2070 if ((rc & 2) == 0) /* Ack? */
2071 break;
2072
2073 /* I2C abort */
2074 reg_w(sd, R511_I2C_CTL, 0x10);
2075
2076 if (--retries < 0) {
2077 PDEBUG(D_USBI, "i2c write retries exhausted");
2078 return -1;
2079 }
2080 }
2081
2082 /* Two byte read cycle */
2083 for (retries = 6; ; ) {
2084 /* Initiate 2-byte read cycle */
2085 rc = reg_w(sd, R511_I2C_CTL, 0x05);
2086 if (rc < 0)
2087 return rc;
2088
83955556 2089 do {
1876bb92 2090 rc = reg_r(sd, R511_I2C_CTL);
83955556 2091 } while (rc > 0 && ((rc & 1) == 0)); /* Retry until idle */
1876bb92
HG		 2092
2093 if (rc < 0)
2094 return rc;
2095
2096 if ((rc & 2) == 0) /* Ack? */
2097 break;
2098
2099 /* I2C abort */
2100 rc = reg_w(sd, R511_I2C_CTL, 0x10);
2101 if (rc < 0)
2102 return rc;
2103
2104 if (--retries < 0) {
2105 PDEBUG(D_USBI, "i2c read retries exhausted");
2106 return -1;
2107 }
2108 }
2109
2110 value = reg_r(sd, R51x_I2C_DATA);
2111
2112 PDEBUG(D_USBI, "i2c [0x%02X] -> 0x%02X", reg, value);
2113
2114 /* This is needed to make i2c_w() work */
2115 rc = reg_w(sd, R511_I2C_CTL, 0x05);
2116 if (rc < 0)
2117 return rc;
2118
2119 return value;
2120}
49809d6a 2121
6a7eba24
JFM		 2122/*
2123 * The OV518 I2C I/O procedure is different, hence, this function.
2124 * This is normally only called from i2c_w(). Note that this function
2125 * always succeeds regardless of whether the sensor is present and working.
2126 */
1876bb92 2127static int ov518_i2c_w(struct sd *sd,
6a7eba24
JFM		 2128 __u8 reg,
2129 __u8 value)
2130{
2131 int rc;
2132
2133 PDEBUG(D_USBO, "i2c 0x%02x -> [0x%02x]", value, reg);
2134
2135 /* Select camera register */
2136 rc = reg_w(sd, R51x_I2C_SADDR_3, reg);
2137 if (rc < 0)
2138 return rc;
2139
2140 /* Write "value" to I2C data port of OV511 */
2141 rc = reg_w(sd, R51x_I2C_DATA, value);
2142 if (rc < 0)
2143 return rc;
2144
2145 /* Initiate 3-byte write cycle */
2146 rc = reg_w(sd, R518_I2C_CTL, 0x01);
ac40b1fa
JFM		 2147 if (rc < 0)
2148 return rc;
6a7eba24
JFM		 2149
2150 /* wait for write complete */
2151 msleep(4);
6a7eba24
JFM		 2152 return reg_r8(sd, R518_I2C_CTL);
2153}
2154
2155/*
2156 * returns: negative is error, pos or zero is data
2157 *
2158 * The OV518 I2C I/O procedure is different, hence, this function.
2159 * This is normally only called from i2c_r(). Note that this function
2160 * always succeeds regardless of whether the sensor is present and working.
2161 */
1876bb92 2162static int ov518_i2c_r(struct sd *sd, __u8 reg)
6a7eba24
JFM		 2163{
2164 int rc, value;
2165
2166 /* Select camera register */
2167 rc = reg_w(sd, R51x_I2C_SADDR_2, reg);
2168 if (rc < 0)
2169 return rc;
2170
2171 /* Initiate 2-byte write cycle */
2172 rc = reg_w(sd, R518_I2C_CTL, 0x03);
2173 if (rc < 0)
2174 return rc;
2175
2176 /* Initiate 2-byte read cycle */
2177 rc = reg_w(sd, R518_I2C_CTL, 0x05);
2178 if (rc < 0)
2179 return rc;
2180 value = reg_r(sd, R51x_I2C_DATA);
2181 PDEBUG(D_USBI, "i2c [0x%02X] -> 0x%02X", reg, value);
2182 return value;
2183}
2184
b46aaa02
HG		 2185static int ovfx2_i2c_w(struct sd *sd, __u8 reg, __u8 value)
2186{
2187 int ret;
2188
2189 ret = usb_control_msg(sd->gspca_dev.dev,
2190 usb_sndctrlpipe(sd->gspca_dev.dev, 0),
2191 0x02,
2192 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
2193 (__u16)value, (__u16)reg, NULL, 0, 500);
2194
a511ba94 2195 if (ret < 0) {
b46aaa02 2196 PDEBUG(D_ERR, "i2c 0x%02x -> [0x%02x] failed", value, reg);
a511ba94
HG		 2197 return ret;
2198 }
b46aaa02 2199
a511ba94
HG		 2200 PDEBUG(D_USBO, "i2c 0x%02x -> [0x%02x]", value, reg);
2201 return 0;
b46aaa02
HG		 2202}
2203
2204static int ovfx2_i2c_r(struct sd *sd, __u8 reg)
2205{
2206 int ret;
2207
2208 ret = usb_control_msg(sd->gspca_dev.dev,
2209 usb_rcvctrlpipe(sd->gspca_dev.dev, 0),
2210 0x03,
2211 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
2212 0, (__u16)reg, sd->gspca_dev.usb_buf, 1, 500);
2213
2214 if (ret >= 0) {
2215 ret = sd->gspca_dev.usb_buf[0];
2216 PDEBUG(D_USBI, "i2c [0x%02X] -> 0x%02X", reg, ret);
2217 } else
2218 PDEBUG(D_ERR, "i2c read [0x%02x] failed", reg);
2219
2220 return ret;
2221}
2222
1876bb92
HG		 2223static int i2c_w(struct sd *sd, __u8 reg, __u8 value)
2224{
fb1f9020
HG		 2225 int ret = -1;
2226
2227 if (sd->sensor_reg_cache[reg] == value)
2228 return 0;
2229
1876bb92
HG		 2230 switch (sd->bridge) {
2231 case BRIDGE_OV511:
2232 case BRIDGE_OV511PLUS:
fb1f9020
HG		 2233 ret = ov511_i2c_w(sd, reg, value);
2234 break;
1876bb92
HG		 2235 case BRIDGE_OV518:
2236 case BRIDGE_OV518PLUS:
2237 case BRIDGE_OV519:
fb1f9020
HG		 2238 ret = ov518_i2c_w(sd, reg, value);
2239 break;
b46aaa02 2240 case BRIDGE_OVFX2:
fb1f9020
HG		 2241 ret = ovfx2_i2c_w(sd, reg, value);
2242 break;
a511ba94 2243 case BRIDGE_W9968CF:
fb1f9020
HG		 2244 ret = w9968cf_i2c_w(sd, reg, value);
2245 break;
1876bb92 2246 }
fb1f9020
HG		 2247
2248 if (ret >= 0) {
2249 /* Up on sensor reset empty the register cache */
2250 if (reg == 0x12 && (value & 0x80))
2251 memset(sd->sensor_reg_cache, -1,
2252 sizeof(sd->sensor_reg_cache));
2253 else
2254 sd->sensor_reg_cache[reg] = value;
2255 }
2256
2257 return ret;
1876bb92
HG		 2258}
2259
2260static int i2c_r(struct sd *sd, __u8 reg)
2261{
8394bcf3 2262 int ret = -1;
fb1f9020
HG		 2263
2264 if (sd->sensor_reg_cache[reg] != -1)
2265 return sd->sensor_reg_cache[reg];
2266
1876bb92
HG		 2267 switch (sd->bridge) {
2268 case BRIDGE_OV511:
2269 case BRIDGE_OV511PLUS:
fb1f9020
HG		 2270 ret = ov511_i2c_r(sd, reg);
2271 break;
1876bb92
HG		 2272 case BRIDGE_OV518:
2273 case BRIDGE_OV518PLUS:
2274 case BRIDGE_OV519:
fb1f9020
HG		 2275 ret = ov518_i2c_r(sd, reg);
2276 break;
b46aaa02 2277 case BRIDGE_OVFX2:
fb1f9020
HG		 2278 ret = ovfx2_i2c_r(sd, reg);
2279 break;
a511ba94 2280 case BRIDGE_W9968CF:
fb1f9020
HG		 2281 ret = w9968cf_i2c_r(sd, reg);
2282 break;
1876bb92 2283 }
fb1f9020
HG		 2284
2285 if (ret >= 0)
2286 sd->sensor_reg_cache[reg] = ret;
2287
2288 return ret;
1876bb92
HG		 2289}
2290
6a7eba24
JFM		 2291/* Writes bits at positions specified by mask to an I2C reg. Bits that are in
2292 * the same position as 1's in "mask" are cleared and set to "value". Bits
2293 * that are in the same position as 0's in "mask" are preserved, regardless
2294 * of their respective state in "value".
2295 */
2296static int i2c_w_mask(struct sd *sd,
2297 __u8 reg,
2298 __u8 value,
2299 __u8 mask)
2300{
2301 int rc;
2302 __u8 oldval;
2303
2304 value &= mask; /* Enforce mask on value */
2305 rc = i2c_r(sd, reg);
2306 if (rc < 0)
2307 return rc;
2308 oldval = rc & ~mask; /* Clear the masked bits */
2309 value |= oldval; /* Set the desired bits */
2310 return i2c_w(sd, reg, value);
2311}
2312
2313/* Temporarily stops OV511 from functioning. Must do this before changing
2314 * registers while the camera is streaming */
2315static inline int ov51x_stop(struct sd *sd)
2316{
2317 PDEBUG(D_STREAM, "stopping");
2318 sd->stopped = 1;
49809d6a
HG		 2319 switch (sd->bridge) {
2320 case BRIDGE_OV511:
2321 case BRIDGE_OV511PLUS:
2322 return reg_w(sd, R51x_SYS_RESET, 0x3d);
2323 case BRIDGE_OV518:
2324 case BRIDGE_OV518PLUS:
2325 return reg_w_mask(sd, R51x_SYS_RESET, 0x3a, 0x3a);
2326 case BRIDGE_OV519:
2327 return reg_w(sd, OV519_SYS_RESET1, 0x0f);
b46aaa02
HG		 2328 case BRIDGE_OVFX2:
2329 return reg_w_mask(sd, 0x0f, 0x00, 0x02);
a511ba94 2330 case BRIDGE_W9968CF:
79b35902 2331 return reg_w(sd, 0x3c, 0x0a05); /* stop USB transfer */
49809d6a
HG		 2332 }
2333
2334 return 0;
6a7eba24
JFM		 2335}
2336
2337/* Restarts OV511 after ov511_stop() is called. Has no effect if it is not
2338 * actually stopped (for performance). */
2339static inline int ov51x_restart(struct sd *sd)
2340{
49809d6a
HG		 2341 int rc;
2342
6a7eba24
JFM		 2343 PDEBUG(D_STREAM, "restarting");
2344 if (!sd->stopped)
2345 return 0;
2346 sd->stopped = 0;
2347
2348 /* Reinitialize the stream */
49809d6a
HG		 2349 switch (sd->bridge) {
2350 case BRIDGE_OV511:
2351 case BRIDGE_OV511PLUS:
2352 return reg_w(sd, R51x_SYS_RESET, 0x00);
2353 case BRIDGE_OV518:
2354 case BRIDGE_OV518PLUS:
2355 rc = reg_w(sd, 0x2f, 0x80);
2356 if (rc < 0)
2357 return rc;
2358 return reg_w(sd, R51x_SYS_RESET, 0x00);
2359 case BRIDGE_OV519:
2360 return reg_w(sd, OV519_SYS_RESET1, 0x00);
b46aaa02
HG		 2361 case BRIDGE_OVFX2:
2362 return reg_w_mask(sd, 0x0f, 0x02, 0x02);
a511ba94
HG		 2363 case BRIDGE_W9968CF:
2364 return reg_w(sd, 0x3c, 0x8a05); /* USB FIFO enable */
49809d6a
HG		 2365 }
2366
2367 return 0;
6a7eba24
JFM		 2368}
2369
229bb7dc
HG		 2370static int ov51x_set_slave_ids(struct sd *sd, __u8 slave);
2371
6a7eba24
JFM		 2372/* This does an initial reset of an OmniVision sensor and ensures that I2C
2373 * is synchronized. Returns <0 on failure.
2374 */
229bb7dc 2375static int init_ov_sensor(struct sd *sd, __u8 slave)
6a7eba24 2376{
ac40b1fa 2377 int i;
6a7eba24 2378
229bb7dc
HG		 2379 if (ov51x_set_slave_ids(sd, slave) < 0)
2380 return -EIO;
2381
6a7eba24
JFM		 2382 /* Reset the sensor */
2383 if (i2c_w(sd, 0x12, 0x80) < 0)
2384 return -EIO;
2385
2386 /* Wait for it to initialize */
2387 msleep(150);
2388
ac40b1fa 2389 for (i = 0; i < i2c_detect_tries; i++) {
6a7eba24
JFM		 2390 if (i2c_r(sd, OV7610_REG_ID_HIGH) == 0x7f &&
2391 i2c_r(sd, OV7610_REG_ID_LOW) == 0xa2) {
ac40b1fa
JFM		 2392 PDEBUG(D_PROBE, "I2C synced in %d attempt(s)", i);
2393 return 0;
6a7eba24
JFM		 2394 }
2395
2396 /* Reset the sensor */
2397 if (i2c_w(sd, 0x12, 0x80) < 0)
2398 return -EIO;
2399 /* Wait for it to initialize */
2400 msleep(150);
2401 /* Dummy read to sync I2C */
2402 if (i2c_r(sd, 0x00) < 0)
2403 return -EIO;
2404 }
ac40b1fa 2405 return -EIO;
6a7eba24
JFM		 2406}
2407
6a7eba24
JFM		 2408/* Set the read and write slave IDs. The "slave" argument is the write slave,
2409 * and the read slave will be set to (slave + 1).
2410 * This should not be called from outside the i2c I/O functions.
2411 * Sets I2C read and write slave IDs. Returns <0 for error
2412 */
2413static int ov51x_set_slave_ids(struct sd *sd,
2414 __u8 slave)
2415{
2416 int rc;
2417
a511ba94
HG		 2418 switch (sd->bridge) {
2419 case BRIDGE_OVFX2:
b46aaa02 2420 return reg_w(sd, OVFX2_I2C_ADDR, slave);
a511ba94
HG		 2421 case BRIDGE_W9968CF:
2422 sd->sensor_addr = slave;
2423 return 0;
2424 }
b46aaa02 2425
6a7eba24
JFM		 2426 rc = reg_w(sd, R51x_I2C_W_SID, slave);
2427 if (rc < 0)
2428 return rc;
2429 return reg_w(sd, R51x_I2C_R_SID, slave + 1);
2430}
2431
6a7eba24 2432static int write_regvals(struct sd *sd,
a5ae2062 2433 const struct ov_regvals *regvals,
6a7eba24
JFM		 2434 int n)
2435{
2436 int rc;
2437
2438 while (--n >= 0) {
2439 rc = reg_w(sd, regvals->reg, regvals->val);
2440 if (rc < 0)
2441 return rc;
2442 regvals++;
2443 }
2444 return 0;
2445}
2446
2447static int write_i2c_regvals(struct sd *sd,
a5ae2062 2448 const struct ov_i2c_regvals *regvals,
6a7eba24
JFM		 2449 int n)
2450{
2451 int rc;
2452
2453 while (--n >= 0) {
2454 rc = i2c_w(sd, regvals->reg, regvals->val);
2455 if (rc < 0)
2456 return rc;
2457 regvals++;
2458 }
2459 return 0;
2460}
2461
2462/****************************************************************************
2463 *
2464 * OV511 and sensor configuration
2465 *
2466 ***************************************************************************/
2467
635118d5
HG		 2468/* This initializes the OV2x10 / OV3610 / OV3620 */
2469static int ov_hires_configure(struct sd *sd)
2470{
2471 int high, low;
2472
2473 if (sd->bridge != BRIDGE_OVFX2) {
2474 PDEBUG(D_ERR, "error hires sensors only supported with ovfx2");
2475 return -1;
2476 }
2477
2478 PDEBUG(D_PROBE, "starting ov hires configuration");
2479
2480 /* Detect sensor (sub)type */
2481 high = i2c_r(sd, 0x0a);
2482 low = i2c_r(sd, 0x0b);
2483 /* info("%x, %x", high, low); */
2484 if (high == 0x96 && low == 0x40) {
2485 PDEBUG(D_PROBE, "Sensor is an OV2610");
2486 sd->sensor = SEN_OV2610;
2487 } else if (high == 0x36 && (low & 0x0f) == 0x00) {
2488 PDEBUG(D_PROBE, "Sensor is an OV3610");
2489 sd->sensor = SEN_OV3610;
2490 } else {
2491 PDEBUG(D_ERR, "Error unknown sensor type: 0x%02x%02x",
2492 high, low);
2493 return -1;
2494 }
2495
2496 /* Set sensor-specific vars */
2497 return 0;
2498}
2499
2500
6a7eba24
JFM		 2501/* This initializes the OV8110, OV8610 sensor. The OV8110 uses
2502 * the same register settings as the OV8610, since they are very similar.
2503 */
2504static int ov8xx0_configure(struct sd *sd)
2505{
2506 int rc;
6a7eba24
JFM		 2507
2508 PDEBUG(D_PROBE, "starting ov8xx0 configuration");
2509
6a7eba24
JFM		 2510 /* Detect sensor (sub)type */
2511 rc = i2c_r(sd, OV7610_REG_COM_I);
2512 if (rc < 0) {
2513 PDEBUG(D_ERR, "Error detecting sensor type");
2514 return -1;
2515 }
2516 if ((rc & 3) == 1) {
6a7eba24
JFM		 2517 sd->sensor = SEN_OV8610;
2518 } else {
2519 PDEBUG(D_ERR, "Unknown image sensor version: %d", rc & 3);
2520 return -1;
2521 }
6a7eba24
JFM		 2522
2523 /* Set sensor-specific vars */
6a7eba24
JFM		 2524 return 0;
2525}
2526
2527/* This initializes the OV7610, OV7620, or OV76BE sensor. The OV76BE uses
2528 * the same register settings as the OV7610, since they are very similar.
2529 */
2530static int ov7xx0_configure(struct sd *sd)
2531{
2532 int rc, high, low;
2533
6a7eba24
JFM		 2534
2535 PDEBUG(D_PROBE, "starting OV7xx0 configuration");
2536
6a7eba24
JFM		 2537 /* Detect sensor (sub)type */
2538 rc = i2c_r(sd, OV7610_REG_COM_I);
2539
2540 /* add OV7670 here
2541 * it appears to be wrongly detected as a 7610 by default */
2542 if (rc < 0) {
2543 PDEBUG(D_ERR, "Error detecting sensor type");
2544 return -1;
2545 }
2546 if ((rc & 3) == 3) {
2547 /* quick hack to make OV7670s work */
2548 high = i2c_r(sd, 0x0a);
2549 low = i2c_r(sd, 0x0b);
2550 /* info("%x, %x", high, low); */
2551 if (high == 0x76 && low == 0x73) {
2552 PDEBUG(D_PROBE, "Sensor is an OV7670");
2553 sd->sensor = SEN_OV7670;
2554 } else {
2555 PDEBUG(D_PROBE, "Sensor is an OV7610");
2556 sd->sensor = SEN_OV7610;
2557 }
2558 } else if ((rc & 3) == 1) {
2559 /* I don't know what's different about the 76BE yet. */
b282d873 2560 if (i2c_r(sd, 0x15) & 1) {
6a7eba24 2561 PDEBUG(D_PROBE, "Sensor is an OV7620AE");
859cc470 2562 sd->sensor = SEN_OV7620AE;
b282d873 2563 } else {
6a7eba24 2564 PDEBUG(D_PROBE, "Sensor is an OV76BE");
b282d873
HG		 2565 sd->sensor = SEN_OV76BE;
2566 }
6a7eba24
JFM		 2567 } else if ((rc & 3) == 0) {
2568 /* try to read product id registers */
2569 high = i2c_r(sd, 0x0a);
2570 if (high < 0) {
2571 PDEBUG(D_ERR, "Error detecting camera chip PID");
2572 return high;
2573 }
2574 low = i2c_r(sd, 0x0b);
2575 if (low < 0) {
2576 PDEBUG(D_ERR, "Error detecting camera chip VER");
2577 return low;
2578 }
2579 if (high == 0x76) {
594f5b8b
JFM		 2580 switch (low) {
2581 case 0x30:
6a7eba24 2582 PDEBUG(D_PROBE, "Sensor is an OV7630/OV7635");
4202f71c
JFM		 2583 PDEBUG(D_ERR,
2584 "7630 is not supported by this driver");
2585 return -1;
594f5b8b 2586 case 0x40:
6a7eba24
JFM		 2587 PDEBUG(D_PROBE, "Sensor is an OV7645");
2588 sd->sensor = SEN_OV7640; /* FIXME */
594f5b8b
JFM		 2589 break;
2590 case 0x45:
6a7eba24
JFM		 2591 PDEBUG(D_PROBE, "Sensor is an OV7645B");
2592 sd->sensor = SEN_OV7640; /* FIXME */
594f5b8b
JFM		 2593 break;
2594 case 0x48:
6a7eba24 2595 PDEBUG(D_PROBE, "Sensor is an OV7648");
035d3a3d 2596 sd->sensor = SEN_OV7648;
594f5b8b
JFM		 2597 break;
2598 default:
2599 PDEBUG(D_PROBE, "Unknown sensor: 0x76%x", low);
6a7eba24
JFM		 2600 return -1;
2601 }
2602 } else {
2603 PDEBUG(D_PROBE, "Sensor is an OV7620");
2604 sd->sensor = SEN_OV7620;
2605 }
2606 } else {
2607 PDEBUG(D_ERR, "Unknown image sensor version: %d", rc & 3);
2608 return -1;
2609 }
2610
6a7eba24 2611 /* Set sensor-specific vars */
6a7eba24
JFM		 2612 return 0;
2613}
2614
2615/* This initializes the OV6620, OV6630, OV6630AE, or OV6630AF sensor. */
2616static int ov6xx0_configure(struct sd *sd)
2617{
2618 int rc;
4202f71c 2619 PDEBUG(D_PROBE, "starting OV6xx0 configuration");
6a7eba24
JFM		 2620
2621 /* Detect sensor (sub)type */
2622 rc = i2c_r(sd, OV7610_REG_COM_I);
2623 if (rc < 0) {
2624 PDEBUG(D_ERR, "Error detecting sensor type");
2625 return -1;
2626 }
2627
2628 /* Ugh. The first two bits are the version bits, but
2629 * the entire register value must be used. I guess OVT
2630 * underestimated how many variants they would make. */
594f5b8b
JFM		 2631 switch (rc) {
2632 case 0x00:
6a7eba24
JFM		 2633 sd->sensor = SEN_OV6630;
2634 PDEBUG(D_ERR,
2635 "WARNING: Sensor is an OV66308. Your camera may have");
2636 PDEBUG(D_ERR, "been misdetected in previous driver versions.");
594f5b8b
JFM		 2637 break;
2638 case 0x01:
6a7eba24 2639 sd->sensor = SEN_OV6620;
7d971373 2640 PDEBUG(D_PROBE, "Sensor is an OV6620");
594f5b8b
JFM		 2641 break;
2642 case 0x02:
6a7eba24
JFM		 2643 sd->sensor = SEN_OV6630;
2644 PDEBUG(D_PROBE, "Sensor is an OV66308AE");
594f5b8b
JFM		 2645 break;
2646 case 0x03:
7d971373 2647 sd->sensor = SEN_OV66308AF;
6a7eba24 2648 PDEBUG(D_PROBE, "Sensor is an OV66308AF");
594f5b8b
JFM		 2649 break;
2650 case 0x90:
6a7eba24
JFM		 2651 sd->sensor = SEN_OV6630;
2652 PDEBUG(D_ERR,
2653 "WARNING: Sensor is an OV66307. Your camera may have");
2654 PDEBUG(D_ERR, "been misdetected in previous driver versions.");
594f5b8b
JFM		 2655 break;
2656 default:
6a7eba24
JFM		 2657 PDEBUG(D_ERR, "FATAL: Unknown sensor version: 0x%02x", rc);
2658 return -1;
2659 }
2660
2661 /* Set sensor-specific vars */
594f5b8b 2662 sd->sif = 1;
6a7eba24 2663
6a7eba24
JFM		 2664 return 0;
2665}
2666
2667/* Turns on or off the LED. Only has an effect with OV511+/OV518(+)/OV519 */
2668static void ov51x_led_control(struct sd *sd, int on)
2669{
9e4d8258
HG		 2670 if (sd->invert_led)
2671 on = !on;
2672
49809d6a
HG		 2673 switch (sd->bridge) {
2674 /* OV511 has no LED control */
2675 case BRIDGE_OV511PLUS:
2676 reg_w(sd, R511_SYS_LED_CTL, on ? 1 : 0);
2677 break;
2678 case BRIDGE_OV518:
2679 case BRIDGE_OV518PLUS:
2680 reg_w_mask(sd, R518_GPIO_OUT, on ? 0x02 : 0x00, 0x02);
2681 break;
2682 case BRIDGE_OV519:
2683 reg_w_mask(sd, OV519_GPIO_DATA_OUT0, !on, 1); /* 0 / 1 */
2684 break;
2685 }
6a7eba24
JFM		 2686}
2687
1876bb92 2688static int ov51x_upload_quan_tables(struct sd *sd)
49809d6a 2689{
1876bb92
HG		 2690 const unsigned char yQuanTable511[] = {
2691 0, 1, 1, 2, 2, 3, 3, 4,
2692 1, 1, 1, 2, 2, 3, 4, 4,
2693 1, 1, 2, 2, 3, 4, 4, 4,
2694 2, 2, 2, 3, 4, 4, 4, 4,
2695 2, 2, 3, 4, 4, 5, 5, 5,
2696 3, 3, 4, 4, 5, 5, 5, 5,
2697 3, 4, 4, 4, 5, 5, 5, 5,
2698 4, 4, 4, 4, 5, 5, 5, 5
2699 };
2700
2701 const unsigned char uvQuanTable511[] = {
2702 0, 2, 2, 3, 4, 4, 4, 4,
2703 2, 2, 2, 4, 4, 4, 4, 4,
2704 2, 2, 3, 4, 4, 4, 4, 4,
2705 3, 4, 4, 4, 4, 4, 4, 4,
2706 4, 4, 4, 4, 4, 4, 4, 4,
2707 4, 4, 4, 4, 4, 4, 4, 4,
2708 4, 4, 4, 4, 4, 4, 4, 4,
2709 4, 4, 4, 4, 4, 4, 4, 4
2710 };
2711
2712 /* OV518 quantization tables are 8x4 (instead of 8x8) */
49809d6a
HG		 2713 const unsigned char yQuanTable518[] = {
2714 5, 4, 5, 6, 6, 7, 7, 7,
2715 5, 5, 5, 5, 6, 7, 7, 7,
2716 6, 6, 6, 6, 7, 7, 7, 8,
2717 7, 7, 6, 7, 7, 7, 8, 8
2718 };
2719
2720 const unsigned char uvQuanTable518[] = {
2721 6, 6, 6, 7, 7, 7, 7, 7,
2722 6, 6, 6, 7, 7, 7, 7, 7,
2723 6, 6, 6, 7, 7, 7, 7, 8,
2724 7, 7, 7, 7, 7, 7, 8, 8
2725 };
2726
1876bb92 2727 const unsigned char *pYTable, *pUVTable;
49809d6a 2728 unsigned char val0, val1;
1876bb92 2729 int i, size, rc, reg = R51x_COMP_LUT_BEGIN;
49809d6a
HG		 2730
2731 PDEBUG(D_PROBE, "Uploading quantization tables");
2732
1876bb92
HG		 2733 if (sd->bridge == BRIDGE_OV511 || sd->bridge == BRIDGE_OV511PLUS) {
2734 pYTable = yQuanTable511;
2735 pUVTable = uvQuanTable511;
2736 size = 32;
2737 } else {
2738 pYTable = yQuanTable518;
2739 pUVTable = uvQuanTable518;
2740 size = 16;
2741 }
2742
2743 for (i = 0; i < size; i++) {
49809d6a
HG		 2744 val0 = *pYTable++;
2745 val1 = *pYTable++;
2746 val0 &= 0x0f;
2747 val1 &= 0x0f;
2748 val0 |= val1 << 4;
2749 rc = reg_w(sd, reg, val0);
2750 if (rc < 0)
2751 return rc;
2752
2753 val0 = *pUVTable++;
2754 val1 = *pUVTable++;
2755 val0 &= 0x0f;
2756 val1 &= 0x0f;
2757 val0 |= val1 << 4;
1876bb92 2758 rc = reg_w(sd, reg + size, val0);
49809d6a
HG		 2759 if (rc < 0)
2760 return rc;
2761
2762 reg++;
2763 }
2764
2765 return 0;
2766}
2767
1876bb92
HG		 2768/* This initializes the OV511/OV511+ and the sensor */
2769static int ov511_configure(struct gspca_dev *gspca_dev)
2770{
2771 struct sd *sd = (struct sd *) gspca_dev;
2772 int rc;
2773
2774 /* For 511 and 511+ */
2775 const struct ov_regvals init_511[] = {
2776 { R51x_SYS_RESET, 0x7f },
2777 { R51x_SYS_INIT, 0x01 },
2778 { R51x_SYS_RESET, 0x7f },
2779 { R51x_SYS_INIT, 0x01 },
2780 { R51x_SYS_RESET, 0x3f },
2781 { R51x_SYS_INIT, 0x01 },
2782 { R51x_SYS_RESET, 0x3d },
2783 };
2784
2785 const struct ov_regvals norm_511[] = {
2786 { R511_DRAM_FLOW_CTL, 0x01 },
2787 { R51x_SYS_SNAP, 0x00 },
2788 { R51x_SYS_SNAP, 0x02 },
2789 { R51x_SYS_SNAP, 0x00 },
2790 { R511_FIFO_OPTS, 0x1f },
2791 { R511_COMP_EN, 0x00 },
2792 { R511_COMP_LUT_EN, 0x03 },
2793 };
2794
2795 const struct ov_regvals norm_511_p[] = {
2796 { R511_DRAM_FLOW_CTL, 0xff },
2797 { R51x_SYS_SNAP, 0x00 },
2798 { R51x_SYS_SNAP, 0x02 },
2799 { R51x_SYS_SNAP, 0x00 },
2800 { R511_FIFO_OPTS, 0xff },
2801 { R511_COMP_EN, 0x00 },
2802 { R511_COMP_LUT_EN, 0x03 },
2803 };
2804
2805 const struct ov_regvals compress_511[] = {
2806 { 0x70, 0x1f },
2807 { 0x71, 0x05 },
2808 { 0x72, 0x06 },
2809 { 0x73, 0x06 },
2810 { 0x74, 0x14 },
2811 { 0x75, 0x03 },
2812 { 0x76, 0x04 },
2813 { 0x77, 0x04 },
2814 };
2815
2816 PDEBUG(D_PROBE, "Device custom id %x", reg_r(sd, R51x_SYS_CUST_ID));
2817
2818 rc = write_regvals(sd, init_511, ARRAY_SIZE(init_511));
2819 if (rc < 0)
2820 return rc;
2821
2822 switch (sd->bridge) {
2823 case BRIDGE_OV511:
2824 rc = write_regvals(sd, norm_511, ARRAY_SIZE(norm_511));
2825 if (rc < 0)
2826 return rc;
2827 break;
2828 case BRIDGE_OV511PLUS:
2829 rc = write_regvals(sd, norm_511_p, ARRAY_SIZE(norm_511_p));
2830 if (rc < 0)
2831 return rc;
2832 break;
2833 }
2834
2835 /* Init compression */
2836 rc = write_regvals(sd, compress_511, ARRAY_SIZE(compress_511));
2837 if (rc < 0)
2838 return rc;
2839
2840 rc = ov51x_upload_quan_tables(sd);
2841 if (rc < 0) {
2842 PDEBUG(D_ERR, "Error uploading quantization tables");
2843 return rc;
2844 }
2845
2846 return 0;
2847}
2848
49809d6a
HG		 2849/* This initializes the OV518/OV518+ and the sensor */
2850static int ov518_configure(struct gspca_dev *gspca_dev)
6a7eba24
JFM		 2851{
2852 struct sd *sd = (struct sd *) gspca_dev;
49809d6a
HG		 2853 int rc;
2854
2855 /* For 518 and 518+ */
e080fcd9 2856 const struct ov_regvals init_518[] = {
49809d6a
HG		 2857 { R51x_SYS_RESET, 0x40 },
2858 { R51x_SYS_INIT, 0xe1 },
2859 { R51x_SYS_RESET, 0x3e },
2860 { R51x_SYS_INIT, 0xe1 },
2861 { R51x_SYS_RESET, 0x00 },
2862 { R51x_SYS_INIT, 0xe1 },
2863 { 0x46, 0x00 },
2864 { 0x5d, 0x03 },
2865 };
2866
e080fcd9 2867 const struct ov_regvals norm_518[] = {
49809d6a
HG		 2868 { R51x_SYS_SNAP, 0x02 }, /* Reset */
2869 { R51x_SYS_SNAP, 0x01 }, /* Enable */
2870 { 0x31, 0x0f },
2871 { 0x5d, 0x03 },
2872 { 0x24, 0x9f },
2873 { 0x25, 0x90 },
2874 { 0x20, 0x00 },
2875 { 0x51, 0x04 },
2876 { 0x71, 0x19 },
2877 { 0x2f, 0x80 },
2878 };
2879
e080fcd9 2880 const struct ov_regvals norm_518_p[] = {
49809d6a
HG		 2881 { R51x_SYS_SNAP, 0x02 }, /* Reset */
2882 { R51x_SYS_SNAP, 0x01 }, /* Enable */
2883 { 0x31, 0x0f },
2884 { 0x5d, 0x03 },
2885 { 0x24, 0x9f },
2886 { 0x25, 0x90 },
2887 { 0x20, 0x60 },
2888 { 0x51, 0x02 },
2889 { 0x71, 0x19 },
2890 { 0x40, 0xff },
2891 { 0x41, 0x42 },
2892 { 0x46, 0x00 },
2893 { 0x33, 0x04 },
2894 { 0x21, 0x19 },
2895 { 0x3f, 0x10 },
2896 { 0x2f, 0x80 },
2897 };
2898
2899 /* First 5 bits of custom ID reg are a revision ID on OV518 */
2900 PDEBUG(D_PROBE, "Device revision %d",
2901 0x1F & reg_r(sd, R51x_SYS_CUST_ID));
2902
2903 rc = write_regvals(sd, init_518, ARRAY_SIZE(init_518));
2904 if (rc < 0)
2905 return rc;
2906
2907 /* Set LED GPIO pin to output mode */
2908 rc = reg_w_mask(sd, R518_GPIO_CTL, 0x00, 0x02);
2909 if (rc < 0)
2910 return rc;
6a7eba24 2911
49809d6a
HG		 2912 switch (sd->bridge) {
2913 case BRIDGE_OV518:
2914 rc = write_regvals(sd, norm_518, ARRAY_SIZE(norm_518));
2915 if (rc < 0)
2916 return rc;
2917 break;
2918 case BRIDGE_OV518PLUS:
2919 rc = write_regvals(sd, norm_518_p, ARRAY_SIZE(norm_518_p));
2920 if (rc < 0)
2921 return rc;
2922 break;
2923 }
2924
1876bb92 2925 rc = ov51x_upload_quan_tables(sd);
49809d6a
HG		 2926 if (rc < 0) {
2927 PDEBUG(D_ERR, "Error uploading quantization tables");
2928 return rc;
2929 }
2930
2931 rc = reg_w(sd, 0x2f, 0x80);
2932 if (rc < 0)
2933 return rc;
2934
2935 return 0;
2936}
2937
2938static int ov519_configure(struct sd *sd)
2939{
a5ae2062 2940 static const struct ov_regvals init_519[] = {
6a7eba24 2941 { 0x5a, 0x6d }, /* EnableSystem */
6a7eba24
JFM		 2942 { 0x53, 0x9b },
2943 { 0x54, 0xff }, /* set bit2 to enable jpeg */
2944 { 0x5d, 0x03 },
2945 { 0x49, 0x01 },
2946 { 0x48, 0x00 },
2947 /* Set LED pin to output mode. Bit 4 must be cleared or sensor
2948 * detection will fail. This deserves further investigation. */
2949 { OV519_GPIO_IO_CTRL0, 0xee },
2950 { 0x51, 0x0f }, /* SetUsbInit */
2951 { 0x51, 0x00 },
2952 { 0x22, 0x00 },
2953 /* windows reads 0x55 at this point*/
2954 };
2955
49809d6a
HG		 2956 return write_regvals(sd, init_519, ARRAY_SIZE(init_519));
2957}
2958
b46aaa02
HG		 2959static int ovfx2_configure(struct sd *sd)
2960{
2961 static const struct ov_regvals init_fx2[] = {
2962 { 0x00, 0x60 },
2963 { 0x02, 0x01 },
2964 { 0x0f, 0x1d },
2965 { 0xe9, 0x82 },
2966 { 0xea, 0xc7 },
2967 { 0xeb, 0x10 },
2968 { 0xec, 0xf6 },
2969 };
2970
2971 sd->stopped = 1;
2972
2973 return write_regvals(sd, init_fx2, ARRAY_SIZE(init_fx2));
2974}
2975
49809d6a
HG		 2976/* this function is called at probe time */
2977static int sd_config(struct gspca_dev *gspca_dev,
2978 const struct usb_device_id *id)
2979{
2980 struct sd *sd = (struct sd *) gspca_dev;
b46aaa02 2981 struct cam *cam = &gspca_dev->cam;
49809d6a
HG		 2982 int ret = 0;
2983
9e4d8258
HG		 2984 sd->bridge = id->driver_info & BRIDGE_MASK;
2985 sd->invert_led = id->driver_info & BRIDGE_INVERT_LED;
49809d6a
HG		 2986
2987 switch (sd->bridge) {
1876bb92
HG		 2988 case BRIDGE_OV511:
2989 case BRIDGE_OV511PLUS:
2990 ret = ov511_configure(gspca_dev);
2991 break;
49809d6a
HG		 2992 case BRIDGE_OV518:
2993 case BRIDGE_OV518PLUS:
2994 ret = ov518_configure(gspca_dev);
2995 break;
2996 case BRIDGE_OV519:
2997 ret = ov519_configure(sd);
2998 break;
b46aaa02
HG		 2999 case BRIDGE_OVFX2:
3000 ret = ovfx2_configure(sd);
3001 cam->bulk_size = OVFX2_BULK_SIZE;
3002 cam->bulk_nurbs = MAX_NURBS;
3003 cam->bulk = 1;
3004 break;
a511ba94
HG		 3005 case BRIDGE_W9968CF:
3006 ret = w9968cf_configure(sd);
3007 cam->reverse_alts = 1;
3008 break;
49809d6a
HG		 3009 }
3010
3011 if (ret)
6a7eba24 3012 goto error;
49809d6a 3013
6a7eba24
JFM		 3014 ov51x_led_control(sd, 0); /* turn LED off */
3015
6a7eba24
JFM		 3016 /* The OV519 must be more aggressive about sensor detection since
3017 * I2C write will never fail if the sensor is not present. We have
3018 * to try to initialize the sensor to detect its presence */
229bb7dc
HG		 3019
3020 /* Test for 76xx */
3021 if (init_ov_sensor(sd, OV7xx0_SID) >= 0) {
4202f71c
JFM		 3022 if (ov7xx0_configure(sd) < 0) {
3023 PDEBUG(D_ERR, "Failed to configure OV7xx0");
3024 goto error;
3025 }
229bb7dc
HG		 3026 /* Test for 6xx0 */
3027 } else if (init_ov_sensor(sd, OV6xx0_SID) >= 0) {
3028 if (ov6xx0_configure(sd) < 0) {
3029 PDEBUG(D_ERR, "Failed to configure OV6xx0");
3030 goto error;
3031 }
3032 /* Test for 8xx0 */
3033 } else if (init_ov_sensor(sd, OV8xx0_SID) >= 0) {
3034 if (ov8xx0_configure(sd) < 0) {
3035 PDEBUG(D_ERR, "Failed to configure OV8xx0");
6a7eba24 3036 goto error;
6a7eba24 3037 }
635118d5
HG		 3038 /* Test for 3xxx / 2xxx */
3039 } else if (init_ov_sensor(sd, OV_HIRES_SID) >= 0) {
3040 if (ov_hires_configure(sd) < 0) {
3041 PDEBUG(D_ERR, "Failed to configure high res OV");
3042 goto error;
3043 }
229bb7dc
HG		 3044 } else {
3045 PDEBUG(D_ERR, "Can't determine sensor slave IDs");
3046 goto error;
6a7eba24
JFM		 3047 }
3048
49809d6a 3049 switch (sd->bridge) {
1876bb92
HG		 3050 case BRIDGE_OV511:
3051 case BRIDGE_OV511PLUS:
3052 if (!sd->sif) {
3053 cam->cam_mode = ov511_vga_mode;
3054 cam->nmodes = ARRAY_SIZE(ov511_vga_mode);
3055 } else {
3056 cam->cam_mode = ov511_sif_mode;
3057 cam->nmodes = ARRAY_SIZE(ov511_sif_mode);
3058 }
3059 break;
49809d6a
HG		 3060 case BRIDGE_OV518:
3061 case BRIDGE_OV518PLUS:
3062 if (!sd->sif) {
3063 cam->cam_mode = ov518_vga_mode;
3064 cam->nmodes = ARRAY_SIZE(ov518_vga_mode);
3065 } else {
3066 cam->cam_mode = ov518_sif_mode;
3067 cam->nmodes = ARRAY_SIZE(ov518_sif_mode);
3068 }
3069 break;
3070 case BRIDGE_OV519:
3071 if (!sd->sif) {
3072 cam->cam_mode = ov519_vga_mode;
3073 cam->nmodes = ARRAY_SIZE(ov519_vga_mode);
3074 } else {
3075 cam->cam_mode = ov519_sif_mode;
3076 cam->nmodes = ARRAY_SIZE(ov519_sif_mode);
3077 }
3078 break;
635118d5
HG		 3079 case BRIDGE_OVFX2:
3080 if (sd->sensor == SEN_OV2610) {
3081 cam->cam_mode = ovfx2_ov2610_mode;
3082 cam->nmodes = ARRAY_SIZE(ovfx2_ov2610_mode);
3083 } else if (sd->sensor == SEN_OV3610) {
3084 cam->cam_mode = ovfx2_ov3610_mode;
3085 cam->nmodes = ARRAY_SIZE(ovfx2_ov3610_mode);
3086 } else if (!sd->sif) {
3087 cam->cam_mode = ov519_vga_mode;
3088 cam->nmodes = ARRAY_SIZE(ov519_vga_mode);
3089 } else {
3090 cam->cam_mode = ov519_sif_mode;
3091 cam->nmodes = ARRAY_SIZE(ov519_sif_mode);
3092 }
3093 break;
a511ba94
HG		 3094 case BRIDGE_W9968CF:
3095 cam->cam_mode = w9968cf_vga_mode;
3096 cam->nmodes = ARRAY_SIZE(w9968cf_vga_mode);
79b35902
HG		 3097 if (sd->sif)
3098 cam->nmodes--;
a511ba94
HG		 3099
3100 /* w9968cf needs initialisation once the sensor is known */
3101 if (w9968cf_init(sd) < 0)
3102 goto error;
3103 break;
6a7eba24 3104 }
594f5b8b 3105 sd->brightness = BRIGHTNESS_DEF;
f5cee95c
HG		 3106 if (sd->sensor == SEN_OV6630 || sd->sensor == SEN_OV66308AF)
3107 sd->contrast = 200; /* The default is too low for the ov6630 */
3108 else
3109 sd->contrast = CONTRAST_DEF;
594f5b8b 3110 sd->colors = COLOR_DEF;
0cd6759d
JFM		 3111 sd->hflip = HFLIP_DEF;
3112 sd->vflip = VFLIP_DEF;
02ab18b0
HG		 3113 sd->autobrightness = AUTOBRIGHT_DEF;
3114 if (sd->sensor == SEN_OV7670) {
3115 sd->freq = OV7670_FREQ_DEF;
3116 gspca_dev->ctrl_dis = 1 << FREQ_IDX;
3117 } else {
3118 sd->freq = FREQ_DEF;
3119 gspca_dev->ctrl_dis = (1 << HFLIP_IDX) | (1 << VFLIP_IDX) |
3120 (1 << OV7670_FREQ_IDX);
3121 }
79b35902 3122 sd->quality = QUALITY_DEF;
035d3a3d 3123 if (sd->sensor == SEN_OV7640 ||
d02134dd
HG		 3124 sd->sensor == SEN_OV7648)
3125 gspca_dev->ctrl_dis |= (1 << AUTOBRIGHT_IDX) |
3126 (1 << CONTRAST_IDX);
3127 if (sd->sensor == SEN_OV7670)
02ab18b0
HG		 3128 gspca_dev->ctrl_dis |= 1 << AUTOBRIGHT_IDX;
3129 /* OV8610 Frequency filter control should work but needs testing */
3130 if (sd->sensor == SEN_OV8610)
3131 gspca_dev->ctrl_dis |= 1 << FREQ_IDX;
635118d5
HG		 3132 /* No controls for the OV2610/OV3610 */
3133 if (sd->sensor == SEN_OV2610 || sd->sensor == SEN_OV3610)
3134 gspca_dev->ctrl_dis |= 0xFF;
02ab18b0 3135
6a7eba24
JFM		 3136 return 0;
3137error:
3138 PDEBUG(D_ERR, "OV519 Config failed");
3139 return -EBUSY;
3140}
3141
012d6b02
JFM		 3142/* this function is called at probe and resume time */
3143static int sd_init(struct gspca_dev *gspca_dev)
6a7eba24 3144{
4202f71c
JFM		 3145 struct sd *sd = (struct sd *) gspca_dev;
3146
3147 /* initialize the sensor */
3148 switch (sd->sensor) {
635118d5
HG		 3149 case SEN_OV2610:
3150 if (write_i2c_regvals(sd, norm_2610, ARRAY_SIZE(norm_2610)))
3151 return -EIO;
3152 /* Enable autogain, autoexpo, awb, bandfilter */
3153 if (i2c_w_mask(sd, 0x13, 0x27, 0x27) < 0)
3154 return -EIO;
3155 break;
3156 case SEN_OV3610:
3157 if (write_i2c_regvals(sd, norm_3620b, ARRAY_SIZE(norm_3620b)))
3158 return -EIO;
3159 /* Enable autogain, autoexpo, awb, bandfilter */
3160 if (i2c_w_mask(sd, 0x13, 0x27, 0x27) < 0)
3161 return -EIO;
3162 break;
4202f71c
JFM		 3163 case SEN_OV6620:
3164 if (write_i2c_regvals(sd, norm_6x20, ARRAY_SIZE(norm_6x20)))
3165 return -EIO;
3166 break;
3167 case SEN_OV6630:
7d971373 3168 case SEN_OV66308AF:
4202f71c
JFM		 3169 if (write_i2c_regvals(sd, norm_6x30, ARRAY_SIZE(norm_6x30)))
3170 return -EIO;
3171 break;
3172 default:
3173/* case SEN_OV7610: */
3174/* case SEN_OV76BE: */
3175 if (write_i2c_regvals(sd, norm_7610, ARRAY_SIZE(norm_7610)))
3176 return -EIO;
ae49c404
HG		 3177 if (i2c_w_mask(sd, 0x0e, 0x00, 0x40))
3178 return -EIO;
4202f71c
JFM		 3179 break;
3180 case SEN_OV7620:
859cc470 3181 case SEN_OV7620AE:
4202f71c
JFM		 3182 if (write_i2c_regvals(sd, norm_7620, ARRAY_SIZE(norm_7620)))
3183 return -EIO;
3184 break;
3185 case SEN_OV7640:
035d3a3d 3186 case SEN_OV7648:
4202f71c
JFM		 3187 if (write_i2c_regvals(sd, norm_7640, ARRAY_SIZE(norm_7640)))
3188 return -EIO;
3189 break;
3190 case SEN_OV7670:
3191 if (write_i2c_regvals(sd, norm_7670, ARRAY_SIZE(norm_7670)))
3192 return -EIO;
3193 break;
3194 case SEN_OV8610:
3195 if (write_i2c_regvals(sd, norm_8610, ARRAY_SIZE(norm_8610)))
3196 return -EIO;
3197 break;
3198 }
6a7eba24
JFM		 3199 return 0;
3200}
3201
1876bb92
HG		 3202/* Set up the OV511/OV511+ with the given image parameters.
3203 *
3204 * Do not put any sensor-specific code in here (including I2C I/O functions)
3205 */
3206static int ov511_mode_init_regs(struct sd *sd)
3207{
3208 int hsegs, vsegs, packet_size, fps, needed;
3209 int interlaced = 0;
3210 struct usb_host_interface *alt;
3211 struct usb_interface *intf;
3212
3213 intf = usb_ifnum_to_if(sd->gspca_dev.dev, sd->gspca_dev.iface);
3214 alt = usb_altnum_to_altsetting(intf, sd->gspca_dev.alt);
3215 if (!alt) {
3216 PDEBUG(D_ERR, "Couldn't get altsetting");
3217 return -EIO;
3218 }
3219
3220 packet_size = le16_to_cpu(alt->endpoint[0].desc.wMaxPacketSize);
3221 reg_w(sd, R51x_FIFO_PSIZE, packet_size >> 5);
3222
3223 reg_w(sd, R511_CAM_UV_EN, 0x01);
3224 reg_w(sd, R511_SNAP_UV_EN, 0x01);
3225 reg_w(sd, R511_SNAP_OPTS, 0x03);
3226
3227 /* Here I'm assuming that snapshot size == image size.
3228 * I hope that's always true. --claudio
3229 */
3230 hsegs = (sd->gspca_dev.width >> 3) - 1;
3231 vsegs = (sd->gspca_dev.height >> 3) - 1;
3232
3233 reg_w(sd, R511_CAM_PXCNT, hsegs);
3234 reg_w(sd, R511_CAM_LNCNT, vsegs);
3235 reg_w(sd, R511_CAM_PXDIV, 0x00);
3236 reg_w(sd, R511_CAM_LNDIV, 0x00);
3237
3238 /* YUV420, low pass filter on */
3239 reg_w(sd, R511_CAM_OPTS, 0x03);
3240
3241 /* Snapshot additions */
3242 reg_w(sd, R511_SNAP_PXCNT, hsegs);
3243 reg_w(sd, R511_SNAP_LNCNT, vsegs);
3244 reg_w(sd, R511_SNAP_PXDIV, 0x00);
3245 reg_w(sd, R511_SNAP_LNDIV, 0x00);
3246
3247 /******** Set the framerate ********/
3248 if (frame_rate > 0)
3249 sd->frame_rate = frame_rate;
3250
3251 switch (sd->sensor) {
3252 case SEN_OV6620:
3253 /* No framerate control, doesn't like higher rates yet */
3254 sd->clockdiv = 3;
3255 break;
3256
3257 /* Note once the FIXME's in mode_init_ov_sensor_regs() are fixed
3258 for more sensors we need to do this for them too */
3259 case SEN_OV7620:
859cc470 3260 case SEN_OV7620AE:
1876bb92 3261 case SEN_OV7640:
035d3a3d 3262 case SEN_OV7648:
b282d873 3263 case SEN_OV76BE:
1876bb92
HG		 3264 if (sd->gspca_dev.width == 320)
3265 interlaced = 1;
3266 /* Fall through */
3267 case SEN_OV6630:
1876bb92
HG		 3268 case SEN_OV7610:
3269 case SEN_OV7670:
3270 switch (sd->frame_rate) {
3271 case 30:
3272 case 25:
3273 /* Not enough bandwidth to do 640x480 @ 30 fps */
3274 if (sd->gspca_dev.width != 640) {
3275 sd->clockdiv = 0;
3276 break;
3277 }
3278 /* Fall through for 640x480 case */
3279 default:
3280/* case 20: */
3281/* case 15: */
3282 sd->clockdiv = 1;
3283 break;
3284 case 10:
3285 sd->clockdiv = 2;
3286 break;
3287 case 5:
3288 sd->clockdiv = 5;
3289 break;
3290 }
3291 if (interlaced) {
3292 sd->clockdiv = (sd->clockdiv + 1) * 2 - 1;
3293 /* Higher then 10 does not work */
3294 if (sd->clockdiv > 10)
3295 sd->clockdiv = 10;
3296 }
3297 break;
3298
3299 case SEN_OV8610:
3300 /* No framerate control ?? */
3301 sd->clockdiv = 0;
3302 break;
3303 }
3304
3305 /* Check if we have enough bandwidth to disable compression */
3306 fps = (interlaced ? 60 : 30) / (sd->clockdiv + 1) + 1;
3307 needed = fps * sd->gspca_dev.width * sd->gspca_dev.height * 3 / 2;
3308 /* 1400 is a conservative estimate of the max nr of isoc packets/sec */
3309 if (needed > 1400 * packet_size) {
3310 /* Enable Y and UV quantization and compression */
3311 reg_w(sd, R511_COMP_EN, 0x07);
3312 reg_w(sd, R511_COMP_LUT_EN, 0x03);
3313 } else {
3314 reg_w(sd, R511_COMP_EN, 0x06);
3315 reg_w(sd, R511_COMP_LUT_EN, 0x00);
3316 }
3317
3318 reg_w(sd, R51x_SYS_RESET, OV511_RESET_OMNICE);
3319 reg_w(sd, R51x_SYS_RESET, 0);
3320
3321 return 0;
3322}
3323
49809d6a
HG		 3324/* Sets up the OV518/OV518+ with the given image parameters
3325 *
3326 * OV518 needs a completely different approach, until we can figure out what
3327 * the individual registers do. Also, only 15 FPS is supported now.
3328 *
3329 * Do not put any sensor-specific code in here (including I2C I/O functions)
3330 */
3331static int ov518_mode_init_regs(struct sd *sd)
3332{
b282d873
HG		 3333 int hsegs, vsegs, packet_size;
3334 struct usb_host_interface *alt;
3335 struct usb_interface *intf;
3336
3337 intf = usb_ifnum_to_if(sd->gspca_dev.dev, sd->gspca_dev.iface);
3338 alt = usb_altnum_to_altsetting(intf, sd->gspca_dev.alt);
3339 if (!alt) {
3340 PDEBUG(D_ERR, "Couldn't get altsetting");
3341 return -EIO;
3342 }
3343
3344 packet_size = le16_to_cpu(alt->endpoint[0].desc.wMaxPacketSize);
3345 ov518_reg_w32(sd, R51x_FIFO_PSIZE, packet_size & ~7, 2);
49809d6a
HG		 3346
3347 /******** Set the mode ********/
3348
3349 reg_w(sd, 0x2b, 0);
3350 reg_w(sd, 0x2c, 0);
3351 reg_w(sd, 0x2d, 0);
3352 reg_w(sd, 0x2e, 0);
3353 reg_w(sd, 0x3b, 0);
3354 reg_w(sd, 0x3c, 0);
3355 reg_w(sd, 0x3d, 0);
3356 reg_w(sd, 0x3e, 0);
3357
3358 if (sd->bridge == BRIDGE_OV518) {
3359 /* Set 8-bit (YVYU) input format */
3360 reg_w_mask(sd, 0x20, 0x08, 0x08);
3361
3362 /* Set 12-bit (4:2:0) output format */
3363 reg_w_mask(sd, 0x28, 0x80, 0xf0);
3364 reg_w_mask(sd, 0x38, 0x80, 0xf0);
3365 } else {
3366 reg_w(sd, 0x28, 0x80);
3367 reg_w(sd, 0x38, 0x80);
3368 }
3369
3370 hsegs = sd->gspca_dev.width / 16;
3371 vsegs = sd->gspca_dev.height / 4;
3372
3373 reg_w(sd, 0x29, hsegs);
3374 reg_w(sd, 0x2a, vsegs);
3375
3376 reg_w(sd, 0x39, hsegs);
3377 reg_w(sd, 0x3a, vsegs);
3378
3379 /* Windows driver does this here; who knows why */
3380 reg_w(sd, 0x2f, 0x80);
3381
b282d873
HG		 3382 /******** Set the framerate ********/
3383 sd->clockdiv = 1;
49809d6a
HG		 3384
3385 /* Mode independent, but framerate dependent, regs */
b282d873
HG		 3386 /* 0x51: Clock divider; Only works on some cams which use 2 crystals */
3387 reg_w(sd, 0x51, 0x04);
49809d6a
HG		 3388 reg_w(sd, 0x22, 0x18);
3389 reg_w(sd, 0x23, 0xff);
3390
b282d873
HG		 3391 if (sd->bridge == BRIDGE_OV518PLUS) {
3392 switch (sd->sensor) {
859cc470 3393 case SEN_OV7620AE:
b282d873
HG		 3394 if (sd->gspca_dev.width == 320) {
3395 reg_w(sd, 0x20, 0x00);
3396 reg_w(sd, 0x21, 0x19);
3397 } else {
3398 reg_w(sd, 0x20, 0x60);
3399 reg_w(sd, 0x21, 0x1f);
3400 }
3401 break;
859cc470
HG		 3402 case SEN_OV7620:
3403 reg_w(sd, 0x20, 0x00);
3404 reg_w(sd, 0x21, 0x19);
3405 break;
b282d873
HG		 3406 default:
3407 reg_w(sd, 0x21, 0x19);
3408 }
3409 } else
49809d6a
HG		 3410 reg_w(sd, 0x71, 0x17); /* Compression-related? */
3411
3412 /* FIXME: Sensor-specific */
3413 /* Bit 5 is what matters here. Of course, it is "reserved" */
3414 i2c_w(sd, 0x54, 0x23);
3415
3416 reg_w(sd, 0x2f, 0x80);
3417
3418 if (sd->bridge == BRIDGE_OV518PLUS) {
3419 reg_w(sd, 0x24, 0x94);
3420 reg_w(sd, 0x25, 0x90);
3421 ov518_reg_w32(sd, 0xc4, 400, 2); /* 190h */
3422 ov518_reg_w32(sd, 0xc6, 540, 2); /* 21ch */
3423 ov518_reg_w32(sd, 0xc7, 540, 2); /* 21ch */
3424 ov518_reg_w32(sd, 0xc8, 108, 2); /* 6ch */
3425 ov518_reg_w32(sd, 0xca, 131098, 3); /* 2001ah */
3426 ov518_reg_w32(sd, 0xcb, 532, 2); /* 214h */
3427 ov518_reg_w32(sd, 0xcc, 2400, 2); /* 960h */
3428 ov518_reg_w32(sd, 0xcd, 32, 2); /* 20h */
3429 ov518_reg_w32(sd, 0xce, 608, 2); /* 260h */
3430 } else {
3431 reg_w(sd, 0x24, 0x9f);
3432 reg_w(sd, 0x25, 0x90);
3433 ov518_reg_w32(sd, 0xc4, 400, 2); /* 190h */
3434 ov518_reg_w32(sd, 0xc6, 381, 2); /* 17dh */
3435 ov518_reg_w32(sd, 0xc7, 381, 2); /* 17dh */
3436 ov518_reg_w32(sd, 0xc8, 128, 2); /* 80h */
3437 ov518_reg_w32(sd, 0xca, 183331, 3); /* 2cc23h */
3438 ov518_reg_w32(sd, 0xcb, 746, 2); /* 2eah */
3439 ov518_reg_w32(sd, 0xcc, 1750, 2); /* 6d6h */
3440 ov518_reg_w32(sd, 0xcd, 45, 2); /* 2dh */
3441 ov518_reg_w32(sd, 0xce, 851, 2); /* 353h */
3442 }
3443
3444 reg_w(sd, 0x2f, 0x80);
3445
3446 return 0;
3447}
3448
3449
6a7eba24
JFM		 3450/* Sets up the OV519 with the given image parameters
3451 *
3452 * OV519 needs a completely different approach, until we can figure out what
3453 * the individual registers do.
3454 *
3455 * Do not put any sensor-specific code in here (including I2C I/O functions)
3456 */
594f5b8b 3457static int ov519_mode_init_regs(struct sd *sd)
6a7eba24 3458{
a5ae2062 3459 static const struct ov_regvals mode_init_519_ov7670[] = {
6a7eba24
JFM		 3460 { 0x5d, 0x03 }, /* Turn off suspend mode */
3461 { 0x53, 0x9f }, /* was 9b in 1.65-1.08 */
3462 { 0x54, 0x0f }, /* bit2 (jpeg enable) */
3463 { 0xa2, 0x20 }, /* a2-a5 are undocumented */
3464 { 0xa3, 0x18 },
3465 { 0xa4, 0x04 },
3466 { 0xa5, 0x28 },
3467 { 0x37, 0x00 }, /* SetUsbInit */
3468 { 0x55, 0x02 }, /* 4.096 Mhz audio clock */
3469 /* Enable both fields, YUV Input, disable defect comp (why?) */
3470 { 0x20, 0x0c },
3471 { 0x21, 0x38 },
3472 { 0x22, 0x1d },
3473 { 0x17, 0x50 }, /* undocumented */
3474 { 0x37, 0x00 }, /* undocumented */
3475 { 0x40, 0xff }, /* I2C timeout counter */
3476 { 0x46, 0x00 }, /* I2C clock prescaler */
3477 { 0x59, 0x04 }, /* new from windrv 090403 */
3478 { 0xff, 0x00 }, /* undocumented */
3479 /* windows reads 0x55 at this point, why? */
3480 };
3481
a5ae2062 3482 static const struct ov_regvals mode_init_519[] = {
6a7eba24
JFM		 3483 { 0x5d, 0x03 }, /* Turn off suspend mode */
3484 { 0x53, 0x9f }, /* was 9b in 1.65-1.08 */
3485 { 0x54, 0x0f }, /* bit2 (jpeg enable) */
3486 { 0xa2, 0x20 }, /* a2-a5 are undocumented */
3487 { 0xa3, 0x18 },
3488 { 0xa4, 0x04 },
3489 { 0xa5, 0x28 },
3490 { 0x37, 0x00 }, /* SetUsbInit */
3491 { 0x55, 0x02 }, /* 4.096 Mhz audio clock */
3492 /* Enable both fields, YUV Input, disable defect comp (why?) */
3493 { 0x22, 0x1d },
3494 { 0x17, 0x50 }, /* undocumented */
3495 { 0x37, 0x00 }, /* undocumented */
3496 { 0x40, 0xff }, /* I2C timeout counter */
3497 { 0x46, 0x00 }, /* I2C clock prescaler */
3498 { 0x59, 0x04 }, /* new from windrv 090403 */
3499 { 0xff, 0x00 }, /* undocumented */
3500 /* windows reads 0x55 at this point, why? */
3501 };
3502
6a7eba24
JFM		 3503 /******** Set the mode ********/
3504 if (sd->sensor != SEN_OV7670) {
3505 if (write_regvals(sd, mode_init_519,
a5ae2062 3506 ARRAY_SIZE(mode_init_519)))
6a7eba24 3507 return -EIO;
035d3a3d
HG		 3508 if (sd->sensor == SEN_OV7640 ||
3509 sd->sensor == SEN_OV7648) {
594f5b8b 3510 /* Select 8-bit input mode */
ac40b1fa 3511 reg_w_mask(sd, OV519_R20_DFR, 0x10, 0x10);
594f5b8b 3512 }
6a7eba24
JFM		 3513 } else {
3514 if (write_regvals(sd, mode_init_519_ov7670,
a5ae2062 3515 ARRAY_SIZE(mode_init_519_ov7670)))
6a7eba24
JFM		 3516 return -EIO;
3517 }
3518
ac40b1fa
JFM		 3519 reg_w(sd, OV519_R10_H_SIZE, sd->gspca_dev.width >> 4);
3520 reg_w(sd, OV519_R11_V_SIZE, sd->gspca_dev.height >> 3);
80142efa
HG		 3521 if (sd->sensor == SEN_OV7670 &&
3522 sd->gspca_dev.cam.cam_mode[sd->gspca_dev.curr_mode].priv)
3523 reg_w(sd, OV519_R12_X_OFFSETL, 0x04);
035d3a3d
HG		 3524 else if (sd->sensor == SEN_OV7648 &&
3525 sd->gspca_dev.cam.cam_mode[sd->gspca_dev.curr_mode].priv)
3526 reg_w(sd, OV519_R12_X_OFFSETL, 0x01);
80142efa
HG		 3527 else
3528 reg_w(sd, OV519_R12_X_OFFSETL, 0x00);
ac40b1fa
JFM		 3529 reg_w(sd, OV519_R13_X_OFFSETH, 0x00);
3530 reg_w(sd, OV519_R14_Y_OFFSETL, 0x00);
3531 reg_w(sd, OV519_R15_Y_OFFSETH, 0x00);
3532 reg_w(sd, OV519_R16_DIVIDER, 0x00);
3533 reg_w(sd, OV519_R25_FORMAT, 0x03); /* YUV422 */
6a7eba24
JFM		 3534 reg_w(sd, 0x26, 0x00); /* Undocumented */
3535
3536 /******** Set the framerate ********/
3537 if (frame_rate > 0)
3538 sd->frame_rate = frame_rate;
3539
3540/* FIXME: These are only valid at the max resolution. */
3541 sd->clockdiv = 0;
594f5b8b
JFM		 3542 switch (sd->sensor) {
3543 case SEN_OV7640:
035d3a3d 3544 case SEN_OV7648:
6a7eba24 3545 switch (sd->frame_rate) {
53e74515
JFM		 3546 default:
3547/* case 30: */
6a7eba24
JFM		 3548 reg_w(sd, 0xa4, 0x0c);
3549 reg_w(sd, 0x23, 0xff);
3550 break;
3551 case 25:
3552 reg_w(sd, 0xa4, 0x0c);
3553 reg_w(sd, 0x23, 0x1f);
3554 break;
3555 case 20:
3556 reg_w(sd, 0xa4, 0x0c);
3557 reg_w(sd, 0x23, 0x1b);
3558 break;
53e74515 3559 case 15:
6a7eba24
JFM		 3560 reg_w(sd, 0xa4, 0x04);
3561 reg_w(sd, 0x23, 0xff);
3562 sd->clockdiv = 1;
3563 break;
3564 case 10:
3565 reg_w(sd, 0xa4, 0x04);
3566 reg_w(sd, 0x23, 0x1f);
3567 sd->clockdiv = 1;
3568 break;
3569 case 5:
3570 reg_w(sd, 0xa4, 0x04);
3571 reg_w(sd, 0x23, 0x1b);
3572 sd->clockdiv = 1;
3573 break;
3574 }
594f5b8b
JFM		 3575 break;
3576 case SEN_OV8610:
6a7eba24
JFM		 3577 switch (sd->frame_rate) {
3578 default: /* 15 fps */
3579/* case 15: */
3580 reg_w(sd, 0xa4, 0x06);
3581 reg_w(sd, 0x23, 0xff);
3582 break;
3583 case 10:
3584 reg_w(sd, 0xa4, 0x06);
3585 reg_w(sd, 0x23, 0x1f);
3586 break;
3587 case 5:
3588 reg_w(sd, 0xa4, 0x06);
3589 reg_w(sd, 0x23, 0x1b);
3590 break;
3591 }
594f5b8b
JFM		 3592 break;
3593 case SEN_OV7670: /* guesses, based on 7640 */
6a7eba24
JFM		 3594 PDEBUG(D_STREAM, "Setting framerate to %d fps",
3595 (sd->frame_rate == 0) ? 15 : sd->frame_rate);
594f5b8b 3596 reg_w(sd, 0xa4, 0x10);
6a7eba24
JFM		 3597 switch (sd->frame_rate) {
3598 case 30:
6a7eba24
JFM		 3599 reg_w(sd, 0x23, 0xff);
3600 break;
3601 case 20:
6a7eba24
JFM		 3602 reg_w(sd, 0x23, 0x1b);
3603 break;
594f5b8b
JFM		 3604 default:
3605/* case 15: */
6a7eba24
JFM		 3606 reg_w(sd, 0x23, 0xff);
3607 sd->clockdiv = 1;
3608 break;
3609 }
594f5b8b 3610 break;
6a7eba24 3611 }
6a7eba24
JFM		 3612 return 0;
3613}
3614
594f5b8b 3615static int mode_init_ov_sensor_regs(struct sd *sd)
6a7eba24 3616{
594f5b8b 3617 struct gspca_dev *gspca_dev;
ebbb5c3e
HG		 3618 int qvga, xstart, xend, ystart, yend;
3619 __u8 v;
594f5b8b
JFM		 3620
3621 gspca_dev = &sd->gspca_dev;
124cc9c0 3622 qvga = gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].priv & 1;
6a7eba24
JFM		 3623
3624 /******** Mode (VGA/QVGA) and sensor specific regs ********/
3625 switch (sd->sensor) {
635118d5
HG		 3626 case SEN_OV2610:
3627 i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
3628 i2c_w_mask(sd, 0x28, qvga ? 0x00 : 0x20, 0x20);
3629 i2c_w(sd, 0x24, qvga ? 0x20 : 0x3a);
3630 i2c_w(sd, 0x25, qvga ? 0x30 : 0x60);
3631 i2c_w_mask(sd, 0x2d, qvga ? 0x40 : 0x00, 0x40);
3632 i2c_w_mask(sd, 0x67, qvga ? 0xf0 : 0x90, 0xf0);
3633 i2c_w_mask(sd, 0x74, qvga ? 0x20 : 0x00, 0x20);
3634 return 0;
ebbb5c3e 3635 case SEN_OV3610:
635118d5
HG		 3636 if (qvga) {
3637 xstart = (1040 - gspca_dev->width) / 2 + (0x1f << 4);
b46aaa02 3638 ystart = (776 - gspca_dev->height) / 2;
635118d5 3639 } else {
b46aaa02 3640 xstart = (2076 - gspca_dev->width) / 2 + (0x10 << 4);
635118d5
HG		 3641 ystart = (1544 - gspca_dev->height) / 2;
3642 }
3643 xend = xstart + gspca_dev->width;
3644 yend = ystart + gspca_dev->height;
3645 /* Writing to the COMH register resets the other windowing regs
3646 to their default values, so we must do this first. */
3647 i2c_w_mask(sd, 0x12, qvga ? 0x40 : 0x00, 0xf0);
3648 i2c_w_mask(sd, 0x32,
3649 (((xend >> 1) & 7) << 3) | ((xstart >> 1) & 7),
3650 0x3f);
3651 i2c_w_mask(sd, 0x03,
3652 (((yend >> 1) & 3) << 2) | ((ystart >> 1) & 3),
3653 0x0f);
3654 i2c_w(sd, 0x17, xstart >> 4);
3655 i2c_w(sd, 0x18, xend >> 4);
3656 i2c_w(sd, 0x19, ystart >> 3);
3657 i2c_w(sd, 0x1a, yend >> 3);
3658 return 0;
6a7eba24
JFM		 3659 case SEN_OV8610:
3660 /* For OV8610 qvga means qsvga */
3661 i2c_w_mask(sd, OV7610_REG_COM_C, qvga ? (1 << 5) : 0, 1 << 5);
ebbb5c3e
HG		 3662 i2c_w_mask(sd, 0x13, 0x00, 0x20); /* Select 16 bit data bus */
3663 i2c_w_mask(sd, 0x12, 0x04, 0x06); /* AWB: 1 Test pattern: 0 */
3664 i2c_w_mask(sd, 0x2d, 0x00, 0x40); /* from windrv 090403 */
3665 i2c_w_mask(sd, 0x28, 0x20, 0x20); /* progressive mode on */
6a7eba24
JFM		 3666 break;
3667 case SEN_OV7610:
3668 i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
ebbb5c3e
HG		 3669 i2c_w(sd, 0x35, qvga?0x1e:0x9e);
3670 i2c_w_mask(sd, 0x13, 0x00, 0x20); /* Select 16 bit data bus */
3671 i2c_w_mask(sd, 0x12, 0x04, 0x06); /* AWB: 1 Test pattern: 0 */
6a7eba24
JFM		 3672 break;
3673 case SEN_OV7620:
859cc470 3674 case SEN_OV7620AE:
b282d873 3675 case SEN_OV76BE:
6a7eba24
JFM		 3676 i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
3677 i2c_w_mask(sd, 0x28, qvga ? 0x00 : 0x20, 0x20);
3678 i2c_w(sd, 0x24, qvga ? 0x20 : 0x3a);
3679 i2c_w(sd, 0x25, qvga ? 0x30 : 0x60);
3680 i2c_w_mask(sd, 0x2d, qvga ? 0x40 : 0x00, 0x40);
b282d873 3681 i2c_w_mask(sd, 0x67, qvga ? 0xb0 : 0x90, 0xf0);
6a7eba24 3682 i2c_w_mask(sd, 0x74, qvga ? 0x20 : 0x00, 0x20);
ebbb5c3e
HG		 3683 i2c_w_mask(sd, 0x13, 0x00, 0x20); /* Select 16 bit data bus */
3684 i2c_w_mask(sd, 0x12, 0x04, 0x06); /* AWB: 1 Test pattern: 0 */
3685 if (sd->sensor == SEN_OV76BE)
3686 i2c_w(sd, 0x35, qvga ? 0x1e : 0x9e);
6a7eba24 3687 break;
6a7eba24 3688 case SEN_OV7640:
035d3a3d 3689 case SEN_OV7648:
6a7eba24
JFM		 3690 i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
3691 i2c_w_mask(sd, 0x28, qvga ? 0x00 : 0x20, 0x20);
8d0082fa
HG		 3692 /* Setting this undocumented bit in qvga mode removes a very
3693 annoying vertical shaking of the image */
035d3a3d 3694 i2c_w_mask(sd, 0x2d, qvga ? 0x40 : 0x00, 0x40);
8d0082fa 3695 /* Unknown */
035d3a3d 3696 i2c_w_mask(sd, 0x67, qvga ? 0xf0 : 0x90, 0xf0);
8d0082fa 3697 /* Allow higher automatic gain (to allow higher framerates) */
035d3a3d 3698 i2c_w_mask(sd, 0x74, qvga ? 0x20 : 0x00, 0x20);
ebbb5c3e 3699 i2c_w_mask(sd, 0x12, 0x04, 0x04); /* AWB: 1 */
6a7eba24
JFM		 3700 break;
3701 case SEN_OV7670:
3702 /* set COM7_FMT_VGA or COM7_FMT_QVGA
3703 * do we need to set anything else?
3704 * HSTART etc are set in set_ov_sensor_window itself */
3705 i2c_w_mask(sd, OV7670_REG_COM7,
3706 qvga ? OV7670_COM7_FMT_QVGA : OV7670_COM7_FMT_VGA,
3707 OV7670_COM7_FMT_MASK);
ebbb5c3e
HG		 3708 i2c_w_mask(sd, 0x13, 0x00, 0x20); /* Select 16 bit data bus */
3709 i2c_w_mask(sd, OV7670_REG_COM8, OV7670_COM8_AWB,
3710 OV7670_COM8_AWB);
3711 if (qvga) { /* QVGA from ov7670.c by
3712 * Jonathan Corbet */
3713 xstart = 164;
3714 xend = 28;
3715 ystart = 14;
3716 yend = 494;
3717 } else { /* VGA */
3718 xstart = 158;
3719 xend = 14;
3720 ystart = 10;
3721 yend = 490;
3722 }
3723 /* OV7670 hardware window registers are split across
3724 * multiple locations */
3725 i2c_w(sd, OV7670_REG_HSTART, xstart >> 3);
3726 i2c_w(sd, OV7670_REG_HSTOP, xend >> 3);
3727 v = i2c_r(sd, OV7670_REG_HREF);
3728 v = (v & 0xc0) | ((xend & 0x7) << 3) | (xstart & 0x07);
3729 msleep(10); /* need to sleep between read and write to
3730 * same reg! */
3731 i2c_w(sd, OV7670_REG_HREF, v);
3732
3733 i2c_w(sd, OV7670_REG_VSTART, ystart >> 2);
3734 i2c_w(sd, OV7670_REG_VSTOP, yend >> 2);
3735 v = i2c_r(sd, OV7670_REG_VREF);
3736 v = (v & 0xc0) | ((yend & 0x3) << 2) | (ystart & 0x03);
3737 msleep(10); /* need to sleep between read and write to
3738 * same reg! */
3739 i2c_w(sd, OV7670_REG_VREF, v);
6a7eba24
JFM		 3740 break;
3741 case SEN_OV6620:
ebbb5c3e
HG		 3742 i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
3743 i2c_w_mask(sd, 0x13, 0x00, 0x20); /* Select 16 bit data bus */
3744 i2c_w_mask(sd, 0x12, 0x04, 0x06); /* AWB: 1 Test pattern: 0 */
3745 break;
6a7eba24 3746 case SEN_OV6630:
7d971373 3747 case SEN_OV66308AF:
6a7eba24 3748 i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
ebbb5c3e 3749 i2c_w_mask(sd, 0x12, 0x04, 0x06); /* AWB: 1 Test pattern: 0 */
6a7eba24
JFM		 3750 break;
3751 default:
3752 return -EINVAL;
3753 }
3754
6a7eba24 3755 /******** Clock programming ********/
ae49c404 3756 i2c_w(sd, 0x11, sd->clockdiv);
6a7eba24 3757
6a7eba24
JFM		 3758 return 0;
3759}
3760
594f5b8b 3761static void sethvflip(struct sd *sd)
0cd6759d 3762{
594f5b8b
JFM		 3763 if (sd->sensor != SEN_OV7670)
3764 return;
0cd6759d
JFM		 3765 if (sd->gspca_dev.streaming)
3766 ov51x_stop(sd);
3767 i2c_w_mask(sd, OV7670_REG_MVFP,
594f5b8b
JFM		 3768 OV7670_MVFP_MIRROR * sd->hflip
3769 | OV7670_MVFP_VFLIP * sd->vflip,
3770 OV7670_MVFP_MIRROR | OV7670_MVFP_VFLIP);
0cd6759d
JFM		 3771 if (sd->gspca_dev.streaming)
3772 ov51x_restart(sd);
3773}
3774
594f5b8b 3775static int set_ov_sensor_window(struct sd *sd)
6a7eba24 3776{
594f5b8b 3777 struct gspca_dev *gspca_dev;
124cc9c0 3778 int qvga, crop;
6a7eba24 3779 int hwsbase, hwebase, vwsbase, vwebase, hwscale, vwscale;
ebbb5c3e 3780 int ret;
6a7eba24 3781
635118d5 3782 /* mode setup is fully handled in mode_init_ov_sensor_regs for these */
ebbb5c3e
HG		 3783 if (sd->sensor == SEN_OV2610 || sd->sensor == SEN_OV3610 ||
3784 sd->sensor == SEN_OV7670)
635118d5
HG		 3785 return mode_init_ov_sensor_regs(sd);
3786
594f5b8b 3787 gspca_dev = &sd->gspca_dev;
124cc9c0
HG		 3788 qvga = gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].priv & 1;
3789 crop = gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].priv & 2;
594f5b8b 3790
6a7eba24
JFM		 3791 /* The different sensor ICs handle setting up of window differently.
3792 * IF YOU SET IT WRONG, YOU WILL GET ALL ZERO ISOC DATA FROM OV51x!! */
3793 switch (sd->sensor) {
3794 case SEN_OV8610:
3795 hwsbase = 0x1e;
3796 hwebase = 0x1e;
3797 vwsbase = 0x02;
3798 vwebase = 0x02;
3799 break;
3800 case SEN_OV7610:
3801 case SEN_OV76BE:
3802 hwsbase = 0x38;
3803 hwebase = 0x3a;
3804 vwsbase = vwebase = 0x05;
3805 break;
3806 case SEN_OV6620:
3807 case SEN_OV6630:
7d971373 3808 case SEN_OV66308AF:
6a7eba24
JFM		 3809 hwsbase = 0x38;
3810 hwebase = 0x3a;
3811 vwsbase = 0x05;
3812 vwebase = 0x06;
7d971373 3813 if (sd->sensor == SEN_OV66308AF && qvga)
49809d6a 3814 /* HDG: this fixes U and V getting swapped */
7d971373 3815 hwsbase++;
124cc9c0
HG		 3816 if (crop) {
3817 hwsbase += 8;
3818 hwebase += 8;
3819 vwsbase += 11;
3820 vwebase += 11;
3821 }
6a7eba24
JFM		 3822 break;
3823 case SEN_OV7620:
859cc470 3824 case SEN_OV7620AE:
6a7eba24
JFM		 3825 hwsbase = 0x2f; /* From 7620.SET (spec is wrong) */
3826 hwebase = 0x2f;
3827 vwsbase = vwebase = 0x05;
3828 break;
3829 case SEN_OV7640:
035d3a3d 3830 case SEN_OV7648:
6a7eba24
JFM		 3831 hwsbase = 0x1a;
3832 hwebase = 0x1a;
3833 vwsbase = vwebase = 0x03;
3834 break;
6a7eba24
JFM		 3835 default:
3836 return -EINVAL;
3837 }
3838
3839 switch (sd->sensor) {
3840 case SEN_OV6620:
3841 case SEN_OV6630:
7d971373 3842 case SEN_OV66308AF:
594f5b8b 3843 if (qvga) { /* QCIF */
6a7eba24
JFM		 3844 hwscale = 0;
3845 vwscale = 0;
3846 } else { /* CIF */
3847 hwscale = 1;
3848 vwscale = 1; /* The datasheet says 0;
3849 * it's wrong */
3850 }
3851 break;
3852 case SEN_OV8610:
594f5b8b 3853 if (qvga) { /* QSVGA */
6a7eba24
JFM		 3854 hwscale = 1;
3855 vwscale = 1;
3856 } else { /* SVGA */
3857 hwscale = 2;
3858 vwscale = 2;
3859 }
3860 break;
3861 default: /* SEN_OV7xx0 */
594f5b8b 3862 if (qvga) { /* QVGA */
6a7eba24
JFM		 3863 hwscale = 1;
3864 vwscale = 0;
3865 } else { /* VGA */
3866 hwscale = 2;
3867 vwscale = 1;
3868 }
3869 }
3870
594f5b8b 3871 ret = mode_init_ov_sensor_regs(sd);
6a7eba24
JFM		 3872 if (ret < 0)
3873 return ret;
3874
ebbb5c3e 3875 i2c_w(sd, 0x17, hwsbase);
a511ba94 3876 i2c_w(sd, 0x18, hwebase + (sd->sensor_width >> hwscale));
ebbb5c3e 3877 i2c_w(sd, 0x19, vwsbase);
a511ba94 3878 i2c_w(sd, 0x1a, vwebase + (sd->sensor_height >> vwscale));
6a7eba24 3879
6a7eba24
JFM		 3880 return 0;
3881}
3882
6a7eba24 3883/* -- start the camera -- */
72ab97ce 3884static int sd_start(struct gspca_dev *gspca_dev)
6a7eba24
JFM		 3885{
3886 struct sd *sd = (struct sd *) gspca_dev;
49809d6a 3887 int ret = 0;
6a7eba24 3888
a511ba94
HG		 3889 /* Default for most bridges, allow bridge_mode_init_regs to override */
3890 sd->sensor_width = sd->gspca_dev.width;
3891 sd->sensor_height = sd->gspca_dev.height;
3892
49809d6a 3893 switch (sd->bridge) {
1876bb92
HG		 3894 case BRIDGE_OV511:
3895 case BRIDGE_OV511PLUS:
3896 ret = ov511_mode_init_regs(sd);
3897 break;
49809d6a
HG		 3898 case BRIDGE_OV518:
3899 case BRIDGE_OV518PLUS:
3900 ret = ov518_mode_init_regs(sd);
3901 break;
3902 case BRIDGE_OV519:
3903 ret = ov519_mode_init_regs(sd);
3904 break;
b46aaa02 3905 /* case BRIDGE_OVFX2: nothing to do */
a511ba94
HG		 3906 case BRIDGE_W9968CF:
3907 ret = w9968cf_mode_init_regs(sd);
3908 break;
49809d6a 3909 }
6a7eba24
JFM		 3910 if (ret < 0)
3911 goto out;
49809d6a 3912
594f5b8b 3913 ret = set_ov_sensor_window(sd);
6a7eba24
JFM		 3914 if (ret < 0)
3915 goto out;
3916
49809d6a
HG		 3917 setcontrast(gspca_dev);
3918 setbrightness(gspca_dev);
3919 setcolors(gspca_dev);
02ab18b0
HG		 3920 sethvflip(sd);
3921 setautobrightness(sd);
3922 setfreq(sd);
49809d6a 3923
594f5b8b 3924 ret = ov51x_restart(sd);
6a7eba24
JFM		 3925 if (ret < 0)
3926 goto out;
6a7eba24 3927 ov51x_led_control(sd, 1);
72ab97ce 3928 return 0;
6a7eba24
JFM		 3929out:
3930 PDEBUG(D_ERR, "camera start error:%d", ret);
72ab97ce 3931 return ret;
6a7eba24
JFM		 3932}
3933
3934static void sd_stopN(struct gspca_dev *gspca_dev)
3935{
ac40b1fa
JFM		 3936 struct sd *sd = (struct sd *) gspca_dev;
3937
3938 ov51x_stop(sd);
3939 ov51x_led_control(sd, 0);
6a7eba24
JFM		 3940}
3941
79b35902
HG		 3942static void sd_stop0(struct gspca_dev *gspca_dev)
3943{
3944 struct sd *sd = (struct sd *) gspca_dev;
3945
3946 if (sd->bridge == BRIDGE_W9968CF)
3947 w9968cf_stop0(sd);
3948}
3949
1876bb92 3950static void ov511_pkt_scan(struct gspca_dev *gspca_dev,
76dd272b
JFM		 3951 u8 *in, /* isoc packet */
3952 int len) /* iso packet length */
1876bb92
HG		 3953{
3954 struct sd *sd = (struct sd *) gspca_dev;
3955
3956 /* SOF/EOF packets have 1st to 8th bytes zeroed and the 9th
3957 * byte non-zero. The EOF packet has image width/height in the
3958 * 10th and 11th bytes. The 9th byte is given as follows:
3959 *
3960 * bit 7: EOF
3961 * 6: compression enabled
3962 * 5: 422/420/400 modes
3963 * 4: 422/420/400 modes
3964 * 3: 1
3965 * 2: snapshot button on
3966 * 1: snapshot frame
3967 * 0: even/odd field
3968 */
3969 if (!(in[0] | in[1] | in[2] | in[3] | in[4] | in[5] | in[6] | in[7]) &&
3970 (in[8] & 0x08)) {
3971 if (in[8] & 0x80) {
3972 /* Frame end */
3973 if ((in[9] + 1) * 8 != gspca_dev->width ||
3974 (in[10] + 1) * 8 != gspca_dev->height) {
3975 PDEBUG(D_ERR, "Invalid frame size, got: %dx%d,"
3976 " requested: %dx%d\n",
3977 (in[9] + 1) * 8, (in[10] + 1) * 8,
3978 gspca_dev->width, gspca_dev->height);
3979 gspca_dev->last_packet_type = DISCARD_PACKET;
3980 return;
3981 }
3982 /* Add 11 byte footer to frame, might be usefull */
76dd272b 3983 gspca_frame_add(gspca_dev, LAST_PACKET, in, 11);
1876bb92
HG		 3984 return;
3985 } else {
3986 /* Frame start */
76dd272b 3987 gspca_frame_add(gspca_dev, FIRST_PACKET, in, 0);
1876bb92
HG		 3988 sd->packet_nr = 0;
3989 }
3990 }
3991
3992 /* Ignore the packet number */
3993 len--;
3994
3995 /* intermediate packet */
76dd272b 3996 gspca_frame_add(gspca_dev, INTER_PACKET, in, len);
1876bb92
HG		 3997}
3998
49809d6a 3999static void ov518_pkt_scan(struct gspca_dev *gspca_dev,
76dd272b 4000 u8 *data, /* isoc packet */
49809d6a
HG		 4001 int len) /* iso packet length */
4002{
92918a53 4003 struct sd *sd = (struct sd *) gspca_dev;
49809d6a
HG		 4004
4005 /* A false positive here is likely, until OVT gives me
4006 * the definitive SOF/EOF format */
4007 if ((!(data[0] | data[1] | data[2] | data[3] | data[5])) && data[6]) {
76dd272b
JFM		 4008 gspca_frame_add(gspca_dev, LAST_PACKET, NULL, 0);
4009 gspca_frame_add(gspca_dev, FIRST_PACKET, NULL, 0);
92918a53
HG		 4010 sd->packet_nr = 0;
4011 }
4012
4013 if (gspca_dev->last_packet_type == DISCARD_PACKET)
4014 return;
4015
4016 /* Does this device use packet numbers ? */
4017 if (len & 7) {
4018 len--;
4019 if (sd->packet_nr == data[len])
4020 sd->packet_nr++;
4021 /* The last few packets of the frame (which are all 0's
4022 except that they may contain part of the footer), are
4023 numbered 0 */
4024 else if (sd->packet_nr == 0 || data[len]) {
4025 PDEBUG(D_ERR, "Invalid packet nr: %d (expect: %d)",
4026 (int)data[len], (int)sd->packet_nr);
4027 gspca_dev->last_packet_type = DISCARD_PACKET;
4028 return;
4029 }
49809d6a
HG		 4030 }
4031
4032 /* intermediate packet */
76dd272b 4033 gspca_frame_add(gspca_dev, INTER_PACKET, data, len);
49809d6a
HG		 4034}
4035
4036static void ov519_pkt_scan(struct gspca_dev *gspca_dev,
76dd272b 4037 u8 *data, /* isoc packet */
6a7eba24
JFM		 4038 int len) /* iso packet length */
4039{
4040 /* Header of ov519 is 16 bytes:
4041 * Byte Value Description
4042 * 0 0xff magic
4043 * 1 0xff magic
4044 * 2 0xff magic
4045 * 3 0xXX 0x50 = SOF, 0x51 = EOF
4046 * 9 0xXX 0x01 initial frame without data,
4047 * 0x00 standard frame with image
4048 * 14 Lo in EOF: length of image data / 8
4049 * 15 Hi
4050 */
4051
4052 if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff) {
4053 switch (data[3]) {
4054 case 0x50: /* start of frame */
4055#define HDRSZ 16
4056 data += HDRSZ;
4057 len -= HDRSZ;
4058#undef HDRSZ
4059 if (data[0] == 0xff || data[1] == 0xd8)
76dd272b 4060 gspca_frame_add(gspca_dev, FIRST_PACKET,
6a7eba24
JFM		 4061 data, len);
4062 else
4063 gspca_dev->last_packet_type = DISCARD_PACKET;
4064 return;
4065 case 0x51: /* end of frame */
4066 if (data[9] != 0)
4067 gspca_dev->last_packet_type = DISCARD_PACKET;
76dd272b
JFM		 4068 gspca_frame_add(gspca_dev, LAST_PACKET,
4069 NULL, 0);
6a7eba24
JFM		 4070 return;
4071 }
4072 }
4073
4074 /* intermediate packet */
76dd272b 4075 gspca_frame_add(gspca_dev, INTER_PACKET, data, len);
6a7eba24
JFM		 4076}
4077
b46aaa02 4078static void ovfx2_pkt_scan(struct gspca_dev *gspca_dev,
76dd272b 4079 u8 *data, /* isoc packet */
b46aaa02
HG		 4080 int len) /* iso packet length */
4081{
4082 /* A short read signals EOF */
4083 if (len < OVFX2_BULK_SIZE) {
76dd272b
JFM		 4084 gspca_frame_add(gspca_dev, LAST_PACKET, data, len);
4085 gspca_frame_add(gspca_dev, FIRST_PACKET, NULL, 0);
b46aaa02
HG		 4086 return;
4087 }
76dd272b 4088 gspca_frame_add(gspca_dev, INTER_PACKET, data, len);
b46aaa02
HG		 4089}
4090
49809d6a 4091static void sd_pkt_scan(struct gspca_dev *gspca_dev,
76dd272b 4092 u8 *data, /* isoc packet */
49809d6a
HG		 4093 int len) /* iso packet length */
4094{
4095 struct sd *sd = (struct sd *) gspca_dev;
4096
4097 switch (sd->bridge) {
4098 case BRIDGE_OV511:
4099 case BRIDGE_OV511PLUS:
76dd272b 4100 ov511_pkt_scan(gspca_dev, data, len);
49809d6a
HG		 4101 break;
4102 case BRIDGE_OV518:
4103 case BRIDGE_OV518PLUS:
76dd272b 4104 ov518_pkt_scan(gspca_dev, data, len);
49809d6a
HG		 4105 break;
4106 case BRIDGE_OV519:
76dd272b 4107 ov519_pkt_scan(gspca_dev, data, len);
49809d6a 4108 break;
b46aaa02 4109 case BRIDGE_OVFX2:
76dd272b 4110 ovfx2_pkt_scan(gspca_dev, data, len);
b46aaa02 4111 break;
a511ba94 4112 case BRIDGE_W9968CF:
76dd272b 4113 w9968cf_pkt_scan(gspca_dev, data, len);
a511ba94 4114 break;
49809d6a
HG		 4115 }
4116}
4117
6a7eba24
JFM		 4118/* -- management routines -- */
4119
4120static void setbrightness(struct gspca_dev *gspca_dev)
4121{
4122 struct sd *sd = (struct sd *) gspca_dev;
4123 int val;
6a7eba24
JFM		 4124
4125 val = sd->brightness;
6a7eba24
JFM		 4126 switch (sd->sensor) {
4127 case SEN_OV8610:
4128 case SEN_OV7610:
4129 case SEN_OV76BE:
4130 case SEN_OV6620:
4131 case SEN_OV6630:
7d971373 4132 case SEN_OV66308AF:
6a7eba24 4133 case SEN_OV7640:
035d3a3d 4134 case SEN_OV7648:
6a7eba24
JFM		 4135 i2c_w(sd, OV7610_REG_BRT, val);
4136 break;
4137 case SEN_OV7620:
859cc470 4138 case SEN_OV7620AE:
6a7eba24 4139 /* 7620 doesn't like manual changes when in auto mode */
02ab18b0 4140 if (!sd->autobrightness)
6a7eba24
JFM		 4141 i2c_w(sd, OV7610_REG_BRT, val);
4142 break;
4143 case SEN_OV7670:
594f5b8b 4144/*win trace
6a7eba24
JFM		 4145 * i2c_w_mask(sd, OV7670_REG_COM8, 0, OV7670_COM8_AEC); */
4146 i2c_w(sd, OV7670_REG_BRIGHT, ov7670_abs_to_sm(val));
4147 break;
4148 }
6a7eba24
JFM		 4149}
4150
4151static void setcontrast(struct gspca_dev *gspca_dev)
4152{
4153 struct sd *sd = (struct sd *) gspca_dev;
4154 int val;
6a7eba24
JFM		 4155
4156 val = sd->contrast;
6a7eba24
JFM		 4157 switch (sd->sensor) {
4158 case SEN_OV7610:
4159 case SEN_OV6620:
4160 i2c_w(sd, OV7610_REG_CNT, val);
4161 break;
4162 case SEN_OV6630:
7d971373 4163 case SEN_OV66308AF:
6a7eba24 4164 i2c_w_mask(sd, OV7610_REG_CNT, val >> 4, 0x0f);
49809d6a 4165 break;
6a7eba24 4166 case SEN_OV8610: {
a5ae2062 4167 static const __u8 ctab[] = {
6a7eba24
JFM		 4168 0x03, 0x09, 0x0b, 0x0f, 0x53, 0x6f, 0x35, 0x7f
4169 };
4170
4171 /* Use Y gamma control instead. Bit 0 enables it. */
4172 i2c_w(sd, 0x64, ctab[val >> 5]);
4173 break;
4174 }
859cc470
HG		 4175 case SEN_OV7620:
4176 case SEN_OV7620AE: {
a5ae2062 4177 static const __u8 ctab[] = {
6a7eba24
JFM		 4178 0x01, 0x05, 0x09, 0x11, 0x15, 0x35, 0x37, 0x57,
4179 0x5b, 0xa5, 0xa7, 0xc7, 0xc9, 0xcf, 0xef, 0xff
4180 };
4181
4182 /* Use Y gamma control instead. Bit 0 enables it. */
4183 i2c_w(sd, 0x64, ctab[val >> 4]);
4184 break;
4185 }
6a7eba24
JFM		 4186 case SEN_OV7670:
4187 /* check that this isn't just the same as ov7610 */
4188 i2c_w(sd, OV7670_REG_CONTRAS, val >> 1);
4189 break;
4190 }
6a7eba24
JFM		 4191}
4192
4193static void setcolors(struct gspca_dev *gspca_dev)
4194{
4195 struct sd *sd = (struct sd *) gspca_dev;
4196 int val;
6a7eba24
JFM		 4197
4198 val = sd->colors;
6a7eba24
JFM		 4199 switch (sd->sensor) {
4200 case SEN_OV8610:
4201 case SEN_OV7610:
4202 case SEN_OV76BE:
4203 case SEN_OV6620:
4204 case SEN_OV6630:
7d971373 4205 case SEN_OV66308AF:
6a7eba24
JFM		 4206 i2c_w(sd, OV7610_REG_SAT, val);
4207 break;
4208 case SEN_OV7620:
859cc470 4209 case SEN_OV7620AE:
6a7eba24
JFM		 4210 /* Use UV gamma control instead. Bits 0 & 7 are reserved. */
4211/* rc = ov_i2c_write(sd->dev, 0x62, (val >> 9) & 0x7e);
4212 if (rc < 0)
4213 goto out; */
4214 i2c_w(sd, OV7610_REG_SAT, val);
4215 break;
4216 case SEN_OV7640:
035d3a3d 4217 case SEN_OV7648:
6a7eba24
JFM		 4218 i2c_w(sd, OV7610_REG_SAT, val & 0xf0);
4219 break;
4220 case SEN_OV7670:
4221 /* supported later once I work out how to do it
4222 * transparently fail now! */
4223 /* set REG_COM13 values for UV sat auto mode */
4224 break;
4225 }
6a7eba24
JFM		 4226}
4227
02ab18b0
HG		 4228static void setautobrightness(struct sd *sd)
4229{
035d3a3d
HG		 4230 if (sd->sensor == SEN_OV7640 || sd->sensor == SEN_OV7648 ||
4231 sd->sensor == SEN_OV7670 ||
635118d5 4232 sd->sensor == SEN_OV2610 || sd->sensor == SEN_OV3610)
02ab18b0
HG		 4233 return;
4234
4235 i2c_w_mask(sd, 0x2d, sd->autobrightness ? 0x10 : 0x00, 0x10);
4236}
4237
4238static void setfreq(struct sd *sd)
4239{
635118d5
HG		 4240 if (sd->sensor == SEN_OV2610 || sd->sensor == SEN_OV3610)
4241 return;
4242
02ab18b0
HG		 4243 if (sd->sensor == SEN_OV7670) {
4244 switch (sd->freq) {
4245 case 0: /* Banding filter disabled */
4246 i2c_w_mask(sd, OV7670_REG_COM8, 0, OV7670_COM8_BFILT);
4247 break;
4248 case 1: /* 50 hz */
4249 i2c_w_mask(sd, OV7670_REG_COM8, OV7670_COM8_BFILT,
4250 OV7670_COM8_BFILT);
4251 i2c_w_mask(sd, OV7670_REG_COM11, 0x08, 0x18);
4252 break;
4253 case 2: /* 60 hz */
4254 i2c_w_mask(sd, OV7670_REG_COM8, OV7670_COM8_BFILT,
4255 OV7670_COM8_BFILT);
4256 i2c_w_mask(sd, OV7670_REG_COM11, 0x00, 0x18);
4257 break;
4258 case 3: /* Auto hz */
4259 i2c_w_mask(sd, OV7670_REG_COM8, OV7670_COM8_BFILT,
4260 OV7670_COM8_BFILT);
4261 i2c_w_mask(sd, OV7670_REG_COM11, OV7670_COM11_HZAUTO,
4262 0x18);
4263 break;
4264 }
4265 } else {
4266 switch (sd->freq) {
4267 case 0: /* Banding filter disabled */
4268 i2c_w_mask(sd, 0x2d, 0x00, 0x04);
4269 i2c_w_mask(sd, 0x2a, 0x00, 0x80);
4270 break;
4271 case 1: /* 50 hz (filter on and framerate adj) */
4272 i2c_w_mask(sd, 0x2d, 0x04, 0x04);
4273 i2c_w_mask(sd, 0x2a, 0x80, 0x80);
4274 /* 20 fps -> 16.667 fps */
4275 if (sd->sensor == SEN_OV6620 ||
7d971373
HG		 4276 sd->sensor == SEN_OV6630 ||
4277 sd->sensor == SEN_OV66308AF)
02ab18b0
HG		 4278 i2c_w(sd, 0x2b, 0x5e);
4279 else
4280 i2c_w(sd, 0x2b, 0xac);
4281 break;
4282 case 2: /* 60 hz (filter on, ...) */
4283 i2c_w_mask(sd, 0x2d, 0x04, 0x04);
4284 if (sd->sensor == SEN_OV6620 ||
7d971373
HG		 4285 sd->sensor == SEN_OV6630 ||
4286 sd->sensor == SEN_OV66308AF) {
02ab18b0
HG		 4287 /* 20 fps -> 15 fps */
4288 i2c_w_mask(sd, 0x2a, 0x80, 0x80);
4289 i2c_w(sd, 0x2b, 0xa8);
4290 } else {
4291 /* no framerate adj. */
4292 i2c_w_mask(sd, 0x2a, 0x00, 0x80);
4293 }
4294 break;
4295 }
4296 }
4297}
4298
6a7eba24
JFM		 4299static int sd_setbrightness(struct gspca_dev *gspca_dev, __s32 val)
4300{
4301 struct sd *sd = (struct sd *) gspca_dev;
4302
4303 sd->brightness = val;
ac40b1fa
JFM		 4304 if (gspca_dev->streaming)
4305 setbrightness(gspca_dev);
6a7eba24
JFM		 4306 return 0;
4307}
4308
4309static int sd_getbrightness(struct gspca_dev *gspca_dev, __s32 *val)
4310{
4311 struct sd *sd = (struct sd *) gspca_dev;
4312
4313 *val = sd->brightness;
4314 return 0;
4315}
4316
4317static int sd_setcontrast(struct gspca_dev *gspca_dev, __s32 val)
4318{
4319 struct sd *sd = (struct sd *) gspca_dev;
4320
4321 sd->contrast = val;
ac40b1fa
JFM		 4322 if (gspca_dev->streaming)
4323 setcontrast(gspca_dev);
6a7eba24
JFM		 4324 return 0;
4325}
4326
4327static int sd_getcontrast(struct gspca_dev *gspca_dev, __s32 *val)
4328{
4329 struct sd *sd = (struct sd *) gspca_dev;
4330
4331 *val = sd->contrast;
4332 return 0;
4333}
4334
4335static int sd_setcolors(struct gspca_dev *gspca_dev, __s32 val)
4336{
4337 struct sd *sd = (struct sd *) gspca_dev;
4338
4339 sd->colors = val;
ac40b1fa
JFM		 4340 if (gspca_dev->streaming)
4341 setcolors(gspca_dev);
6a7eba24
JFM		 4342 return 0;
4343}
4344
4345static int sd_getcolors(struct gspca_dev *gspca_dev, __s32 *val)
4346{
4347 struct sd *sd = (struct sd *) gspca_dev;
4348
4349 *val = sd->colors;
4350 return 0;
4351}
4352
0cd6759d
JFM		 4353static int sd_sethflip(struct gspca_dev *gspca_dev, __s32 val)
4354{
4355 struct sd *sd = (struct sd *) gspca_dev;
4356
4357 sd->hflip = val;
ac40b1fa
JFM		 4358 if (gspca_dev->streaming)
4359 sethvflip(sd);
0cd6759d
JFM		 4360 return 0;
4361}
4362
4363static int sd_gethflip(struct gspca_dev *gspca_dev, __s32 *val)
4364{
4365 struct sd *sd = (struct sd *) gspca_dev;
4366
4367 *val = sd->hflip;
4368 return 0;
4369}
4370
4371static int sd_setvflip(struct gspca_dev *gspca_dev, __s32 val)
4372{
4373 struct sd *sd = (struct sd *) gspca_dev;
4374
4375 sd->vflip = val;
ac40b1fa
JFM		 4376 if (gspca_dev->streaming)
4377 sethvflip(sd);
0cd6759d
JFM		 4378 return 0;
4379}
4380
4381static int sd_getvflip(struct gspca_dev *gspca_dev, __s32 *val)
4382{
4383 struct sd *sd = (struct sd *) gspca_dev;
4384
4385 *val = sd->vflip;
4386 return 0;
4387}
4388
02ab18b0
HG		 4389static int sd_setautobrightness(struct gspca_dev *gspca_dev, __s32 val)
4390{
4391 struct sd *sd = (struct sd *) gspca_dev;
4392
4393 sd->autobrightness = val;
4394 if (gspca_dev->streaming)
4395 setautobrightness(sd);
4396 return 0;
4397}
4398
4399static int sd_getautobrightness(struct gspca_dev *gspca_dev, __s32 *val)
4400{
4401 struct sd *sd = (struct sd *) gspca_dev;
4402
4403 *val = sd->autobrightness;
4404 return 0;
4405}
4406
4407static int sd_setfreq(struct gspca_dev *gspca_dev, __s32 val)
4408{
4409 struct sd *sd = (struct sd *) gspca_dev;
4410
4411 sd->freq = val;
a511ba94 4412 if (gspca_dev->streaming) {
02ab18b0 4413 setfreq(sd);
a511ba94
HG		 4414 /* Ugly but necessary */
4415 if (sd->bridge == BRIDGE_W9968CF)
4416 w9968cf_set_crop_window(sd);
4417 }
02ab18b0
HG		 4418 return 0;
4419}
4420
4421static int sd_getfreq(struct gspca_dev *gspca_dev, __s32 *val)
4422{
4423 struct sd *sd = (struct sd *) gspca_dev;
4424
4425 *val = sd->freq;
4426 return 0;
4427}
4428
4429static int sd_querymenu(struct gspca_dev *gspca_dev,
4430 struct v4l2_querymenu *menu)
4431{
4432 struct sd *sd = (struct sd *) gspca_dev;
4433
4434 switch (menu->id) {
4435 case V4L2_CID_POWER_LINE_FREQUENCY:
4436 switch (menu->index) {
4437 case 0: /* V4L2_CID_POWER_LINE_FREQUENCY_DISABLED */
4438 strcpy((char *) menu->name, "NoFliker");
4439 return 0;
4440 case 1: /* V4L2_CID_POWER_LINE_FREQUENCY_50HZ */
4441 strcpy((char *) menu->name, "50 Hz");
4442 return 0;
4443 case 2: /* V4L2_CID_POWER_LINE_FREQUENCY_60HZ */
4444 strcpy((char *) menu->name, "60 Hz");
4445 return 0;
4446 case 3:
4447 if (sd->sensor != SEN_OV7670)
4448 return -EINVAL;
4449
4450 strcpy((char *) menu->name, "Automatic");
4451 return 0;
4452 }
4453 break;
4454 }
4455 return -EINVAL;
4456}
4457
79b35902
HG		 4458static int sd_get_jcomp(struct gspca_dev *gspca_dev,
4459 struct v4l2_jpegcompression *jcomp)
4460{
4461 struct sd *sd = (struct sd *) gspca_dev;
4462
4463 if (sd->bridge != BRIDGE_W9968CF)
4464 return -EINVAL;
4465
4466 memset(jcomp, 0, sizeof *jcomp);
4467 jcomp->quality = sd->quality;
4468 jcomp->jpeg_markers = V4L2_JPEG_MARKER_DHT | V4L2_JPEG_MARKER_DQT |
4469 V4L2_JPEG_MARKER_DRI;
4470 return 0;
4471}
4472
4473static int sd_set_jcomp(struct gspca_dev *gspca_dev,
4474 struct v4l2_jpegcompression *jcomp)
4475{
4476 struct sd *sd = (struct sd *) gspca_dev;
4477
4478 if (sd->bridge != BRIDGE_W9968CF)
4479 return -EINVAL;
4480
4481 if (gspca_dev->streaming)
4482 return -EBUSY;
4483
4484 if (jcomp->quality < QUALITY_MIN)
4485 sd->quality = QUALITY_MIN;
4486 else if (jcomp->quality > QUALITY_MAX)
4487 sd->quality = QUALITY_MAX;
4488 else
4489 sd->quality = jcomp->quality;
4490
4491 /* Return resulting jcomp params to app */
4492 sd_get_jcomp(gspca_dev, jcomp);
4493
4494 return 0;
4495}
4496
6a7eba24 4497/* sub-driver description */
a5ae2062 4498static const struct sd_desc sd_desc = {
6a7eba24
JFM		 4499 .name = MODULE_NAME,
4500 .ctrls = sd_ctrls,
4501 .nctrls = ARRAY_SIZE(sd_ctrls),
4502 .config = sd_config,
012d6b02 4503 .init = sd_init,
6a7eba24
JFM		 4504 .start = sd_start,
4505 .stopN = sd_stopN,
79b35902 4506 .stop0 = sd_stop0,
6a7eba24 4507 .pkt_scan = sd_pkt_scan,
02ab18b0 4508 .querymenu = sd_querymenu,
79b35902
HG		 4509 .get_jcomp = sd_get_jcomp,
4510 .set_jcomp = sd_set_jcomp,
6a7eba24
JFM		 4511};
4512
4513/* -- module initialisation -- */
a5ae2062 4514static const __devinitdata struct usb_device_id device_table[] = {
a511ba94 4515 {USB_DEVICE(0x041e, 0x4003), .driver_info = BRIDGE_W9968CF },
49809d6a
HG		 4516 {USB_DEVICE(0x041e, 0x4052), .driver_info = BRIDGE_OV519 },
4517 {USB_DEVICE(0x041e, 0x405f), .driver_info = BRIDGE_OV519 },
4518 {USB_DEVICE(0x041e, 0x4060), .driver_info = BRIDGE_OV519 },
4519 {USB_DEVICE(0x041e, 0x4061), .driver_info = BRIDGE_OV519 },
9e4d8258
HG		 4520 {USB_DEVICE(0x041e, 0x4064),
4521 .driver_info = BRIDGE_OV519 | BRIDGE_INVERT_LED },
518c8df7 4522 {USB_DEVICE(0x041e, 0x4067), .driver_info = BRIDGE_OV519 },
9e4d8258
HG		 4523 {USB_DEVICE(0x041e, 0x4068),
4524 .driver_info = BRIDGE_OV519 | BRIDGE_INVERT_LED },
49809d6a
HG		 4525 {USB_DEVICE(0x045e, 0x028c), .driver_info = BRIDGE_OV519 },
4526 {USB_DEVICE(0x054c, 0x0154), .driver_info = BRIDGE_OV519 },
98184f78
HG		 4527 {USB_DEVICE(0x054c, 0x0155),
4528 .driver_info = BRIDGE_OV519 | BRIDGE_INVERT_LED },
1876bb92 4529 {USB_DEVICE(0x05a9, 0x0511), .driver_info = BRIDGE_OV511 },
49809d6a
HG		 4530 {USB_DEVICE(0x05a9, 0x0518), .driver_info = BRIDGE_OV518 },
4531 {USB_DEVICE(0x05a9, 0x0519), .driver_info = BRIDGE_OV519 },
4532 {USB_DEVICE(0x05a9, 0x0530), .driver_info = BRIDGE_OV519 },
b46aaa02 4533 {USB_DEVICE(0x05a9, 0x2800), .driver_info = BRIDGE_OVFX2 },
49809d6a
HG		 4534 {USB_DEVICE(0x05a9, 0x4519), .driver_info = BRIDGE_OV519 },
4535 {USB_DEVICE(0x05a9, 0x8519), .driver_info = BRIDGE_OV519 },
1876bb92 4536 {USB_DEVICE(0x05a9, 0xa511), .driver_info = BRIDGE_OV511PLUS },
49809d6a 4537 {USB_DEVICE(0x05a9, 0xa518), .driver_info = BRIDGE_OV518PLUS },
1876bb92 4538 {USB_DEVICE(0x0813, 0x0002), .driver_info = BRIDGE_OV511PLUS },
b46aaa02
HG		 4539 {USB_DEVICE(0x0b62, 0x0059), .driver_info = BRIDGE_OVFX2 },
4540 {USB_DEVICE(0x0e96, 0xc001), .driver_info = BRIDGE_OVFX2 },
a511ba94 4541 {USB_DEVICE(0x1046, 0x9967), .driver_info = BRIDGE_W9968CF },
b46aaa02 4542 {USB_DEVICE(0x8020, 0xEF04), .driver_info = BRIDGE_OVFX2 },
6a7eba24
JFM		 4543 {}
4544};
ac40b1fa 4545
6a7eba24
JFM		 4546MODULE_DEVICE_TABLE(usb, device_table);
4547
4548/* -- device connect -- */
4549static int sd_probe(struct usb_interface *intf,
4550 const struct usb_device_id *id)
4551{
4552 return gspca_dev_probe(intf, id, &sd_desc, sizeof(struct sd),
4553 THIS_MODULE);
4554}
4555
4556static struct usb_driver sd_driver = {
4557 .name = MODULE_NAME,
4558 .id_table = device_table,
4559 .probe = sd_probe,
4560 .disconnect = gspca_disconnect,
6a709749
JFM		 4561#ifdef CONFIG_PM
4562 .suspend = gspca_suspend,
4563 .resume = gspca_resume,
4564#endif
6a7eba24
JFM		 4565};
4566
4567/* -- module insert / remove -- */
4568static int __init sd_mod_init(void)
4569{
f69e9529
AK		 4570 int ret;
4571 ret = usb_register(&sd_driver);
4572 if (ret < 0)
e6b14849 4573 return ret;
10b0e96e 4574 PDEBUG(D_PROBE, "registered");
6a7eba24
JFM		 4575 return 0;
4576}
4577static void __exit sd_mod_exit(void)
4578{
4579 usb_deregister(&sd_driver);
4580 PDEBUG(D_PROBE, "deregistered");
4581}
4582
4583module_init(sd_mod_init);
4584module_exit(sd_mod_exit);
4585
4586module_param(frame_rate, int, 0644);
4587MODULE_PARM_DESC(frame_rate, "Frame rate (5, 10, 15, 20 or 30 fps)");
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