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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[mirror_ubuntu-bionic-kernel.git] / drivers / media / video / ks0127.c
CommitLineData
fbe60daa
MS		 1/*
2 * Video Capture Driver (Video for Linux 1/2)
3 * for the Matrox Marvel G200,G400 and Rainbow Runner-G series
4 *
5 * This module is an interface to the KS0127 video decoder chip.
6 *
7 * Copyright (C) 1999 Ryan Drake <stiletto@mediaone.net>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 *
23 *****************************************************************************
24 *
25 * Modified and extended by
26 * Mike Bernson <mike@mlb.org>
27 * Gerard v.d. Horst
28 * Leon van Stuivenberg <l.vanstuivenberg@chello.nl>
29 * Gernot Ziegler <gz@lysator.liu.se>
30 *
31 * Version History:
32 * V1.0 Ryan Drake Initial version by Ryan Drake
33 * V1.1 Gerard v.d. Horst Added some debugoutput, reset the video-standard
34 */
35
fbe60daa
MS		 36#include <linux/init.h>
37#include <linux/module.h>
38#include <linux/delay.h>
39#include <linux/errno.h>
40#include <linux/kernel.h>
fbe60daa 41#include <linux/i2c.h>
0750e971 42#include <linux/videodev2.h>
5a0e3ad6 43#include <linux/slab.h>
0750e971
HV		 44#include <media/v4l2-device.h>
45#include <media/v4l2-chip-ident.h>
2d26698e 46#include <media/v4l2-i2c-drv.h>
9875c0fb 47#include "ks0127.h"
fbe60daa 48
9875c0fb
HV		 49MODULE_DESCRIPTION("KS0127 video decoder driver");
50MODULE_AUTHOR("Ryan Drake");
51MODULE_LICENSE("GPL");
fbe60daa 52
2d26698e 53/* Addresses */
0750e971
HV		 54#define I2C_KS0127_ADDON 0xD8
55#define I2C_KS0127_ONBOARD 0xDA
56
fbe60daa
MS		 57
58/* ks0127 control registers */
59#define KS_STAT 0x00
60#define KS_CMDA 0x01
61#define KS_CMDB 0x02
62#define KS_CMDC 0x03
63#define KS_CMDD 0x04
64#define KS_HAVB 0x05
65#define KS_HAVE 0x06
66#define KS_HS1B 0x07
67#define KS_HS1E 0x08
68#define KS_HS2B 0x09
69#define KS_HS2E 0x0a
70#define KS_AGC 0x0b
71#define KS_HXTRA 0x0c
72#define KS_CDEM 0x0d
73#define KS_PORTAB 0x0e
74#define KS_LUMA 0x0f
75#define KS_CON 0x10
76#define KS_BRT 0x11
77#define KS_CHROMA 0x12
78#define KS_CHROMB 0x13
79#define KS_DEMOD 0x14
80#define KS_SAT 0x15
81#define KS_HUE 0x16
82#define KS_VERTIA 0x17
83#define KS_VERTIB 0x18
84#define KS_VERTIC 0x19
85#define KS_HSCLL 0x1a
86#define KS_HSCLH 0x1b
87#define KS_VSCLL 0x1c
88#define KS_VSCLH 0x1d
89#define KS_OFMTA 0x1e
90#define KS_OFMTB 0x1f
91#define KS_VBICTL 0x20
92#define KS_CCDAT2 0x21
93#define KS_CCDAT1 0x22
94#define KS_VBIL30 0x23
95#define KS_VBIL74 0x24
96#define KS_VBIL118 0x25
97#define KS_VBIL1512 0x26
98#define KS_TTFRAM 0x27
99#define KS_TESTA 0x28
100#define KS_UVOFFH 0x29
101#define KS_UVOFFL 0x2a
102#define KS_UGAIN 0x2b
103#define KS_VGAIN 0x2c
104#define KS_VAVB 0x2d
105#define KS_VAVE 0x2e
106#define KS_CTRACK 0x2f
107#define KS_POLCTL 0x30
108#define KS_REFCOD 0x31
109#define KS_INVALY 0x32
110#define KS_INVALU 0x33
111#define KS_INVALV 0x34
112#define KS_UNUSEY 0x35
113#define KS_UNUSEU 0x36
114#define KS_UNUSEV 0x37
115#define KS_USRSAV 0x38
116#define KS_USREAV 0x39
117#define KS_SHS1A 0x3a
118#define KS_SHS1B 0x3b
119#define KS_SHS1C 0x3c
120#define KS_CMDE 0x3d
121#define KS_VSDEL 0x3e
122#define KS_CMDF 0x3f
123#define KS_GAMMA0 0x40
124#define KS_GAMMA1 0x41
125#define KS_GAMMA2 0x42
126#define KS_GAMMA3 0x43
127#define KS_GAMMA4 0x44
128#define KS_GAMMA5 0x45
129#define KS_GAMMA6 0x46
130#define KS_GAMMA7 0x47
131#define KS_GAMMA8 0x48
132#define KS_GAMMA9 0x49
133#define KS_GAMMA10 0x4a
134#define KS_GAMMA11 0x4b
135#define KS_GAMMA12 0x4c
136#define KS_GAMMA13 0x4d
137#define KS_GAMMA14 0x4e
138#define KS_GAMMA15 0x4f
139#define KS_GAMMA16 0x50
140#define KS_GAMMA17 0x51
141#define KS_GAMMA18 0x52
142#define KS_GAMMA19 0x53
143#define KS_GAMMA20 0x54
144#define KS_GAMMA21 0x55
145#define KS_GAMMA22 0x56
146#define KS_GAMMA23 0x57
147#define KS_GAMMA24 0x58
148#define KS_GAMMA25 0x59
149#define KS_GAMMA26 0x5a
150#define KS_GAMMA27 0x5b
151#define KS_GAMMA28 0x5c
152#define KS_GAMMA29 0x5d
153#define KS_GAMMA30 0x5e
154#define KS_GAMMA31 0x5f
155#define KS_GAMMAD0 0x60
156#define KS_GAMMAD1 0x61
157#define KS_GAMMAD2 0x62
158#define KS_GAMMAD3 0x63
159#define KS_GAMMAD4 0x64
160#define KS_GAMMAD5 0x65
161#define KS_GAMMAD6 0x66
162#define KS_GAMMAD7 0x67
163#define KS_GAMMAD8 0x68
164#define KS_GAMMAD9 0x69
165#define KS_GAMMAD10 0x6a
166#define KS_GAMMAD11 0x6b
167#define KS_GAMMAD12 0x6c
168#define KS_GAMMAD13 0x6d
169#define KS_GAMMAD14 0x6e
170#define KS_GAMMAD15 0x6f
171#define KS_GAMMAD16 0x70
172#define KS_GAMMAD17 0x71
173#define KS_GAMMAD18 0x72
174#define KS_GAMMAD19 0x73
175#define KS_GAMMAD20 0x74
176#define KS_GAMMAD21 0x75
177#define KS_GAMMAD22 0x76
178#define KS_GAMMAD23 0x77
179#define KS_GAMMAD24 0x78
180#define KS_GAMMAD25 0x79
181#define KS_GAMMAD26 0x7a
182#define KS_GAMMAD27 0x7b
183#define KS_GAMMAD28 0x7c
184#define KS_GAMMAD29 0x7d
185#define KS_GAMMAD30 0x7e
186#define KS_GAMMAD31 0x7f
187
188
189/****************************************************************************
190* mga_dev : represents one ks0127 chip.
191****************************************************************************/
192
193struct adjust {
194 int contrast;
195 int bright;
196 int hue;
197 int ugain;
198 int vgain;
199};
200
201struct ks0127 {
0750e971 202 struct v4l2_subdev sd;
107063c6 203 v4l2_std_id norm;
0750e971 204 int ident;
fbe60daa
MS		 205 u8 regs[256];
206};
207
0750e971
HV		 208static inline struct ks0127 *to_ks0127(struct v4l2_subdev *sd)
209{
210 return container_of(sd, struct ks0127, sd);
211}
212
fbe60daa
MS		 213
214static int debug; /* insmod parameter */
215
216module_param(debug, int, 0);
217MODULE_PARM_DESC(debug, "Debug output");
fbe60daa
MS		 218
219static u8 reg_defaults[64];
220
fbe60daa
MS		 221static void init_reg_defaults(void)
222{
9875c0fb 223 static int initialized;
fbe60daa
MS		 224 u8 *table = reg_defaults;
225
9875c0fb
HV		 226 if (initialized)
227 return;
228 initialized = 1;
229
fbe60daa
MS		 230 table[KS_CMDA] = 0x2c; /* VSE=0, CCIR 601, autodetect standard */
231 table[KS_CMDB] = 0x12; /* VALIGN=0, AGC control and input */
232 table[KS_CMDC] = 0x00; /* Test options */
233 /* clock & input select, write 1 to PORTA */
234 table[KS_CMDD] = 0x01;
235 table[KS_HAVB] = 0x00; /* HAV Start Control */
236 table[KS_HAVE] = 0x00; /* HAV End Control */
237 table[KS_HS1B] = 0x10; /* HS1 Start Control */
238 table[KS_HS1E] = 0x00; /* HS1 End Control */
239 table[KS_HS2B] = 0x00; /* HS2 Start Control */
240 table[KS_HS2E] = 0x00; /* HS2 End Control */
241 table[KS_AGC] = 0x53; /* Manual setting for AGC */
242 table[KS_HXTRA] = 0x00; /* Extra Bits for HAV and HS1/2 */
243 table[KS_CDEM] = 0x00; /* Chroma Demodulation Control */
244 table[KS_PORTAB] = 0x0f; /* port B is input, port A output GPPORT */
245 table[KS_LUMA] = 0x01; /* Luma control */
246 table[KS_CON] = 0x00; /* Contrast Control */
247 table[KS_BRT] = 0x00; /* Brightness Control */
248 table[KS_CHROMA] = 0x2a; /* Chroma control A */
249 table[KS_CHROMB] = 0x90; /* Chroma control B */
250 table[KS_DEMOD] = 0x00; /* Chroma Demodulation Control & Status */
251 table[KS_SAT] = 0x00; /* Color Saturation Control*/
252 table[KS_HUE] = 0x00; /* Hue Control */
253 table[KS_VERTIA] = 0x00; /* Vertical Processing Control A */
254 /* Vertical Processing Control B, luma 1 line delayed */
255 table[KS_VERTIB] = 0x12;
256 table[KS_VERTIC] = 0x0b; /* Vertical Processing Control C */
257 table[KS_HSCLL] = 0x00; /* Horizontal Scaling Ratio Low */
258 table[KS_HSCLH] = 0x00; /* Horizontal Scaling Ratio High */
259 table[KS_VSCLL] = 0x00; /* Vertical Scaling Ratio Low */
260 table[KS_VSCLH] = 0x00; /* Vertical Scaling Ratio High */
261 /* 16 bit YCbCr 4:2:2 output; I can't make the bt866 like 8 bit /Sam */
262 table[KS_OFMTA] = 0x30;
263 table[KS_OFMTB] = 0x00; /* Output Control B */
264 /* VBI Decoder Control; 4bit fmt: avoid Y overflow */
265 table[KS_VBICTL] = 0x5d;
266 table[KS_CCDAT2] = 0x00; /* Read Only register */
267 table[KS_CCDAT1] = 0x00; /* Read Only register */
268 table[KS_VBIL30] = 0xa8; /* VBI data decoding options */
269 table[KS_VBIL74] = 0xaa; /* VBI data decoding options */
270 table[KS_VBIL118] = 0x2a; /* VBI data decoding options */
271 table[KS_VBIL1512] = 0x00; /* VBI data decoding options */
272 table[KS_TTFRAM] = 0x00; /* Teletext frame alignment pattern */
273 table[KS_TESTA] = 0x00; /* test register, shouldn't be written */
274 table[KS_UVOFFH] = 0x00; /* UV Offset Adjustment High */
275 table[KS_UVOFFL] = 0x00; /* UV Offset Adjustment Low */
276 table[KS_UGAIN] = 0x00; /* U Component Gain Adjustment */
277 table[KS_VGAIN] = 0x00; /* V Component Gain Adjustment */
278 table[KS_VAVB] = 0x07; /* VAV Begin */
279 table[KS_VAVE] = 0x00; /* VAV End */
280 table[KS_CTRACK] = 0x00; /* Chroma Tracking Control */
281 table[KS_POLCTL] = 0x41; /* Timing Signal Polarity Control */
282 table[KS_REFCOD] = 0x80; /* Reference Code Insertion Control */
283 table[KS_INVALY] = 0x10; /* Invalid Y Code */
284 table[KS_INVALU] = 0x80; /* Invalid U Code */
285 table[KS_INVALV] = 0x80; /* Invalid V Code */
286 table[KS_UNUSEY] = 0x10; /* Unused Y Code */
287 table[KS_UNUSEU] = 0x80; /* Unused U Code */
288 table[KS_UNUSEV] = 0x80; /* Unused V Code */
289 table[KS_USRSAV] = 0x00; /* reserved */
290 table[KS_USREAV] = 0x00; /* reserved */
291 table[KS_SHS1A] = 0x00; /* User Defined SHS1 A */
292 /* User Defined SHS1 B, ALT656=1 on 0127B */
293 table[KS_SHS1B] = 0x80;
294 table[KS_SHS1C] = 0x00; /* User Defined SHS1 C */
295 table[KS_CMDE] = 0x00; /* Command Register E */
296 table[KS_VSDEL] = 0x00; /* VS Delay Control */
297 /* Command Register F, update -immediately- */
298 /* (there might come no vsync)*/
299 table[KS_CMDF] = 0x02;
300}
301
302
303/* We need to manually read because of a bug in the KS0127 chip.
304 *
305 * An explanation from kayork@mail.utexas.edu:
306 *
307 * During I2C reads, the KS0127 only samples for a stop condition
9875c0fb 308 * during the place where the acknowledge bit should be. Any standard
fbe60daa
MS		 309 * I2C implementation (correctly) throws in another clock transition
310 * at the 9th bit, and the KS0127 will not recognize the stop condition
311 * and will continue to clock out data.
312 *
313 * So we have to do the read ourself. Big deal.
9875c0fb 314 * workaround in i2c-algo-bit
fbe60daa
MS		 315 */
316
317
0750e971 318static u8 ks0127_read(struct v4l2_subdev *sd, u8 reg)
fbe60daa 319{
0750e971 320 struct i2c_client *client = v4l2_get_subdevdata(sd);
fbe60daa
MS		 321 char val = 0;
322 struct i2c_msg msgs[] = {
0750e971
HV		 323 { client->addr, 0, sizeof(reg), &reg },
324 { client->addr, I2C_M_RD | I2C_M_NO_RD_ACK, sizeof(val), &val }
9875c0fb 325 };
fbe60daa
MS		 326 int ret;
327
0750e971 328 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
fbe60daa 329 if (ret != ARRAY_SIZE(msgs))
0750e971 330 v4l2_dbg(1, debug, sd, "read error\n");
fbe60daa
MS		 331
332 return val;
333}
334
335
0750e971 336static void ks0127_write(struct v4l2_subdev *sd, u8 reg, u8 val)
fbe60daa 337{
0750e971
HV		 338 struct i2c_client *client = v4l2_get_subdevdata(sd);
339 struct ks0127 *ks = to_ks0127(sd);
9875c0fb 340 char msg[] = { reg, val };
fbe60daa 341
0750e971
HV		 342 if (i2c_master_send(client, msg, sizeof(msg)) != sizeof(msg))
343 v4l2_dbg(1, debug, sd, "write error\n");
fbe60daa
MS		 344
345 ks->regs[reg] = val;
346}
347
348
349/* generic bit-twiddling */
0750e971 350static void ks0127_and_or(struct v4l2_subdev *sd, u8 reg, u8 and_v, u8 or_v)
fbe60daa 351{
0750e971 352 struct ks0127 *ks = to_ks0127(sd);
9875c0fb 353
fbe60daa
MS		 354 u8 val = ks->regs[reg];
355 val = (val & and_v) | or_v;
0750e971 356 ks0127_write(sd, reg, val);
fbe60daa
MS		 357}
358
359
360
361/****************************************************************************
362* ks0127 private api
363****************************************************************************/
0750e971 364static void ks0127_init(struct v4l2_subdev *sd)
fbe60daa 365{
0750e971 366 struct ks0127 *ks = to_ks0127(sd);
fbe60daa 367 u8 *table = reg_defaults;
9875c0fb 368 int i;
fbe60daa 369
0750e971 370 ks->ident = V4L2_IDENT_KS0127;
fbe60daa 371
0750e971 372 v4l2_dbg(1, debug, sd, "reset\n");
fbe60daa
MS		 373 msleep(1);
374
375 /* initialize all registers to known values */
376 /* (except STAT, 0x21, 0x22, TEST and 0x38,0x39) */
377
9875c0fb 378 for (i = 1; i < 33; i++)
0750e971 379 ks0127_write(sd, i, table[i]);
fbe60daa 380
9875c0fb 381 for (i = 35; i < 40; i++)
0750e971 382 ks0127_write(sd, i, table[i]);
fbe60daa 383
9875c0fb 384 for (i = 41; i < 56; i++)
0750e971 385 ks0127_write(sd, i, table[i]);
fbe60daa 386
9875c0fb 387 for (i = 58; i < 64; i++)
0750e971 388 ks0127_write(sd, i, table[i]);
fbe60daa
MS		 389
390
0750e971
HV		 391 if ((ks0127_read(sd, KS_STAT) & 0x80) == 0) {
392 ks->ident = V4L2_IDENT_KS0122S;
393 v4l2_dbg(1, debug, sd, "ks0122s found\n");
fbe60daa
MS		 394 return;
395 }
396
0750e971 397 switch (ks0127_read(sd, KS_CMDE) & 0x0f) {
fbe60daa 398 case 0:
0750e971 399 v4l2_dbg(1, debug, sd, "ks0127 found\n");
fbe60daa
MS		 400 break;
401
402 case 9:
0750e971
HV		 403 ks->ident = V4L2_IDENT_KS0127B;
404 v4l2_dbg(1, debug, sd, "ks0127B Revision A found\n");
fbe60daa
MS		 405 break;
406
407 default:
0750e971 408 v4l2_dbg(1, debug, sd, "unknown revision\n");
fbe60daa
MS		 409 break;
410 }
411}
412
5325b427
HV		 413static int ks0127_s_routing(struct v4l2_subdev *sd,
414 u32 input, u32 output, u32 config)
fbe60daa 415{
0750e971
HV		 416 struct ks0127 *ks = to_ks0127(sd);
417
5325b427 418 switch (input) {
0750e971
HV		 419 case KS_INPUT_COMPOSITE_1:
420 case KS_INPUT_COMPOSITE_2:
421 case KS_INPUT_COMPOSITE_3:
422 case KS_INPUT_COMPOSITE_4:
423 case KS_INPUT_COMPOSITE_5:
424 case KS_INPUT_COMPOSITE_6:
425 v4l2_dbg(1, debug, sd,
5325b427 426 "s_routing %d: Composite\n", input);
0750e971
HV		 427 /* autodetect 50/60 Hz */
428 ks0127_and_or(sd, KS_CMDA, 0xfc, 0x00);
429 /* VSE=0 */
430 ks0127_and_or(sd, KS_CMDA, ~0x40, 0x00);
431 /* set input line */
5325b427 432 ks0127_and_or(sd, KS_CMDB, 0xb0, input);
0750e971
HV		 433 /* non-freerunning mode */
434 ks0127_and_or(sd, KS_CMDC, 0x70, 0x0a);
435 /* analog input */
436 ks0127_and_or(sd, KS_CMDD, 0x03, 0x00);
437 /* enable chroma demodulation */
438 ks0127_and_or(sd, KS_CTRACK, 0xcf, 0x00);
439 /* chroma trap, HYBWR=1 */
440 ks0127_and_or(sd, KS_LUMA, 0x00,
441 (reg_defaults[KS_LUMA])|0x0c);
442 /* scaler fullbw, luma comb off */
443 ks0127_and_or(sd, KS_VERTIA, 0x08, 0x81);
444 /* manual chroma comb .25 .5 .25 */
445 ks0127_and_or(sd, KS_VERTIC, 0x0f, 0x90);
446
447 /* chroma path delay */
448 ks0127_and_or(sd, KS_CHROMB, 0x0f, 0x90);
449
450 ks0127_write(sd, KS_UGAIN, reg_defaults[KS_UGAIN]);
451 ks0127_write(sd, KS_VGAIN, reg_defaults[KS_VGAIN]);
452 ks0127_write(sd, KS_UVOFFH, reg_defaults[KS_UVOFFH]);
453 ks0127_write(sd, KS_UVOFFL, reg_defaults[KS_UVOFFL]);
fbe60daa
MS		 454 break;
455
0750e971
HV		 456 case KS_INPUT_SVIDEO_1:
457 case KS_INPUT_SVIDEO_2:
458 case KS_INPUT_SVIDEO_3:
459 v4l2_dbg(1, debug, sd,
5325b427 460 "s_routing %d: S-Video\n", input);
0750e971
HV		 461 /* autodetect 50/60 Hz */
462 ks0127_and_or(sd, KS_CMDA, 0xfc, 0x00);
463 /* VSE=0 */
464 ks0127_and_or(sd, KS_CMDA, ~0x40, 0x00);
465 /* set input line */
5325b427 466 ks0127_and_or(sd, KS_CMDB, 0xb0, input);
0750e971
HV		 467 /* non-freerunning mode */
468 ks0127_and_or(sd, KS_CMDC, 0x70, 0x0a);
469 /* analog input */
470 ks0127_and_or(sd, KS_CMDD, 0x03, 0x00);
471 /* enable chroma demodulation */
472 ks0127_and_or(sd, KS_CTRACK, 0xcf, 0x00);
473 ks0127_and_or(sd, KS_LUMA, 0x00,
474 reg_defaults[KS_LUMA]);
475 /* disable luma comb */
476 ks0127_and_or(sd, KS_VERTIA, 0x08,
477 (reg_defaults[KS_VERTIA]&0xf0)|0x01);
478 ks0127_and_or(sd, KS_VERTIC, 0x0f,
479 reg_defaults[KS_VERTIC]&0xf0);
480
481 ks0127_and_or(sd, KS_CHROMB, 0x0f,
482 reg_defaults[KS_CHROMB]&0xf0);
483
484 ks0127_write(sd, KS_UGAIN, reg_defaults[KS_UGAIN]);
485 ks0127_write(sd, KS_VGAIN, reg_defaults[KS_VGAIN]);
486 ks0127_write(sd, KS_UVOFFH, reg_defaults[KS_UVOFFH]);
487 ks0127_write(sd, KS_UVOFFL, reg_defaults[KS_UVOFFL]);
fbe60daa
MS		 488 break;
489
0750e971 490 case KS_INPUT_YUV656:
bccfa449 491 v4l2_dbg(1, debug, sd, "s_routing 15: YUV656\n");
0750e971
HV		 492 if (ks->norm & V4L2_STD_525_60)
493 /* force 60 Hz */
494 ks0127_and_or(sd, KS_CMDA, 0xfc, 0x03);
495 else
496 /* force 50 Hz */
497 ks0127_and_or(sd, KS_CMDA, 0xfc, 0x02);
498
499 ks0127_and_or(sd, KS_CMDA, 0xff, 0x40); /* VSE=1 */
500 /* set input line and VALIGN */
5325b427 501 ks0127_and_or(sd, KS_CMDB, 0xb0, (input | 0x40));
0750e971
HV		 502 /* freerunning mode, */
503 /* TSTGEN = 1 TSTGFR=11 TSTGPH=0 TSTGPK=0 VMEM=1*/
504 ks0127_and_or(sd, KS_CMDC, 0x70, 0x87);
505 /* digital input, SYNDIR = 0 INPSL=01 CLKDIR=0 EAV=0 */
506 ks0127_and_or(sd, KS_CMDD, 0x03, 0x08);
507 /* disable chroma demodulation */
508 ks0127_and_or(sd, KS_CTRACK, 0xcf, 0x30);
509 /* HYPK =01 CTRAP = 0 HYBWR=0 PED=1 RGBH=1 UNIT=1 */
510 ks0127_and_or(sd, KS_LUMA, 0x00, 0x71);
511 ks0127_and_or(sd, KS_VERTIC, 0x0f,
512 reg_defaults[KS_VERTIC]&0xf0);
513
514 /* scaler fullbw, luma comb off */
515 ks0127_and_or(sd, KS_VERTIA, 0x08, 0x81);
516
517 ks0127_and_or(sd, KS_CHROMB, 0x0f,
518 reg_defaults[KS_CHROMB]&0xf0);
519
520 ks0127_and_or(sd, KS_CON, 0x00, 0x00);
521 ks0127_and_or(sd, KS_BRT, 0x00, 32); /* spec: 34 */
522 /* spec: 229 (e5) */
523 ks0127_and_or(sd, KS_SAT, 0x00, 0xe8);
524 ks0127_and_or(sd, KS_HUE, 0x00, 0);
525
526 ks0127_and_or(sd, KS_UGAIN, 0x00, 238);
527 ks0127_and_or(sd, KS_VGAIN, 0x00, 0x00);
528
529 /*UOFF:0x30, VOFF:0x30, TSTCGN=1 */
530 ks0127_and_or(sd, KS_UVOFFH, 0x00, 0x4f);
531 ks0127_and_or(sd, KS_UVOFFL, 0x00, 0x00);
fbe60daa
MS		 532 break;
533
0750e971
HV		 534 default:
535 v4l2_dbg(1, debug, sd,
5325b427 536 "s_routing: Unknown input %d\n", input);
fbe60daa 537 break;
9875c0fb 538 }
fbe60daa 539
0750e971
HV		 540 /* hack: CDMLPF sometimes spontaneously switches on; */
541 /* force back off */
542 ks0127_write(sd, KS_DEMOD, reg_defaults[KS_DEMOD]);
543 return 0;
544}
545
546static int ks0127_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
547{
548 struct ks0127 *ks = to_ks0127(sd);
549
550 /* Set to automatic SECAM/Fsc mode */
551 ks0127_and_or(sd, KS_DEMOD, 0xf0, 0x00);
552
553 ks->norm = std;
554 if (std & V4L2_STD_NTSC) {
555 v4l2_dbg(1, debug, sd,
bccfa449 556 "s_std: NTSC_M\n");
0750e971
HV		 557 ks0127_and_or(sd, KS_CHROMA, 0x9f, 0x20);
558 } else if (std & V4L2_STD_PAL_N) {
559 v4l2_dbg(1, debug, sd,
bccfa449 560 "s_std: NTSC_N (fixme)\n");
0750e971
HV		 561 ks0127_and_or(sd, KS_CHROMA, 0x9f, 0x40);
562 } else if (std & V4L2_STD_PAL) {
563 v4l2_dbg(1, debug, sd,
bccfa449 564 "s_std: PAL_N\n");
0750e971
HV		 565 ks0127_and_or(sd, KS_CHROMA, 0x9f, 0x20);
566 } else if (std & V4L2_STD_PAL_M) {
567 v4l2_dbg(1, debug, sd,
bccfa449 568 "s_std: PAL_M (fixme)\n");
0750e971
HV		 569 ks0127_and_or(sd, KS_CHROMA, 0x9f, 0x40);
570 } else if (std & V4L2_STD_SECAM) {
571 v4l2_dbg(1, debug, sd,
bccfa449 572 "s_std: SECAM\n");
0750e971
HV		 573
574 /* set to secam autodetection */
575 ks0127_and_or(sd, KS_CHROMA, 0xdf, 0x20);
576 ks0127_and_or(sd, KS_DEMOD, 0xf0, 0x00);
577 schedule_timeout_interruptible(HZ/10+1);
578
579 /* did it autodetect? */
580 if (!(ks0127_read(sd, KS_DEMOD) & 0x40))
581 /* force to secam mode */
582 ks0127_and_or(sd, KS_DEMOD, 0xf0, 0x0f);
583 } else {
bccfa449 584 v4l2_dbg(1, debug, sd, "s_std: Unknown norm %llx\n",
cc5cef8e 585 (unsigned long long)std);
107063c6 586 }
0750e971
HV		 587 return 0;
588}
fbe60daa 589
0750e971
HV		 590static int ks0127_s_stream(struct v4l2_subdev *sd, int enable)
591{
592 v4l2_dbg(1, debug, sd, "s_stream(%d)\n", enable);
593 if (enable) {
594 /* All output pins on */
595 ks0127_and_or(sd, KS_OFMTA, 0xcf, 0x30);
596 /* Obey the OEN pin */
597 ks0127_and_or(sd, KS_CDEM, 0x7f, 0x00);
598 } else {
599 /* Video output pins off */
600 ks0127_and_or(sd, KS_OFMTA, 0xcf, 0x00);
601 /* Ignore the OEN pin */
602 ks0127_and_or(sd, KS_CDEM, 0x7f, 0x80);
fbe60daa
MS		 603 }
604 return 0;
605}
606
0750e971
HV		 607static int ks0127_status(struct v4l2_subdev *sd, u32 *pstatus, v4l2_std_id *pstd)
608{
609 int stat = V4L2_IN_ST_NO_SIGNAL;
610 u8 status;
611 v4l2_std_id std = V4L2_STD_ALL;
612
0750e971
HV		 613 status = ks0127_read(sd, KS_STAT);
614 if (!(status & 0x20)) /* NOVID not set */
615 stat = 0;
616 if (!(status & 0x01)) /* CLOCK set */
617 stat |= V4L2_IN_ST_NO_COLOR;
618 if ((status & 0x08)) /* PALDET set */
619 std = V4L2_STD_PAL;
620 else
621 std = V4L2_STD_NTSC;
622 if (pstd)
623 *pstd = std;
624 if (pstatus)
625 *pstatus = stat;
626 return 0;
627}
fbe60daa 628
0750e971
HV		 629static int ks0127_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
630{
bccfa449 631 v4l2_dbg(1, debug, sd, "querystd\n");
0750e971
HV		 632 return ks0127_status(sd, NULL, std);
633}
fbe60daa 634
0750e971
HV		 635static int ks0127_g_input_status(struct v4l2_subdev *sd, u32 *status)
636{
bccfa449 637 v4l2_dbg(1, debug, sd, "g_input_status\n");
0750e971
HV		 638 return ks0127_status(sd, status, NULL);
639}
640
641static int ks0127_g_chip_ident(struct v4l2_subdev *sd, struct v4l2_dbg_chip_ident *chip)
642{
643 struct i2c_client *client = v4l2_get_subdevdata(sd);
644 struct ks0127 *ks = to_ks0127(sd);
645
646 return v4l2_chip_ident_i2c_client(client, chip, ks->ident, 0);
647}
648
0750e971
HV		 649/* ----------------------------------------------------------------------- */
650
651static const struct v4l2_subdev_core_ops ks0127_core_ops = {
652 .g_chip_ident = ks0127_g_chip_ident,
0750e971
HV		 653 .s_std = ks0127_s_std,
654};
655
656static const struct v4l2_subdev_video_ops ks0127_video_ops = {
657 .s_routing = ks0127_s_routing,
658 .s_stream = ks0127_s_stream,
659 .querystd = ks0127_querystd,
660 .g_input_status = ks0127_g_input_status,
661};
fbe60daa 662
0750e971
HV		 663static const struct v4l2_subdev_ops ks0127_ops = {
664 .core = &ks0127_core_ops,
0750e971
HV		 665 .video = &ks0127_video_ops,
666};
667
668/* ----------------------------------------------------------------------- */
669
670
671static int ks0127_probe(struct i2c_client *client, const struct i2c_device_id *id)
fbe60daa
MS		 672{
673 struct ks0127 *ks;
0750e971 674 struct v4l2_subdev *sd;
fbe60daa 675
0750e971
HV		 676 v4l_info(client, "%s chip found @ 0x%x (%s)\n",
677 client->addr == (I2C_KS0127_ADDON >> 1) ? "addon" : "on-board",
678 client->addr << 1, client->adapter->name);
fbe60daa
MS		 679
680 ks = kzalloc(sizeof(*ks), GFP_KERNEL);
9875c0fb 681 if (ks == NULL)
fbe60daa 682 return -ENOMEM;
0750e971
HV		 683 sd = &ks->sd;
684 v4l2_i2c_subdev_init(sd, client, &ks0127_ops);
fbe60daa
MS		 685
686 /* power up */
9875c0fb 687 init_reg_defaults();
0750e971 688 ks0127_write(sd, KS_CMDA, 0x2c);
fbe60daa
MS		 689 mdelay(10);
690
691 /* reset the device */
0750e971 692 ks0127_init(sd);
fbe60daa
MS		 693 return 0;
694}
695
0750e971 696static int ks0127_remove(struct i2c_client *client)
fbe60daa 697{
0750e971 698 struct v4l2_subdev *sd = i2c_get_clientdata(client);
fbe60daa 699
0750e971
HV		 700 v4l2_device_unregister_subdev(sd);
701 ks0127_write(sd, KS_OFMTA, 0x20); /* tristate */
702 ks0127_write(sd, KS_CMDA, 0x2c | 0x80); /* power down */
703 kfree(to_ks0127(sd));
fbe60daa
MS		 704 return 0;
705}
706
9875c0fb
HV		 707static const struct i2c_device_id ks0127_id[] = {
708 { "ks0127", 0 },
18d135ad
HV		 709 { "ks0127b", 0 },
710 { "ks0122s", 0 },
9875c0fb
HV		 711 { }
712};
713MODULE_DEVICE_TABLE(i2c, ks0127_id);
714
715static struct v4l2_i2c_driver_data v4l2_i2c_data = {
716 .name = "ks0127",
9875c0fb
HV		 717 .probe = ks0127_probe,
718 .remove = ks0127_remove,
9875c0fb
HV		 719 .id_table = ks0127_id,
720};
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