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[media] V4L: mt9m111: remove superfluous soc-camera client operations
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CommitLineData
77110abb 1/*
c8cf078e 2 * Driver for MT9M111/MT9M112/MT9M131 CMOS Image Sensor from Micron/Aptina
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3 *
4 * Copyright (C) 2008, Robert Jarzmik <robert.jarzmik@free.fr>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/videodev2.h>
11#include <linux/slab.h>
12#include <linux/i2c.h>
13#include <linux/log2.h>
14#include <linux/gpio.h>
15#include <linux/delay.h>
16
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17#include <media/soc_camera.h>
18#include <media/soc_mediabus.h>
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19#include <media/v4l2-common.h>
20#include <media/v4l2-chip-ident.h>
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21
22/*
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23 * MT9M111, MT9M112 and MT9M131:
24 * i2c address is 0x48 or 0x5d (depending on SADDR pin)
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25 * The platform has to define i2c_board_info and call i2c_register_board_info()
26 */
27
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28/*
29 * Sensor core register addresses (0x000..0x0ff)
30 */
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31#define MT9M111_CHIP_VERSION 0x000
32#define MT9M111_ROW_START 0x001
33#define MT9M111_COLUMN_START 0x002
34#define MT9M111_WINDOW_HEIGHT 0x003
35#define MT9M111_WINDOW_WIDTH 0x004
36#define MT9M111_HORIZONTAL_BLANKING_B 0x005
37#define MT9M111_VERTICAL_BLANKING_B 0x006
38#define MT9M111_HORIZONTAL_BLANKING_A 0x007
39#define MT9M111_VERTICAL_BLANKING_A 0x008
40#define MT9M111_SHUTTER_WIDTH 0x009
41#define MT9M111_ROW_SPEED 0x00a
42#define MT9M111_EXTRA_DELAY 0x00b
43#define MT9M111_SHUTTER_DELAY 0x00c
44#define MT9M111_RESET 0x00d
45#define MT9M111_READ_MODE_B 0x020
46#define MT9M111_READ_MODE_A 0x021
47#define MT9M111_FLASH_CONTROL 0x023
48#define MT9M111_GREEN1_GAIN 0x02b
49#define MT9M111_BLUE_GAIN 0x02c
50#define MT9M111_RED_GAIN 0x02d
51#define MT9M111_GREEN2_GAIN 0x02e
52#define MT9M111_GLOBAL_GAIN 0x02f
53#define MT9M111_CONTEXT_CONTROL 0x0c8
54#define MT9M111_PAGE_MAP 0x0f0
55#define MT9M111_BYTE_WISE_ADDR 0x0f1
56
57#define MT9M111_RESET_SYNC_CHANGES (1 << 15)
58#define MT9M111_RESET_RESTART_BAD_FRAME (1 << 9)
59#define MT9M111_RESET_SHOW_BAD_FRAMES (1 << 8)
60#define MT9M111_RESET_RESET_SOC (1 << 5)
61#define MT9M111_RESET_OUTPUT_DISABLE (1 << 4)
62#define MT9M111_RESET_CHIP_ENABLE (1 << 3)
63#define MT9M111_RESET_ANALOG_STANDBY (1 << 2)
64#define MT9M111_RESET_RESTART_FRAME (1 << 1)
65#define MT9M111_RESET_RESET_MODE (1 << 0)
66
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67#define MT9M111_RM_FULL_POWER_RD (0 << 10)
68#define MT9M111_RM_LOW_POWER_RD (1 << 10)
69#define MT9M111_RM_COL_SKIP_4X (1 << 5)
70#define MT9M111_RM_ROW_SKIP_4X (1 << 4)
71#define MT9M111_RM_COL_SKIP_2X (1 << 3)
72#define MT9M111_RM_ROW_SKIP_2X (1 << 2)
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73#define MT9M111_RMB_MIRROR_COLS (1 << 1)
74#define MT9M111_RMB_MIRROR_ROWS (1 << 0)
75#define MT9M111_CTXT_CTRL_RESTART (1 << 15)
76#define MT9M111_CTXT_CTRL_DEFECTCOR_B (1 << 12)
77#define MT9M111_CTXT_CTRL_RESIZE_B (1 << 10)
78#define MT9M111_CTXT_CTRL_CTRL2_B (1 << 9)
79#define MT9M111_CTXT_CTRL_GAMMA_B (1 << 8)
80#define MT9M111_CTXT_CTRL_XENON_EN (1 << 7)
81#define MT9M111_CTXT_CTRL_READ_MODE_B (1 << 3)
82#define MT9M111_CTXT_CTRL_LED_FLASH_EN (1 << 2)
83#define MT9M111_CTXT_CTRL_VBLANK_SEL_B (1 << 1)
84#define MT9M111_CTXT_CTRL_HBLANK_SEL_B (1 << 0)
c8cf078e 85
77110abb 86/*
c8cf078e 87 * Colorpipe register addresses (0x100..0x1ff)
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88 */
89#define MT9M111_OPER_MODE_CTRL 0x106
90#define MT9M111_OUTPUT_FORMAT_CTRL 0x108
91#define MT9M111_REDUCER_XZOOM_B 0x1a0
92#define MT9M111_REDUCER_XSIZE_B 0x1a1
93#define MT9M111_REDUCER_YZOOM_B 0x1a3
94#define MT9M111_REDUCER_YSIZE_B 0x1a4
95#define MT9M111_REDUCER_XZOOM_A 0x1a6
96#define MT9M111_REDUCER_XSIZE_A 0x1a7
97#define MT9M111_REDUCER_YZOOM_A 0x1a9
98#define MT9M111_REDUCER_YSIZE_A 0x1aa
99
100#define MT9M111_OUTPUT_FORMAT_CTRL2_A 0x13a
101#define MT9M111_OUTPUT_FORMAT_CTRL2_B 0x19b
102
103#define MT9M111_OPMODE_AUTOEXPO_EN (1 << 14)
39bf372f 104#define MT9M111_OPMODE_AUTOWHITEBAL_EN (1 << 1)
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105#define MT9M111_OUTFMT_FLIP_BAYER_COL (1 << 9)
106#define MT9M111_OUTFMT_FLIP_BAYER_ROW (1 << 8)
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107#define MT9M111_OUTFMT_PROCESSED_BAYER (1 << 14)
108#define MT9M111_OUTFMT_BYPASS_IFP (1 << 10)
109#define MT9M111_OUTFMT_INV_PIX_CLOCK (1 << 9)
110#define MT9M111_OUTFMT_RGB (1 << 8)
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111#define MT9M111_OUTFMT_RGB565 (0 << 6)
112#define MT9M111_OUTFMT_RGB555 (1 << 6)
113#define MT9M111_OUTFMT_RGB444x (2 << 6)
114#define MT9M111_OUTFMT_RGBx444 (3 << 6)
115#define MT9M111_OUTFMT_TST_RAMP_OFF (0 << 4)
116#define MT9M111_OUTFMT_TST_RAMP_COL (1 << 4)
117#define MT9M111_OUTFMT_TST_RAMP_ROW (2 << 4)
118#define MT9M111_OUTFMT_TST_RAMP_FRAME (3 << 4)
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119#define MT9M111_OUTFMT_SHIFT_3_UP (1 << 3)
120#define MT9M111_OUTFMT_AVG_CHROMA (1 << 2)
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121#define MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN (1 << 1)
122#define MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B (1 << 0)
c8cf078e 123
77110abb 124/*
c8cf078e 125 * Camera control register addresses (0x200..0x2ff not implemented)
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126 */
127
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128#define reg_read(reg) mt9m111_reg_read(client, MT9M111_##reg)
129#define reg_write(reg, val) mt9m111_reg_write(client, MT9M111_##reg, (val))
130#define reg_set(reg, val) mt9m111_reg_set(client, MT9M111_##reg, (val))
131#define reg_clear(reg, val) mt9m111_reg_clear(client, MT9M111_##reg, (val))
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132#define reg_mask(reg, val, mask) mt9m111_reg_mask(client, MT9M111_##reg, \
133 (val), (mask))
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134
135#define MT9M111_MIN_DARK_ROWS 8
669470a8 136#define MT9M111_MIN_DARK_COLS 26
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137#define MT9M111_MAX_HEIGHT 1024
138#define MT9M111_MAX_WIDTH 1280
139
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140/* MT9M111 has only one fixed colorspace per pixelcode */
141struct mt9m111_datafmt {
142 enum v4l2_mbus_pixelcode code;
143 enum v4l2_colorspace colorspace;
144};
145
146/* Find a data format by a pixel code in an array */
147static const struct mt9m111_datafmt *mt9m111_find_datafmt(
148 enum v4l2_mbus_pixelcode code, const struct mt9m111_datafmt *fmt,
149 int n)
150{
151 int i;
152 for (i = 0; i < n; i++)
153 if (fmt[i].code == code)
154 return fmt + i;
155
156 return NULL;
157}
158
159static const struct mt9m111_datafmt mt9m111_colour_fmts[] = {
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160 {V4L2_MBUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_JPEG},
161 {V4L2_MBUS_FMT_YVYU8_2X8, V4L2_COLORSPACE_JPEG},
162 {V4L2_MBUS_FMT_UYVY8_2X8, V4L2_COLORSPACE_JPEG},
163 {V4L2_MBUS_FMT_VYUY8_2X8, V4L2_COLORSPACE_JPEG},
760697be 164 {V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB},
7c58e7d0 165 {V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE, V4L2_COLORSPACE_SRGB},
760697be 166 {V4L2_MBUS_FMT_RGB565_2X8_LE, V4L2_COLORSPACE_SRGB},
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167 {V4L2_MBUS_FMT_RGB565_2X8_BE, V4L2_COLORSPACE_SRGB},
168 {V4L2_MBUS_FMT_BGR565_2X8_LE, V4L2_COLORSPACE_SRGB},
169 {V4L2_MBUS_FMT_BGR565_2X8_BE, V4L2_COLORSPACE_SRGB},
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170 {V4L2_MBUS_FMT_SBGGR8_1X8, V4L2_COLORSPACE_SRGB},
171 {V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB},
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172};
173
174enum mt9m111_context {
175 HIGHPOWER = 0,
176 LOWPOWER,
177};
178
179struct mt9m111 {
979ea1dd 180 struct v4l2_subdev subdev;
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181 int model; /* V4L2_IDENT_MT9M111 or V4L2_IDENT_MT9M112 code
182 * from v4l2-chip-ident.h */
77110abb 183 enum mt9m111_context context;
09e231b3 184 struct v4l2_rect rect;
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185 struct mutex power_lock; /* lock to protect power_count */
186 int power_count;
760697be 187 const struct mt9m111_datafmt *fmt;
096b703f 188 int lastpage; /* PageMap cache value */
96c75399 189 unsigned int gain;
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190 unsigned char autoexposure;
191 unsigned char datawidth;
192 unsigned int powered:1;
193 unsigned int hflip:1;
194 unsigned int vflip:1;
39bf372f 195 unsigned int autowhitebalance:1;
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196};
197
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198static struct mt9m111 *to_mt9m111(const struct i2c_client *client)
199{
200 return container_of(i2c_get_clientdata(client), struct mt9m111, subdev);
201}
202
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203static int reg_page_map_set(struct i2c_client *client, const u16 reg)
204{
205 int ret;
206 u16 page;
096b703f 207 struct mt9m111 *mt9m111 = to_mt9m111(client);
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208
209 page = (reg >> 8);
096b703f 210 if (page == mt9m111->lastpage)
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211 return 0;
212 if (page > 2)
213 return -EINVAL;
214
215 ret = i2c_smbus_write_word_data(client, MT9M111_PAGE_MAP, swab16(page));
506c629a 216 if (!ret)
096b703f 217 mt9m111->lastpage = page;
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218 return ret;
219}
220
9538e1c2 221static int mt9m111_reg_read(struct i2c_client *client, const u16 reg)
77110abb 222{
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223 int ret;
224
225 ret = reg_page_map_set(client, reg);
226 if (!ret)
6a6c8786 227 ret = swab16(i2c_smbus_read_word_data(client, reg & 0xff));
77110abb 228
9538e1c2 229 dev_dbg(&client->dev, "read reg.%03x -> %04x\n", reg, ret);
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230 return ret;
231}
232
9538e1c2 233static int mt9m111_reg_write(struct i2c_client *client, const u16 reg,
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234 const u16 data)
235{
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236 int ret;
237
238 ret = reg_page_map_set(client, reg);
506c629a 239 if (!ret)
40e2e092 240 ret = i2c_smbus_write_word_data(client, reg & 0xff,
77110abb 241 swab16(data));
9538e1c2 242 dev_dbg(&client->dev, "write reg.%03x = %04x -> %d\n", reg, data, ret);
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243 return ret;
244}
245
9538e1c2 246static int mt9m111_reg_set(struct i2c_client *client, const u16 reg,
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247 const u16 data)
248{
249 int ret;
250
9538e1c2 251 ret = mt9m111_reg_read(client, reg);
77110abb 252 if (ret >= 0)
9538e1c2 253 ret = mt9m111_reg_write(client, reg, ret | data);
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254 return ret;
255}
256
9538e1c2 257static int mt9m111_reg_clear(struct i2c_client *client, const u16 reg,
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258 const u16 data)
259{
260 int ret;
261
9538e1c2 262 ret = mt9m111_reg_read(client, reg);
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263 if (ret >= 0)
264 ret = mt9m111_reg_write(client, reg, ret & ~data);
265 return ret;
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266}
267
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268static int mt9m111_reg_mask(struct i2c_client *client, const u16 reg,
269 const u16 data, const u16 mask)
270{
271 int ret;
272
273 ret = mt9m111_reg_read(client, reg);
274 if (ret >= 0)
275 ret = mt9m111_reg_write(client, reg, (ret & ~mask) | data);
276 return ret;
277}
278
2768cbbb 279static int mt9m111_set_context(struct mt9m111 *mt9m111,
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280 enum mt9m111_context ctxt)
281{
2768cbbb 282 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
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283 int valB = MT9M111_CTXT_CTRL_RESTART | MT9M111_CTXT_CTRL_DEFECTCOR_B
284 | MT9M111_CTXT_CTRL_RESIZE_B | MT9M111_CTXT_CTRL_CTRL2_B
285 | MT9M111_CTXT_CTRL_GAMMA_B | MT9M111_CTXT_CTRL_READ_MODE_B
286 | MT9M111_CTXT_CTRL_VBLANK_SEL_B
287 | MT9M111_CTXT_CTRL_HBLANK_SEL_B;
288 int valA = MT9M111_CTXT_CTRL_RESTART;
289
290 if (ctxt == HIGHPOWER)
291 return reg_write(CONTEXT_CONTROL, valB);
292 else
293 return reg_write(CONTEXT_CONTROL, valA);
294}
295
2768cbbb 296static int mt9m111_setup_rect(struct mt9m111 *mt9m111,
09e231b3 297 struct v4l2_rect *rect)
77110abb 298{
2768cbbb 299 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
506c629a 300 int ret, is_raw_format;
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GL
301 int width = rect->width;
302 int height = rect->height;
77110abb 303
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304 if (mt9m111->fmt->code == V4L2_MBUS_FMT_SBGGR8_1X8 ||
305 mt9m111->fmt->code == V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE)
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306 is_raw_format = 1;
307 else
308 is_raw_format = 0;
309
09e231b3 310 ret = reg_write(COLUMN_START, rect->left);
506c629a 311 if (!ret)
09e231b3 312 ret = reg_write(ROW_START, rect->top);
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313
314 if (is_raw_format) {
506c629a 315 if (!ret)
77110abb 316 ret = reg_write(WINDOW_WIDTH, width);
506c629a 317 if (!ret)
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318 ret = reg_write(WINDOW_HEIGHT, height);
319 } else {
506c629a 320 if (!ret)
77110abb 321 ret = reg_write(REDUCER_XZOOM_B, MT9M111_MAX_WIDTH);
506c629a 322 if (!ret)
77110abb 323 ret = reg_write(REDUCER_YZOOM_B, MT9M111_MAX_HEIGHT);
506c629a 324 if (!ret)
77110abb 325 ret = reg_write(REDUCER_XSIZE_B, width);
506c629a 326 if (!ret)
77110abb 327 ret = reg_write(REDUCER_YSIZE_B, height);
506c629a 328 if (!ret)
77110abb 329 ret = reg_write(REDUCER_XZOOM_A, MT9M111_MAX_WIDTH);
506c629a 330 if (!ret)
77110abb 331 ret = reg_write(REDUCER_YZOOM_A, MT9M111_MAX_HEIGHT);
506c629a 332 if (!ret)
77110abb 333 ret = reg_write(REDUCER_XSIZE_A, width);
506c629a 334 if (!ret)
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335 ret = reg_write(REDUCER_YSIZE_A, height);
336 }
337
338 return ret;
339}
340
2768cbbb 341static int mt9m111_enable(struct mt9m111 *mt9m111)
77110abb 342{
2768cbbb 343 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
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344 int ret;
345
346 ret = reg_set(RESET, MT9M111_RESET_CHIP_ENABLE);
506c629a 347 if (!ret)
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348 mt9m111->powered = 1;
349 return ret;
350}
351
2768cbbb 352static int mt9m111_reset(struct mt9m111 *mt9m111)
77110abb 353{
2768cbbb 354 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
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355 int ret;
356
357 ret = reg_set(RESET, MT9M111_RESET_RESET_MODE);
506c629a 358 if (!ret)
77110abb 359 ret = reg_set(RESET, MT9M111_RESET_RESET_SOC);
506c629a 360 if (!ret)
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361 ret = reg_clear(RESET, MT9M111_RESET_RESET_MODE
362 | MT9M111_RESET_RESET_SOC);
afb13683 363
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364 return ret;
365}
366
2768cbbb 367static int mt9m111_make_rect(struct mt9m111 *mt9m111,
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GL
368 struct v4l2_rect *rect)
369{
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370 if (mt9m111->fmt->code == V4L2_MBUS_FMT_SBGGR8_1X8 ||
371 mt9m111->fmt->code == V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE) {
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372 /* Bayer format - even size lengths */
373 rect->width = ALIGN(rect->width, 2);
374 rect->height = ALIGN(rect->height, 2);
375 /* Let the user play with the starting pixel */
376 }
377
378 /* FIXME: the datasheet doesn't specify minimum sizes */
379 soc_camera_limit_side(&rect->left, &rect->width,
380 MT9M111_MIN_DARK_COLS, 2, MT9M111_MAX_WIDTH);
381
382 soc_camera_limit_side(&rect->top, &rect->height,
383 MT9M111_MIN_DARK_ROWS, 2, MT9M111_MAX_HEIGHT);
384
2768cbbb 385 return mt9m111_setup_rect(mt9m111, rect);
6a6c8786
GL
386}
387
08590b96 388static int mt9m111_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
09e231b3 389{
6a6c8786 390 struct v4l2_rect rect = a->c;
c4ce6d14 391 struct i2c_client *client = v4l2_get_subdevdata(sd);
2768cbbb 392 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
09e231b3
GL
393 int ret;
394
85f8be68 395 dev_dbg(&client->dev, "%s left=%d, top=%d, width=%d, height=%d\n",
6a6c8786 396 __func__, rect.left, rect.top, rect.width, rect.height);
09e231b3 397
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MG
398 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
399 return -EINVAL;
400
2768cbbb 401 ret = mt9m111_make_rect(mt9m111, &rect);
09e231b3 402 if (!ret)
6a6c8786 403 mt9m111->rect = rect;
09e231b3
GL
404 return ret;
405}
406
6a6c8786
GL
407static int mt9m111_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
408{
2768cbbb 409 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
6a6c8786
GL
410
411 a->c = mt9m111->rect;
412 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
413
414 return 0;
415}
416
417static int mt9m111_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
418{
6b6d33c7
MG
419 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
420 return -EINVAL;
421
6a6c8786
GL
422 a->bounds.left = MT9M111_MIN_DARK_COLS;
423 a->bounds.top = MT9M111_MIN_DARK_ROWS;
424 a->bounds.width = MT9M111_MAX_WIDTH;
425 a->bounds.height = MT9M111_MAX_HEIGHT;
426 a->defrect = a->bounds;
6a6c8786
GL
427 a->pixelaspect.numerator = 1;
428 a->pixelaspect.denominator = 1;
429
430 return 0;
431}
432
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GL
433static int mt9m111_g_fmt(struct v4l2_subdev *sd,
434 struct v4l2_mbus_framefmt *mf)
6a6c8786 435{
2768cbbb 436 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
6a6c8786 437
760697be
GL
438 mf->width = mt9m111->rect.width;
439 mf->height = mt9m111->rect.height;
440 mf->code = mt9m111->fmt->code;
01f5a394 441 mf->colorspace = mt9m111->fmt->colorspace;
760697be 442 mf->field = V4L2_FIELD_NONE;
6a6c8786
GL
443
444 return 0;
445}
446
2768cbbb 447static int mt9m111_set_pixfmt(struct mt9m111 *mt9m111,
760697be 448 enum v4l2_mbus_pixelcode code)
77110abb 449{
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MG
450 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
451 u16 data_outfmt2, mask_outfmt2 = MT9M111_OUTFMT_PROCESSED_BAYER |
452 MT9M111_OUTFMT_BYPASS_IFP | MT9M111_OUTFMT_RGB |
453 MT9M111_OUTFMT_RGB565 | MT9M111_OUTFMT_RGB555 |
454 MT9M111_OUTFMT_RGB444x | MT9M111_OUTFMT_RGBx444 |
455 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN |
456 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
506c629a 457 int ret;
77110abb 458
760697be
GL
459 switch (code) {
460 case V4L2_MBUS_FMT_SBGGR8_1X8:
7c58e7d0
MG
461 data_outfmt2 = MT9M111_OUTFMT_PROCESSED_BAYER |
462 MT9M111_OUTFMT_RGB;
77110abb 463 break;
760697be 464 case V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE:
7c58e7d0 465 data_outfmt2 = MT9M111_OUTFMT_BYPASS_IFP | MT9M111_OUTFMT_RGB;
77110abb 466 break;
760697be 467 case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE:
7c58e7d0
MG
468 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB555 |
469 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN;
470 break;
471 case V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE:
472 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB555;
77110abb 473 break;
760697be 474 case V4L2_MBUS_FMT_RGB565_2X8_LE:
7c58e7d0
MG
475 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 |
476 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN;
477 break;
478 case V4L2_MBUS_FMT_RGB565_2X8_BE:
479 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565;
480 break;
481 case V4L2_MBUS_FMT_BGR565_2X8_BE:
482 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 |
483 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
484 break;
485 case V4L2_MBUS_FMT_BGR565_2X8_LE:
486 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 |
487 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN |
488 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
77110abb 489 break;
ace6e979 490 case V4L2_MBUS_FMT_UYVY8_2X8:
7c58e7d0 491 data_outfmt2 = 0;
88f4b899 492 break;
ace6e979 493 case V4L2_MBUS_FMT_VYUY8_2X8:
7c58e7d0 494 data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
88f4b899 495 break;
ace6e979 496 case V4L2_MBUS_FMT_YUYV8_2X8:
7c58e7d0 497 data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN;
88f4b899 498 break;
ace6e979 499 case V4L2_MBUS_FMT_YVYU8_2X8:
7c58e7d0
MG
500 data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN |
501 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
77110abb
RJ
502 break;
503 default:
7c58e7d0
MG
504 dev_err(&client->dev, "Pixel format not handled: %x\n", code);
505 return -EINVAL;
77110abb
RJ
506 }
507
7c58e7d0
MG
508 ret = reg_mask(OUTPUT_FORMAT_CTRL2_A, data_outfmt2,
509 mask_outfmt2);
510 if (!ret)
511 ret = reg_mask(OUTPUT_FORMAT_CTRL2_B, data_outfmt2,
512 mask_outfmt2);
513
77110abb
RJ
514 return ret;
515}
516
760697be
GL
517static int mt9m111_s_fmt(struct v4l2_subdev *sd,
518 struct v4l2_mbus_framefmt *mf)
77110abb 519{
c4ce6d14 520 struct i2c_client *client = v4l2_get_subdevdata(sd);
760697be 521 const struct mt9m111_datafmt *fmt;
2768cbbb 522 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
09e231b3
GL
523 struct v4l2_rect rect = {
524 .left = mt9m111->rect.left,
525 .top = mt9m111->rect.top,
760697be
GL
526 .width = mf->width,
527 .height = mf->height,
09e231b3 528 };
506c629a 529 int ret;
77110abb 530
760697be
GL
531 fmt = mt9m111_find_datafmt(mf->code, mt9m111_colour_fmts,
532 ARRAY_SIZE(mt9m111_colour_fmts));
533 if (!fmt)
534 return -EINVAL;
535
96c75399 536 dev_dbg(&client->dev,
760697be
GL
537 "%s code=%x left=%d, top=%d, width=%d, height=%d\n", __func__,
538 mf->code, rect.left, rect.top, rect.width, rect.height);
77110abb 539
2768cbbb 540 ret = mt9m111_make_rect(mt9m111, &rect);
09e231b3 541 if (!ret)
2768cbbb 542 ret = mt9m111_set_pixfmt(mt9m111, mf->code);
760697be
GL
543 if (!ret) {
544 mt9m111->rect = rect;
545 mt9m111->fmt = fmt;
546 mf->colorspace = fmt->colorspace;
547 }
548
506c629a 549 return ret;
77110abb
RJ
550}
551
760697be
GL
552static int mt9m111_try_fmt(struct v4l2_subdev *sd,
553 struct v4l2_mbus_framefmt *mf)
77110abb 554{
2768cbbb 555 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
760697be
GL
556 const struct mt9m111_datafmt *fmt;
557 bool bayer = mf->code == V4L2_MBUS_FMT_SBGGR8_1X8 ||
558 mf->code == V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE;
559
560 fmt = mt9m111_find_datafmt(mf->code, mt9m111_colour_fmts,
561 ARRAY_SIZE(mt9m111_colour_fmts));
562 if (!fmt) {
563 fmt = mt9m111->fmt;
564 mf->code = fmt->code;
565 }
6a6c8786
GL
566
567 /*
568 * With Bayer format enforce even side lengths, but let the user play
569 * with the starting pixel
570 */
64f5905e 571
760697be
GL
572 if (mf->height > MT9M111_MAX_HEIGHT)
573 mf->height = MT9M111_MAX_HEIGHT;
574 else if (mf->height < 2)
575 mf->height = 2;
6a6c8786 576 else if (bayer)
760697be 577 mf->height = ALIGN(mf->height, 2);
6a6c8786 578
760697be
GL
579 if (mf->width > MT9M111_MAX_WIDTH)
580 mf->width = MT9M111_MAX_WIDTH;
581 else if (mf->width < 2)
582 mf->width = 2;
6a6c8786 583 else if (bayer)
760697be
GL
584 mf->width = ALIGN(mf->width, 2);
585
586 mf->colorspace = fmt->colorspace;
77110abb
RJ
587
588 return 0;
589}
590
979ea1dd
GL
591static int mt9m111_g_chip_ident(struct v4l2_subdev *sd,
592 struct v4l2_dbg_chip_ident *id)
77110abb 593{
c4ce6d14 594 struct i2c_client *client = v4l2_get_subdevdata(sd);
2768cbbb 595 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
77110abb 596
aecde8b5 597 if (id->match.type != V4L2_CHIP_MATCH_I2C_ADDR)
77110abb
RJ
598 return -EINVAL;
599
40e2e092 600 if (id->match.addr != client->addr)
77110abb
RJ
601 return -ENODEV;
602
603 id->ident = mt9m111->model;
604 id->revision = 0;
605
606 return 0;
607}
608
609#ifdef CONFIG_VIDEO_ADV_DEBUG
979ea1dd
GL
610static int mt9m111_g_register(struct v4l2_subdev *sd,
611 struct v4l2_dbg_register *reg)
77110abb 612{
c4ce6d14 613 struct i2c_client *client = v4l2_get_subdevdata(sd);
77110abb 614 int val;
77110abb 615
aecde8b5 616 if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0x2ff)
77110abb 617 return -EINVAL;
9538e1c2 618 if (reg->match.addr != client->addr)
77110abb
RJ
619 return -ENODEV;
620
9538e1c2 621 val = mt9m111_reg_read(client, reg->reg);
aecde8b5 622 reg->size = 2;
77110abb
RJ
623 reg->val = (u64)val;
624
625 if (reg->val > 0xffff)
626 return -EIO;
627
628 return 0;
629}
630
979ea1dd
GL
631static int mt9m111_s_register(struct v4l2_subdev *sd,
632 struct v4l2_dbg_register *reg)
77110abb 633{
c4ce6d14 634 struct i2c_client *client = v4l2_get_subdevdata(sd);
77110abb 635
aecde8b5 636 if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0x2ff)
77110abb
RJ
637 return -EINVAL;
638
9538e1c2 639 if (reg->match.addr != client->addr)
77110abb
RJ
640 return -ENODEV;
641
9538e1c2 642 if (mt9m111_reg_write(client, reg->reg, reg->val) < 0)
77110abb
RJ
643 return -EIO;
644
645 return 0;
646}
647#endif
648
649static const struct v4l2_queryctrl mt9m111_controls[] = {
650 {
651 .id = V4L2_CID_VFLIP,
652 .type = V4L2_CTRL_TYPE_BOOLEAN,
653 .name = "Flip Verticaly",
654 .minimum = 0,
655 .maximum = 1,
656 .step = 1,
657 .default_value = 0,
658 }, {
659 .id = V4L2_CID_HFLIP,
660 .type = V4L2_CTRL_TYPE_BOOLEAN,
661 .name = "Flip Horizontaly",
662 .minimum = 0,
663 .maximum = 1,
664 .step = 1,
665 .default_value = 0,
666 }, { /* gain = 1/32*val (=>gain=1 if val==32) */
667 .id = V4L2_CID_GAIN,
668 .type = V4L2_CTRL_TYPE_INTEGER,
669 .name = "Gain",
670 .minimum = 0,
671 .maximum = 63 * 2 * 2,
672 .step = 1,
673 .default_value = 32,
674 .flags = V4L2_CTRL_FLAG_SLIDER,
675 }, {
676 .id = V4L2_CID_EXPOSURE_AUTO,
677 .type = V4L2_CTRL_TYPE_BOOLEAN,
678 .name = "Auto Exposure",
679 .minimum = 0,
680 .maximum = 1,
681 .step = 1,
682 .default_value = 1,
683 }
684};
685
77110abb 686static struct soc_camera_ops mt9m111_ops = {
77110abb
RJ
687 .controls = mt9m111_controls,
688 .num_controls = ARRAY_SIZE(mt9m111_controls),
77110abb
RJ
689};
690
2768cbbb 691static int mt9m111_set_flip(struct mt9m111 *mt9m111, int flip, int mask)
77110abb 692{
2768cbbb 693 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
77110abb
RJ
694 int ret;
695
696 if (mt9m111->context == HIGHPOWER) {
697 if (flip)
698 ret = reg_set(READ_MODE_B, mask);
699 else
700 ret = reg_clear(READ_MODE_B, mask);
701 } else {
702 if (flip)
703 ret = reg_set(READ_MODE_A, mask);
704 else
705 ret = reg_clear(READ_MODE_A, mask);
706 }
707
708 return ret;
709}
710
2768cbbb 711static int mt9m111_get_global_gain(struct mt9m111 *mt9m111)
77110abb 712{
2768cbbb 713 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
0f28b793 714 int data;
77110abb
RJ
715
716 data = reg_read(GLOBAL_GAIN);
717 if (data >= 0)
0f28b793 718 return (data & 0x2f) * (1 << ((data >> 10) & 1)) *
719 (1 << ((data >> 9) & 1));
720 return data;
77110abb 721}
0f28b793 722
2768cbbb 723static int mt9m111_set_global_gain(struct mt9m111 *mt9m111, int gain)
77110abb 724{
2768cbbb 725 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
77110abb
RJ
726 u16 val;
727
728 if (gain > 63 * 2 * 2)
729 return -EINVAL;
730
96c75399 731 mt9m111->gain = gain;
77110abb
RJ
732 if ((gain >= 64 * 2) && (gain < 63 * 2 * 2))
733 val = (1 << 10) | (1 << 9) | (gain / 4);
734 else if ((gain >= 64) && (gain < 64 * 2))
506c629a 735 val = (1 << 9) | (gain / 2);
77110abb
RJ
736 else
737 val = gain;
738
739 return reg_write(GLOBAL_GAIN, val);
740}
741
2768cbbb 742static int mt9m111_set_autoexposure(struct mt9m111 *mt9m111, int on)
77110abb 743{
2768cbbb 744 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
77110abb
RJ
745 int ret;
746
747 if (on)
748 ret = reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN);
749 else
750 ret = reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN);
751
506c629a 752 if (!ret)
77110abb
RJ
753 mt9m111->autoexposure = on;
754
755 return ret;
756}
39bf372f 757
2768cbbb 758static int mt9m111_set_autowhitebalance(struct mt9m111 *mt9m111, int on)
39bf372f 759{
2768cbbb 760 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
39bf372f
RJ
761 int ret;
762
763 if (on)
764 ret = reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN);
765 else
766 ret = reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN);
767
768 if (!ret)
769 mt9m111->autowhitebalance = on;
770
771 return ret;
772}
773
979ea1dd 774static int mt9m111_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
77110abb 775{
c4ce6d14 776 struct i2c_client *client = v4l2_get_subdevdata(sd);
2768cbbb 777 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
77110abb
RJ
778 int data;
779
780 switch (ctrl->id) {
781 case V4L2_CID_VFLIP:
782 if (mt9m111->context == HIGHPOWER)
783 data = reg_read(READ_MODE_B);
784 else
785 data = reg_read(READ_MODE_A);
786
787 if (data < 0)
788 return -EIO;
789 ctrl->value = !!(data & MT9M111_RMB_MIRROR_ROWS);
790 break;
791 case V4L2_CID_HFLIP:
792 if (mt9m111->context == HIGHPOWER)
793 data = reg_read(READ_MODE_B);
794 else
795 data = reg_read(READ_MODE_A);
796
797 if (data < 0)
798 return -EIO;
799 ctrl->value = !!(data & MT9M111_RMB_MIRROR_COLS);
800 break;
801 case V4L2_CID_GAIN:
2768cbbb 802 data = mt9m111_get_global_gain(mt9m111);
77110abb
RJ
803 if (data < 0)
804 return data;
805 ctrl->value = data;
806 break;
807 case V4L2_CID_EXPOSURE_AUTO:
808 ctrl->value = mt9m111->autoexposure;
809 break;
39bf372f
RJ
810 case V4L2_CID_AUTO_WHITE_BALANCE:
811 ctrl->value = mt9m111->autowhitebalance;
812 break;
77110abb
RJ
813 }
814 return 0;
815}
816
979ea1dd 817static int mt9m111_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
77110abb 818{
2768cbbb 819 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
77110abb 820 const struct v4l2_queryctrl *qctrl;
506c629a 821 int ret;
77110abb
RJ
822
823 qctrl = soc_camera_find_qctrl(&mt9m111_ops, ctrl->id);
77110abb
RJ
824 if (!qctrl)
825 return -EINVAL;
826
827 switch (ctrl->id) {
828 case V4L2_CID_VFLIP:
829 mt9m111->vflip = ctrl->value;
2768cbbb 830 ret = mt9m111_set_flip(mt9m111, ctrl->value,
77110abb
RJ
831 MT9M111_RMB_MIRROR_ROWS);
832 break;
833 case V4L2_CID_HFLIP:
834 mt9m111->hflip = ctrl->value;
2768cbbb 835 ret = mt9m111_set_flip(mt9m111, ctrl->value,
77110abb
RJ
836 MT9M111_RMB_MIRROR_COLS);
837 break;
838 case V4L2_CID_GAIN:
2768cbbb 839 ret = mt9m111_set_global_gain(mt9m111, ctrl->value);
77110abb
RJ
840 break;
841 case V4L2_CID_EXPOSURE_AUTO:
2768cbbb 842 ret = mt9m111_set_autoexposure(mt9m111, ctrl->value);
77110abb 843 break;
39bf372f 844 case V4L2_CID_AUTO_WHITE_BALANCE:
2768cbbb 845 ret = mt9m111_set_autowhitebalance(mt9m111, ctrl->value);
39bf372f 846 break;
77110abb
RJ
847 default:
848 ret = -EINVAL;
849 }
850
506c629a 851 return ret;
77110abb
RJ
852}
853
14c5ea9b 854static int mt9m111_suspend(struct mt9m111 *mt9m111)
96c75399 855{
2768cbbb 856 mt9m111->gain = mt9m111_get_global_gain(mt9m111);
96c75399
GL
857
858 return 0;
859}
860
2768cbbb 861static void mt9m111_restore_state(struct mt9m111 *mt9m111)
77110abb 862{
2768cbbb
GL
863 mt9m111_set_context(mt9m111, mt9m111->context);
864 mt9m111_set_pixfmt(mt9m111, mt9m111->fmt->code);
865 mt9m111_setup_rect(mt9m111, &mt9m111->rect);
866 mt9m111_set_flip(mt9m111, mt9m111->hflip, MT9M111_RMB_MIRROR_COLS);
867 mt9m111_set_flip(mt9m111, mt9m111->vflip, MT9M111_RMB_MIRROR_ROWS);
868 mt9m111_set_global_gain(mt9m111, mt9m111->gain);
869 mt9m111_set_autoexposure(mt9m111, mt9m111->autoexposure);
870 mt9m111_set_autowhitebalance(mt9m111, mt9m111->autowhitebalance);
77110abb
RJ
871}
872
14c5ea9b 873static int mt9m111_resume(struct mt9m111 *mt9m111)
77110abb 874{
77110abb
RJ
875 int ret = 0;
876
877 if (mt9m111->powered) {
2768cbbb 878 ret = mt9m111_enable(mt9m111);
506c629a 879 if (!ret)
2768cbbb 880 ret = mt9m111_reset(mt9m111);
506c629a 881 if (!ret)
2768cbbb 882 mt9m111_restore_state(mt9m111);
77110abb
RJ
883 }
884 return ret;
885}
886
2768cbbb 887static int mt9m111_init(struct mt9m111 *mt9m111)
77110abb 888{
2768cbbb 889 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
77110abb
RJ
890 int ret;
891
892 mt9m111->context = HIGHPOWER;
2768cbbb 893 ret = mt9m111_enable(mt9m111);
506c629a 894 if (!ret)
2768cbbb 895 ret = mt9m111_reset(mt9m111);
506c629a 896 if (!ret)
2768cbbb 897 ret = mt9m111_set_context(mt9m111, mt9m111->context);
506c629a 898 if (!ret)
2768cbbb 899 ret = mt9m111_set_autoexposure(mt9m111, mt9m111->autoexposure);
506c629a 900 if (ret)
c8cf078e 901 dev_err(&client->dev, "mt9m111 init failed: %d\n", ret);
506c629a 902 return ret;
77110abb
RJ
903}
904
77110abb
RJ
905/*
906 * Interface active, can use i2c. If it fails, it can indeed mean, that
907 * this wasn't our capture interface, so, we wait for the right one
908 */
40e2e092
GL
909static int mt9m111_video_probe(struct soc_camera_device *icd,
910 struct i2c_client *client)
77110abb 911{
979ea1dd 912 struct mt9m111 *mt9m111 = to_mt9m111(client);
77110abb
RJ
913 s32 data;
914 int ret;
915
7dfff953
GL
916 /* We must have a parent by now. And it cannot be a wrong one. */
917 BUG_ON(!icd->parent ||
918 to_soc_camera_host(icd->parent)->nr != icd->iface);
77110abb 919
096b703f
MG
920 mt9m111->lastpage = -1;
921
a4c56fd8
GL
922 mt9m111->autoexposure = 1;
923 mt9m111->autowhitebalance = 1;
924
77110abb
RJ
925 data = reg_read(CHIP_VERSION);
926
927 switch (data) {
c8cf078e 928 case 0x143a: /* MT9M111 or MT9M131 */
77110abb 929 mt9m111->model = V4L2_IDENT_MT9M111;
c8cf078e
PW
930 dev_info(&client->dev,
931 "Detected a MT9M111/MT9M131 chip ID %x\n", data);
d7f83a51
MR
932 break;
933 case 0x148c: /* MT9M112 */
934 mt9m111->model = V4L2_IDENT_MT9M112;
c8cf078e 935 dev_info(&client->dev, "Detected a MT9M112 chip ID %x\n", data);
77110abb
RJ
936 break;
937 default:
938 ret = -ENODEV;
85f8be68 939 dev_err(&client->dev,
c8cf078e
PW
940 "No MT9M111/MT9M112/MT9M131 chip detected register read %x\n",
941 data);
77110abb
RJ
942 goto ei2c;
943 }
944
2768cbbb 945 ret = mt9m111_init(mt9m111);
175bad92 946
77110abb
RJ
947ei2c:
948 return ret;
949}
950
14c5ea9b
GL
951static int mt9m111_s_power(struct v4l2_subdev *sd, int on)
952{
953 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
954 struct i2c_client *client = v4l2_get_subdevdata(sd);
955 int ret = 0;
956
957 mutex_lock(&mt9m111->power_lock);
958
959 /*
960 * If the power count is modified from 0 to != 0 or from != 0 to 0,
961 * update the power state.
962 */
963 if (mt9m111->power_count == !on) {
964 if (on) {
965 ret = mt9m111_resume(mt9m111);
966 if (ret) {
967 dev_err(&client->dev,
968 "Failed to resume the sensor: %d\n", ret);
969 goto out;
970 }
971 } else {
972 mt9m111_suspend(mt9m111);
973 }
974 }
975
976 /* Update the power count. */
977 mt9m111->power_count += on ? 1 : -1;
978 WARN_ON(mt9m111->power_count < 0);
979
980out:
981 mutex_unlock(&mt9m111->power_lock);
982 return ret;
983}
984
979ea1dd
GL
985static struct v4l2_subdev_core_ops mt9m111_subdev_core_ops = {
986 .g_ctrl = mt9m111_g_ctrl,
987 .s_ctrl = mt9m111_s_ctrl,
988 .g_chip_ident = mt9m111_g_chip_ident,
14c5ea9b 989 .s_power = mt9m111_s_power,
979ea1dd
GL
990#ifdef CONFIG_VIDEO_ADV_DEBUG
991 .g_register = mt9m111_g_register,
992 .s_register = mt9m111_s_register,
993#endif
994};
995
3805f201 996static int mt9m111_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
760697be
GL
997 enum v4l2_mbus_pixelcode *code)
998{
3805f201 999 if (index >= ARRAY_SIZE(mt9m111_colour_fmts))
760697be
GL
1000 return -EINVAL;
1001
1002 *code = mt9m111_colour_fmts[index].code;
1003 return 0;
1004}
1005
0c0b446d
GL
1006static int mt9m111_g_mbus_config(struct v4l2_subdev *sd,
1007 struct v4l2_mbus_config *cfg)
1008{
1009 struct i2c_client *client = v4l2_get_subdevdata(sd);
1010 struct soc_camera_device *icd = client->dev.platform_data;
1011 struct soc_camera_link *icl = to_soc_camera_link(icd);
1012
1013 cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING |
1014 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_HIGH |
1015 V4L2_MBUS_DATA_ACTIVE_HIGH;
1016 cfg->type = V4L2_MBUS_PARALLEL;
1017 cfg->flags = soc_camera_apply_board_flags(icl, cfg);
1018
1019 return 0;
1020}
1021
979ea1dd 1022static struct v4l2_subdev_video_ops mt9m111_subdev_video_ops = {
760697be
GL
1023 .s_mbus_fmt = mt9m111_s_fmt,
1024 .g_mbus_fmt = mt9m111_g_fmt,
1025 .try_mbus_fmt = mt9m111_try_fmt,
08590b96 1026 .s_crop = mt9m111_s_crop,
6a6c8786
GL
1027 .g_crop = mt9m111_g_crop,
1028 .cropcap = mt9m111_cropcap,
760697be 1029 .enum_mbus_fmt = mt9m111_enum_fmt,
0c0b446d 1030 .g_mbus_config = mt9m111_g_mbus_config,
979ea1dd
GL
1031};
1032
1033static struct v4l2_subdev_ops mt9m111_subdev_ops = {
1034 .core = &mt9m111_subdev_core_ops,
1035 .video = &mt9m111_subdev_video_ops,
1036};
1037
77110abb
RJ
1038static int mt9m111_probe(struct i2c_client *client,
1039 const struct i2c_device_id *did)
1040{
1041 struct mt9m111 *mt9m111;
40e2e092 1042 struct soc_camera_device *icd = client->dev.platform_data;
77110abb 1043 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
40e2e092 1044 struct soc_camera_link *icl;
77110abb
RJ
1045 int ret;
1046
40e2e092 1047 if (!icd) {
c8cf078e 1048 dev_err(&client->dev, "mt9m111: soc-camera data missing!\n");
40e2e092
GL
1049 return -EINVAL;
1050 }
1051
1052 icl = to_soc_camera_link(icd);
77110abb 1053 if (!icl) {
c8cf078e 1054 dev_err(&client->dev, "mt9m111: driver needs platform data\n");
77110abb
RJ
1055 return -EINVAL;
1056 }
1057
1058 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) {
1059 dev_warn(&adapter->dev,
1060 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
1061 return -EIO;
1062 }
1063
1064 mt9m111 = kzalloc(sizeof(struct mt9m111), GFP_KERNEL);
1065 if (!mt9m111)
1066 return -ENOMEM;
1067
979ea1dd 1068 v4l2_i2c_subdev_init(&mt9m111->subdev, client, &mt9m111_subdev_ops);
77110abb
RJ
1069
1070 /* Second stage probe - when a capture adapter is there */
a0705b07 1071 icd->ops = &mt9m111_ops;
77110abb 1072
6a6c8786
GL
1073 mt9m111->rect.left = MT9M111_MIN_DARK_COLS;
1074 mt9m111->rect.top = MT9M111_MIN_DARK_ROWS;
1075 mt9m111->rect.width = MT9M111_MAX_WIDTH;
1076 mt9m111->rect.height = MT9M111_MAX_HEIGHT;
760697be 1077 mt9m111->fmt = &mt9m111_colour_fmts[0];
6a6c8786 1078
40e2e092
GL
1079 ret = mt9m111_video_probe(icd, client);
1080 if (ret) {
1081 icd->ops = NULL;
40e2e092
GL
1082 kfree(mt9m111);
1083 }
77110abb 1084
77110abb
RJ
1085 return ret;
1086}
1087
1088static int mt9m111_remove(struct i2c_client *client)
1089{
979ea1dd 1090 struct mt9m111 *mt9m111 = to_mt9m111(client);
40e2e092
GL
1091 struct soc_camera_device *icd = client->dev.platform_data;
1092
1093 icd->ops = NULL;
77110abb
RJ
1094 kfree(mt9m111);
1095
1096 return 0;
1097}
1098
1099static const struct i2c_device_id mt9m111_id[] = {
1100 { "mt9m111", 0 },
1101 { }
1102};
1103MODULE_DEVICE_TABLE(i2c, mt9m111_id);
1104
1105static struct i2c_driver mt9m111_i2c_driver = {
1106 .driver = {
1107 .name = "mt9m111",
1108 },
1109 .probe = mt9m111_probe,
1110 .remove = mt9m111_remove,
1111 .id_table = mt9m111_id,
1112};
1113
1114static int __init mt9m111_mod_init(void)
1115{
1116 return i2c_add_driver(&mt9m111_i2c_driver);
1117}
1118
1119static void __exit mt9m111_mod_exit(void)
1120{
1121 i2c_del_driver(&mt9m111_i2c_driver);
1122}
1123
1124module_init(mt9m111_mod_init);
1125module_exit(mt9m111_mod_exit);
1126
c8cf078e 1127MODULE_DESCRIPTION("Micron/Aptina MT9M111/MT9M112/MT9M131 Camera driver");
77110abb
RJ
1128MODULE_AUTHOR("Robert Jarzmik");
1129MODULE_LICENSE("GPL");