[mirror_ubuntu-jammy-kernel.git] / drivers / media / video / mt9v011.c

/*
 * mt9v011 -Micron 1/4-Inch VGA Digital Image Sensor
 *
 * Copyright (c) 2009 Mauro Carvalho Chehab (mchehab@redhat.com)
 * This code is placed under the terms of the GNU General Public License v2
 */

#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/videodev2.h>
#include <linux/delay.h>
#include <asm/div64.h>
#include <media/v4l2-device.h>
#include <media/v4l2-chip-ident.h>
#include <media/mt9v011.h>

MODULE_DESCRIPTION("Micron mt9v011 sensor driver");
MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
MODULE_LICENSE("GPL");

static int debug;
module_param(debug, int, 0);
MODULE_PARM_DESC(debug, "Debug level (0-2)");

#define R00_MT9V011_CHIP_VERSION	0x00
#define R01_MT9V011_ROWSTART		0x01
#define R02_MT9V011_COLSTART		0x02
#define R03_MT9V011_HEIGHT		0x03
#define R04_MT9V011_WIDTH		0x04
#define R05_MT9V011_HBLANK		0x05
#define R06_MT9V011_VBLANK		0x06
#define R07_MT9V011_OUT_CTRL		0x07
#define R09_MT9V011_SHUTTER_WIDTH	0x09
#define R0A_MT9V011_CLK_SPEED		0x0a
#define R0B_MT9V011_RESTART		0x0b
#define R0C_MT9V011_SHUTTER_DELAY	0x0c
#define R0D_MT9V011_RESET		0x0d
#define R1E_MT9V011_DIGITAL_ZOOM	0x1e
#define R20_MT9V011_READ_MODE		0x20
#define R2B_MT9V011_GREEN_1_GAIN	0x2b
#define R2C_MT9V011_BLUE_GAIN		0x2c
#define R2D_MT9V011_RED_GAIN		0x2d
#define R2E_MT9V011_GREEN_2_GAIN	0x2e
#define R35_MT9V011_GLOBAL_GAIN		0x35
#define RF1_MT9V011_CHIP_ENABLE		0xf1

#define MT9V011_VERSION			0x8232
#define MT9V011_REV_B_VERSION		0x8243

/* supported controls */
static struct v4l2_queryctrl mt9v011_qctrl[] = {
	{
		.id = V4L2_CID_GAIN,
		.type = V4L2_CTRL_TYPE_INTEGER,
		.name = "Gain",
		.minimum = 0,
		.maximum = (1 << 10) - 1,
		.step = 1,
		.default_value = 0x0020,
		.flags = 0,
	}, {
		.id = V4L2_CID_EXPOSURE,
		.type = V4L2_CTRL_TYPE_INTEGER,
		.name = "Exposure",
		.minimum = 0,
		.maximum = 2047,
		.step = 1,
		.default_value = 0x01fc,
		.flags = 0,
	}, {
		.id = V4L2_CID_RED_BALANCE,
		.type = V4L2_CTRL_TYPE_INTEGER,
		.name = "Red Balance",
		.minimum = -1 << 9,
		.maximum = (1 << 9) - 1,
		.step = 1,
		.default_value = 0,
		.flags = 0,
	}, {
		.id = V4L2_CID_BLUE_BALANCE,
		.type = V4L2_CTRL_TYPE_INTEGER,
		.name = "Blue Balance",
		.minimum = -1 << 9,
		.maximum = (1 << 9) - 1,
		.step = 1,
		.default_value = 0,
		.flags = 0,
	}, {
		.id      = V4L2_CID_HFLIP,
		.type    = V4L2_CTRL_TYPE_BOOLEAN,
		.name    = "Mirror",
		.minimum = 0,
		.maximum = 1,
		.step    = 1,
		.default_value = 0,
		.flags = 0,
	}, {
		.id      = V4L2_CID_VFLIP,
		.type    = V4L2_CTRL_TYPE_BOOLEAN,
		.name    = "Vflip",
		.minimum = 0,
		.maximum = 1,
		.step    = 1,
		.default_value = 0,
		.flags = 0,
	}, {
	}
};

struct mt9v011 {
	struct v4l2_subdev sd;
	unsigned width, height;
	unsigned xtal;
	unsigned hflip:1;
	unsigned vflip:1;

	u16 global_gain, exposure, red_bal, blue_bal;
};

static inline struct mt9v011 *to_mt9v011(struct v4l2_subdev *sd)
{
	return container_of(sd, struct mt9v011, sd);
}

static int mt9v011_read(struct v4l2_subdev *sd, unsigned char addr)
{
	struct i2c_client *c = v4l2_get_subdevdata(sd);
	__be16 buffer;
	int rc, val;

	rc = i2c_master_send(c, &addr, 1);
	if (rc != 1)
		v4l2_dbg(0, debug, sd,
			 "i2c i/o error: rc == %d (should be 1)\n", rc);

	msleep(10);

	rc = i2c_master_recv(c, (char *)&buffer, 2);
	if (rc != 2)
		v4l2_dbg(0, debug, sd,
			 "i2c i/o error: rc == %d (should be 2)\n", rc);

	val = be16_to_cpu(buffer);

	v4l2_dbg(2, debug, sd, "mt9v011: read 0x%02x = 0x%04x\n", addr, val);

	return val;
}

static void mt9v011_write(struct v4l2_subdev *sd, unsigned char addr,
				 u16 value)
{
	struct i2c_client *c = v4l2_get_subdevdata(sd);
	unsigned char buffer[3];
	int rc;

	buffer[0] = addr;
	buffer[1] = value >> 8;
	buffer[2] = value & 0xff;

	v4l2_dbg(2, debug, sd,
		 "mt9v011: writing 0x%02x 0x%04x\n", buffer[0], value);
	rc = i2c_master_send(c, buffer, 3);
	if (rc != 3)
		v4l2_dbg(0, debug, sd,
			 "i2c i/o error: rc == %d (should be 3)\n", rc);
}


struct i2c_reg_value {
	unsigned char reg;
	u16           value;
};

/*
 * Values used at the original driver
 * Some values are marked as Reserved at the datasheet
 */
static const struct i2c_reg_value mt9v011_init_default[] = {
		{ R0D_MT9V011_RESET, 0x0001 },
		{ R0D_MT9V011_RESET, 0x0000 },

		{ R0C_MT9V011_SHUTTER_DELAY, 0x0000 },
		{ R09_MT9V011_SHUTTER_WIDTH, 0x1fc },

		{ R0A_MT9V011_CLK_SPEED, 0x0000 },
		{ R1E_MT9V011_DIGITAL_ZOOM,  0x0000 },

		{ R07_MT9V011_OUT_CTRL, 0x0002 },	/* chip enable */
};

static void set_balance(struct v4l2_subdev *sd)
{
	struct mt9v011 *core = to_mt9v011(sd);
	u16 green1_gain, green2_gain, blue_gain, red_gain;
	u16 exposure;

	exposure = core->exposure;

	green1_gain = core->global_gain;
	green2_gain = core->global_gain;

	blue_gain = core->global_gain +
		    core->global_gain * core->blue_bal / (1 << 9);

	red_gain = core->global_gain +
		   core->global_gain * core->blue_bal / (1 << 9);

	mt9v011_write(sd, R2B_MT9V011_GREEN_1_GAIN, green1_gain);
	mt9v011_write(sd, R2E_MT9V011_GREEN_2_GAIN,  green1_gain);
	mt9v011_write(sd, R2C_MT9V011_BLUE_GAIN, blue_gain);
	mt9v011_write(sd, R2D_MT9V011_RED_GAIN, red_gain);
	mt9v011_write(sd, R09_MT9V011_SHUTTER_WIDTH, exposure);
}

static void calc_fps(struct v4l2_subdev *sd, u32 *numerator, u32 *denominator)
{
	struct mt9v011 *core = to_mt9v011(sd);
	unsigned height, width, hblank, vblank, speed;
	unsigned row_time, t_time;
	u64 frames_per_ms;
	unsigned tmp;

	height = mt9v011_read(sd, R03_MT9V011_HEIGHT);
	width = mt9v011_read(sd, R04_MT9V011_WIDTH);
	hblank = mt9v011_read(sd, R05_MT9V011_HBLANK);
	vblank = mt9v011_read(sd, R06_MT9V011_VBLANK);
	speed = mt9v011_read(sd, R0A_MT9V011_CLK_SPEED);

	row_time = (width + 113 + hblank) * (speed + 2);
	t_time = row_time * (height + vblank + 1);

	frames_per_ms = core->xtal * 1000l;
	do_div(frames_per_ms, t_time);
	tmp = frames_per_ms;

	v4l2_dbg(1, debug, sd, "Programmed to %u.%03u fps (%d pixel clcks)\n",
		tmp / 1000, tmp % 1000, t_time);

	if (numerator && denominator) {
		*numerator = 1000;
		*denominator = (u32)frames_per_ms;
	}
}

static u16 calc_speed(struct v4l2_subdev *sd, u32 numerator, u32 denominator)
{
	struct mt9v011 *core = to_mt9v011(sd);
	unsigned height, width, hblank, vblank;
	unsigned row_time, line_time;
	u64 t_time, speed;

	/* Avoid bogus calculus */
	if (!numerator || !denominator)
		return 0;

	height = mt9v011_read(sd, R03_MT9V011_HEIGHT);
	width = mt9v011_read(sd, R04_MT9V011_WIDTH);
	hblank = mt9v011_read(sd, R05_MT9V011_HBLANK);
	vblank = mt9v011_read(sd, R06_MT9V011_VBLANK);

	row_time = width + 113 + hblank;
	line_time = height + vblank + 1;

	t_time = core->xtal * ((u64)numerator);
	/* round to the closest value */
	t_time += denominator / 2;
	do_div(t_time, denominator);

	speed = t_time;
	do_div(speed, row_time * line_time);

	/* Avoid having a negative value for speed */
	if (speed < 2)
		speed = 0;
	else
		speed -= 2;

	/* Avoid speed overflow */
	if (speed > 15)
		return 15;

	return (u16)speed;
}

static void set_res(struct v4l2_subdev *sd)
{
	struct mt9v011 *core = to_mt9v011(sd);
	unsigned vstart, hstart;

	/*
	 * The mt9v011 doesn't have scaling. So, in order to select the desired
	 * resolution, we're cropping at the middle of the sensor.
	 * hblank and vblank should be adjusted, in order to warrant that
	 * we'll preserve the line timings for 30 fps, no matter what resolution
	 * is selected.
	 * NOTE: datasheet says that width (and height) should be filled with
	 * width-1. However, this doesn't work, since one pixel per line will
	 * be missing.
	 */

	hstart = 20 + (640 - core->width) / 2;
	mt9v011_write(sd, R02_MT9V011_COLSTART, hstart);
	mt9v011_write(sd, R04_MT9V011_WIDTH, core->width);
	mt9v011_write(sd, R05_MT9V011_HBLANK, 771 - core->width);

	vstart = 8 + (480 - core->height) / 2;
	mt9v011_write(sd, R01_MT9V011_ROWSTART, vstart);
	mt9v011_write(sd, R03_MT9V011_HEIGHT, core->height);
	mt9v011_write(sd, R06_MT9V011_VBLANK, 508 - core->height);

	calc_fps(sd, NULL, NULL);
};

static void set_read_mode(struct v4l2_subdev *sd)
{
	struct mt9v011 *core = to_mt9v011(sd);
	unsigned mode = 0x1000;

	if (core->hflip)
		mode |= 0x4000;

	if (core->vflip)
		mode |= 0x8000;

	mt9v011_write(sd, R20_MT9V011_READ_MODE, mode);
}

static int mt9v011_reset(struct v4l2_subdev *sd, u32 val)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(mt9v011_init_default); i++)
		mt9v011_write(sd, mt9v011_init_default[i].reg,
			       mt9v011_init_default[i].value);

	set_balance(sd);
	set_res(sd);
	set_read_mode(sd);

	return 0;
};

static int mt9v011_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
{
	struct mt9v011 *core = to_mt9v011(sd);

	v4l2_dbg(1, debug, sd, "g_ctrl called\n");

	switch (ctrl->id) {
	case V4L2_CID_GAIN:
		ctrl->value = core->global_gain;
		return 0;
	case V4L2_CID_EXPOSURE:
		ctrl->value = core->exposure;
		return 0;
	case V4L2_CID_RED_BALANCE:
		ctrl->value = core->red_bal;
		return 0;
	case V4L2_CID_BLUE_BALANCE:
		ctrl->value = core->blue_bal;
		return 0;
	case V4L2_CID_HFLIP:
		ctrl->value = core->hflip ? 1 : 0;
		return 0;
	case V4L2_CID_VFLIP:
		ctrl->value = core->vflip ? 1 : 0;
		return 0;
	}
	return -EINVAL;
}

static int mt9v011_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc)
{
	int i;

	v4l2_dbg(1, debug, sd, "queryctrl called\n");

	for (i = 0; i < ARRAY_SIZE(mt9v011_qctrl); i++)
		if (qc->id && qc->id == mt9v011_qctrl[i].id) {
			memcpy(qc, &(mt9v011_qctrl[i]),
			       sizeof(*qc));
			return 0;
		}

	return -EINVAL;
}


static int mt9v011_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
{
	struct mt9v011 *core = to_mt9v011(sd);
	u8 i, n;
	n = ARRAY_SIZE(mt9v011_qctrl);

	for (i = 0; i < n; i++) {
		if (ctrl->id != mt9v011_qctrl[i].id)
			continue;
		if (ctrl->value < mt9v011_qctrl[i].minimum ||
		    ctrl->value > mt9v011_qctrl[i].maximum)
			return -ERANGE;
		v4l2_dbg(1, debug, sd, "s_ctrl: id=%d, value=%d\n",
					ctrl->id, ctrl->value);
		break;
	}

	switch (ctrl->id) {
	case V4L2_CID_GAIN:
		core->global_gain = ctrl->value;
		break;
	case V4L2_CID_EXPOSURE:
		core->exposure = ctrl->value;
		break;
	case V4L2_CID_RED_BALANCE:
		core->red_bal = ctrl->value;
		break;
	case V4L2_CID_BLUE_BALANCE:
		core->blue_bal = ctrl->value;
		break;
	case V4L2_CID_HFLIP:
		core->hflip = ctrl->value;
		set_read_mode(sd);
		return 0;
	case V4L2_CID_VFLIP:
		core->vflip = ctrl->value;
		set_read_mode(sd);
		return 0;
	default:
		return -EINVAL;
	}

	set_balance(sd);

	return 0;
}

static int mt9v011_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned index,
					enum v4l2_mbus_pixelcode *code)
{
	if (index > 0)
		return -EINVAL;

	*code = V4L2_MBUS_FMT_SGRBG8_1X8;
	return 0;
}

static int mt9v011_try_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *fmt)
{
	if (fmt->code != V4L2_MBUS_FMT_SGRBG8_1X8)
		return -EINVAL;

	v4l_bound_align_image(&fmt->width, 48, 639, 1,
			      &fmt->height, 32, 480, 1, 0);
	fmt->field = V4L2_FIELD_NONE;
	fmt->colorspace = V4L2_COLORSPACE_SRGB;

	return 0;
}

static int mt9v011_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
{
	struct v4l2_captureparm *cp = &parms->parm.capture;

	if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
		return -EINVAL;

	memset(cp, 0, sizeof(struct v4l2_captureparm));
	cp->capability = V4L2_CAP_TIMEPERFRAME;
	calc_fps(sd,
		 &cp->timeperframe.numerator,
		 &cp->timeperframe.denominator);

	return 0;
}

static int mt9v011_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
{
	struct v4l2_captureparm *cp = &parms->parm.capture;
	struct v4l2_fract *tpf = &cp->timeperframe;
	u16 speed;

	if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
		return -EINVAL;
	if (cp->extendedmode != 0)
		return -EINVAL;

	speed = calc_speed(sd, tpf->numerator, tpf->denominator);

	mt9v011_write(sd, R0A_MT9V011_CLK_SPEED, speed);
	v4l2_dbg(1, debug, sd, "Setting speed to %d\n", speed);

	/* Recalculate and update fps info */
	calc_fps(sd, &tpf->numerator, &tpf->denominator);

	return 0;
}

static int mt9v011_s_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *fmt)
{
	struct mt9v011 *core = to_mt9v011(sd);
	int rc;

	rc = mt9v011_try_mbus_fmt(sd, fmt);
	if (rc < 0)
		return -EINVAL;

	core->width = fmt->width;
	core->height = fmt->height;

	set_res(sd);

	return 0;
}

#ifdef CONFIG_VIDEO_ADV_DEBUG
static int mt9v011_g_register(struct v4l2_subdev *sd,
			      struct v4l2_dbg_register *reg)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);

	if (!v4l2_chip_match_i2c_client(client, &reg->match))
		return -EINVAL;
	if (!capable(CAP_SYS_ADMIN))
		return -EPERM;

	reg->val = mt9v011_read(sd, reg->reg & 0xff);
	reg->size = 2;

	return 0;
}

static int mt9v011_s_register(struct v4l2_subdev *sd,
			      struct v4l2_dbg_register *reg)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);

	if (!v4l2_chip_match_i2c_client(client, &reg->match))
		return -EINVAL;
	if (!capable(CAP_SYS_ADMIN))
		return -EPERM;

	mt9v011_write(sd, reg->reg & 0xff, reg->val & 0xffff);

	return 0;
}
#endif

static int mt9v011_g_chip_ident(struct v4l2_subdev *sd,
				struct v4l2_dbg_chip_ident *chip)
{
	u16 version;
	struct i2c_client *client = v4l2_get_subdevdata(sd);

	version = mt9v011_read(sd, R00_MT9V011_CHIP_VERSION);

	return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_MT9V011,
					  version);
}

static const struct v4l2_subdev_core_ops mt9v011_core_ops = {
	.queryctrl = mt9v011_queryctrl,
	.g_ctrl = mt9v011_g_ctrl,
	.s_ctrl = mt9v011_s_ctrl,
	.reset = mt9v011_reset,
	.g_chip_ident = mt9v011_g_chip_ident,
#ifdef CONFIG_VIDEO_ADV_DEBUG
	.g_register = mt9v011_g_register,
	.s_register = mt9v011_s_register,
#endif
};

static const struct v4l2_subdev_video_ops mt9v011_video_ops = {
	.enum_mbus_fmt = mt9v011_enum_mbus_fmt,
	.try_mbus_fmt = mt9v011_try_mbus_fmt,
	.s_mbus_fmt = mt9v011_s_mbus_fmt,
	.g_parm = mt9v011_g_parm,
	.s_parm = mt9v011_s_parm,
};

static const struct v4l2_subdev_ops mt9v011_ops = {
	.core  = &mt9v011_core_ops,
	.video = &mt9v011_video_ops,
};


/****************************************************************************
			I2C Client & Driver
 ****************************************************************************/

static int mt9v011_probe(struct i2c_client *c,
			 const struct i2c_device_id *id)
{
	u16 version;
	struct mt9v011 *core;
	struct v4l2_subdev *sd;

	/* Check if the adapter supports the needed features */
	if (!i2c_check_functionality(c->adapter,
	     I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
		return -EIO;

	core = kzalloc(sizeof(struct mt9v011), GFP_KERNEL);
	if (!core)
		return -ENOMEM;

	sd = &core->sd;
	v4l2_i2c_subdev_init(sd, c, &mt9v011_ops);

	/* Check if the sensor is really a MT9V011 */
	version = mt9v011_read(sd, R00_MT9V011_CHIP_VERSION);
	if ((version != MT9V011_VERSION) &&
	    (version != MT9V011_REV_B_VERSION)) {
		v4l2_info(sd, "*** unknown micron chip detected (0x%04x).\n",
			  version);
		kfree(core);
		return -EINVAL;
	}

	core->global_gain = 0x0024;
	core->exposure = 0x01fc;
	core->width  = 640;
	core->height = 480;
	core->xtal = 27000000;	/* Hz */

	if (c->dev.platform_data) {
		struct mt9v011_platform_data *pdata = c->dev.platform_data;

		core->xtal = pdata->xtal;
		v4l2_dbg(1, debug, sd, "xtal set to %d.%03d MHz\n",
			core->xtal / 1000000, (core->xtal / 1000) % 1000);
	}

	v4l_info(c, "chip found @ 0x%02x (%s - chip version 0x%04x)\n",
		 c->addr << 1, c->adapter->name, version);

	return 0;
}

static int mt9v011_remove(struct i2c_client *c)
{
	struct v4l2_subdev *sd = i2c_get_clientdata(c);

	v4l2_dbg(1, debug, sd,
		"mt9v011.c: removing mt9v011 adapter on address 0x%x\n",
		c->addr << 1);

	v4l2_device_unregister_subdev(sd);
	kfree(to_mt9v011(sd));
	return 0;
}

/* ----------------------------------------------------------------------- */

static const struct i2c_device_id mt9v011_id[] = {
	{ "mt9v011", 0 },
	{ }
};
MODULE_DEVICE_TABLE(i2c, mt9v011_id);

static struct i2c_driver mt9v011_driver = {
	.driver = {
		.owner	= THIS_MODULE,
		.name	= "mt9v011",
	},
	.probe		= mt9v011_probe,
	.remove		= mt9v011_remove,
	.id_table	= mt9v011_id,
};

static __init int init_mt9v011(void)
{
	return i2c_add_driver(&mt9v011_driver);
}

static __exit void exit_mt9v011(void)
{
	i2c_del_driver(&mt9v011_driver);
}

module_init(init_mt9v011);
module_exit(exit_mt9v011);
Commit	Line	Data
7dfba00d MCC	1	/*
	2	* mt9v011 -Micron 1/4-Inch VGA Digital Image Sensor
	3	*
	4	* Copyright (c) 2009 Mauro Carvalho Chehab (mchehab@redhat.com)
	5	* This code is placed under the terms of the GNU General Public License v2
	6	*/
	7
	8	#include <linux/i2c.h>
5a0e3ad6	9	#include <linux/slab.h>
7dfba00d MCC	10	#include <linux/videodev2.h>
7dfba00d MCC	11	#include <linux/delay.h>
e11206e6	12	#include <asm/div64.h>
7dfba00d	13	#include <media/v4l2-device.h>
7dfba00d	14	#include <media/v4l2-chip-ident.h>
3c7c9370	15	#include <media/mt9v011.h>
7dfba00d MCC	16
	17	MODULE_DESCRIPTION("Micron mt9v011 sensor driver");
	18	MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
	19	MODULE_LICENSE("GPL");
	20
7dfba00d MCC	21	static int debug;
	22	module_param(debug, int, 0);
	23	MODULE_PARM_DESC(debug, "Debug level (0-2)");
	24
3c7c9370 HV	25	#define R00_MT9V011_CHIP_VERSION 0x00
	26	#define R01_MT9V011_ROWSTART 0x01
	27	#define R02_MT9V011_COLSTART 0x02
	28	#define R03_MT9V011_HEIGHT 0x03
	29	#define R04_MT9V011_WIDTH 0x04
	30	#define R05_MT9V011_HBLANK 0x05
	31	#define R06_MT9V011_VBLANK 0x06
	32	#define R07_MT9V011_OUT_CTRL 0x07
	33	#define R09_MT9V011_SHUTTER_WIDTH 0x09
	34	#define R0A_MT9V011_CLK_SPEED 0x0a
	35	#define R0B_MT9V011_RESTART 0x0b
	36	#define R0C_MT9V011_SHUTTER_DELAY 0x0c
	37	#define R0D_MT9V011_RESET 0x0d
	38	#define R1E_MT9V011_DIGITAL_ZOOM 0x1e
	39	#define R20_MT9V011_READ_MODE 0x20
	40	#define R2B_MT9V011_GREEN_1_GAIN 0x2b
	41	#define R2C_MT9V011_BLUE_GAIN 0x2c
	42	#define R2D_MT9V011_RED_GAIN 0x2d
	43	#define R2E_MT9V011_GREEN_2_GAIN 0x2e
	44	#define R35_MT9V011_GLOBAL_GAIN 0x35
	45	#define RF1_MT9V011_CHIP_ENABLE 0xf1
	46
	47	#define MT9V011_VERSION 0x8232
	48	#define MT9V011_REV_B_VERSION 0x8243
	49
7dfba00d MCC	50	/* supported controls */
	51	static struct v4l2_queryctrl mt9v011_qctrl[] = {
	52	{
	53	.id = V4L2_CID_GAIN,
	54	.type = V4L2_CTRL_TYPE_INTEGER,
	55	.name = "Gain",
	56	.minimum = 0,
	57	.maximum = (1 << 10) - 1,
	58	.step = 1,
	59	.default_value = 0x0020,
	60	.flags = 0,
590929f3 JO	61	}, {
	62	.id = V4L2_CID_EXPOSURE,
	63	.type = V4L2_CTRL_TYPE_INTEGER,
	64	.name = "Exposure",
	65	.minimum = 0,
	66	.maximum = 2047,
	67	.step = 1,
	68	.default_value = 0x01fc,
	69	.flags = 0,
7dfba00d MCC	70	}, {
	71	.id = V4L2_CID_RED_BALANCE,
	72	.type = V4L2_CTRL_TYPE_INTEGER,
	73	.name = "Red Balance",
	74	.minimum = -1 << 9,
	75	.maximum = (1 << 9) - 1,
	76	.step = 1,
	77	.default_value = 0,
	78	.flags = 0,
	79	}, {
	80	.id = V4L2_CID_BLUE_BALANCE,
	81	.type = V4L2_CTRL_TYPE_INTEGER,
	82	.name = "Blue Balance",
	83	.minimum = -1 << 9,
	84	.maximum = (1 << 9) - 1,
	85	.step = 1,
	86	.default_value = 0,
	87	.flags = 0,
2526ea6e MCC	88	}, {
	89	.id = V4L2_CID_HFLIP,
	90	.type = V4L2_CTRL_TYPE_BOOLEAN,
	91	.name = "Mirror",
	92	.minimum = 0,
	93	.maximum = 1,
	94	.step = 1,
	95	.default_value = 0,
	96	.flags = 0,
	97	}, {
	98	.id = V4L2_CID_VFLIP,
	99	.type = V4L2_CTRL_TYPE_BOOLEAN,
	100	.name = "Vflip",
	101	.minimum = 0,
	102	.maximum = 1,
	103	.step = 1,
	104	.default_value = 0,
	105	.flags = 0,
	106	}, {
	107	}
7dfba00d MCC	108	};
	109
	110	struct mt9v011 {
	111	struct v4l2_subdev sd;
27fe4a30	112	unsigned width, height;
e11206e6	113	unsigned xtal;
2526ea6e MCC	114	unsigned hflip:1;
2526ea6e MCC	115	unsigned vflip:1;
7dfba00d	116
590929f3	117	u16 global_gain, exposure, red_bal, blue_bal;
7dfba00d MCC	118	};
	119
	120	static inline struct mt9v011 to_mt9v011(struct v4l2_subdev sd)
	121	{
	122	return container_of(sd, struct mt9v011, sd);
	123	}
	124
	125	static int mt9v011_read(struct v4l2_subdev *sd, unsigned char addr)
	126	{
	127	struct i2c_client *c = v4l2_get_subdevdata(sd);
	128	__be16 buffer;
	129	int rc, val;
	130
fbe2800c MCC	131	rc = i2c_master_send(c, &addr, 1);
fbe2800c MCC	132	if (rc != 1)
7dfba00d MCC	133	v4l2_dbg(0, debug, sd,
	134	"i2c i/o error: rc == %d (should be 1)\n", rc);
	135
	136	msleep(10);
	137
fbe2800c MCC	138	rc = i2c_master_recv(c, (char *)&buffer, 2);
fbe2800c MCC	139	if (rc != 2)
7dfba00d	140	v4l2_dbg(0, debug, sd,
fbe2800c	141	"i2c i/o error: rc == %d (should be 2)\n", rc);
7dfba00d MCC	142
	143	val = be16_to_cpu(buffer);
	144
	145	v4l2_dbg(2, debug, sd, "mt9v011: read 0x%02x = 0x%04x\n", addr, val);
	146
	147	return val;
	148	}
	149
	150	static void mt9v011_write(struct v4l2_subdev *sd, unsigned char addr,
	151	u16 value)
	152	{
	153	struct i2c_client *c = v4l2_get_subdevdata(sd);
	154	unsigned char buffer[3];
	155	int rc;
	156
	157	buffer[0] = addr;
	158	buffer[1] = value >> 8;
	159	buffer[2] = value & 0xff;
	160
	161	v4l2_dbg(2, debug, sd,
	162	"mt9v011: writing 0x%02x 0x%04x\n", buffer[0], value);
27fe4a30	163	rc = i2c_master_send(c, buffer, 3);
fbe2800c	164	if (rc != 3)
7dfba00d MCC	165	v4l2_dbg(0, debug, sd,
	166	"i2c i/o error: rc == %d (should be 3)\n", rc);
	167	}
	168
	169
	170	struct i2c_reg_value {
	171	unsigned char reg;
	172	u16 value;
	173	};
	174
	175	/*
	176	* Values used at the original driver
	177	* Some values are marked as Reserved at the datasheet
	178	*/
	179	static const struct i2c_reg_value mt9v011_init_default[] = {
7dfba00d MCC	180	{ R0D_MT9V011_RESET, 0x0001 },
7dfba00d MCC	181	{ R0D_MT9V011_RESET, 0x0000 },
afe09f82	182
afe09f82	183	{ R0C_MT9V011_SHUTTER_DELAY, 0x0000 },
6934e6ff MCC	184	{ R09_MT9V011_SHUTTER_WIDTH, 0x1fc },
	185
	186	{ R0A_MT9V011_CLK_SPEED, 0x0000 },
afe09f82	187	{ R1E_MT9V011_DIGITAL_ZOOM, 0x0000 },
afe09f82	188
e11206e6	189	{ R07_MT9V011_OUT_CTRL, 0x0002 }, /* chip enable */
7dfba00d MCC	190	};
	191
	192	static void set_balance(struct v4l2_subdev *sd)
	193	{
	194	struct mt9v011 *core = to_mt9v011(sd);
	195	u16 green1_gain, green2_gain, blue_gain, red_gain;
590929f3 JO	196	u16 exposure;
	197
	198	exposure = core->exposure;
7dfba00d MCC	199
	200	green1_gain = core->global_gain;
	201	green2_gain = core->global_gain;
	202
	203	blue_gain = core->global_gain +
	204	core->global_gain * core->blue_bal / (1 << 9);
	205
	206	red_gain = core->global_gain +
	207	core->global_gain * core->blue_bal / (1 << 9);
	208
	209	mt9v011_write(sd, R2B_MT9V011_GREEN_1_GAIN, green1_gain);
	210	mt9v011_write(sd, R2E_MT9V011_GREEN_2_GAIN, green1_gain);
	211	mt9v011_write(sd, R2C_MT9V011_BLUE_GAIN, blue_gain);
	212	mt9v011_write(sd, R2D_MT9V011_RED_GAIN, red_gain);
590929f3	213	mt9v011_write(sd, R09_MT9V011_SHUTTER_WIDTH, exposure);
7dfba00d MCC	214	}
7dfba00d MCC	215
83053f7f	216	static void calc_fps(struct v4l2_subdev sd, u32 numerator, u32 *denominator)
e11206e6 MCC	217	{
	218	struct mt9v011 *core = to_mt9v011(sd);
	219	unsigned height, width, hblank, vblank, speed;
	220	unsigned row_time, t_time;
	221	u64 frames_per_ms;
	222	unsigned tmp;
	223
	224	height = mt9v011_read(sd, R03_MT9V011_HEIGHT);
	225	width = mt9v011_read(sd, R04_MT9V011_WIDTH);
	226	hblank = mt9v011_read(sd, R05_MT9V011_HBLANK);
	227	vblank = mt9v011_read(sd, R06_MT9V011_VBLANK);
	228	speed = mt9v011_read(sd, R0A_MT9V011_CLK_SPEED);
	229
	230	row_time = (width + 113 + hblank) * (speed + 2);
	231	t_time = row_time * (height + vblank + 1);
	232
	233	frames_per_ms = core->xtal * 1000l;
	234	do_div(frames_per_ms, t_time);
	235	tmp = frames_per_ms;
	236
	237	v4l2_dbg(1, debug, sd, "Programmed to %u.%03u fps (%d pixel clcks)\n",
	238	tmp / 1000, tmp % 1000, t_time);
83053f7f MCC	239
	240	if (numerator && denominator) {
	241	*numerator = 1000;
	242	*denominator = (u32)frames_per_ms;
	243	}
	244	}
	245
	246	static u16 calc_speed(struct v4l2_subdev *sd, u32 numerator, u32 denominator)
	247	{
	248	struct mt9v011 *core = to_mt9v011(sd);
	249	unsigned height, width, hblank, vblank;
	250	unsigned row_time, line_time;
	251	u64 t_time, speed;
	252
	253	/* Avoid bogus calculus */
	254	if (!numerator \|\| !denominator)
	255	return 0;
	256
	257	height = mt9v011_read(sd, R03_MT9V011_HEIGHT);
	258	width = mt9v011_read(sd, R04_MT9V011_WIDTH);
	259	hblank = mt9v011_read(sd, R05_MT9V011_HBLANK);
	260	vblank = mt9v011_read(sd, R06_MT9V011_VBLANK);
	261
	262	row_time = width + 113 + hblank;
	263	line_time = height + vblank + 1;
	264
	265	t_time = core->xtal * ((u64)numerator);
	266	/* round to the closest value */
	267	t_time += denominator / 2;
	268	do_div(t_time, denominator);
	269
	270	speed = t_time;
	271	do_div(speed, row_time * line_time);
	272
	273	/* Avoid having a negative value for speed */
	274	if (speed < 2)
	275	speed = 0;
	276	else
	277	speed -= 2;
	278
	279	/* Avoid speed overflow */
	280	if (speed > 15)
	281	return 15;
	282
	283	return (u16)speed;
e11206e6 MCC	284	}
e11206e6 MCC	285
27fe4a30 MCC	286	static void set_res(struct v4l2_subdev *sd)
	287	{
	288	struct mt9v011 *core = to_mt9v011(sd);
	289	unsigned vstart, hstart;
	290
	291	/*
	292	* The mt9v011 doesn't have scaling. So, in order to select the desired
	293	* resolution, we're cropping at the middle of the sensor.
	294	* hblank and vblank should be adjusted, in order to warrant that
	295	* we'll preserve the line timings for 30 fps, no matter what resolution
	296	* is selected.
6934e6ff MCC	297	* NOTE: datasheet says that width (and height) should be filled with
	298	* width-1. However, this doesn't work, since one pixel per line will
	299	* be missing.
27fe4a30 MCC	300	*/
27fe4a30 MCC	301
1048af2f	302	hstart = 20 + (640 - core->width) / 2;
27fe4a30 MCC	303	mt9v011_write(sd, R02_MT9V011_COLSTART, hstart);
	304	mt9v011_write(sd, R04_MT9V011_WIDTH, core->width);
	305	mt9v011_write(sd, R05_MT9V011_HBLANK, 771 - core->width);
	306
c180604a	307	vstart = 8 + (480 - core->height) / 2;
27fe4a30 MCC	308	mt9v011_write(sd, R01_MT9V011_ROWSTART, vstart);
	309	mt9v011_write(sd, R03_MT9V011_HEIGHT, core->height);
	310	mt9v011_write(sd, R06_MT9V011_VBLANK, 508 - core->height);
e11206e6	311
83053f7f	312	calc_fps(sd, NULL, NULL);
27fe4a30 MCC	313	};
27fe4a30 MCC	314
2526ea6e MCC	315	static void set_read_mode(struct v4l2_subdev *sd)
	316	{
	317	struct mt9v011 *core = to_mt9v011(sd);
	318	unsigned mode = 0x1000;
	319
	320	if (core->hflip)
	321	mode \|= 0x4000;
	322
	323	if (core->vflip)
	324	mode \|= 0x8000;
	325
	326	mt9v011_write(sd, R20_MT9V011_READ_MODE, mode);
	327	}
	328
7dfba00d MCC	329	static int mt9v011_reset(struct v4l2_subdev *sd, u32 val)
7dfba00d MCC	330	{
7dfba00d MCC	331	int i;
7dfba00d MCC	332
7dfba00d MCC	333	for (i = 0; i < ARRAY_SIZE(mt9v011_init_default); i++)
	334	mt9v011_write(sd, mt9v011_init_default[i].reg,
	335	mt9v011_init_default[i].value);
	336
	337	set_balance(sd);
27fe4a30	338	set_res(sd);
2526ea6e	339	set_read_mode(sd);
7dfba00d MCC	340
	341	return 0;
	342	};
	343
	344	static int mt9v011_g_ctrl(struct v4l2_subdev sd, struct v4l2_control ctrl)
	345	{
	346	struct mt9v011 *core = to_mt9v011(sd);
	347
	348	v4l2_dbg(1, debug, sd, "g_ctrl called\n");
	349
	350	switch (ctrl->id) {
	351	case V4L2_CID_GAIN:
	352	ctrl->value = core->global_gain;
	353	return 0;
590929f3 JO	354	case V4L2_CID_EXPOSURE:
	355	ctrl->value = core->exposure;
	356	return 0;
7dfba00d MCC	357	case V4L2_CID_RED_BALANCE:
	358	ctrl->value = core->red_bal;
	359	return 0;
	360	case V4L2_CID_BLUE_BALANCE:
	361	ctrl->value = core->blue_bal;
	362	return 0;
2526ea6e MCC	363	case V4L2_CID_HFLIP:
	364	ctrl->value = core->hflip ? 1 : 0;
	365	return 0;
	366	case V4L2_CID_VFLIP:
	367	ctrl->value = core->vflip ? 1 : 0;
	368	return 0;
7dfba00d MCC	369	}
	370	return -EINVAL;
	371	}
	372
9873740b MCC	373	static int mt9v011_queryctrl(struct v4l2_subdev sd, struct v4l2_queryctrl qc)
	374	{
	375	int i;
	376
	377	v4l2_dbg(1, debug, sd, "queryctrl called\n");
	378
	379	for (i = 0; i < ARRAY_SIZE(mt9v011_qctrl); i++)
	380	if (qc->id && qc->id == mt9v011_qctrl[i].id) {
	381	memcpy(qc, &(mt9v011_qctrl[i]),
	382	sizeof(*qc));
	383	return 0;
	384	}
	385
	386	return -EINVAL;
	387	}
	388
	389
7dfba00d MCC	390	static int mt9v011_s_ctrl(struct v4l2_subdev sd, struct v4l2_control ctrl)
	391	{
	392	struct mt9v011 *core = to_mt9v011(sd);
	393	u8 i, n;
	394	n = ARRAY_SIZE(mt9v011_qctrl);
	395
	396	for (i = 0; i < n; i++) {
	397	if (ctrl->id != mt9v011_qctrl[i].id)
	398	continue;
	399	if (ctrl->value < mt9v011_qctrl[i].minimum \|\|
	400	ctrl->value > mt9v011_qctrl[i].maximum)
	401	return -ERANGE;
	402	v4l2_dbg(1, debug, sd, "s_ctrl: id=%d, value=%d\n",
	403	ctrl->id, ctrl->value);
	404	break;
	405	}
	406
	407	switch (ctrl->id) {
	408	case V4L2_CID_GAIN:
	409	core->global_gain = ctrl->value;
	410	break;
590929f3 JO	411	case V4L2_CID_EXPOSURE:
	412	core->exposure = ctrl->value;
	413	break;
7dfba00d MCC	414	case V4L2_CID_RED_BALANCE:
	415	core->red_bal = ctrl->value;
	416	break;
	417	case V4L2_CID_BLUE_BALANCE:
	418	core->blue_bal = ctrl->value;
	419	break;
2526ea6e MCC	420	case V4L2_CID_HFLIP:
	421	core->hflip = ctrl->value;
	422	set_read_mode(sd);
	423	return 0;
	424	case V4L2_CID_VFLIP:
	425	core->vflip = ctrl->value;
	426	set_read_mode(sd);
	427	return 0;
7dfba00d MCC	428	default:
	429	return -EINVAL;
	430	}
	431
	432	set_balance(sd);
	433
	434	return 0;
	435	}
	436
ea01b11a HV	437	static int mt9v011_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned index,
ea01b11a HV	438	enum v4l2_mbus_pixelcode *code)
27fe4a30	439	{
ea01b11a	440	if (index > 0)
27fe4a30 MCC	441	return -EINVAL;
27fe4a30 MCC	442
ea01b11a	443	*code = V4L2_MBUS_FMT_SGRBG8_1X8;
27fe4a30 MCC	444	return 0;
	445	}
	446
ea01b11a	447	static int mt9v011_try_mbus_fmt(struct v4l2_subdev sd, struct v4l2_mbus_framefmt fmt)
27fe4a30	448	{
ea01b11a	449	if (fmt->code != V4L2_MBUS_FMT_SGRBG8_1X8)
27fe4a30 MCC	450	return -EINVAL;
27fe4a30 MCC	451
ea01b11a HV	452	v4l_bound_align_image(&fmt->width, 48, 639, 1,
	453	&fmt->height, 32, 480, 1, 0);
	454	fmt->field = V4L2_FIELD_NONE;
	455	fmt->colorspace = V4L2_COLORSPACE_SRGB;
27fe4a30 MCC	456
	457	return 0;
	458	}
	459
83053f7f MCC	460	static int mt9v011_g_parm(struct v4l2_subdev sd, struct v4l2_streamparm parms)
	461	{
	462	struct v4l2_captureparm *cp = &parms->parm.capture;
	463
	464	if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
	465	return -EINVAL;
	466
	467	memset(cp, 0, sizeof(struct v4l2_captureparm));
	468	cp->capability = V4L2_CAP_TIMEPERFRAME;
	469	calc_fps(sd,
	470	&cp->timeperframe.numerator,
	471	&cp->timeperframe.denominator);
	472
	473	return 0;
	474	}
	475
	476	static int mt9v011_s_parm(struct v4l2_subdev sd, struct v4l2_streamparm parms)
	477	{
	478	struct v4l2_captureparm *cp = &parms->parm.capture;
	479	struct v4l2_fract *tpf = &cp->timeperframe;
	480	u16 speed;
	481
	482	if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
	483	return -EINVAL;
	484	if (cp->extendedmode != 0)
	485	return -EINVAL;
	486
	487	speed = calc_speed(sd, tpf->numerator, tpf->denominator);
	488
	489	mt9v011_write(sd, R0A_MT9V011_CLK_SPEED, speed);
	490	v4l2_dbg(1, debug, sd, "Setting speed to %d\n", speed);
	491
	492	/* Recalculate and update fps info */
	493	calc_fps(sd, &tpf->numerator, &tpf->denominator);
	494
	495	return 0;
	496	}
	497
ea01b11a	498	static int mt9v011_s_mbus_fmt(struct v4l2_subdev sd, struct v4l2_mbus_framefmt fmt)
27fe4a30	499	{
27fe4a30 MCC	500	struct mt9v011 *core = to_mt9v011(sd);
	501	int rc;
	502
ea01b11a	503	rc = mt9v011_try_mbus_fmt(sd, fmt);
27fe4a30 MCC	504	if (rc < 0)
	505	return -EINVAL;
	506
ea01b11a HV	507	core->width = fmt->width;
ea01b11a HV	508	core->height = fmt->height;
27fe4a30 MCC	509
	510	set_res(sd);
	511
	512	return 0;
	513	}
	514
7dfba00d MCC	515	#ifdef CONFIG_VIDEO_ADV_DEBUG
	516	static int mt9v011_g_register(struct v4l2_subdev *sd,
	517	struct v4l2_dbg_register *reg)
	518	{
	519	struct i2c_client *client = v4l2_get_subdevdata(sd);
	520
	521	if (!v4l2_chip_match_i2c_client(client, &reg->match))
	522	return -EINVAL;
	523	if (!capable(CAP_SYS_ADMIN))
	524	return -EPERM;
	525
	526	reg->val = mt9v011_read(sd, reg->reg & 0xff);
	527	reg->size = 2;
	528
	529	return 0;
	530	}
	531
	532	static int mt9v011_s_register(struct v4l2_subdev *sd,
	533	struct v4l2_dbg_register *reg)
	534	{
	535	struct i2c_client *client = v4l2_get_subdevdata(sd);
	536
	537	if (!v4l2_chip_match_i2c_client(client, &reg->match))
	538	return -EINVAL;
	539	if (!capable(CAP_SYS_ADMIN))
	540	return -EPERM;
	541
	542	mt9v011_write(sd, reg->reg & 0xff, reg->val & 0xffff);
	543
	544	return 0;
	545	}
	546	#endif
	547
	548	static int mt9v011_g_chip_ident(struct v4l2_subdev *sd,
	549	struct v4l2_dbg_chip_ident *chip)
	550	{
296544e1	551	u16 version;
7dfba00d MCC	552	struct i2c_client *client = v4l2_get_subdevdata(sd);
7dfba00d MCC	553
296544e1 MCC	554	version = mt9v011_read(sd, R00_MT9V011_CHIP_VERSION);
296544e1 MCC	555
7dfba00d	556	return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_MT9V011,
296544e1	557	version);
7dfba00d MCC	558	}
	559
	560	static const struct v4l2_subdev_core_ops mt9v011_core_ops = {
9873740b	561	.queryctrl = mt9v011_queryctrl,
7dfba00d MCC	562	.g_ctrl = mt9v011_g_ctrl,
	563	.s_ctrl = mt9v011_s_ctrl,
	564	.reset = mt9v011_reset,
	565	.g_chip_ident = mt9v011_g_chip_ident,
	566	#ifdef CONFIG_VIDEO_ADV_DEBUG
	567	.g_register = mt9v011_g_register,
	568	.s_register = mt9v011_s_register,
	569	#endif
	570	};
	571
27fe4a30	572	static const struct v4l2_subdev_video_ops mt9v011_video_ops = {
ea01b11a HV	573	.enum_mbus_fmt = mt9v011_enum_mbus_fmt,
	574	.try_mbus_fmt = mt9v011_try_mbus_fmt,
	575	.s_mbus_fmt = mt9v011_s_mbus_fmt,
83053f7f MCC	576	.g_parm = mt9v011_g_parm,
83053f7f MCC	577	.s_parm = mt9v011_s_parm,
27fe4a30 MCC	578	};
27fe4a30 MCC	579
7dfba00d	580	static const struct v4l2_subdev_ops mt9v011_ops = {
27fe4a30 MCC	581	.core = &mt9v011_core_ops,
27fe4a30 MCC	582	.video = &mt9v011_video_ops,
7dfba00d MCC	583	};
	584
	585
	586	/****************************************************************************
	587	I2C Client & Driver
	588	****************************************************************************/
	589
	590	static int mt9v011_probe(struct i2c_client *c,
	591	const struct i2c_device_id *id)
	592	{
27fe4a30	593	u16 version;
7dfba00d MCC	594	struct mt9v011 *core;
	595	struct v4l2_subdev *sd;
	596
	597	/* Check if the adapter supports the needed features */
	598	if (!i2c_check_functionality(c->adapter,
	599	I2C_FUNC_SMBUS_READ_BYTE \| I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
	600	return -EIO;
	601
	602	core = kzalloc(sizeof(struct mt9v011), GFP_KERNEL);
	603	if (!core)
	604	return -ENOMEM;
	605
7dfba00d MCC	606	sd = &core->sd;
7dfba00d MCC	607	v4l2_i2c_subdev_init(sd, c, &mt9v011_ops);
27fe4a30 MCC	608
	609	/* Check if the sensor is really a MT9V011 */
	610	version = mt9v011_read(sd, R00_MT9V011_CHIP_VERSION);
296544e1 MCC	611	if ((version != MT9V011_VERSION) &&
	612	(version != MT9V011_REV_B_VERSION)) {
	613	v4l2_info(sd, "*** unknown micron chip detected (0x%04x).\n",
27fe4a30 MCC	614	version);
	615	kfree(core);
	616	return -EINVAL;
	617	}
	618
	619	core->global_gain = 0x0024;
590929f3	620	core->exposure = 0x01fc;
27fe4a30 MCC	621	core->width = 640;
27fe4a30 MCC	622	core->height = 480;
e11206e6	623	core->xtal = 27000000; /* Hz */
27fe4a30	624
3c7c9370 HV	625	if (c->dev.platform_data) {
	626	struct mt9v011_platform_data *pdata = c->dev.platform_data;
	627
	628	core->xtal = pdata->xtal;
	629	v4l2_dbg(1, debug, sd, "xtal set to %d.%03d MHz\n",
	630	core->xtal / 1000000, (core->xtal / 1000) % 1000);
	631	}
	632
296544e1 MCC	633	v4l_info(c, "chip found @ 0x%02x (%s - chip version 0x%04x)\n",
296544e1 MCC	634	c->addr << 1, c->adapter->name, version);
7dfba00d MCC	635
	636	return 0;
	637	}
	638
	639	static int mt9v011_remove(struct i2c_client *c)
	640	{
	641	struct v4l2_subdev *sd = i2c_get_clientdata(c);
	642
	643	v4l2_dbg(1, debug, sd,
	644	"mt9v011.c: removing mt9v011 adapter on address 0x%x\n",
	645	c->addr << 1);
	646
	647	v4l2_device_unregister_subdev(sd);
	648	kfree(to_mt9v011(sd));
	649	return 0;
	650	}
	651
	652	/* ----------------------------------------------------------------------- */
	653
	654	static const struct i2c_device_id mt9v011_id[] = {
	655	{ "mt9v011", 0 },
	656	{ }
	657	};
	658	MODULE_DEVICE_TABLE(i2c, mt9v011_id);
	659
6ce58bea HV	660	static struct i2c_driver mt9v011_driver = {
	661	.driver = {
	662	.owner = THIS_MODULE,
	663	.name = "mt9v011",
	664	},
	665	.probe = mt9v011_probe,
	666	.remove = mt9v011_remove,
	667	.id_table = mt9v011_id,
7dfba00d	668	};
6ce58bea HV	669
	670	static __init int init_mt9v011(void)
	671	{
	672	return i2c_add_driver(&mt9v011_driver);
	673	}
	674
	675	static __exit void exit_mt9v011(void)
	676	{
	677	i2c_del_driver(&mt9v011_driver);
	678	}
	679
	680	module_init(init_mt9v011);
	681	module_exit(exit_mt9v011);