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V4L/DVB (4238): Make sure flags field is initialized when quering a control in pvrusb2
[mirror_ubuntu-artful-kernel.git] / drivers / media / video / pvrusb2 / pvrusb2-hdw.c
CommitLineData
d855497e
MI		 1/*
2 *
3 * $Id$
4 *
5 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22#include <linux/errno.h>
23#include <linux/string.h>
24#include <linux/slab.h>
25#include <linux/firmware.h>
d855497e 26#include <linux/videodev2.h>
b2bbaa93 27#include <asm/semaphore.h>
d855497e
MI		 28#include "pvrusb2.h"
29#include "pvrusb2-std.h"
30#include "pvrusb2-util.h"
31#include "pvrusb2-hdw.h"
32#include "pvrusb2-i2c-core.h"
33#include "pvrusb2-tuner.h"
34#include "pvrusb2-eeprom.h"
35#include "pvrusb2-hdw-internal.h"
36#include "pvrusb2-encoder.h"
37#include "pvrusb2-debug.h"
38
39struct usb_device_id pvr2_device_table[] = {
40 [PVR2_HDW_TYPE_29XXX] = { USB_DEVICE(0x2040, 0x2900) },
41#ifdef CONFIG_VIDEO_PVRUSB2_24XXX
42 [PVR2_HDW_TYPE_24XXX] = { USB_DEVICE(0x2040, 0x2400) },
43#endif
44 { }
45};
46
47MODULE_DEVICE_TABLE(usb, pvr2_device_table);
48
49static const char *pvr2_device_names[] = {
50 [PVR2_HDW_TYPE_29XXX] = "WinTV PVR USB2 Model Category 29xxxx",
51#ifdef CONFIG_VIDEO_PVRUSB2_24XXX
52 [PVR2_HDW_TYPE_24XXX] = "WinTV PVR USB2 Model Category 24xxxx",
53#endif
54};
55
56struct pvr2_string_table {
57 const char **lst;
58 unsigned int cnt;
59};
60
61#ifdef CONFIG_VIDEO_PVRUSB2_24XXX
62// Names of other client modules to request for 24xxx model hardware
63static const char *pvr2_client_24xxx[] = {
64 "cx25840",
65 "tuner",
66 "tda9887",
67 "wm8775",
68};
69#endif
70
71// Names of other client modules to request for 29xxx model hardware
72static const char *pvr2_client_29xxx[] = {
73 "msp3400",
74 "saa7115",
75 "tuner",
76 "tda9887",
77};
78
79static struct pvr2_string_table pvr2_client_lists[] = {
80 [PVR2_HDW_TYPE_29XXX] = {
81 pvr2_client_29xxx,
82 sizeof(pvr2_client_29xxx)/sizeof(pvr2_client_29xxx[0]),
83 },
84#ifdef CONFIG_VIDEO_PVRUSB2_24XXX
85 [PVR2_HDW_TYPE_24XXX] = {
86 pvr2_client_24xxx,
87 sizeof(pvr2_client_24xxx)/sizeof(pvr2_client_24xxx[0]),
88 },
89#endif
90};
91
92static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = 0};
93DECLARE_MUTEX(pvr2_unit_sem);
94
95static int ctlchg = 0;
96static int initusbreset = 1;
97static int procreload = 0;
98static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
99static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
100static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
101static int init_pause_msec = 0;
102
103module_param(ctlchg, int, S_IRUGO|S_IWUSR);
104MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
105module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
106MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
107module_param(initusbreset, int, S_IRUGO|S_IWUSR);
108MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
109module_param(procreload, int, S_IRUGO|S_IWUSR);
110MODULE_PARM_DESC(procreload,
111 "Attempt init failure recovery with firmware reload");
112module_param_array(tuner, int, NULL, 0444);
113MODULE_PARM_DESC(tuner,"specify installed tuner type");
114module_param_array(video_std, int, NULL, 0444);
115MODULE_PARM_DESC(video_std,"specify initial video standard");
116module_param_array(tolerance, int, NULL, 0444);
117MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
118
119#define PVR2_CTL_WRITE_ENDPOINT 0x01
120#define PVR2_CTL_READ_ENDPOINT 0x81
121
122#define PVR2_GPIO_IN 0x9008
123#define PVR2_GPIO_OUT 0x900c
124#define PVR2_GPIO_DIR 0x9020
125
126#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
127
128#define PVR2_FIRMWARE_ENDPOINT 0x02
129
130/* size of a firmware chunk */
131#define FIRMWARE_CHUNK_SIZE 0x2000
132
c05c0462 133
d855497e
MI		 134static const char *control_values_srate[] = {
135 [PVR2_CVAL_SRATE_48] = "48KHz",
136 [PVR2_CVAL_SRATE_44_1] = "44.1KHz",
137};
138
139
140static const char *control_values_audiobitrate[] = {
141 [PVR2_CVAL_AUDIOBITRATE_384] = "384kb/s",
142 [PVR2_CVAL_AUDIOBITRATE_320] = "320kb/s",
143 [PVR2_CVAL_AUDIOBITRATE_256] = "256kb/s",
144 [PVR2_CVAL_AUDIOBITRATE_224] = "224kb/s",
145 [PVR2_CVAL_AUDIOBITRATE_192] = "192kb/s",
146 [PVR2_CVAL_AUDIOBITRATE_160] = "160kb/s",
147 [PVR2_CVAL_AUDIOBITRATE_128] = "128kb/s",
148 [PVR2_CVAL_AUDIOBITRATE_112] = "112kb/s",
149 [PVR2_CVAL_AUDIOBITRATE_96] = "96kb/s",
150 [PVR2_CVAL_AUDIOBITRATE_80] = "80kb/s",
151 [PVR2_CVAL_AUDIOBITRATE_64] = "64kb/s",
152 [PVR2_CVAL_AUDIOBITRATE_56] = "56kb/s",
153 [PVR2_CVAL_AUDIOBITRATE_48] = "48kb/s",
154 [PVR2_CVAL_AUDIOBITRATE_32] = "32kb/s",
155 [PVR2_CVAL_AUDIOBITRATE_VBR] = "VBR",
156};
157
158
159static const char *control_values_audioemphasis[] = {
160 [PVR2_CVAL_AUDIOEMPHASIS_NONE] = "None",
161 [PVR2_CVAL_AUDIOEMPHASIS_50_15] = "50/15us",
162 [PVR2_CVAL_AUDIOEMPHASIS_CCITT] = "CCITT J.17",
163};
164
165
166static const char *control_values_input[] = {
167 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
168 [PVR2_CVAL_INPUT_RADIO] = "radio",
169 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
170 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
171};
172
173
174static const char *control_values_audiomode[] = {
175 [V4L2_TUNER_MODE_MONO] = "Mono",
176 [V4L2_TUNER_MODE_STEREO] = "Stereo",
177 [V4L2_TUNER_MODE_LANG1] = "Lang1",
178 [V4L2_TUNER_MODE_LANG2] = "Lang2",
179 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
180};
181
182
183static const char *control_values_hsm[] = {
184 [PVR2_CVAL_HSM_FAIL] = "Fail",
185 [PVR2_CVAL_HSM_HIGH] = "High",
186 [PVR2_CVAL_HSM_FULL] = "Full",
187};
188
189
190static const char *control_values_subsystem[] = {
191 [PVR2_SUBSYS_B_ENC_FIRMWARE] = "enc_firmware",
192 [PVR2_SUBSYS_B_ENC_CFG] = "enc_config",
193 [PVR2_SUBSYS_B_DIGITIZER_RUN] = "digitizer_run",
194 [PVR2_SUBSYS_B_USBSTREAM_RUN] = "usbstream_run",
195 [PVR2_SUBSYS_B_ENC_RUN] = "enc_run",
196};
197
198
199static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
200{
201 struct pvr2_hdw *hdw = cptr->hdw;
202 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
203 *vp = hdw->freqTable[hdw->freqProgSlot-1];
204 } else {
205 *vp = 0;
206 }
207 return 0;
208}
209
210static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
211{
212 struct pvr2_hdw *hdw = cptr->hdw;
213 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
214 hdw->freqTable[hdw->freqProgSlot-1] = v;
215 }
216 return 0;
217}
218
219static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
220{
221 *vp = cptr->hdw->freqProgSlot;
222 return 0;
223}
224
225static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
226{
227 struct pvr2_hdw *hdw = cptr->hdw;
228 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
229 hdw->freqProgSlot = v;
230 }
231 return 0;
232}
233
234static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
235{
236 *vp = cptr->hdw->freqSlot;
237 return 0;
238}
239
240static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int v)
241{
242 unsigned freq = 0;
243 struct pvr2_hdw *hdw = cptr->hdw;
244 hdw->freqSlot = v;
245 if ((hdw->freqSlot > 0) && (hdw->freqSlot <= FREQTABLE_SIZE)) {
246 freq = hdw->freqTable[hdw->freqSlot-1];
247 }
248 if (freq && (freq != hdw->freqVal)) {
249 hdw->freqVal = freq;
250 hdw->freqDirty = !0;
251 }
252 return 0;
253}
254
255static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
256{
257 *vp = cptr->hdw->freqVal;
258 return 0;
259}
260
261static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
262{
263 return cptr->hdw->freqDirty != 0;
264}
265
266static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
267{
268 cptr->hdw->freqDirty = 0;
269}
270
271static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
272{
273 struct pvr2_hdw *hdw = cptr->hdw;
274 hdw->freqVal = v;
275 hdw->freqDirty = !0;
276 hdw->freqSlot = 0;
277 return 0;
278}
279
280static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
281{
282 *vp = cptr->hdw->flag_streaming_enabled;
283 return 0;
284}
285
286static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
287{
288 int result = pvr2_hdw_is_hsm(cptr->hdw);
289 *vp = PVR2_CVAL_HSM_FULL;
290 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
291 if (result) *vp = PVR2_CVAL_HSM_HIGH;
292 return 0;
293}
294
295static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
296{
297 *vp = cptr->hdw->std_mask_avail;
298 return 0;
299}
300
301static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
302{
303 struct pvr2_hdw *hdw = cptr->hdw;
304 v4l2_std_id ns;
305 ns = hdw->std_mask_avail;
306 ns = (ns & ~m) | (v & m);
307 if (ns == hdw->std_mask_avail) return 0;
308 hdw->std_mask_avail = ns;
309 pvr2_hdw_internal_set_std_avail(hdw);
310 pvr2_hdw_internal_find_stdenum(hdw);
311 return 0;
312}
313
314static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
315 char *bufPtr,unsigned int bufSize,
316 unsigned int *len)
317{
318 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
319 return 0;
320}
321
322static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
323 const char *bufPtr,unsigned int bufSize,
324 int *mskp,int *valp)
325{
326 int ret;
327 v4l2_std_id id;
328 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
329 if (ret < 0) return ret;
330 if (mskp) *mskp = id;
331 if (valp) *valp = id;
332 return 0;
333}
334
335static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
336{
337 *vp = cptr->hdw->std_mask_cur;
338 return 0;
339}
340
341static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
342{
343 struct pvr2_hdw *hdw = cptr->hdw;
344 v4l2_std_id ns;
345 ns = hdw->std_mask_cur;
346 ns = (ns & ~m) | (v & m);
347 if (ns == hdw->std_mask_cur) return 0;
348 hdw->std_mask_cur = ns;
349 hdw->std_dirty = !0;
350 pvr2_hdw_internal_find_stdenum(hdw);
351 return 0;
352}
353
354static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
355{
356 return cptr->hdw->std_dirty != 0;
357}
358
359static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
360{
361 cptr->hdw->std_dirty = 0;
362}
363
364static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
365{
366 *vp = ((pvr2_hdw_get_signal_status_internal(cptr->hdw) &
367 PVR2_SIGNAL_OK) ? 1 : 0);
368 return 0;
369}
370
371static int ctrl_subsys_get(struct pvr2_ctrl *cptr,int *vp)
372{
373 *vp = cptr->hdw->subsys_enabled_mask;
374 return 0;
375}
376
377static int ctrl_subsys_set(struct pvr2_ctrl *cptr,int m,int v)
378{
379 pvr2_hdw_subsys_bit_chg_no_lock(cptr->hdw,m,v);
380 return 0;
381}
382
383static int ctrl_subsys_stream_get(struct pvr2_ctrl *cptr,int *vp)
384{
385 *vp = cptr->hdw->subsys_stream_mask;
386 return 0;
387}
388
389static int ctrl_subsys_stream_set(struct pvr2_ctrl *cptr,int m,int v)
390{
391 pvr2_hdw_subsys_stream_bit_chg_no_lock(cptr->hdw,m,v);
392 return 0;
393}
394
395static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
396{
397 struct pvr2_hdw *hdw = cptr->hdw;
398 if (v < 0) return -EINVAL;
399 if (v > hdw->std_enum_cnt) return -EINVAL;
400 hdw->std_enum_cur = v;
401 if (!v) return 0;
402 v--;
403 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
404 hdw->std_mask_cur = hdw->std_defs[v].id;
405 hdw->std_dirty = !0;
406 return 0;
407}
408
409
410static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
411{
412 *vp = cptr->hdw->std_enum_cur;
413 return 0;
414}
415
416
417static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
418{
419 return cptr->hdw->std_dirty != 0;
420}
421
422
423static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
424{
425 cptr->hdw->std_dirty = 0;
426}
427
428
429#define DEFINT(vmin,vmax) \
430 .type = pvr2_ctl_int, \
431 .def.type_int.min_value = vmin, \
432 .def.type_int.max_value = vmax
433
434#define DEFENUM(tab) \
435 .type = pvr2_ctl_enum, \
436 .def.type_enum.count = (sizeof(tab)/sizeof((tab)[0])), \
437 .def.type_enum.value_names = tab
438
439#define DEFMASK(msk,tab) \
440 .type = pvr2_ctl_bitmask, \
441 .def.type_bitmask.valid_bits = msk, \
442 .def.type_bitmask.bit_names = tab
443
444#define DEFREF(vname) \
445 .set_value = ctrl_set_##vname, \
446 .get_value = ctrl_get_##vname, \
447 .is_dirty = ctrl_isdirty_##vname, \
448 .clear_dirty = ctrl_cleardirty_##vname
449
450
451#define VCREATE_FUNCS(vname) \
452static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
453{*vp = cptr->hdw->vname##_val; return 0;} \
454static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
455{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
456static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
457{return cptr->hdw->vname##_dirty != 0;} \
458static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
459{cptr->hdw->vname##_dirty = 0;}
460
461VCREATE_FUNCS(brightness)
462VCREATE_FUNCS(contrast)
463VCREATE_FUNCS(saturation)
464VCREATE_FUNCS(hue)
465VCREATE_FUNCS(volume)
466VCREATE_FUNCS(balance)
467VCREATE_FUNCS(bass)
468VCREATE_FUNCS(treble)
469VCREATE_FUNCS(mute)
c05c0462
MI		 470VCREATE_FUNCS(input)
471VCREATE_FUNCS(audiomode)
472VCREATE_FUNCS(res_hor)
473VCREATE_FUNCS(res_ver)
d855497e
MI		 474VCREATE_FUNCS(srate)
475VCREATE_FUNCS(audiobitrate)
476VCREATE_FUNCS(audiocrc)
477VCREATE_FUNCS(audioemphasis)
478VCREATE_FUNCS(vbr)
479VCREATE_FUNCS(videobitrate)
480VCREATE_FUNCS(videopeak)
d855497e
MI		 481VCREATE_FUNCS(interlace)
482VCREATE_FUNCS(audiolayer)
483
484#define MIN_FREQ 55250000L
485#define MAX_FREQ 850000000L
486
487/* Table definition of all controls which can be manipulated */
488static const struct pvr2_ctl_info control_defs[] = {
489 {
490 .v4l_id = V4L2_CID_BRIGHTNESS,
491 .desc = "Brightness",
492 .name = "brightness",
493 .default_value = 128,
494 DEFREF(brightness),
495 DEFINT(0,255),
496 },{
497 .v4l_id = V4L2_CID_CONTRAST,
498 .desc = "Contrast",
499 .name = "contrast",
500 .default_value = 68,
501 DEFREF(contrast),
502 DEFINT(0,127),
503 },{
504 .v4l_id = V4L2_CID_SATURATION,
505 .desc = "Saturation",
506 .name = "saturation",
507 .default_value = 64,
508 DEFREF(saturation),
509 DEFINT(0,127),
510 },{
511 .v4l_id = V4L2_CID_HUE,
512 .desc = "Hue",
513 .name = "hue",
514 .default_value = 0,
515 DEFREF(hue),
516 DEFINT(-128,127),
517 },{
518 .v4l_id = V4L2_CID_AUDIO_VOLUME,
519 .desc = "Volume",
520 .name = "volume",
521 .default_value = 65535,
522 DEFREF(volume),
523 DEFINT(0,65535),
524 },{
525 .v4l_id = V4L2_CID_AUDIO_BALANCE,
526 .desc = "Balance",
527 .name = "balance",
528 .default_value = 0,
529 DEFREF(balance),
530 DEFINT(-32768,32767),
531 },{
532 .v4l_id = V4L2_CID_AUDIO_BASS,
533 .desc = "Bass",
534 .name = "bass",
535 .default_value = 0,
536 DEFREF(bass),
537 DEFINT(-32768,32767),
538 },{
539 .v4l_id = V4L2_CID_AUDIO_TREBLE,
540 .desc = "Treble",
541 .name = "treble",
542 .default_value = 0,
543 DEFREF(treble),
544 DEFINT(-32768,32767),
545 },{
546 .v4l_id = V4L2_CID_AUDIO_MUTE,
547 .desc = "Mute",
548 .name = "mute",
549 .default_value = 0,
550 DEFREF(mute),
551 DEFINT(0,1),
c05c0462
MI		 552 },{
553 .desc = "Video Source",
554 .name = "input",
555 .internal_id = PVR2_CID_INPUT,
556 .default_value = PVR2_CVAL_INPUT_TV,
557 DEFREF(input),
558 DEFENUM(control_values_input),
559 },{
560 .desc = "Audio Mode",
561 .name = "audio_mode",
562 .internal_id = PVR2_CID_AUDIOMODE,
563 .default_value = V4L2_TUNER_MODE_STEREO,
564 DEFREF(audiomode),
565 DEFENUM(control_values_audiomode),
566 },{
567 .desc = "Horizontal capture resolution",
568 .name = "resolution_hor",
569 .internal_id = PVR2_CID_HRES,
570 .default_value = 720,
571 DEFREF(res_hor),
572 DEFINT(320,720),
573 },{
574 .desc = "Vertical capture resolution",
575 .name = "resolution_ver",
576 .internal_id = PVR2_CID_VRES,
577 .default_value = 480,
578 DEFREF(res_ver),
579 DEFINT(200,625),
d855497e
MI		 580 },{
581 .v4l_id = V4L2_CID_PVR_SRATE,
582 .desc = "Sample rate",
583 .name = "srate",
584 .default_value = PVR2_CVAL_SRATE_48,
585 DEFREF(srate),
586 DEFENUM(control_values_srate),
587 },{
588 .v4l_id = V4L2_CID_PVR_AUDIOBITRATE,
589 .desc = "Audio Bitrate",
590 .name = "audio_bitrate",
591 .default_value = PVR2_CVAL_AUDIOBITRATE_224,
592 DEFREF(audiobitrate),
593 DEFENUM(control_values_audiobitrate),
594 },{
595 .v4l_id = V4L2_CID_PVR_AUDIOCRC,
596 .desc = "Audio CRC",
597 .name = "audio_crc",
598 .default_value = 1,
599 DEFREF(audiocrc),
600 DEFINT(0,1),
d855497e
MI		 601 },{
602 .v4l_id = V4L2_CID_PVR_AUDIOEMPHASIS,
603 .desc = "Audio Emphasis",
604 .name = "audio_emphasis",
605 .default_value = PVR2_CVAL_AUDIOEMPHASIS_NONE,
606 DEFREF(audioemphasis),
607 DEFENUM(control_values_audioemphasis),
d855497e
MI		 608 },{
609 .v4l_id = V4L2_CID_PVR_VBR,
610 .desc = "Variable video bitrate",
611 .name = "vbr",
612 .default_value = 0,
613 DEFREF(vbr),
614 DEFINT(0,1),
615 },{
616 .v4l_id = V4L2_CID_PVR_VIDEOBITRATE,
617 .desc = "Average video bitrate",
618 .name = "video_average_bitrate",
619 .default_value = 6000000,
620 DEFREF(videobitrate),
621 DEFINT(500000,20000000),
622 },{
623 .v4l_id = V4L2_CID_PVR_VIDEOPEAK,
624 .desc = "Peak video bitrate",
625 .name = "video_peak_bitrate",
626 .default_value = 6000000,
627 DEFREF(videopeak),
628 DEFINT(500000,20000000),
629 },{
c05c0462
MI		 630 .desc = "Interlace mode",
631 .name = "interlace",
632 .internal_id = PVR2_CID_INTERLACE,
633 .default_value = 0,
634 DEFREF(interlace),
635 DEFINT(0,1),
d855497e 636 },{
c05c0462
MI		 637 .desc = "Audio Layer",
638 .name = "audio_layer",
639 .default_value = 2,
640 DEFREF(audiolayer),
641 DEFINT(0,3),
d855497e
MI		 642 },{
643 .desc = "Tuner Frequency (Hz)",
644 .name = "frequency",
645 .internal_id = PVR2_CID_FREQUENCY,
646 .default_value = 175250000L,
647 .set_value = ctrl_freq_set,
648 .get_value = ctrl_freq_get,
649 .is_dirty = ctrl_freq_is_dirty,
650 .clear_dirty = ctrl_freq_clear_dirty,
651 DEFINT(MIN_FREQ,MAX_FREQ),
652 },{
653 .desc = "Channel",
654 .name = "channel",
655 .set_value = ctrl_channel_set,
656 .get_value = ctrl_channel_get,
657 DEFINT(0,FREQTABLE_SIZE),
658 },{
659 .desc = "Channel Program Frequency",
660 .name = "freq_table_value",
661 .set_value = ctrl_channelfreq_set,
662 .get_value = ctrl_channelfreq_get,
663 DEFINT(MIN_FREQ,MAX_FREQ),
664 },{
665 .desc = "Channel Program ID",
666 .name = "freq_table_channel",
667 .set_value = ctrl_channelprog_set,
668 .get_value = ctrl_channelprog_get,
669 DEFINT(0,FREQTABLE_SIZE),
d855497e
MI		 670 },{
671 .desc = "Streaming Enabled",
672 .name = "streaming_enabled",
673 .get_value = ctrl_streamingenabled_get,
674 DEFINT(0,1),
675 },{
676 .desc = "USB Speed",
677 .name = "usb_speed",
678 .get_value = ctrl_hsm_get,
679 DEFENUM(control_values_hsm),
680 },{
681 .desc = "Signal Present",
682 .name = "signal_present",
683 .get_value = ctrl_signal_get,
684 DEFINT(0,1),
685 },{
686 .desc = "Video Standards Available Mask",
687 .name = "video_standard_mask_available",
688 .internal_id = PVR2_CID_STDAVAIL,
689 .skip_init = !0,
690 .get_value = ctrl_stdavail_get,
691 .set_value = ctrl_stdavail_set,
692 .val_to_sym = ctrl_std_val_to_sym,
693 .sym_to_val = ctrl_std_sym_to_val,
694 .type = pvr2_ctl_bitmask,
695 },{
696 .desc = "Video Standards In Use Mask",
697 .name = "video_standard_mask_active",
698 .internal_id = PVR2_CID_STDCUR,
699 .skip_init = !0,
700 .get_value = ctrl_stdcur_get,
701 .set_value = ctrl_stdcur_set,
702 .is_dirty = ctrl_stdcur_is_dirty,
703 .clear_dirty = ctrl_stdcur_clear_dirty,
704 .val_to_sym = ctrl_std_val_to_sym,
705 .sym_to_val = ctrl_std_sym_to_val,
706 .type = pvr2_ctl_bitmask,
707 },{
708 .desc = "Subsystem enabled mask",
709 .name = "debug_subsys_mask",
710 .skip_init = !0,
711 .get_value = ctrl_subsys_get,
712 .set_value = ctrl_subsys_set,
713 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
714 },{
715 .desc = "Subsystem stream mask",
716 .name = "debug_subsys_stream_mask",
717 .skip_init = !0,
718 .get_value = ctrl_subsys_stream_get,
719 .set_value = ctrl_subsys_stream_set,
720 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
721 },{
722 .desc = "Video Standard Name",
723 .name = "video_standard",
724 .internal_id = PVR2_CID_STDENUM,
725 .skip_init = !0,
726 .get_value = ctrl_stdenumcur_get,
727 .set_value = ctrl_stdenumcur_set,
728 .is_dirty = ctrl_stdenumcur_is_dirty,
729 .clear_dirty = ctrl_stdenumcur_clear_dirty,
730 .type = pvr2_ctl_enum,
731 }
732};
733
c05c0462 734#define CTRLDEF_COUNT (sizeof(control_defs)/sizeof(control_defs[0]))
d855497e
MI		 735
736
737const char *pvr2_config_get_name(enum pvr2_config cfg)
738{
739 switch (cfg) {
740 case pvr2_config_empty: return "empty";
741 case pvr2_config_mpeg: return "mpeg";
742 case pvr2_config_vbi: return "vbi";
743 case pvr2_config_radio: return "radio";
744 }
745 return "<unknown>";
746}
747
748
749struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
750{
751 return hdw->usb_dev;
752}
753
754
755unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
756{
757 return hdw->serial_number;
758}
759
760
761struct pvr2_hdw *pvr2_hdw_find(int unit_number)
762{
763 if (unit_number < 0) return 0;
764 if (unit_number >= PVR_NUM) return 0;
765 return unit_pointers[unit_number];
766}
767
768
769int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
770{
771 return hdw->unit_number;
772}
773
774
775/* Attempt to locate one of the given set of files. Messages are logged
776 appropriate to what has been found. The return value will be 0 or
777 greater on success (it will be the index of the file name found) and
778 fw_entry will be filled in. Otherwise a negative error is returned on
779 failure. If the return value is -ENOENT then no viable firmware file
780 could be located. */
781static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
782 const struct firmware **fw_entry,
783 const char *fwtypename,
784 unsigned int fwcount,
785 const char *fwnames[])
786{
787 unsigned int idx;
788 int ret = -EINVAL;
789 for (idx = 0; idx < fwcount; idx++) {
790 ret = request_firmware(fw_entry,
791 fwnames[idx],
792 &hdw->usb_dev->dev);
793 if (!ret) {
794 trace_firmware("Located %s firmware: %s;"
795 " uploading...",
796 fwtypename,
797 fwnames[idx]);
798 return idx;
799 }
800 if (ret == -ENOENT) continue;
801 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
802 "request_firmware fatal error with code=%d",ret);
803 return ret;
804 }
805 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
806 "***WARNING***"
807 " Device %s firmware"
808 " seems to be missing.",
809 fwtypename);
810 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
811 "Did you install the pvrusb2 firmware files"
812 " in their proper location?");
813 if (fwcount == 1) {
814 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
815 "request_firmware unable to locate %s file %s",
816 fwtypename,fwnames[0]);
817 } else {
818 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
819 "request_firmware unable to locate"
820 " one of the following %s files:",
821 fwtypename);
822 for (idx = 0; idx < fwcount; idx++) {
823 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
824 "request_firmware: Failed to find %s",
825 fwnames[idx]);
826 }
827 }
828 return ret;
829}
830
831
832/*
833 * pvr2_upload_firmware1().
834 *
835 * Send the 8051 firmware to the device. After the upload, arrange for
836 * device to re-enumerate.
837 *
838 * NOTE : the pointer to the firmware data given by request_firmware()
839 * is not suitable for an usb transaction.
840 *
841 */
842int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
843{
844 const struct firmware *fw_entry = 0;
845 void *fw_ptr;
846 unsigned int pipe;
847 int ret;
848 u16 address;
849 static const char *fw_files_29xxx[] = {
850 "v4l-pvrusb2-29xxx-01.fw",
851 };
852#ifdef CONFIG_VIDEO_PVRUSB2_24XXX
853 static const char *fw_files_24xxx[] = {
854 "v4l-pvrusb2-24xxx-01.fw",
855 };
856#endif
857 static const struct pvr2_string_table fw_file_defs[] = {
858 [PVR2_HDW_TYPE_29XXX] = {
859 fw_files_29xxx,
860 sizeof(fw_files_29xxx)/sizeof(fw_files_29xxx[0]),
861 },
862#ifdef CONFIG_VIDEO_PVRUSB2_24XXX
863 [PVR2_HDW_TYPE_24XXX] = {
864 fw_files_24xxx,
865 sizeof(fw_files_24xxx)/sizeof(fw_files_24xxx[0]),
866 },
867#endif
868 };
869 hdw->fw1_state = FW1_STATE_FAILED; // default result
870
871 trace_firmware("pvr2_upload_firmware1");
872
873 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
874 fw_file_defs[hdw->hdw_type].cnt,
875 fw_file_defs[hdw->hdw_type].lst);
876 if (ret < 0) {
877 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
878 return ret;
879 }
880
881 usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
882 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
883
884 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
885
886 if (fw_entry->size != 0x2000){
887 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
888 release_firmware(fw_entry);
889 return -ENOMEM;
890 }
891
892 fw_ptr = kmalloc(0x800, GFP_KERNEL);
893 if (fw_ptr == NULL){
894 release_firmware(fw_entry);
895 return -ENOMEM;
896 }
897
898 /* We have to hold the CPU during firmware upload. */
899 pvr2_hdw_cpureset_assert(hdw,1);
900
901 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
902 chunk. */
903
904 ret = 0;
905 for(address = 0; address < fw_entry->size; address += 0x800) {
906 memcpy(fw_ptr, fw_entry->data + address, 0x800);
907 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
908 0, fw_ptr, 0x800, HZ);
909 }
910
911 trace_firmware("Upload done, releasing device's CPU");
912
913 /* Now release the CPU. It will disconnect and reconnect later. */
914 pvr2_hdw_cpureset_assert(hdw,0);
915
916 kfree(fw_ptr);
917 release_firmware(fw_entry);
918
919 trace_firmware("Upload done (%d bytes sent)",ret);
920
921 /* We should have written 8192 bytes */
922 if (ret == 8192) {
923 hdw->fw1_state = FW1_STATE_RELOAD;
924 return 0;
925 }
926
927 return -EIO;
928}
929
930
931/*
932 * pvr2_upload_firmware2()
933 *
934 * This uploads encoder firmware on endpoint 2.
935 *
936 */
937
938int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
939{
940 const struct firmware *fw_entry = 0;
941 void *fw_ptr;
942 unsigned int pipe, fw_len, fw_done;
943 int actual_length;
944 int ret = 0;
945 int fwidx;
946 static const char *fw_files[] = {
947 CX2341X_FIRM_ENC_FILENAME,
948 };
949
950 trace_firmware("pvr2_upload_firmware2");
951
952 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
953 sizeof(fw_files)/sizeof(fw_files[0]),
954 fw_files);
955 if (ret < 0) return ret;
956 fwidx = ret;
957 ret = 0;
958
959 /* First prepare firmware loading */
960 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
961 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
962 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
963 ret |= pvr2_hdw_cmd_deep_reset(hdw);
964 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
965 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
966 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
967 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
968 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
969 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
970 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
971 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
972 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
973 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
974 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
975 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
976 ret |= pvr2_write_u8(hdw, 0x52, 0);
977 ret |= pvr2_write_u16(hdw, 0x0600, 0);
978
979 if (ret) {
980 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
981 "firmware2 upload prep failed, ret=%d",ret);
982 release_firmware(fw_entry);
983 return ret;
984 }
985
986 /* Now send firmware */
987
988 fw_len = fw_entry->size;
989
990 if (fw_len % FIRMWARE_CHUNK_SIZE) {
991 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
992 "size of %s firmware"
993 " must be a multiple of 8192B",
994 fw_files[fwidx]);
995 release_firmware(fw_entry);
996 return -1;
997 }
998
999 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1000 if (fw_ptr == NULL){
1001 release_firmware(fw_entry);
1002 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1003 "failed to allocate memory for firmware2 upload");
1004 return -ENOMEM;
1005 }
1006
1007 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1008
1009 for (fw_done = 0 ; (fw_done < fw_len) && !ret ;
1010 fw_done += FIRMWARE_CHUNK_SIZE ) {
1011 int i;
1012 memcpy(fw_ptr, fw_entry->data + fw_done, FIRMWARE_CHUNK_SIZE);
1013 /* Usbsnoop log shows that we must swap bytes... */
1014 for (i = 0; i < FIRMWARE_CHUNK_SIZE/4 ; i++)
1015 ((u32 *)fw_ptr)[i] = ___swab32(((u32 *)fw_ptr)[i]);
1016
1017 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,
1018 FIRMWARE_CHUNK_SIZE,
1019 &actual_length, HZ);
1020 ret |= (actual_length != FIRMWARE_CHUNK_SIZE);
1021 }
1022
1023 trace_firmware("upload of %s : %i / %i ",
1024 fw_files[fwidx],fw_done,fw_len);
1025
1026 kfree(fw_ptr);
1027 release_firmware(fw_entry);
1028
1029 if (ret) {
1030 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1031 "firmware2 upload transfer failure");
1032 return ret;
1033 }
1034
1035 /* Finish upload */
1036
1037 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1038 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1039 ret |= pvr2_write_u16(hdw, 0x0600, 0);
1040
1041 if (ret) {
1042 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1043 "firmware2 upload post-proc failure");
1044 } else {
1045 hdw->subsys_enabled_mask |= (1<<PVR2_SUBSYS_B_ENC_FIRMWARE);
1046 }
1047 return ret;
1048}
1049
1050
1051#define FIRMWARE_RECOVERY_BITS \
1052 ((1<<PVR2_SUBSYS_B_ENC_CFG) | \
1053 (1<<PVR2_SUBSYS_B_ENC_RUN) | \
1054 (1<<PVR2_SUBSYS_B_ENC_FIRMWARE) | \
1055 (1<<PVR2_SUBSYS_B_USBSTREAM_RUN))
1056
1057/*
1058
1059 This single function is key to pretty much everything. The pvrusb2
1060 device can logically be viewed as a series of subsystems which can be
1061 stopped / started or unconfigured / configured. To get things streaming,
1062 one must configure everything and start everything, but there may be
1063 various reasons over time to deconfigure something or stop something.
1064 This function handles all of this activity. Everything EVERYWHERE that
1065 must affect a subsystem eventually comes here to do the work.
1066
1067 The current state of all subsystems is represented by a single bit mask,
1068 known as subsys_enabled_mask. The bit positions are defined by the
1069 PVR2_SUBSYS_xxxx macros, with one subsystem per bit position. At any
1070 time the set of configured or active subsystems can be queried just by
1071 looking at that mask. To change bits in that mask, this function here
1072 must be called. The "msk" argument indicates which bit positions to
1073 change, and the "val" argument defines the new values for the positions
1074 defined by "msk".
1075
1076 There is a priority ordering of starting / stopping things, and for
1077 multiple requested changes, this function implements that ordering.
1078 (Thus we will act on a request to load encoder firmware before we
1079 configure the encoder.) In addition to priority ordering, there is a
1080 recovery strategy implemented here. If a particular step fails and we
1081 detect that failure, this function will clear the affected subsystem bits
1082 and restart. Thus we have a means for recovering from a dead encoder:
1083 Clear all bits that correspond to subsystems that we need to restart /
1084 reconfigure and start over.
1085
1086*/
1087void pvr2_hdw_subsys_bit_chg_no_lock(struct pvr2_hdw *hdw,
1088 unsigned long msk,unsigned long val)
1089{
1090 unsigned long nmsk;
1091 unsigned long vmsk;
1092 int ret;
1093 unsigned int tryCount = 0;
1094
1095 if (!hdw->flag_ok) return;
1096
1097 msk &= PVR2_SUBSYS_ALL;
1098
1099 for (;;) {
1100 tryCount++;
1101 vmsk = hdw->subsys_enabled_mask & PVR2_SUBSYS_ALL;
1102 nmsk = (vmsk & ~msk) | (val & msk);
1103 if (!(nmsk ^ vmsk)) break;
1104 if (tryCount > 4) {
1105 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1106 "Too many retries when configuring device;"
1107 " giving up");
1108 pvr2_hdw_render_useless(hdw);
1109 break;
1110 }
1111 if (tryCount > 1) {
1112 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1113 "Retrying device reconfiguration");
1114 }
1115 pvr2_trace(PVR2_TRACE_INIT,
1116 "subsys mask changing 0x%lx:0x%lx"
1117 " from 0x%lx to 0x%lx",
1118 msk,val,hdw->subsys_enabled_mask,nmsk);
1119
1120 vmsk = (nmsk ^ hdw->subsys_enabled_mask) &
1121 hdw->subsys_enabled_mask;
1122 if (vmsk) {
1123 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1124 pvr2_trace(PVR2_TRACE_CTL,
1125 "/*---TRACE_CTL----*/"
1126 " pvr2_encoder_stop");
1127 ret = pvr2_encoder_stop(hdw);
1128 if (ret) {
1129 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1130 "Error recovery initiated");
1131 hdw->subsys_enabled_mask &=
1132 ~FIRMWARE_RECOVERY_BITS;
1133 continue;
1134 }
1135 }
1136 if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1137 pvr2_trace(PVR2_TRACE_CTL,
1138 "/*---TRACE_CTL----*/"
1139 " pvr2_hdw_cmd_usbstream(0)");
1140 pvr2_hdw_cmd_usbstream(hdw,0);
1141 }
1142 if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1143 pvr2_trace(PVR2_TRACE_CTL,
1144 "/*---TRACE_CTL----*/"
1145 " decoder disable");
1146 if (hdw->decoder_ctrl) {
1147 hdw->decoder_ctrl->enable(
1148 hdw->decoder_ctrl->ctxt,0);
1149 } else {
1150 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1151 "WARNING:"
1152 " No decoder present");
1153 }
1154 hdw->subsys_enabled_mask &=
1155 ~(1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1156 }
1157 if (vmsk & PVR2_SUBSYS_CFG_ALL) {
1158 hdw->subsys_enabled_mask &=
1159 ~(vmsk & PVR2_SUBSYS_CFG_ALL);
1160 }
1161 }
1162 vmsk = (nmsk ^ hdw->subsys_enabled_mask) & nmsk;
1163 if (vmsk) {
1164 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_FIRMWARE)) {
1165 pvr2_trace(PVR2_TRACE_CTL,
1166 "/*---TRACE_CTL----*/"
1167 " pvr2_upload_firmware2");
1168 ret = pvr2_upload_firmware2(hdw);
1169 if (ret) {
1170 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1171 "Failure uploading encoder"
1172 " firmware");
1173 pvr2_hdw_render_useless(hdw);
1174 break;
1175 }
1176 }
1177 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_CFG)) {
1178 pvr2_trace(PVR2_TRACE_CTL,
1179 "/*---TRACE_CTL----*/"
1180 " pvr2_encoder_configure");
1181 ret = pvr2_encoder_configure(hdw);
1182 if (ret) {
1183 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1184 "Error recovery initiated");
1185 hdw->subsys_enabled_mask &=
1186 ~FIRMWARE_RECOVERY_BITS;
1187 continue;
1188 }
1189 }
1190 if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1191 pvr2_trace(PVR2_TRACE_CTL,
1192 "/*---TRACE_CTL----*/"
1193 " decoder enable");
1194 if (hdw->decoder_ctrl) {
1195 hdw->decoder_ctrl->enable(
1196 hdw->decoder_ctrl->ctxt,!0);
1197 } else {
1198 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1199 "WARNING:"
1200 " No decoder present");
1201 }
1202 hdw->subsys_enabled_mask |=
1203 (1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1204 }
1205 if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1206 pvr2_trace(PVR2_TRACE_CTL,
1207 "/*---TRACE_CTL----*/"
1208 " pvr2_hdw_cmd_usbstream(1)");
1209 pvr2_hdw_cmd_usbstream(hdw,!0);
1210 }
1211 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1212 pvr2_trace(PVR2_TRACE_CTL,
1213 "/*---TRACE_CTL----*/"
1214 " pvr2_encoder_start");
1215 ret = pvr2_encoder_start(hdw);
1216 if (ret) {
1217 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1218 "Error recovery initiated");
1219 hdw->subsys_enabled_mask &=
1220 ~FIRMWARE_RECOVERY_BITS;
1221 continue;
1222 }
1223 }
1224 }
1225 }
1226}
1227
1228
1229void pvr2_hdw_subsys_bit_chg(struct pvr2_hdw *hdw,
1230 unsigned long msk,unsigned long val)
1231{
1232 LOCK_TAKE(hdw->big_lock); do {
1233 pvr2_hdw_subsys_bit_chg_no_lock(hdw,msk,val);
1234 } while (0); LOCK_GIVE(hdw->big_lock);
1235}
1236
1237
1238void pvr2_hdw_subsys_bit_set(struct pvr2_hdw *hdw,unsigned long msk)
1239{
1240 pvr2_hdw_subsys_bit_chg(hdw,msk,msk);
1241}
1242
1243
1244void pvr2_hdw_subsys_bit_clr(struct pvr2_hdw *hdw,unsigned long msk)
1245{
1246 pvr2_hdw_subsys_bit_chg(hdw,msk,0);
1247}
1248
1249
1250unsigned long pvr2_hdw_subsys_get(struct pvr2_hdw *hdw)
1251{
1252 return hdw->subsys_enabled_mask;
1253}
1254
1255
1256unsigned long pvr2_hdw_subsys_stream_get(struct pvr2_hdw *hdw)
1257{
1258 return hdw->subsys_stream_mask;
1259}
1260
1261
1262void pvr2_hdw_subsys_stream_bit_chg_no_lock(struct pvr2_hdw *hdw,
1263 unsigned long msk,
1264 unsigned long val)
1265{
1266 unsigned long val2;
1267 msk &= PVR2_SUBSYS_ALL;
1268 val2 = ((hdw->subsys_stream_mask & ~msk) | (val & msk));
1269 pvr2_trace(PVR2_TRACE_INIT,
1270 "stream mask changing 0x%lx:0x%lx from 0x%lx to 0x%lx",
1271 msk,val,hdw->subsys_stream_mask,val2);
1272 hdw->subsys_stream_mask = val2;
1273}
1274
1275
1276void pvr2_hdw_subsys_stream_bit_chg(struct pvr2_hdw *hdw,
1277 unsigned long msk,
1278 unsigned long val)
1279{
1280 LOCK_TAKE(hdw->big_lock); do {
1281 pvr2_hdw_subsys_stream_bit_chg_no_lock(hdw,msk,val);
1282 } while (0); LOCK_GIVE(hdw->big_lock);
1283}
1284
1285
1286int pvr2_hdw_set_streaming_no_lock(struct pvr2_hdw *hdw,int enableFl)
1287{
1288 if ((!enableFl) == !(hdw->flag_streaming_enabled)) return 0;
1289 if (enableFl) {
1290 pvr2_trace(PVR2_TRACE_START_STOP,
1291 "/*--TRACE_STREAM--*/ enable");
1292 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,~0);
1293 } else {
1294 pvr2_trace(PVR2_TRACE_START_STOP,
1295 "/*--TRACE_STREAM--*/ disable");
1296 pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1297 }
1298 if (!hdw->flag_ok) return -EIO;
1299 hdw->flag_streaming_enabled = enableFl != 0;
1300 return 0;
1301}
1302
1303
1304int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1305{
1306 return hdw->flag_streaming_enabled != 0;
1307}
1308
1309
1310int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1311{
1312 int ret;
1313 LOCK_TAKE(hdw->big_lock); do {
1314 ret = pvr2_hdw_set_streaming_no_lock(hdw,enable_flag);
1315 } while (0); LOCK_GIVE(hdw->big_lock);
1316 return ret;
1317}
1318
1319
1320int pvr2_hdw_set_stream_type_no_lock(struct pvr2_hdw *hdw,
1321 enum pvr2_config config)
1322{
1323 unsigned long sm = hdw->subsys_enabled_mask;
1324 if (!hdw->flag_ok) return -EIO;
1325 pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1326 hdw->config = config;
1327 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,sm);
1328 return 0;
1329}
1330
1331
1332int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1333{
1334 int ret;
1335 if (!hdw->flag_ok) return -EIO;
1336 LOCK_TAKE(hdw->big_lock);
1337 ret = pvr2_hdw_set_stream_type_no_lock(hdw,config);
1338 LOCK_GIVE(hdw->big_lock);
1339 return ret;
1340}
1341
1342
1343static int get_default_tuner_type(struct pvr2_hdw *hdw)
1344{
1345 int unit_number = hdw->unit_number;
1346 int tp = -1;
1347 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1348 tp = tuner[unit_number];
1349 }
1350 if (tp < 0) return -EINVAL;
1351 hdw->tuner_type = tp;
1352 return 0;
1353}
1354
1355
1356static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1357{
1358 int unit_number = hdw->unit_number;
1359 int tp = 0;
1360 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1361 tp = video_std[unit_number];
1362 }
1363 return tp;
1364}
1365
1366
1367static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1368{
1369 int unit_number = hdw->unit_number;
1370 int tp = 0;
1371 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1372 tp = tolerance[unit_number];
1373 }
1374 return tp;
1375}
1376
1377
1378static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1379{
1380 /* Try a harmless request to fetch the eeprom's address over
1381 endpoint 1. See what happens. Only the full FX2 image can
1382 respond to this. If this probe fails then likely the FX2
1383 firmware needs be loaded. */
1384 int result;
1385 LOCK_TAKE(hdw->ctl_lock); do {
1386 hdw->cmd_buffer[0] = 0xeb;
1387 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1388 hdw->cmd_buffer,1,
1389 hdw->cmd_buffer,1);
1390 if (result < 0) break;
1391 } while(0); LOCK_GIVE(hdw->ctl_lock);
1392 if (result) {
1393 pvr2_trace(PVR2_TRACE_INIT,
1394 "Probe of device endpoint 1 result status %d",
1395 result);
1396 } else {
1397 pvr2_trace(PVR2_TRACE_INIT,
1398 "Probe of device endpoint 1 succeeded");
1399 }
1400 return result == 0;
1401}
1402
1403static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1404{
1405 char buf[40];
1406 unsigned int bcnt;
1407 v4l2_std_id std1,std2;
1408
1409 std1 = get_default_standard(hdw);
1410
1411 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1412 pvr2_trace(PVR2_TRACE_INIT,
1413 "Supported video standard(s) reported by eeprom: %.*s",
1414 bcnt,buf);
1415
1416 hdw->std_mask_avail = hdw->std_mask_eeprom;
1417
1418 std2 = std1 & ~hdw->std_mask_avail;
1419 if (std2) {
1420 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1421 pvr2_trace(PVR2_TRACE_INIT,
1422 "Expanding supported video standards"
1423 " to include: %.*s",
1424 bcnt,buf);
1425 hdw->std_mask_avail |= std2;
1426 }
1427
1428 pvr2_hdw_internal_set_std_avail(hdw);
1429
1430 if (std1) {
1431 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1432 pvr2_trace(PVR2_TRACE_INIT,
1433 "Initial video standard forced to %.*s",
1434 bcnt,buf);
1435 hdw->std_mask_cur = std1;
1436 hdw->std_dirty = !0;
1437 pvr2_hdw_internal_find_stdenum(hdw);
1438 return;
1439 }
1440
1441 if (hdw->std_enum_cnt > 1) {
1442 // Autoselect the first listed standard
1443 hdw->std_enum_cur = 1;
1444 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1445 hdw->std_dirty = !0;
1446 pvr2_trace(PVR2_TRACE_INIT,
1447 "Initial video standard auto-selected to %s",
1448 hdw->std_defs[hdw->std_enum_cur-1].name);
1449 return;
1450 }
1451
1452 pvr2_trace(PVR2_TRACE_EEPROM,
1453 "Unable to select a viable initial video standard");
1454}
1455
1456
1457static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1458{
1459 int ret;
1460 unsigned int idx;
1461 struct pvr2_ctrl *cptr;
1462 int reloadFl = 0;
1463 if (!reloadFl) {
1464 reloadFl = (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1465 == 0);
1466 if (reloadFl) {
1467 pvr2_trace(PVR2_TRACE_INIT,
1468 "USB endpoint config looks strange"
1469 "; possibly firmware needs to be loaded");
1470 }
1471 }
1472 if (!reloadFl) {
1473 reloadFl = !pvr2_hdw_check_firmware(hdw);
1474 if (reloadFl) {
1475 pvr2_trace(PVR2_TRACE_INIT,
1476 "Check for FX2 firmware failed"
1477 "; possibly firmware needs to be loaded");
1478 }
1479 }
1480 if (reloadFl) {
1481 if (pvr2_upload_firmware1(hdw) != 0) {
1482 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1483 "Failure uploading firmware1");
1484 }
1485 return;
1486 }
1487 hdw->fw1_state = FW1_STATE_OK;
1488
1489 if (initusbreset) {
1490 pvr2_hdw_device_reset(hdw);
1491 }
1492 if (!pvr2_hdw_dev_ok(hdw)) return;
1493
1494 for (idx = 0; idx < pvr2_client_lists[hdw->hdw_type].cnt; idx++) {
1495 request_module(pvr2_client_lists[hdw->hdw_type].lst[idx]);
1496 }
1497
1498 pvr2_hdw_cmd_powerup(hdw);
1499 if (!pvr2_hdw_dev_ok(hdw)) return;
1500
1501 if (pvr2_upload_firmware2(hdw)){
1502 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"device unstable!!");
1503 pvr2_hdw_render_useless(hdw);
1504 return;
1505 }
1506
1507 // This step MUST happen after the earlier powerup step.
1508 pvr2_i2c_core_init(hdw);
1509 if (!pvr2_hdw_dev_ok(hdw)) return;
1510
c05c0462 1511 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e
MI		 1512 cptr = hdw->controls + idx;
1513 if (cptr->info->skip_init) continue;
1514 if (!cptr->info->set_value) continue;
1515 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1516 }
1517
1518 // Do not use pvr2_reset_ctl_endpoints() here. It is not
1519 // thread-safe against the normal pvr2_send_request() mechanism.
1520 // (We should make it thread safe).
1521
1522 ret = pvr2_hdw_get_eeprom_addr(hdw);
1523 if (!pvr2_hdw_dev_ok(hdw)) return;
1524 if (ret < 0) {
1525 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1526 "Unable to determine location of eeprom, skipping");
1527 } else {
1528 hdw->eeprom_addr = ret;
1529 pvr2_eeprom_analyze(hdw);
1530 if (!pvr2_hdw_dev_ok(hdw)) return;
1531 }
1532
1533 pvr2_hdw_setup_std(hdw);
1534
1535 if (!get_default_tuner_type(hdw)) {
1536 pvr2_trace(PVR2_TRACE_INIT,
1537 "pvr2_hdw_setup: Tuner type overridden to %d",
1538 hdw->tuner_type);
1539 }
1540
1541 hdw->tuner_updated = !0;
1542 pvr2_i2c_core_check_stale(hdw);
1543 hdw->tuner_updated = 0;
1544
1545 if (!pvr2_hdw_dev_ok(hdw)) return;
1546
1547 pvr2_hdw_commit_ctl_internal(hdw);
1548 if (!pvr2_hdw_dev_ok(hdw)) return;
1549
1550 hdw->vid_stream = pvr2_stream_create();
1551 if (!pvr2_hdw_dev_ok(hdw)) return;
1552 pvr2_trace(PVR2_TRACE_INIT,
1553 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1554 if (hdw->vid_stream) {
1555 idx = get_default_error_tolerance(hdw);
1556 if (idx) {
1557 pvr2_trace(PVR2_TRACE_INIT,
1558 "pvr2_hdw_setup: video stream %p"
1559 " setting tolerance %u",
1560 hdw->vid_stream,idx);
1561 }
1562 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1563 PVR2_VID_ENDPOINT,idx);
1564 }
1565
1566 if (!pvr2_hdw_dev_ok(hdw)) return;
1567
1568 /* Make sure everything is up to date */
1569 pvr2_i2c_core_sync(hdw);
1570
1571 if (!pvr2_hdw_dev_ok(hdw)) return;
1572
1573 hdw->flag_init_ok = !0;
1574}
1575
1576
1577int pvr2_hdw_setup(struct pvr2_hdw *hdw)
1578{
1579 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
1580 LOCK_TAKE(hdw->big_lock); do {
1581 pvr2_hdw_setup_low(hdw);
1582 pvr2_trace(PVR2_TRACE_INIT,
1583 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
1584 hdw,hdw->flag_ok,hdw->flag_init_ok);
1585 if (pvr2_hdw_dev_ok(hdw)) {
1586 if (pvr2_hdw_init_ok(hdw)) {
1587 pvr2_trace(
1588 PVR2_TRACE_INFO,
1589 "Device initialization"
1590 " completed successfully.");
1591 break;
1592 }
1593 if (hdw->fw1_state == FW1_STATE_RELOAD) {
1594 pvr2_trace(
1595 PVR2_TRACE_INFO,
1596 "Device microcontroller firmware"
1597 " (re)loaded; it should now reset"
1598 " and reconnect.");
1599 break;
1600 }
1601 pvr2_trace(
1602 PVR2_TRACE_ERROR_LEGS,
1603 "Device initialization was not successful.");
1604 if (hdw->fw1_state == FW1_STATE_MISSING) {
1605 pvr2_trace(
1606 PVR2_TRACE_ERROR_LEGS,
1607 "Giving up since device"
1608 " microcontroller firmware"
1609 " appears to be missing.");
1610 break;
1611 }
1612 }
1613 if (procreload) {
1614 pvr2_trace(
1615 PVR2_TRACE_ERROR_LEGS,
1616 "Attempting pvrusb2 recovery by reloading"
1617 " primary firmware.");
1618 pvr2_trace(
1619 PVR2_TRACE_ERROR_LEGS,
1620 "If this works, device should disconnect"
1621 " and reconnect in a sane state.");
1622 hdw->fw1_state = FW1_STATE_UNKNOWN;
1623 pvr2_upload_firmware1(hdw);
1624 } else {
1625 pvr2_trace(
1626 PVR2_TRACE_ERROR_LEGS,
1627 "***WARNING*** pvrusb2 device hardware"
1628 " appears to be jammed"
1629 " and I can't clear it.");
1630 pvr2_trace(
1631 PVR2_TRACE_ERROR_LEGS,
1632 "You might need to power cycle"
1633 " the pvrusb2 device"
1634 " in order to recover.");
1635 }
1636 } while (0); LOCK_GIVE(hdw->big_lock);
1637 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
1638 return hdw->flag_init_ok;
1639}
1640
1641
1642/* Create and return a structure for interacting with the underlying
1643 hardware */
1644struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1645 const struct usb_device_id *devid)
1646{
1647 unsigned int idx,cnt1,cnt2;
1648 struct pvr2_hdw *hdw;
1649 unsigned int hdw_type;
1650 int valid_std_mask;
1651 struct pvr2_ctrl *cptr;
1652 __u8 ifnum;
1653
1654 hdw_type = devid - pvr2_device_table;
1655 if (hdw_type >=
1656 sizeof(pvr2_device_names)/sizeof(pvr2_device_names[0])) {
1657 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1658 "Bogus device type of %u reported",hdw_type);
1659 return 0;
1660 }
1661
1662 hdw = kmalloc(sizeof(*hdw),GFP_KERNEL);
1663 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
1664 hdw,pvr2_device_names[hdw_type]);
1665 if (!hdw) goto fail;
1666 memset(hdw,0,sizeof(*hdw));
1667
c05c0462
MI		 1668 hdw->control_cnt = CTRLDEF_COUNT;
1669 hdw->controls = kmalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
d855497e
MI		 1670 GFP_KERNEL);
1671 if (!hdw->controls) goto fail;
c05c0462 1672 memset(hdw->controls,0,sizeof(struct pvr2_ctrl) * hdw->control_cnt);
d855497e 1673 hdw->hdw_type = hdw_type;
c05c0462
MI		 1674 for (idx = 0; idx < hdw->control_cnt; idx++) {
1675 cptr = hdw->controls + idx;
1676 cptr->hdw = hdw;
1677 }
d855497e
MI		 1678 for (idx = 0; idx < 32; idx++) {
1679 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
1680 }
c05c0462 1681 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e 1682 cptr = hdw->controls + idx;
d855497e
MI		 1683 cptr->info = control_defs+idx;
1684 }
1685
1686 // Initialize video standard enum dynamic control
1687 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
1688 if (cptr) {
1689 memcpy(&hdw->std_info_enum,cptr->info,
1690 sizeof(hdw->std_info_enum));
1691 cptr->info = &hdw->std_info_enum;
1692
1693 }
1694 // Initialize control data regarding video standard masks
1695 valid_std_mask = pvr2_std_get_usable();
1696 for (idx = 0; idx < 32; idx++) {
1697 if (!(valid_std_mask & (1 << idx))) continue;
1698 cnt1 = pvr2_std_id_to_str(
1699 hdw->std_mask_names[idx],
1700 sizeof(hdw->std_mask_names[idx])-1,
1701 1 << idx);
1702 hdw->std_mask_names[idx][cnt1] = 0;
1703 }
1704 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
1705 if (cptr) {
1706 memcpy(&hdw->std_info_avail,cptr->info,
1707 sizeof(hdw->std_info_avail));
1708 cptr->info = &hdw->std_info_avail;
1709 hdw->std_info_avail.def.type_bitmask.bit_names =
1710 hdw->std_mask_ptrs;
1711 hdw->std_info_avail.def.type_bitmask.valid_bits =
1712 valid_std_mask;
1713 }
1714 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
1715 if (cptr) {
1716 memcpy(&hdw->std_info_cur,cptr->info,
1717 sizeof(hdw->std_info_cur));
1718 cptr->info = &hdw->std_info_cur;
1719 hdw->std_info_cur.def.type_bitmask.bit_names =
1720 hdw->std_mask_ptrs;
1721 hdw->std_info_avail.def.type_bitmask.valid_bits =
1722 valid_std_mask;
1723 }
1724
1725 hdw->eeprom_addr = -1;
1726 hdw->unit_number = -1;
1727 hdw->v4l_minor_number = -1;
1728 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1729 if (!hdw->ctl_write_buffer) goto fail;
1730 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1731 if (!hdw->ctl_read_buffer) goto fail;
1732 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
1733 if (!hdw->ctl_write_urb) goto fail;
1734 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
1735 if (!hdw->ctl_read_urb) goto fail;
1736
1737 down(&pvr2_unit_sem); do {
1738 for (idx = 0; idx < PVR_NUM; idx++) {
1739 if (unit_pointers[idx]) continue;
1740 hdw->unit_number = idx;
1741 unit_pointers[idx] = hdw;
1742 break;
1743 }
1744 } while (0); up(&pvr2_unit_sem);
1745
1746 cnt1 = 0;
1747 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
1748 cnt1 += cnt2;
1749 if (hdw->unit_number >= 0) {
1750 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
1751 ('a' + hdw->unit_number));
1752 cnt1 += cnt2;
1753 }
1754 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
1755 hdw->name[cnt1] = 0;
1756
1757 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
1758 hdw->unit_number,hdw->name);
1759
1760 hdw->tuner_type = -1;
1761 hdw->flag_ok = !0;
1762 /* Initialize the mask of subsystems that we will shut down when we
1763 stop streaming. */
1764 hdw->subsys_stream_mask = PVR2_SUBSYS_RUN_ALL;
1765 hdw->subsys_stream_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
1766
1767 pvr2_trace(PVR2_TRACE_INIT,"subsys_stream_mask: 0x%lx",
1768 hdw->subsys_stream_mask);
1769
1770 hdw->usb_intf = intf;
1771 hdw->usb_dev = interface_to_usbdev(intf);
1772
1773 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
1774 usb_set_interface(hdw->usb_dev,ifnum,0);
1775
1776 mutex_init(&hdw->ctl_lock_mutex);
1777 mutex_init(&hdw->big_lock_mutex);
1778
1779 return hdw;
1780 fail:
1781 if (hdw) {
1782 if (hdw->ctl_read_urb) usb_free_urb(hdw->ctl_read_urb);
1783 if (hdw->ctl_write_urb) usb_free_urb(hdw->ctl_write_urb);
1784 if (hdw->ctl_read_buffer) kfree(hdw->ctl_read_buffer);
1785 if (hdw->ctl_write_buffer) kfree(hdw->ctl_write_buffer);
1786 if (hdw->controls) kfree(hdw->controls);
1787 kfree(hdw);
1788 }
1789 return 0;
1790}
1791
1792
1793/* Remove _all_ associations between this driver and the underlying USB
1794 layer. */
1795void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
1796{
1797 if (hdw->flag_disconnected) return;
1798 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
1799 if (hdw->ctl_read_urb) {
1800 usb_kill_urb(hdw->ctl_read_urb);
1801 usb_free_urb(hdw->ctl_read_urb);
1802 hdw->ctl_read_urb = 0;
1803 }
1804 if (hdw->ctl_write_urb) {
1805 usb_kill_urb(hdw->ctl_write_urb);
1806 usb_free_urb(hdw->ctl_write_urb);
1807 hdw->ctl_write_urb = 0;
1808 }
1809 if (hdw->ctl_read_buffer) {
1810 kfree(hdw->ctl_read_buffer);
1811 hdw->ctl_read_buffer = 0;
1812 }
1813 if (hdw->ctl_write_buffer) {
1814 kfree(hdw->ctl_write_buffer);
1815 hdw->ctl_write_buffer = 0;
1816 }
1817 pvr2_hdw_render_useless_unlocked(hdw);
1818 hdw->flag_disconnected = !0;
1819 hdw->usb_dev = 0;
1820 hdw->usb_intf = 0;
1821}
1822
1823
1824/* Destroy hardware interaction structure */
1825void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
1826{
1827 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
1828 if (hdw->fw_buffer) {
1829 kfree(hdw->fw_buffer);
1830 hdw->fw_buffer = 0;
1831 }
1832 if (hdw->vid_stream) {
1833 pvr2_stream_destroy(hdw->vid_stream);
1834 hdw->vid_stream = 0;
1835 }
1836 if (hdw->audio_stat) {
1837 hdw->audio_stat->detach(hdw->audio_stat->ctxt);
1838 }
1839 if (hdw->decoder_ctrl) {
1840 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
1841 }
1842 pvr2_i2c_core_done(hdw);
1843 pvr2_hdw_remove_usb_stuff(hdw);
1844 down(&pvr2_unit_sem); do {
1845 if ((hdw->unit_number >= 0) &&
1846 (hdw->unit_number < PVR_NUM) &&
1847 (unit_pointers[hdw->unit_number] == hdw)) {
1848 unit_pointers[hdw->unit_number] = 0;
1849 }
1850 } while (0); up(&pvr2_unit_sem);
c05c0462 1851 if (hdw->controls) kfree(hdw->controls);
d855497e
MI		 1852 if (hdw->std_defs) kfree(hdw->std_defs);
1853 if (hdw->std_enum_names) kfree(hdw->std_enum_names);
1854 kfree(hdw);
1855}
1856
1857
1858int pvr2_hdw_init_ok(struct pvr2_hdw *hdw)
1859{
1860 return hdw->flag_init_ok;
1861}
1862
1863
1864int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
1865{
1866 return (hdw && hdw->flag_ok);
1867}
1868
1869
1870/* Called when hardware has been unplugged */
1871void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
1872{
1873 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
1874 LOCK_TAKE(hdw->big_lock);
1875 LOCK_TAKE(hdw->ctl_lock);
1876 pvr2_hdw_remove_usb_stuff(hdw);
1877 LOCK_GIVE(hdw->ctl_lock);
1878 LOCK_GIVE(hdw->big_lock);
1879}
1880
1881
1882// Attempt to autoselect an appropriate value for std_enum_cur given
1883// whatever is currently in std_mask_cur
1884void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
1885{
1886 unsigned int idx;
1887 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
1888 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
1889 hdw->std_enum_cur = idx;
1890 return;
1891 }
1892 }
1893 hdw->std_enum_cur = 0;
1894}
1895
1896
1897// Calculate correct set of enumerated standards based on currently known
1898// set of available standards bits.
1899void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
1900{
1901 struct v4l2_standard *newstd;
1902 unsigned int std_cnt;
1903 unsigned int idx;
1904
1905 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
1906
1907 if (hdw->std_defs) {
1908 kfree(hdw->std_defs);
1909 hdw->std_defs = 0;
1910 }
1911 hdw->std_enum_cnt = 0;
1912 if (hdw->std_enum_names) {
1913 kfree(hdw->std_enum_names);
1914 hdw->std_enum_names = 0;
1915 }
1916
1917 if (!std_cnt) {
1918 pvr2_trace(
1919 PVR2_TRACE_ERROR_LEGS,
1920 "WARNING: Failed to identify any viable standards");
1921 }
1922 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
1923 hdw->std_enum_names[0] = "none";
1924 for (idx = 0; idx < std_cnt; idx++) {
1925 hdw->std_enum_names[idx+1] =
1926 newstd[idx].name;
1927 }
1928 // Set up the dynamic control for this standard
1929 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
1930 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
1931 hdw->std_defs = newstd;
1932 hdw->std_enum_cnt = std_cnt+1;
1933 hdw->std_enum_cur = 0;
1934 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
1935}
1936
1937
1938int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
1939 struct v4l2_standard *std,
1940 unsigned int idx)
1941{
1942 int ret = -EINVAL;
1943 if (!idx) return ret;
1944 LOCK_TAKE(hdw->big_lock); do {
1945 if (idx >= hdw->std_enum_cnt) break;
1946 idx--;
1947 memcpy(std,hdw->std_defs+idx,sizeof(*std));
1948 ret = 0;
1949 } while (0); LOCK_GIVE(hdw->big_lock);
1950 return ret;
1951}
1952
1953
1954/* Get the number of defined controls */
1955unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
1956{
c05c0462 1957 return hdw->control_cnt;
d855497e
MI		 1958}
1959
1960
1961/* Retrieve a control handle given its index (0..count-1) */
1962struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
1963 unsigned int idx)
1964{
c05c0462 1965 if (idx >= hdw->control_cnt) return 0;
d855497e
MI		 1966 return hdw->controls + idx;
1967}
1968
1969
1970/* Retrieve a control handle given its index (0..count-1) */
1971struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
1972 unsigned int ctl_id)
1973{
1974 struct pvr2_ctrl *cptr;
1975 unsigned int idx;
1976 int i;
1977
1978 /* This could be made a lot more efficient, but for now... */
c05c0462 1979 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 1980 cptr = hdw->controls + idx;
1981 i = cptr->info->internal_id;
1982 if (i && (i == ctl_id)) return cptr;
1983 }
1984 return 0;
1985}
1986
1987
1988/* Given an ID, retrieve the control structure associated with it. */
1989struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
1990{
1991 struct pvr2_ctrl *cptr;
1992 unsigned int idx;
1993 int i;
1994
1995 /* This could be made a lot more efficient, but for now... */
c05c0462 1996 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 1997 cptr = hdw->controls + idx;
1998 i = cptr->info->v4l_id;
1999 if (i && (i == ctl_id)) return cptr;
2000 }
2001 return 0;
2002}
2003
2004
2005static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2006{
2007 switch (tp) {
2008 case pvr2_ctl_int: return "integer";
2009 case pvr2_ctl_enum: return "enum";
2010 case pvr2_ctl_bitmask: return "bitmask";
2011 }
2012 return "";
2013}
2014
2015
2016/* Commit all control changes made up to this point. Subsystems can be
2017 indirectly affected by these changes. For a given set of things being
2018 committed, we'll clear the affected subsystem bits and then once we're
2019 done committing everything we'll make a request to restore the subsystem
2020 state(s) back to their previous value before this function was called.
2021 Thus we can automatically reconfigure affected pieces of the driver as
2022 controls are changed. */
2023int pvr2_hdw_commit_ctl_internal(struct pvr2_hdw *hdw)
2024{
2025 unsigned long saved_subsys_mask = hdw->subsys_enabled_mask;
2026 unsigned long stale_subsys_mask = 0;
2027 unsigned int idx;
2028 struct pvr2_ctrl *cptr;
2029 int value;
2030 int commit_flag = 0;
2031 char buf[100];
2032 unsigned int bcnt,ccnt;
2033
c05c0462 2034 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2035 cptr = hdw->controls + idx;
2036 if (cptr->info->is_dirty == 0) continue;
2037 if (!cptr->info->is_dirty(cptr)) continue;
2038 if (!commit_flag) {
2039 commit_flag = !0;
2040 }
2041
2042 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2043 cptr->info->name);
2044 value = 0;
2045 cptr->info->get_value(cptr,&value);
2046 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2047 buf+bcnt,
2048 sizeof(buf)-bcnt,&ccnt);
2049 bcnt += ccnt;
2050 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2051 get_ctrl_typename(cptr->info->type));
2052 pvr2_trace(PVR2_TRACE_CTL,
2053 "/*--TRACE_COMMIT--*/ %.*s",
2054 bcnt,buf);
2055 }
2056
2057 if (!commit_flag) {
2058 /* Nothing has changed */
2059 return 0;
2060 }
2061
2062 /* When video standard changes, reset the hres and vres values -
2063 but if the user has pending changes there, then let the changes
2064 take priority. */
2065 if (hdw->std_dirty) {
2066 /* Rewrite the vertical resolution to be appropriate to the
2067 video standard that has been selected. */
2068 int nvres;
2069 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2070 nvres = 480;
2071 } else {
2072 nvres = 576;
2073 }
2074 if (nvres != hdw->res_ver_val) {
2075 hdw->res_ver_val = nvres;
2076 hdw->res_ver_dirty = !0;
2077 }
2078 if (!hdw->interlace_val) {
2079 hdw->interlace_val = 0;
2080 hdw->interlace_dirty = !0;
2081 }
2082 }
2083
2084 if (hdw->std_dirty ||
d855497e
MI		 2085 hdw->interlace_dirty ||
2086 hdw->vbr_dirty ||
2087 hdw->videobitrate_dirty ||
2088 hdw->videopeak_dirty ||
2089 hdw->audiobitrate_dirty ||
d855497e
MI		 2090 hdw->audiolayer_dirty ||
2091 hdw->audiocrc_dirty ||
c05c0462
MI		 2092 hdw->audioemphasis_dirty ||
2093 hdw->srate_dirty ||
2094 hdw->res_ver_dirty ||
2095 hdw->res_hor_dirty) {
d855497e
MI		 2096 /* If any of this changes, then the encoder needs to be
2097 reconfigured, and we need to reset the stream. */
2098 stale_subsys_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
2099 stale_subsys_mask |= hdw->subsys_stream_mask;
2100 }
2101
c05c0462 2102
d855497e
MI		 2103 /* Scan i2c core at this point - before we clear all the dirty
2104 bits. Various parts of the i2c core will notice dirty bits as
2105 appropriate and arrange to broadcast or directly send updates to
2106 the client drivers in order to keep everything in sync */
2107 pvr2_i2c_core_check_stale(hdw);
2108
c05c0462 2109 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2110 cptr = hdw->controls + idx;
2111 if (!cptr->info->clear_dirty) continue;
2112 cptr->info->clear_dirty(cptr);
2113 }
2114
2115 /* Now execute i2c core update */
2116 pvr2_i2c_core_sync(hdw);
2117
2118 pvr2_hdw_subsys_bit_chg_no_lock(hdw,stale_subsys_mask,0);
2119 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,saved_subsys_mask);
2120
2121 return 0;
2122}
2123
2124
2125int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2126{
2127 LOCK_TAKE(hdw->big_lock); do {
2128 pvr2_hdw_commit_ctl_internal(hdw);
2129 } while (0); LOCK_GIVE(hdw->big_lock);
2130 return 0;
2131}
2132
2133
2134void pvr2_hdw_poll(struct pvr2_hdw *hdw)
2135{
2136 LOCK_TAKE(hdw->big_lock); do {
2137 pvr2_i2c_core_sync(hdw);
2138 } while (0); LOCK_GIVE(hdw->big_lock);
2139}
2140
2141
2142void pvr2_hdw_setup_poll_trigger(struct pvr2_hdw *hdw,
2143 void (*func)(void *),
2144 void *data)
2145{
2146 LOCK_TAKE(hdw->big_lock); do {
2147 hdw->poll_trigger_func = func;
2148 hdw->poll_trigger_data = data;
2149 } while (0); LOCK_GIVE(hdw->big_lock);
2150}
2151
2152
2153void pvr2_hdw_poll_trigger_unlocked(struct pvr2_hdw *hdw)
2154{
2155 if (hdw->poll_trigger_func) {
2156 hdw->poll_trigger_func(hdw->poll_trigger_data);
2157 }
2158}
2159
2160
2161void pvr2_hdw_poll_trigger(struct pvr2_hdw *hdw)
2162{
2163 LOCK_TAKE(hdw->big_lock); do {
2164 pvr2_hdw_poll_trigger_unlocked(hdw);
2165 } while (0); LOCK_GIVE(hdw->big_lock);
2166}
2167
2168
2169/* Return name for this driver instance */
2170const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2171{
2172 return hdw->name;
2173}
2174
2175
2176/* Return bit mask indicating signal status */
2177unsigned int pvr2_hdw_get_signal_status_internal(struct pvr2_hdw *hdw)
2178{
2179 unsigned int msk = 0;
2180 switch (hdw->input_val) {
2181 case PVR2_CVAL_INPUT_TV:
2182 case PVR2_CVAL_INPUT_RADIO:
2183 if (hdw->decoder_ctrl &&
2184 hdw->decoder_ctrl->tuned(hdw->decoder_ctrl->ctxt)) {
2185 msk |= PVR2_SIGNAL_OK;
2186 if (hdw->audio_stat &&
2187 hdw->audio_stat->status(hdw->audio_stat->ctxt)) {
2188 if (hdw->flag_stereo) {
2189 msk |= PVR2_SIGNAL_STEREO;
2190 }
2191 if (hdw->flag_bilingual) {
2192 msk |= PVR2_SIGNAL_SAP;
2193 }
2194 }
2195 }
2196 break;
2197 default:
2198 msk |= PVR2_SIGNAL_OK | PVR2_SIGNAL_STEREO;
2199 }
2200 return msk;
2201}
2202
2203
2204int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2205{
2206 int result;
2207 LOCK_TAKE(hdw->ctl_lock); do {
2208 hdw->cmd_buffer[0] = 0x0b;
2209 result = pvr2_send_request(hdw,
2210 hdw->cmd_buffer,1,
2211 hdw->cmd_buffer,1);
2212 if (result < 0) break;
2213 result = (hdw->cmd_buffer[0] != 0);
2214 } while(0); LOCK_GIVE(hdw->ctl_lock);
2215 return result;
2216}
2217
2218
2219/* Return bit mask indicating signal status */
2220unsigned int pvr2_hdw_get_signal_status(struct pvr2_hdw *hdw)
2221{
2222 unsigned int msk = 0;
2223 LOCK_TAKE(hdw->big_lock); do {
2224 msk = pvr2_hdw_get_signal_status_internal(hdw);
2225 } while (0); LOCK_GIVE(hdw->big_lock);
2226 return msk;
2227}
2228
2229
2230/* Get handle to video output stream */
2231struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2232{
2233 return hp->vid_stream;
2234}
2235
2236
2237void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2238{
4f1a3e5b 2239 int nr = pvr2_hdw_get_unit_number(hdw);
d855497e
MI		 2240 LOCK_TAKE(hdw->big_lock); do {
2241 hdw->log_requested = !0;
4f1a3e5b 2242 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
d855497e
MI		 2243 pvr2_i2c_core_check_stale(hdw);
2244 hdw->log_requested = 0;
2245 pvr2_i2c_core_sync(hdw);
4f1a3e5b 2246 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
d855497e
MI		 2247 } while (0); LOCK_GIVE(hdw->big_lock);
2248}
2249
2250void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw, int enable_flag)
2251{
2252 int ret;
2253 u16 address;
2254 unsigned int pipe;
2255 LOCK_TAKE(hdw->big_lock); do {
2256 if ((hdw->fw_buffer == 0) == !enable_flag) break;
2257
2258 if (!enable_flag) {
2259 pvr2_trace(PVR2_TRACE_FIRMWARE,
2260 "Cleaning up after CPU firmware fetch");
2261 kfree(hdw->fw_buffer);
2262 hdw->fw_buffer = 0;
2263 hdw->fw_size = 0;
2264 /* Now release the CPU. It will disconnect and
2265 reconnect later. */
2266 pvr2_hdw_cpureset_assert(hdw,0);
2267 break;
2268 }
2269
2270 pvr2_trace(PVR2_TRACE_FIRMWARE,
2271 "Preparing to suck out CPU firmware");
2272 hdw->fw_size = 0x2000;
2273 hdw->fw_buffer = kmalloc(hdw->fw_size,GFP_KERNEL);
2274 if (!hdw->fw_buffer) {
2275 hdw->fw_size = 0;
2276 break;
2277 }
2278
2279 memset(hdw->fw_buffer,0,hdw->fw_size);
2280
2281 /* We have to hold the CPU during firmware upload. */
2282 pvr2_hdw_cpureset_assert(hdw,1);
2283
2284 /* download the firmware from address 0000-1fff in 2048
2285 (=0x800) bytes chunk. */
2286
2287 pvr2_trace(PVR2_TRACE_FIRMWARE,"Grabbing CPU firmware");
2288 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2289 for(address = 0; address < hdw->fw_size; address += 0x800) {
2290 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0xc0,
2291 address,0,
2292 hdw->fw_buffer+address,0x800,HZ);
2293 if (ret < 0) break;
2294 }
2295
2296 pvr2_trace(PVR2_TRACE_FIRMWARE,"Done grabbing CPU firmware");
2297
2298 } while (0); LOCK_GIVE(hdw->big_lock);
2299}
2300
2301
2302/* Return true if we're in a mode for retrieval CPU firmware */
2303int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2304{
2305 return hdw->fw_buffer != 0;
2306}
2307
2308
2309int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2310 char *buf,unsigned int cnt)
2311{
2312 int ret = -EINVAL;
2313 LOCK_TAKE(hdw->big_lock); do {
2314 if (!buf) break;
2315 if (!cnt) break;
2316
2317 if (!hdw->fw_buffer) {
2318 ret = -EIO;
2319 break;
2320 }
2321
2322 if (offs >= hdw->fw_size) {
2323 pvr2_trace(PVR2_TRACE_FIRMWARE,
2324 "Read firmware data offs=%d EOF",
2325 offs);
2326 ret = 0;
2327 break;
2328 }
2329
2330 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2331
2332 memcpy(buf,hdw->fw_buffer+offs,cnt);
2333
2334 pvr2_trace(PVR2_TRACE_FIRMWARE,
2335 "Read firmware data offs=%d cnt=%d",
2336 offs,cnt);
2337 ret = cnt;
2338 } while (0); LOCK_GIVE(hdw->big_lock);
2339
2340 return ret;
2341}
2342
2343
2344int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw)
2345{
2346 return hdw->v4l_minor_number;
2347}
2348
2349
2350/* Store the v4l minor device number */
2351void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,int v)
2352{
2353 hdw->v4l_minor_number = v;
2354}
2355
2356
2357void pvr2_reset_ctl_endpoints(struct pvr2_hdw *hdw)
2358{
2359 if (!hdw->usb_dev) return;
2360 usb_settoggle(hdw->usb_dev, PVR2_CTL_WRITE_ENDPOINT & 0xf,
2361 !(PVR2_CTL_WRITE_ENDPOINT & USB_DIR_IN), 0);
2362 usb_settoggle(hdw->usb_dev, PVR2_CTL_READ_ENDPOINT & 0xf,
2363 !(PVR2_CTL_READ_ENDPOINT & USB_DIR_IN), 0);
2364 usb_clear_halt(hdw->usb_dev,
2365 usb_rcvbulkpipe(hdw->usb_dev,
2366 PVR2_CTL_READ_ENDPOINT & 0x7f));
2367 usb_clear_halt(hdw->usb_dev,
2368 usb_sndbulkpipe(hdw->usb_dev,
2369 PVR2_CTL_WRITE_ENDPOINT & 0x7f));
2370}
2371
2372
2373static void pvr2_ctl_write_complete(struct urb *urb, struct pt_regs *regs)
2374{
2375 struct pvr2_hdw *hdw = urb->context;
2376 hdw->ctl_write_pend_flag = 0;
2377 if (hdw->ctl_read_pend_flag) return;
2378 complete(&hdw->ctl_done);
2379}
2380
2381
2382static void pvr2_ctl_read_complete(struct urb *urb, struct pt_regs *regs)
2383{
2384 struct pvr2_hdw *hdw = urb->context;
2385 hdw->ctl_read_pend_flag = 0;
2386 if (hdw->ctl_write_pend_flag) return;
2387 complete(&hdw->ctl_done);
2388}
2389
2390
2391static void pvr2_ctl_timeout(unsigned long data)
2392{
2393 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2394 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2395 hdw->ctl_timeout_flag = !0;
2396 if (hdw->ctl_write_pend_flag && hdw->ctl_write_urb) {
2397 usb_unlink_urb(hdw->ctl_write_urb);
2398 }
2399 if (hdw->ctl_read_pend_flag && hdw->ctl_read_urb) {
2400 usb_unlink_urb(hdw->ctl_read_urb);
2401 }
2402 }
2403}
2404
2405
2406int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2407 unsigned int timeout,int probe_fl,
2408 void *write_data,unsigned int write_len,
2409 void *read_data,unsigned int read_len)
2410{
2411 unsigned int idx;
2412 int status = 0;
2413 struct timer_list timer;
2414 if (!hdw->ctl_lock_held) {
2415 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2416 "Attempted to execute control transfer"
2417 " without lock!!");
2418 return -EDEADLK;
2419 }
2420 if ((!hdw->flag_ok) && !probe_fl) {
2421 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2422 "Attempted to execute control transfer"
2423 " when device not ok");
2424 return -EIO;
2425 }
2426 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2427 if (!probe_fl) {
2428 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2429 "Attempted to execute control transfer"
2430 " when USB is disconnected");
2431 }
2432 return -ENOTTY;
2433 }
2434
2435 /* Ensure that we have sane parameters */
2436 if (!write_data) write_len = 0;
2437 if (!read_data) read_len = 0;
2438 if (write_len > PVR2_CTL_BUFFSIZE) {
2439 pvr2_trace(
2440 PVR2_TRACE_ERROR_LEGS,
2441 "Attempted to execute %d byte"
2442 " control-write transfer (limit=%d)",
2443 write_len,PVR2_CTL_BUFFSIZE);
2444 return -EINVAL;
2445 }
2446 if (read_len > PVR2_CTL_BUFFSIZE) {
2447 pvr2_trace(
2448 PVR2_TRACE_ERROR_LEGS,
2449 "Attempted to execute %d byte"
2450 " control-read transfer (limit=%d)",
2451 write_len,PVR2_CTL_BUFFSIZE);
2452 return -EINVAL;
2453 }
2454 if ((!write_len) && (!read_len)) {
2455 pvr2_trace(
2456 PVR2_TRACE_ERROR_LEGS,
2457 "Attempted to execute null control transfer?");
2458 return -EINVAL;
2459 }
2460
2461
2462 hdw->cmd_debug_state = 1;
2463 if (write_len) {
2464 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
2465 } else {
2466 hdw->cmd_debug_code = 0;
2467 }
2468 hdw->cmd_debug_write_len = write_len;
2469 hdw->cmd_debug_read_len = read_len;
2470
2471 /* Initialize common stuff */
2472 init_completion(&hdw->ctl_done);
2473 hdw->ctl_timeout_flag = 0;
2474 hdw->ctl_write_pend_flag = 0;
2475 hdw->ctl_read_pend_flag = 0;
2476 init_timer(&timer);
2477 timer.expires = jiffies + timeout;
2478 timer.data = (unsigned long)hdw;
2479 timer.function = pvr2_ctl_timeout;
2480
2481 if (write_len) {
2482 hdw->cmd_debug_state = 2;
2483 /* Transfer write data to internal buffer */
2484 for (idx = 0; idx < write_len; idx++) {
2485 hdw->ctl_write_buffer[idx] =
2486 ((unsigned char *)write_data)[idx];
2487 }
2488 /* Initiate a write request */
2489 usb_fill_bulk_urb(hdw->ctl_write_urb,
2490 hdw->usb_dev,
2491 usb_sndbulkpipe(hdw->usb_dev,
2492 PVR2_CTL_WRITE_ENDPOINT),
2493 hdw->ctl_write_buffer,
2494 write_len,
2495 pvr2_ctl_write_complete,
2496 hdw);
2497 hdw->ctl_write_urb->actual_length = 0;
2498 hdw->ctl_write_pend_flag = !0;
2499 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
2500 if (status < 0) {
2501 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2502 "Failed to submit write-control"
2503 " URB status=%d",status);
2504 hdw->ctl_write_pend_flag = 0;
2505 goto done;
2506 }
2507 }
2508
2509 if (read_len) {
2510 hdw->cmd_debug_state = 3;
2511 memset(hdw->ctl_read_buffer,0x43,read_len);
2512 /* Initiate a read request */
2513 usb_fill_bulk_urb(hdw->ctl_read_urb,
2514 hdw->usb_dev,
2515 usb_rcvbulkpipe(hdw->usb_dev,
2516 PVR2_CTL_READ_ENDPOINT),
2517 hdw->ctl_read_buffer,
2518 read_len,
2519 pvr2_ctl_read_complete,
2520 hdw);
2521 hdw->ctl_read_urb->actual_length = 0;
2522 hdw->ctl_read_pend_flag = !0;
2523 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
2524 if (status < 0) {
2525 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2526 "Failed to submit read-control"
2527 " URB status=%d",status);
2528 hdw->ctl_read_pend_flag = 0;
2529 goto done;
2530 }
2531 }
2532
2533 /* Start timer */
2534 add_timer(&timer);
2535
2536 /* Now wait for all I/O to complete */
2537 hdw->cmd_debug_state = 4;
2538 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2539 wait_for_completion(&hdw->ctl_done);
2540 }
2541 hdw->cmd_debug_state = 5;
2542
2543 /* Stop timer */
2544 del_timer_sync(&timer);
2545
2546 hdw->cmd_debug_state = 6;
2547 status = 0;
2548
2549 if (hdw->ctl_timeout_flag) {
2550 status = -ETIMEDOUT;
2551 if (!probe_fl) {
2552 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2553 "Timed out control-write");
2554 }
2555 goto done;
2556 }
2557
2558 if (write_len) {
2559 /* Validate results of write request */
2560 if ((hdw->ctl_write_urb->status != 0) &&
2561 (hdw->ctl_write_urb->status != -ENOENT) &&
2562 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
2563 (hdw->ctl_write_urb->status != -ECONNRESET)) {
2564 /* USB subsystem is reporting some kind of failure
2565 on the write */
2566 status = hdw->ctl_write_urb->status;
2567 if (!probe_fl) {
2568 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2569 "control-write URB failure,"
2570 " status=%d",
2571 status);
2572 }
2573 goto done;
2574 }
2575 if (hdw->ctl_write_urb->actual_length < write_len) {
2576 /* Failed to write enough data */
2577 status = -EIO;
2578 if (!probe_fl) {
2579 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2580 "control-write URB short,"
2581 " expected=%d got=%d",
2582 write_len,
2583 hdw->ctl_write_urb->actual_length);
2584 }
2585 goto done;
2586 }
2587 }
2588 if (read_len) {
2589 /* Validate results of read request */
2590 if ((hdw->ctl_read_urb->status != 0) &&
2591 (hdw->ctl_read_urb->status != -ENOENT) &&
2592 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
2593 (hdw->ctl_read_urb->status != -ECONNRESET)) {
2594 /* USB subsystem is reporting some kind of failure
2595 on the read */
2596 status = hdw->ctl_read_urb->status;
2597 if (!probe_fl) {
2598 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2599 "control-read URB failure,"
2600 " status=%d",
2601 status);
2602 }
2603 goto done;
2604 }
2605 if (hdw->ctl_read_urb->actual_length < read_len) {
2606 /* Failed to read enough data */
2607 status = -EIO;
2608 if (!probe_fl) {
2609 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2610 "control-read URB short,"
2611 " expected=%d got=%d",
2612 read_len,
2613 hdw->ctl_read_urb->actual_length);
2614 }
2615 goto done;
2616 }
2617 /* Transfer retrieved data out from internal buffer */
2618 for (idx = 0; idx < read_len; idx++) {
2619 ((unsigned char *)read_data)[idx] =
2620 hdw->ctl_read_buffer[idx];
2621 }
2622 }
2623
2624 done:
2625
2626 hdw->cmd_debug_state = 0;
2627 if ((status < 0) && (!probe_fl)) {
2628 pvr2_hdw_render_useless_unlocked(hdw);
2629 }
2630 return status;
2631}
2632
2633
2634int pvr2_send_request(struct pvr2_hdw *hdw,
2635 void *write_data,unsigned int write_len,
2636 void *read_data,unsigned int read_len)
2637{
2638 return pvr2_send_request_ex(hdw,HZ*4,0,
2639 write_data,write_len,
2640 read_data,read_len);
2641}
2642
2643int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
2644{
2645 int ret;
2646
2647 LOCK_TAKE(hdw->ctl_lock);
2648
2649 hdw->cmd_buffer[0] = 0x04; /* write register prefix */
2650 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
2651 hdw->cmd_buffer[5] = 0;
2652 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
2653 hdw->cmd_buffer[7] = reg & 0xff;
2654
2655
2656 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
2657
2658 LOCK_GIVE(hdw->ctl_lock);
2659
2660 return ret;
2661}
2662
2663
2664int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
2665{
2666 int ret = 0;
2667
2668 LOCK_TAKE(hdw->ctl_lock);
2669
2670 hdw->cmd_buffer[0] = 0x05; /* read register prefix */
2671 hdw->cmd_buffer[1] = 0;
2672 hdw->cmd_buffer[2] = 0;
2673 hdw->cmd_buffer[3] = 0;
2674 hdw->cmd_buffer[4] = 0;
2675 hdw->cmd_buffer[5] = 0;
2676 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
2677 hdw->cmd_buffer[7] = reg & 0xff;
2678
2679 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
2680 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
2681
2682 LOCK_GIVE(hdw->ctl_lock);
2683
2684 return ret;
2685}
2686
2687
2688int pvr2_write_u16(struct pvr2_hdw *hdw, u16 data, int res)
2689{
2690 int ret;
2691
2692 LOCK_TAKE(hdw->ctl_lock);
2693
2694 hdw->cmd_buffer[0] = (data >> 8) & 0xff;
2695 hdw->cmd_buffer[1] = data & 0xff;
2696
2697 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 2, hdw->cmd_buffer, res);
2698
2699 LOCK_GIVE(hdw->ctl_lock);
2700
2701 return ret;
2702}
2703
2704
2705int pvr2_write_u8(struct pvr2_hdw *hdw, u8 data, int res)
2706{
2707 int ret;
2708
2709 LOCK_TAKE(hdw->ctl_lock);
2710
2711 hdw->cmd_buffer[0] = data;
2712
2713 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 1, hdw->cmd_buffer, res);
2714
2715 LOCK_GIVE(hdw->ctl_lock);
2716
2717 return ret;
2718}
2719
2720
2721void pvr2_hdw_render_useless_unlocked(struct pvr2_hdw *hdw)
2722{
2723 if (!hdw->flag_ok) return;
2724 pvr2_trace(PVR2_TRACE_INIT,"render_useless");
2725 hdw->flag_ok = 0;
2726 if (hdw->vid_stream) {
2727 pvr2_stream_setup(hdw->vid_stream,0,0,0);
2728 }
2729 hdw->flag_streaming_enabled = 0;
2730 hdw->subsys_enabled_mask = 0;
2731}
2732
2733
2734void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
2735{
2736 LOCK_TAKE(hdw->ctl_lock);
2737 pvr2_hdw_render_useless_unlocked(hdw);
2738 LOCK_GIVE(hdw->ctl_lock);
2739}
2740
2741
2742void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
2743{
2744 int ret;
2745 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
2746 ret = usb_lock_device_for_reset(hdw->usb_dev,0);
2747 if (ret == 1) {
2748 ret = usb_reset_device(hdw->usb_dev);
2749 usb_unlock_device(hdw->usb_dev);
2750 } else {
2751 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2752 "Failed to lock USB device ret=%d",ret);
2753 }
2754 if (init_pause_msec) {
2755 pvr2_trace(PVR2_TRACE_INFO,
2756 "Waiting %u msec for hardware to settle",
2757 init_pause_msec);
2758 msleep(init_pause_msec);
2759 }
2760
2761}
2762
2763
2764void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
2765{
2766 char da[1];
2767 unsigned int pipe;
2768 int ret;
2769
2770 if (!hdw->usb_dev) return;
2771
2772 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
2773
2774 da[0] = val ? 0x01 : 0x00;
2775
2776 /* Write the CPUCS register on the 8051. The lsb of the register
2777 is the reset bit; a 1 asserts reset while a 0 clears it. */
2778 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
2779 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
2780 if (ret < 0) {
2781 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2782 "cpureset_assert(%d) error=%d",val,ret);
2783 pvr2_hdw_render_useless(hdw);
2784 }
2785}
2786
2787
2788int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
2789{
2790 int status;
2791 LOCK_TAKE(hdw->ctl_lock); do {
2792 pvr2_trace(PVR2_TRACE_INIT,"Requesting uproc hard reset");
2793 hdw->flag_ok = !0;
2794 hdw->cmd_buffer[0] = 0xdd;
2795 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,0,0);
2796 } while (0); LOCK_GIVE(hdw->ctl_lock);
2797 return status;
2798}
2799
2800
2801int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
2802{
2803 int status;
2804 LOCK_TAKE(hdw->ctl_lock); do {
2805 pvr2_trace(PVR2_TRACE_INIT,"Requesting powerup");
2806 hdw->cmd_buffer[0] = 0xde;
2807 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,0,0);
2808 } while (0); LOCK_GIVE(hdw->ctl_lock);
2809 return status;
2810}
2811
2812
2813int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
2814{
2815 if (!hdw->decoder_ctrl) {
2816 pvr2_trace(PVR2_TRACE_INIT,
2817 "Unable to reset decoder: nothing attached");
2818 return -ENOTTY;
2819 }
2820
2821 if (!hdw->decoder_ctrl->force_reset) {
2822 pvr2_trace(PVR2_TRACE_INIT,
2823 "Unable to reset decoder: not implemented");
2824 return -ENOTTY;
2825 }
2826
2827 pvr2_trace(PVR2_TRACE_INIT,
2828 "Requesting decoder reset");
2829 hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
2830 return 0;
2831}
2832
2833
2834int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
2835{
2836 int status;
2837 LOCK_TAKE(hdw->ctl_lock); do {
2838 hdw->cmd_buffer[0] = (runFl ? 0x36 : 0x37);
2839 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,0,0);
2840 } while (0); LOCK_GIVE(hdw->ctl_lock);
2841 if (!status) {
2842 hdw->subsys_enabled_mask =
2843 ((hdw->subsys_enabled_mask &
2844 ~(1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) |
2845 (runFl ? (1<<PVR2_SUBSYS_B_USBSTREAM_RUN) : 0));
2846 }
2847 return status;
2848}
2849
2850
2851void pvr2_hdw_get_debug_info(const struct pvr2_hdw *hdw,
2852 struct pvr2_hdw_debug_info *ptr)
2853{
2854 ptr->big_lock_held = hdw->big_lock_held;
2855 ptr->ctl_lock_held = hdw->ctl_lock_held;
2856 ptr->flag_ok = hdw->flag_ok;
2857 ptr->flag_disconnected = hdw->flag_disconnected;
2858 ptr->flag_init_ok = hdw->flag_init_ok;
2859 ptr->flag_streaming_enabled = hdw->flag_streaming_enabled;
2860 ptr->subsys_flags = hdw->subsys_enabled_mask;
2861 ptr->cmd_debug_state = hdw->cmd_debug_state;
2862 ptr->cmd_code = hdw->cmd_debug_code;
2863 ptr->cmd_debug_write_len = hdw->cmd_debug_write_len;
2864 ptr->cmd_debug_read_len = hdw->cmd_debug_read_len;
2865 ptr->cmd_debug_timeout = hdw->ctl_timeout_flag;
2866 ptr->cmd_debug_write_pend = hdw->ctl_write_pend_flag;
2867 ptr->cmd_debug_read_pend = hdw->ctl_read_pend_flag;
2868 ptr->cmd_debug_rstatus = hdw->ctl_read_urb->status;
2869 ptr->cmd_debug_wstatus = hdw->ctl_read_urb->status;
2870}
2871
2872
2873int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
2874{
2875 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
2876}
2877
2878
2879int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
2880{
2881 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
2882}
2883
2884
2885int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
2886{
2887 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
2888}
2889
2890
2891int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
2892{
2893 u32 cval,nval;
2894 int ret;
2895 if (~msk) {
2896 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
2897 if (ret) return ret;
2898 nval = (cval & ~msk) | (val & msk);
2899 pvr2_trace(PVR2_TRACE_GPIO,
2900 "GPIO direction changing 0x%x:0x%x"
2901 " from 0x%x to 0x%x",
2902 msk,val,cval,nval);
2903 } else {
2904 nval = val;
2905 pvr2_trace(PVR2_TRACE_GPIO,
2906 "GPIO direction changing to 0x%x",nval);
2907 }
2908 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
2909}
2910
2911
2912int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
2913{
2914 u32 cval,nval;
2915 int ret;
2916 if (~msk) {
2917 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
2918 if (ret) return ret;
2919 nval = (cval & ~msk) | (val & msk);
2920 pvr2_trace(PVR2_TRACE_GPIO,
2921 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
2922 msk,val,cval,nval);
2923 } else {
2924 nval = val;
2925 pvr2_trace(PVR2_TRACE_GPIO,
2926 "GPIO output changing to 0x%x",nval);
2927 }
2928 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
2929}
2930
2931
2932int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
2933{
2934 int result;
2935 LOCK_TAKE(hdw->ctl_lock); do {
2936 hdw->cmd_buffer[0] = 0xeb;
2937 result = pvr2_send_request(hdw,
2938 hdw->cmd_buffer,1,
2939 hdw->cmd_buffer,1);
2940 if (result < 0) break;
2941 result = hdw->cmd_buffer[0];
2942 } while(0); LOCK_GIVE(hdw->ctl_lock);
2943 return result;
2944}
2945
2946
2947/*
2948 Stuff for Emacs to see, in order to encourage consistent editing style:
2949 *** Local Variables: ***
2950 *** mode: c ***
2951 *** fill-column: 75 ***
2952 *** tab-width: 8 ***
2953 *** c-basic-offset: 8 ***
2954 *** End: ***
2955 */
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