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[media] pvrusb2: Implement querystd for videodev_ioctl2
[mirror_ubuntu-artful-kernel.git] / drivers / media / video / pvrusb2 / pvrusb2-hdw.c
CommitLineData
d855497e
MI		 1/*
2 *
d855497e
MI		 3 *
4 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 *
19 */
20
21#include <linux/errno.h>
22#include <linux/string.h>
23#include <linux/slab.h>
7a707b89 24#include <linux/module.h>
d855497e 25#include <linux/firmware.h>
d855497e 26#include <linux/videodev2.h>
32ffa9ae 27#include <media/v4l2-common.h>
75212a02 28#include <media/tuner.h>
d855497e
MI		 29#include "pvrusb2.h"
30#include "pvrusb2-std.h"
31#include "pvrusb2-util.h"
32#include "pvrusb2-hdw.h"
33#include "pvrusb2-i2c-core.h"
d855497e
MI		 34#include "pvrusb2-eeprom.h"
35#include "pvrusb2-hdw-internal.h"
36#include "pvrusb2-encoder.h"
37#include "pvrusb2-debug.h"
8d364363 38#include "pvrusb2-fx2-cmd.h"
5f6dae80 39#include "pvrusb2-wm8775.h"
6f956512 40#include "pvrusb2-video-v4l.h"
634ba268 41#include "pvrusb2-cx2584x-v4l.h"
2a6b627f 42#include "pvrusb2-cs53l32a.h"
76891d65 43#include "pvrusb2-audio.h"
d855497e 44
1bde0289
MI		 45#define TV_MIN_FREQ 55250000L
46#define TV_MAX_FREQ 850000000L
25d8527a 47
83ce57aa
MI		 48/* This defines a minimum interval that the decoder must remain quiet
49 before we are allowed to start it running. */
50#define TIME_MSEC_DECODER_WAIT 50
51
6e931375
MI		 52/* This defines a minimum interval that the decoder must be allowed to run
53 before we can safely begin using its streaming output. */
54#define TIME_MSEC_DECODER_STABILIZATION_WAIT 300
55
83ce57aa 56/* This defines a minimum interval that the encoder must remain quiet
91b5b489
MI		 57 before we are allowed to configure it. */
58#define TIME_MSEC_ENCODER_WAIT 50
83ce57aa
MI		 59
60/* This defines the minimum interval that the encoder must successfully run
61 before we consider that the encoder has run at least once since its
62 firmware has been loaded. This measurement is in important for cases
63 where we can't do something until we know that the encoder has been run
64 at least once. */
65#define TIME_MSEC_ENCODER_OK 250
66
a0fd1cb1 67static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
8df0c87c 68static DEFINE_MUTEX(pvr2_unit_mtx);
d855497e 69
ff699e6b 70static int ctlchg;
ff699e6b 71static int procreload;
d855497e
MI		 72static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
73static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
74static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
ff699e6b 75static int init_pause_msec;
d855497e
MI		 76
77module_param(ctlchg, int, S_IRUGO|S_IWUSR);
78MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
79module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
80MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
d855497e
MI		 81module_param(procreload, int, S_IRUGO|S_IWUSR);
82MODULE_PARM_DESC(procreload,
83 "Attempt init failure recovery with firmware reload");
84module_param_array(tuner, int, NULL, 0444);
85MODULE_PARM_DESC(tuner,"specify installed tuner type");
86module_param_array(video_std, int, NULL, 0444);
87MODULE_PARM_DESC(video_std,"specify initial video standard");
88module_param_array(tolerance, int, NULL, 0444);
89MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
90
6f441ed7
MI		 91/* US Broadcast channel 3 (61.25 MHz), to help with testing */
92static int default_tv_freq = 61250000L;
5a4f5da6
MK		 93/* 104.3 MHz, a usable FM station for my area */
94static int default_radio_freq = 104300000L;
95
96module_param_named(tv_freq, default_tv_freq, int, 0444);
97MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
98module_param_named(radio_freq, default_radio_freq, int, 0444);
99MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
100
d855497e
MI		 101#define PVR2_CTL_WRITE_ENDPOINT 0x01
102#define PVR2_CTL_READ_ENDPOINT 0x81
103
104#define PVR2_GPIO_IN 0x9008
105#define PVR2_GPIO_OUT 0x900c
106#define PVR2_GPIO_DIR 0x9020
107
108#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
109
110#define PVR2_FIRMWARE_ENDPOINT 0x02
111
112/* size of a firmware chunk */
113#define FIRMWARE_CHUNK_SIZE 0x2000
114
edb9dcb8
MI		 115typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
116 struct v4l2_subdev *);
117
118static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
4ecbc28d 119 [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
6f956512 120 [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
76891d65 121 [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
634ba268 122 [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
2a6b627f 123 [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
edb9dcb8
MI		 124};
125
e9c64a78
MI		 126static const char *module_names[] = {
127 [PVR2_CLIENT_ID_MSP3400] = "msp3400",
128 [PVR2_CLIENT_ID_CX25840] = "cx25840",
129 [PVR2_CLIENT_ID_SAA7115] = "saa7115",
130 [PVR2_CLIENT_ID_TUNER] = "tuner",
bb65242a 131 [PVR2_CLIENT_ID_DEMOD] = "tuner",
851981a1 132 [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
5f6dae80 133 [PVR2_CLIENT_ID_WM8775] = "wm8775",
e9c64a78
MI		 134};
135
136
137static const unsigned char *module_i2c_addresses[] = {
138 [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
bb65242a 139 [PVR2_CLIENT_ID_DEMOD] = "\x43",
1dfe6c77
MI		 140 [PVR2_CLIENT_ID_MSP3400] = "\x40",
141 [PVR2_CLIENT_ID_SAA7115] = "\x21",
ae111f76 142 [PVR2_CLIENT_ID_WM8775] = "\x1b",
0b467014 143 [PVR2_CLIENT_ID_CX25840] = "\x44",
23334a22 144 [PVR2_CLIENT_ID_CS53L32A] = "\x11",
e9c64a78
MI		 145};
146
147
27eab384
MI		 148static const char *ir_scheme_names[] = {
149 [PVR2_IR_SCHEME_NONE] = "none",
150 [PVR2_IR_SCHEME_29XXX] = "29xxx",
151 [PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)",
152 [PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)",
153 [PVR2_IR_SCHEME_ZILOG] = "Zilog",
154};
155
156
b30d2441
MI		 157/* Define the list of additional controls we'll dynamically construct based
158 on query of the cx2341x module. */
159struct pvr2_mpeg_ids {
160 const char *strid;
161 int id;
162};
163static const struct pvr2_mpeg_ids mpeg_ids[] = {
164 {
165 .strid = "audio_layer",
166 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
167 },{
168 .strid = "audio_bitrate",
169 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
170 },{
171 /* Already using audio_mode elsewhere :-( */
172 .strid = "mpeg_audio_mode",
173 .id = V4L2_CID_MPEG_AUDIO_MODE,
174 },{
175 .strid = "mpeg_audio_mode_extension",
176 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
177 },{
178 .strid = "audio_emphasis",
179 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
180 },{
181 .strid = "audio_crc",
182 .id = V4L2_CID_MPEG_AUDIO_CRC,
183 },{
184 .strid = "video_aspect",
185 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
186 },{
187 .strid = "video_b_frames",
188 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
189 },{
190 .strid = "video_gop_size",
191 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
192 },{
193 .strid = "video_gop_closure",
194 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
b30d2441
MI		 195 },{
196 .strid = "video_bitrate_mode",
197 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
198 },{
199 .strid = "video_bitrate",
200 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
201 },{
202 .strid = "video_bitrate_peak",
203 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
204 },{
205 .strid = "video_temporal_decimation",
206 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
207 },{
208 .strid = "stream_type",
209 .id = V4L2_CID_MPEG_STREAM_TYPE,
210 },{
211 .strid = "video_spatial_filter_mode",
212 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
213 },{
214 .strid = "video_spatial_filter",
215 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
216 },{
217 .strid = "video_luma_spatial_filter_type",
218 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
219 },{
220 .strid = "video_chroma_spatial_filter_type",
221 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
222 },{
223 .strid = "video_temporal_filter_mode",
224 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
225 },{
226 .strid = "video_temporal_filter",
227 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
228 },{
229 .strid = "video_median_filter_type",
230 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
231 },{
232 .strid = "video_luma_median_filter_top",
233 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
234 },{
235 .strid = "video_luma_median_filter_bottom",
236 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
237 },{
238 .strid = "video_chroma_median_filter_top",
239 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
240 },{
241 .strid = "video_chroma_median_filter_bottom",
242 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
243 }
244};
eca8ebfc 245#define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
c05c0462 246
434449f4 247
d855497e 248static const char *control_values_srate[] = {
434449f4
MI		 249 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
250 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
251 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
d855497e
MI		 252};
253
254
d855497e 255
d855497e
MI		 256static const char *control_values_input[] = {
257 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
29bf5b1d 258 [PVR2_CVAL_INPUT_DTV] = "dtv",
d855497e
MI		 259 [PVR2_CVAL_INPUT_RADIO] = "radio",
260 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
261 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
262};
263
264
265static const char *control_values_audiomode[] = {
266 [V4L2_TUNER_MODE_MONO] = "Mono",
267 [V4L2_TUNER_MODE_STEREO] = "Stereo",
268 [V4L2_TUNER_MODE_LANG1] = "Lang1",
269 [V4L2_TUNER_MODE_LANG2] = "Lang2",
270 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
271};
272
273
274static const char *control_values_hsm[] = {
275 [PVR2_CVAL_HSM_FAIL] = "Fail",
276 [PVR2_CVAL_HSM_HIGH] = "High",
277 [PVR2_CVAL_HSM_FULL] = "Full",
278};
279
280
681c7399
MI		 281static const char *pvr2_state_names[] = {
282 [PVR2_STATE_NONE] = "none",
283 [PVR2_STATE_DEAD] = "dead",
284 [PVR2_STATE_COLD] = "cold",
285 [PVR2_STATE_WARM] = "warm",
286 [PVR2_STATE_ERROR] = "error",
287 [PVR2_STATE_READY] = "ready",
288 [PVR2_STATE_RUN] = "run",
d855497e
MI		 289};
290
681c7399 291
694dca2b 292struct pvr2_fx2cmd_descdef {
1c9d10d4
MI		 293 unsigned char id;
294 unsigned char *desc;
295};
296
694dca2b 297static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
1c9d10d4
MI		 298 {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
299 {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
31335b13 300 {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
1c9d10d4
MI		 301 {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
302 {FX2CMD_REG_WRITE, "write encoder register"},
303 {FX2CMD_REG_READ, "read encoder register"},
304 {FX2CMD_MEMSEL, "encoder memsel"},
305 {FX2CMD_I2C_WRITE, "i2c write"},
306 {FX2CMD_I2C_READ, "i2c read"},
307 {FX2CMD_GET_USB_SPEED, "get USB speed"},
308 {FX2CMD_STREAMING_ON, "stream on"},
309 {FX2CMD_STREAMING_OFF, "stream off"},
310 {FX2CMD_FWPOST1, "fwpost1"},
311 {FX2CMD_POWER_OFF, "power off"},
312 {FX2CMD_POWER_ON, "power on"},
313 {FX2CMD_DEEP_RESET, "deep reset"},
314 {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
315 {FX2CMD_GET_IR_CODE, "get IR code"},
316 {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
317 {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
318 {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
319 {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
320 {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
321 {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
322 {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
323};
324
325
1cb03b76 326static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
681c7399
MI		 327static void pvr2_hdw_state_sched(struct pvr2_hdw *);
328static int pvr2_hdw_state_eval(struct pvr2_hdw *);
1bde0289 329static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
681c7399 330static void pvr2_hdw_worker_poll(struct work_struct *work);
681c7399
MI		 331static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
332static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
333static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
07e337ee 334static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
681c7399 335static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
07e337ee 336static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
07e337ee
AB		 337static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
338static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
681c7399 339static void pvr2_hdw_quiescent_timeout(unsigned long);
6e931375 340static void pvr2_hdw_decoder_stabilization_timeout(unsigned long);
681c7399 341static void pvr2_hdw_encoder_wait_timeout(unsigned long);
d913d630 342static void pvr2_hdw_encoder_run_timeout(unsigned long);
1c9d10d4 343static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
07e337ee
AB		 344static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
345 unsigned int timeout,int probe_fl,
346 void *write_data,unsigned int write_len,
347 void *read_data,unsigned int read_len);
432907f7 348static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
d855497e 349
681c7399
MI		 350
351static void trace_stbit(const char *name,int val)
352{
353 pvr2_trace(PVR2_TRACE_STBITS,
354 "State bit %s <-- %s",
355 name,(val ? "true" : "false"));
356}
357
d855497e
MI		 358static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
359{
360 struct pvr2_hdw *hdw = cptr->hdw;
361 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
362 *vp = hdw->freqTable[hdw->freqProgSlot-1];
363 } else {
364 *vp = 0;
365 }
366 return 0;
367}
368
369static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
370{
371 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 372 unsigned int slotId = hdw->freqProgSlot;
373 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
374 hdw->freqTable[slotId-1] = v;
375 /* Handle side effects correctly - if we're tuned to this
376 slot, then forgot the slot id relation since the stored
377 frequency has been changed. */
378 if (hdw->freqSelector) {
379 if (hdw->freqSlotRadio == slotId) {
380 hdw->freqSlotRadio = 0;
381 }
382 } else {
383 if (hdw->freqSlotTelevision == slotId) {
384 hdw->freqSlotTelevision = 0;
385 }
386 }
d855497e
MI		 387 }
388 return 0;
389}
390
391static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
392{
393 *vp = cptr->hdw->freqProgSlot;
394 return 0;
395}
396
397static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
398{
399 struct pvr2_hdw *hdw = cptr->hdw;
400 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
401 hdw->freqProgSlot = v;
402 }
403 return 0;
404}
405
406static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
407{
1bde0289
MI		 408 struct pvr2_hdw *hdw = cptr->hdw;
409 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
d855497e
MI		 410 return 0;
411}
412
1bde0289 413static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
d855497e
MI		 414{
415 unsigned freq = 0;
416 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 417 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
418 if (slotId > 0) {
419 freq = hdw->freqTable[slotId-1];
420 if (!freq) return 0;
421 pvr2_hdw_set_cur_freq(hdw,freq);
d855497e 422 }
1bde0289
MI		 423 if (hdw->freqSelector) {
424 hdw->freqSlotRadio = slotId;
425 } else {
426 hdw->freqSlotTelevision = slotId;
d855497e
MI		 427 }
428 return 0;
429}
430
431static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
432{
1bde0289 433 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
d855497e
MI		 434 return 0;
435}
436
437static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
438{
439 return cptr->hdw->freqDirty != 0;
440}
441
442static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
443{
444 cptr->hdw->freqDirty = 0;
445}
446
447static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
448{
1bde0289 449 pvr2_hdw_set_cur_freq(cptr->hdw,v);
d855497e
MI		 450 return 0;
451}
452
e784bfb9 453static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
454{
432907f7
MI		 455 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
456 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
457 if (stat != 0) {
432907f7 458 return stat;
e784bfb9 459 }
432907f7 460 *left = cap->bounds.left;
e784bfb9 461 return 0;
462}
463
464static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
465{
432907f7
MI		 466 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
467 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
468 if (stat != 0) {
432907f7
MI		 469 return stat;
470 }
471 *left = cap->bounds.left;
472 if (cap->bounds.width > cptr->hdw->cropw_val) {
432907f7 473 *left += cap->bounds.width - cptr->hdw->cropw_val;
e784bfb9 474 }
475 return 0;
476}
477
478static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
479{
432907f7
MI		 480 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
481 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
482 if (stat != 0) {
432907f7 483 return stat;
e784bfb9 484 }
432907f7 485 *top = cap->bounds.top;
e784bfb9 486 return 0;
487}
488
432907f7 489static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
3ad9fc37 490{
432907f7
MI		 491 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
492 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
493 if (stat != 0) {
432907f7
MI		 494 return stat;
495 }
496 *top = cap->bounds.top;
497 if (cap->bounds.height > cptr->hdw->croph_val) {
432907f7 498 *top += cap->bounds.height - cptr->hdw->croph_val;
3ad9fc37
MI		 499 }
500 return 0;
501}
502
6188a0f1 503static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *width)
432907f7
MI		 504{
505 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
6188a0f1
SV		 506 int stat, bleftend, cleft;
507
508 stat = pvr2_hdw_check_cropcap(cptr->hdw);
432907f7 509 if (stat != 0) {
432907f7
MI		 510 return stat;
511 }
6188a0f1
SV		 512 bleftend = cap->bounds.left+cap->bounds.width;
513 cleft = cptr->hdw->cropl_val;
514
515 *width = cleft < bleftend ? bleftend-cleft : 0;
432907f7
MI		 516 return 0;
517}
518
6188a0f1 519static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *height)
432907f7
MI		 520{
521 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
6188a0f1
SV		 522 int stat, btopend, ctop;
523
524 stat = pvr2_hdw_check_cropcap(cptr->hdw);
432907f7 525 if (stat != 0) {
432907f7
MI		 526 return stat;
527 }
6188a0f1
SV		 528 btopend = cap->bounds.top+cap->bounds.height;
529 ctop = cptr->hdw->cropt_val;
530
531 *height = ctop < btopend ? btopend-ctop : 0;
432907f7
MI		 532 return 0;
533}
534
535static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
536{
537 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
538 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
539 if (stat != 0) {
432907f7
MI		 540 return stat;
541 }
542 *val = cap->bounds.left;
543 return 0;
544}
545
546static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
547{
548 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
549 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
550 if (stat != 0) {
432907f7
MI		 551 return stat;
552 }
553 *val = cap->bounds.top;
554 return 0;
555}
556
557static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
558{
559 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
560 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
561 if (stat != 0) {
432907f7
MI		 562 return stat;
563 }
564 *val = cap->bounds.width;
565 return 0;
566}
567
568static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
569{
570 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
571 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
572 if (stat != 0) {
432907f7
MI		 573 return stat;
574 }
575 *val = cap->bounds.height;
576 return 0;
577}
578
579static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
580{
581 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
582 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
583 if (stat != 0) {
432907f7
MI		 584 return stat;
585 }
586 *val = cap->defrect.left;
587 return 0;
588}
589
590static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
591{
592 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
593 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
594 if (stat != 0) {
432907f7
MI		 595 return stat;
596 }
597 *val = cap->defrect.top;
598 return 0;
599}
600
601static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
602{
603 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
604 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
605 if (stat != 0) {
432907f7
MI		 606 return stat;
607 }
608 *val = cap->defrect.width;
609 return 0;
610}
611
612static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
613{
614 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
615 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
616 if (stat != 0) {
432907f7
MI		 617 return stat;
618 }
619 *val = cap->defrect.height;
620 return 0;
621}
622
623static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
624{
625 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
626 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
627 if (stat != 0) {
432907f7
MI		 628 return stat;
629 }
630 *val = cap->pixelaspect.numerator;
631 return 0;
632}
633
634static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
635{
636 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
637 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
638 if (stat != 0) {
432907f7
MI		 639 return stat;
640 }
641 *val = cap->pixelaspect.denominator;
642 return 0;
643}
644
645static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
e784bfb9 646{
432907f7
MI		 647 /* Actual maximum depends on the video standard in effect. */
648 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
649 *vp = 480;
e784bfb9 650 } else {
432907f7 651 *vp = 576;
e784bfb9 652 }
653 return 0;
654}
655
3ad9fc37
MI		 656static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
657{
989eb154
MI		 658 /* Actual minimum depends on device digitizer type. */
659 if (cptr->hdw->hdw_desc->flag_has_cx25840) {
3ad9fc37
MI		 660 *vp = 75;
661 } else {
662 *vp = 17;
663 }
664 return 0;
665}
666
1bde0289 667static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
5549f54f 668{
1bde0289
MI		 669 *vp = cptr->hdw->input_val;
670 return 0;
671}
672
29bf5b1d
MI		 673static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
674{
1cb03b76 675 return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
29bf5b1d
MI		 676}
677
1bde0289
MI		 678static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
679{
1cb03b76 680 return pvr2_hdw_set_input(cptr->hdw,v);
1bde0289
MI		 681}
682
683static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
684{
685 return cptr->hdw->input_dirty != 0;
686}
687
688static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
689{
690 cptr->hdw->input_dirty = 0;
691}
692
5549f54f 693
25d8527a
PK		 694static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
695{
644afdb9
MI		 696 unsigned long fv;
697 struct pvr2_hdw *hdw = cptr->hdw;
698 if (hdw->tuner_signal_stale) {
a51f5000 699 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 700 }
701 fv = hdw->tuner_signal_info.rangehigh;
702 if (!fv) {
703 /* Safety fallback */
25d8527a 704 *vp = TV_MAX_FREQ;
644afdb9 705 return 0;
25d8527a 706 }
644afdb9
MI		 707 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
708 fv = (fv * 125) / 2;
709 } else {
710 fv = fv * 62500;
711 }
712 *vp = fv;
25d8527a
PK		 713 return 0;
714}
715
716static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
717{
644afdb9
MI		 718 unsigned long fv;
719 struct pvr2_hdw *hdw = cptr->hdw;
720 if (hdw->tuner_signal_stale) {
a51f5000 721 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 722 }
723 fv = hdw->tuner_signal_info.rangelow;
724 if (!fv) {
725 /* Safety fallback */
25d8527a 726 *vp = TV_MIN_FREQ;
644afdb9
MI		 727 return 0;
728 }
729 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
730 fv = (fv * 125) / 2;
731 } else {
732 fv = fv * 62500;
25d8527a 733 }
644afdb9 734 *vp = fv;
25d8527a
PK		 735 return 0;
736}
737
b30d2441
MI		 738static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
739{
740 return cptr->hdw->enc_stale != 0;
741}
742
743static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
744{
745 cptr->hdw->enc_stale = 0;
681c7399 746 cptr->hdw->enc_unsafe_stale = 0;
b30d2441
MI		 747}
748
749static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
750{
751 int ret;
752 struct v4l2_ext_controls cs;
753 struct v4l2_ext_control c1;
754 memset(&cs,0,sizeof(cs));
755 memset(&c1,0,sizeof(c1));
756 cs.controls = &c1;
757 cs.count = 1;
758 c1.id = cptr->info->v4l_id;
01f1e44f 759 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
b30d2441
MI		 760 VIDIOC_G_EXT_CTRLS);
761 if (ret) return ret;
762 *vp = c1.value;
763 return 0;
764}
765
766static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
767{
768 int ret;
681c7399 769 struct pvr2_hdw *hdw = cptr->hdw;
b30d2441
MI		 770 struct v4l2_ext_controls cs;
771 struct v4l2_ext_control c1;
772 memset(&cs,0,sizeof(cs));
773 memset(&c1,0,sizeof(c1));
774 cs.controls = &c1;
775 cs.count = 1;
776 c1.id = cptr->info->v4l_id;
777 c1.value = v;
681c7399
MI		 778 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
779 hdw->state_encoder_run, &cs,
b30d2441 780 VIDIOC_S_EXT_CTRLS);
681c7399
MI		 781 if (ret == -EBUSY) {
782 /* Oops. cx2341x is telling us it's not safe to change
783 this control while we're capturing. Make a note of this
784 fact so that the pipeline will be stopped the next time
785 controls are committed. Then go on ahead and store this
786 change anyway. */
787 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
788 0, &cs,
789 VIDIOC_S_EXT_CTRLS);
790 if (!ret) hdw->enc_unsafe_stale = !0;
791 }
b30d2441 792 if (ret) return ret;
681c7399 793 hdw->enc_stale = !0;
b30d2441
MI		 794 return 0;
795}
796
797static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
798{
799 struct v4l2_queryctrl qctrl;
800 struct pvr2_ctl_info *info;
801 qctrl.id = cptr->info->v4l_id;
802 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
803 /* Strip out the const so we can adjust a function pointer. It's
804 OK to do this here because we know this is a dynamically created
805 control, so the underlying storage for the info pointer is (a)
806 private to us, and (b) not in read-only storage. Either we do
807 this or we significantly complicate the underlying control
808 implementation. */
809 info = (struct pvr2_ctl_info *)(cptr->info);
810 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
811 if (info->set_value) {
a0fd1cb1 812 info->set_value = NULL;
b30d2441
MI		 813 }
814 } else {
815 if (!(info->set_value)) {
816 info->set_value = ctrl_cx2341x_set;
817 }
818 }
819 return qctrl.flags;
820}
821
d855497e
MI		 822static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
823{
681c7399
MI		 824 *vp = cptr->hdw->state_pipeline_req;
825 return 0;
826}
827
828static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
829{
830 *vp = cptr->hdw->master_state;
d855497e
MI		 831 return 0;
832}
833
834static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
835{
836 int result = pvr2_hdw_is_hsm(cptr->hdw);
837 *vp = PVR2_CVAL_HSM_FULL;
838 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
839 if (result) *vp = PVR2_CVAL_HSM_HIGH;
840 return 0;
841}
842
843static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
844{
845 *vp = cptr->hdw->std_mask_avail;
846 return 0;
847}
848
849static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
850{
851 struct pvr2_hdw *hdw = cptr->hdw;
852 v4l2_std_id ns;
853 ns = hdw->std_mask_avail;
854 ns = (ns & ~m) | (v & m);
855 if (ns == hdw->std_mask_avail) return 0;
856 hdw->std_mask_avail = ns;
857 pvr2_hdw_internal_set_std_avail(hdw);
858 pvr2_hdw_internal_find_stdenum(hdw);
859 return 0;
860}
861
862static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
863 char *bufPtr,unsigned int bufSize,
864 unsigned int *len)
865{
866 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
867 return 0;
868}
869
870static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
871 const char *bufPtr,unsigned int bufSize,
872 int *mskp,int *valp)
873{
874 int ret;
875 v4l2_std_id id;
876 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
877 if (ret < 0) return ret;
878 if (mskp) *mskp = id;
879 if (valp) *valp = id;
880 return 0;
881}
882
883static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
884{
885 *vp = cptr->hdw->std_mask_cur;
886 return 0;
887}
888
889static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
890{
891 struct pvr2_hdw *hdw = cptr->hdw;
892 v4l2_std_id ns;
893 ns = hdw->std_mask_cur;
894 ns = (ns & ~m) | (v & m);
895 if (ns == hdw->std_mask_cur) return 0;
896 hdw->std_mask_cur = ns;
897 hdw->std_dirty = !0;
898 pvr2_hdw_internal_find_stdenum(hdw);
899 return 0;
900}
901
902static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
903{
904 return cptr->hdw->std_dirty != 0;
905}
906
907static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
908{
909 cptr->hdw->std_dirty = 0;
910}
911
912static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
913{
18103c57 914 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 915 pvr2_hdw_status_poll(hdw);
18103c57
MI		 916 *vp = hdw->tuner_signal_info.signal;
917 return 0;
918}
919
920static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
921{
922 int val = 0;
923 unsigned int subchan;
924 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 925 pvr2_hdw_status_poll(hdw);
18103c57
MI		 926 subchan = hdw->tuner_signal_info.rxsubchans;
927 if (subchan & V4L2_TUNER_SUB_MONO) {
928 val |= (1 << V4L2_TUNER_MODE_MONO);
929 }
930 if (subchan & V4L2_TUNER_SUB_STEREO) {
931 val |= (1 << V4L2_TUNER_MODE_STEREO);
932 }
933 if (subchan & V4L2_TUNER_SUB_LANG1) {
934 val |= (1 << V4L2_TUNER_MODE_LANG1);
935 }
936 if (subchan & V4L2_TUNER_SUB_LANG2) {
937 val |= (1 << V4L2_TUNER_MODE_LANG2);
938 }
939 *vp = val;
d855497e
MI		 940 return 0;
941}
942
d855497e
MI		 943
944static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
945{
946 struct pvr2_hdw *hdw = cptr->hdw;
947 if (v < 0) return -EINVAL;
948 if (v > hdw->std_enum_cnt) return -EINVAL;
949 hdw->std_enum_cur = v;
950 if (!v) return 0;
951 v--;
952 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
953 hdw->std_mask_cur = hdw->std_defs[v].id;
954 hdw->std_dirty = !0;
955 return 0;
956}
957
958
959static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
960{
961 *vp = cptr->hdw->std_enum_cur;
962 return 0;
963}
964
965
966static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
967{
968 return cptr->hdw->std_dirty != 0;
969}
970
971
972static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
973{
974 cptr->hdw->std_dirty = 0;
975}
976
977
978#define DEFINT(vmin,vmax) \
979 .type = pvr2_ctl_int, \
980 .def.type_int.min_value = vmin, \
981 .def.type_int.max_value = vmax
982
983#define DEFENUM(tab) \
984 .type = pvr2_ctl_enum, \
27c7b710 985 .def.type_enum.count = ARRAY_SIZE(tab), \
d855497e
MI		 986 .def.type_enum.value_names = tab
987
33213963
MI		 988#define DEFBOOL \
989 .type = pvr2_ctl_bool
990
d855497e
MI		 991#define DEFMASK(msk,tab) \
992 .type = pvr2_ctl_bitmask, \
993 .def.type_bitmask.valid_bits = msk, \
994 .def.type_bitmask.bit_names = tab
995
996#define DEFREF(vname) \
997 .set_value = ctrl_set_##vname, \
998 .get_value = ctrl_get_##vname, \
999 .is_dirty = ctrl_isdirty_##vname, \
1000 .clear_dirty = ctrl_cleardirty_##vname
1001
1002
1003#define VCREATE_FUNCS(vname) \
1004static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
1005{*vp = cptr->hdw->vname##_val; return 0;} \
1006static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
1007{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
1008static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
1009{return cptr->hdw->vname##_dirty != 0;} \
1010static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
1011{cptr->hdw->vname##_dirty = 0;}
1012
1013VCREATE_FUNCS(brightness)
1014VCREATE_FUNCS(contrast)
1015VCREATE_FUNCS(saturation)
1016VCREATE_FUNCS(hue)
1017VCREATE_FUNCS(volume)
1018VCREATE_FUNCS(balance)
1019VCREATE_FUNCS(bass)
1020VCREATE_FUNCS(treble)
1021VCREATE_FUNCS(mute)
e784bfb9 1022VCREATE_FUNCS(cropl)
1023VCREATE_FUNCS(cropt)
1024VCREATE_FUNCS(cropw)
1025VCREATE_FUNCS(croph)
c05c0462
MI		 1026VCREATE_FUNCS(audiomode)
1027VCREATE_FUNCS(res_hor)
1028VCREATE_FUNCS(res_ver)
d855497e 1029VCREATE_FUNCS(srate)
d855497e 1030
d855497e
MI		 1031/* Table definition of all controls which can be manipulated */
1032static const struct pvr2_ctl_info control_defs[] = {
1033 {
1034 .v4l_id = V4L2_CID_BRIGHTNESS,
1035 .desc = "Brightness",
1036 .name = "brightness",
1037 .default_value = 128,
1038 DEFREF(brightness),
1039 DEFINT(0,255),
1040 },{
1041 .v4l_id = V4L2_CID_CONTRAST,
1042 .desc = "Contrast",
1043 .name = "contrast",
1044 .default_value = 68,
1045 DEFREF(contrast),
1046 DEFINT(0,127),
1047 },{
1048 .v4l_id = V4L2_CID_SATURATION,
1049 .desc = "Saturation",
1050 .name = "saturation",
1051 .default_value = 64,
1052 DEFREF(saturation),
1053 DEFINT(0,127),
1054 },{
1055 .v4l_id = V4L2_CID_HUE,
1056 .desc = "Hue",
1057 .name = "hue",
1058 .default_value = 0,
1059 DEFREF(hue),
1060 DEFINT(-128,127),
1061 },{
1062 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1063 .desc = "Volume",
1064 .name = "volume",
139eecf9 1065 .default_value = 62000,
d855497e
MI		 1066 DEFREF(volume),
1067 DEFINT(0,65535),
1068 },{
1069 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1070 .desc = "Balance",
1071 .name = "balance",
1072 .default_value = 0,
1073 DEFREF(balance),
1074 DEFINT(-32768,32767),
1075 },{
1076 .v4l_id = V4L2_CID_AUDIO_BASS,
1077 .desc = "Bass",
1078 .name = "bass",
1079 .default_value = 0,
1080 DEFREF(bass),
1081 DEFINT(-32768,32767),
1082 },{
1083 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1084 .desc = "Treble",
1085 .name = "treble",
1086 .default_value = 0,
1087 DEFREF(treble),
1088 DEFINT(-32768,32767),
1089 },{
1090 .v4l_id = V4L2_CID_AUDIO_MUTE,
1091 .desc = "Mute",
1092 .name = "mute",
1093 .default_value = 0,
1094 DEFREF(mute),
33213963 1095 DEFBOOL,
e784bfb9 1096 }, {
432907f7 1097 .desc = "Capture crop left margin",
e784bfb9 1098 .name = "crop_left",
1099 .internal_id = PVR2_CID_CROPL,
1100 .default_value = 0,
1101 DEFREF(cropl),
1102 DEFINT(-129, 340),
1103 .get_min_value = ctrl_cropl_min_get,
1104 .get_max_value = ctrl_cropl_max_get,
432907f7 1105 .get_def_value = ctrl_get_cropcapdl,
e784bfb9 1106 }, {
432907f7 1107 .desc = "Capture crop top margin",
e784bfb9 1108 .name = "crop_top",
1109 .internal_id = PVR2_CID_CROPT,
1110 .default_value = 0,
1111 DEFREF(cropt),
1112 DEFINT(-35, 544),
1113 .get_min_value = ctrl_cropt_min_get,
1114 .get_max_value = ctrl_cropt_max_get,
432907f7 1115 .get_def_value = ctrl_get_cropcapdt,
e784bfb9 1116 }, {
432907f7 1117 .desc = "Capture crop width",
e784bfb9 1118 .name = "crop_width",
1119 .internal_id = PVR2_CID_CROPW,
1120 .default_value = 720,
1121 DEFREF(cropw),
35fa5d4c 1122 DEFINT(0, 864),
432907f7
MI		 1123 .get_max_value = ctrl_cropw_max_get,
1124 .get_def_value = ctrl_get_cropcapdw,
e784bfb9 1125 }, {
432907f7 1126 .desc = "Capture crop height",
e784bfb9 1127 .name = "crop_height",
1128 .internal_id = PVR2_CID_CROPH,
1129 .default_value = 480,
1130 DEFREF(croph),
35fa5d4c 1131 DEFINT(0, 576),
432907f7
MI		 1132 .get_max_value = ctrl_croph_max_get,
1133 .get_def_value = ctrl_get_cropcapdh,
1134 }, {
1135 .desc = "Capture capability pixel aspect numerator",
1136 .name = "cropcap_pixel_numerator",
1137 .internal_id = PVR2_CID_CROPCAPPAN,
1138 .get_value = ctrl_get_cropcappan,
1139 }, {
1140 .desc = "Capture capability pixel aspect denominator",
1141 .name = "cropcap_pixel_denominator",
1142 .internal_id = PVR2_CID_CROPCAPPAD,
1143 .get_value = ctrl_get_cropcappad,
1144 }, {
1145 .desc = "Capture capability bounds top",
1146 .name = "cropcap_bounds_top",
1147 .internal_id = PVR2_CID_CROPCAPBT,
1148 .get_value = ctrl_get_cropcapbt,
1149 }, {
1150 .desc = "Capture capability bounds left",
1151 .name = "cropcap_bounds_left",
1152 .internal_id = PVR2_CID_CROPCAPBL,
1153 .get_value = ctrl_get_cropcapbl,
1154 }, {
1155 .desc = "Capture capability bounds width",
1156 .name = "cropcap_bounds_width",
1157 .internal_id = PVR2_CID_CROPCAPBW,
1158 .get_value = ctrl_get_cropcapbw,
1159 }, {
1160 .desc = "Capture capability bounds height",
1161 .name = "cropcap_bounds_height",
1162 .internal_id = PVR2_CID_CROPCAPBH,
1163 .get_value = ctrl_get_cropcapbh,
c05c0462
MI		 1164 },{
1165 .desc = "Video Source",
1166 .name = "input",
1167 .internal_id = PVR2_CID_INPUT,
1168 .default_value = PVR2_CVAL_INPUT_TV,
29bf5b1d 1169 .check_value = ctrl_check_input,
c05c0462
MI		 1170 DEFREF(input),
1171 DEFENUM(control_values_input),
1172 },{
1173 .desc = "Audio Mode",
1174 .name = "audio_mode",
1175 .internal_id = PVR2_CID_AUDIOMODE,
1176 .default_value = V4L2_TUNER_MODE_STEREO,
1177 DEFREF(audiomode),
1178 DEFENUM(control_values_audiomode),
1179 },{
1180 .desc = "Horizontal capture resolution",
1181 .name = "resolution_hor",
1182 .internal_id = PVR2_CID_HRES,
1183 .default_value = 720,
1184 DEFREF(res_hor),
3ad9fc37 1185 DEFINT(19,720),
c05c0462
MI		 1186 },{
1187 .desc = "Vertical capture resolution",
1188 .name = "resolution_ver",
1189 .internal_id = PVR2_CID_VRES,
1190 .default_value = 480,
1191 DEFREF(res_ver),
3ad9fc37
MI		 1192 DEFINT(17,576),
1193 /* Hook in check for video standard and adjust maximum
1194 depending on the standard. */
1195 .get_max_value = ctrl_vres_max_get,
1196 .get_min_value = ctrl_vres_min_get,
d855497e 1197 },{
b30d2441 1198 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
434449f4
MI		 1199 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1200 .desc = "Audio Sampling Frequency",
d855497e 1201 .name = "srate",
d855497e
MI		 1202 DEFREF(srate),
1203 DEFENUM(control_values_srate),
d855497e
MI		 1204 },{
1205 .desc = "Tuner Frequency (Hz)",
1206 .name = "frequency",
1207 .internal_id = PVR2_CID_FREQUENCY,
1bde0289 1208 .default_value = 0,
d855497e
MI		 1209 .set_value = ctrl_freq_set,
1210 .get_value = ctrl_freq_get,
1211 .is_dirty = ctrl_freq_is_dirty,
1212 .clear_dirty = ctrl_freq_clear_dirty,
644afdb9 1213 DEFINT(0,0),
25d8527a
PK		 1214 /* Hook in check for input value (tv/radio) and adjust
1215 max/min values accordingly */
1216 .get_max_value = ctrl_freq_max_get,
1217 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1218 },{
1219 .desc = "Channel",
1220 .name = "channel",
1221 .set_value = ctrl_channel_set,
1222 .get_value = ctrl_channel_get,
1223 DEFINT(0,FREQTABLE_SIZE),
1224 },{
1225 .desc = "Channel Program Frequency",
1226 .name = "freq_table_value",
1227 .set_value = ctrl_channelfreq_set,
1228 .get_value = ctrl_channelfreq_get,
644afdb9 1229 DEFINT(0,0),
1bde0289
MI		 1230 /* Hook in check for input value (tv/radio) and adjust
1231 max/min values accordingly */
1bde0289
MI		 1232 .get_max_value = ctrl_freq_max_get,
1233 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1234 },{
1235 .desc = "Channel Program ID",
1236 .name = "freq_table_channel",
1237 .set_value = ctrl_channelprog_set,
1238 .get_value = ctrl_channelprog_get,
1239 DEFINT(0,FREQTABLE_SIZE),
d855497e
MI		 1240 },{
1241 .desc = "Streaming Enabled",
1242 .name = "streaming_enabled",
1243 .get_value = ctrl_streamingenabled_get,
33213963 1244 DEFBOOL,
d855497e
MI		 1245 },{
1246 .desc = "USB Speed",
1247 .name = "usb_speed",
1248 .get_value = ctrl_hsm_get,
1249 DEFENUM(control_values_hsm),
681c7399
MI		 1250 },{
1251 .desc = "Master State",
1252 .name = "master_state",
1253 .get_value = ctrl_masterstate_get,
1254 DEFENUM(pvr2_state_names),
d855497e
MI		 1255 },{
1256 .desc = "Signal Present",
1257 .name = "signal_present",
1258 .get_value = ctrl_signal_get,
18103c57
MI		 1259 DEFINT(0,65535),
1260 },{
1261 .desc = "Audio Modes Present",
1262 .name = "audio_modes_present",
1263 .get_value = ctrl_audio_modes_present_get,
1264 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1265 v4l. Nothing outside of this module cares about this,
1266 but I reuse it in order to also reuse the
1267 control_values_audiomode string table. */
1268 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1269 (1 << V4L2_TUNER_MODE_STEREO)|
1270 (1 << V4L2_TUNER_MODE_LANG1)|
1271 (1 << V4L2_TUNER_MODE_LANG2)),
1272 control_values_audiomode),
d855497e
MI		 1273 },{
1274 .desc = "Video Standards Available Mask",
1275 .name = "video_standard_mask_available",
1276 .internal_id = PVR2_CID_STDAVAIL,
1277 .skip_init = !0,
1278 .get_value = ctrl_stdavail_get,
1279 .set_value = ctrl_stdavail_set,
1280 .val_to_sym = ctrl_std_val_to_sym,
1281 .sym_to_val = ctrl_std_sym_to_val,
1282 .type = pvr2_ctl_bitmask,
1283 },{
1284 .desc = "Video Standards In Use Mask",
1285 .name = "video_standard_mask_active",
1286 .internal_id = PVR2_CID_STDCUR,
1287 .skip_init = !0,
1288 .get_value = ctrl_stdcur_get,
1289 .set_value = ctrl_stdcur_set,
1290 .is_dirty = ctrl_stdcur_is_dirty,
1291 .clear_dirty = ctrl_stdcur_clear_dirty,
1292 .val_to_sym = ctrl_std_val_to_sym,
1293 .sym_to_val = ctrl_std_sym_to_val,
1294 .type = pvr2_ctl_bitmask,
d855497e
MI		 1295 },{
1296 .desc = "Video Standard Name",
1297 .name = "video_standard",
1298 .internal_id = PVR2_CID_STDENUM,
1299 .skip_init = !0,
1300 .get_value = ctrl_stdenumcur_get,
1301 .set_value = ctrl_stdenumcur_set,
1302 .is_dirty = ctrl_stdenumcur_is_dirty,
1303 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1304 .type = pvr2_ctl_enum,
1305 }
1306};
1307
eca8ebfc 1308#define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
d855497e
MI		 1309
1310
1311const char *pvr2_config_get_name(enum pvr2_config cfg)
1312{
1313 switch (cfg) {
1314 case pvr2_config_empty: return "empty";
1315 case pvr2_config_mpeg: return "mpeg";
1316 case pvr2_config_vbi: return "vbi";
16eb40d3
MI		 1317 case pvr2_config_pcm: return "pcm";
1318 case pvr2_config_rawvideo: return "raw video";
d855497e
MI		 1319 }
1320 return "<unknown>";
1321}
1322
1323
1324struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1325{
1326 return hdw->usb_dev;
1327}
1328
1329
1330unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1331{
1332 return hdw->serial_number;
1333}
1334
31a18547
MI		 1335
1336const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1337{
1338 return hdw->bus_info;
1339}
1340
1341
13a88797
MI		 1342const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1343{
1344 return hdw->identifier;
1345}
1346
1347
1bde0289
MI		 1348unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1349{
1350 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1351}
1352
1353/* Set the currently tuned frequency and account for all possible
1354 driver-core side effects of this action. */
f55a8712 1355static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1bde0289 1356{
7c74e57e 1357 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1bde0289
MI		 1358 if (hdw->freqSelector) {
1359 /* Swing over to radio frequency selection */
1360 hdw->freqSelector = 0;
1361 hdw->freqDirty = !0;
1362 }
1bde0289
MI		 1363 if (hdw->freqValRadio != val) {
1364 hdw->freqValRadio = val;
1365 hdw->freqSlotRadio = 0;
7c74e57e 1366 hdw->freqDirty = !0;
1bde0289 1367 }
7c74e57e 1368 } else {
1bde0289
MI		 1369 if (!(hdw->freqSelector)) {
1370 /* Swing over to television frequency selection */
1371 hdw->freqSelector = 1;
1372 hdw->freqDirty = !0;
1373 }
1bde0289
MI		 1374 if (hdw->freqValTelevision != val) {
1375 hdw->freqValTelevision = val;
1376 hdw->freqSlotTelevision = 0;
7c74e57e 1377 hdw->freqDirty = !0;
1bde0289 1378 }
1bde0289
MI		 1379 }
1380}
1381
d855497e
MI		 1382int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1383{
1384 return hdw->unit_number;
1385}
1386
1387
1388/* Attempt to locate one of the given set of files. Messages are logged
1389 appropriate to what has been found. The return value will be 0 or
1390 greater on success (it will be the index of the file name found) and
1391 fw_entry will be filled in. Otherwise a negative error is returned on
1392 failure. If the return value is -ENOENT then no viable firmware file
1393 could be located. */
1394static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1395 const struct firmware **fw_entry,
1396 const char *fwtypename,
1397 unsigned int fwcount,
1398 const char *fwnames[])
1399{
1400 unsigned int idx;
1401 int ret = -EINVAL;
1402 for (idx = 0; idx < fwcount; idx++) {
1403 ret = request_firmware(fw_entry,
1404 fwnames[idx],
1405 &hdw->usb_dev->dev);
1406 if (!ret) {
1407 trace_firmware("Located %s firmware: %s;"
1408 " uploading...",
1409 fwtypename,
1410 fwnames[idx]);
1411 return idx;
1412 }
1413 if (ret == -ENOENT) continue;
1414 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1415 "request_firmware fatal error with code=%d",ret);
1416 return ret;
1417 }
1418 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1419 "***WARNING***"
1420 " Device %s firmware"
1421 " seems to be missing.",
1422 fwtypename);
1423 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1424 "Did you install the pvrusb2 firmware files"
1425 " in their proper location?");
1426 if (fwcount == 1) {
1427 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1428 "request_firmware unable to locate %s file %s",
1429 fwtypename,fwnames[0]);
1430 } else {
1431 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1432 "request_firmware unable to locate"
1433 " one of the following %s files:",
1434 fwtypename);
1435 for (idx = 0; idx < fwcount; idx++) {
1436 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1437 "request_firmware: Failed to find %s",
1438 fwnames[idx]);
1439 }
1440 }
1441 return ret;
1442}
1443
1444
1445/*
1446 * pvr2_upload_firmware1().
1447 *
1448 * Send the 8051 firmware to the device. After the upload, arrange for
1449 * device to re-enumerate.
1450 *
1451 * NOTE : the pointer to the firmware data given by request_firmware()
1452 * is not suitable for an usb transaction.
1453 *
1454 */
07e337ee 1455static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
d855497e 1456{
a0fd1cb1 1457 const struct firmware *fw_entry = NULL;
d855497e
MI		 1458 void *fw_ptr;
1459 unsigned int pipe;
9081d901 1460 unsigned int fwsize;
d855497e
MI		 1461 int ret;
1462 u16 address;
1d643a37 1463
989eb154 1464 if (!hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37 1465 hdw->fw1_state = FW1_STATE_OK;
56dcbfa0
MI		 1466 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1467 "Connected device type defines"
1468 " no firmware to upload; ignoring firmware");
1469 return -ENOTTY;
1d643a37
MI		 1470 }
1471
d855497e
MI		 1472 hdw->fw1_state = FW1_STATE_FAILED; // default result
1473
1474 trace_firmware("pvr2_upload_firmware1");
1475
1476 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
989eb154
MI		 1477 hdw->hdw_desc->fx2_firmware.cnt,
1478 hdw->hdw_desc->fx2_firmware.lst);
d855497e
MI		 1479 if (ret < 0) {
1480 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1481 return ret;
1482 }
1483
d855497e
MI		 1484 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1485
1486 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
9081d901 1487 fwsize = fw_entry->size;
d855497e 1488
9081d901
MI		 1489 if ((fwsize != 0x2000) &&
1490 (!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) {
c21c2db4
MI		 1491 if (hdw->hdw_desc->flag_fx2_16kb) {
1492 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1493 "Wrong fx2 firmware size"
1494 " (expected 8192 or 16384, got %u)",
9081d901 1495 fwsize);
c21c2db4
MI		 1496 } else {
1497 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1498 "Wrong fx2 firmware size"
1499 " (expected 8192, got %u)",
9081d901 1500 fwsize);
c21c2db4 1501 }
d855497e
MI		 1502 release_firmware(fw_entry);
1503 return -ENOMEM;
1504 }
1505
1506 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1507 if (fw_ptr == NULL){
1508 release_firmware(fw_entry);
1509 return -ENOMEM;
1510 }
1511
1512 /* We have to hold the CPU during firmware upload. */
1513 pvr2_hdw_cpureset_assert(hdw,1);
1514
1515 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1516 chunk. */
1517
1518 ret = 0;
9081d901 1519 for (address = 0; address < fwsize; address += 0x800) {
d855497e
MI		 1520 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1521 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1522 0, fw_ptr, 0x800, HZ);
1523 }
1524
1525 trace_firmware("Upload done, releasing device's CPU");
1526
1527 /* Now release the CPU. It will disconnect and reconnect later. */
1528 pvr2_hdw_cpureset_assert(hdw,0);
1529
1530 kfree(fw_ptr);
1531 release_firmware(fw_entry);
1532
1533 trace_firmware("Upload done (%d bytes sent)",ret);
1534
75727460
GF		 1535 /* We should have written fwsize bytes */
1536 if (ret == fwsize) {
d855497e
MI		 1537 hdw->fw1_state = FW1_STATE_RELOAD;
1538 return 0;
1539 }
1540
1541 return -EIO;
1542}
1543
1544
1545/*
1546 * pvr2_upload_firmware2()
1547 *
1548 * This uploads encoder firmware on endpoint 2.
1549 *
1550 */
1551
1552int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1553{
a0fd1cb1 1554 const struct firmware *fw_entry = NULL;
d855497e 1555 void *fw_ptr;
90060d32 1556 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
d855497e
MI		 1557 int actual_length;
1558 int ret = 0;
1559 int fwidx;
1560 static const char *fw_files[] = {
1561 CX2341X_FIRM_ENC_FILENAME,
1562 };
1563
989eb154 1564 if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1d643a37
MI		 1565 return 0;
1566 }
1567
d855497e
MI		 1568 trace_firmware("pvr2_upload_firmware2");
1569
1570 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
eca8ebfc 1571 ARRAY_SIZE(fw_files), fw_files);
d855497e
MI		 1572 if (ret < 0) return ret;
1573 fwidx = ret;
1574 ret = 0;
b30d2441
MI		 1575 /* Since we're about to completely reinitialize the encoder,
1576 invalidate our cached copy of its configuration state. Next
1577 time we configure the encoder, then we'll fully configure it. */
1578 hdw->enc_cur_valid = 0;
d855497e 1579
d913d630
MI		 1580 /* Encoder is about to be reset so note that as far as we're
1581 concerned now, the encoder has never been run. */
1582 del_timer_sync(&hdw->encoder_run_timer);
1583 if (hdw->state_encoder_runok) {
1584 hdw->state_encoder_runok = 0;
1585 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1586 }
1587
d855497e
MI		 1588 /* First prepare firmware loading */
1589 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1590 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1591 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1592 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1593 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1594 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1595 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1596 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1597 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1598 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1599 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1600 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1601 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1602 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1603 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1604 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1c9d10d4
MI		 1605 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1606 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1607
1608 if (ret) {
1609 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1610 "firmware2 upload prep failed, ret=%d",ret);
1611 release_firmware(fw_entry);
21684ba9 1612 goto done;
d855497e
MI		 1613 }
1614
1615 /* Now send firmware */
1616
1617 fw_len = fw_entry->size;
1618
90060d32 1619 if (fw_len % sizeof(u32)) {
d855497e
MI		 1620 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1621 "size of %s firmware"
48dc30a1 1622 " must be a multiple of %zu bytes",
90060d32 1623 fw_files[fwidx],sizeof(u32));
d855497e 1624 release_firmware(fw_entry);
21684ba9
MI		 1625 ret = -EINVAL;
1626 goto done;
d855497e
MI		 1627 }
1628
1629 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1630 if (fw_ptr == NULL){
1631 release_firmware(fw_entry);
1632 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1633 "failed to allocate memory for firmware2 upload");
21684ba9
MI		 1634 ret = -ENOMEM;
1635 goto done;
d855497e
MI		 1636 }
1637
1638 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1639
90060d32
MI		 1640 fw_done = 0;
1641 for (fw_done = 0; fw_done < fw_len;) {
1642 bcnt = fw_len - fw_done;
1643 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1644 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1645 /* Usbsnoop log shows that we must swap bytes... */
5f33df14
MI		 1646 /* Some background info: The data being swapped here is a
1647 firmware image destined for the mpeg encoder chip that
1648 lives at the other end of a USB endpoint. The encoder
1649 chip always talks in 32 bit chunks and its storage is
1650 organized into 32 bit words. However from the file
1651 system to the encoder chip everything is purely a byte
1652 stream. The firmware file's contents are always 32 bit
1653 swapped from what the encoder expects. Thus the need
1654 always exists to swap the bytes regardless of the endian
1655 type of the host processor and therefore swab32() makes
1656 the most sense. */
90060d32 1657 for (icnt = 0; icnt < bcnt/4 ; icnt++)
513edce6 1658 ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
90060d32
MI		 1659
1660 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
d855497e 1661 &actual_length, HZ);
90060d32
MI		 1662 ret |= (actual_length != bcnt);
1663 if (ret) break;
1664 fw_done += bcnt;
d855497e
MI		 1665 }
1666
1667 trace_firmware("upload of %s : %i / %i ",
1668 fw_files[fwidx],fw_done,fw_len);
1669
1670 kfree(fw_ptr);
1671 release_firmware(fw_entry);
1672
1673 if (ret) {
1674 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1675 "firmware2 upload transfer failure");
21684ba9 1676 goto done;
d855497e
MI		 1677 }
1678
1679 /* Finish upload */
1680
1681 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1682 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1c9d10d4 1683 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1684
1685 if (ret) {
1686 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1687 "firmware2 upload post-proc failure");
d855497e 1688 }
21684ba9
MI		 1689
1690 done:
1df59f0b
MI		 1691 if (hdw->hdw_desc->signal_routing_scheme ==
1692 PVR2_ROUTING_SCHEME_GOTVIEW) {
1693 /* Ensure that GPIO 11 is set to output for GOTVIEW
1694 hardware. */
1695 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1696 }
d855497e
MI		 1697 return ret;
1698}
1699
1700
681c7399
MI		 1701static const char *pvr2_get_state_name(unsigned int st)
1702{
1703 if (st < ARRAY_SIZE(pvr2_state_names)) {
1704 return pvr2_state_names[st];
d855497e 1705 }
681c7399 1706 return "???";
d855497e
MI		 1707}
1708
681c7399 1709static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
d855497e 1710{
af78e16b
MI		 1711 /* Even though we really only care about the video decoder chip at
1712 this point, we'll broadcast stream on/off to all sub-devices
1713 anyway, just in case somebody else wants to hear the
1714 command... */
e260508d
MI		 1715 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1716 (enablefl ? "on" : "off"));
af78e16b 1717 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
3ccc646b 1718 v4l2_device_call_all(&hdw->v4l2_dev, 0, audio, s_stream, enablefl);
af78e16b
MI		 1719 if (hdw->decoder_client_id) {
1720 /* We get here if the encoder has been noticed. Otherwise
1721 we'll issue a warning to the user (which should
1722 normally never happen). */
1723 return 0;
1724 }
1725 if (!hdw->flag_decoder_missed) {
1726 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1727 "WARNING: No decoder present");
1728 hdw->flag_decoder_missed = !0;
1729 trace_stbit("flag_decoder_missed",
1730 hdw->flag_decoder_missed);
1731 }
1732 return -EIO;
d855497e
MI		 1733}
1734
1735
681c7399 1736int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
d855497e 1737{
681c7399 1738 return hdw->master_state;
d855497e
MI		 1739}
1740
1741
681c7399 1742static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
d855497e 1743{
681c7399
MI		 1744 if (!hdw->flag_tripped) return 0;
1745 hdw->flag_tripped = 0;
1746 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1747 "Clearing driver error statuss");
1748 return !0;
d855497e
MI		 1749}
1750
1751
681c7399 1752int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
d855497e 1753{
681c7399 1754 int fl;
d855497e 1755 LOCK_TAKE(hdw->big_lock); do {
681c7399 1756 fl = pvr2_hdw_untrip_unlocked(hdw);
d855497e 1757 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1758 if (fl) pvr2_hdw_state_sched(hdw);
1759 return 0;
d855497e
MI		 1760}
1761
1762
d855497e
MI		 1763
1764
1765int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1766{
681c7399 1767 return hdw->state_pipeline_req != 0;
d855497e
MI		 1768}
1769
1770
1771int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1772{
681c7399 1773 int ret,st;
d855497e 1774 LOCK_TAKE(hdw->big_lock); do {
681c7399
MI		 1775 pvr2_hdw_untrip_unlocked(hdw);
1776 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1777 hdw->state_pipeline_req = enable_flag != 0;
1778 pvr2_trace(PVR2_TRACE_START_STOP,
1779 "/*--TRACE_STREAM--*/ %s",
1780 enable_flag ? "enable" : "disable");
1781 }
1782 pvr2_hdw_state_sched(hdw);
d855497e 1783 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1784 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1785 if (enable_flag) {
1786 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1787 if (st != PVR2_STATE_READY) return -EIO;
1788 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1789 }
1790 }
d855497e
MI		 1791 return 0;
1792}
1793
1794
1795int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1796{
681c7399 1797 int fl;
d855497e 1798 LOCK_TAKE(hdw->big_lock);
681c7399
MI		 1799 if ((fl = (hdw->desired_stream_type != config)) != 0) {
1800 hdw->desired_stream_type = config;
1801 hdw->state_pipeline_config = 0;
1802 trace_stbit("state_pipeline_config",
1803 hdw->state_pipeline_config);
1804 pvr2_hdw_state_sched(hdw);
1805 }
d855497e 1806 LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1807 if (fl) return 0;
1808 return pvr2_hdw_wait(hdw,0);
d855497e
MI		 1809}
1810
1811
1812static int get_default_tuner_type(struct pvr2_hdw *hdw)
1813{
1814 int unit_number = hdw->unit_number;
1815 int tp = -1;
1816 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1817 tp = tuner[unit_number];
1818 }
1819 if (tp < 0) return -EINVAL;
1820 hdw->tuner_type = tp;
aaf7884d 1821 hdw->tuner_updated = !0;
d855497e
MI		 1822 return 0;
1823}
1824
1825
1826static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1827{
1828 int unit_number = hdw->unit_number;
1829 int tp = 0;
1830 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1831 tp = video_std[unit_number];
6a540254 1832 if (tp) return tp;
d855497e 1833 }
6a540254 1834 return 0;
d855497e
MI		 1835}
1836
1837
1838static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1839{
1840 int unit_number = hdw->unit_number;
1841 int tp = 0;
1842 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1843 tp = tolerance[unit_number];
1844 }
1845 return tp;
1846}
1847
1848
1849static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1850{
1851 /* Try a harmless request to fetch the eeprom's address over
1852 endpoint 1. See what happens. Only the full FX2 image can
1853 respond to this. If this probe fails then likely the FX2
1854 firmware needs be loaded. */
1855 int result;
1856 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 1857 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 1858 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1859 hdw->cmd_buffer,1,
1860 hdw->cmd_buffer,1);
1861 if (result < 0) break;
1862 } while(0); LOCK_GIVE(hdw->ctl_lock);
1863 if (result) {
1864 pvr2_trace(PVR2_TRACE_INIT,
1865 "Probe of device endpoint 1 result status %d",
1866 result);
1867 } else {
1868 pvr2_trace(PVR2_TRACE_INIT,
1869 "Probe of device endpoint 1 succeeded");
1870 }
1871 return result == 0;
1872}
1873
9f66d4ea
MI		 1874struct pvr2_std_hack {
1875 v4l2_std_id pat; /* Pattern to match */
1876 v4l2_std_id msk; /* Which bits we care about */
1877 v4l2_std_id std; /* What additional standards or default to set */
1878};
1879
1880/* This data structure labels specific combinations of standards from
1881 tveeprom that we'll try to recognize. If we recognize one, then assume
1882 a specified default standard to use. This is here because tveeprom only
1883 tells us about available standards not the intended default standard (if
1884 any) for the device in question. We guess the default based on what has
1885 been reported as available. Note that this is only for guessing a
1886 default - which can always be overridden explicitly - and if the user
1887 has otherwise named a default then that default will always be used in
1888 place of this table. */
ebff0330 1889static const struct pvr2_std_hack std_eeprom_maps[] = {
9f66d4ea
MI		 1890 { /* PAL(B/G) */
1891 .pat = V4L2_STD_B|V4L2_STD_GH,
1892 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1893 },
1894 { /* NTSC(M) */
1895 .pat = V4L2_STD_MN,
1896 .std = V4L2_STD_NTSC_M,
1897 },
1898 { /* PAL(I) */
1899 .pat = V4L2_STD_PAL_I,
1900 .std = V4L2_STD_PAL_I,
1901 },
1902 { /* SECAM(L/L') */
1903 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1904 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1905 },
1906 { /* PAL(D/D1/K) */
1907 .pat = V4L2_STD_DK,
ea2562d9 1908 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
9f66d4ea
MI		 1909 },
1910};
1911
d855497e
MI		 1912static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1913{
1914 char buf[40];
1915 unsigned int bcnt;
3d290bdb 1916 v4l2_std_id std1,std2,std3;
d855497e
MI		 1917
1918 std1 = get_default_standard(hdw);
3d290bdb 1919 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
d855497e
MI		 1920
1921 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
56585386 1922 pvr2_trace(PVR2_TRACE_STD,
56dcbfa0
MI		 1923 "Supported video standard(s) reported available"
1924 " in hardware: %.*s",
d855497e
MI		 1925 bcnt,buf);
1926
1927 hdw->std_mask_avail = hdw->std_mask_eeprom;
1928
3d290bdb 1929 std2 = (std1|std3) & ~hdw->std_mask_avail;
d855497e
MI		 1930 if (std2) {
1931 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
56585386 1932 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1933 "Expanding supported video standards"
1934 " to include: %.*s",
1935 bcnt,buf);
1936 hdw->std_mask_avail |= std2;
1937 }
1938
1939 pvr2_hdw_internal_set_std_avail(hdw);
1940
1941 if (std1) {
1942 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
56585386 1943 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1944 "Initial video standard forced to %.*s",
1945 bcnt,buf);
1946 hdw->std_mask_cur = std1;
1947 hdw->std_dirty = !0;
1948 pvr2_hdw_internal_find_stdenum(hdw);
1949 return;
1950 }
3d290bdb
MI		 1951 if (std3) {
1952 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1953 pvr2_trace(PVR2_TRACE_STD,
1954 "Initial video standard"
1955 " (determined by device type): %.*s",bcnt,buf);
1956 hdw->std_mask_cur = std3;
1957 hdw->std_dirty = !0;
1958 pvr2_hdw_internal_find_stdenum(hdw);
1959 return;
1960 }
d855497e 1961
9f66d4ea
MI		 1962 {
1963 unsigned int idx;
1964 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1965 if (std_eeprom_maps[idx].msk ?
1966 ((std_eeprom_maps[idx].pat ^
1967 hdw->std_mask_eeprom) &
1968 std_eeprom_maps[idx].msk) :
1969 (std_eeprom_maps[idx].pat !=
1970 hdw->std_mask_eeprom)) continue;
1971 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1972 std_eeprom_maps[idx].std);
56585386 1973 pvr2_trace(PVR2_TRACE_STD,
9f66d4ea
MI		 1974 "Initial video standard guessed as %.*s",
1975 bcnt,buf);
1976 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1977 hdw->std_dirty = !0;
1978 pvr2_hdw_internal_find_stdenum(hdw);
1979 return;
1980 }
1981 }
1982
d855497e
MI		 1983 if (hdw->std_enum_cnt > 1) {
1984 // Autoselect the first listed standard
1985 hdw->std_enum_cur = 1;
1986 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1987 hdw->std_dirty = !0;
56585386 1988 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1989 "Initial video standard auto-selected to %s",
1990 hdw->std_defs[hdw->std_enum_cur-1].name);
1991 return;
1992 }
1993
0885ba1d 1994 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
d855497e
MI		 1995 "Unable to select a viable initial video standard");
1996}
1997
1998
e9c64a78
MI		 1999static unsigned int pvr2_copy_i2c_addr_list(
2000 unsigned short *dst, const unsigned char *src,
2001 unsigned int dst_max)
2002{
3ab8d295 2003 unsigned int cnt = 0;
e9c64a78
MI		 2004 if (!src) return 0;
2005 while (src[cnt] && (cnt + 1) < dst_max) {
2006 dst[cnt] = src[cnt];
2007 cnt++;
2008 }
2009 dst[cnt] = I2C_CLIENT_END;
2010 return cnt;
2011}
2012
2013
e17d787c
MI		 2014static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw)
2015{
2016 /*
2017 Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness
2018 for cx25840 causes that module to correctly set up its video
2019 scaling. This is really a problem in the cx25840 module itself,
2020 but we work around it here. The problem has not been seen in
2021 ivtv because there VBI is supported and set up. We don't do VBI
2022 here (at least not yet) and thus we never attempted to even set
2023 it up.
2024 */
2025 struct v4l2_format fmt;
2026 if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) {
2027 /* We're not using a cx25840 so don't enable the hack */
2028 return;
2029 }
2030
2031 pvr2_trace(PVR2_TRACE_INIT,
2032 "Module ID %u:"
2033 " Executing cx25840 VBI hack",
2034 hdw->decoder_client_id);
2035 memset(&fmt, 0, sizeof(fmt));
2036 fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
058caa87
MI		 2037 fmt.fmt.sliced.service_lines[0][21] = V4L2_SLICED_CAPTION_525;
2038 fmt.fmt.sliced.service_lines[1][21] = V4L2_SLICED_CAPTION_525;
e17d787c 2039 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
09419af3 2040 vbi, s_sliced_fmt, &fmt.fmt.sliced);
e17d787c
MI		 2041}
2042
2043
1ab5e74f
MI		 2044static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
2045 const struct pvr2_device_client_desc *cd)
e9c64a78
MI		 2046{
2047 const char *fname;
2048 unsigned char mid;
2049 struct v4l2_subdev *sd;
2050 unsigned int i2ccnt;
2051 const unsigned char *p;
2052 /* Arbitrary count - max # i2c addresses we will probe */
2053 unsigned short i2caddr[25];
2054
2055 mid = cd->module_id;
2056 fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
2057 if (!fname) {
2058 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
27108147
MI		 2059 "Module ID %u for device %s has no name?"
2060 " The driver might have a configuration problem.",
e9c64a78
MI		 2061 mid,
2062 hdw->hdw_desc->description);
1ab5e74f 2063 return -EINVAL;
e9c64a78 2064 }
bd14d4f8
MI		 2065 pvr2_trace(PVR2_TRACE_INIT,
2066 "Module ID %u (%s) for device %s being loaded...",
2067 mid, fname,
2068 hdw->hdw_desc->description);
e9c64a78
MI		 2069
2070 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2071 ARRAY_SIZE(i2caddr));
2072 if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2073 module_i2c_addresses[mid] : NULL) != NULL)) {
2074 /* Second chance: Try default i2c address list */
2075 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2076 ARRAY_SIZE(i2caddr));
bd14d4f8
MI		 2077 if (i2ccnt) {
2078 pvr2_trace(PVR2_TRACE_INIT,
2079 "Module ID %u:"
2080 " Using default i2c address list",
2081 mid);
2082 }
e9c64a78
MI		 2083 }
2084
2085 if (!i2ccnt) {
2086 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1ab5e74f 2087 "Module ID %u (%s) for device %s:"
27108147
MI		 2088 " No i2c addresses."
2089 " The driver might have a configuration problem.",
1ab5e74f
MI		 2090 mid, fname, hdw->hdw_desc->description);
2091 return -EINVAL;
e9c64a78
MI		 2092 }
2093
e9c64a78 2094 if (i2ccnt == 1) {
bd14d4f8
MI		 2095 pvr2_trace(PVR2_TRACE_INIT,
2096 "Module ID %u:"
2097 " Setting up with specified i2c address 0x%x",
2098 mid, i2caddr[0]);
e6574f2f 2099 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
9a1f8b34 2100 fname, i2caddr[0], NULL);
e9c64a78 2101 } else {
bd14d4f8
MI		 2102 pvr2_trace(PVR2_TRACE_INIT,
2103 "Module ID %u:"
2104 " Setting up with address probe list",
2105 mid);
53dacb15 2106 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
9a1f8b34 2107 fname, 0, i2caddr);
e9c64a78
MI		 2108 }
2109
446dfdc6
MI		 2110 if (!sd) {
2111 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
27108147
MI		 2112 "Module ID %u (%s) for device %s failed to load."
2113 " Possible missing sub-device kernel module or"
2114 " initialization failure within module.",
1ab5e74f
MI		 2115 mid, fname, hdw->hdw_desc->description);
2116 return -EIO;
446dfdc6
MI		 2117 }
2118
2119 /* Tag this sub-device instance with the module ID we know about.
2120 In other places we'll use that tag to determine if the instance
2121 requires special handling. */
2122 sd->grp_id = mid;
2123
bd14d4f8 2124 pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
a932f507 2125
e9c64a78 2126
00e5f736
MI		 2127 /* client-specific setup... */
2128 switch (mid) {
2129 case PVR2_CLIENT_ID_CX25840:
00e5f736
MI		 2130 case PVR2_CLIENT_ID_SAA7115:
2131 hdw->decoder_client_id = mid;
2132 break;
2133 default: break;
2134 }
1ab5e74f
MI		 2135
2136 return 0;
e9c64a78
MI		 2137}
2138
2139
2140static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2141{
2142 unsigned int idx;
2143 const struct pvr2_string_table *cm;
2144 const struct pvr2_device_client_table *ct;
1ab5e74f 2145 int okFl = !0;
e9c64a78
MI		 2146
2147 cm = &hdw->hdw_desc->client_modules;
2148 for (idx = 0; idx < cm->cnt; idx++) {
2149 request_module(cm->lst[idx]);
2150 }
2151
2152 ct = &hdw->hdw_desc->client_table;
2153 for (idx = 0; idx < ct->cnt; idx++) {
bd14d4f8 2154 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
e9c64a78 2155 }
27108147
MI		 2156 if (!okFl) {
2157 hdw->flag_modulefail = !0;
2158 pvr2_hdw_render_useless(hdw);
2159 }
e9c64a78
MI		 2160}
2161
2162
d855497e
MI		 2163static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2164{
2165 int ret;
2166 unsigned int idx;
2167 struct pvr2_ctrl *cptr;
2168 int reloadFl = 0;
989eb154 2169 if (hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37
MI		 2170 if (!reloadFl) {
2171 reloadFl =
2172 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2173 == 0);
2174 if (reloadFl) {
2175 pvr2_trace(PVR2_TRACE_INIT,
2176 "USB endpoint config looks strange"
2177 "; possibly firmware needs to be"
2178 " loaded");
2179 }
d855497e 2180 }
1d643a37
MI		 2181 if (!reloadFl) {
2182 reloadFl = !pvr2_hdw_check_firmware(hdw);
2183 if (reloadFl) {
2184 pvr2_trace(PVR2_TRACE_INIT,
2185 "Check for FX2 firmware failed"
2186 "; possibly firmware needs to be"
2187 " loaded");
2188 }
d855497e 2189 }
1d643a37
MI		 2190 if (reloadFl) {
2191 if (pvr2_upload_firmware1(hdw) != 0) {
2192 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2193 "Failure uploading firmware1");
2194 }
2195 return;
d855497e 2196 }
d855497e
MI		 2197 }
2198 hdw->fw1_state = FW1_STATE_OK;
2199
d855497e
MI		 2200 if (!pvr2_hdw_dev_ok(hdw)) return;
2201
27764726
MI		 2202 hdw->force_dirty = !0;
2203
989eb154 2204 if (!hdw->hdw_desc->flag_no_powerup) {
1d643a37
MI		 2205 pvr2_hdw_cmd_powerup(hdw);
2206 if (!pvr2_hdw_dev_ok(hdw)) return;
d855497e
MI		 2207 }
2208
31335b13 2209 /* Take the IR chip out of reset, if appropriate */
27eab384 2210 if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) {
31335b13
MI		 2211 pvr2_issue_simple_cmd(hdw,
2212 FX2CMD_HCW_ZILOG_RESET |
2213 (1 << 8) |
2214 ((0) << 16));
2215 }
2216
d855497e
MI		 2217 // This step MUST happen after the earlier powerup step.
2218 pvr2_i2c_core_init(hdw);
2219 if (!pvr2_hdw_dev_ok(hdw)) return;
2220
e9c64a78 2221 pvr2_hdw_load_modules(hdw);
1ab5e74f 2222 if (!pvr2_hdw_dev_ok(hdw)) return;
e9c64a78 2223
cc26b076 2224 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
5c6cb4e2 2225
c05c0462 2226 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e
MI		 2227 cptr = hdw->controls + idx;
2228 if (cptr->info->skip_init) continue;
2229 if (!cptr->info->set_value) continue;
2230 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2231 }
2232
e17d787c
MI		 2233 pvr2_hdw_cx25840_vbi_hack(hdw);
2234
1bde0289
MI		 2235 /* Set up special default values for the television and radio
2236 frequencies here. It's not really important what these defaults
2237 are, but I set them to something usable in the Chicago area just
2238 to make driver testing a little easier. */
2239
5a4f5da6
MK		 2240 hdw->freqValTelevision = default_tv_freq;
2241 hdw->freqValRadio = default_radio_freq;
1bde0289 2242
d855497e
MI		 2243 // Do not use pvr2_reset_ctl_endpoints() here. It is not
2244 // thread-safe against the normal pvr2_send_request() mechanism.
2245 // (We should make it thread safe).
2246
aaf7884d
MI		 2247 if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2248 ret = pvr2_hdw_get_eeprom_addr(hdw);
d855497e 2249 if (!pvr2_hdw_dev_ok(hdw)) return;
aaf7884d
MI		 2250 if (ret < 0) {
2251 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2252 "Unable to determine location of eeprom,"
2253 " skipping");
2254 } else {
2255 hdw->eeprom_addr = ret;
2256 pvr2_eeprom_analyze(hdw);
2257 if (!pvr2_hdw_dev_ok(hdw)) return;
2258 }
2259 } else {
2260 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2261 hdw->tuner_updated = !0;
2262 hdw->std_mask_eeprom = V4L2_STD_ALL;
d855497e
MI		 2263 }
2264
13a88797
MI		 2265 if (hdw->serial_number) {
2266 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2267 "sn-%lu", hdw->serial_number);
2268 } else if (hdw->unit_number >= 0) {
2269 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2270 "unit-%c",
2271 hdw->unit_number + 'a');
2272 } else {
2273 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2274 "unit-??");
2275 }
2276 hdw->identifier[idx] = 0;
2277
d855497e
MI		 2278 pvr2_hdw_setup_std(hdw);
2279
2280 if (!get_default_tuner_type(hdw)) {
2281 pvr2_trace(PVR2_TRACE_INIT,
2282 "pvr2_hdw_setup: Tuner type overridden to %d",
2283 hdw->tuner_type);
2284 }
2285
d855497e
MI		 2286
2287 if (!pvr2_hdw_dev_ok(hdw)) return;
2288
1df59f0b
MI		 2289 if (hdw->hdw_desc->signal_routing_scheme ==
2290 PVR2_ROUTING_SCHEME_GOTVIEW) {
2291 /* Ensure that GPIO 11 is set to output for GOTVIEW
2292 hardware. */
2293 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2294 }
2295
681c7399 2296 pvr2_hdw_commit_setup(hdw);
d855497e
MI		 2297
2298 hdw->vid_stream = pvr2_stream_create();
2299 if (!pvr2_hdw_dev_ok(hdw)) return;
2300 pvr2_trace(PVR2_TRACE_INIT,
2301 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2302 if (hdw->vid_stream) {
2303 idx = get_default_error_tolerance(hdw);
2304 if (idx) {
2305 pvr2_trace(PVR2_TRACE_INIT,
2306 "pvr2_hdw_setup: video stream %p"
2307 " setting tolerance %u",
2308 hdw->vid_stream,idx);
2309 }
2310 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2311 PVR2_VID_ENDPOINT,idx);
2312 }
2313
2314 if (!pvr2_hdw_dev_ok(hdw)) return;
2315
d855497e 2316 hdw->flag_init_ok = !0;
681c7399
MI		 2317
2318 pvr2_hdw_state_sched(hdw);
d855497e
MI		 2319}
2320
2321
681c7399
MI		 2322/* Set up the structure and attempt to put the device into a usable state.
2323 This can be a time-consuming operation, which is why it is not done
2324 internally as part of the create() step. */
2325static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
d855497e
MI		 2326{
2327 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
681c7399 2328 do {
d855497e
MI		 2329 pvr2_hdw_setup_low(hdw);
2330 pvr2_trace(PVR2_TRACE_INIT,
2331 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
681c7399 2332 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
d855497e 2333 if (pvr2_hdw_dev_ok(hdw)) {
681c7399 2334 if (hdw->flag_init_ok) {
d855497e
MI		 2335 pvr2_trace(
2336 PVR2_TRACE_INFO,
2337 "Device initialization"
2338 " completed successfully.");
2339 break;
2340 }
2341 if (hdw->fw1_state == FW1_STATE_RELOAD) {
2342 pvr2_trace(
2343 PVR2_TRACE_INFO,
2344 "Device microcontroller firmware"
2345 " (re)loaded; it should now reset"
2346 " and reconnect.");
2347 break;
2348 }
2349 pvr2_trace(
2350 PVR2_TRACE_ERROR_LEGS,
2351 "Device initialization was not successful.");
2352 if (hdw->fw1_state == FW1_STATE_MISSING) {
2353 pvr2_trace(
2354 PVR2_TRACE_ERROR_LEGS,
2355 "Giving up since device"
2356 " microcontroller firmware"
2357 " appears to be missing.");
2358 break;
2359 }
2360 }
27108147
MI		 2361 if (hdw->flag_modulefail) {
2362 pvr2_trace(
2363 PVR2_TRACE_ERROR_LEGS,
2364 "***WARNING*** pvrusb2 driver initialization"
2365 " failed due to the failure of one or more"
2366 " sub-device kernel modules.");
2367 pvr2_trace(
2368 PVR2_TRACE_ERROR_LEGS,
2369 "You need to resolve the failing condition"
2370 " before this driver can function. There"
2371 " should be some earlier messages giving more"
2372 " information about the problem.");
515ebf79 2373 break;
27108147 2374 }
d855497e
MI		 2375 if (procreload) {
2376 pvr2_trace(
2377 PVR2_TRACE_ERROR_LEGS,
2378 "Attempting pvrusb2 recovery by reloading"
2379 " primary firmware.");
2380 pvr2_trace(
2381 PVR2_TRACE_ERROR_LEGS,
2382 "If this works, device should disconnect"
2383 " and reconnect in a sane state.");
2384 hdw->fw1_state = FW1_STATE_UNKNOWN;
2385 pvr2_upload_firmware1(hdw);
2386 } else {
2387 pvr2_trace(
2388 PVR2_TRACE_ERROR_LEGS,
2389 "***WARNING*** pvrusb2 device hardware"
2390 " appears to be jammed"
2391 " and I can't clear it.");
2392 pvr2_trace(
2393 PVR2_TRACE_ERROR_LEGS,
2394 "You might need to power cycle"
2395 " the pvrusb2 device"
2396 " in order to recover.");
2397 }
681c7399 2398 } while (0);
d855497e 2399 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
d855497e
MI		 2400}
2401
2402
c4a8828d
MI		 2403/* Perform second stage initialization. Set callback pointer first so that
2404 we can avoid a possible initialization race (if the kernel thread runs
2405 before the callback has been set). */
794b1607
MI		 2406int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2407 void (*callback_func)(void *),
2408 void *callback_data)
c4a8828d
MI		 2409{
2410 LOCK_TAKE(hdw->big_lock); do {
97f26ff6
MI		 2411 if (hdw->flag_disconnected) {
2412 /* Handle a race here: If we're already
2413 disconnected by this point, then give up. If we
2414 get past this then we'll remain connected for
2415 the duration of initialization since the entire
2416 initialization sequence is now protected by the
2417 big_lock. */
2418 break;
2419 }
c4a8828d
MI		 2420 hdw->state_data = callback_data;
2421 hdw->state_func = callback_func;
97f26ff6 2422 pvr2_hdw_setup(hdw);
c4a8828d 2423 } while (0); LOCK_GIVE(hdw->big_lock);
794b1607 2424 return hdw->flag_init_ok;
c4a8828d
MI		 2425}
2426
2427
2428/* Create, set up, and return a structure for interacting with the
2429 underlying hardware. */
d855497e
MI		 2430struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2431 const struct usb_device_id *devid)
2432{
7fb20fa3 2433 unsigned int idx,cnt1,cnt2,m;
fe15f136 2434 struct pvr2_hdw *hdw = NULL;
d855497e
MI		 2435 int valid_std_mask;
2436 struct pvr2_ctrl *cptr;
b72b7bf5 2437 struct usb_device *usb_dev;
989eb154 2438 const struct pvr2_device_desc *hdw_desc;
d855497e 2439 __u8 ifnum;
b30d2441
MI		 2440 struct v4l2_queryctrl qctrl;
2441 struct pvr2_ctl_info *ciptr;
d855497e 2442
b72b7bf5
MI		 2443 usb_dev = interface_to_usbdev(intf);
2444
d130fa8a 2445 hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
d855497e 2446
fe15f136
MI		 2447 if (hdw_desc == NULL) {
2448 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2449 " No device description pointer,"
2450 " unable to continue.");
2451 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2452 " please contact Mike Isely <isely@pobox.com>"
2453 " to get it included in the driver\n");
2454 goto fail;
2455 }
2456
ca545f7c 2457 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
d855497e 2458 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
989eb154 2459 hdw,hdw_desc->description);
e67e376b 2460 pvr2_trace(PVR2_TRACE_INFO, "Hardware description: %s",
00970beb 2461 hdw_desc->description);
8fd04448
MI		 2462 if (hdw_desc->flag_is_experimental) {
2463 pvr2_trace(PVR2_TRACE_INFO, "**********");
2464 pvr2_trace(PVR2_TRACE_INFO,
2465 "WARNING: Support for this device (%s) is"
2466 " experimental.", hdw_desc->description);
2467 pvr2_trace(PVR2_TRACE_INFO,
2468 "Important functionality might not be"
2469 " entirely working.");
2470 pvr2_trace(PVR2_TRACE_INFO,
2471 "Please consider contacting the driver author to"
2472 " help with further stabilization of the driver.");
2473 pvr2_trace(PVR2_TRACE_INFO, "**********");
2474 }
d855497e 2475 if (!hdw) goto fail;
681c7399
MI		 2476
2477 init_timer(&hdw->quiescent_timer);
2478 hdw->quiescent_timer.data = (unsigned long)hdw;
2479 hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2480
6e931375
MI		 2481 init_timer(&hdw->decoder_stabilization_timer);
2482 hdw->decoder_stabilization_timer.data = (unsigned long)hdw;
2483 hdw->decoder_stabilization_timer.function =
2484 pvr2_hdw_decoder_stabilization_timeout;
2485
681c7399
MI		 2486 init_timer(&hdw->encoder_wait_timer);
2487 hdw->encoder_wait_timer.data = (unsigned long)hdw;
2488 hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2489
d913d630
MI		 2490 init_timer(&hdw->encoder_run_timer);
2491 hdw->encoder_run_timer.data = (unsigned long)hdw;
2492 hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2493
681c7399
MI		 2494 hdw->master_state = PVR2_STATE_DEAD;
2495
2496 init_waitqueue_head(&hdw->state_wait_data);
2497
18103c57 2498 hdw->tuner_signal_stale = !0;
b30d2441 2499 cx2341x_fill_defaults(&hdw->enc_ctl_state);
d855497e 2500
7fb20fa3
MI		 2501 /* Calculate which inputs are OK */
2502 m = 0;
2503 if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
e8f5bacf
MI		 2504 if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2505 m |= 1 << PVR2_CVAL_INPUT_DTV;
2506 }
7fb20fa3
MI		 2507 if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2508 if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2509 if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2510 hdw->input_avail_mask = m;
1cb03b76 2511 hdw->input_allowed_mask = hdw->input_avail_mask;
7fb20fa3 2512
62433e31
MI		 2513 /* If not a hybrid device, pathway_state never changes. So
2514 initialize it here to what it should forever be. */
2515 if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2516 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2517 } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2518 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2519 }
2520
c05c0462 2521 hdw->control_cnt = CTRLDEF_COUNT;
b30d2441 2522 hdw->control_cnt += MPEGDEF_COUNT;
ca545f7c 2523 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
d855497e
MI		 2524 GFP_KERNEL);
2525 if (!hdw->controls) goto fail;
989eb154 2526 hdw->hdw_desc = hdw_desc;
27eab384 2527 hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme;
c05c0462
MI		 2528 for (idx = 0; idx < hdw->control_cnt; idx++) {
2529 cptr = hdw->controls + idx;
2530 cptr->hdw = hdw;
2531 }
d855497e
MI		 2532 for (idx = 0; idx < 32; idx++) {
2533 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2534 }
c05c0462 2535 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e 2536 cptr = hdw->controls + idx;
d855497e
MI		 2537 cptr->info = control_defs+idx;
2538 }
dbc40a0e
MI		 2539
2540 /* Ensure that default input choice is a valid one. */
2541 m = hdw->input_avail_mask;
2542 if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2543 if (!((1 << idx) & m)) continue;
2544 hdw->input_val = idx;
2545 break;
2546 }
2547
b30d2441 2548 /* Define and configure additional controls from cx2341x module. */
e79c70e6
TM		 2549 hdw->mpeg_ctrl_info = kcalloc(MPEGDEF_COUNT,
2550 sizeof(*(hdw->mpeg_ctrl_info)),
2551 GFP_KERNEL);
b30d2441 2552 if (!hdw->mpeg_ctrl_info) goto fail;
b30d2441
MI		 2553 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2554 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2555 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2556 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2557 ciptr->name = mpeg_ids[idx].strid;
2558 ciptr->v4l_id = mpeg_ids[idx].id;
2559 ciptr->skip_init = !0;
2560 ciptr->get_value = ctrl_cx2341x_get;
2561 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2562 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2563 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2564 qctrl.id = ciptr->v4l_id;
2565 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2566 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2567 ciptr->set_value = ctrl_cx2341x_set;
2568 }
2569 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2570 PVR2_CTLD_INFO_DESC_SIZE);
2571 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2572 ciptr->default_value = qctrl.default_value;
2573 switch (qctrl.type) {
2574 default:
2575 case V4L2_CTRL_TYPE_INTEGER:
2576 ciptr->type = pvr2_ctl_int;
2577 ciptr->def.type_int.min_value = qctrl.minimum;
2578 ciptr->def.type_int.max_value = qctrl.maximum;
2579 break;
2580 case V4L2_CTRL_TYPE_BOOLEAN:
2581 ciptr->type = pvr2_ctl_bool;
2582 break;
2583 case V4L2_CTRL_TYPE_MENU:
2584 ciptr->type = pvr2_ctl_enum;
2585 ciptr->def.type_enum.value_names =
e0e31cdb
HV		 2586 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2587 ciptr->v4l_id);
b30d2441
MI		 2588 for (cnt1 = 0;
2589 ciptr->def.type_enum.value_names[cnt1] != NULL;
2590 cnt1++) { }
2591 ciptr->def.type_enum.count = cnt1;
2592 break;
2593 }
2594 cptr->info = ciptr;
2595 }
d855497e
MI		 2596
2597 // Initialize video standard enum dynamic control
2598 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2599 if (cptr) {
2600 memcpy(&hdw->std_info_enum,cptr->info,
2601 sizeof(hdw->std_info_enum));
2602 cptr->info = &hdw->std_info_enum;
2603
2604 }
2605 // Initialize control data regarding video standard masks
2606 valid_std_mask = pvr2_std_get_usable();
2607 for (idx = 0; idx < 32; idx++) {
2608 if (!(valid_std_mask & (1 << idx))) continue;
2609 cnt1 = pvr2_std_id_to_str(
2610 hdw->std_mask_names[idx],
2611 sizeof(hdw->std_mask_names[idx])-1,
2612 1 << idx);
2613 hdw->std_mask_names[idx][cnt1] = 0;
2614 }
2615 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2616 if (cptr) {
2617 memcpy(&hdw->std_info_avail,cptr->info,
2618 sizeof(hdw->std_info_avail));
2619 cptr->info = &hdw->std_info_avail;
2620 hdw->std_info_avail.def.type_bitmask.bit_names =
2621 hdw->std_mask_ptrs;
2622 hdw->std_info_avail.def.type_bitmask.valid_bits =
2623 valid_std_mask;
2624 }
2625 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2626 if (cptr) {
2627 memcpy(&hdw->std_info_cur,cptr->info,
2628 sizeof(hdw->std_info_cur));
2629 cptr->info = &hdw->std_info_cur;
2630 hdw->std_info_cur.def.type_bitmask.bit_names =
2631 hdw->std_mask_ptrs;
2632 hdw->std_info_avail.def.type_bitmask.valid_bits =
2633 valid_std_mask;
2634 }
2635
432907f7 2636 hdw->cropcap_stale = !0;
d855497e
MI		 2637 hdw->eeprom_addr = -1;
2638 hdw->unit_number = -1;
8079384e
MI		 2639 hdw->v4l_minor_number_video = -1;
2640 hdw->v4l_minor_number_vbi = -1;
fd5a75fe 2641 hdw->v4l_minor_number_radio = -1;
d855497e
MI		 2642 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2643 if (!hdw->ctl_write_buffer) goto fail;
2644 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2645 if (!hdw->ctl_read_buffer) goto fail;
2646 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2647 if (!hdw->ctl_write_urb) goto fail;
2648 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2649 if (!hdw->ctl_read_urb) goto fail;
2650
70ad6383 2651 if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) {
b72b7bf5
MI		 2652 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2653 "Error registering with v4l core, giving up");
2654 goto fail;
2655 }
8df0c87c 2656 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2657 for (idx = 0; idx < PVR_NUM; idx++) {
2658 if (unit_pointers[idx]) continue;
2659 hdw->unit_number = idx;
2660 unit_pointers[idx] = hdw;
2661 break;
2662 }
8df0c87c 2663 } while (0); mutex_unlock(&pvr2_unit_mtx);
d855497e
MI		 2664
2665 cnt1 = 0;
2666 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2667 cnt1 += cnt2;
2668 if (hdw->unit_number >= 0) {
2669 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2670 ('a' + hdw->unit_number));
2671 cnt1 += cnt2;
2672 }
2673 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2674 hdw->name[cnt1] = 0;
2675
681c7399
MI		 2676 hdw->workqueue = create_singlethread_workqueue(hdw->name);
2677 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
681c7399 2678
d855497e
MI		 2679 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2680 hdw->unit_number,hdw->name);
2681
2682 hdw->tuner_type = -1;
2683 hdw->flag_ok = !0;
d855497e
MI		 2684
2685 hdw->usb_intf = intf;
b72b7bf5 2686 hdw->usb_dev = usb_dev;
d855497e 2687
87e3495c 2688 usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
31a18547 2689
d855497e
MI		 2690 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2691 usb_set_interface(hdw->usb_dev,ifnum,0);
2692
2693 mutex_init(&hdw->ctl_lock_mutex);
2694 mutex_init(&hdw->big_lock_mutex);
2695
2696 return hdw;
2697 fail:
2698 if (hdw) {
681c7399 2699 del_timer_sync(&hdw->quiescent_timer);
6e931375 2700 del_timer_sync(&hdw->decoder_stabilization_timer);
d913d630 2701 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 2702 del_timer_sync(&hdw->encoder_wait_timer);
2703 if (hdw->workqueue) {
2704 flush_workqueue(hdw->workqueue);
2705 destroy_workqueue(hdw->workqueue);
2706 hdw->workqueue = NULL;
2707 }
5e55d2ce
MK		 2708 usb_free_urb(hdw->ctl_read_urb);
2709 usb_free_urb(hdw->ctl_write_urb);
22071a42
MK		 2710 kfree(hdw->ctl_read_buffer);
2711 kfree(hdw->ctl_write_buffer);
2712 kfree(hdw->controls);
2713 kfree(hdw->mpeg_ctrl_info);
681c7399
MI		 2714 kfree(hdw->std_defs);
2715 kfree(hdw->std_enum_names);
d855497e
MI		 2716 kfree(hdw);
2717 }
a0fd1cb1 2718 return NULL;
d855497e
MI		 2719}
2720
2721
2722/* Remove _all_ associations between this driver and the underlying USB
2723 layer. */
07e337ee 2724static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
d855497e
MI		 2725{
2726 if (hdw->flag_disconnected) return;
2727 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2728 if (hdw->ctl_read_urb) {
2729 usb_kill_urb(hdw->ctl_read_urb);
2730 usb_free_urb(hdw->ctl_read_urb);
a0fd1cb1 2731 hdw->ctl_read_urb = NULL;
d855497e
MI		 2732 }
2733 if (hdw->ctl_write_urb) {
2734 usb_kill_urb(hdw->ctl_write_urb);
2735 usb_free_urb(hdw->ctl_write_urb);
a0fd1cb1 2736 hdw->ctl_write_urb = NULL;
d855497e
MI		 2737 }
2738 if (hdw->ctl_read_buffer) {
2739 kfree(hdw->ctl_read_buffer);
a0fd1cb1 2740 hdw->ctl_read_buffer = NULL;
d855497e
MI		 2741 }
2742 if (hdw->ctl_write_buffer) {
2743 kfree(hdw->ctl_write_buffer);
a0fd1cb1 2744 hdw->ctl_write_buffer = NULL;
d855497e 2745 }
d855497e 2746 hdw->flag_disconnected = !0;
b72b7bf5
MI		 2747 /* If we don't do this, then there will be a dangling struct device
2748 reference to our disappearing device persisting inside the V4L
2749 core... */
dc070bcc 2750 v4l2_device_disconnect(&hdw->v4l2_dev);
a0fd1cb1
MI		 2751 hdw->usb_dev = NULL;
2752 hdw->usb_intf = NULL;
681c7399 2753 pvr2_hdw_render_useless(hdw);
d855497e
MI		 2754}
2755
2756
2757/* Destroy hardware interaction structure */
2758void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2759{
401c27ce 2760 if (!hdw) return;
d855497e 2761 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
681c7399
MI		 2762 if (hdw->workqueue) {
2763 flush_workqueue(hdw->workqueue);
2764 destroy_workqueue(hdw->workqueue);
2765 hdw->workqueue = NULL;
2766 }
8f59100a 2767 del_timer_sync(&hdw->quiescent_timer);
6e931375 2768 del_timer_sync(&hdw->decoder_stabilization_timer);
d913d630 2769 del_timer_sync(&hdw->encoder_run_timer);
8f59100a 2770 del_timer_sync(&hdw->encoder_wait_timer);
d855497e
MI		 2771 if (hdw->fw_buffer) {
2772 kfree(hdw->fw_buffer);
a0fd1cb1 2773 hdw->fw_buffer = NULL;
d855497e
MI		 2774 }
2775 if (hdw->vid_stream) {
2776 pvr2_stream_destroy(hdw->vid_stream);
a0fd1cb1 2777 hdw->vid_stream = NULL;
d855497e 2778 }
d855497e 2779 pvr2_i2c_core_done(hdw);
b72b7bf5 2780 v4l2_device_unregister(&hdw->v4l2_dev);
d855497e 2781 pvr2_hdw_remove_usb_stuff(hdw);
8df0c87c 2782 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2783 if ((hdw->unit_number >= 0) &&
2784 (hdw->unit_number < PVR_NUM) &&
2785 (unit_pointers[hdw->unit_number] == hdw)) {
a0fd1cb1 2786 unit_pointers[hdw->unit_number] = NULL;
d855497e 2787 }
8df0c87c 2788 } while (0); mutex_unlock(&pvr2_unit_mtx);
22071a42
MK		 2789 kfree(hdw->controls);
2790 kfree(hdw->mpeg_ctrl_info);
2791 kfree(hdw->std_defs);
2792 kfree(hdw->std_enum_names);
d855497e
MI		 2793 kfree(hdw);
2794}
2795
2796
d855497e
MI		 2797int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2798{
2799 return (hdw && hdw->flag_ok);
2800}
2801
2802
2803/* Called when hardware has been unplugged */
2804void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2805{
2806 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2807 LOCK_TAKE(hdw->big_lock);
2808 LOCK_TAKE(hdw->ctl_lock);
2809 pvr2_hdw_remove_usb_stuff(hdw);
2810 LOCK_GIVE(hdw->ctl_lock);
2811 LOCK_GIVE(hdw->big_lock);
2812}
2813
2814
2815// Attempt to autoselect an appropriate value for std_enum_cur given
2816// whatever is currently in std_mask_cur
07e337ee 2817static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
d855497e
MI		 2818{
2819 unsigned int idx;
2820 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2821 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2822 hdw->std_enum_cur = idx;
2823 return;
2824 }
2825 }
2826 hdw->std_enum_cur = 0;
2827}
2828
2829
2830// Calculate correct set of enumerated standards based on currently known
2831// set of available standards bits.
07e337ee 2832static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
d855497e
MI		 2833{
2834 struct v4l2_standard *newstd;
2835 unsigned int std_cnt;
2836 unsigned int idx;
2837
2838 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2839
2840 if (hdw->std_defs) {
2841 kfree(hdw->std_defs);
a0fd1cb1 2842 hdw->std_defs = NULL;
d855497e
MI		 2843 }
2844 hdw->std_enum_cnt = 0;
2845 if (hdw->std_enum_names) {
2846 kfree(hdw->std_enum_names);
a0fd1cb1 2847 hdw->std_enum_names = NULL;
d855497e
MI		 2848 }
2849
2850 if (!std_cnt) {
2851 pvr2_trace(
2852 PVR2_TRACE_ERROR_LEGS,
2853 "WARNING: Failed to identify any viable standards");
2854 }
c05df8b3
XW		 2855
2856 /* Set up the dynamic control for this standard */
d855497e 2857 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
c05df8b3
XW		 2858 if (hdw->std_enum_names) {
2859 hdw->std_enum_names[0] = "none";
2860 for (idx = 0; idx < std_cnt; idx++)
2861 hdw->std_enum_names[idx+1] = newstd[idx].name;
2862 hdw->std_info_enum.def.type_enum.value_names =
2863 hdw->std_enum_names;
2864 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2865 } else {
2866 pvr2_trace(
2867 PVR2_TRACE_ERROR_LEGS,
2868 "WARNING: Failed to alloc memory for names");
2869 hdw->std_info_enum.def.type_enum.value_names = NULL;
2870 hdw->std_info_enum.def.type_enum.count = 0;
2871 }
d855497e
MI		 2872 hdw->std_defs = newstd;
2873 hdw->std_enum_cnt = std_cnt+1;
2874 hdw->std_enum_cur = 0;
2875 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2876}
2877
2878
2879int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2880 struct v4l2_standard *std,
2881 unsigned int idx)
2882{
2883 int ret = -EINVAL;
2884 if (!idx) return ret;
2885 LOCK_TAKE(hdw->big_lock); do {
2886 if (idx >= hdw->std_enum_cnt) break;
2887 idx--;
2888 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2889 ret = 0;
2890 } while (0); LOCK_GIVE(hdw->big_lock);
2891 return ret;
2892}
2893
2894
2895/* Get the number of defined controls */
2896unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2897{
c05c0462 2898 return hdw->control_cnt;
d855497e
MI		 2899}
2900
2901
2902/* Retrieve a control handle given its index (0..count-1) */
2903struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2904 unsigned int idx)
2905{
a0fd1cb1 2906 if (idx >= hdw->control_cnt) return NULL;
d855497e
MI		 2907 return hdw->controls + idx;
2908}
2909
2910
2911/* Retrieve a control handle given its index (0..count-1) */
2912struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2913 unsigned int ctl_id)
2914{
2915 struct pvr2_ctrl *cptr;
2916 unsigned int idx;
2917 int i;
2918
2919 /* This could be made a lot more efficient, but for now... */
c05c0462 2920 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2921 cptr = hdw->controls + idx;
2922 i = cptr->info->internal_id;
2923 if (i && (i == ctl_id)) return cptr;
2924 }
a0fd1cb1 2925 return NULL;
d855497e
MI		 2926}
2927
2928
a761f431 2929/* Given a V4L ID, retrieve the control structure associated with it. */
d855497e
MI		 2930struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2931{
2932 struct pvr2_ctrl *cptr;
2933 unsigned int idx;
2934 int i;
2935
2936 /* This could be made a lot more efficient, but for now... */
c05c0462 2937 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2938 cptr = hdw->controls + idx;
2939 i = cptr->info->v4l_id;
2940 if (i && (i == ctl_id)) return cptr;
2941 }
a0fd1cb1 2942 return NULL;
d855497e
MI		 2943}
2944
2945
a761f431
MI		 2946/* Given a V4L ID for its immediate predecessor, retrieve the control
2947 structure associated with it. */
2948struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2949 unsigned int ctl_id)
2950{
2951 struct pvr2_ctrl *cptr,*cp2;
2952 unsigned int idx;
2953 int i;
2954
2955 /* This could be made a lot more efficient, but for now... */
a0fd1cb1 2956 cp2 = NULL;
a761f431
MI		 2957 for (idx = 0; idx < hdw->control_cnt; idx++) {
2958 cptr = hdw->controls + idx;
2959 i = cptr->info->v4l_id;
2960 if (!i) continue;
2961 if (i <= ctl_id) continue;
2962 if (cp2 && (cp2->info->v4l_id < i)) continue;
2963 cp2 = cptr;
2964 }
2965 return cp2;
a0fd1cb1 2966 return NULL;
a761f431
MI		 2967}
2968
2969
d855497e
MI		 2970static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2971{
2972 switch (tp) {
2973 case pvr2_ctl_int: return "integer";
2974 case pvr2_ctl_enum: return "enum";
33213963 2975 case pvr2_ctl_bool: return "boolean";
d855497e
MI		 2976 case pvr2_ctl_bitmask: return "bitmask";
2977 }
2978 return "";
2979}
2980
2981
2641df36
MI		 2982static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2983 const char *name, int val)
2984{
2985 struct v4l2_control ctrl;
2986 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2987 memset(&ctrl, 0, sizeof(ctrl));
2988 ctrl.id = id;
2989 ctrl.value = val;
2990 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2991}
2992
2993#define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
27764726 2994 if ((hdw)->lab##_dirty || (hdw)->force_dirty) { \
2641df36
MI		 2995 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2996 }
2997
7383a473
MCC		 2998int pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw, v4l2_std_id *std)
2999{
7378c184 3000 *std = V4L2_STD_ALL;
7383a473
MCC		 3001 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3002 video, querystd, std);
3003 return 0;
3004}
3005
5ceaad14 3006/* Execute whatever commands are required to update the state of all the
2641df36 3007 sub-devices so that they match our current control values. */
5ceaad14
MI		 3008static void pvr2_subdev_update(struct pvr2_hdw *hdw)
3009{
edb9dcb8
MI		 3010 struct v4l2_subdev *sd;
3011 unsigned int id;
3012 pvr2_subdev_update_func fp;
3013
75212a02
MI		 3014 pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
3015
27764726 3016 if (hdw->tuner_updated || hdw->force_dirty) {
75212a02
MI		 3017 struct tuner_setup setup;
3018 pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
3019 hdw->tuner_type);
3020 if (((int)(hdw->tuner_type)) >= 0) {
fcd62cf7 3021 memset(&setup, 0, sizeof(setup));
75212a02
MI		 3022 setup.addr = ADDR_UNSET;
3023 setup.type = hdw->tuner_type;
3024 setup.mode_mask = T_RADIO | T_ANALOG_TV;
3025 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3026 tuner, s_type_addr, &setup);
3027 }
3028 }
3029
27764726 3030 if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
b481880b 3031 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
2641df36
MI		 3032 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3033 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3034 tuner, s_radio);
3035 } else {
3036 v4l2_std_id vs;
3037 vs = hdw->std_mask_cur;
3038 v4l2_device_call_all(&hdw->v4l2_dev, 0,
f41737ec 3039 core, s_std, vs);
a6862da2 3040 pvr2_hdw_cx25840_vbi_hack(hdw);
2641df36
MI		 3041 }
3042 hdw->tuner_signal_stale = !0;
3043 hdw->cropcap_stale = !0;
3044 }
3045
3046 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
3047 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
3048 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
3049 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
3050 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
3051 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
3052 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
3053 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
3054 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
3055
27764726 3056 if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
2641df36
MI		 3057 struct v4l2_tuner vt;
3058 memset(&vt, 0, sizeof(vt));
50e9efd6
HV		 3059 vt.type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
3060 V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
2641df36
MI		 3061 vt.audmode = hdw->audiomode_val;
3062 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
3063 }
3064
27764726 3065 if (hdw->freqDirty || hdw->force_dirty) {
2641df36
MI		 3066 unsigned long fv;
3067 struct v4l2_frequency freq;
3068 fv = pvr2_hdw_get_cur_freq(hdw);
3069 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
3070 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
3071 memset(&freq, 0, sizeof(freq));
3072 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
3073 /* ((fv * 1000) / 62500) */
3074 freq.frequency = (fv * 2) / 125;
3075 } else {
3076 freq.frequency = fv / 62500;
3077 }
3078 /* tuner-core currently doesn't seem to care about this, but
3079 let's set it anyway for completeness. */
3080 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3081 freq.type = V4L2_TUNER_RADIO;
3082 } else {
3083 freq.type = V4L2_TUNER_ANALOG_TV;
3084 }
3085 freq.tuner = 0;
3086 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
3087 s_frequency, &freq);
3088 }
3089
27764726 3090 if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
fa190ee9 3091 struct v4l2_mbus_framefmt fmt;
2641df36 3092 memset(&fmt, 0, sizeof(fmt));
fa190ee9
HV		 3093 fmt.width = hdw->res_hor_val;
3094 fmt.height = hdw->res_ver_val;
3095 fmt.code = V4L2_MBUS_FMT_FIXED;
7dfdf1ee 3096 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
fa190ee9
HV		 3097 fmt.width, fmt.height);
3098 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_mbus_fmt, &fmt);
2641df36
MI		 3099 }
3100
27764726 3101 if (hdw->srate_dirty || hdw->force_dirty) {
01c59df8
MI		 3102 u32 val;
3103 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
3104 hdw->srate_val);
3105 switch (hdw->srate_val) {
3106 default:
3107 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
3108 val = 48000;
3109 break;
3110 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
3111 val = 44100;
3112 break;
3113 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
3114 val = 32000;
3115 break;
3116 }
3117 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3118 audio, s_clock_freq, val);
3119 }
3120
2641df36
MI		 3121 /* Unable to set crop parameters; there is apparently no equivalent
3122 for VIDIOC_S_CROP */
3123
edb9dcb8
MI		 3124 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
3125 id = sd->grp_id;
3126 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
3127 fp = pvr2_module_update_functions[id];
3128 if (!fp) continue;
3129 (*fp)(hdw, sd);
3130 }
2641df36 3131
27764726 3132 if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
2641df36
MI		 3133 pvr2_hdw_status_poll(hdw);
3134 }
5ceaad14
MI		 3135}
3136
3137
681c7399
MI		 3138/* Figure out if we need to commit control changes. If so, mark internal
3139 state flags to indicate this fact and return true. Otherwise do nothing
3140 else and return false. */
3141static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
d855497e 3142{
d855497e
MI		 3143 unsigned int idx;
3144 struct pvr2_ctrl *cptr;
3145 int value;
27764726 3146 int commit_flag = hdw->force_dirty;
d855497e
MI		 3147 char buf[100];
3148 unsigned int bcnt,ccnt;
3149
c05c0462 3150 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e 3151 cptr = hdw->controls + idx;
5fa1247a 3152 if (!cptr->info->is_dirty) continue;
d855497e 3153 if (!cptr->info->is_dirty(cptr)) continue;
fe23a280 3154 commit_flag = !0;
d855497e 3155
fe23a280 3156 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
d855497e
MI		 3157 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3158 cptr->info->name);
3159 value = 0;
3160 cptr->info->get_value(cptr,&value);
3161 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3162 buf+bcnt,
3163 sizeof(buf)-bcnt,&ccnt);
3164 bcnt += ccnt;
3165 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3166 get_ctrl_typename(cptr->info->type));
3167 pvr2_trace(PVR2_TRACE_CTL,
3168 "/*--TRACE_COMMIT--*/ %.*s",
3169 bcnt,buf);
3170 }
3171
3172 if (!commit_flag) {
3173 /* Nothing has changed */
3174 return 0;
3175 }
3176
681c7399
MI		 3177 hdw->state_pipeline_config = 0;
3178 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3179 pvr2_hdw_state_sched(hdw);
3180
3181 return !0;
3182}
3183
3184
3185/* Perform all operations needed to commit all control changes. This must
3186 be performed in synchronization with the pipeline state and is thus
3187 expected to be called as part of the driver's worker thread. Return
3188 true if commit successful, otherwise return false to indicate that
3189 commit isn't possible at this time. */
3190static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3191{
3192 unsigned int idx;
3193 struct pvr2_ctrl *cptr;
3194 int disruptive_change;
3195
9bf98321
MI		 3196 if (hdw->input_dirty && hdw->state_pathway_ok &&
3197 (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3198 PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3199 hdw->pathway_state)) {
3200 /* Change of mode being asked for... */
3201 hdw->state_pathway_ok = 0;
3202 trace_stbit("state_pathway_ok", hdw->state_pathway_ok);
3203 }
3204 if (!hdw->state_pathway_ok) {
3205 /* Can't commit anything until pathway is ok. */
3206 return 0;
3207 }
3208
ab062fe3
MI		 3209 /* Handle some required side effects when the video standard is
3210 changed.... */
d855497e 3211 if (hdw->std_dirty) {
d855497e 3212 int nvres;
00528d9c 3213 int gop_size;
d855497e
MI		 3214 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3215 nvres = 480;
00528d9c 3216 gop_size = 15;
d855497e
MI		 3217 } else {
3218 nvres = 576;
00528d9c 3219 gop_size = 12;
d855497e 3220 }
00528d9c
MI		 3221 /* Rewrite the vertical resolution to be appropriate to the
3222 video standard that has been selected. */
d855497e
MI		 3223 if (nvres != hdw->res_ver_val) {
3224 hdw->res_ver_val = nvres;
3225 hdw->res_ver_dirty = !0;
3226 }
00528d9c
MI		 3227 /* Rewrite the GOP size to be appropriate to the video
3228 standard that has been selected. */
3229 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3230 struct v4l2_ext_controls cs;
3231 struct v4l2_ext_control c1;
3232 memset(&cs, 0, sizeof(cs));
3233 memset(&c1, 0, sizeof(c1));
3234 cs.controls = &c1;
3235 cs.count = 1;
3236 c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3237 c1.value = gop_size;
3238 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3239 VIDIOC_S_EXT_CTRLS);
3240 }
d855497e
MI		 3241 }
3242
e784bfb9 3243 /* The broadcast decoder can only scale down, so if
3244 * res_*_dirty && crop window < output format ==> enlarge crop.
3245 *
3246 * The mpeg encoder receives fields of res_hor_val dots and
3247 * res_ver_val halflines. Limits: hor<=720, ver<=576.
3248 */
3249 if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3250 hdw->cropw_val = hdw->res_hor_val;
3251 hdw->cropw_dirty = !0;
3252 } else if (hdw->cropw_dirty) {
3253 hdw->res_hor_dirty = !0; /* must rescale */
3254 hdw->res_hor_val = min(720, hdw->cropw_val);
3255 }
3256 if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3257 hdw->croph_val = hdw->res_ver_val;
3258 hdw->croph_dirty = !0;
3259 } else if (hdw->croph_dirty) {
3260 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3261 hdw->res_ver_dirty = !0;
3262 hdw->res_ver_val = min(nvres, hdw->croph_val);
3263 }
3264
681c7399
MI		 3265 /* If any of the below has changed, then we can't do the update
3266 while the pipeline is running. Pipeline must be paused first
3267 and decoder -> encoder connection be made quiescent before we
3268 can proceed. */
3269 disruptive_change =
3270 (hdw->std_dirty ||
3271 hdw->enc_unsafe_stale ||
3272 hdw->srate_dirty ||
3273 hdw->res_ver_dirty ||
3274 hdw->res_hor_dirty ||
755879c6
MI		 3275 hdw->cropw_dirty ||
3276 hdw->croph_dirty ||
681c7399
MI		 3277 hdw->input_dirty ||
3278 (hdw->active_stream_type != hdw->desired_stream_type));
3279 if (disruptive_change && !hdw->state_pipeline_idle) {
3280 /* Pipeline is not idle; we can't proceed. Arrange to
3281 cause pipeline to stop so that we can try this again
3282 later.... */
3283 hdw->state_pipeline_pause = !0;
3284 return 0;
275b2e28
PK		 3285 }
3286
b30d2441
MI		 3287 if (hdw->srate_dirty) {
3288 /* Write new sample rate into control structure since
3289 * the master copy is stale. We must track srate
3290 * separate from the mpeg control structure because
3291 * other logic also uses this value. */
3292 struct v4l2_ext_controls cs;
3293 struct v4l2_ext_control c1;
3294 memset(&cs,0,sizeof(cs));
3295 memset(&c1,0,sizeof(c1));
3296 cs.controls = &c1;
3297 cs.count = 1;
3298 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3299 c1.value = hdw->srate_val;
01f1e44f 3300 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
b30d2441 3301 }
c05c0462 3302
681c7399
MI		 3303 if (hdw->active_stream_type != hdw->desired_stream_type) {
3304 /* Handle any side effects of stream config here */
3305 hdw->active_stream_type = hdw->desired_stream_type;
3306 }
3307
1df59f0b
MI		 3308 if (hdw->hdw_desc->signal_routing_scheme ==
3309 PVR2_ROUTING_SCHEME_GOTVIEW) {
3310 u32 b;
3311 /* Handle GOTVIEW audio switching */
3312 pvr2_hdw_gpio_get_out(hdw,&b);
3313 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3314 /* Set GPIO 11 */
3315 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3316 } else {
3317 /* Clear GPIO 11 */
3318 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3319 }
3320 }
3321
e68a619a
MI		 3322 /* Check and update state for all sub-devices. */
3323 pvr2_subdev_update(hdw);
3324
75212a02 3325 hdw->tuner_updated = 0;
27764726 3326 hdw->force_dirty = 0;
5ceaad14
MI		 3327 for (idx = 0; idx < hdw->control_cnt; idx++) {
3328 cptr = hdw->controls + idx;
3329 if (!cptr->info->clear_dirty) continue;
3330 cptr->info->clear_dirty(cptr);
3331 }
3332
62433e31
MI		 3333 if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3334 hdw->state_encoder_run) {
3335 /* If encoder isn't running or it can't be touched, then
3336 this will get worked out later when we start the
3337 encoder. */
681c7399
MI		 3338 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3339 }
d855497e 3340
681c7399 3341 hdw->state_pipeline_config = !0;
432907f7
MI		 3342 /* Hardware state may have changed in a way to cause the cropping
3343 capabilities to have changed. So mark it stale, which will
3344 cause a later re-fetch. */
681c7399
MI		 3345 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3346 return !0;
d855497e
MI		 3347}
3348
3349
3350int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3351{
681c7399
MI		 3352 int fl;
3353 LOCK_TAKE(hdw->big_lock);
3354 fl = pvr2_hdw_commit_setup(hdw);
3355 LOCK_GIVE(hdw->big_lock);
3356 if (!fl) return 0;
3357 return pvr2_hdw_wait(hdw,0);
3358}
3359
3360
681c7399 3361static void pvr2_hdw_worker_poll(struct work_struct *work)
d855497e 3362{
681c7399
MI		 3363 int fl = 0;
3364 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
d855497e 3365 LOCK_TAKE(hdw->big_lock); do {
681c7399 3366 fl = pvr2_hdw_state_eval(hdw);
d855497e 3367 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 3368 if (fl && hdw->state_func) {
3369 hdw->state_func(hdw->state_data);
3370 }
d855497e
MI		 3371}
3372
3373
681c7399 3374static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
d855497e 3375{
681c7399
MI		 3376 return wait_event_interruptible(
3377 hdw->state_wait_data,
3378 (hdw->state_stale == 0) &&
3379 (!state || (hdw->master_state != state)));
3380}
3381
3382
d855497e
MI		 3383/* Return name for this driver instance */
3384const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3385{
3386 return hdw->name;
3387}
3388
3389
78a47101
MI		 3390const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3391{
3392 return hdw->hdw_desc->description;
3393}
3394
3395
3396const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3397{
3398 return hdw->hdw_desc->shortname;
3399}
3400
3401
d855497e
MI		 3402int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3403{
3404 int result;
3405 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 3406 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
d855497e
MI		 3407 result = pvr2_send_request(hdw,
3408 hdw->cmd_buffer,1,
3409 hdw->cmd_buffer,1);
3410 if (result < 0) break;
3411 result = (hdw->cmd_buffer[0] != 0);
3412 } while(0); LOCK_GIVE(hdw->ctl_lock);
3413 return result;
3414}
3415
3416
18103c57
MI		 3417/* Execute poll of tuner status */
3418void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
d855497e 3419{
d855497e 3420 LOCK_TAKE(hdw->big_lock); do {
a51f5000 3421 pvr2_hdw_status_poll(hdw);
d855497e 3422 } while (0); LOCK_GIVE(hdw->big_lock);
18103c57
MI		 3423}
3424
3425
432907f7
MI		 3426static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3427{
3428 if (!hdw->cropcap_stale) {
432907f7
MI		 3429 return 0;
3430 }
a51f5000 3431 pvr2_hdw_status_poll(hdw);
432907f7 3432 if (hdw->cropcap_stale) {
432907f7
MI		 3433 return -EIO;
3434 }
3435 return 0;
3436}
3437
3438
3439/* Return information about cropping capabilities */
3440int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3441{
3442 int stat = 0;
3443 LOCK_TAKE(hdw->big_lock);
3444 stat = pvr2_hdw_check_cropcap(hdw);
3445 if (!stat) {
432907f7
MI		 3446 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3447 }
3448 LOCK_GIVE(hdw->big_lock);
3449 return stat;
3450}
3451
3452
18103c57
MI		 3453/* Return information about the tuner */
3454int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3455{
3456 LOCK_TAKE(hdw->big_lock); do {
3457 if (hdw->tuner_signal_stale) {
a51f5000 3458 pvr2_hdw_status_poll(hdw);
18103c57
MI		 3459 }
3460 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3461 } while (0); LOCK_GIVE(hdw->big_lock);
3462 return 0;
d855497e
MI		 3463}
3464
3465
3466/* Get handle to video output stream */
3467struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3468{
3469 return hp->vid_stream;
3470}
3471
3472
3473void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3474{
4f1a3e5b 3475 int nr = pvr2_hdw_get_unit_number(hdw);
d855497e 3476 LOCK_TAKE(hdw->big_lock); do {
4f1a3e5b 3477 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
ed3261a8 3478 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
b30d2441 3479 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
99eb44fe 3480 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
681c7399 3481 pvr2_hdw_state_log_state(hdw);
4f1a3e5b 3482 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
d855497e
MI		 3483 } while (0); LOCK_GIVE(hdw->big_lock);
3484}
3485
4db666cc
MI		 3486
3487/* Grab EEPROM contents, needed for direct method. */
3488#define EEPROM_SIZE 8192
3489#define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3490static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3491{
3492 struct i2c_msg msg[2];
3493 u8 *eeprom;
3494 u8 iadd[2];
3495 u8 addr;
3496 u16 eepromSize;
3497 unsigned int offs;
3498 int ret;
3499 int mode16 = 0;
3500 unsigned pcnt,tcnt;
3501 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3502 if (!eeprom) {
3503 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3504 "Failed to allocate memory"
3505 " required to read eeprom");
3506 return NULL;
3507 }
3508
3509 trace_eeprom("Value for eeprom addr from controller was 0x%x",
3510 hdw->eeprom_addr);
3511 addr = hdw->eeprom_addr;
3512 /* Seems that if the high bit is set, then the *real* eeprom
3513 address is shifted right now bit position (noticed this in
3514 newer PVR USB2 hardware) */
3515 if (addr & 0x80) addr >>= 1;
3516
3517 /* FX2 documentation states that a 16bit-addressed eeprom is
3518 expected if the I2C address is an odd number (yeah, this is
3519 strange but it's what they do) */
3520 mode16 = (addr & 1);
3521 eepromSize = (mode16 ? EEPROM_SIZE : 256);
3522 trace_eeprom("Examining %d byte eeprom at location 0x%x"
3523 " using %d bit addressing",eepromSize,addr,
3524 mode16 ? 16 : 8);
3525
3526 msg[0].addr = addr;
3527 msg[0].flags = 0;
3528 msg[0].len = mode16 ? 2 : 1;
3529 msg[0].buf = iadd;
3530 msg[1].addr = addr;
3531 msg[1].flags = I2C_M_RD;
3532
3533 /* We have to do the actual eeprom data fetch ourselves, because
3534 (1) we're only fetching part of the eeprom, and (2) if we were
3535 getting the whole thing our I2C driver can't grab it in one
3536 pass - which is what tveeprom is otherwise going to attempt */
3537 memset(eeprom,0,EEPROM_SIZE);
3538 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3539 pcnt = 16;
3540 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3541 offs = tcnt + (eepromSize - EEPROM_SIZE);
3542 if (mode16) {
3543 iadd[0] = offs >> 8;
3544 iadd[1] = offs;
3545 } else {
3546 iadd[0] = offs;
3547 }
3548 msg[1].len = pcnt;
3549 msg[1].buf = eeprom+tcnt;
3550 if ((ret = i2c_transfer(&hdw->i2c_adap,
3551 msg,ARRAY_SIZE(msg))) != 2) {
3552 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3553 "eeprom fetch set offs err=%d",ret);
3554 kfree(eeprom);
3555 return NULL;
3556 }
3557 }
3558 return eeprom;
3559}
3560
3561
3562void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
568efaa2 3563 int mode,
4db666cc 3564 int enable_flag)
d855497e
MI		 3565{
3566 int ret;
3567 u16 address;
3568 unsigned int pipe;
3569 LOCK_TAKE(hdw->big_lock); do {
5fa1247a 3570 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
d855497e
MI		 3571
3572 if (!enable_flag) {
3573 pvr2_trace(PVR2_TRACE_FIRMWARE,
3574 "Cleaning up after CPU firmware fetch");
3575 kfree(hdw->fw_buffer);
a0fd1cb1 3576 hdw->fw_buffer = NULL;
d855497e 3577 hdw->fw_size = 0;
4db666cc
MI		 3578 if (hdw->fw_cpu_flag) {
3579 /* Now release the CPU. It will disconnect
3580 and reconnect later. */
3581 pvr2_hdw_cpureset_assert(hdw,0);
3582 }
d855497e
MI		 3583 break;
3584 }
3585
568efaa2 3586 hdw->fw_cpu_flag = (mode != 2);
4db666cc 3587 if (hdw->fw_cpu_flag) {
568efaa2 3588 hdw->fw_size = (mode == 1) ? 0x4000 : 0x2000;
4db666cc 3589 pvr2_trace(PVR2_TRACE_FIRMWARE,
568efaa2
MI		 3590 "Preparing to suck out CPU firmware"
3591 " (size=%u)", hdw->fw_size);
4db666cc
MI		 3592 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3593 if (!hdw->fw_buffer) {
3594 hdw->fw_size = 0;
3595 break;
3596 }
d855497e 3597
4db666cc
MI		 3598 /* We have to hold the CPU during firmware upload. */
3599 pvr2_hdw_cpureset_assert(hdw,1);
d855497e 3600
4db666cc
MI		 3601 /* download the firmware from address 0000-1fff in 2048
3602 (=0x800) bytes chunk. */
d855497e 3603
4db666cc
MI		 3604 pvr2_trace(PVR2_TRACE_FIRMWARE,
3605 "Grabbing CPU firmware");
3606 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3607 for(address = 0; address < hdw->fw_size;
3608 address += 0x800) {
3609 ret = usb_control_msg(hdw->usb_dev,pipe,
3610 0xa0,0xc0,
3611 address,0,
3612 hdw->fw_buffer+address,
3613 0x800,HZ);
3614 if (ret < 0) break;
3615 }
d855497e 3616
4db666cc
MI		 3617 pvr2_trace(PVR2_TRACE_FIRMWARE,
3618 "Done grabbing CPU firmware");
3619 } else {
3620 pvr2_trace(PVR2_TRACE_FIRMWARE,
3621 "Sucking down EEPROM contents");
3622 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3623 if (!hdw->fw_buffer) {
3624 pvr2_trace(PVR2_TRACE_FIRMWARE,
3625 "EEPROM content suck failed.");
3626 break;
3627 }
3628 hdw->fw_size = EEPROM_SIZE;
3629 pvr2_trace(PVR2_TRACE_FIRMWARE,
3630 "Done sucking down EEPROM contents");
3631 }
d855497e
MI		 3632
3633 } while (0); LOCK_GIVE(hdw->big_lock);
3634}
3635
3636
3637/* Return true if we're in a mode for retrieval CPU firmware */
3638int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3639{
5fa1247a 3640 return hdw->fw_buffer != NULL;
d855497e
MI		 3641}
3642
3643
3644int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3645 char *buf,unsigned int cnt)
3646{
3647 int ret = -EINVAL;
3648 LOCK_TAKE(hdw->big_lock); do {
3649 if (!buf) break;
3650 if (!cnt) break;
3651
3652 if (!hdw->fw_buffer) {
3653 ret = -EIO;
3654 break;
3655 }
3656
3657 if (offs >= hdw->fw_size) {
3658 pvr2_trace(PVR2_TRACE_FIRMWARE,
3659 "Read firmware data offs=%d EOF",
3660 offs);
3661 ret = 0;
3662 break;
3663 }
3664
3665 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3666
3667 memcpy(buf,hdw->fw_buffer+offs,cnt);
3668
3669 pvr2_trace(PVR2_TRACE_FIRMWARE,
3670 "Read firmware data offs=%d cnt=%d",
3671 offs,cnt);
3672 ret = cnt;
3673 } while (0); LOCK_GIVE(hdw->big_lock);
3674
3675 return ret;
3676}
3677
3678
fd5a75fe 3679int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
8079384e 3680 enum pvr2_v4l_type index)
d855497e 3681{
fd5a75fe 3682 switch (index) {
8079384e
MI		 3683 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3684 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3685 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
fd5a75fe
MI		 3686 default: return -1;
3687 }
d855497e
MI		 3688}
3689
3690
2fdf3d9c 3691/* Store a v4l minor device number */
fd5a75fe 3692void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
8079384e 3693 enum pvr2_v4l_type index,int v)
d855497e 3694{
fd5a75fe 3695 switch (index) {
8079384e
MI		 3696 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3697 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3698 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
fd5a75fe
MI		 3699 default: break;
3700 }
d855497e
MI		 3701}
3702
3703
7d12e780 3704static void pvr2_ctl_write_complete(struct urb *urb)
d855497e
MI		 3705{
3706 struct pvr2_hdw *hdw = urb->context;
3707 hdw->ctl_write_pend_flag = 0;
3708 if (hdw->ctl_read_pend_flag) return;
3709 complete(&hdw->ctl_done);
3710}
3711
3712
7d12e780 3713static void pvr2_ctl_read_complete(struct urb *urb)
d855497e
MI		 3714{
3715 struct pvr2_hdw *hdw = urb->context;
3716 hdw->ctl_read_pend_flag = 0;
3717 if (hdw->ctl_write_pend_flag) return;
3718 complete(&hdw->ctl_done);
3719}
3720
3721
3722static void pvr2_ctl_timeout(unsigned long data)
3723{
3724 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3725 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3726 hdw->ctl_timeout_flag = !0;
5e55d2ce 3727 if (hdw->ctl_write_pend_flag)
d855497e 3728 usb_unlink_urb(hdw->ctl_write_urb);
5e55d2ce 3729 if (hdw->ctl_read_pend_flag)
d855497e 3730 usb_unlink_urb(hdw->ctl_read_urb);
d855497e
MI		 3731 }
3732}
3733
3734
e61b6fc5
MI		 3735/* Issue a command and get a response from the device. This extended
3736 version includes a probe flag (which if set means that device errors
3737 should not be logged or treated as fatal) and a timeout in jiffies.
3738 This can be used to non-lethally probe the health of endpoint 1. */
07e337ee
AB		 3739static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3740 unsigned int timeout,int probe_fl,
3741 void *write_data,unsigned int write_len,
3742 void *read_data,unsigned int read_len)
d855497e
MI		 3743{
3744 unsigned int idx;
3745 int status = 0;
3746 struct timer_list timer;
3747 if (!hdw->ctl_lock_held) {
3748 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3749 "Attempted to execute control transfer"
3750 " without lock!!");
3751 return -EDEADLK;
3752 }
681c7399 3753 if (!hdw->flag_ok && !probe_fl) {
d855497e
MI		 3754 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3755 "Attempted to execute control transfer"
3756 " when device not ok");
3757 return -EIO;
3758 }
3759 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3760 if (!probe_fl) {
3761 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3762 "Attempted to execute control transfer"
3763 " when USB is disconnected");
3764 }
3765 return -ENOTTY;
3766 }
3767
3768 /* Ensure that we have sane parameters */
3769 if (!write_data) write_len = 0;
3770 if (!read_data) read_len = 0;
3771 if (write_len > PVR2_CTL_BUFFSIZE) {
3772 pvr2_trace(
3773 PVR2_TRACE_ERROR_LEGS,
3774 "Attempted to execute %d byte"
3775 " control-write transfer (limit=%d)",
3776 write_len,PVR2_CTL_BUFFSIZE);
3777 return -EINVAL;
3778 }
3779 if (read_len > PVR2_CTL_BUFFSIZE) {
3780 pvr2_trace(
3781 PVR2_TRACE_ERROR_LEGS,
3782 "Attempted to execute %d byte"
3783 " control-read transfer (limit=%d)",
3784 write_len,PVR2_CTL_BUFFSIZE);
3785 return -EINVAL;
3786 }
3787 if ((!write_len) && (!read_len)) {
3788 pvr2_trace(
3789 PVR2_TRACE_ERROR_LEGS,
3790 "Attempted to execute null control transfer?");
3791 return -EINVAL;
3792 }
3793
3794
3795 hdw->cmd_debug_state = 1;
3796 if (write_len) {
3797 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3798 } else {
3799 hdw->cmd_debug_code = 0;
3800 }
3801 hdw->cmd_debug_write_len = write_len;
3802 hdw->cmd_debug_read_len = read_len;
3803
3804 /* Initialize common stuff */
3805 init_completion(&hdw->ctl_done);
3806 hdw->ctl_timeout_flag = 0;
3807 hdw->ctl_write_pend_flag = 0;
3808 hdw->ctl_read_pend_flag = 0;
3809 init_timer(&timer);
3810 timer.expires = jiffies + timeout;
3811 timer.data = (unsigned long)hdw;
3812 timer.function = pvr2_ctl_timeout;
3813
3814 if (write_len) {
3815 hdw->cmd_debug_state = 2;
3816 /* Transfer write data to internal buffer */
3817 for (idx = 0; idx < write_len; idx++) {
3818 hdw->ctl_write_buffer[idx] =
3819 ((unsigned char *)write_data)[idx];
3820 }
3821 /* Initiate a write request */
3822 usb_fill_bulk_urb(hdw->ctl_write_urb,
3823 hdw->usb_dev,
3824 usb_sndbulkpipe(hdw->usb_dev,
3825 PVR2_CTL_WRITE_ENDPOINT),
3826 hdw->ctl_write_buffer,
3827 write_len,
3828 pvr2_ctl_write_complete,
3829 hdw);
3830 hdw->ctl_write_urb->actual_length = 0;
3831 hdw->ctl_write_pend_flag = !0;
3832 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3833 if (status < 0) {
3834 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3835 "Failed to submit write-control"
3836 " URB status=%d",status);
3837 hdw->ctl_write_pend_flag = 0;
3838 goto done;
3839 }
3840 }
3841
3842 if (read_len) {
3843 hdw->cmd_debug_state = 3;
3844 memset(hdw->ctl_read_buffer,0x43,read_len);
3845 /* Initiate a read request */
3846 usb_fill_bulk_urb(hdw->ctl_read_urb,
3847 hdw->usb_dev,
3848 usb_rcvbulkpipe(hdw->usb_dev,
3849 PVR2_CTL_READ_ENDPOINT),
3850 hdw->ctl_read_buffer,
3851 read_len,
3852 pvr2_ctl_read_complete,
3853 hdw);
3854 hdw->ctl_read_urb->actual_length = 0;
3855 hdw->ctl_read_pend_flag = !0;
3856 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3857 if (status < 0) {
3858 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3859 "Failed to submit read-control"
3860 " URB status=%d",status);
3861 hdw->ctl_read_pend_flag = 0;
3862 goto done;
3863 }
3864 }
3865
3866 /* Start timer */
3867 add_timer(&timer);
3868
3869 /* Now wait for all I/O to complete */
3870 hdw->cmd_debug_state = 4;
3871 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3872 wait_for_completion(&hdw->ctl_done);
3873 }
3874 hdw->cmd_debug_state = 5;
3875
3876 /* Stop timer */
3877 del_timer_sync(&timer);
3878
3879 hdw->cmd_debug_state = 6;
3880 status = 0;
3881
3882 if (hdw->ctl_timeout_flag) {
3883 status = -ETIMEDOUT;
3884 if (!probe_fl) {
3885 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3886 "Timed out control-write");
3887 }
3888 goto done;
3889 }
3890
3891 if (write_len) {
3892 /* Validate results of write request */
3893 if ((hdw->ctl_write_urb->status != 0) &&
3894 (hdw->ctl_write_urb->status != -ENOENT) &&
3895 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3896 (hdw->ctl_write_urb->status != -ECONNRESET)) {
3897 /* USB subsystem is reporting some kind of failure
3898 on the write */
3899 status = hdw->ctl_write_urb->status;
3900 if (!probe_fl) {
3901 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3902 "control-write URB failure,"
3903 " status=%d",
3904 status);
3905 }
3906 goto done;
3907 }
3908 if (hdw->ctl_write_urb->actual_length < write_len) {
3909 /* Failed to write enough data */
3910 status = -EIO;
3911 if (!probe_fl) {
3912 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3913 "control-write URB short,"
3914 " expected=%d got=%d",
3915 write_len,
3916 hdw->ctl_write_urb->actual_length);
3917 }
3918 goto done;
3919 }
3920 }
3921 if (read_len) {
3922 /* Validate results of read request */
3923 if ((hdw->ctl_read_urb->status != 0) &&
3924 (hdw->ctl_read_urb->status != -ENOENT) &&
3925 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3926 (hdw->ctl_read_urb->status != -ECONNRESET)) {
3927 /* USB subsystem is reporting some kind of failure
3928 on the read */
3929 status = hdw->ctl_read_urb->status;
3930 if (!probe_fl) {
3931 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3932 "control-read URB failure,"
3933 " status=%d",
3934 status);
3935 }
3936 goto done;
3937 }
3938 if (hdw->ctl_read_urb->actual_length < read_len) {
3939 /* Failed to read enough data */
3940 status = -EIO;
3941 if (!probe_fl) {
3942 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3943 "control-read URB short,"
3944 " expected=%d got=%d",
3945 read_len,
3946 hdw->ctl_read_urb->actual_length);
3947 }
3948 goto done;
3949 }
3950 /* Transfer retrieved data out from internal buffer */
3951 for (idx = 0; idx < read_len; idx++) {
3952 ((unsigned char *)read_data)[idx] =
3953 hdw->ctl_read_buffer[idx];
3954 }
3955 }
3956
3957 done:
3958
3959 hdw->cmd_debug_state = 0;
3960 if ((status < 0) && (!probe_fl)) {
681c7399 3961 pvr2_hdw_render_useless(hdw);
d855497e
MI		 3962 }
3963 return status;
3964}
3965
3966
3967int pvr2_send_request(struct pvr2_hdw *hdw,
3968 void *write_data,unsigned int write_len,
3969 void *read_data,unsigned int read_len)
3970{
3971 return pvr2_send_request_ex(hdw,HZ*4,0,
3972 write_data,write_len,
3973 read_data,read_len);
3974}
3975
1c9d10d4
MI		 3976
3977static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3978{
3979 int ret;
3980 unsigned int cnt = 1;
3981 unsigned int args = 0;
3982 LOCK_TAKE(hdw->ctl_lock);
3983 hdw->cmd_buffer[0] = cmdcode & 0xffu;
3984 args = (cmdcode >> 8) & 0xffu;
3985 args = (args > 2) ? 2 : args;
3986 if (args) {
3987 cnt += args;
3988 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3989 if (args > 1) {
3990 hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3991 }
3992 }
3993 if (pvrusb2_debug & PVR2_TRACE_INIT) {
3994 unsigned int idx;
3995 unsigned int ccnt,bcnt;
3996 char tbuf[50];
3997 cmdcode &= 0xffu;
3998 bcnt = 0;
3999 ccnt = scnprintf(tbuf+bcnt,
4000 sizeof(tbuf)-bcnt,
4001 "Sending FX2 command 0x%x",cmdcode);
4002 bcnt += ccnt;
4003 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
4004 if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
4005 ccnt = scnprintf(tbuf+bcnt,
4006 sizeof(tbuf)-bcnt,
4007 " \"%s\"",
4008 pvr2_fx2cmd_desc[idx].desc);
4009 bcnt += ccnt;
4010 break;
4011 }
4012 }
4013 if (args) {
4014 ccnt = scnprintf(tbuf+bcnt,
4015 sizeof(tbuf)-bcnt,
4016 " (%u",hdw->cmd_buffer[1]);
4017 bcnt += ccnt;
4018 if (args > 1) {
4019 ccnt = scnprintf(tbuf+bcnt,
4020 sizeof(tbuf)-bcnt,
4021 ",%u",hdw->cmd_buffer[2]);
4022 bcnt += ccnt;
4023 }
4024 ccnt = scnprintf(tbuf+bcnt,
4025 sizeof(tbuf)-bcnt,
4026 ")");
4027 bcnt += ccnt;
4028 }
4029 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
4030 }
4031 ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
4032 LOCK_GIVE(hdw->ctl_lock);
4033 return ret;
4034}
4035
4036
d855497e
MI		 4037int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
4038{
4039 int ret;
4040
4041 LOCK_TAKE(hdw->ctl_lock);
4042
8d364363 4043 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
d855497e
MI		 4044 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
4045 hdw->cmd_buffer[5] = 0;
4046 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4047 hdw->cmd_buffer[7] = reg & 0xff;
4048
4049
4050 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
4051
4052 LOCK_GIVE(hdw->ctl_lock);
4053
4054 return ret;
4055}
4056
4057
07e337ee 4058static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
d855497e
MI		 4059{
4060 int ret = 0;
4061
4062 LOCK_TAKE(hdw->ctl_lock);
4063
8d364363 4064 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
d855497e
MI		 4065 hdw->cmd_buffer[1] = 0;
4066 hdw->cmd_buffer[2] = 0;
4067 hdw->cmd_buffer[3] = 0;
4068 hdw->cmd_buffer[4] = 0;
4069 hdw->cmd_buffer[5] = 0;
4070 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4071 hdw->cmd_buffer[7] = reg & 0xff;
4072
4073 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
4074 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
4075
4076 LOCK_GIVE(hdw->ctl_lock);
4077
4078 return ret;
4079}
4080
4081
681c7399 4082void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
d855497e
MI		 4083{
4084 if (!hdw->flag_ok) return;
681c7399
MI		 4085 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4086 "Device being rendered inoperable");
d855497e 4087 if (hdw->vid_stream) {
a0fd1cb1 4088 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
d855497e 4089 }
681c7399
MI		 4090 hdw->flag_ok = 0;
4091 trace_stbit("flag_ok",hdw->flag_ok);
4092 pvr2_hdw_state_sched(hdw);
d855497e
MI		 4093}
4094
4095
4096void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
4097{
4098 int ret;
4099 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
a0fd1cb1 4100 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
011b15df 4101 if (ret == 0) {
d855497e
MI		 4102 ret = usb_reset_device(hdw->usb_dev);
4103 usb_unlock_device(hdw->usb_dev);
4104 } else {
4105 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4106 "Failed to lock USB device ret=%d",ret);
4107 }
4108 if (init_pause_msec) {
4109 pvr2_trace(PVR2_TRACE_INFO,
4110 "Waiting %u msec for hardware to settle",
4111 init_pause_msec);
4112 msleep(init_pause_msec);
4113 }
4114
4115}
4116
4117
4118void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
4119{
6861800c 4120 char *da;
d855497e
MI		 4121 unsigned int pipe;
4122 int ret;
4123
4124 if (!hdw->usb_dev) return;
4125
6861800c
MI		 4126 da = kmalloc(16, GFP_KERNEL);
4127
4128 if (da == NULL) {
4129 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4130 "Unable to allocate memory to control CPU reset");
4131 return;
4132 }
4133
d855497e
MI		 4134 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4135
4136 da[0] = val ? 0x01 : 0x00;
4137
4138 /* Write the CPUCS register on the 8051. The lsb of the register
4139 is the reset bit; a 1 asserts reset while a 0 clears it. */
4140 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4141 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4142 if (ret < 0) {
4143 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4144 "cpureset_assert(%d) error=%d",val,ret);
4145 pvr2_hdw_render_useless(hdw);
4146 }
6861800c
MI		 4147
4148 kfree(da);
d855497e
MI		 4149}
4150
4151
4152int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4153{
1c9d10d4 4154 return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
d855497e
MI		 4155}
4156
4157
e1edb19a
MK		 4158int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4159{
1c9d10d4 4160 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
e1edb19a
MK		 4161}
4162
1c9d10d4 4163
e1edb19a
MK		 4164int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4165{
1c9d10d4 4166 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
e1edb19a
MK		 4167}
4168
d855497e
MI		 4169
4170int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4171{
af78e16b
MI		 4172 pvr2_trace(PVR2_TRACE_INIT,
4173 "Requesting decoder reset");
af78e16b
MI		 4174 if (hdw->decoder_client_id) {
4175 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4176 core, reset, 0);
e17d787c 4177 pvr2_hdw_cx25840_vbi_hack(hdw);
af78e16b 4178 return 0;
d855497e 4179 }
d855497e 4180 pvr2_trace(PVR2_TRACE_INIT,
af78e16b
MI		 4181 "Unable to reset decoder: nothing attached");
4182 return -ENOTTY;
d855497e
MI		 4183}
4184
4185
62433e31 4186static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
84147f3d 4187{
1c9d10d4
MI		 4188 hdw->flag_ok = !0;
4189 return pvr2_issue_simple_cmd(hdw,
4190 FX2CMD_HCW_DEMOD_RESETIN |
4191 (1 << 8) |
4192 ((onoff ? 1 : 0) << 16));
84147f3d
MI		 4193}
4194
84147f3d 4195
62433e31 4196static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
84147f3d 4197{
1c9d10d4
MI		 4198 hdw->flag_ok = !0;
4199 return pvr2_issue_simple_cmd(hdw,(onoff ?
4200 FX2CMD_ONAIR_DTV_POWER_ON :
4201 FX2CMD_ONAIR_DTV_POWER_OFF));
84147f3d
MI		 4202}
4203
62433e31
MI		 4204
4205static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4206 int onoff)
84147f3d 4207{
1c9d10d4
MI		 4208 return pvr2_issue_simple_cmd(hdw,(onoff ?
4209 FX2CMD_ONAIR_DTV_STREAMING_ON :
4210 FX2CMD_ONAIR_DTV_STREAMING_OFF));
84147f3d
MI		 4211}
4212
62433e31
MI		 4213
4214static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4215{
4216 int cmode;
4217 /* Compare digital/analog desired setting with current setting. If
4218 they don't match, fix it... */
4219 cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4220 if (cmode == hdw->pathway_state) {
4221 /* They match; nothing to do */
4222 return;
4223 }
4224
4225 switch (hdw->hdw_desc->digital_control_scheme) {
4226 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4227 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4228 if (cmode == PVR2_PATHWAY_ANALOG) {
4229 /* If moving to analog mode, also force the decoder
4230 to reset. If no decoder is attached, then it's
4231 ok to ignore this because if/when the decoder
4232 attaches, it will reset itself at that time. */
4233 pvr2_hdw_cmd_decoder_reset(hdw);
4234 }
4235 break;
4236 case PVR2_DIGITAL_SCHEME_ONAIR:
4237 /* Supposedly we should always have the power on whether in
4238 digital or analog mode. But for now do what appears to
4239 work... */
bb0c2fe0 4240 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
62433e31
MI		 4241 break;
4242 default: break;
4243 }
4244
1b9c18c5 4245 pvr2_hdw_untrip_unlocked(hdw);
62433e31
MI		 4246 hdw->pathway_state = cmode;
4247}
4248
4249
e9b59f6e 4250static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
c55a97d7
MI		 4251{
4252 /* change some GPIO data
4253 *
4254 * note: bit d7 of dir appears to control the LED,
4255 * so we shut it off here.
4256 *
c55a97d7 4257 */
40381cb0 4258 if (onoff) {
c55a97d7 4259 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
40381cb0 4260 } else {
c55a97d7 4261 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
40381cb0 4262 }
c55a97d7 4263 pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
40381cb0 4264}
c55a97d7 4265
40381cb0
MI		 4266
4267typedef void (*led_method_func)(struct pvr2_hdw *,int);
4268
4269static led_method_func led_methods[] = {
4270 [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4271};
4272
4273
4274/* Toggle LED */
4275static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4276{
4277 unsigned int scheme_id;
4278 led_method_func fp;
4279
4280 if ((!onoff) == (!hdw->led_on)) return;
4281
4282 hdw->led_on = onoff != 0;
4283
4284 scheme_id = hdw->hdw_desc->led_scheme;
4285 if (scheme_id < ARRAY_SIZE(led_methods)) {
4286 fp = led_methods[scheme_id];
4287 } else {
4288 fp = NULL;
4289 }
4290
4291 if (fp) (*fp)(hdw,onoff);
c55a97d7
MI		 4292}
4293
4294
e61b6fc5 4295/* Stop / start video stream transport */
07e337ee 4296static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
d855497e 4297{
bb0c2fe0
MI		 4298 int ret;
4299
4300 /* If we're in analog mode, then just issue the usual analog
4301 command. */
4302 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4303 return pvr2_issue_simple_cmd(hdw,
4304 (runFl ?
4305 FX2CMD_STREAMING_ON :
4306 FX2CMD_STREAMING_OFF));
4307 /*Note: Not reached */
4308 }
4309
4310 if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4311 /* Whoops, we don't know what mode we're in... */
4312 return -EINVAL;
4313 }
4314
4315 /* To get here we have to be in digital mode. The mechanism here
4316 is unfortunately different for different vendors. So we switch
4317 on the device's digital scheme attribute in order to figure out
4318 what to do. */
4319 switch (hdw->hdw_desc->digital_control_scheme) {
4320 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4321 return pvr2_issue_simple_cmd(hdw,
4322 (runFl ?
4323 FX2CMD_HCW_DTV_STREAMING_ON :
4324 FX2CMD_HCW_DTV_STREAMING_OFF));
4325 case PVR2_DIGITAL_SCHEME_ONAIR:
4326 ret = pvr2_issue_simple_cmd(hdw,
4327 (runFl ?
4328 FX2CMD_STREAMING_ON :
4329 FX2CMD_STREAMING_OFF));
4330 if (ret) return ret;
4331 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4332 default:
4333 return -EINVAL;
62433e31 4334 }
d855497e
MI		 4335}
4336
4337
62433e31
MI		 4338/* Evaluate whether or not state_pathway_ok can change */
4339static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4340{
4341 if (hdw->state_pathway_ok) {
4342 /* Nothing to do if pathway is already ok */
4343 return 0;
4344 }
4345 if (!hdw->state_pipeline_idle) {
4346 /* Not allowed to change anything if pipeline is not idle */
4347 return 0;
4348 }
4349 pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4350 hdw->state_pathway_ok = !0;
e9db1ff2 4351 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 4352 return !0;
4353}
4354
4355
681c7399
MI		 4356/* Evaluate whether or not state_encoder_ok can change */
4357static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4358{
4359 if (hdw->state_encoder_ok) return 0;
4360 if (hdw->flag_tripped) return 0;
4361 if (hdw->state_encoder_run) return 0;
4362 if (hdw->state_encoder_config) return 0;
4363 if (hdw->state_decoder_run) return 0;
4364 if (hdw->state_usbstream_run) return 0;
72998b71
MI		 4365 if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4366 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4367 } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4368 return 0;
4369 }
4370
681c7399
MI		 4371 if (pvr2_upload_firmware2(hdw) < 0) {
4372 hdw->flag_tripped = !0;
4373 trace_stbit("flag_tripped",hdw->flag_tripped);
4374 return !0;
4375 }
4376 hdw->state_encoder_ok = !0;
4377 trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4378 return !0;
4379}
4380
4381
4382/* Evaluate whether or not state_encoder_config can change */
4383static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4384{
4385 if (hdw->state_encoder_config) {
4386 if (hdw->state_encoder_ok) {
4387 if (hdw->state_pipeline_req &&
4388 !hdw->state_pipeline_pause) return 0;
4389 }
4390 hdw->state_encoder_config = 0;
4391 hdw->state_encoder_waitok = 0;
4392 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4393 /* paranoia - solve race if timer just completed */
4394 del_timer_sync(&hdw->encoder_wait_timer);
4395 } else {
62433e31
MI		 4396 if (!hdw->state_pathway_ok ||
4397 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4398 !hdw->state_encoder_ok ||
681c7399
MI		 4399 !hdw->state_pipeline_idle ||
4400 hdw->state_pipeline_pause ||
4401 !hdw->state_pipeline_req ||
4402 !hdw->state_pipeline_config) {
4403 /* We must reset the enforced wait interval if
4404 anything has happened that might have disturbed
4405 the encoder. This should be a rare case. */
4406 if (timer_pending(&hdw->encoder_wait_timer)) {
4407 del_timer_sync(&hdw->encoder_wait_timer);
4408 }
4409 if (hdw->state_encoder_waitok) {
4410 /* Must clear the state - therefore we did
4411 something to a state bit and must also
4412 return true. */
4413 hdw->state_encoder_waitok = 0;
4414 trace_stbit("state_encoder_waitok",
4415 hdw->state_encoder_waitok);
4416 return !0;
4417 }
4418 return 0;
4419 }
4420 if (!hdw->state_encoder_waitok) {
4421 if (!timer_pending(&hdw->encoder_wait_timer)) {
4422 /* waitok flag wasn't set and timer isn't
4423 running. Check flag once more to avoid
4424 a race then start the timer. This is
4425 the point when we measure out a minimal
4426 quiet interval before doing something to
4427 the encoder. */
4428 if (!hdw->state_encoder_waitok) {
4429 hdw->encoder_wait_timer.expires =
83ce57aa
MI		 4430 jiffies +
4431 (HZ * TIME_MSEC_ENCODER_WAIT
4432 / 1000);
681c7399
MI		 4433 add_timer(&hdw->encoder_wait_timer);
4434 }
4435 }
4436 /* We can't continue until we know we have been
4437 quiet for the interval measured by this
4438 timer. */
4439 return 0;
4440 }
4441 pvr2_encoder_configure(hdw);
4442 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4443 }
4444 trace_stbit("state_encoder_config",hdw->state_encoder_config);
4445 return !0;
4446}
4447
4448
d913d630
MI		 4449/* Return true if the encoder should not be running. */
4450static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4451{
4452 if (!hdw->state_encoder_ok) {
4453 /* Encoder isn't healthy at the moment, so stop it. */
4454 return !0;
4455 }
4456 if (!hdw->state_pathway_ok) {
4457 /* Mode is not understood at the moment (i.e. it wants to
4458 change), so encoder must be stopped. */
4459 return !0;
4460 }
4461
4462 switch (hdw->pathway_state) {
4463 case PVR2_PATHWAY_ANALOG:
4464 if (!hdw->state_decoder_run) {
4465 /* We're in analog mode and the decoder is not
4466 running; thus the encoder should be stopped as
4467 well. */
4468 return !0;
4469 }
4470 break;
4471 case PVR2_PATHWAY_DIGITAL:
4472 if (hdw->state_encoder_runok) {
4473 /* This is a funny case. We're in digital mode so
4474 really the encoder should be stopped. However
4475 if it really is running, only kill it after
4476 runok has been set. This gives a chance for the
4477 onair quirk to function (encoder must run
4478 briefly first, at least once, before onair
4479 digital streaming can work). */
4480 return !0;
4481 }
4482 break;
4483 default:
4484 /* Unknown mode; so encoder should be stopped. */
4485 return !0;
4486 }
4487
4488 /* If we get here, we haven't found a reason to stop the
4489 encoder. */
4490 return 0;
4491}
4492
4493
4494/* Return true if the encoder should be running. */
4495static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4496{
4497 if (!hdw->state_encoder_ok) {
4498 /* Don't run the encoder if it isn't healthy... */
4499 return 0;
4500 }
4501 if (!hdw->state_pathway_ok) {
4502 /* Don't run the encoder if we don't (yet) know what mode
4503 we need to be in... */
4504 return 0;
4505 }
4506
4507 switch (hdw->pathway_state) {
4508 case PVR2_PATHWAY_ANALOG:
6e931375 4509 if (hdw->state_decoder_run && hdw->state_decoder_ready) {
d913d630
MI		 4510 /* In analog mode, if the decoder is running, then
4511 run the encoder. */
4512 return !0;
4513 }
4514 break;
4515 case PVR2_PATHWAY_DIGITAL:
4516 if ((hdw->hdw_desc->digital_control_scheme ==
4517 PVR2_DIGITAL_SCHEME_ONAIR) &&
4518 !hdw->state_encoder_runok) {
4519 /* This is a quirk. OnAir hardware won't stream
4520 digital until the encoder has been run at least
4521 once, for a minimal period of time (empiricially
4522 measured to be 1/4 second). So if we're on
4523 OnAir hardware and the encoder has never been
4524 run at all, then start the encoder. Normal
4525 state machine logic in the driver will
4526 automatically handle the remaining bits. */
4527 return !0;
4528 }
4529 break;
4530 default:
4531 /* For completeness (unknown mode; encoder won't run ever) */
4532 break;
4533 }
4534 /* If we get here, then we haven't found any reason to run the
4535 encoder, so don't run it. */
4536 return 0;
4537}
4538
4539
681c7399
MI		 4540/* Evaluate whether or not state_encoder_run can change */
4541static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4542{
4543 if (hdw->state_encoder_run) {
d913d630 4544 if (!state_check_disable_encoder_run(hdw)) return 0;
681c7399 4545 if (hdw->state_encoder_ok) {
d913d630 4546 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 4547 if (pvr2_encoder_stop(hdw) < 0) return !0;
4548 }
4549 hdw->state_encoder_run = 0;
4550 } else {
d913d630 4551 if (!state_check_enable_encoder_run(hdw)) return 0;
681c7399
MI		 4552 if (pvr2_encoder_start(hdw) < 0) return !0;
4553 hdw->state_encoder_run = !0;
d913d630
MI		 4554 if (!hdw->state_encoder_runok) {
4555 hdw->encoder_run_timer.expires =
83ce57aa 4556 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
d913d630
MI		 4557 add_timer(&hdw->encoder_run_timer);
4558 }
681c7399
MI		 4559 }
4560 trace_stbit("state_encoder_run",hdw->state_encoder_run);
4561 return !0;
4562}
4563
4564
4565/* Timeout function for quiescent timer. */
4566static void pvr2_hdw_quiescent_timeout(unsigned long data)
4567{
4568 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4569 hdw->state_decoder_quiescent = !0;
4570 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4571 hdw->state_stale = !0;
4572 queue_work(hdw->workqueue,&hdw->workpoll);
4573}
4574
4575
6e931375
MI		 4576/* Timeout function for decoder stabilization timer. */
4577static void pvr2_hdw_decoder_stabilization_timeout(unsigned long data)
4578{
4579 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4580 hdw->state_decoder_ready = !0;
4581 trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4582 hdw->state_stale = !0;
4583 queue_work(hdw->workqueue, &hdw->workpoll);
4584}
4585
4586
681c7399
MI		 4587/* Timeout function for encoder wait timer. */
4588static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4589{
4590 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4591 hdw->state_encoder_waitok = !0;
4592 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4593 hdw->state_stale = !0;
4594 queue_work(hdw->workqueue,&hdw->workpoll);
4595}
4596
4597
d913d630
MI		 4598/* Timeout function for encoder run timer. */
4599static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4600{
4601 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4602 if (!hdw->state_encoder_runok) {
4603 hdw->state_encoder_runok = !0;
4604 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4605 hdw->state_stale = !0;
4606 queue_work(hdw->workqueue,&hdw->workpoll);
4607 }
4608}
4609
4610
681c7399
MI		 4611/* Evaluate whether or not state_decoder_run can change */
4612static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4613{
4614 if (hdw->state_decoder_run) {
4615 if (hdw->state_encoder_ok) {
4616 if (hdw->state_pipeline_req &&
62433e31
MI		 4617 !hdw->state_pipeline_pause &&
4618 hdw->state_pathway_ok) return 0;
681c7399
MI		 4619 }
4620 if (!hdw->flag_decoder_missed) {
4621 pvr2_decoder_enable(hdw,0);
4622 }
4623 hdw->state_decoder_quiescent = 0;
4624 hdw->state_decoder_run = 0;
6e931375 4625 /* paranoia - solve race if timer(s) just completed */
681c7399 4626 del_timer_sync(&hdw->quiescent_timer);
6e931375
MI		 4627 /* Kill the stabilization timer, in case we're killing the
4628 encoder before the previous stabilization interval has
4629 been properly timed. */
4630 del_timer_sync(&hdw->decoder_stabilization_timer);
4631 hdw->state_decoder_ready = 0;
681c7399
MI		 4632 } else {
4633 if (!hdw->state_decoder_quiescent) {
4634 if (!timer_pending(&hdw->quiescent_timer)) {
4635 /* We don't do something about the
4636 quiescent timer until right here because
4637 we also want to catch cases where the
4638 decoder was already not running (like
4639 after initialization) as opposed to
4640 knowing that we had just stopped it.
4641 The second flag check is here to cover a
4642 race - the timer could have run and set
4643 this flag just after the previous check
4644 but before we did the pending check. */
4645 if (!hdw->state_decoder_quiescent) {
4646 hdw->quiescent_timer.expires =
83ce57aa
MI		 4647 jiffies +
4648 (HZ * TIME_MSEC_DECODER_WAIT
4649 / 1000);
681c7399
MI		 4650 add_timer(&hdw->quiescent_timer);
4651 }
4652 }
4653 /* Don't allow decoder to start again until it has
4654 been quiesced first. This little detail should
4655 hopefully further stabilize the encoder. */
4656 return 0;
4657 }
62433e31
MI		 4658 if (!hdw->state_pathway_ok ||
4659 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4660 !hdw->state_pipeline_req ||
681c7399
MI		 4661 hdw->state_pipeline_pause ||
4662 !hdw->state_pipeline_config ||
4663 !hdw->state_encoder_config ||
4664 !hdw->state_encoder_ok) return 0;
4665 del_timer_sync(&hdw->quiescent_timer);
4666 if (hdw->flag_decoder_missed) return 0;
4667 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4668 hdw->state_decoder_quiescent = 0;
6e931375 4669 hdw->state_decoder_ready = 0;
681c7399 4670 hdw->state_decoder_run = !0;
fb640224
MI		 4671 if (hdw->decoder_client_id == PVR2_CLIENT_ID_SAA7115) {
4672 hdw->decoder_stabilization_timer.expires =
4673 jiffies +
4674 (HZ * TIME_MSEC_DECODER_STABILIZATION_WAIT /
4675 1000);
4676 add_timer(&hdw->decoder_stabilization_timer);
4677 } else {
4678 hdw->state_decoder_ready = !0;
4679 }
681c7399
MI		 4680 }
4681 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4682 trace_stbit("state_decoder_run",hdw->state_decoder_run);
6e931375 4683 trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
681c7399
MI		 4684 return !0;
4685}
4686
4687
4688/* Evaluate whether or not state_usbstream_run can change */
4689static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4690{
4691 if (hdw->state_usbstream_run) {
72998b71 4692 int fl = !0;
62433e31 4693 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
72998b71
MI		 4694 fl = (hdw->state_encoder_ok &&
4695 hdw->state_encoder_run);
4696 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4697 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4698 fl = hdw->state_encoder_ok;
4699 }
4700 if (fl &&
4701 hdw->state_pipeline_req &&
4702 !hdw->state_pipeline_pause &&
4703 hdw->state_pathway_ok) {
4704 return 0;
681c7399
MI		 4705 }
4706 pvr2_hdw_cmd_usbstream(hdw,0);
4707 hdw->state_usbstream_run = 0;
4708 } else {
62433e31
MI		 4709 if (!hdw->state_pipeline_req ||
4710 hdw->state_pipeline_pause ||
4711 !hdw->state_pathway_ok) return 0;
4712 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4713 if (!hdw->state_encoder_ok ||
4714 !hdw->state_encoder_run) return 0;
72998b71
MI		 4715 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4716 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4717 if (!hdw->state_encoder_ok) return 0;
d913d630
MI		 4718 if (hdw->state_encoder_run) return 0;
4719 if (hdw->hdw_desc->digital_control_scheme ==
4720 PVR2_DIGITAL_SCHEME_ONAIR) {
4721 /* OnAir digital receivers won't stream
4722 unless the analog encoder has run first.
4723 Why? I have no idea. But don't even
4724 try until we know the analog side is
4725 known to have run. */
4726 if (!hdw->state_encoder_runok) return 0;
4727 }
62433e31 4728 }
681c7399
MI		 4729 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4730 hdw->state_usbstream_run = !0;
4731 }
4732 trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4733 return !0;
4734}
4735
4736
4737/* Attempt to configure pipeline, if needed */
4738static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4739{
4740 if (hdw->state_pipeline_config ||
4741 hdw->state_pipeline_pause) return 0;
4742 pvr2_hdw_commit_execute(hdw);
4743 return !0;
4744}
4745
4746
4747/* Update pipeline idle and pipeline pause tracking states based on other
4748 inputs. This must be called whenever the other relevant inputs have
4749 changed. */
4750static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4751{
4752 unsigned int st;
4753 int updatedFl = 0;
4754 /* Update pipeline state */
4755 st = !(hdw->state_encoder_run ||
4756 hdw->state_decoder_run ||
4757 hdw->state_usbstream_run ||
4758 (!hdw->state_decoder_quiescent));
4759 if (!st != !hdw->state_pipeline_idle) {
4760 hdw->state_pipeline_idle = st;
4761 updatedFl = !0;
4762 }
4763 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4764 hdw->state_pipeline_pause = 0;
4765 updatedFl = !0;
4766 }
4767 return updatedFl;
4768}
4769
4770
4771typedef int (*state_eval_func)(struct pvr2_hdw *);
4772
4773/* Set of functions to be run to evaluate various states in the driver. */
ebff0330 4774static const state_eval_func eval_funcs[] = {
62433e31 4775 state_eval_pathway_ok,
681c7399
MI		 4776 state_eval_pipeline_config,
4777 state_eval_encoder_ok,
4778 state_eval_encoder_config,
4779 state_eval_decoder_run,
4780 state_eval_encoder_run,
4781 state_eval_usbstream_run,
4782};
4783
4784
4785/* Process various states and return true if we did anything interesting. */
4786static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4787{
4788 unsigned int i;
4789 int state_updated = 0;
4790 int check_flag;
4791
4792 if (!hdw->state_stale) return 0;
4793 if ((hdw->fw1_state != FW1_STATE_OK) ||
4794 !hdw->flag_ok) {
4795 hdw->state_stale = 0;
4796 return !0;
4797 }
4798 /* This loop is the heart of the entire driver. It keeps trying to
4799 evaluate various bits of driver state until nothing changes for
4800 one full iteration. Each "bit of state" tracks some global
4801 aspect of the driver, e.g. whether decoder should run, if
4802 pipeline is configured, usb streaming is on, etc. We separately
4803 evaluate each of those questions based on other driver state to
4804 arrive at the correct running configuration. */
4805 do {
4806 check_flag = 0;
4807 state_update_pipeline_state(hdw);
4808 /* Iterate over each bit of state */
4809 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4810 if ((*eval_funcs[i])(hdw)) {
4811 check_flag = !0;
4812 state_updated = !0;
4813 state_update_pipeline_state(hdw);
4814 }
4815 }
4816 } while (check_flag && hdw->flag_ok);
4817 hdw->state_stale = 0;
4818 trace_stbit("state_stale",hdw->state_stale);
4819 return state_updated;
4820}
4821
4822
1cb03b76
MI		 4823static unsigned int print_input_mask(unsigned int msk,
4824 char *buf,unsigned int acnt)
4825{
4826 unsigned int idx,ccnt;
4827 unsigned int tcnt = 0;
4828 for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4829 if (!((1 << idx) & msk)) continue;
4830 ccnt = scnprintf(buf+tcnt,
4831 acnt-tcnt,
4832 "%s%s",
4833 (tcnt ? ", " : ""),
4834 control_values_input[idx]);
4835 tcnt += ccnt;
4836 }
4837 return tcnt;
4838}
4839
4840
62433e31
MI		 4841static const char *pvr2_pathway_state_name(int id)
4842{
4843 switch (id) {
4844 case PVR2_PATHWAY_ANALOG: return "analog";
4845 case PVR2_PATHWAY_DIGITAL: return "digital";
4846 default: return "unknown";
4847 }
4848}
4849
4850
681c7399
MI		 4851static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4852 char *buf,unsigned int acnt)
4853{
4854 switch (which) {
4855 case 0:
4856 return scnprintf(
4857 buf,acnt,
e9db1ff2 4858 "driver:%s%s%s%s%s <mode=%s>",
681c7399
MI		 4859 (hdw->flag_ok ? " <ok>" : " <fail>"),
4860 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4861 (hdw->flag_disconnected ? " <disconnected>" :
4862 " <connected>"),
4863 (hdw->flag_tripped ? " <tripped>" : ""),
62433e31
MI		 4864 (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4865 pvr2_pathway_state_name(hdw->pathway_state));
4866
681c7399
MI		 4867 case 1:
4868 return scnprintf(
4869 buf,acnt,
4870 "pipeline:%s%s%s%s",
4871 (hdw->state_pipeline_idle ? " <idle>" : ""),
4872 (hdw->state_pipeline_config ?
4873 " <configok>" : " <stale>"),
4874 (hdw->state_pipeline_req ? " <req>" : ""),
4875 (hdw->state_pipeline_pause ? " <pause>" : ""));
4876 case 2:
4877 return scnprintf(
4878 buf,acnt,
62433e31 4879 "worker:%s%s%s%s%s%s%s",
681c7399 4880 (hdw->state_decoder_run ?
6e931375
MI		 4881 (hdw->state_decoder_ready ?
4882 "<decode:run>" : " <decode:start>") :
681c7399
MI		 4883 (hdw->state_decoder_quiescent ?
4884 "" : " <decode:stop>")),
4885 (hdw->state_decoder_quiescent ?
4886 " <decode:quiescent>" : ""),
4887 (hdw->state_encoder_ok ?
4888 "" : " <encode:init>"),
4889 (hdw->state_encoder_run ?
d913d630
MI		 4890 (hdw->state_encoder_runok ?
4891 " <encode:run>" :
4892 " <encode:firstrun>") :
4893 (hdw->state_encoder_runok ?
4894 " <encode:stop>" :
4895 " <encode:virgin>")),
681c7399
MI		 4896 (hdw->state_encoder_config ?
4897 " <encode:configok>" :
4898 (hdw->state_encoder_waitok ?
b9a37d91 4899 "" : " <encode:waitok>")),
681c7399 4900 (hdw->state_usbstream_run ?
62433e31
MI		 4901 " <usb:run>" : " <usb:stop>"),
4902 (hdw->state_pathway_ok ?
e9db1ff2 4903 " <pathway:ok>" : ""));
681c7399
MI		 4904 case 3:
4905 return scnprintf(
4906 buf,acnt,
4907 "state: %s",
4908 pvr2_get_state_name(hdw->master_state));
ad0992e9 4909 case 4: {
1cb03b76
MI		 4910 unsigned int tcnt = 0;
4911 unsigned int ccnt;
4912
4913 ccnt = scnprintf(buf,
4914 acnt,
4915 "Hardware supported inputs: ");
4916 tcnt += ccnt;
4917 tcnt += print_input_mask(hdw->input_avail_mask,
4918 buf+tcnt,
4919 acnt-tcnt);
4920 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4921 ccnt = scnprintf(buf+tcnt,
4922 acnt-tcnt,
4923 "; allowed inputs: ");
4924 tcnt += ccnt;
4925 tcnt += print_input_mask(hdw->input_allowed_mask,
4926 buf+tcnt,
4927 acnt-tcnt);
4928 }
4929 return tcnt;
4930 }
4931 case 5: {
ad0992e9
MI		 4932 struct pvr2_stream_stats stats;
4933 if (!hdw->vid_stream) break;
4934 pvr2_stream_get_stats(hdw->vid_stream,
4935 &stats,
4936 0);
4937 return scnprintf(
4938 buf,acnt,
4939 "Bytes streamed=%u"
4940 " URBs: queued=%u idle=%u ready=%u"
4941 " processed=%u failed=%u",
4942 stats.bytes_processed,
4943 stats.buffers_in_queue,
4944 stats.buffers_in_idle,
4945 stats.buffers_in_ready,
4946 stats.buffers_processed,
4947 stats.buffers_failed);
4948 }
27eab384
MI		 4949 case 6: {
4950 unsigned int id = hdw->ir_scheme_active;
4951 return scnprintf(buf, acnt, "ir scheme: id=%d %s", id,
4952 (id >= ARRAY_SIZE(ir_scheme_names) ?
4953 "?" : ir_scheme_names[id]));
4954 }
2eb563b7
MI		 4955 default: break;
4956 }
4957 return 0;
4958}
4959
4960
4961/* Generate report containing info about attached sub-devices and attached
4962 i2c clients, including an indication of which attached i2c clients are
4963 actually sub-devices. */
4964static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
4965 char *buf, unsigned int acnt)
4966{
4967 struct v4l2_subdev *sd;
4968 unsigned int tcnt = 0;
4969 unsigned int ccnt;
4970 struct i2c_client *client;
2eb563b7
MI		 4971 const char *p;
4972 unsigned int id;
4973
fa7ce764 4974 ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n");
2eb563b7
MI		 4975 tcnt += ccnt;
4976 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4977 id = sd->grp_id;
4978 p = NULL;
4979 if (id < ARRAY_SIZE(module_names)) p = module_names[id];
4980 if (p) {
fa7ce764 4981 ccnt = scnprintf(buf + tcnt, acnt - tcnt, " %s:", p);
2eb563b7
MI		 4982 tcnt += ccnt;
4983 } else {
4984 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
fa7ce764 4985 " (unknown id=%u):", id);
2eb563b7
MI		 4986 tcnt += ccnt;
4987 }
fa7ce764
JD		 4988 client = v4l2_get_subdevdata(sd);
4989 if (client) {
4990 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4991 " %s @ %02x\n", client->name,
4992 client->addr);
4993 tcnt += ccnt;
4994 } else {
4995 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4996 " no i2c client\n");
4997 tcnt += ccnt;
858f910e 4998 }
681c7399 4999 }
2eb563b7 5000 return tcnt;
681c7399
MI		 5001}
5002
5003
5004unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
5005 char *buf,unsigned int acnt)
5006{
5007 unsigned int bcnt,ccnt,idx;
5008 bcnt = 0;
5009 LOCK_TAKE(hdw->big_lock);
5010 for (idx = 0; ; idx++) {
5011 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
5012 if (!ccnt) break;
5013 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
5014 if (!acnt) break;
5015 buf[0] = '\n'; ccnt = 1;
5016 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
5017 }
2eb563b7
MI		 5018 ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
5019 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
681c7399
MI		 5020 LOCK_GIVE(hdw->big_lock);
5021 return bcnt;
5022}
5023
5024
5025static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
5026{
2eb563b7
MI		 5027 char buf[256];
5028 unsigned int idx, ccnt;
5029 unsigned int lcnt, ucnt;
681c7399
MI		 5030
5031 for (idx = 0; ; idx++) {
5032 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
5033 if (!ccnt) break;
5034 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
5035 }
2eb563b7
MI		 5036 ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
5037 ucnt = 0;
5038 while (ucnt < ccnt) {
5039 lcnt = 0;
5040 while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
5041 lcnt++;
5042 }
5043 printk(KERN_INFO "%s %.*s\n", hdw->name, lcnt, buf + ucnt);
5044 ucnt += lcnt + 1;
5045 }
681c7399
MI		 5046}
5047
5048
5049/* Evaluate and update the driver's current state, taking various actions
5050 as appropriate for the update. */
5051static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
5052{
5053 unsigned int st;
5054 int state_updated = 0;
5055 int callback_flag = 0;
1b9c18c5 5056 int analog_mode;
681c7399
MI		 5057
5058 pvr2_trace(PVR2_TRACE_STBITS,
5059 "Drive state check START");
5060 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
5061 pvr2_hdw_state_log_state(hdw);
5062 }
5063
5064 /* Process all state and get back over disposition */
5065 state_updated = pvr2_hdw_state_update(hdw);
5066
1b9c18c5
MI		 5067 analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
5068
681c7399
MI		 5069 /* Update master state based upon all other states. */
5070 if (!hdw->flag_ok) {
5071 st = PVR2_STATE_DEAD;
5072 } else if (hdw->fw1_state != FW1_STATE_OK) {
5073 st = PVR2_STATE_COLD;
72998b71
MI		 5074 } else if ((analog_mode ||
5075 hdw->hdw_desc->flag_digital_requires_cx23416) &&
5076 !hdw->state_encoder_ok) {
681c7399 5077 st = PVR2_STATE_WARM;
1b9c18c5
MI		 5078 } else if (hdw->flag_tripped ||
5079 (analog_mode && hdw->flag_decoder_missed)) {
681c7399 5080 st = PVR2_STATE_ERROR;
62433e31 5081 } else if (hdw->state_usbstream_run &&
1b9c18c5 5082 (!analog_mode ||
62433e31 5083 (hdw->state_encoder_run && hdw->state_decoder_run))) {
681c7399
MI		 5084 st = PVR2_STATE_RUN;
5085 } else {
5086 st = PVR2_STATE_READY;
5087 }
5088 if (hdw->master_state != st) {
5089 pvr2_trace(PVR2_TRACE_STATE,
5090 "Device state change from %s to %s",
5091 pvr2_get_state_name(hdw->master_state),
5092 pvr2_get_state_name(st));
40381cb0 5093 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
681c7399
MI		 5094 hdw->master_state = st;
5095 state_updated = !0;
5096 callback_flag = !0;
5097 }
5098 if (state_updated) {
5099 /* Trigger anyone waiting on any state changes here. */
5100 wake_up(&hdw->state_wait_data);
5101 }
5102
5103 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
5104 pvr2_hdw_state_log_state(hdw);
5105 }
5106 pvr2_trace(PVR2_TRACE_STBITS,
5107 "Drive state check DONE callback=%d",callback_flag);
5108
5109 return callback_flag;
5110}
5111
5112
5113/* Cause kernel thread to check / update driver state */
5114static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
5115{
5116 if (hdw->state_stale) return;
5117 hdw->state_stale = !0;
5118 trace_stbit("state_stale",hdw->state_stale);
5119 queue_work(hdw->workqueue,&hdw->workpoll);
5120}
5121
5122
d855497e
MI		 5123int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
5124{
5125 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
5126}
5127
5128
5129int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
5130{
5131 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
5132}
5133
5134
5135int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
5136{
5137 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
5138}
5139
5140
5141int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
5142{
5143 u32 cval,nval;
5144 int ret;
5145 if (~msk) {
5146 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
5147 if (ret) return ret;
5148 nval = (cval & ~msk) | (val & msk);
5149 pvr2_trace(PVR2_TRACE_GPIO,
5150 "GPIO direction changing 0x%x:0x%x"
5151 " from 0x%x to 0x%x",
5152 msk,val,cval,nval);
5153 } else {
5154 nval = val;
5155 pvr2_trace(PVR2_TRACE_GPIO,
5156 "GPIO direction changing to 0x%x",nval);
5157 }
5158 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5159}
5160
5161
5162int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5163{
5164 u32 cval,nval;
5165 int ret;
5166 if (~msk) {
5167 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5168 if (ret) return ret;
5169 nval = (cval & ~msk) | (val & msk);
5170 pvr2_trace(PVR2_TRACE_GPIO,
5171 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5172 msk,val,cval,nval);
5173 } else {
5174 nval = val;
5175 pvr2_trace(PVR2_TRACE_GPIO,
5176 "GPIO output changing to 0x%x",nval);
5177 }
5178 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5179}
5180
5181
a51f5000
MI		 5182void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5183{
40f07111
MI		 5184 struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5185 memset(vtp, 0, sizeof(*vtp));
50e9efd6
HV		 5186 vtp->type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
5187 V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
2641df36 5188 hdw->tuner_signal_stale = 0;
40f07111
MI		 5189 /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5190 using v4l2-subdev - therefore we can't support that AT ALL right
5191 now. (Of course, no sub-drivers seem to implement it either.
5192 But now it's a a chicken and egg problem...) */
4cfe3319 5193 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner, vtp);
2641df36 5194 pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
40f07111
MI		 5195 " type=%u strength=%u audio=0x%x cap=0x%x"
5196 " low=%u hi=%u",
5197 vtp->type,
5198 vtp->signal, vtp->rxsubchans, vtp->capability,
5199 vtp->rangelow, vtp->rangehigh);
2641df36
MI		 5200
5201 /* We have to do this to avoid getting into constant polling if
5202 there's nobody to answer a poll of cropcap info. */
5203 hdw->cropcap_stale = 0;
a51f5000
MI		 5204}
5205
5206
7fb20fa3
MI		 5207unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5208{
5209 return hdw->input_avail_mask;
5210}
5211
5212
1cb03b76
MI		 5213unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5214{
5215 return hdw->input_allowed_mask;
5216}
5217
5218
5219static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5220{
5221 if (hdw->input_val != v) {
5222 hdw->input_val = v;
5223 hdw->input_dirty = !0;
5224 }
5225
5226 /* Handle side effects - if we switch to a mode that needs the RF
5227 tuner, then select the right frequency choice as well and mark
5228 it dirty. */
5229 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5230 hdw->freqSelector = 0;
5231 hdw->freqDirty = !0;
5232 } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5233 (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5234 hdw->freqSelector = 1;
5235 hdw->freqDirty = !0;
5236 }
5237 return 0;
5238}
5239
5240
5241int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5242 unsigned int change_mask,
5243 unsigned int change_val)
5244{
5245 int ret = 0;
5246 unsigned int nv,m,idx;
5247 LOCK_TAKE(hdw->big_lock);
5248 do {
5249 nv = hdw->input_allowed_mask & ~change_mask;
5250 nv |= (change_val & change_mask);
5251 nv &= hdw->input_avail_mask;
5252 if (!nv) {
5253 /* No legal modes left; return error instead. */
5254 ret = -EPERM;
5255 break;
5256 }
5257 hdw->input_allowed_mask = nv;
5258 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5259 /* Current mode is still in the allowed mask, so
5260 we're done. */
5261 break;
5262 }
5263 /* Select and switch to a mode that is still in the allowed
5264 mask */
5265 if (!hdw->input_allowed_mask) {
5266 /* Nothing legal; give up */
5267 break;
5268 }
5269 m = hdw->input_allowed_mask;
5270 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5271 if (!((1 << idx) & m)) continue;
5272 pvr2_hdw_set_input(hdw,idx);
5273 break;
5274 }
5275 } while (0);
5276 LOCK_GIVE(hdw->big_lock);
5277 return ret;
5278}
5279
5280
e61b6fc5 5281/* Find I2C address of eeprom */
07e337ee 5282static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
d855497e
MI		 5283{
5284 int result;
5285 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 5286 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 5287 result = pvr2_send_request(hdw,
5288 hdw->cmd_buffer,1,
5289 hdw->cmd_buffer,1);
5290 if (result < 0) break;
5291 result = hdw->cmd_buffer[0];
5292 } while(0); LOCK_GIVE(hdw->ctl_lock);
5293 return result;
5294}
5295
5296
32ffa9ae 5297int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
aecde8b5
HV		 5298 struct v4l2_dbg_match *match, u64 reg_id,
5299 int setFl, u64 *val_ptr)
32ffa9ae
MI		 5300{
5301#ifdef CONFIG_VIDEO_ADV_DEBUG
aecde8b5 5302 struct v4l2_dbg_register req;
6d98816f
MI		 5303 int stat = 0;
5304 int okFl = 0;
32ffa9ae 5305
201f5c9c
MI		 5306 if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5307
aecde8b5 5308 req.match = *match;
32ffa9ae
MI		 5309 req.reg = reg_id;
5310 if (setFl) req.val = *val_ptr;
d8f5b9ba
MI		 5311 /* It would be nice to know if a sub-device answered the request */
5312 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5313 if (!setFl) *val_ptr = req.val;
6d98816f
MI		 5314 if (okFl) {
5315 return stat;
5316 }
32ffa9ae
MI		 5317 return -EINVAL;
5318#else
5319 return -ENOSYS;
5320#endif
5321}
5322
5323
d855497e
MI		 5324/*
5325 Stuff for Emacs to see, in order to encourage consistent editing style:
5326 *** Local Variables: ***
5327 *** mode: c ***
5328 *** fill-column: 75 ***
5329 *** tab-width: 8 ***
5330 *** c-basic-offset: 8 ***
5331 *** End: ***
5332 */
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