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V4L/DVB (11191): pvrusb2: Define default I2C address for cx25840 sub-device
[mirror_ubuntu-artful-kernel.git] / drivers / media / video / pvrusb2 / pvrusb2-hdw.c
CommitLineData
d855497e
MI		 1/*
2 *
d855497e
MI		 3 *
4 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 *
19 */
20
21#include <linux/errno.h>
22#include <linux/string.h>
23#include <linux/slab.h>
24#include <linux/firmware.h>
d855497e 25#include <linux/videodev2.h>
32ffa9ae 26#include <media/v4l2-common.h>
75212a02 27#include <media/tuner.h>
d855497e
MI		 28#include "pvrusb2.h"
29#include "pvrusb2-std.h"
30#include "pvrusb2-util.h"
31#include "pvrusb2-hdw.h"
32#include "pvrusb2-i2c-core.h"
59af3367 33#include "pvrusb2-i2c-track.h"
d855497e
MI		 34#include "pvrusb2-tuner.h"
35#include "pvrusb2-eeprom.h"
36#include "pvrusb2-hdw-internal.h"
37#include "pvrusb2-encoder.h"
38#include "pvrusb2-debug.h"
8d364363 39#include "pvrusb2-fx2-cmd.h"
5f6dae80 40#include "pvrusb2-wm8775.h"
6f956512 41#include "pvrusb2-video-v4l.h"
634ba268 42#include "pvrusb2-cx2584x-v4l.h"
76891d65 43#include "pvrusb2-audio.h"
d855497e 44
1bde0289
MI		 45#define TV_MIN_FREQ 55250000L
46#define TV_MAX_FREQ 850000000L
25d8527a 47
83ce57aa
MI		 48/* This defines a minimum interval that the decoder must remain quiet
49 before we are allowed to start it running. */
50#define TIME_MSEC_DECODER_WAIT 50
51
52/* This defines a minimum interval that the encoder must remain quiet
fa98e594
MI		 53 before we are allowed to configure it. I had this originally set to
54 50msec, but Martin Dauskardt <martin.dauskardt@gmx.de> reports that
55 things work better when it's set to 100msec. */
56#define TIME_MSEC_ENCODER_WAIT 100
83ce57aa
MI		 57
58/* This defines the minimum interval that the encoder must successfully run
59 before we consider that the encoder has run at least once since its
60 firmware has been loaded. This measurement is in important for cases
61 where we can't do something until we know that the encoder has been run
62 at least once. */
63#define TIME_MSEC_ENCODER_OK 250
64
a0fd1cb1 65static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
8df0c87c 66static DEFINE_MUTEX(pvr2_unit_mtx);
d855497e 67
ff699e6b 68static int ctlchg;
ff699e6b 69static int procreload;
d855497e
MI		 70static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
71static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
72static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
ff699e6b 73static int init_pause_msec;
d855497e
MI		 74
75module_param(ctlchg, int, S_IRUGO|S_IWUSR);
76MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
77module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
78MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
d855497e
MI		 79module_param(procreload, int, S_IRUGO|S_IWUSR);
80MODULE_PARM_DESC(procreload,
81 "Attempt init failure recovery with firmware reload");
82module_param_array(tuner, int, NULL, 0444);
83MODULE_PARM_DESC(tuner,"specify installed tuner type");
84module_param_array(video_std, int, NULL, 0444);
85MODULE_PARM_DESC(video_std,"specify initial video standard");
86module_param_array(tolerance, int, NULL, 0444);
87MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
88
5a4f5da6
MK		 89/* US Broadcast channel 7 (175.25 MHz) */
90static int default_tv_freq = 175250000L;
91/* 104.3 MHz, a usable FM station for my area */
92static int default_radio_freq = 104300000L;
93
94module_param_named(tv_freq, default_tv_freq, int, 0444);
95MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
96module_param_named(radio_freq, default_radio_freq, int, 0444);
97MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
98
d855497e
MI		 99#define PVR2_CTL_WRITE_ENDPOINT 0x01
100#define PVR2_CTL_READ_ENDPOINT 0x81
101
102#define PVR2_GPIO_IN 0x9008
103#define PVR2_GPIO_OUT 0x900c
104#define PVR2_GPIO_DIR 0x9020
105
106#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
107
108#define PVR2_FIRMWARE_ENDPOINT 0x02
109
110/* size of a firmware chunk */
111#define FIRMWARE_CHUNK_SIZE 0x2000
112
edb9dcb8
MI		 113typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
114 struct v4l2_subdev *);
115
116static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
4ecbc28d 117 [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
6f956512 118 [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
76891d65 119 [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
634ba268 120 [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
edb9dcb8
MI		 121};
122
e9c64a78
MI		 123static const char *module_names[] = {
124 [PVR2_CLIENT_ID_MSP3400] = "msp3400",
125 [PVR2_CLIENT_ID_CX25840] = "cx25840",
126 [PVR2_CLIENT_ID_SAA7115] = "saa7115",
127 [PVR2_CLIENT_ID_TUNER] = "tuner",
128 [PVR2_CLIENT_ID_CS53132A] = "cs53132a",
5f6dae80 129 [PVR2_CLIENT_ID_WM8775] = "wm8775",
e9c64a78
MI		 130};
131
132
133static const unsigned char *module_i2c_addresses[] = {
134 [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
ae111f76 135 [PVR2_CLIENT_ID_WM8775] = "\x1b",
0b467014 136 [PVR2_CLIENT_ID_CX25840] = "\x44",
e9c64a78
MI		 137};
138
139
b30d2441
MI		 140/* Define the list of additional controls we'll dynamically construct based
141 on query of the cx2341x module. */
142struct pvr2_mpeg_ids {
143 const char *strid;
144 int id;
145};
146static const struct pvr2_mpeg_ids mpeg_ids[] = {
147 {
148 .strid = "audio_layer",
149 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
150 },{
151 .strid = "audio_bitrate",
152 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
153 },{
154 /* Already using audio_mode elsewhere :-( */
155 .strid = "mpeg_audio_mode",
156 .id = V4L2_CID_MPEG_AUDIO_MODE,
157 },{
158 .strid = "mpeg_audio_mode_extension",
159 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
160 },{
161 .strid = "audio_emphasis",
162 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
163 },{
164 .strid = "audio_crc",
165 .id = V4L2_CID_MPEG_AUDIO_CRC,
166 },{
167 .strid = "video_aspect",
168 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
169 },{
170 .strid = "video_b_frames",
171 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
172 },{
173 .strid = "video_gop_size",
174 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
175 },{
176 .strid = "video_gop_closure",
177 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
b30d2441
MI		 178 },{
179 .strid = "video_bitrate_mode",
180 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
181 },{
182 .strid = "video_bitrate",
183 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
184 },{
185 .strid = "video_bitrate_peak",
186 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
187 },{
188 .strid = "video_temporal_decimation",
189 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
190 },{
191 .strid = "stream_type",
192 .id = V4L2_CID_MPEG_STREAM_TYPE,
193 },{
194 .strid = "video_spatial_filter_mode",
195 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
196 },{
197 .strid = "video_spatial_filter",
198 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
199 },{
200 .strid = "video_luma_spatial_filter_type",
201 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
202 },{
203 .strid = "video_chroma_spatial_filter_type",
204 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
205 },{
206 .strid = "video_temporal_filter_mode",
207 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
208 },{
209 .strid = "video_temporal_filter",
210 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
211 },{
212 .strid = "video_median_filter_type",
213 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
214 },{
215 .strid = "video_luma_median_filter_top",
216 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
217 },{
218 .strid = "video_luma_median_filter_bottom",
219 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
220 },{
221 .strid = "video_chroma_median_filter_top",
222 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
223 },{
224 .strid = "video_chroma_median_filter_bottom",
225 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
226 }
227};
eca8ebfc 228#define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
c05c0462 229
434449f4 230
d855497e 231static const char *control_values_srate[] = {
434449f4
MI		 232 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
233 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
234 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
d855497e
MI		 235};
236
237
d855497e 238
d855497e
MI		 239static const char *control_values_input[] = {
240 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
29bf5b1d 241 [PVR2_CVAL_INPUT_DTV] = "dtv",
d855497e
MI		 242 [PVR2_CVAL_INPUT_RADIO] = "radio",
243 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
244 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
245};
246
247
248static const char *control_values_audiomode[] = {
249 [V4L2_TUNER_MODE_MONO] = "Mono",
250 [V4L2_TUNER_MODE_STEREO] = "Stereo",
251 [V4L2_TUNER_MODE_LANG1] = "Lang1",
252 [V4L2_TUNER_MODE_LANG2] = "Lang2",
253 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
254};
255
256
257static const char *control_values_hsm[] = {
258 [PVR2_CVAL_HSM_FAIL] = "Fail",
259 [PVR2_CVAL_HSM_HIGH] = "High",
260 [PVR2_CVAL_HSM_FULL] = "Full",
261};
262
263
681c7399
MI		 264static const char *pvr2_state_names[] = {
265 [PVR2_STATE_NONE] = "none",
266 [PVR2_STATE_DEAD] = "dead",
267 [PVR2_STATE_COLD] = "cold",
268 [PVR2_STATE_WARM] = "warm",
269 [PVR2_STATE_ERROR] = "error",
270 [PVR2_STATE_READY] = "ready",
271 [PVR2_STATE_RUN] = "run",
d855497e
MI		 272};
273
681c7399 274
694dca2b 275struct pvr2_fx2cmd_descdef {
1c9d10d4
MI		 276 unsigned char id;
277 unsigned char *desc;
278};
279
694dca2b 280static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
1c9d10d4
MI		 281 {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
282 {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
31335b13 283 {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
1c9d10d4
MI		 284 {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
285 {FX2CMD_REG_WRITE, "write encoder register"},
286 {FX2CMD_REG_READ, "read encoder register"},
287 {FX2CMD_MEMSEL, "encoder memsel"},
288 {FX2CMD_I2C_WRITE, "i2c write"},
289 {FX2CMD_I2C_READ, "i2c read"},
290 {FX2CMD_GET_USB_SPEED, "get USB speed"},
291 {FX2CMD_STREAMING_ON, "stream on"},
292 {FX2CMD_STREAMING_OFF, "stream off"},
293 {FX2CMD_FWPOST1, "fwpost1"},
294 {FX2CMD_POWER_OFF, "power off"},
295 {FX2CMD_POWER_ON, "power on"},
296 {FX2CMD_DEEP_RESET, "deep reset"},
297 {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
298 {FX2CMD_GET_IR_CODE, "get IR code"},
299 {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
300 {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
301 {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
302 {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
303 {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
304 {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
305 {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
306};
307
308
1cb03b76 309static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
681c7399
MI		 310static void pvr2_hdw_state_sched(struct pvr2_hdw *);
311static int pvr2_hdw_state_eval(struct pvr2_hdw *);
1bde0289 312static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
681c7399
MI		 313static void pvr2_hdw_worker_i2c(struct work_struct *work);
314static void pvr2_hdw_worker_poll(struct work_struct *work);
681c7399
MI		 315static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
316static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
317static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
07e337ee 318static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
681c7399 319static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
07e337ee 320static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
07e337ee
AB		 321static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
322static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
681c7399
MI		 323static void pvr2_hdw_quiescent_timeout(unsigned long);
324static void pvr2_hdw_encoder_wait_timeout(unsigned long);
d913d630 325static void pvr2_hdw_encoder_run_timeout(unsigned long);
1c9d10d4 326static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
07e337ee
AB		 327static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
328 unsigned int timeout,int probe_fl,
329 void *write_data,unsigned int write_len,
330 void *read_data,unsigned int read_len);
432907f7 331static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
d855497e 332
681c7399
MI		 333
334static void trace_stbit(const char *name,int val)
335{
336 pvr2_trace(PVR2_TRACE_STBITS,
337 "State bit %s <-- %s",
338 name,(val ? "true" : "false"));
339}
340
d855497e
MI		 341static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
342{
343 struct pvr2_hdw *hdw = cptr->hdw;
344 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
345 *vp = hdw->freqTable[hdw->freqProgSlot-1];
346 } else {
347 *vp = 0;
348 }
349 return 0;
350}
351
352static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
353{
354 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 355 unsigned int slotId = hdw->freqProgSlot;
356 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
357 hdw->freqTable[slotId-1] = v;
358 /* Handle side effects correctly - if we're tuned to this
359 slot, then forgot the slot id relation since the stored
360 frequency has been changed. */
361 if (hdw->freqSelector) {
362 if (hdw->freqSlotRadio == slotId) {
363 hdw->freqSlotRadio = 0;
364 }
365 } else {
366 if (hdw->freqSlotTelevision == slotId) {
367 hdw->freqSlotTelevision = 0;
368 }
369 }
d855497e
MI		 370 }
371 return 0;
372}
373
374static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
375{
376 *vp = cptr->hdw->freqProgSlot;
377 return 0;
378}
379
380static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
381{
382 struct pvr2_hdw *hdw = cptr->hdw;
383 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
384 hdw->freqProgSlot = v;
385 }
386 return 0;
387}
388
389static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
390{
1bde0289
MI		 391 struct pvr2_hdw *hdw = cptr->hdw;
392 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
d855497e
MI		 393 return 0;
394}
395
1bde0289 396static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
d855497e
MI		 397{
398 unsigned freq = 0;
399 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 400 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
401 if (slotId > 0) {
402 freq = hdw->freqTable[slotId-1];
403 if (!freq) return 0;
404 pvr2_hdw_set_cur_freq(hdw,freq);
d855497e 405 }
1bde0289
MI		 406 if (hdw->freqSelector) {
407 hdw->freqSlotRadio = slotId;
408 } else {
409 hdw->freqSlotTelevision = slotId;
d855497e
MI		 410 }
411 return 0;
412}
413
414static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
415{
1bde0289 416 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
d855497e
MI		 417 return 0;
418}
419
420static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
421{
422 return cptr->hdw->freqDirty != 0;
423}
424
425static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
426{
427 cptr->hdw->freqDirty = 0;
428}
429
430static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
431{
1bde0289 432 pvr2_hdw_set_cur_freq(cptr->hdw,v);
d855497e
MI		 433 return 0;
434}
435
e784bfb9 436static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
437{
432907f7
MI		 438 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
439 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
440 if (stat != 0) {
432907f7 441 return stat;
e784bfb9 442 }
432907f7 443 *left = cap->bounds.left;
e784bfb9 444 return 0;
445}
446
447static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
448{
432907f7
MI		 449 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
450 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
451 if (stat != 0) {
432907f7
MI		 452 return stat;
453 }
454 *left = cap->bounds.left;
455 if (cap->bounds.width > cptr->hdw->cropw_val) {
432907f7 456 *left += cap->bounds.width - cptr->hdw->cropw_val;
e784bfb9 457 }
458 return 0;
459}
460
461static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
462{
432907f7
MI		 463 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
464 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
465 if (stat != 0) {
432907f7 466 return stat;
e784bfb9 467 }
432907f7 468 *top = cap->bounds.top;
e784bfb9 469 return 0;
470}
471
432907f7 472static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
3ad9fc37 473{
432907f7
MI		 474 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
475 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
476 if (stat != 0) {
432907f7
MI		 477 return stat;
478 }
479 *top = cap->bounds.top;
480 if (cap->bounds.height > cptr->hdw->croph_val) {
432907f7 481 *top += cap->bounds.height - cptr->hdw->croph_val;
3ad9fc37
MI		 482 }
483 return 0;
484}
485
432907f7
MI		 486static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
487{
488 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
489 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
490 if (stat != 0) {
432907f7
MI		 491 return stat;
492 }
493 *val = 0;
494 if (cap->bounds.width > cptr->hdw->cropl_val) {
432907f7
MI		 495 *val = cap->bounds.width - cptr->hdw->cropl_val;
496 }
497 return 0;
498}
499
500static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
501{
502 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
503 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
504 if (stat != 0) {
432907f7
MI		 505 return stat;
506 }
507 *val = 0;
508 if (cap->bounds.height > cptr->hdw->cropt_val) {
432907f7
MI		 509 *val = cap->bounds.height - cptr->hdw->cropt_val;
510 }
511 return 0;
512}
513
514static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
515{
516 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
517 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
518 if (stat != 0) {
432907f7
MI		 519 return stat;
520 }
521 *val = cap->bounds.left;
522 return 0;
523}
524
525static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
526{
527 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
528 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
529 if (stat != 0) {
432907f7
MI		 530 return stat;
531 }
532 *val = cap->bounds.top;
533 return 0;
534}
535
536static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
537{
538 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
539 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
540 if (stat != 0) {
432907f7
MI		 541 return stat;
542 }
543 *val = cap->bounds.width;
544 return 0;
545}
546
547static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
548{
549 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
550 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
551 if (stat != 0) {
432907f7
MI		 552 return stat;
553 }
554 *val = cap->bounds.height;
555 return 0;
556}
557
558static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
559{
560 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
561 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
562 if (stat != 0) {
432907f7
MI		 563 return stat;
564 }
565 *val = cap->defrect.left;
566 return 0;
567}
568
569static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
570{
571 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
572 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
573 if (stat != 0) {
432907f7
MI		 574 return stat;
575 }
576 *val = cap->defrect.top;
577 return 0;
578}
579
580static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
581{
582 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
583 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
584 if (stat != 0) {
432907f7
MI		 585 return stat;
586 }
587 *val = cap->defrect.width;
588 return 0;
589}
590
591static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
592{
593 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
594 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
595 if (stat != 0) {
432907f7
MI		 596 return stat;
597 }
598 *val = cap->defrect.height;
599 return 0;
600}
601
602static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
603{
604 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
605 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
606 if (stat != 0) {
432907f7
MI		 607 return stat;
608 }
609 *val = cap->pixelaspect.numerator;
610 return 0;
611}
612
613static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
614{
615 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
616 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
617 if (stat != 0) {
432907f7
MI		 618 return stat;
619 }
620 *val = cap->pixelaspect.denominator;
621 return 0;
622}
623
624static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
e784bfb9 625{
432907f7
MI		 626 /* Actual maximum depends on the video standard in effect. */
627 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
628 *vp = 480;
e784bfb9 629 } else {
432907f7 630 *vp = 576;
e784bfb9 631 }
632 return 0;
633}
634
3ad9fc37
MI		 635static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
636{
989eb154
MI		 637 /* Actual minimum depends on device digitizer type. */
638 if (cptr->hdw->hdw_desc->flag_has_cx25840) {
3ad9fc37
MI		 639 *vp = 75;
640 } else {
641 *vp = 17;
642 }
643 return 0;
644}
645
1bde0289 646static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
5549f54f 647{
1bde0289
MI		 648 *vp = cptr->hdw->input_val;
649 return 0;
650}
651
29bf5b1d
MI		 652static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
653{
1cb03b76 654 return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
29bf5b1d
MI		 655}
656
1bde0289
MI		 657static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
658{
1cb03b76 659 return pvr2_hdw_set_input(cptr->hdw,v);
1bde0289
MI		 660}
661
662static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
663{
664 return cptr->hdw->input_dirty != 0;
665}
666
667static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
668{
669 cptr->hdw->input_dirty = 0;
670}
671
5549f54f 672
25d8527a
PK		 673static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
674{
644afdb9
MI		 675 unsigned long fv;
676 struct pvr2_hdw *hdw = cptr->hdw;
677 if (hdw->tuner_signal_stale) {
a51f5000 678 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 679 }
680 fv = hdw->tuner_signal_info.rangehigh;
681 if (!fv) {
682 /* Safety fallback */
25d8527a 683 *vp = TV_MAX_FREQ;
644afdb9 684 return 0;
25d8527a 685 }
644afdb9
MI		 686 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
687 fv = (fv * 125) / 2;
688 } else {
689 fv = fv * 62500;
690 }
691 *vp = fv;
25d8527a
PK		 692 return 0;
693}
694
695static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
696{
644afdb9
MI		 697 unsigned long fv;
698 struct pvr2_hdw *hdw = cptr->hdw;
699 if (hdw->tuner_signal_stale) {
a51f5000 700 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 701 }
702 fv = hdw->tuner_signal_info.rangelow;
703 if (!fv) {
704 /* Safety fallback */
25d8527a 705 *vp = TV_MIN_FREQ;
644afdb9
MI		 706 return 0;
707 }
708 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
709 fv = (fv * 125) / 2;
710 } else {
711 fv = fv * 62500;
25d8527a 712 }
644afdb9 713 *vp = fv;
25d8527a
PK		 714 return 0;
715}
716
b30d2441
MI		 717static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
718{
719 return cptr->hdw->enc_stale != 0;
720}
721
722static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
723{
724 cptr->hdw->enc_stale = 0;
681c7399 725 cptr->hdw->enc_unsafe_stale = 0;
b30d2441
MI		 726}
727
728static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
729{
730 int ret;
731 struct v4l2_ext_controls cs;
732 struct v4l2_ext_control c1;
733 memset(&cs,0,sizeof(cs));
734 memset(&c1,0,sizeof(c1));
735 cs.controls = &c1;
736 cs.count = 1;
737 c1.id = cptr->info->v4l_id;
01f1e44f 738 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
b30d2441
MI		 739 VIDIOC_G_EXT_CTRLS);
740 if (ret) return ret;
741 *vp = c1.value;
742 return 0;
743}
744
745static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
746{
747 int ret;
681c7399 748 struct pvr2_hdw *hdw = cptr->hdw;
b30d2441
MI		 749 struct v4l2_ext_controls cs;
750 struct v4l2_ext_control c1;
751 memset(&cs,0,sizeof(cs));
752 memset(&c1,0,sizeof(c1));
753 cs.controls = &c1;
754 cs.count = 1;
755 c1.id = cptr->info->v4l_id;
756 c1.value = v;
681c7399
MI		 757 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
758 hdw->state_encoder_run, &cs,
b30d2441 759 VIDIOC_S_EXT_CTRLS);
681c7399
MI		 760 if (ret == -EBUSY) {
761 /* Oops. cx2341x is telling us it's not safe to change
762 this control while we're capturing. Make a note of this
763 fact so that the pipeline will be stopped the next time
764 controls are committed. Then go on ahead and store this
765 change anyway. */
766 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
767 0, &cs,
768 VIDIOC_S_EXT_CTRLS);
769 if (!ret) hdw->enc_unsafe_stale = !0;
770 }
b30d2441 771 if (ret) return ret;
681c7399 772 hdw->enc_stale = !0;
b30d2441
MI		 773 return 0;
774}
775
776static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
777{
778 struct v4l2_queryctrl qctrl;
779 struct pvr2_ctl_info *info;
780 qctrl.id = cptr->info->v4l_id;
781 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
782 /* Strip out the const so we can adjust a function pointer. It's
783 OK to do this here because we know this is a dynamically created
784 control, so the underlying storage for the info pointer is (a)
785 private to us, and (b) not in read-only storage. Either we do
786 this or we significantly complicate the underlying control
787 implementation. */
788 info = (struct pvr2_ctl_info *)(cptr->info);
789 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
790 if (info->set_value) {
a0fd1cb1 791 info->set_value = NULL;
b30d2441
MI		 792 }
793 } else {
794 if (!(info->set_value)) {
795 info->set_value = ctrl_cx2341x_set;
796 }
797 }
798 return qctrl.flags;
799}
800
d855497e
MI		 801static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
802{
681c7399
MI		 803 *vp = cptr->hdw->state_pipeline_req;
804 return 0;
805}
806
807static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
808{
809 *vp = cptr->hdw->master_state;
d855497e
MI		 810 return 0;
811}
812
813static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
814{
815 int result = pvr2_hdw_is_hsm(cptr->hdw);
816 *vp = PVR2_CVAL_HSM_FULL;
817 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
818 if (result) *vp = PVR2_CVAL_HSM_HIGH;
819 return 0;
820}
821
822static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
823{
824 *vp = cptr->hdw->std_mask_avail;
825 return 0;
826}
827
828static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
829{
830 struct pvr2_hdw *hdw = cptr->hdw;
831 v4l2_std_id ns;
832 ns = hdw->std_mask_avail;
833 ns = (ns & ~m) | (v & m);
834 if (ns == hdw->std_mask_avail) return 0;
835 hdw->std_mask_avail = ns;
836 pvr2_hdw_internal_set_std_avail(hdw);
837 pvr2_hdw_internal_find_stdenum(hdw);
838 return 0;
839}
840
841static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
842 char *bufPtr,unsigned int bufSize,
843 unsigned int *len)
844{
845 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
846 return 0;
847}
848
849static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
850 const char *bufPtr,unsigned int bufSize,
851 int *mskp,int *valp)
852{
853 int ret;
854 v4l2_std_id id;
855 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
856 if (ret < 0) return ret;
857 if (mskp) *mskp = id;
858 if (valp) *valp = id;
859 return 0;
860}
861
862static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
863{
864 *vp = cptr->hdw->std_mask_cur;
865 return 0;
866}
867
868static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
869{
870 struct pvr2_hdw *hdw = cptr->hdw;
871 v4l2_std_id ns;
872 ns = hdw->std_mask_cur;
873 ns = (ns & ~m) | (v & m);
874 if (ns == hdw->std_mask_cur) return 0;
875 hdw->std_mask_cur = ns;
876 hdw->std_dirty = !0;
877 pvr2_hdw_internal_find_stdenum(hdw);
878 return 0;
879}
880
881static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
882{
883 return cptr->hdw->std_dirty != 0;
884}
885
886static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
887{
888 cptr->hdw->std_dirty = 0;
889}
890
891static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
892{
18103c57 893 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 894 pvr2_hdw_status_poll(hdw);
18103c57
MI		 895 *vp = hdw->tuner_signal_info.signal;
896 return 0;
897}
898
899static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
900{
901 int val = 0;
902 unsigned int subchan;
903 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 904 pvr2_hdw_status_poll(hdw);
18103c57
MI		 905 subchan = hdw->tuner_signal_info.rxsubchans;
906 if (subchan & V4L2_TUNER_SUB_MONO) {
907 val |= (1 << V4L2_TUNER_MODE_MONO);
908 }
909 if (subchan & V4L2_TUNER_SUB_STEREO) {
910 val |= (1 << V4L2_TUNER_MODE_STEREO);
911 }
912 if (subchan & V4L2_TUNER_SUB_LANG1) {
913 val |= (1 << V4L2_TUNER_MODE_LANG1);
914 }
915 if (subchan & V4L2_TUNER_SUB_LANG2) {
916 val |= (1 << V4L2_TUNER_MODE_LANG2);
917 }
918 *vp = val;
d855497e
MI		 919 return 0;
920}
921
d855497e
MI		 922
923static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
924{
925 struct pvr2_hdw *hdw = cptr->hdw;
926 if (v < 0) return -EINVAL;
927 if (v > hdw->std_enum_cnt) return -EINVAL;
928 hdw->std_enum_cur = v;
929 if (!v) return 0;
930 v--;
931 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
932 hdw->std_mask_cur = hdw->std_defs[v].id;
933 hdw->std_dirty = !0;
934 return 0;
935}
936
937
938static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
939{
940 *vp = cptr->hdw->std_enum_cur;
941 return 0;
942}
943
944
945static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
946{
947 return cptr->hdw->std_dirty != 0;
948}
949
950
951static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
952{
953 cptr->hdw->std_dirty = 0;
954}
955
956
957#define DEFINT(vmin,vmax) \
958 .type = pvr2_ctl_int, \
959 .def.type_int.min_value = vmin, \
960 .def.type_int.max_value = vmax
961
962#define DEFENUM(tab) \
963 .type = pvr2_ctl_enum, \
27c7b710 964 .def.type_enum.count = ARRAY_SIZE(tab), \
d855497e
MI		 965 .def.type_enum.value_names = tab
966
33213963
MI		 967#define DEFBOOL \
968 .type = pvr2_ctl_bool
969
d855497e
MI		 970#define DEFMASK(msk,tab) \
971 .type = pvr2_ctl_bitmask, \
972 .def.type_bitmask.valid_bits = msk, \
973 .def.type_bitmask.bit_names = tab
974
975#define DEFREF(vname) \
976 .set_value = ctrl_set_##vname, \
977 .get_value = ctrl_get_##vname, \
978 .is_dirty = ctrl_isdirty_##vname, \
979 .clear_dirty = ctrl_cleardirty_##vname
980
981
982#define VCREATE_FUNCS(vname) \
983static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
984{*vp = cptr->hdw->vname##_val; return 0;} \
985static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
986{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
987static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
988{return cptr->hdw->vname##_dirty != 0;} \
989static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
990{cptr->hdw->vname##_dirty = 0;}
991
992VCREATE_FUNCS(brightness)
993VCREATE_FUNCS(contrast)
994VCREATE_FUNCS(saturation)
995VCREATE_FUNCS(hue)
996VCREATE_FUNCS(volume)
997VCREATE_FUNCS(balance)
998VCREATE_FUNCS(bass)
999VCREATE_FUNCS(treble)
1000VCREATE_FUNCS(mute)
e784bfb9 1001VCREATE_FUNCS(cropl)
1002VCREATE_FUNCS(cropt)
1003VCREATE_FUNCS(cropw)
1004VCREATE_FUNCS(croph)
c05c0462
MI		 1005VCREATE_FUNCS(audiomode)
1006VCREATE_FUNCS(res_hor)
1007VCREATE_FUNCS(res_ver)
d855497e 1008VCREATE_FUNCS(srate)
d855497e 1009
d855497e
MI		 1010/* Table definition of all controls which can be manipulated */
1011static const struct pvr2_ctl_info control_defs[] = {
1012 {
1013 .v4l_id = V4L2_CID_BRIGHTNESS,
1014 .desc = "Brightness",
1015 .name = "brightness",
1016 .default_value = 128,
1017 DEFREF(brightness),
1018 DEFINT(0,255),
1019 },{
1020 .v4l_id = V4L2_CID_CONTRAST,
1021 .desc = "Contrast",
1022 .name = "contrast",
1023 .default_value = 68,
1024 DEFREF(contrast),
1025 DEFINT(0,127),
1026 },{
1027 .v4l_id = V4L2_CID_SATURATION,
1028 .desc = "Saturation",
1029 .name = "saturation",
1030 .default_value = 64,
1031 DEFREF(saturation),
1032 DEFINT(0,127),
1033 },{
1034 .v4l_id = V4L2_CID_HUE,
1035 .desc = "Hue",
1036 .name = "hue",
1037 .default_value = 0,
1038 DEFREF(hue),
1039 DEFINT(-128,127),
1040 },{
1041 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1042 .desc = "Volume",
1043 .name = "volume",
139eecf9 1044 .default_value = 62000,
d855497e
MI		 1045 DEFREF(volume),
1046 DEFINT(0,65535),
1047 },{
1048 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1049 .desc = "Balance",
1050 .name = "balance",
1051 .default_value = 0,
1052 DEFREF(balance),
1053 DEFINT(-32768,32767),
1054 },{
1055 .v4l_id = V4L2_CID_AUDIO_BASS,
1056 .desc = "Bass",
1057 .name = "bass",
1058 .default_value = 0,
1059 DEFREF(bass),
1060 DEFINT(-32768,32767),
1061 },{
1062 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1063 .desc = "Treble",
1064 .name = "treble",
1065 .default_value = 0,
1066 DEFREF(treble),
1067 DEFINT(-32768,32767),
1068 },{
1069 .v4l_id = V4L2_CID_AUDIO_MUTE,
1070 .desc = "Mute",
1071 .name = "mute",
1072 .default_value = 0,
1073 DEFREF(mute),
33213963 1074 DEFBOOL,
e784bfb9 1075 }, {
432907f7 1076 .desc = "Capture crop left margin",
e784bfb9 1077 .name = "crop_left",
1078 .internal_id = PVR2_CID_CROPL,
1079 .default_value = 0,
1080 DEFREF(cropl),
1081 DEFINT(-129, 340),
1082 .get_min_value = ctrl_cropl_min_get,
1083 .get_max_value = ctrl_cropl_max_get,
432907f7 1084 .get_def_value = ctrl_get_cropcapdl,
e784bfb9 1085 }, {
432907f7 1086 .desc = "Capture crop top margin",
e784bfb9 1087 .name = "crop_top",
1088 .internal_id = PVR2_CID_CROPT,
1089 .default_value = 0,
1090 DEFREF(cropt),
1091 DEFINT(-35, 544),
1092 .get_min_value = ctrl_cropt_min_get,
1093 .get_max_value = ctrl_cropt_max_get,
432907f7 1094 .get_def_value = ctrl_get_cropcapdt,
e784bfb9 1095 }, {
432907f7 1096 .desc = "Capture crop width",
e784bfb9 1097 .name = "crop_width",
1098 .internal_id = PVR2_CID_CROPW,
1099 .default_value = 720,
1100 DEFREF(cropw),
432907f7
MI		 1101 .get_max_value = ctrl_cropw_max_get,
1102 .get_def_value = ctrl_get_cropcapdw,
e784bfb9 1103 }, {
432907f7 1104 .desc = "Capture crop height",
e784bfb9 1105 .name = "crop_height",
1106 .internal_id = PVR2_CID_CROPH,
1107 .default_value = 480,
1108 DEFREF(croph),
432907f7
MI		 1109 .get_max_value = ctrl_croph_max_get,
1110 .get_def_value = ctrl_get_cropcapdh,
1111 }, {
1112 .desc = "Capture capability pixel aspect numerator",
1113 .name = "cropcap_pixel_numerator",
1114 .internal_id = PVR2_CID_CROPCAPPAN,
1115 .get_value = ctrl_get_cropcappan,
1116 }, {
1117 .desc = "Capture capability pixel aspect denominator",
1118 .name = "cropcap_pixel_denominator",
1119 .internal_id = PVR2_CID_CROPCAPPAD,
1120 .get_value = ctrl_get_cropcappad,
1121 }, {
1122 .desc = "Capture capability bounds top",
1123 .name = "cropcap_bounds_top",
1124 .internal_id = PVR2_CID_CROPCAPBT,
1125 .get_value = ctrl_get_cropcapbt,
1126 }, {
1127 .desc = "Capture capability bounds left",
1128 .name = "cropcap_bounds_left",
1129 .internal_id = PVR2_CID_CROPCAPBL,
1130 .get_value = ctrl_get_cropcapbl,
1131 }, {
1132 .desc = "Capture capability bounds width",
1133 .name = "cropcap_bounds_width",
1134 .internal_id = PVR2_CID_CROPCAPBW,
1135 .get_value = ctrl_get_cropcapbw,
1136 }, {
1137 .desc = "Capture capability bounds height",
1138 .name = "cropcap_bounds_height",
1139 .internal_id = PVR2_CID_CROPCAPBH,
1140 .get_value = ctrl_get_cropcapbh,
c05c0462
MI		 1141 },{
1142 .desc = "Video Source",
1143 .name = "input",
1144 .internal_id = PVR2_CID_INPUT,
1145 .default_value = PVR2_CVAL_INPUT_TV,
29bf5b1d 1146 .check_value = ctrl_check_input,
c05c0462
MI		 1147 DEFREF(input),
1148 DEFENUM(control_values_input),
1149 },{
1150 .desc = "Audio Mode",
1151 .name = "audio_mode",
1152 .internal_id = PVR2_CID_AUDIOMODE,
1153 .default_value = V4L2_TUNER_MODE_STEREO,
1154 DEFREF(audiomode),
1155 DEFENUM(control_values_audiomode),
1156 },{
1157 .desc = "Horizontal capture resolution",
1158 .name = "resolution_hor",
1159 .internal_id = PVR2_CID_HRES,
1160 .default_value = 720,
1161 DEFREF(res_hor),
3ad9fc37 1162 DEFINT(19,720),
c05c0462
MI		 1163 },{
1164 .desc = "Vertical capture resolution",
1165 .name = "resolution_ver",
1166 .internal_id = PVR2_CID_VRES,
1167 .default_value = 480,
1168 DEFREF(res_ver),
3ad9fc37
MI		 1169 DEFINT(17,576),
1170 /* Hook in check for video standard and adjust maximum
1171 depending on the standard. */
1172 .get_max_value = ctrl_vres_max_get,
1173 .get_min_value = ctrl_vres_min_get,
d855497e 1174 },{
b30d2441 1175 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
434449f4
MI		 1176 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1177 .desc = "Audio Sampling Frequency",
d855497e 1178 .name = "srate",
d855497e
MI		 1179 DEFREF(srate),
1180 DEFENUM(control_values_srate),
d855497e
MI		 1181 },{
1182 .desc = "Tuner Frequency (Hz)",
1183 .name = "frequency",
1184 .internal_id = PVR2_CID_FREQUENCY,
1bde0289 1185 .default_value = 0,
d855497e
MI		 1186 .set_value = ctrl_freq_set,
1187 .get_value = ctrl_freq_get,
1188 .is_dirty = ctrl_freq_is_dirty,
1189 .clear_dirty = ctrl_freq_clear_dirty,
644afdb9 1190 DEFINT(0,0),
25d8527a
PK		 1191 /* Hook in check for input value (tv/radio) and adjust
1192 max/min values accordingly */
1193 .get_max_value = ctrl_freq_max_get,
1194 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1195 },{
1196 .desc = "Channel",
1197 .name = "channel",
1198 .set_value = ctrl_channel_set,
1199 .get_value = ctrl_channel_get,
1200 DEFINT(0,FREQTABLE_SIZE),
1201 },{
1202 .desc = "Channel Program Frequency",
1203 .name = "freq_table_value",
1204 .set_value = ctrl_channelfreq_set,
1205 .get_value = ctrl_channelfreq_get,
644afdb9 1206 DEFINT(0,0),
1bde0289
MI		 1207 /* Hook in check for input value (tv/radio) and adjust
1208 max/min values accordingly */
1bde0289
MI		 1209 .get_max_value = ctrl_freq_max_get,
1210 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1211 },{
1212 .desc = "Channel Program ID",
1213 .name = "freq_table_channel",
1214 .set_value = ctrl_channelprog_set,
1215 .get_value = ctrl_channelprog_get,
1216 DEFINT(0,FREQTABLE_SIZE),
d855497e
MI		 1217 },{
1218 .desc = "Streaming Enabled",
1219 .name = "streaming_enabled",
1220 .get_value = ctrl_streamingenabled_get,
33213963 1221 DEFBOOL,
d855497e
MI		 1222 },{
1223 .desc = "USB Speed",
1224 .name = "usb_speed",
1225 .get_value = ctrl_hsm_get,
1226 DEFENUM(control_values_hsm),
681c7399
MI		 1227 },{
1228 .desc = "Master State",
1229 .name = "master_state",
1230 .get_value = ctrl_masterstate_get,
1231 DEFENUM(pvr2_state_names),
d855497e
MI		 1232 },{
1233 .desc = "Signal Present",
1234 .name = "signal_present",
1235 .get_value = ctrl_signal_get,
18103c57
MI		 1236 DEFINT(0,65535),
1237 },{
1238 .desc = "Audio Modes Present",
1239 .name = "audio_modes_present",
1240 .get_value = ctrl_audio_modes_present_get,
1241 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1242 v4l. Nothing outside of this module cares about this,
1243 but I reuse it in order to also reuse the
1244 control_values_audiomode string table. */
1245 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1246 (1 << V4L2_TUNER_MODE_STEREO)|
1247 (1 << V4L2_TUNER_MODE_LANG1)|
1248 (1 << V4L2_TUNER_MODE_LANG2)),
1249 control_values_audiomode),
d855497e
MI		 1250 },{
1251 .desc = "Video Standards Available Mask",
1252 .name = "video_standard_mask_available",
1253 .internal_id = PVR2_CID_STDAVAIL,
1254 .skip_init = !0,
1255 .get_value = ctrl_stdavail_get,
1256 .set_value = ctrl_stdavail_set,
1257 .val_to_sym = ctrl_std_val_to_sym,
1258 .sym_to_val = ctrl_std_sym_to_val,
1259 .type = pvr2_ctl_bitmask,
1260 },{
1261 .desc = "Video Standards In Use Mask",
1262 .name = "video_standard_mask_active",
1263 .internal_id = PVR2_CID_STDCUR,
1264 .skip_init = !0,
1265 .get_value = ctrl_stdcur_get,
1266 .set_value = ctrl_stdcur_set,
1267 .is_dirty = ctrl_stdcur_is_dirty,
1268 .clear_dirty = ctrl_stdcur_clear_dirty,
1269 .val_to_sym = ctrl_std_val_to_sym,
1270 .sym_to_val = ctrl_std_sym_to_val,
1271 .type = pvr2_ctl_bitmask,
d855497e
MI		 1272 },{
1273 .desc = "Video Standard Name",
1274 .name = "video_standard",
1275 .internal_id = PVR2_CID_STDENUM,
1276 .skip_init = !0,
1277 .get_value = ctrl_stdenumcur_get,
1278 .set_value = ctrl_stdenumcur_set,
1279 .is_dirty = ctrl_stdenumcur_is_dirty,
1280 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1281 .type = pvr2_ctl_enum,
1282 }
1283};
1284
eca8ebfc 1285#define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
d855497e
MI		 1286
1287
1288const char *pvr2_config_get_name(enum pvr2_config cfg)
1289{
1290 switch (cfg) {
1291 case pvr2_config_empty: return "empty";
1292 case pvr2_config_mpeg: return "mpeg";
1293 case pvr2_config_vbi: return "vbi";
16eb40d3
MI		 1294 case pvr2_config_pcm: return "pcm";
1295 case pvr2_config_rawvideo: return "raw video";
d855497e
MI		 1296 }
1297 return "<unknown>";
1298}
1299
1300
1301struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1302{
1303 return hdw->usb_dev;
1304}
1305
1306
1307unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1308{
1309 return hdw->serial_number;
1310}
1311
31a18547
MI		 1312
1313const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1314{
1315 return hdw->bus_info;
1316}
1317
1318
13a88797
MI		 1319const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1320{
1321 return hdw->identifier;
1322}
1323
1324
1bde0289
MI		 1325unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1326{
1327 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1328}
1329
1330/* Set the currently tuned frequency and account for all possible
1331 driver-core side effects of this action. */
f55a8712 1332static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1bde0289 1333{
7c74e57e 1334 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1bde0289
MI		 1335 if (hdw->freqSelector) {
1336 /* Swing over to radio frequency selection */
1337 hdw->freqSelector = 0;
1338 hdw->freqDirty = !0;
1339 }
1bde0289
MI		 1340 if (hdw->freqValRadio != val) {
1341 hdw->freqValRadio = val;
1342 hdw->freqSlotRadio = 0;
7c74e57e 1343 hdw->freqDirty = !0;
1bde0289 1344 }
7c74e57e 1345 } else {
1bde0289
MI		 1346 if (!(hdw->freqSelector)) {
1347 /* Swing over to television frequency selection */
1348 hdw->freqSelector = 1;
1349 hdw->freqDirty = !0;
1350 }
1bde0289
MI		 1351 if (hdw->freqValTelevision != val) {
1352 hdw->freqValTelevision = val;
1353 hdw->freqSlotTelevision = 0;
7c74e57e 1354 hdw->freqDirty = !0;
1bde0289 1355 }
1bde0289
MI		 1356 }
1357}
1358
d855497e
MI		 1359int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1360{
1361 return hdw->unit_number;
1362}
1363
1364
1365/* Attempt to locate one of the given set of files. Messages are logged
1366 appropriate to what has been found. The return value will be 0 or
1367 greater on success (it will be the index of the file name found) and
1368 fw_entry will be filled in. Otherwise a negative error is returned on
1369 failure. If the return value is -ENOENT then no viable firmware file
1370 could be located. */
1371static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1372 const struct firmware **fw_entry,
1373 const char *fwtypename,
1374 unsigned int fwcount,
1375 const char *fwnames[])
1376{
1377 unsigned int idx;
1378 int ret = -EINVAL;
1379 for (idx = 0; idx < fwcount; idx++) {
1380 ret = request_firmware(fw_entry,
1381 fwnames[idx],
1382 &hdw->usb_dev->dev);
1383 if (!ret) {
1384 trace_firmware("Located %s firmware: %s;"
1385 " uploading...",
1386 fwtypename,
1387 fwnames[idx]);
1388 return idx;
1389 }
1390 if (ret == -ENOENT) continue;
1391 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1392 "request_firmware fatal error with code=%d",ret);
1393 return ret;
1394 }
1395 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1396 "***WARNING***"
1397 " Device %s firmware"
1398 " seems to be missing.",
1399 fwtypename);
1400 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1401 "Did you install the pvrusb2 firmware files"
1402 " in their proper location?");
1403 if (fwcount == 1) {
1404 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1405 "request_firmware unable to locate %s file %s",
1406 fwtypename,fwnames[0]);
1407 } else {
1408 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1409 "request_firmware unable to locate"
1410 " one of the following %s files:",
1411 fwtypename);
1412 for (idx = 0; idx < fwcount; idx++) {
1413 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1414 "request_firmware: Failed to find %s",
1415 fwnames[idx]);
1416 }
1417 }
1418 return ret;
1419}
1420
1421
1422/*
1423 * pvr2_upload_firmware1().
1424 *
1425 * Send the 8051 firmware to the device. After the upload, arrange for
1426 * device to re-enumerate.
1427 *
1428 * NOTE : the pointer to the firmware data given by request_firmware()
1429 * is not suitable for an usb transaction.
1430 *
1431 */
07e337ee 1432static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
d855497e 1433{
a0fd1cb1 1434 const struct firmware *fw_entry = NULL;
d855497e
MI		 1435 void *fw_ptr;
1436 unsigned int pipe;
1437 int ret;
1438 u16 address;
1d643a37 1439
989eb154 1440 if (!hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37 1441 hdw->fw1_state = FW1_STATE_OK;
56dcbfa0
MI		 1442 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1443 "Connected device type defines"
1444 " no firmware to upload; ignoring firmware");
1445 return -ENOTTY;
1d643a37
MI		 1446 }
1447
d855497e
MI		 1448 hdw->fw1_state = FW1_STATE_FAILED; // default result
1449
1450 trace_firmware("pvr2_upload_firmware1");
1451
1452 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
989eb154
MI		 1453 hdw->hdw_desc->fx2_firmware.cnt,
1454 hdw->hdw_desc->fx2_firmware.lst);
d855497e
MI		 1455 if (ret < 0) {
1456 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1457 return ret;
1458 }
1459
1460 usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1461 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1462
1463 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1464
1465 if (fw_entry->size != 0x2000){
1466 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1467 release_firmware(fw_entry);
1468 return -ENOMEM;
1469 }
1470
1471 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1472 if (fw_ptr == NULL){
1473 release_firmware(fw_entry);
1474 return -ENOMEM;
1475 }
1476
1477 /* We have to hold the CPU during firmware upload. */
1478 pvr2_hdw_cpureset_assert(hdw,1);
1479
1480 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1481 chunk. */
1482
1483 ret = 0;
1484 for(address = 0; address < fw_entry->size; address += 0x800) {
1485 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1486 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1487 0, fw_ptr, 0x800, HZ);
1488 }
1489
1490 trace_firmware("Upload done, releasing device's CPU");
1491
1492 /* Now release the CPU. It will disconnect and reconnect later. */
1493 pvr2_hdw_cpureset_assert(hdw,0);
1494
1495 kfree(fw_ptr);
1496 release_firmware(fw_entry);
1497
1498 trace_firmware("Upload done (%d bytes sent)",ret);
1499
1500 /* We should have written 8192 bytes */
1501 if (ret == 8192) {
1502 hdw->fw1_state = FW1_STATE_RELOAD;
1503 return 0;
1504 }
1505
1506 return -EIO;
1507}
1508
1509
1510/*
1511 * pvr2_upload_firmware2()
1512 *
1513 * This uploads encoder firmware on endpoint 2.
1514 *
1515 */
1516
1517int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1518{
a0fd1cb1 1519 const struct firmware *fw_entry = NULL;
d855497e 1520 void *fw_ptr;
90060d32 1521 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
d855497e
MI		 1522 int actual_length;
1523 int ret = 0;
1524 int fwidx;
1525 static const char *fw_files[] = {
1526 CX2341X_FIRM_ENC_FILENAME,
1527 };
1528
989eb154 1529 if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1d643a37
MI		 1530 return 0;
1531 }
1532
d855497e
MI		 1533 trace_firmware("pvr2_upload_firmware2");
1534
1535 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
eca8ebfc 1536 ARRAY_SIZE(fw_files), fw_files);
d855497e
MI		 1537 if (ret < 0) return ret;
1538 fwidx = ret;
1539 ret = 0;
b30d2441
MI		 1540 /* Since we're about to completely reinitialize the encoder,
1541 invalidate our cached copy of its configuration state. Next
1542 time we configure the encoder, then we'll fully configure it. */
1543 hdw->enc_cur_valid = 0;
d855497e 1544
d913d630
MI		 1545 /* Encoder is about to be reset so note that as far as we're
1546 concerned now, the encoder has never been run. */
1547 del_timer_sync(&hdw->encoder_run_timer);
1548 if (hdw->state_encoder_runok) {
1549 hdw->state_encoder_runok = 0;
1550 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1551 }
1552
d855497e
MI		 1553 /* First prepare firmware loading */
1554 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1555 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1556 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1557 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1558 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1559 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1560 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1561 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1562 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1563 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1564 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1565 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1566 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1567 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1568 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1569 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1c9d10d4
MI		 1570 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1571 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1572
1573 if (ret) {
1574 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1575 "firmware2 upload prep failed, ret=%d",ret);
1576 release_firmware(fw_entry);
21684ba9 1577 goto done;
d855497e
MI		 1578 }
1579
1580 /* Now send firmware */
1581
1582 fw_len = fw_entry->size;
1583
90060d32 1584 if (fw_len % sizeof(u32)) {
d855497e
MI		 1585 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1586 "size of %s firmware"
48dc30a1 1587 " must be a multiple of %zu bytes",
90060d32 1588 fw_files[fwidx],sizeof(u32));
d855497e 1589 release_firmware(fw_entry);
21684ba9
MI		 1590 ret = -EINVAL;
1591 goto done;
d855497e
MI		 1592 }
1593
1594 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1595 if (fw_ptr == NULL){
1596 release_firmware(fw_entry);
1597 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1598 "failed to allocate memory for firmware2 upload");
21684ba9
MI		 1599 ret = -ENOMEM;
1600 goto done;
d855497e
MI		 1601 }
1602
1603 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1604
90060d32
MI		 1605 fw_done = 0;
1606 for (fw_done = 0; fw_done < fw_len;) {
1607 bcnt = fw_len - fw_done;
1608 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1609 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1610 /* Usbsnoop log shows that we must swap bytes... */
5f33df14
MI		 1611 /* Some background info: The data being swapped here is a
1612 firmware image destined for the mpeg encoder chip that
1613 lives at the other end of a USB endpoint. The encoder
1614 chip always talks in 32 bit chunks and its storage is
1615 organized into 32 bit words. However from the file
1616 system to the encoder chip everything is purely a byte
1617 stream. The firmware file's contents are always 32 bit
1618 swapped from what the encoder expects. Thus the need
1619 always exists to swap the bytes regardless of the endian
1620 type of the host processor and therefore swab32() makes
1621 the most sense. */
90060d32 1622 for (icnt = 0; icnt < bcnt/4 ; icnt++)
513edce6 1623 ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
90060d32
MI		 1624
1625 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
d855497e 1626 &actual_length, HZ);
90060d32
MI		 1627 ret |= (actual_length != bcnt);
1628 if (ret) break;
1629 fw_done += bcnt;
d855497e
MI		 1630 }
1631
1632 trace_firmware("upload of %s : %i / %i ",
1633 fw_files[fwidx],fw_done,fw_len);
1634
1635 kfree(fw_ptr);
1636 release_firmware(fw_entry);
1637
1638 if (ret) {
1639 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1640 "firmware2 upload transfer failure");
21684ba9 1641 goto done;
d855497e
MI		 1642 }
1643
1644 /* Finish upload */
1645
1646 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1647 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1c9d10d4 1648 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1649
1650 if (ret) {
1651 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1652 "firmware2 upload post-proc failure");
d855497e 1653 }
21684ba9
MI		 1654
1655 done:
1df59f0b
MI		 1656 if (hdw->hdw_desc->signal_routing_scheme ==
1657 PVR2_ROUTING_SCHEME_GOTVIEW) {
1658 /* Ensure that GPIO 11 is set to output for GOTVIEW
1659 hardware. */
1660 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1661 }
d855497e
MI		 1662 return ret;
1663}
1664
1665
681c7399
MI		 1666static const char *pvr2_get_state_name(unsigned int st)
1667{
1668 if (st < ARRAY_SIZE(pvr2_state_names)) {
1669 return pvr2_state_names[st];
d855497e 1670 }
681c7399 1671 return "???";
d855497e
MI		 1672}
1673
681c7399 1674static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
d855497e 1675{
af78e16b
MI		 1676 if (hdw->decoder_ctrl) {
1677 hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt, enablefl);
1678 return 0;
681c7399 1679 }
af78e16b
MI		 1680 /* Even though we really only care about the video decoder chip at
1681 this point, we'll broadcast stream on/off to all sub-devices
1682 anyway, just in case somebody else wants to hear the
1683 command... */
1684 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1685 if (hdw->decoder_client_id) {
1686 /* We get here if the encoder has been noticed. Otherwise
1687 we'll issue a warning to the user (which should
1688 normally never happen). */
1689 return 0;
1690 }
1691 if (!hdw->flag_decoder_missed) {
1692 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1693 "WARNING: No decoder present");
1694 hdw->flag_decoder_missed = !0;
1695 trace_stbit("flag_decoder_missed",
1696 hdw->flag_decoder_missed);
1697 }
1698 return -EIO;
d855497e
MI		 1699}
1700
1701
681c7399 1702void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
d855497e 1703{
681c7399
MI		 1704 if (hdw->decoder_ctrl == ptr) return;
1705 hdw->decoder_ctrl = ptr;
1706 if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1707 hdw->flag_decoder_missed = 0;
1708 trace_stbit("flag_decoder_missed",
1709 hdw->flag_decoder_missed);
1710 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1711 "Decoder has appeared");
1712 pvr2_hdw_state_sched(hdw);
1713 }
d855497e
MI		 1714}
1715
1716
681c7399 1717int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
d855497e 1718{
681c7399 1719 return hdw->master_state;
d855497e
MI		 1720}
1721
1722
681c7399 1723static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
d855497e 1724{
681c7399
MI		 1725 if (!hdw->flag_tripped) return 0;
1726 hdw->flag_tripped = 0;
1727 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1728 "Clearing driver error statuss");
1729 return !0;
d855497e
MI		 1730}
1731
1732
681c7399 1733int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
d855497e 1734{
681c7399 1735 int fl;
d855497e 1736 LOCK_TAKE(hdw->big_lock); do {
681c7399 1737 fl = pvr2_hdw_untrip_unlocked(hdw);
d855497e 1738 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1739 if (fl) pvr2_hdw_state_sched(hdw);
1740 return 0;
d855497e
MI		 1741}
1742
1743
d855497e
MI		 1744
1745
1746int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1747{
681c7399 1748 return hdw->state_pipeline_req != 0;
d855497e
MI		 1749}
1750
1751
1752int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1753{
681c7399 1754 int ret,st;
d855497e 1755 LOCK_TAKE(hdw->big_lock); do {
681c7399
MI		 1756 pvr2_hdw_untrip_unlocked(hdw);
1757 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1758 hdw->state_pipeline_req = enable_flag != 0;
1759 pvr2_trace(PVR2_TRACE_START_STOP,
1760 "/*--TRACE_STREAM--*/ %s",
1761 enable_flag ? "enable" : "disable");
1762 }
1763 pvr2_hdw_state_sched(hdw);
d855497e 1764 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1765 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1766 if (enable_flag) {
1767 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1768 if (st != PVR2_STATE_READY) return -EIO;
1769 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1770 }
1771 }
d855497e
MI		 1772 return 0;
1773}
1774
1775
1776int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1777{
681c7399 1778 int fl;
d855497e 1779 LOCK_TAKE(hdw->big_lock);
681c7399
MI		 1780 if ((fl = (hdw->desired_stream_type != config)) != 0) {
1781 hdw->desired_stream_type = config;
1782 hdw->state_pipeline_config = 0;
1783 trace_stbit("state_pipeline_config",
1784 hdw->state_pipeline_config);
1785 pvr2_hdw_state_sched(hdw);
1786 }
d855497e 1787 LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1788 if (fl) return 0;
1789 return pvr2_hdw_wait(hdw,0);
d855497e
MI		 1790}
1791
1792
1793static int get_default_tuner_type(struct pvr2_hdw *hdw)
1794{
1795 int unit_number = hdw->unit_number;
1796 int tp = -1;
1797 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1798 tp = tuner[unit_number];
1799 }
1800 if (tp < 0) return -EINVAL;
1801 hdw->tuner_type = tp;
aaf7884d 1802 hdw->tuner_updated = !0;
d855497e
MI		 1803 return 0;
1804}
1805
1806
1807static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1808{
1809 int unit_number = hdw->unit_number;
1810 int tp = 0;
1811 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1812 tp = video_std[unit_number];
6a540254 1813 if (tp) return tp;
d855497e 1814 }
6a540254 1815 return 0;
d855497e
MI		 1816}
1817
1818
1819static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1820{
1821 int unit_number = hdw->unit_number;
1822 int tp = 0;
1823 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1824 tp = tolerance[unit_number];
1825 }
1826 return tp;
1827}
1828
1829
1830static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1831{
1832 /* Try a harmless request to fetch the eeprom's address over
1833 endpoint 1. See what happens. Only the full FX2 image can
1834 respond to this. If this probe fails then likely the FX2
1835 firmware needs be loaded. */
1836 int result;
1837 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 1838 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 1839 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1840 hdw->cmd_buffer,1,
1841 hdw->cmd_buffer,1);
1842 if (result < 0) break;
1843 } while(0); LOCK_GIVE(hdw->ctl_lock);
1844 if (result) {
1845 pvr2_trace(PVR2_TRACE_INIT,
1846 "Probe of device endpoint 1 result status %d",
1847 result);
1848 } else {
1849 pvr2_trace(PVR2_TRACE_INIT,
1850 "Probe of device endpoint 1 succeeded");
1851 }
1852 return result == 0;
1853}
1854
9f66d4ea
MI		 1855struct pvr2_std_hack {
1856 v4l2_std_id pat; /* Pattern to match */
1857 v4l2_std_id msk; /* Which bits we care about */
1858 v4l2_std_id std; /* What additional standards or default to set */
1859};
1860
1861/* This data structure labels specific combinations of standards from
1862 tveeprom that we'll try to recognize. If we recognize one, then assume
1863 a specified default standard to use. This is here because tveeprom only
1864 tells us about available standards not the intended default standard (if
1865 any) for the device in question. We guess the default based on what has
1866 been reported as available. Note that this is only for guessing a
1867 default - which can always be overridden explicitly - and if the user
1868 has otherwise named a default then that default will always be used in
1869 place of this table. */
ebff0330 1870static const struct pvr2_std_hack std_eeprom_maps[] = {
9f66d4ea
MI		 1871 { /* PAL(B/G) */
1872 .pat = V4L2_STD_B|V4L2_STD_GH,
1873 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1874 },
1875 { /* NTSC(M) */
1876 .pat = V4L2_STD_MN,
1877 .std = V4L2_STD_NTSC_M,
1878 },
1879 { /* PAL(I) */
1880 .pat = V4L2_STD_PAL_I,
1881 .std = V4L2_STD_PAL_I,
1882 },
1883 { /* SECAM(L/L') */
1884 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1885 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1886 },
1887 { /* PAL(D/D1/K) */
1888 .pat = V4L2_STD_DK,
ea2562d9 1889 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
9f66d4ea
MI		 1890 },
1891};
1892
d855497e
MI		 1893static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1894{
1895 char buf[40];
1896 unsigned int bcnt;
3d290bdb 1897 v4l2_std_id std1,std2,std3;
d855497e
MI		 1898
1899 std1 = get_default_standard(hdw);
3d290bdb 1900 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
d855497e
MI		 1901
1902 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
56585386 1903 pvr2_trace(PVR2_TRACE_STD,
56dcbfa0
MI		 1904 "Supported video standard(s) reported available"
1905 " in hardware: %.*s",
d855497e
MI		 1906 bcnt,buf);
1907
1908 hdw->std_mask_avail = hdw->std_mask_eeprom;
1909
3d290bdb 1910 std2 = (std1|std3) & ~hdw->std_mask_avail;
d855497e
MI		 1911 if (std2) {
1912 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
56585386 1913 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1914 "Expanding supported video standards"
1915 " to include: %.*s",
1916 bcnt,buf);
1917 hdw->std_mask_avail |= std2;
1918 }
1919
1920 pvr2_hdw_internal_set_std_avail(hdw);
1921
1922 if (std1) {
1923 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
56585386 1924 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1925 "Initial video standard forced to %.*s",
1926 bcnt,buf);
1927 hdw->std_mask_cur = std1;
1928 hdw->std_dirty = !0;
1929 pvr2_hdw_internal_find_stdenum(hdw);
1930 return;
1931 }
3d290bdb
MI		 1932 if (std3) {
1933 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1934 pvr2_trace(PVR2_TRACE_STD,
1935 "Initial video standard"
1936 " (determined by device type): %.*s",bcnt,buf);
1937 hdw->std_mask_cur = std3;
1938 hdw->std_dirty = !0;
1939 pvr2_hdw_internal_find_stdenum(hdw);
1940 return;
1941 }
d855497e 1942
9f66d4ea
MI		 1943 {
1944 unsigned int idx;
1945 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1946 if (std_eeprom_maps[idx].msk ?
1947 ((std_eeprom_maps[idx].pat ^
1948 hdw->std_mask_eeprom) &
1949 std_eeprom_maps[idx].msk) :
1950 (std_eeprom_maps[idx].pat !=
1951 hdw->std_mask_eeprom)) continue;
1952 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1953 std_eeprom_maps[idx].std);
56585386 1954 pvr2_trace(PVR2_TRACE_STD,
9f66d4ea
MI		 1955 "Initial video standard guessed as %.*s",
1956 bcnt,buf);
1957 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1958 hdw->std_dirty = !0;
1959 pvr2_hdw_internal_find_stdenum(hdw);
1960 return;
1961 }
1962 }
1963
d855497e
MI		 1964 if (hdw->std_enum_cnt > 1) {
1965 // Autoselect the first listed standard
1966 hdw->std_enum_cur = 1;
1967 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1968 hdw->std_dirty = !0;
56585386 1969 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1970 "Initial video standard auto-selected to %s",
1971 hdw->std_defs[hdw->std_enum_cur-1].name);
1972 return;
1973 }
1974
0885ba1d 1975 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
d855497e
MI		 1976 "Unable to select a viable initial video standard");
1977}
1978
1979
e9c64a78
MI		 1980static unsigned int pvr2_copy_i2c_addr_list(
1981 unsigned short *dst, const unsigned char *src,
1982 unsigned int dst_max)
1983{
3ab8d295 1984 unsigned int cnt = 0;
e9c64a78
MI		 1985 if (!src) return 0;
1986 while (src[cnt] && (cnt + 1) < dst_max) {
1987 dst[cnt] = src[cnt];
1988 cnt++;
1989 }
1990 dst[cnt] = I2C_CLIENT_END;
1991 return cnt;
1992}
1993
1994
1ab5e74f
MI		 1995static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
1996 const struct pvr2_device_client_desc *cd)
e9c64a78
MI		 1997{
1998 const char *fname;
1999 unsigned char mid;
2000 struct v4l2_subdev *sd;
2001 unsigned int i2ccnt;
2002 const unsigned char *p;
2003 /* Arbitrary count - max # i2c addresses we will probe */
2004 unsigned short i2caddr[25];
2005
2006 mid = cd->module_id;
2007 fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
2008 if (!fname) {
2009 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1ab5e74f 2010 "Module ID %u for device %s has no name",
e9c64a78
MI		 2011 mid,
2012 hdw->hdw_desc->description);
1ab5e74f 2013 return -EINVAL;
e9c64a78 2014 }
bd14d4f8
MI		 2015 pvr2_trace(PVR2_TRACE_INIT,
2016 "Module ID %u (%s) for device %s being loaded...",
2017 mid, fname,
2018 hdw->hdw_desc->description);
e9c64a78
MI		 2019
2020 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2021 ARRAY_SIZE(i2caddr));
2022 if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2023 module_i2c_addresses[mid] : NULL) != NULL)) {
2024 /* Second chance: Try default i2c address list */
2025 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2026 ARRAY_SIZE(i2caddr));
bd14d4f8
MI		 2027 if (i2ccnt) {
2028 pvr2_trace(PVR2_TRACE_INIT,
2029 "Module ID %u:"
2030 " Using default i2c address list",
2031 mid);
2032 }
e9c64a78
MI		 2033 }
2034
2035 if (!i2ccnt) {
2036 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1ab5e74f
MI		 2037 "Module ID %u (%s) for device %s:"
2038 " No i2c addresses",
2039 mid, fname, hdw->hdw_desc->description);
2040 return -EINVAL;
e9c64a78
MI		 2041 }
2042
2043 /* Note how the 2nd and 3rd arguments are the same for both
2044 * v4l2_i2c_new_subdev() and v4l2_i2c_new_probed_subdev(). Why?
2045 * Well the 2nd argument is the module name to load, while the 3rd
2046 * argument is documented in the framework as being the "chipid" -
2047 * and every other place where I can find examples of this, the
2048 * "chipid" appears to just be the module name again. So here we
2049 * just do the same thing. */
0db85568 2050 hdw->i2c_adap.class = 0;
e9c64a78 2051 if (i2ccnt == 1) {
bd14d4f8
MI		 2052 pvr2_trace(PVR2_TRACE_INIT,
2053 "Module ID %u:"
2054 " Setting up with specified i2c address 0x%x",
2055 mid, i2caddr[0]);
e9c64a78
MI		 2056 sd = v4l2_i2c_new_subdev(&hdw->i2c_adap,
2057 fname, fname,
2058 i2caddr[0]);
2059 } else {
bd14d4f8
MI		 2060 pvr2_trace(PVR2_TRACE_INIT,
2061 "Module ID %u:"
2062 " Setting up with address probe list",
2063 mid);
e9c64a78
MI		 2064 sd = v4l2_i2c_new_probed_subdev(&hdw->i2c_adap,
2065 fname, fname,
2066 i2caddr);
2067 }
0db85568 2068 hdw->i2c_adap.class = I2C_CLASS_TV_ANALOG;
e9c64a78 2069
446dfdc6
MI		 2070 if (!sd) {
2071 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1ab5e74f
MI		 2072 "Module ID %u (%s) for device %s failed to load",
2073 mid, fname, hdw->hdw_desc->description);
2074 return -EIO;
446dfdc6
MI		 2075 }
2076
2077 /* Tag this sub-device instance with the module ID we know about.
2078 In other places we'll use that tag to determine if the instance
2079 requires special handling. */
2080 sd->grp_id = mid;
2081
a932f507
MI		 2082 /* If we have both old and new i2c layers enabled, make sure that
2083 old layer isn't also tracking this module. This is a debugging
2084 aid, in normal situations there's no reason for both mechanisms
2085 to be enabled. */
2086 pvr2_i2c_untrack_subdev(hdw, sd);
bd14d4f8 2087 pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
a932f507 2088
e9c64a78 2089
00e5f736
MI		 2090 /* client-specific setup... */
2091 switch (mid) {
2092 case PVR2_CLIENT_ID_CX25840:
2093 hdw->decoder_client_id = mid;
2094 {
2095 /*
2096 Mike Isely <isely@pobox.com> 19-Nov-2006 - This
2097 bit of nuttiness for cx25840 causes that module
2098 to correctly set up its video scaling. This is
2099 really a problem in the cx25840 module itself,
2100 but we work around it here. The problem has not
2101 been seen in ivtv because there VBI is supported
2102 and set up. We don't do VBI here (at least not
2103 yet) and thus we never attempted to even set it
2104 up.
2105 */
2106 struct v4l2_format fmt;
bd14d4f8
MI		 2107 pvr2_trace(PVR2_TRACE_INIT,
2108 "Module ID %u:"
2109 " Executing cx25840 VBI hack",
2110 mid);
00e5f736
MI		 2111 memset(&fmt, 0, sizeof(fmt));
2112 fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
2113 v4l2_device_call_all(&hdw->v4l2_dev, mid,
2114 video, s_fmt, &fmt);
2115 }
2116 break;
2117 case PVR2_CLIENT_ID_SAA7115:
2118 hdw->decoder_client_id = mid;
2119 break;
2120 default: break;
2121 }
1ab5e74f
MI		 2122
2123 return 0;
e9c64a78
MI		 2124}
2125
2126
2127static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2128{
2129 unsigned int idx;
2130 const struct pvr2_string_table *cm;
2131 const struct pvr2_device_client_table *ct;
1ab5e74f 2132 int okFl = !0;
e9c64a78
MI		 2133
2134 cm = &hdw->hdw_desc->client_modules;
2135 for (idx = 0; idx < cm->cnt; idx++) {
2136 request_module(cm->lst[idx]);
2137 }
2138
2139 ct = &hdw->hdw_desc->client_table;
2140 for (idx = 0; idx < ct->cnt; idx++) {
bd14d4f8 2141 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
e9c64a78 2142 }
1ab5e74f 2143 if (!okFl) pvr2_hdw_render_useless(hdw);
e9c64a78
MI		 2144}
2145
2146
d855497e
MI		 2147static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2148{
2149 int ret;
2150 unsigned int idx;
2151 struct pvr2_ctrl *cptr;
2152 int reloadFl = 0;
989eb154 2153 if (hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37
MI		 2154 if (!reloadFl) {
2155 reloadFl =
2156 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2157 == 0);
2158 if (reloadFl) {
2159 pvr2_trace(PVR2_TRACE_INIT,
2160 "USB endpoint config looks strange"
2161 "; possibly firmware needs to be"
2162 " loaded");
2163 }
d855497e 2164 }
1d643a37
MI		 2165 if (!reloadFl) {
2166 reloadFl = !pvr2_hdw_check_firmware(hdw);
2167 if (reloadFl) {
2168 pvr2_trace(PVR2_TRACE_INIT,
2169 "Check for FX2 firmware failed"
2170 "; possibly firmware needs to be"
2171 " loaded");
2172 }
d855497e 2173 }
1d643a37
MI		 2174 if (reloadFl) {
2175 if (pvr2_upload_firmware1(hdw) != 0) {
2176 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2177 "Failure uploading firmware1");
2178 }
2179 return;
d855497e 2180 }
d855497e
MI		 2181 }
2182 hdw->fw1_state = FW1_STATE_OK;
2183
d855497e
MI		 2184 if (!pvr2_hdw_dev_ok(hdw)) return;
2185
989eb154 2186 if (!hdw->hdw_desc->flag_no_powerup) {
1d643a37
MI		 2187 pvr2_hdw_cmd_powerup(hdw);
2188 if (!pvr2_hdw_dev_ok(hdw)) return;
d855497e
MI		 2189 }
2190
31335b13
MI		 2191 /* Take the IR chip out of reset, if appropriate */
2192 if (hdw->hdw_desc->ir_scheme == PVR2_IR_SCHEME_ZILOG) {
2193 pvr2_issue_simple_cmd(hdw,
2194 FX2CMD_HCW_ZILOG_RESET |
2195 (1 << 8) |
2196 ((0) << 16));
2197 }
2198
d855497e 2199 // This step MUST happen after the earlier powerup step.
59af3367 2200 pvr2_i2c_track_init(hdw);
d855497e
MI		 2201 pvr2_i2c_core_init(hdw);
2202 if (!pvr2_hdw_dev_ok(hdw)) return;
2203
e9c64a78 2204 pvr2_hdw_load_modules(hdw);
1ab5e74f 2205 if (!pvr2_hdw_dev_ok(hdw)) return;
e9c64a78 2206
c05c0462 2207 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e
MI		 2208 cptr = hdw->controls + idx;
2209 if (cptr->info->skip_init) continue;
2210 if (!cptr->info->set_value) continue;
2211 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2212 }
2213
1bde0289
MI		 2214 /* Set up special default values for the television and radio
2215 frequencies here. It's not really important what these defaults
2216 are, but I set them to something usable in the Chicago area just
2217 to make driver testing a little easier. */
2218
5a4f5da6
MK		 2219 hdw->freqValTelevision = default_tv_freq;
2220 hdw->freqValRadio = default_radio_freq;
1bde0289 2221
d855497e
MI		 2222 // Do not use pvr2_reset_ctl_endpoints() here. It is not
2223 // thread-safe against the normal pvr2_send_request() mechanism.
2224 // (We should make it thread safe).
2225
aaf7884d
MI		 2226 if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2227 ret = pvr2_hdw_get_eeprom_addr(hdw);
d855497e 2228 if (!pvr2_hdw_dev_ok(hdw)) return;
aaf7884d
MI		 2229 if (ret < 0) {
2230 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2231 "Unable to determine location of eeprom,"
2232 " skipping");
2233 } else {
2234 hdw->eeprom_addr = ret;
2235 pvr2_eeprom_analyze(hdw);
2236 if (!pvr2_hdw_dev_ok(hdw)) return;
2237 }
2238 } else {
2239 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2240 hdw->tuner_updated = !0;
2241 hdw->std_mask_eeprom = V4L2_STD_ALL;
d855497e
MI		 2242 }
2243
13a88797
MI		 2244 if (hdw->serial_number) {
2245 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2246 "sn-%lu", hdw->serial_number);
2247 } else if (hdw->unit_number >= 0) {
2248 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2249 "unit-%c",
2250 hdw->unit_number + 'a');
2251 } else {
2252 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2253 "unit-??");
2254 }
2255 hdw->identifier[idx] = 0;
2256
d855497e
MI		 2257 pvr2_hdw_setup_std(hdw);
2258
2259 if (!get_default_tuner_type(hdw)) {
2260 pvr2_trace(PVR2_TRACE_INIT,
2261 "pvr2_hdw_setup: Tuner type overridden to %d",
2262 hdw->tuner_type);
2263 }
2264
d855497e 2265 pvr2_i2c_core_check_stale(hdw);
d855497e
MI		 2266
2267 if (!pvr2_hdw_dev_ok(hdw)) return;
2268
1df59f0b
MI		 2269 if (hdw->hdw_desc->signal_routing_scheme ==
2270 PVR2_ROUTING_SCHEME_GOTVIEW) {
2271 /* Ensure that GPIO 11 is set to output for GOTVIEW
2272 hardware. */
2273 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2274 }
2275
681c7399 2276 pvr2_hdw_commit_setup(hdw);
d855497e
MI		 2277
2278 hdw->vid_stream = pvr2_stream_create();
2279 if (!pvr2_hdw_dev_ok(hdw)) return;
2280 pvr2_trace(PVR2_TRACE_INIT,
2281 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2282 if (hdw->vid_stream) {
2283 idx = get_default_error_tolerance(hdw);
2284 if (idx) {
2285 pvr2_trace(PVR2_TRACE_INIT,
2286 "pvr2_hdw_setup: video stream %p"
2287 " setting tolerance %u",
2288 hdw->vid_stream,idx);
2289 }
2290 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2291 PVR2_VID_ENDPOINT,idx);
2292 }
2293
2294 if (!pvr2_hdw_dev_ok(hdw)) return;
2295
d855497e 2296 hdw->flag_init_ok = !0;
681c7399
MI		 2297
2298 pvr2_hdw_state_sched(hdw);
d855497e
MI		 2299}
2300
2301
681c7399
MI		 2302/* Set up the structure and attempt to put the device into a usable state.
2303 This can be a time-consuming operation, which is why it is not done
2304 internally as part of the create() step. */
2305static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
d855497e
MI		 2306{
2307 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
681c7399 2308 do {
d855497e
MI		 2309 pvr2_hdw_setup_low(hdw);
2310 pvr2_trace(PVR2_TRACE_INIT,
2311 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
681c7399 2312 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
d855497e 2313 if (pvr2_hdw_dev_ok(hdw)) {
681c7399 2314 if (hdw->flag_init_ok) {
d855497e
MI		 2315 pvr2_trace(
2316 PVR2_TRACE_INFO,
2317 "Device initialization"
2318 " completed successfully.");
2319 break;
2320 }
2321 if (hdw->fw1_state == FW1_STATE_RELOAD) {
2322 pvr2_trace(
2323 PVR2_TRACE_INFO,
2324 "Device microcontroller firmware"
2325 " (re)loaded; it should now reset"
2326 " and reconnect.");
2327 break;
2328 }
2329 pvr2_trace(
2330 PVR2_TRACE_ERROR_LEGS,
2331 "Device initialization was not successful.");
2332 if (hdw->fw1_state == FW1_STATE_MISSING) {
2333 pvr2_trace(
2334 PVR2_TRACE_ERROR_LEGS,
2335 "Giving up since device"
2336 " microcontroller firmware"
2337 " appears to be missing.");
2338 break;
2339 }
2340 }
2341 if (procreload) {
2342 pvr2_trace(
2343 PVR2_TRACE_ERROR_LEGS,
2344 "Attempting pvrusb2 recovery by reloading"
2345 " primary firmware.");
2346 pvr2_trace(
2347 PVR2_TRACE_ERROR_LEGS,
2348 "If this works, device should disconnect"
2349 " and reconnect in a sane state.");
2350 hdw->fw1_state = FW1_STATE_UNKNOWN;
2351 pvr2_upload_firmware1(hdw);
2352 } else {
2353 pvr2_trace(
2354 PVR2_TRACE_ERROR_LEGS,
2355 "***WARNING*** pvrusb2 device hardware"
2356 " appears to be jammed"
2357 " and I can't clear it.");
2358 pvr2_trace(
2359 PVR2_TRACE_ERROR_LEGS,
2360 "You might need to power cycle"
2361 " the pvrusb2 device"
2362 " in order to recover.");
2363 }
681c7399 2364 } while (0);
d855497e 2365 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
d855497e
MI		 2366}
2367
2368
c4a8828d
MI		 2369/* Perform second stage initialization. Set callback pointer first so that
2370 we can avoid a possible initialization race (if the kernel thread runs
2371 before the callback has been set). */
794b1607
MI		 2372int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2373 void (*callback_func)(void *),
2374 void *callback_data)
c4a8828d
MI		 2375{
2376 LOCK_TAKE(hdw->big_lock); do {
97f26ff6
MI		 2377 if (hdw->flag_disconnected) {
2378 /* Handle a race here: If we're already
2379 disconnected by this point, then give up. If we
2380 get past this then we'll remain connected for
2381 the duration of initialization since the entire
2382 initialization sequence is now protected by the
2383 big_lock. */
2384 break;
2385 }
c4a8828d
MI		 2386 hdw->state_data = callback_data;
2387 hdw->state_func = callback_func;
97f26ff6 2388 pvr2_hdw_setup(hdw);
c4a8828d 2389 } while (0); LOCK_GIVE(hdw->big_lock);
794b1607 2390 return hdw->flag_init_ok;
c4a8828d
MI		 2391}
2392
2393
2394/* Create, set up, and return a structure for interacting with the
2395 underlying hardware. */
d855497e
MI		 2396struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2397 const struct usb_device_id *devid)
2398{
7fb20fa3 2399 unsigned int idx,cnt1,cnt2,m;
fe15f136 2400 struct pvr2_hdw *hdw = NULL;
d855497e
MI		 2401 int valid_std_mask;
2402 struct pvr2_ctrl *cptr;
b72b7bf5 2403 struct usb_device *usb_dev;
989eb154 2404 const struct pvr2_device_desc *hdw_desc;
d855497e 2405 __u8 ifnum;
b30d2441
MI		 2406 struct v4l2_queryctrl qctrl;
2407 struct pvr2_ctl_info *ciptr;
d855497e 2408
b72b7bf5
MI		 2409 usb_dev = interface_to_usbdev(intf);
2410
d130fa8a 2411 hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
d855497e 2412
fe15f136
MI		 2413 if (hdw_desc == NULL) {
2414 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2415 " No device description pointer,"
2416 " unable to continue.");
2417 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2418 " please contact Mike Isely <isely@pobox.com>"
2419 " to get it included in the driver\n");
2420 goto fail;
2421 }
2422
ca545f7c 2423 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
d855497e 2424 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
989eb154 2425 hdw,hdw_desc->description);
d855497e 2426 if (!hdw) goto fail;
681c7399
MI		 2427
2428 init_timer(&hdw->quiescent_timer);
2429 hdw->quiescent_timer.data = (unsigned long)hdw;
2430 hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2431
2432 init_timer(&hdw->encoder_wait_timer);
2433 hdw->encoder_wait_timer.data = (unsigned long)hdw;
2434 hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2435
d913d630
MI		 2436 init_timer(&hdw->encoder_run_timer);
2437 hdw->encoder_run_timer.data = (unsigned long)hdw;
2438 hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2439
681c7399
MI		 2440 hdw->master_state = PVR2_STATE_DEAD;
2441
2442 init_waitqueue_head(&hdw->state_wait_data);
2443
18103c57 2444 hdw->tuner_signal_stale = !0;
b30d2441 2445 cx2341x_fill_defaults(&hdw->enc_ctl_state);
d855497e 2446
7fb20fa3
MI		 2447 /* Calculate which inputs are OK */
2448 m = 0;
2449 if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
e8f5bacf
MI		 2450 if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2451 m |= 1 << PVR2_CVAL_INPUT_DTV;
2452 }
7fb20fa3
MI		 2453 if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2454 if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2455 if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2456 hdw->input_avail_mask = m;
1cb03b76 2457 hdw->input_allowed_mask = hdw->input_avail_mask;
7fb20fa3 2458
62433e31
MI		 2459 /* If not a hybrid device, pathway_state never changes. So
2460 initialize it here to what it should forever be. */
2461 if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2462 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2463 } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2464 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2465 }
2466
c05c0462 2467 hdw->control_cnt = CTRLDEF_COUNT;
b30d2441 2468 hdw->control_cnt += MPEGDEF_COUNT;
ca545f7c 2469 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
d855497e
MI		 2470 GFP_KERNEL);
2471 if (!hdw->controls) goto fail;
989eb154 2472 hdw->hdw_desc = hdw_desc;
c05c0462
MI		 2473 for (idx = 0; idx < hdw->control_cnt; idx++) {
2474 cptr = hdw->controls + idx;
2475 cptr->hdw = hdw;
2476 }
d855497e
MI		 2477 for (idx = 0; idx < 32; idx++) {
2478 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2479 }
c05c0462 2480 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e 2481 cptr = hdw->controls + idx;
d855497e
MI		 2482 cptr->info = control_defs+idx;
2483 }
dbc40a0e
MI		 2484
2485 /* Ensure that default input choice is a valid one. */
2486 m = hdw->input_avail_mask;
2487 if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2488 if (!((1 << idx) & m)) continue;
2489 hdw->input_val = idx;
2490 break;
2491 }
2492
b30d2441 2493 /* Define and configure additional controls from cx2341x module. */
ca545f7c 2494 hdw->mpeg_ctrl_info = kzalloc(
b30d2441
MI		 2495 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2496 if (!hdw->mpeg_ctrl_info) goto fail;
b30d2441
MI		 2497 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2498 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2499 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2500 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2501 ciptr->name = mpeg_ids[idx].strid;
2502 ciptr->v4l_id = mpeg_ids[idx].id;
2503 ciptr->skip_init = !0;
2504 ciptr->get_value = ctrl_cx2341x_get;
2505 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2506 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2507 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2508 qctrl.id = ciptr->v4l_id;
2509 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2510 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2511 ciptr->set_value = ctrl_cx2341x_set;
2512 }
2513 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2514 PVR2_CTLD_INFO_DESC_SIZE);
2515 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2516 ciptr->default_value = qctrl.default_value;
2517 switch (qctrl.type) {
2518 default:
2519 case V4L2_CTRL_TYPE_INTEGER:
2520 ciptr->type = pvr2_ctl_int;
2521 ciptr->def.type_int.min_value = qctrl.minimum;
2522 ciptr->def.type_int.max_value = qctrl.maximum;
2523 break;
2524 case V4L2_CTRL_TYPE_BOOLEAN:
2525 ciptr->type = pvr2_ctl_bool;
2526 break;
2527 case V4L2_CTRL_TYPE_MENU:
2528 ciptr->type = pvr2_ctl_enum;
2529 ciptr->def.type_enum.value_names =
e0e31cdb
HV		 2530 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2531 ciptr->v4l_id);
b30d2441
MI		 2532 for (cnt1 = 0;
2533 ciptr->def.type_enum.value_names[cnt1] != NULL;
2534 cnt1++) { }
2535 ciptr->def.type_enum.count = cnt1;
2536 break;
2537 }
2538 cptr->info = ciptr;
2539 }
d855497e
MI		 2540
2541 // Initialize video standard enum dynamic control
2542 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2543 if (cptr) {
2544 memcpy(&hdw->std_info_enum,cptr->info,
2545 sizeof(hdw->std_info_enum));
2546 cptr->info = &hdw->std_info_enum;
2547
2548 }
2549 // Initialize control data regarding video standard masks
2550 valid_std_mask = pvr2_std_get_usable();
2551 for (idx = 0; idx < 32; idx++) {
2552 if (!(valid_std_mask & (1 << idx))) continue;
2553 cnt1 = pvr2_std_id_to_str(
2554 hdw->std_mask_names[idx],
2555 sizeof(hdw->std_mask_names[idx])-1,
2556 1 << idx);
2557 hdw->std_mask_names[idx][cnt1] = 0;
2558 }
2559 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2560 if (cptr) {
2561 memcpy(&hdw->std_info_avail,cptr->info,
2562 sizeof(hdw->std_info_avail));
2563 cptr->info = &hdw->std_info_avail;
2564 hdw->std_info_avail.def.type_bitmask.bit_names =
2565 hdw->std_mask_ptrs;
2566 hdw->std_info_avail.def.type_bitmask.valid_bits =
2567 valid_std_mask;
2568 }
2569 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2570 if (cptr) {
2571 memcpy(&hdw->std_info_cur,cptr->info,
2572 sizeof(hdw->std_info_cur));
2573 cptr->info = &hdw->std_info_cur;
2574 hdw->std_info_cur.def.type_bitmask.bit_names =
2575 hdw->std_mask_ptrs;
2576 hdw->std_info_avail.def.type_bitmask.valid_bits =
2577 valid_std_mask;
2578 }
2579
432907f7 2580 hdw->cropcap_stale = !0;
d855497e
MI		 2581 hdw->eeprom_addr = -1;
2582 hdw->unit_number = -1;
8079384e
MI		 2583 hdw->v4l_minor_number_video = -1;
2584 hdw->v4l_minor_number_vbi = -1;
fd5a75fe 2585 hdw->v4l_minor_number_radio = -1;
d855497e
MI		 2586 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2587 if (!hdw->ctl_write_buffer) goto fail;
2588 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2589 if (!hdw->ctl_read_buffer) goto fail;
2590 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2591 if (!hdw->ctl_write_urb) goto fail;
2592 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2593 if (!hdw->ctl_read_urb) goto fail;
2594
b72b7bf5
MI		 2595 if (v4l2_device_register(&usb_dev->dev, &hdw->v4l2_dev) != 0) {
2596 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2597 "Error registering with v4l core, giving up");
2598 goto fail;
2599 }
8df0c87c 2600 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2601 for (idx = 0; idx < PVR_NUM; idx++) {
2602 if (unit_pointers[idx]) continue;
2603 hdw->unit_number = idx;
2604 unit_pointers[idx] = hdw;
2605 break;
2606 }
8df0c87c 2607 } while (0); mutex_unlock(&pvr2_unit_mtx);
d855497e
MI		 2608
2609 cnt1 = 0;
2610 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2611 cnt1 += cnt2;
2612 if (hdw->unit_number >= 0) {
2613 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2614 ('a' + hdw->unit_number));
2615 cnt1 += cnt2;
2616 }
2617 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2618 hdw->name[cnt1] = 0;
2619
681c7399
MI		 2620 hdw->workqueue = create_singlethread_workqueue(hdw->name);
2621 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2622 INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
681c7399 2623
d855497e
MI		 2624 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2625 hdw->unit_number,hdw->name);
2626
2627 hdw->tuner_type = -1;
2628 hdw->flag_ok = !0;
d855497e
MI		 2629
2630 hdw->usb_intf = intf;
b72b7bf5 2631 hdw->usb_dev = usb_dev;
d855497e 2632
87e3495c 2633 usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
31a18547 2634
d855497e
MI		 2635 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2636 usb_set_interface(hdw->usb_dev,ifnum,0);
2637
2638 mutex_init(&hdw->ctl_lock_mutex);
2639 mutex_init(&hdw->big_lock_mutex);
2640
2641 return hdw;
2642 fail:
2643 if (hdw) {
681c7399 2644 del_timer_sync(&hdw->quiescent_timer);
d913d630 2645 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 2646 del_timer_sync(&hdw->encoder_wait_timer);
2647 if (hdw->workqueue) {
2648 flush_workqueue(hdw->workqueue);
2649 destroy_workqueue(hdw->workqueue);
2650 hdw->workqueue = NULL;
2651 }
5e55d2ce
MK		 2652 usb_free_urb(hdw->ctl_read_urb);
2653 usb_free_urb(hdw->ctl_write_urb);
22071a42
MK		 2654 kfree(hdw->ctl_read_buffer);
2655 kfree(hdw->ctl_write_buffer);
2656 kfree(hdw->controls);
2657 kfree(hdw->mpeg_ctrl_info);
681c7399
MI		 2658 kfree(hdw->std_defs);
2659 kfree(hdw->std_enum_names);
d855497e
MI		 2660 kfree(hdw);
2661 }
a0fd1cb1 2662 return NULL;
d855497e
MI		 2663}
2664
2665
2666/* Remove _all_ associations between this driver and the underlying USB
2667 layer. */
07e337ee 2668static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
d855497e
MI		 2669{
2670 if (hdw->flag_disconnected) return;
2671 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2672 if (hdw->ctl_read_urb) {
2673 usb_kill_urb(hdw->ctl_read_urb);
2674 usb_free_urb(hdw->ctl_read_urb);
a0fd1cb1 2675 hdw->ctl_read_urb = NULL;
d855497e
MI		 2676 }
2677 if (hdw->ctl_write_urb) {
2678 usb_kill_urb(hdw->ctl_write_urb);
2679 usb_free_urb(hdw->ctl_write_urb);
a0fd1cb1 2680 hdw->ctl_write_urb = NULL;
d855497e
MI		 2681 }
2682 if (hdw->ctl_read_buffer) {
2683 kfree(hdw->ctl_read_buffer);
a0fd1cb1 2684 hdw->ctl_read_buffer = NULL;
d855497e
MI		 2685 }
2686 if (hdw->ctl_write_buffer) {
2687 kfree(hdw->ctl_write_buffer);
a0fd1cb1 2688 hdw->ctl_write_buffer = NULL;
d855497e 2689 }
d855497e 2690 hdw->flag_disconnected = !0;
b72b7bf5
MI		 2691 /* If we don't do this, then there will be a dangling struct device
2692 reference to our disappearing device persisting inside the V4L
2693 core... */
2694 if (hdw->v4l2_dev.dev) {
2695 dev_set_drvdata(hdw->v4l2_dev.dev, NULL);
2696 hdw->v4l2_dev.dev = NULL;
2697 }
a0fd1cb1
MI		 2698 hdw->usb_dev = NULL;
2699 hdw->usb_intf = NULL;
681c7399 2700 pvr2_hdw_render_useless(hdw);
d855497e
MI		 2701}
2702
2703
2704/* Destroy hardware interaction structure */
2705void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2706{
401c27ce 2707 if (!hdw) return;
d855497e 2708 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
681c7399
MI		 2709 if (hdw->workqueue) {
2710 flush_workqueue(hdw->workqueue);
2711 destroy_workqueue(hdw->workqueue);
2712 hdw->workqueue = NULL;
2713 }
8f59100a 2714 del_timer_sync(&hdw->quiescent_timer);
d913d630 2715 del_timer_sync(&hdw->encoder_run_timer);
8f59100a 2716 del_timer_sync(&hdw->encoder_wait_timer);
d855497e
MI		 2717 if (hdw->fw_buffer) {
2718 kfree(hdw->fw_buffer);
a0fd1cb1 2719 hdw->fw_buffer = NULL;
d855497e
MI		 2720 }
2721 if (hdw->vid_stream) {
2722 pvr2_stream_destroy(hdw->vid_stream);
a0fd1cb1 2723 hdw->vid_stream = NULL;
d855497e 2724 }
d855497e
MI		 2725 if (hdw->decoder_ctrl) {
2726 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2727 }
2728 pvr2_i2c_core_done(hdw);
59af3367 2729 pvr2_i2c_track_done(hdw);
b72b7bf5 2730 v4l2_device_unregister(&hdw->v4l2_dev);
d855497e 2731 pvr2_hdw_remove_usb_stuff(hdw);
8df0c87c 2732 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2733 if ((hdw->unit_number >= 0) &&
2734 (hdw->unit_number < PVR_NUM) &&
2735 (unit_pointers[hdw->unit_number] == hdw)) {
a0fd1cb1 2736 unit_pointers[hdw->unit_number] = NULL;
d855497e 2737 }
8df0c87c 2738 } while (0); mutex_unlock(&pvr2_unit_mtx);
22071a42
MK		 2739 kfree(hdw->controls);
2740 kfree(hdw->mpeg_ctrl_info);
2741 kfree(hdw->std_defs);
2742 kfree(hdw->std_enum_names);
d855497e
MI		 2743 kfree(hdw);
2744}
2745
2746
d855497e
MI		 2747int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2748{
2749 return (hdw && hdw->flag_ok);
2750}
2751
2752
2753/* Called when hardware has been unplugged */
2754void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2755{
2756 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2757 LOCK_TAKE(hdw->big_lock);
2758 LOCK_TAKE(hdw->ctl_lock);
2759 pvr2_hdw_remove_usb_stuff(hdw);
2760 LOCK_GIVE(hdw->ctl_lock);
2761 LOCK_GIVE(hdw->big_lock);
2762}
2763
2764
2765// Attempt to autoselect an appropriate value for std_enum_cur given
2766// whatever is currently in std_mask_cur
07e337ee 2767static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
d855497e
MI		 2768{
2769 unsigned int idx;
2770 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2771 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2772 hdw->std_enum_cur = idx;
2773 return;
2774 }
2775 }
2776 hdw->std_enum_cur = 0;
2777}
2778
2779
2780// Calculate correct set of enumerated standards based on currently known
2781// set of available standards bits.
07e337ee 2782static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
d855497e
MI		 2783{
2784 struct v4l2_standard *newstd;
2785 unsigned int std_cnt;
2786 unsigned int idx;
2787
2788 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2789
2790 if (hdw->std_defs) {
2791 kfree(hdw->std_defs);
a0fd1cb1 2792 hdw->std_defs = NULL;
d855497e
MI		 2793 }
2794 hdw->std_enum_cnt = 0;
2795 if (hdw->std_enum_names) {
2796 kfree(hdw->std_enum_names);
a0fd1cb1 2797 hdw->std_enum_names = NULL;
d855497e
MI		 2798 }
2799
2800 if (!std_cnt) {
2801 pvr2_trace(
2802 PVR2_TRACE_ERROR_LEGS,
2803 "WARNING: Failed to identify any viable standards");
2804 }
2805 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2806 hdw->std_enum_names[0] = "none";
2807 for (idx = 0; idx < std_cnt; idx++) {
2808 hdw->std_enum_names[idx+1] =
2809 newstd[idx].name;
2810 }
2811 // Set up the dynamic control for this standard
2812 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2813 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2814 hdw->std_defs = newstd;
2815 hdw->std_enum_cnt = std_cnt+1;
2816 hdw->std_enum_cur = 0;
2817 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2818}
2819
2820
2821int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2822 struct v4l2_standard *std,
2823 unsigned int idx)
2824{
2825 int ret = -EINVAL;
2826 if (!idx) return ret;
2827 LOCK_TAKE(hdw->big_lock); do {
2828 if (idx >= hdw->std_enum_cnt) break;
2829 idx--;
2830 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2831 ret = 0;
2832 } while (0); LOCK_GIVE(hdw->big_lock);
2833 return ret;
2834}
2835
2836
2837/* Get the number of defined controls */
2838unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2839{
c05c0462 2840 return hdw->control_cnt;
d855497e
MI		 2841}
2842
2843
2844/* Retrieve a control handle given its index (0..count-1) */
2845struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2846 unsigned int idx)
2847{
a0fd1cb1 2848 if (idx >= hdw->control_cnt) return NULL;
d855497e
MI		 2849 return hdw->controls + idx;
2850}
2851
2852
2853/* Retrieve a control handle given its index (0..count-1) */
2854struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2855 unsigned int ctl_id)
2856{
2857 struct pvr2_ctrl *cptr;
2858 unsigned int idx;
2859 int i;
2860
2861 /* This could be made a lot more efficient, but for now... */
c05c0462 2862 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2863 cptr = hdw->controls + idx;
2864 i = cptr->info->internal_id;
2865 if (i && (i == ctl_id)) return cptr;
2866 }
a0fd1cb1 2867 return NULL;
d855497e
MI		 2868}
2869
2870
a761f431 2871/* Given a V4L ID, retrieve the control structure associated with it. */
d855497e
MI		 2872struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2873{
2874 struct pvr2_ctrl *cptr;
2875 unsigned int idx;
2876 int i;
2877
2878 /* This could be made a lot more efficient, but for now... */
c05c0462 2879 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2880 cptr = hdw->controls + idx;
2881 i = cptr->info->v4l_id;
2882 if (i && (i == ctl_id)) return cptr;
2883 }
a0fd1cb1 2884 return NULL;
d855497e
MI		 2885}
2886
2887
a761f431
MI		 2888/* Given a V4L ID for its immediate predecessor, retrieve the control
2889 structure associated with it. */
2890struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2891 unsigned int ctl_id)
2892{
2893 struct pvr2_ctrl *cptr,*cp2;
2894 unsigned int idx;
2895 int i;
2896
2897 /* This could be made a lot more efficient, but for now... */
a0fd1cb1 2898 cp2 = NULL;
a761f431
MI		 2899 for (idx = 0; idx < hdw->control_cnt; idx++) {
2900 cptr = hdw->controls + idx;
2901 i = cptr->info->v4l_id;
2902 if (!i) continue;
2903 if (i <= ctl_id) continue;
2904 if (cp2 && (cp2->info->v4l_id < i)) continue;
2905 cp2 = cptr;
2906 }
2907 return cp2;
a0fd1cb1 2908 return NULL;
a761f431
MI		 2909}
2910
2911
d855497e
MI		 2912static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2913{
2914 switch (tp) {
2915 case pvr2_ctl_int: return "integer";
2916 case pvr2_ctl_enum: return "enum";
33213963 2917 case pvr2_ctl_bool: return "boolean";
d855497e
MI		 2918 case pvr2_ctl_bitmask: return "bitmask";
2919 }
2920 return "";
2921}
2922
2923
2641df36
MI		 2924static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2925 const char *name, int val)
2926{
2927 struct v4l2_control ctrl;
2928 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2929 memset(&ctrl, 0, sizeof(ctrl));
2930 ctrl.id = id;
2931 ctrl.value = val;
2932 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2933}
2934
2935#define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
2936 if ((hdw)->lab##_dirty) { \
2937 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2938 }
2939
5ceaad14 2940/* Execute whatever commands are required to update the state of all the
2641df36 2941 sub-devices so that they match our current control values. */
5ceaad14
MI		 2942static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2943{
edb9dcb8
MI		 2944 struct v4l2_subdev *sd;
2945 unsigned int id;
2946 pvr2_subdev_update_func fp;
2947
75212a02
MI		 2948 pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
2949
2950 if (hdw->tuner_updated) {
2951 struct tuner_setup setup;
2952 pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
2953 hdw->tuner_type);
2954 if (((int)(hdw->tuner_type)) >= 0) {
2955 setup.addr = ADDR_UNSET;
2956 setup.type = hdw->tuner_type;
2957 setup.mode_mask = T_RADIO | T_ANALOG_TV;
2958 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2959 tuner, s_type_addr, &setup);
2960 }
2961 }
2962
2641df36 2963 if (hdw->input_dirty || hdw->std_dirty) {
b481880b 2964 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
2641df36
MI		 2965 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2966 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2967 tuner, s_radio);
2968 } else {
2969 v4l2_std_id vs;
2970 vs = hdw->std_mask_cur;
2971 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2972 tuner, s_std, vs);
2973 }
2974 hdw->tuner_signal_stale = !0;
2975 hdw->cropcap_stale = !0;
2976 }
2977
2978 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2979 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2980 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2981 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2982 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2983 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2984 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2985 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2986 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2987
2988 if (hdw->input_dirty || hdw->audiomode_dirty) {
2989 struct v4l2_tuner vt;
2990 memset(&vt, 0, sizeof(vt));
2991 vt.audmode = hdw->audiomode_val;
2992 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
2993 }
2994
2995 if (hdw->freqDirty) {
2996 unsigned long fv;
2997 struct v4l2_frequency freq;
2998 fv = pvr2_hdw_get_cur_freq(hdw);
2999 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
3000 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
3001 memset(&freq, 0, sizeof(freq));
3002 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
3003 /* ((fv * 1000) / 62500) */
3004 freq.frequency = (fv * 2) / 125;
3005 } else {
3006 freq.frequency = fv / 62500;
3007 }
3008 /* tuner-core currently doesn't seem to care about this, but
3009 let's set it anyway for completeness. */
3010 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3011 freq.type = V4L2_TUNER_RADIO;
3012 } else {
3013 freq.type = V4L2_TUNER_ANALOG_TV;
3014 }
3015 freq.tuner = 0;
3016 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
3017 s_frequency, &freq);
3018 }
3019
3020 if (hdw->res_hor_dirty || hdw->res_ver_dirty) {
3021 struct v4l2_format fmt;
3022 memset(&fmt, 0, sizeof(fmt));
3023 fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
3024 fmt.fmt.pix.width = hdw->res_hor_val;
3025 fmt.fmt.pix.height = hdw->res_ver_val;
3026 pvr2_trace(PVR2_TRACE_CHIPS,"subdev v4l2 set_size(%dx%d)",
3027 fmt.fmt.pix.width, fmt.fmt.pix.height);
3028 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_fmt, &fmt);
3029 }
3030
01c59df8
MI		 3031 if (hdw->srate_dirty) {
3032 u32 val;
3033 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
3034 hdw->srate_val);
3035 switch (hdw->srate_val) {
3036 default:
3037 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
3038 val = 48000;
3039 break;
3040 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
3041 val = 44100;
3042 break;
3043 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
3044 val = 32000;
3045 break;
3046 }
3047 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3048 audio, s_clock_freq, val);
3049 }
3050
2641df36
MI		 3051 /* Unable to set crop parameters; there is apparently no equivalent
3052 for VIDIOC_S_CROP */
3053
edb9dcb8
MI		 3054 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
3055 id = sd->grp_id;
3056 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
3057 fp = pvr2_module_update_functions[id];
3058 if (!fp) continue;
3059 (*fp)(hdw, sd);
3060 }
2641df36
MI		 3061
3062 if (hdw->tuner_signal_stale && hdw->cropcap_stale) {
3063 pvr2_hdw_status_poll(hdw);
3064 }
5ceaad14
MI		 3065}
3066
3067
681c7399
MI		 3068/* Figure out if we need to commit control changes. If so, mark internal
3069 state flags to indicate this fact and return true. Otherwise do nothing
3070 else and return false. */
3071static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
d855497e 3072{
d855497e
MI		 3073 unsigned int idx;
3074 struct pvr2_ctrl *cptr;
3075 int value;
3076 int commit_flag = 0;
3077 char buf[100];
3078 unsigned int bcnt,ccnt;
3079
c05c0462 3080 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e 3081 cptr = hdw->controls + idx;
5fa1247a 3082 if (!cptr->info->is_dirty) continue;
d855497e 3083 if (!cptr->info->is_dirty(cptr)) continue;
fe23a280 3084 commit_flag = !0;
d855497e 3085
fe23a280 3086 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
d855497e
MI		 3087 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3088 cptr->info->name);
3089 value = 0;
3090 cptr->info->get_value(cptr,&value);
3091 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3092 buf+bcnt,
3093 sizeof(buf)-bcnt,&ccnt);
3094 bcnt += ccnt;
3095 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3096 get_ctrl_typename(cptr->info->type));
3097 pvr2_trace(PVR2_TRACE_CTL,
3098 "/*--TRACE_COMMIT--*/ %.*s",
3099 bcnt,buf);
3100 }
3101
3102 if (!commit_flag) {
3103 /* Nothing has changed */
3104 return 0;
3105 }
3106
681c7399
MI		 3107 hdw->state_pipeline_config = 0;
3108 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3109 pvr2_hdw_state_sched(hdw);
3110
3111 return !0;
3112}
3113
3114
3115/* Perform all operations needed to commit all control changes. This must
3116 be performed in synchronization with the pipeline state and is thus
3117 expected to be called as part of the driver's worker thread. Return
3118 true if commit successful, otherwise return false to indicate that
3119 commit isn't possible at this time. */
3120static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3121{
3122 unsigned int idx;
3123 struct pvr2_ctrl *cptr;
3124 int disruptive_change;
3125
ab062fe3
MI		 3126 /* Handle some required side effects when the video standard is
3127 changed.... */
d855497e 3128 if (hdw->std_dirty) {
d855497e 3129 int nvres;
00528d9c 3130 int gop_size;
d855497e
MI		 3131 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3132 nvres = 480;
00528d9c 3133 gop_size = 15;
d855497e
MI		 3134 } else {
3135 nvres = 576;
00528d9c 3136 gop_size = 12;
d855497e 3137 }
00528d9c
MI		 3138 /* Rewrite the vertical resolution to be appropriate to the
3139 video standard that has been selected. */
d855497e
MI		 3140 if (nvres != hdw->res_ver_val) {
3141 hdw->res_ver_val = nvres;
3142 hdw->res_ver_dirty = !0;
3143 }
00528d9c
MI		 3144 /* Rewrite the GOP size to be appropriate to the video
3145 standard that has been selected. */
3146 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3147 struct v4l2_ext_controls cs;
3148 struct v4l2_ext_control c1;
3149 memset(&cs, 0, sizeof(cs));
3150 memset(&c1, 0, sizeof(c1));
3151 cs.controls = &c1;
3152 cs.count = 1;
3153 c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3154 c1.value = gop_size;
3155 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3156 VIDIOC_S_EXT_CTRLS);
3157 }
d855497e
MI		 3158 }
3159
38d9a2cf 3160 if (hdw->input_dirty && hdw->state_pathway_ok &&
62433e31
MI		 3161 (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3162 PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3163 hdw->pathway_state)) {
3164 /* Change of mode being asked for... */
3165 hdw->state_pathway_ok = 0;
e9db1ff2 3166 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 3167 }
3168 if (!hdw->state_pathway_ok) {
3169 /* Can't commit anything until pathway is ok. */
3170 return 0;
3171 }
e784bfb9 3172 /* The broadcast decoder can only scale down, so if
3173 * res_*_dirty && crop window < output format ==> enlarge crop.
3174 *
3175 * The mpeg encoder receives fields of res_hor_val dots and
3176 * res_ver_val halflines. Limits: hor<=720, ver<=576.
3177 */
3178 if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3179 hdw->cropw_val = hdw->res_hor_val;
3180 hdw->cropw_dirty = !0;
3181 } else if (hdw->cropw_dirty) {
3182 hdw->res_hor_dirty = !0; /* must rescale */
3183 hdw->res_hor_val = min(720, hdw->cropw_val);
3184 }
3185 if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3186 hdw->croph_val = hdw->res_ver_val;
3187 hdw->croph_dirty = !0;
3188 } else if (hdw->croph_dirty) {
3189 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3190 hdw->res_ver_dirty = !0;
3191 hdw->res_ver_val = min(nvres, hdw->croph_val);
3192 }
3193
681c7399
MI		 3194 /* If any of the below has changed, then we can't do the update
3195 while the pipeline is running. Pipeline must be paused first
3196 and decoder -> encoder connection be made quiescent before we
3197 can proceed. */
3198 disruptive_change =
3199 (hdw->std_dirty ||
3200 hdw->enc_unsafe_stale ||
3201 hdw->srate_dirty ||
3202 hdw->res_ver_dirty ||
3203 hdw->res_hor_dirty ||
755879c6
MI		 3204 hdw->cropw_dirty ||
3205 hdw->croph_dirty ||
681c7399
MI		 3206 hdw->input_dirty ||
3207 (hdw->active_stream_type != hdw->desired_stream_type));
3208 if (disruptive_change && !hdw->state_pipeline_idle) {
3209 /* Pipeline is not idle; we can't proceed. Arrange to
3210 cause pipeline to stop so that we can try this again
3211 later.... */
3212 hdw->state_pipeline_pause = !0;
3213 return 0;
275b2e28
PK		 3214 }
3215
b30d2441
MI		 3216 if (hdw->srate_dirty) {
3217 /* Write new sample rate into control structure since
3218 * the master copy is stale. We must track srate
3219 * separate from the mpeg control structure because
3220 * other logic also uses this value. */
3221 struct v4l2_ext_controls cs;
3222 struct v4l2_ext_control c1;
3223 memset(&cs,0,sizeof(cs));
3224 memset(&c1,0,sizeof(c1));
3225 cs.controls = &c1;
3226 cs.count = 1;
3227 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3228 c1.value = hdw->srate_val;
01f1e44f 3229 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
b30d2441 3230 }
c05c0462 3231
d855497e
MI		 3232 /* Scan i2c core at this point - before we clear all the dirty
3233 bits. Various parts of the i2c core will notice dirty bits as
3234 appropriate and arrange to broadcast or directly send updates to
3235 the client drivers in order to keep everything in sync */
3236 pvr2_i2c_core_check_stale(hdw);
3237
681c7399
MI		 3238 if (hdw->active_stream_type != hdw->desired_stream_type) {
3239 /* Handle any side effects of stream config here */
3240 hdw->active_stream_type = hdw->desired_stream_type;
3241 }
3242
1df59f0b
MI		 3243 if (hdw->hdw_desc->signal_routing_scheme ==
3244 PVR2_ROUTING_SCHEME_GOTVIEW) {
3245 u32 b;
3246 /* Handle GOTVIEW audio switching */
3247 pvr2_hdw_gpio_get_out(hdw,&b);
3248 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3249 /* Set GPIO 11 */
3250 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3251 } else {
3252 /* Clear GPIO 11 */
3253 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3254 }
3255 }
3256
e68a619a
MI		 3257 /* Check and update state for all sub-devices. */
3258 pvr2_subdev_update(hdw);
3259
75212a02 3260 hdw->tuner_updated = 0;
5ceaad14
MI		 3261 for (idx = 0; idx < hdw->control_cnt; idx++) {
3262 cptr = hdw->controls + idx;
3263 if (!cptr->info->clear_dirty) continue;
3264 cptr->info->clear_dirty(cptr);
3265 }
3266
d855497e
MI		 3267 /* Now execute i2c core update */
3268 pvr2_i2c_core_sync(hdw);
3269
62433e31
MI		 3270 if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3271 hdw->state_encoder_run) {
3272 /* If encoder isn't running or it can't be touched, then
3273 this will get worked out later when we start the
3274 encoder. */
681c7399
MI		 3275 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3276 }
d855497e 3277
681c7399 3278 hdw->state_pipeline_config = !0;
432907f7
MI		 3279 /* Hardware state may have changed in a way to cause the cropping
3280 capabilities to have changed. So mark it stale, which will
3281 cause a later re-fetch. */
681c7399
MI		 3282 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3283 return !0;
d855497e
MI		 3284}
3285
3286
3287int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3288{
681c7399
MI		 3289 int fl;
3290 LOCK_TAKE(hdw->big_lock);
3291 fl = pvr2_hdw_commit_setup(hdw);
3292 LOCK_GIVE(hdw->big_lock);
3293 if (!fl) return 0;
3294 return pvr2_hdw_wait(hdw,0);
3295}
3296
3297
3298static void pvr2_hdw_worker_i2c(struct work_struct *work)
3299{
3300 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
d855497e 3301 LOCK_TAKE(hdw->big_lock); do {
681c7399 3302 pvr2_i2c_core_sync(hdw);
d855497e 3303 } while (0); LOCK_GIVE(hdw->big_lock);
d855497e
MI		 3304}
3305
3306
681c7399 3307static void pvr2_hdw_worker_poll(struct work_struct *work)
d855497e 3308{
681c7399
MI		 3309 int fl = 0;
3310 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
d855497e 3311 LOCK_TAKE(hdw->big_lock); do {
681c7399 3312 fl = pvr2_hdw_state_eval(hdw);
d855497e 3313 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 3314 if (fl && hdw->state_func) {
3315 hdw->state_func(hdw->state_data);
3316 }
d855497e
MI		 3317}
3318
3319
681c7399 3320static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
d855497e 3321{
681c7399
MI		 3322 return wait_event_interruptible(
3323 hdw->state_wait_data,
3324 (hdw->state_stale == 0) &&
3325 (!state || (hdw->master_state != state)));
3326}
3327
3328
d855497e
MI		 3329/* Return name for this driver instance */
3330const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3331{
3332 return hdw->name;
3333}
3334
3335
78a47101
MI		 3336const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3337{
3338 return hdw->hdw_desc->description;
3339}
3340
3341
3342const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3343{
3344 return hdw->hdw_desc->shortname;
3345}
3346
3347
d855497e
MI		 3348int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3349{
3350 int result;
3351 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 3352 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
d855497e
MI		 3353 result = pvr2_send_request(hdw,
3354 hdw->cmd_buffer,1,
3355 hdw->cmd_buffer,1);
3356 if (result < 0) break;
3357 result = (hdw->cmd_buffer[0] != 0);
3358 } while(0); LOCK_GIVE(hdw->ctl_lock);
3359 return result;
3360}
3361
3362
18103c57
MI		 3363/* Execute poll of tuner status */
3364void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
d855497e 3365{
d855497e 3366 LOCK_TAKE(hdw->big_lock); do {
a51f5000 3367 pvr2_hdw_status_poll(hdw);
d855497e 3368 } while (0); LOCK_GIVE(hdw->big_lock);
18103c57
MI		 3369}
3370
3371
432907f7
MI		 3372static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3373{
3374 if (!hdw->cropcap_stale) {
432907f7
MI		 3375 return 0;
3376 }
a51f5000 3377 pvr2_hdw_status_poll(hdw);
432907f7 3378 if (hdw->cropcap_stale) {
432907f7
MI		 3379 return -EIO;
3380 }
3381 return 0;
3382}
3383
3384
3385/* Return information about cropping capabilities */
3386int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3387{
3388 int stat = 0;
3389 LOCK_TAKE(hdw->big_lock);
3390 stat = pvr2_hdw_check_cropcap(hdw);
3391 if (!stat) {
432907f7
MI		 3392 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3393 }
3394 LOCK_GIVE(hdw->big_lock);
3395 return stat;
3396}
3397
3398
18103c57
MI		 3399/* Return information about the tuner */
3400int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3401{
3402 LOCK_TAKE(hdw->big_lock); do {
3403 if (hdw->tuner_signal_stale) {
a51f5000 3404 pvr2_hdw_status_poll(hdw);
18103c57
MI		 3405 }
3406 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3407 } while (0); LOCK_GIVE(hdw->big_lock);
3408 return 0;
d855497e
MI		 3409}
3410
3411
3412/* Get handle to video output stream */
3413struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3414{
3415 return hp->vid_stream;
3416}
3417
3418
3419void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3420{
4f1a3e5b 3421 int nr = pvr2_hdw_get_unit_number(hdw);
d855497e 3422 LOCK_TAKE(hdw->big_lock); do {
4f1a3e5b 3423 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
5ceaad14 3424 hdw->log_requested = !0;
d855497e 3425 pvr2_i2c_core_check_stale(hdw);
d855497e 3426 pvr2_i2c_core_sync(hdw);
a51f5000 3427 hdw->log_requested = 0;
ed3261a8 3428 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
b30d2441 3429 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
99eb44fe 3430 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
681c7399 3431 pvr2_hdw_state_log_state(hdw);
4f1a3e5b 3432 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
d855497e
MI		 3433 } while (0); LOCK_GIVE(hdw->big_lock);
3434}
3435
4db666cc
MI		 3436
3437/* Grab EEPROM contents, needed for direct method. */
3438#define EEPROM_SIZE 8192
3439#define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3440static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3441{
3442 struct i2c_msg msg[2];
3443 u8 *eeprom;
3444 u8 iadd[2];
3445 u8 addr;
3446 u16 eepromSize;
3447 unsigned int offs;
3448 int ret;
3449 int mode16 = 0;
3450 unsigned pcnt,tcnt;
3451 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3452 if (!eeprom) {
3453 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3454 "Failed to allocate memory"
3455 " required to read eeprom");
3456 return NULL;
3457 }
3458
3459 trace_eeprom("Value for eeprom addr from controller was 0x%x",
3460 hdw->eeprom_addr);
3461 addr = hdw->eeprom_addr;
3462 /* Seems that if the high bit is set, then the *real* eeprom
3463 address is shifted right now bit position (noticed this in
3464 newer PVR USB2 hardware) */
3465 if (addr & 0x80) addr >>= 1;
3466
3467 /* FX2 documentation states that a 16bit-addressed eeprom is
3468 expected if the I2C address is an odd number (yeah, this is
3469 strange but it's what they do) */
3470 mode16 = (addr & 1);
3471 eepromSize = (mode16 ? EEPROM_SIZE : 256);
3472 trace_eeprom("Examining %d byte eeprom at location 0x%x"
3473 " using %d bit addressing",eepromSize,addr,
3474 mode16 ? 16 : 8);
3475
3476 msg[0].addr = addr;
3477 msg[0].flags = 0;
3478 msg[0].len = mode16 ? 2 : 1;
3479 msg[0].buf = iadd;
3480 msg[1].addr = addr;
3481 msg[1].flags = I2C_M_RD;
3482
3483 /* We have to do the actual eeprom data fetch ourselves, because
3484 (1) we're only fetching part of the eeprom, and (2) if we were
3485 getting the whole thing our I2C driver can't grab it in one
3486 pass - which is what tveeprom is otherwise going to attempt */
3487 memset(eeprom,0,EEPROM_SIZE);
3488 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3489 pcnt = 16;
3490 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3491 offs = tcnt + (eepromSize - EEPROM_SIZE);
3492 if (mode16) {
3493 iadd[0] = offs >> 8;
3494 iadd[1] = offs;
3495 } else {
3496 iadd[0] = offs;
3497 }
3498 msg[1].len = pcnt;
3499 msg[1].buf = eeprom+tcnt;
3500 if ((ret = i2c_transfer(&hdw->i2c_adap,
3501 msg,ARRAY_SIZE(msg))) != 2) {
3502 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3503 "eeprom fetch set offs err=%d",ret);
3504 kfree(eeprom);
3505 return NULL;
3506 }
3507 }
3508 return eeprom;
3509}
3510
3511
3512void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3513 int prom_flag,
3514 int enable_flag)
d855497e
MI		 3515{
3516 int ret;
3517 u16 address;
3518 unsigned int pipe;
3519 LOCK_TAKE(hdw->big_lock); do {
5fa1247a 3520 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
d855497e
MI		 3521
3522 if (!enable_flag) {
3523 pvr2_trace(PVR2_TRACE_FIRMWARE,
3524 "Cleaning up after CPU firmware fetch");
3525 kfree(hdw->fw_buffer);
a0fd1cb1 3526 hdw->fw_buffer = NULL;
d855497e 3527 hdw->fw_size = 0;
4db666cc
MI		 3528 if (hdw->fw_cpu_flag) {
3529 /* Now release the CPU. It will disconnect
3530 and reconnect later. */
3531 pvr2_hdw_cpureset_assert(hdw,0);
3532 }
d855497e
MI		 3533 break;
3534 }
3535
4db666cc
MI		 3536 hdw->fw_cpu_flag = (prom_flag == 0);
3537 if (hdw->fw_cpu_flag) {
3538 pvr2_trace(PVR2_TRACE_FIRMWARE,
3539 "Preparing to suck out CPU firmware");
3540 hdw->fw_size = 0x2000;
3541 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3542 if (!hdw->fw_buffer) {
3543 hdw->fw_size = 0;
3544 break;
3545 }
d855497e 3546
4db666cc
MI		 3547 /* We have to hold the CPU during firmware upload. */
3548 pvr2_hdw_cpureset_assert(hdw,1);
d855497e 3549
4db666cc
MI		 3550 /* download the firmware from address 0000-1fff in 2048
3551 (=0x800) bytes chunk. */
d855497e 3552
4db666cc
MI		 3553 pvr2_trace(PVR2_TRACE_FIRMWARE,
3554 "Grabbing CPU firmware");
3555 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3556 for(address = 0; address < hdw->fw_size;
3557 address += 0x800) {
3558 ret = usb_control_msg(hdw->usb_dev,pipe,
3559 0xa0,0xc0,
3560 address,0,
3561 hdw->fw_buffer+address,
3562 0x800,HZ);
3563 if (ret < 0) break;
3564 }
d855497e 3565
4db666cc
MI		 3566 pvr2_trace(PVR2_TRACE_FIRMWARE,
3567 "Done grabbing CPU firmware");
3568 } else {
3569 pvr2_trace(PVR2_TRACE_FIRMWARE,
3570 "Sucking down EEPROM contents");
3571 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3572 if (!hdw->fw_buffer) {
3573 pvr2_trace(PVR2_TRACE_FIRMWARE,
3574 "EEPROM content suck failed.");
3575 break;
3576 }
3577 hdw->fw_size = EEPROM_SIZE;
3578 pvr2_trace(PVR2_TRACE_FIRMWARE,
3579 "Done sucking down EEPROM contents");
3580 }
d855497e
MI		 3581
3582 } while (0); LOCK_GIVE(hdw->big_lock);
3583}
3584
3585
3586/* Return true if we're in a mode for retrieval CPU firmware */
3587int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3588{
5fa1247a 3589 return hdw->fw_buffer != NULL;
d855497e
MI		 3590}
3591
3592
3593int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3594 char *buf,unsigned int cnt)
3595{
3596 int ret = -EINVAL;
3597 LOCK_TAKE(hdw->big_lock); do {
3598 if (!buf) break;
3599 if (!cnt) break;
3600
3601 if (!hdw->fw_buffer) {
3602 ret = -EIO;
3603 break;
3604 }
3605
3606 if (offs >= hdw->fw_size) {
3607 pvr2_trace(PVR2_TRACE_FIRMWARE,
3608 "Read firmware data offs=%d EOF",
3609 offs);
3610 ret = 0;
3611 break;
3612 }
3613
3614 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3615
3616 memcpy(buf,hdw->fw_buffer+offs,cnt);
3617
3618 pvr2_trace(PVR2_TRACE_FIRMWARE,
3619 "Read firmware data offs=%d cnt=%d",
3620 offs,cnt);
3621 ret = cnt;
3622 } while (0); LOCK_GIVE(hdw->big_lock);
3623
3624 return ret;
3625}
3626
3627
fd5a75fe 3628int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
8079384e 3629 enum pvr2_v4l_type index)
d855497e 3630{
fd5a75fe 3631 switch (index) {
8079384e
MI		 3632 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3633 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3634 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
fd5a75fe
MI		 3635 default: return -1;
3636 }
d855497e
MI		 3637}
3638
3639
2fdf3d9c 3640/* Store a v4l minor device number */
fd5a75fe 3641void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
8079384e 3642 enum pvr2_v4l_type index,int v)
d855497e 3643{
fd5a75fe 3644 switch (index) {
8079384e
MI		 3645 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3646 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3647 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
fd5a75fe
MI		 3648 default: break;
3649 }
d855497e
MI		 3650}
3651
3652
7d12e780 3653static void pvr2_ctl_write_complete(struct urb *urb)
d855497e
MI		 3654{
3655 struct pvr2_hdw *hdw = urb->context;
3656 hdw->ctl_write_pend_flag = 0;
3657 if (hdw->ctl_read_pend_flag) return;
3658 complete(&hdw->ctl_done);
3659}
3660
3661
7d12e780 3662static void pvr2_ctl_read_complete(struct urb *urb)
d855497e
MI		 3663{
3664 struct pvr2_hdw *hdw = urb->context;
3665 hdw->ctl_read_pend_flag = 0;
3666 if (hdw->ctl_write_pend_flag) return;
3667 complete(&hdw->ctl_done);
3668}
3669
3670
3671static void pvr2_ctl_timeout(unsigned long data)
3672{
3673 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3674 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3675 hdw->ctl_timeout_flag = !0;
5e55d2ce 3676 if (hdw->ctl_write_pend_flag)
d855497e 3677 usb_unlink_urb(hdw->ctl_write_urb);
5e55d2ce 3678 if (hdw->ctl_read_pend_flag)
d855497e 3679 usb_unlink_urb(hdw->ctl_read_urb);
d855497e
MI		 3680 }
3681}
3682
3683
e61b6fc5
MI		 3684/* Issue a command and get a response from the device. This extended
3685 version includes a probe flag (which if set means that device errors
3686 should not be logged or treated as fatal) and a timeout in jiffies.
3687 This can be used to non-lethally probe the health of endpoint 1. */
07e337ee
AB		 3688static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3689 unsigned int timeout,int probe_fl,
3690 void *write_data,unsigned int write_len,
3691 void *read_data,unsigned int read_len)
d855497e
MI		 3692{
3693 unsigned int idx;
3694 int status = 0;
3695 struct timer_list timer;
3696 if (!hdw->ctl_lock_held) {
3697 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3698 "Attempted to execute control transfer"
3699 " without lock!!");
3700 return -EDEADLK;
3701 }
681c7399 3702 if (!hdw->flag_ok && !probe_fl) {
d855497e
MI		 3703 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3704 "Attempted to execute control transfer"
3705 " when device not ok");
3706 return -EIO;
3707 }
3708 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3709 if (!probe_fl) {
3710 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3711 "Attempted to execute control transfer"
3712 " when USB is disconnected");
3713 }
3714 return -ENOTTY;
3715 }
3716
3717 /* Ensure that we have sane parameters */
3718 if (!write_data) write_len = 0;
3719 if (!read_data) read_len = 0;
3720 if (write_len > PVR2_CTL_BUFFSIZE) {
3721 pvr2_trace(
3722 PVR2_TRACE_ERROR_LEGS,
3723 "Attempted to execute %d byte"
3724 " control-write transfer (limit=%d)",
3725 write_len,PVR2_CTL_BUFFSIZE);
3726 return -EINVAL;
3727 }
3728 if (read_len > PVR2_CTL_BUFFSIZE) {
3729 pvr2_trace(
3730 PVR2_TRACE_ERROR_LEGS,
3731 "Attempted to execute %d byte"
3732 " control-read transfer (limit=%d)",
3733 write_len,PVR2_CTL_BUFFSIZE);
3734 return -EINVAL;
3735 }
3736 if ((!write_len) && (!read_len)) {
3737 pvr2_trace(
3738 PVR2_TRACE_ERROR_LEGS,
3739 "Attempted to execute null control transfer?");
3740 return -EINVAL;
3741 }
3742
3743
3744 hdw->cmd_debug_state = 1;
3745 if (write_len) {
3746 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3747 } else {
3748 hdw->cmd_debug_code = 0;
3749 }
3750 hdw->cmd_debug_write_len = write_len;
3751 hdw->cmd_debug_read_len = read_len;
3752
3753 /* Initialize common stuff */
3754 init_completion(&hdw->ctl_done);
3755 hdw->ctl_timeout_flag = 0;
3756 hdw->ctl_write_pend_flag = 0;
3757 hdw->ctl_read_pend_flag = 0;
3758 init_timer(&timer);
3759 timer.expires = jiffies + timeout;
3760 timer.data = (unsigned long)hdw;
3761 timer.function = pvr2_ctl_timeout;
3762
3763 if (write_len) {
3764 hdw->cmd_debug_state = 2;
3765 /* Transfer write data to internal buffer */
3766 for (idx = 0; idx < write_len; idx++) {
3767 hdw->ctl_write_buffer[idx] =
3768 ((unsigned char *)write_data)[idx];
3769 }
3770 /* Initiate a write request */
3771 usb_fill_bulk_urb(hdw->ctl_write_urb,
3772 hdw->usb_dev,
3773 usb_sndbulkpipe(hdw->usb_dev,
3774 PVR2_CTL_WRITE_ENDPOINT),
3775 hdw->ctl_write_buffer,
3776 write_len,
3777 pvr2_ctl_write_complete,
3778 hdw);
3779 hdw->ctl_write_urb->actual_length = 0;
3780 hdw->ctl_write_pend_flag = !0;
3781 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3782 if (status < 0) {
3783 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3784 "Failed to submit write-control"
3785 " URB status=%d",status);
3786 hdw->ctl_write_pend_flag = 0;
3787 goto done;
3788 }
3789 }
3790
3791 if (read_len) {
3792 hdw->cmd_debug_state = 3;
3793 memset(hdw->ctl_read_buffer,0x43,read_len);
3794 /* Initiate a read request */
3795 usb_fill_bulk_urb(hdw->ctl_read_urb,
3796 hdw->usb_dev,
3797 usb_rcvbulkpipe(hdw->usb_dev,
3798 PVR2_CTL_READ_ENDPOINT),
3799 hdw->ctl_read_buffer,
3800 read_len,
3801 pvr2_ctl_read_complete,
3802 hdw);
3803 hdw->ctl_read_urb->actual_length = 0;
3804 hdw->ctl_read_pend_flag = !0;
3805 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3806 if (status < 0) {
3807 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3808 "Failed to submit read-control"
3809 " URB status=%d",status);
3810 hdw->ctl_read_pend_flag = 0;
3811 goto done;
3812 }
3813 }
3814
3815 /* Start timer */
3816 add_timer(&timer);
3817
3818 /* Now wait for all I/O to complete */
3819 hdw->cmd_debug_state = 4;
3820 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3821 wait_for_completion(&hdw->ctl_done);
3822 }
3823 hdw->cmd_debug_state = 5;
3824
3825 /* Stop timer */
3826 del_timer_sync(&timer);
3827
3828 hdw->cmd_debug_state = 6;
3829 status = 0;
3830
3831 if (hdw->ctl_timeout_flag) {
3832 status = -ETIMEDOUT;
3833 if (!probe_fl) {
3834 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3835 "Timed out control-write");
3836 }
3837 goto done;
3838 }
3839
3840 if (write_len) {
3841 /* Validate results of write request */
3842 if ((hdw->ctl_write_urb->status != 0) &&
3843 (hdw->ctl_write_urb->status != -ENOENT) &&
3844 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3845 (hdw->ctl_write_urb->status != -ECONNRESET)) {
3846 /* USB subsystem is reporting some kind of failure
3847 on the write */
3848 status = hdw->ctl_write_urb->status;
3849 if (!probe_fl) {
3850 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3851 "control-write URB failure,"
3852 " status=%d",
3853 status);
3854 }
3855 goto done;
3856 }
3857 if (hdw->ctl_write_urb->actual_length < write_len) {
3858 /* Failed to write enough data */
3859 status = -EIO;
3860 if (!probe_fl) {
3861 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3862 "control-write URB short,"
3863 " expected=%d got=%d",
3864 write_len,
3865 hdw->ctl_write_urb->actual_length);
3866 }
3867 goto done;
3868 }
3869 }
3870 if (read_len) {
3871 /* Validate results of read request */
3872 if ((hdw->ctl_read_urb->status != 0) &&
3873 (hdw->ctl_read_urb->status != -ENOENT) &&
3874 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3875 (hdw->ctl_read_urb->status != -ECONNRESET)) {
3876 /* USB subsystem is reporting some kind of failure
3877 on the read */
3878 status = hdw->ctl_read_urb->status;
3879 if (!probe_fl) {
3880 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3881 "control-read URB failure,"
3882 " status=%d",
3883 status);
3884 }
3885 goto done;
3886 }
3887 if (hdw->ctl_read_urb->actual_length < read_len) {
3888 /* Failed to read enough data */
3889 status = -EIO;
3890 if (!probe_fl) {
3891 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3892 "control-read URB short,"
3893 " expected=%d got=%d",
3894 read_len,
3895 hdw->ctl_read_urb->actual_length);
3896 }
3897 goto done;
3898 }
3899 /* Transfer retrieved data out from internal buffer */
3900 for (idx = 0; idx < read_len; idx++) {
3901 ((unsigned char *)read_data)[idx] =
3902 hdw->ctl_read_buffer[idx];
3903 }
3904 }
3905
3906 done:
3907
3908 hdw->cmd_debug_state = 0;
3909 if ((status < 0) && (!probe_fl)) {
681c7399 3910 pvr2_hdw_render_useless(hdw);
d855497e
MI		 3911 }
3912 return status;
3913}
3914
3915
3916int pvr2_send_request(struct pvr2_hdw *hdw,
3917 void *write_data,unsigned int write_len,
3918 void *read_data,unsigned int read_len)
3919{
3920 return pvr2_send_request_ex(hdw,HZ*4,0,
3921 write_data,write_len,
3922 read_data,read_len);
3923}
3924
1c9d10d4
MI		 3925
3926static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3927{
3928 int ret;
3929 unsigned int cnt = 1;
3930 unsigned int args = 0;
3931 LOCK_TAKE(hdw->ctl_lock);
3932 hdw->cmd_buffer[0] = cmdcode & 0xffu;
3933 args = (cmdcode >> 8) & 0xffu;
3934 args = (args > 2) ? 2 : args;
3935 if (args) {
3936 cnt += args;
3937 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3938 if (args > 1) {
3939 hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3940 }
3941 }
3942 if (pvrusb2_debug & PVR2_TRACE_INIT) {
3943 unsigned int idx;
3944 unsigned int ccnt,bcnt;
3945 char tbuf[50];
3946 cmdcode &= 0xffu;
3947 bcnt = 0;
3948 ccnt = scnprintf(tbuf+bcnt,
3949 sizeof(tbuf)-bcnt,
3950 "Sending FX2 command 0x%x",cmdcode);
3951 bcnt += ccnt;
3952 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3953 if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3954 ccnt = scnprintf(tbuf+bcnt,
3955 sizeof(tbuf)-bcnt,
3956 " \"%s\"",
3957 pvr2_fx2cmd_desc[idx].desc);
3958 bcnt += ccnt;
3959 break;
3960 }
3961 }
3962 if (args) {
3963 ccnt = scnprintf(tbuf+bcnt,
3964 sizeof(tbuf)-bcnt,
3965 " (%u",hdw->cmd_buffer[1]);
3966 bcnt += ccnt;
3967 if (args > 1) {
3968 ccnt = scnprintf(tbuf+bcnt,
3969 sizeof(tbuf)-bcnt,
3970 ",%u",hdw->cmd_buffer[2]);
3971 bcnt += ccnt;
3972 }
3973 ccnt = scnprintf(tbuf+bcnt,
3974 sizeof(tbuf)-bcnt,
3975 ")");
3976 bcnt += ccnt;
3977 }
3978 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3979 }
3980 ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3981 LOCK_GIVE(hdw->ctl_lock);
3982 return ret;
3983}
3984
3985
d855497e
MI		 3986int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3987{
3988 int ret;
3989
3990 LOCK_TAKE(hdw->ctl_lock);
3991
8d364363 3992 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
d855497e
MI		 3993 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3994 hdw->cmd_buffer[5] = 0;
3995 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3996 hdw->cmd_buffer[7] = reg & 0xff;
3997
3998
3999 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
4000
4001 LOCK_GIVE(hdw->ctl_lock);
4002
4003 return ret;
4004}
4005
4006
07e337ee 4007static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
d855497e
MI		 4008{
4009 int ret = 0;
4010
4011 LOCK_TAKE(hdw->ctl_lock);
4012
8d364363 4013 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
d855497e
MI		 4014 hdw->cmd_buffer[1] = 0;
4015 hdw->cmd_buffer[2] = 0;
4016 hdw->cmd_buffer[3] = 0;
4017 hdw->cmd_buffer[4] = 0;
4018 hdw->cmd_buffer[5] = 0;
4019 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4020 hdw->cmd_buffer[7] = reg & 0xff;
4021
4022 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
4023 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
4024
4025 LOCK_GIVE(hdw->ctl_lock);
4026
4027 return ret;
4028}
4029
4030
681c7399 4031void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
d855497e
MI		 4032{
4033 if (!hdw->flag_ok) return;
681c7399
MI		 4034 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4035 "Device being rendered inoperable");
d855497e 4036 if (hdw->vid_stream) {
a0fd1cb1 4037 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
d855497e 4038 }
681c7399
MI		 4039 hdw->flag_ok = 0;
4040 trace_stbit("flag_ok",hdw->flag_ok);
4041 pvr2_hdw_state_sched(hdw);
d855497e
MI		 4042}
4043
4044
4045void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
4046{
4047 int ret;
4048 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
a0fd1cb1 4049 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
011b15df 4050 if (ret == 0) {
d855497e
MI		 4051 ret = usb_reset_device(hdw->usb_dev);
4052 usb_unlock_device(hdw->usb_dev);
4053 } else {
4054 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4055 "Failed to lock USB device ret=%d",ret);
4056 }
4057 if (init_pause_msec) {
4058 pvr2_trace(PVR2_TRACE_INFO,
4059 "Waiting %u msec for hardware to settle",
4060 init_pause_msec);
4061 msleep(init_pause_msec);
4062 }
4063
4064}
4065
4066
4067void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
4068{
4069 char da[1];
4070 unsigned int pipe;
4071 int ret;
4072
4073 if (!hdw->usb_dev) return;
4074
4075 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4076
4077 da[0] = val ? 0x01 : 0x00;
4078
4079 /* Write the CPUCS register on the 8051. The lsb of the register
4080 is the reset bit; a 1 asserts reset while a 0 clears it. */
4081 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4082 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4083 if (ret < 0) {
4084 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4085 "cpureset_assert(%d) error=%d",val,ret);
4086 pvr2_hdw_render_useless(hdw);
4087 }
4088}
4089
4090
4091int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4092{
1c9d10d4 4093 return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
d855497e
MI		 4094}
4095
4096
e1edb19a
MK		 4097int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4098{
1c9d10d4 4099 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
e1edb19a
MK		 4100}
4101
1c9d10d4 4102
e1edb19a
MK		 4103int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4104{
1c9d10d4 4105 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
e1edb19a
MK		 4106}
4107
d855497e
MI		 4108
4109int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4110{
af78e16b
MI		 4111 pvr2_trace(PVR2_TRACE_INIT,
4112 "Requesting decoder reset");
4113 if (hdw->decoder_ctrl) {
4114 if (!hdw->decoder_ctrl->force_reset) {
4115 pvr2_trace(PVR2_TRACE_INIT,
4116 "Unable to reset decoder: not implemented");
4117 return -ENOTTY;
4118 }
4119 hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
4120 return 0;
4121 } else {
d855497e 4122 }
af78e16b
MI		 4123 if (hdw->decoder_client_id) {
4124 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4125 core, reset, 0);
4126 return 0;
d855497e 4127 }
d855497e 4128 pvr2_trace(PVR2_TRACE_INIT,
af78e16b
MI		 4129 "Unable to reset decoder: nothing attached");
4130 return -ENOTTY;
d855497e
MI		 4131}
4132
4133
62433e31 4134static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
84147f3d 4135{
1c9d10d4
MI		 4136 hdw->flag_ok = !0;
4137 return pvr2_issue_simple_cmd(hdw,
4138 FX2CMD_HCW_DEMOD_RESETIN |
4139 (1 << 8) |
4140 ((onoff ? 1 : 0) << 16));
84147f3d
MI		 4141}
4142
84147f3d 4143
62433e31 4144static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
84147f3d 4145{
1c9d10d4
MI		 4146 hdw->flag_ok = !0;
4147 return pvr2_issue_simple_cmd(hdw,(onoff ?
4148 FX2CMD_ONAIR_DTV_POWER_ON :
4149 FX2CMD_ONAIR_DTV_POWER_OFF));
84147f3d
MI		 4150}
4151
62433e31
MI		 4152
4153static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4154 int onoff)
84147f3d 4155{
1c9d10d4
MI		 4156 return pvr2_issue_simple_cmd(hdw,(onoff ?
4157 FX2CMD_ONAIR_DTV_STREAMING_ON :
4158 FX2CMD_ONAIR_DTV_STREAMING_OFF));
84147f3d
MI		 4159}
4160
62433e31
MI		 4161
4162static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4163{
4164 int cmode;
4165 /* Compare digital/analog desired setting with current setting. If
4166 they don't match, fix it... */
4167 cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4168 if (cmode == hdw->pathway_state) {
4169 /* They match; nothing to do */
4170 return;
4171 }
4172
4173 switch (hdw->hdw_desc->digital_control_scheme) {
4174 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4175 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4176 if (cmode == PVR2_PATHWAY_ANALOG) {
4177 /* If moving to analog mode, also force the decoder
4178 to reset. If no decoder is attached, then it's
4179 ok to ignore this because if/when the decoder
4180 attaches, it will reset itself at that time. */
4181 pvr2_hdw_cmd_decoder_reset(hdw);
4182 }
4183 break;
4184 case PVR2_DIGITAL_SCHEME_ONAIR:
4185 /* Supposedly we should always have the power on whether in
4186 digital or analog mode. But for now do what appears to
4187 work... */
bb0c2fe0 4188 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
62433e31
MI		 4189 break;
4190 default: break;
4191 }
4192
1b9c18c5 4193 pvr2_hdw_untrip_unlocked(hdw);
62433e31
MI		 4194 hdw->pathway_state = cmode;
4195}
4196
4197
e9b59f6e 4198static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
c55a97d7
MI		 4199{
4200 /* change some GPIO data
4201 *
4202 * note: bit d7 of dir appears to control the LED,
4203 * so we shut it off here.
4204 *
c55a97d7 4205 */
40381cb0 4206 if (onoff) {
c55a97d7 4207 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
40381cb0 4208 } else {
c55a97d7 4209 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
40381cb0 4210 }
c55a97d7 4211 pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
40381cb0 4212}
c55a97d7 4213
40381cb0
MI		 4214
4215typedef void (*led_method_func)(struct pvr2_hdw *,int);
4216
4217static led_method_func led_methods[] = {
4218 [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4219};
4220
4221
4222/* Toggle LED */
4223static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4224{
4225 unsigned int scheme_id;
4226 led_method_func fp;
4227
4228 if ((!onoff) == (!hdw->led_on)) return;
4229
4230 hdw->led_on = onoff != 0;
4231
4232 scheme_id = hdw->hdw_desc->led_scheme;
4233 if (scheme_id < ARRAY_SIZE(led_methods)) {
4234 fp = led_methods[scheme_id];
4235 } else {
4236 fp = NULL;
4237 }
4238
4239 if (fp) (*fp)(hdw,onoff);
c55a97d7
MI		 4240}
4241
4242
e61b6fc5 4243/* Stop / start video stream transport */
07e337ee 4244static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
d855497e 4245{
bb0c2fe0
MI		 4246 int ret;
4247
4248 /* If we're in analog mode, then just issue the usual analog
4249 command. */
4250 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4251 return pvr2_issue_simple_cmd(hdw,
4252 (runFl ?
4253 FX2CMD_STREAMING_ON :
4254 FX2CMD_STREAMING_OFF));
4255 /*Note: Not reached */
4256 }
4257
4258 if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4259 /* Whoops, we don't know what mode we're in... */
4260 return -EINVAL;
4261 }
4262
4263 /* To get here we have to be in digital mode. The mechanism here
4264 is unfortunately different for different vendors. So we switch
4265 on the device's digital scheme attribute in order to figure out
4266 what to do. */
4267 switch (hdw->hdw_desc->digital_control_scheme) {
4268 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4269 return pvr2_issue_simple_cmd(hdw,
4270 (runFl ?
4271 FX2CMD_HCW_DTV_STREAMING_ON :
4272 FX2CMD_HCW_DTV_STREAMING_OFF));
4273 case PVR2_DIGITAL_SCHEME_ONAIR:
4274 ret = pvr2_issue_simple_cmd(hdw,
4275 (runFl ?
4276 FX2CMD_STREAMING_ON :
4277 FX2CMD_STREAMING_OFF));
4278 if (ret) return ret;
4279 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4280 default:
4281 return -EINVAL;
62433e31 4282 }
d855497e
MI		 4283}
4284
4285
62433e31
MI		 4286/* Evaluate whether or not state_pathway_ok can change */
4287static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4288{
4289 if (hdw->state_pathway_ok) {
4290 /* Nothing to do if pathway is already ok */
4291 return 0;
4292 }
4293 if (!hdw->state_pipeline_idle) {
4294 /* Not allowed to change anything if pipeline is not idle */
4295 return 0;
4296 }
4297 pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4298 hdw->state_pathway_ok = !0;
e9db1ff2 4299 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 4300 return !0;
4301}
4302
4303
681c7399
MI		 4304/* Evaluate whether or not state_encoder_ok can change */
4305static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4306{
4307 if (hdw->state_encoder_ok) return 0;
4308 if (hdw->flag_tripped) return 0;
4309 if (hdw->state_encoder_run) return 0;
4310 if (hdw->state_encoder_config) return 0;
4311 if (hdw->state_decoder_run) return 0;
4312 if (hdw->state_usbstream_run) return 0;
72998b71
MI		 4313 if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4314 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4315 } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4316 return 0;
4317 }
4318
681c7399
MI		 4319 if (pvr2_upload_firmware2(hdw) < 0) {
4320 hdw->flag_tripped = !0;
4321 trace_stbit("flag_tripped",hdw->flag_tripped);
4322 return !0;
4323 }
4324 hdw->state_encoder_ok = !0;
4325 trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4326 return !0;
4327}
4328
4329
4330/* Evaluate whether or not state_encoder_config can change */
4331static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4332{
4333 if (hdw->state_encoder_config) {
4334 if (hdw->state_encoder_ok) {
4335 if (hdw->state_pipeline_req &&
4336 !hdw->state_pipeline_pause) return 0;
4337 }
4338 hdw->state_encoder_config = 0;
4339 hdw->state_encoder_waitok = 0;
4340 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4341 /* paranoia - solve race if timer just completed */
4342 del_timer_sync(&hdw->encoder_wait_timer);
4343 } else {
62433e31
MI		 4344 if (!hdw->state_pathway_ok ||
4345 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4346 !hdw->state_encoder_ok ||
681c7399
MI		 4347 !hdw->state_pipeline_idle ||
4348 hdw->state_pipeline_pause ||
4349 !hdw->state_pipeline_req ||
4350 !hdw->state_pipeline_config) {
4351 /* We must reset the enforced wait interval if
4352 anything has happened that might have disturbed
4353 the encoder. This should be a rare case. */
4354 if (timer_pending(&hdw->encoder_wait_timer)) {
4355 del_timer_sync(&hdw->encoder_wait_timer);
4356 }
4357 if (hdw->state_encoder_waitok) {
4358 /* Must clear the state - therefore we did
4359 something to a state bit and must also
4360 return true. */
4361 hdw->state_encoder_waitok = 0;
4362 trace_stbit("state_encoder_waitok",
4363 hdw->state_encoder_waitok);
4364 return !0;
4365 }
4366 return 0;
4367 }
4368 if (!hdw->state_encoder_waitok) {
4369 if (!timer_pending(&hdw->encoder_wait_timer)) {
4370 /* waitok flag wasn't set and timer isn't
4371 running. Check flag once more to avoid
4372 a race then start the timer. This is
4373 the point when we measure out a minimal
4374 quiet interval before doing something to
4375 the encoder. */
4376 if (!hdw->state_encoder_waitok) {
4377 hdw->encoder_wait_timer.expires =
83ce57aa
MI		 4378 jiffies +
4379 (HZ * TIME_MSEC_ENCODER_WAIT
4380 / 1000);
681c7399
MI		 4381 add_timer(&hdw->encoder_wait_timer);
4382 }
4383 }
4384 /* We can't continue until we know we have been
4385 quiet for the interval measured by this
4386 timer. */
4387 return 0;
4388 }
4389 pvr2_encoder_configure(hdw);
4390 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4391 }
4392 trace_stbit("state_encoder_config",hdw->state_encoder_config);
4393 return !0;
4394}
4395
4396
d913d630
MI		 4397/* Return true if the encoder should not be running. */
4398static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4399{
4400 if (!hdw->state_encoder_ok) {
4401 /* Encoder isn't healthy at the moment, so stop it. */
4402 return !0;
4403 }
4404 if (!hdw->state_pathway_ok) {
4405 /* Mode is not understood at the moment (i.e. it wants to
4406 change), so encoder must be stopped. */
4407 return !0;
4408 }
4409
4410 switch (hdw->pathway_state) {
4411 case PVR2_PATHWAY_ANALOG:
4412 if (!hdw->state_decoder_run) {
4413 /* We're in analog mode and the decoder is not
4414 running; thus the encoder should be stopped as
4415 well. */
4416 return !0;
4417 }
4418 break;
4419 case PVR2_PATHWAY_DIGITAL:
4420 if (hdw->state_encoder_runok) {
4421 /* This is a funny case. We're in digital mode so
4422 really the encoder should be stopped. However
4423 if it really is running, only kill it after
4424 runok has been set. This gives a chance for the
4425 onair quirk to function (encoder must run
4426 briefly first, at least once, before onair
4427 digital streaming can work). */
4428 return !0;
4429 }
4430 break;
4431 default:
4432 /* Unknown mode; so encoder should be stopped. */
4433 return !0;
4434 }
4435
4436 /* If we get here, we haven't found a reason to stop the
4437 encoder. */
4438 return 0;
4439}
4440
4441
4442/* Return true if the encoder should be running. */
4443static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4444{
4445 if (!hdw->state_encoder_ok) {
4446 /* Don't run the encoder if it isn't healthy... */
4447 return 0;
4448 }
4449 if (!hdw->state_pathway_ok) {
4450 /* Don't run the encoder if we don't (yet) know what mode
4451 we need to be in... */
4452 return 0;
4453 }
4454
4455 switch (hdw->pathway_state) {
4456 case PVR2_PATHWAY_ANALOG:
4457 if (hdw->state_decoder_run) {
4458 /* In analog mode, if the decoder is running, then
4459 run the encoder. */
4460 return !0;
4461 }
4462 break;
4463 case PVR2_PATHWAY_DIGITAL:
4464 if ((hdw->hdw_desc->digital_control_scheme ==
4465 PVR2_DIGITAL_SCHEME_ONAIR) &&
4466 !hdw->state_encoder_runok) {
4467 /* This is a quirk. OnAir hardware won't stream
4468 digital until the encoder has been run at least
4469 once, for a minimal period of time (empiricially
4470 measured to be 1/4 second). So if we're on
4471 OnAir hardware and the encoder has never been
4472 run at all, then start the encoder. Normal
4473 state machine logic in the driver will
4474 automatically handle the remaining bits. */
4475 return !0;
4476 }
4477 break;
4478 default:
4479 /* For completeness (unknown mode; encoder won't run ever) */
4480 break;
4481 }
4482 /* If we get here, then we haven't found any reason to run the
4483 encoder, so don't run it. */
4484 return 0;
4485}
4486
4487
681c7399
MI		 4488/* Evaluate whether or not state_encoder_run can change */
4489static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4490{
4491 if (hdw->state_encoder_run) {
d913d630 4492 if (!state_check_disable_encoder_run(hdw)) return 0;
681c7399 4493 if (hdw->state_encoder_ok) {
d913d630 4494 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 4495 if (pvr2_encoder_stop(hdw) < 0) return !0;
4496 }
4497 hdw->state_encoder_run = 0;
4498 } else {
d913d630 4499 if (!state_check_enable_encoder_run(hdw)) return 0;
681c7399
MI		 4500 if (pvr2_encoder_start(hdw) < 0) return !0;
4501 hdw->state_encoder_run = !0;
d913d630
MI		 4502 if (!hdw->state_encoder_runok) {
4503 hdw->encoder_run_timer.expires =
83ce57aa 4504 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
d913d630
MI		 4505 add_timer(&hdw->encoder_run_timer);
4506 }
681c7399
MI		 4507 }
4508 trace_stbit("state_encoder_run",hdw->state_encoder_run);
4509 return !0;
4510}
4511
4512
4513/* Timeout function for quiescent timer. */
4514static void pvr2_hdw_quiescent_timeout(unsigned long data)
4515{
4516 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4517 hdw->state_decoder_quiescent = !0;
4518 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4519 hdw->state_stale = !0;
4520 queue_work(hdw->workqueue,&hdw->workpoll);
4521}
4522
4523
4524/* Timeout function for encoder wait timer. */
4525static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4526{
4527 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4528 hdw->state_encoder_waitok = !0;
4529 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4530 hdw->state_stale = !0;
4531 queue_work(hdw->workqueue,&hdw->workpoll);
4532}
4533
4534
d913d630
MI		 4535/* Timeout function for encoder run timer. */
4536static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4537{
4538 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4539 if (!hdw->state_encoder_runok) {
4540 hdw->state_encoder_runok = !0;
4541 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4542 hdw->state_stale = !0;
4543 queue_work(hdw->workqueue,&hdw->workpoll);
4544 }
4545}
4546
4547
681c7399
MI		 4548/* Evaluate whether or not state_decoder_run can change */
4549static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4550{
4551 if (hdw->state_decoder_run) {
4552 if (hdw->state_encoder_ok) {
4553 if (hdw->state_pipeline_req &&
62433e31
MI		 4554 !hdw->state_pipeline_pause &&
4555 hdw->state_pathway_ok) return 0;
681c7399
MI		 4556 }
4557 if (!hdw->flag_decoder_missed) {
4558 pvr2_decoder_enable(hdw,0);
4559 }
4560 hdw->state_decoder_quiescent = 0;
4561 hdw->state_decoder_run = 0;
4562 /* paranoia - solve race if timer just completed */
4563 del_timer_sync(&hdw->quiescent_timer);
4564 } else {
4565 if (!hdw->state_decoder_quiescent) {
4566 if (!timer_pending(&hdw->quiescent_timer)) {
4567 /* We don't do something about the
4568 quiescent timer until right here because
4569 we also want to catch cases where the
4570 decoder was already not running (like
4571 after initialization) as opposed to
4572 knowing that we had just stopped it.
4573 The second flag check is here to cover a
4574 race - the timer could have run and set
4575 this flag just after the previous check
4576 but before we did the pending check. */
4577 if (!hdw->state_decoder_quiescent) {
4578 hdw->quiescent_timer.expires =
83ce57aa
MI		 4579 jiffies +
4580 (HZ * TIME_MSEC_DECODER_WAIT
4581 / 1000);
681c7399
MI		 4582 add_timer(&hdw->quiescent_timer);
4583 }
4584 }
4585 /* Don't allow decoder to start again until it has
4586 been quiesced first. This little detail should
4587 hopefully further stabilize the encoder. */
4588 return 0;
4589 }
62433e31
MI		 4590 if (!hdw->state_pathway_ok ||
4591 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4592 !hdw->state_pipeline_req ||
681c7399
MI		 4593 hdw->state_pipeline_pause ||
4594 !hdw->state_pipeline_config ||
4595 !hdw->state_encoder_config ||
4596 !hdw->state_encoder_ok) return 0;
4597 del_timer_sync(&hdw->quiescent_timer);
4598 if (hdw->flag_decoder_missed) return 0;
4599 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4600 hdw->state_decoder_quiescent = 0;
4601 hdw->state_decoder_run = !0;
4602 }
4603 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4604 trace_stbit("state_decoder_run",hdw->state_decoder_run);
4605 return !0;
4606}
4607
4608
4609/* Evaluate whether or not state_usbstream_run can change */
4610static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4611{
4612 if (hdw->state_usbstream_run) {
72998b71 4613 int fl = !0;
62433e31 4614 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
72998b71
MI		 4615 fl = (hdw->state_encoder_ok &&
4616 hdw->state_encoder_run);
4617 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4618 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4619 fl = hdw->state_encoder_ok;
4620 }
4621 if (fl &&
4622 hdw->state_pipeline_req &&
4623 !hdw->state_pipeline_pause &&
4624 hdw->state_pathway_ok) {
4625 return 0;
681c7399
MI		 4626 }
4627 pvr2_hdw_cmd_usbstream(hdw,0);
4628 hdw->state_usbstream_run = 0;
4629 } else {
62433e31
MI		 4630 if (!hdw->state_pipeline_req ||
4631 hdw->state_pipeline_pause ||
4632 !hdw->state_pathway_ok) return 0;
4633 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4634 if (!hdw->state_encoder_ok ||
4635 !hdw->state_encoder_run) return 0;
72998b71
MI		 4636 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4637 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4638 if (!hdw->state_encoder_ok) return 0;
d913d630
MI		 4639 if (hdw->state_encoder_run) return 0;
4640 if (hdw->hdw_desc->digital_control_scheme ==
4641 PVR2_DIGITAL_SCHEME_ONAIR) {
4642 /* OnAir digital receivers won't stream
4643 unless the analog encoder has run first.
4644 Why? I have no idea. But don't even
4645 try until we know the analog side is
4646 known to have run. */
4647 if (!hdw->state_encoder_runok) return 0;
4648 }
62433e31 4649 }
681c7399
MI		 4650 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4651 hdw->state_usbstream_run = !0;
4652 }
4653 trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4654 return !0;
4655}
4656
4657
4658/* Attempt to configure pipeline, if needed */
4659static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4660{
4661 if (hdw->state_pipeline_config ||
4662 hdw->state_pipeline_pause) return 0;
4663 pvr2_hdw_commit_execute(hdw);
4664 return !0;
4665}
4666
4667
4668/* Update pipeline idle and pipeline pause tracking states based on other
4669 inputs. This must be called whenever the other relevant inputs have
4670 changed. */
4671static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4672{
4673 unsigned int st;
4674 int updatedFl = 0;
4675 /* Update pipeline state */
4676 st = !(hdw->state_encoder_run ||
4677 hdw->state_decoder_run ||
4678 hdw->state_usbstream_run ||
4679 (!hdw->state_decoder_quiescent));
4680 if (!st != !hdw->state_pipeline_idle) {
4681 hdw->state_pipeline_idle = st;
4682 updatedFl = !0;
4683 }
4684 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4685 hdw->state_pipeline_pause = 0;
4686 updatedFl = !0;
4687 }
4688 return updatedFl;
4689}
4690
4691
4692typedef int (*state_eval_func)(struct pvr2_hdw *);
4693
4694/* Set of functions to be run to evaluate various states in the driver. */
ebff0330 4695static const state_eval_func eval_funcs[] = {
62433e31 4696 state_eval_pathway_ok,
681c7399
MI		 4697 state_eval_pipeline_config,
4698 state_eval_encoder_ok,
4699 state_eval_encoder_config,
4700 state_eval_decoder_run,
4701 state_eval_encoder_run,
4702 state_eval_usbstream_run,
4703};
4704
4705
4706/* Process various states and return true if we did anything interesting. */
4707static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4708{
4709 unsigned int i;
4710 int state_updated = 0;
4711 int check_flag;
4712
4713 if (!hdw->state_stale) return 0;
4714 if ((hdw->fw1_state != FW1_STATE_OK) ||
4715 !hdw->flag_ok) {
4716 hdw->state_stale = 0;
4717 return !0;
4718 }
4719 /* This loop is the heart of the entire driver. It keeps trying to
4720 evaluate various bits of driver state until nothing changes for
4721 one full iteration. Each "bit of state" tracks some global
4722 aspect of the driver, e.g. whether decoder should run, if
4723 pipeline is configured, usb streaming is on, etc. We separately
4724 evaluate each of those questions based on other driver state to
4725 arrive at the correct running configuration. */
4726 do {
4727 check_flag = 0;
4728 state_update_pipeline_state(hdw);
4729 /* Iterate over each bit of state */
4730 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4731 if ((*eval_funcs[i])(hdw)) {
4732 check_flag = !0;
4733 state_updated = !0;
4734 state_update_pipeline_state(hdw);
4735 }
4736 }
4737 } while (check_flag && hdw->flag_ok);
4738 hdw->state_stale = 0;
4739 trace_stbit("state_stale",hdw->state_stale);
4740 return state_updated;
4741}
4742
4743
1cb03b76
MI		 4744static unsigned int print_input_mask(unsigned int msk,
4745 char *buf,unsigned int acnt)
4746{
4747 unsigned int idx,ccnt;
4748 unsigned int tcnt = 0;
4749 for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4750 if (!((1 << idx) & msk)) continue;
4751 ccnt = scnprintf(buf+tcnt,
4752 acnt-tcnt,
4753 "%s%s",
4754 (tcnt ? ", " : ""),
4755 control_values_input[idx]);
4756 tcnt += ccnt;
4757 }
4758 return tcnt;
4759}
4760
4761
62433e31
MI		 4762static const char *pvr2_pathway_state_name(int id)
4763{
4764 switch (id) {
4765 case PVR2_PATHWAY_ANALOG: return "analog";
4766 case PVR2_PATHWAY_DIGITAL: return "digital";
4767 default: return "unknown";
4768 }
4769}
4770
4771
681c7399
MI		 4772static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4773 char *buf,unsigned int acnt)
4774{
4775 switch (which) {
4776 case 0:
4777 return scnprintf(
4778 buf,acnt,
e9db1ff2 4779 "driver:%s%s%s%s%s <mode=%s>",
681c7399
MI		 4780 (hdw->flag_ok ? " <ok>" : " <fail>"),
4781 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4782 (hdw->flag_disconnected ? " <disconnected>" :
4783 " <connected>"),
4784 (hdw->flag_tripped ? " <tripped>" : ""),
62433e31
MI		 4785 (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4786 pvr2_pathway_state_name(hdw->pathway_state));
4787
681c7399
MI		 4788 case 1:
4789 return scnprintf(
4790 buf,acnt,
4791 "pipeline:%s%s%s%s",
4792 (hdw->state_pipeline_idle ? " <idle>" : ""),
4793 (hdw->state_pipeline_config ?
4794 " <configok>" : " <stale>"),
4795 (hdw->state_pipeline_req ? " <req>" : ""),
4796 (hdw->state_pipeline_pause ? " <pause>" : ""));
4797 case 2:
4798 return scnprintf(
4799 buf,acnt,
62433e31 4800 "worker:%s%s%s%s%s%s%s",
681c7399
MI		 4801 (hdw->state_decoder_run ?
4802 " <decode:run>" :
4803 (hdw->state_decoder_quiescent ?
4804 "" : " <decode:stop>")),
4805 (hdw->state_decoder_quiescent ?
4806 " <decode:quiescent>" : ""),
4807 (hdw->state_encoder_ok ?
4808 "" : " <encode:init>"),
4809 (hdw->state_encoder_run ?
d913d630
MI		 4810 (hdw->state_encoder_runok ?
4811 " <encode:run>" :
4812 " <encode:firstrun>") :
4813 (hdw->state_encoder_runok ?
4814 " <encode:stop>" :
4815 " <encode:virgin>")),
681c7399
MI		 4816 (hdw->state_encoder_config ?
4817 " <encode:configok>" :
4818 (hdw->state_encoder_waitok ?
b9a37d91 4819 "" : " <encode:waitok>")),
681c7399 4820 (hdw->state_usbstream_run ?
62433e31
MI		 4821 " <usb:run>" : " <usb:stop>"),
4822 (hdw->state_pathway_ok ?
e9db1ff2 4823 " <pathway:ok>" : ""));
681c7399
MI		 4824 case 3:
4825 return scnprintf(
4826 buf,acnt,
4827 "state: %s",
4828 pvr2_get_state_name(hdw->master_state));
ad0992e9 4829 case 4: {
1cb03b76
MI		 4830 unsigned int tcnt = 0;
4831 unsigned int ccnt;
4832
4833 ccnt = scnprintf(buf,
4834 acnt,
4835 "Hardware supported inputs: ");
4836 tcnt += ccnt;
4837 tcnt += print_input_mask(hdw->input_avail_mask,
4838 buf+tcnt,
4839 acnt-tcnt);
4840 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4841 ccnt = scnprintf(buf+tcnt,
4842 acnt-tcnt,
4843 "; allowed inputs: ");
4844 tcnt += ccnt;
4845 tcnt += print_input_mask(hdw->input_allowed_mask,
4846 buf+tcnt,
4847 acnt-tcnt);
4848 }
4849 return tcnt;
4850 }
4851 case 5: {
ad0992e9
MI		 4852 struct pvr2_stream_stats stats;
4853 if (!hdw->vid_stream) break;
4854 pvr2_stream_get_stats(hdw->vid_stream,
4855 &stats,
4856 0);
4857 return scnprintf(
4858 buf,acnt,
4859 "Bytes streamed=%u"
4860 " URBs: queued=%u idle=%u ready=%u"
4861 " processed=%u failed=%u",
4862 stats.bytes_processed,
4863 stats.buffers_in_queue,
4864 stats.buffers_in_idle,
4865 stats.buffers_in_ready,
4866 stats.buffers_processed,
4867 stats.buffers_failed);
4868 }
858f910e
MI		 4869 case 6: {
4870 struct v4l2_subdev *sd;
4871 unsigned int tcnt = 0;
4872 unsigned int ccnt;
4873 const char *p;
4874 unsigned int id;
4875 ccnt = scnprintf(buf,
4876 acnt,
5f757ddd 4877 "Associated v4l2_subdev drivers:");
858f910e
MI		 4878 tcnt += ccnt;
4879 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4880 id = sd->grp_id;
4881 p = NULL;
4882 if (id < ARRAY_SIZE(module_names)) {
4883 p = module_names[id];
4884 }
5f757ddd
MI		 4885 if (p) {
4886 ccnt = scnprintf(buf + tcnt,
4887 acnt - tcnt,
4888 " %s", p);
4889 } else {
4890 ccnt = scnprintf(buf + tcnt,
4891 acnt - tcnt,
4892 " (unknown id=%u)", id);
4893 }
4894 tcnt += ccnt;
858f910e
MI		 4895 }
4896 return tcnt;
4897 }
681c7399
MI		 4898 default: break;
4899 }
4900 return 0;
4901}
4902
4903
4904unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4905 char *buf,unsigned int acnt)
4906{
4907 unsigned int bcnt,ccnt,idx;
4908 bcnt = 0;
4909 LOCK_TAKE(hdw->big_lock);
4910 for (idx = 0; ; idx++) {
4911 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4912 if (!ccnt) break;
4913 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4914 if (!acnt) break;
4915 buf[0] = '\n'; ccnt = 1;
4916 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4917 }
4918 LOCK_GIVE(hdw->big_lock);
4919 return bcnt;
4920}
4921
4922
4923static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4924{
4925 char buf[128];
4926 unsigned int idx,ccnt;
4927
4928 for (idx = 0; ; idx++) {
4929 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4930 if (!ccnt) break;
4931 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4932 }
4933}
4934
4935
4936/* Evaluate and update the driver's current state, taking various actions
4937 as appropriate for the update. */
4938static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4939{
4940 unsigned int st;
4941 int state_updated = 0;
4942 int callback_flag = 0;
1b9c18c5 4943 int analog_mode;
681c7399
MI		 4944
4945 pvr2_trace(PVR2_TRACE_STBITS,
4946 "Drive state check START");
4947 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4948 pvr2_hdw_state_log_state(hdw);
4949 }
4950
4951 /* Process all state and get back over disposition */
4952 state_updated = pvr2_hdw_state_update(hdw);
4953
1b9c18c5
MI		 4954 analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4955
681c7399
MI		 4956 /* Update master state based upon all other states. */
4957 if (!hdw->flag_ok) {
4958 st = PVR2_STATE_DEAD;
4959 } else if (hdw->fw1_state != FW1_STATE_OK) {
4960 st = PVR2_STATE_COLD;
72998b71
MI		 4961 } else if ((analog_mode ||
4962 hdw->hdw_desc->flag_digital_requires_cx23416) &&
4963 !hdw->state_encoder_ok) {
681c7399 4964 st = PVR2_STATE_WARM;
1b9c18c5
MI		 4965 } else if (hdw->flag_tripped ||
4966 (analog_mode && hdw->flag_decoder_missed)) {
681c7399 4967 st = PVR2_STATE_ERROR;
62433e31 4968 } else if (hdw->state_usbstream_run &&
1b9c18c5 4969 (!analog_mode ||
62433e31 4970 (hdw->state_encoder_run && hdw->state_decoder_run))) {
681c7399
MI		 4971 st = PVR2_STATE_RUN;
4972 } else {
4973 st = PVR2_STATE_READY;
4974 }
4975 if (hdw->master_state != st) {
4976 pvr2_trace(PVR2_TRACE_STATE,
4977 "Device state change from %s to %s",
4978 pvr2_get_state_name(hdw->master_state),
4979 pvr2_get_state_name(st));
40381cb0 4980 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
681c7399
MI		 4981 hdw->master_state = st;
4982 state_updated = !0;
4983 callback_flag = !0;
4984 }
4985 if (state_updated) {
4986 /* Trigger anyone waiting on any state changes here. */
4987 wake_up(&hdw->state_wait_data);
4988 }
4989
4990 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4991 pvr2_hdw_state_log_state(hdw);
4992 }
4993 pvr2_trace(PVR2_TRACE_STBITS,
4994 "Drive state check DONE callback=%d",callback_flag);
4995
4996 return callback_flag;
4997}
4998
4999
5000/* Cause kernel thread to check / update driver state */
5001static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
5002{
5003 if (hdw->state_stale) return;
5004 hdw->state_stale = !0;
5005 trace_stbit("state_stale",hdw->state_stale);
5006 queue_work(hdw->workqueue,&hdw->workpoll);
5007}
5008
5009
d855497e
MI		 5010int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
5011{
5012 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
5013}
5014
5015
5016int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
5017{
5018 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
5019}
5020
5021
5022int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
5023{
5024 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
5025}
5026
5027
5028int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
5029{
5030 u32 cval,nval;
5031 int ret;
5032 if (~msk) {
5033 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
5034 if (ret) return ret;
5035 nval = (cval & ~msk) | (val & msk);
5036 pvr2_trace(PVR2_TRACE_GPIO,
5037 "GPIO direction changing 0x%x:0x%x"
5038 " from 0x%x to 0x%x",
5039 msk,val,cval,nval);
5040 } else {
5041 nval = val;
5042 pvr2_trace(PVR2_TRACE_GPIO,
5043 "GPIO direction changing to 0x%x",nval);
5044 }
5045 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5046}
5047
5048
5049int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5050{
5051 u32 cval,nval;
5052 int ret;
5053 if (~msk) {
5054 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5055 if (ret) return ret;
5056 nval = (cval & ~msk) | (val & msk);
5057 pvr2_trace(PVR2_TRACE_GPIO,
5058 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5059 msk,val,cval,nval);
5060 } else {
5061 nval = val;
5062 pvr2_trace(PVR2_TRACE_GPIO,
5063 "GPIO output changing to 0x%x",nval);
5064 }
5065 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5066}
5067
5068
a51f5000
MI		 5069void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5070{
40f07111
MI		 5071 struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5072 memset(vtp, 0, sizeof(*vtp));
2641df36 5073 hdw->tuner_signal_stale = 0;
a51f5000 5074 pvr2_i2c_core_status_poll(hdw);
40f07111
MI		 5075 /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5076 using v4l2-subdev - therefore we can't support that AT ALL right
5077 now. (Of course, no sub-drivers seem to implement it either.
5078 But now it's a a chicken and egg problem...) */
5079 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner,
5080 &hdw->tuner_signal_info);
2641df36 5081 pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
40f07111
MI		 5082 " type=%u strength=%u audio=0x%x cap=0x%x"
5083 " low=%u hi=%u",
5084 vtp->type,
5085 vtp->signal, vtp->rxsubchans, vtp->capability,
5086 vtp->rangelow, vtp->rangehigh);
2641df36
MI		 5087
5088 /* We have to do this to avoid getting into constant polling if
5089 there's nobody to answer a poll of cropcap info. */
5090 hdw->cropcap_stale = 0;
a51f5000
MI		 5091}
5092
5093
7fb20fa3
MI		 5094unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5095{
5096 return hdw->input_avail_mask;
5097}
5098
5099
1cb03b76
MI		 5100unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5101{
5102 return hdw->input_allowed_mask;
5103}
5104
5105
5106static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5107{
5108 if (hdw->input_val != v) {
5109 hdw->input_val = v;
5110 hdw->input_dirty = !0;
5111 }
5112
5113 /* Handle side effects - if we switch to a mode that needs the RF
5114 tuner, then select the right frequency choice as well and mark
5115 it dirty. */
5116 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5117 hdw->freqSelector = 0;
5118 hdw->freqDirty = !0;
5119 } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5120 (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5121 hdw->freqSelector = 1;
5122 hdw->freqDirty = !0;
5123 }
5124 return 0;
5125}
5126
5127
5128int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5129 unsigned int change_mask,
5130 unsigned int change_val)
5131{
5132 int ret = 0;
5133 unsigned int nv,m,idx;
5134 LOCK_TAKE(hdw->big_lock);
5135 do {
5136 nv = hdw->input_allowed_mask & ~change_mask;
5137 nv |= (change_val & change_mask);
5138 nv &= hdw->input_avail_mask;
5139 if (!nv) {
5140 /* No legal modes left; return error instead. */
5141 ret = -EPERM;
5142 break;
5143 }
5144 hdw->input_allowed_mask = nv;
5145 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5146 /* Current mode is still in the allowed mask, so
5147 we're done. */
5148 break;
5149 }
5150 /* Select and switch to a mode that is still in the allowed
5151 mask */
5152 if (!hdw->input_allowed_mask) {
5153 /* Nothing legal; give up */
5154 break;
5155 }
5156 m = hdw->input_allowed_mask;
5157 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5158 if (!((1 << idx) & m)) continue;
5159 pvr2_hdw_set_input(hdw,idx);
5160 break;
5161 }
5162 } while (0);
5163 LOCK_GIVE(hdw->big_lock);
5164 return ret;
5165}
5166
5167
e61b6fc5 5168/* Find I2C address of eeprom */
07e337ee 5169static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
d855497e
MI		 5170{
5171 int result;
5172 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 5173 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 5174 result = pvr2_send_request(hdw,
5175 hdw->cmd_buffer,1,
5176 hdw->cmd_buffer,1);
5177 if (result < 0) break;
5178 result = hdw->cmd_buffer[0];
5179 } while(0); LOCK_GIVE(hdw->ctl_lock);
5180 return result;
5181}
5182
5183
32ffa9ae 5184int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
aecde8b5
HV		 5185 struct v4l2_dbg_match *match, u64 reg_id,
5186 int setFl, u64 *val_ptr)
32ffa9ae
MI		 5187{
5188#ifdef CONFIG_VIDEO_ADV_DEBUG
32ffa9ae 5189 struct pvr2_i2c_client *cp;
aecde8b5 5190 struct v4l2_dbg_register req;
6d98816f
MI		 5191 int stat = 0;
5192 int okFl = 0;
32ffa9ae 5193
201f5c9c
MI		 5194 if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5195
aecde8b5 5196 req.match = *match;
32ffa9ae
MI		 5197 req.reg = reg_id;
5198 if (setFl) req.val = *val_ptr;
d8f5b9ba
MI		 5199 /* It would be nice to know if a sub-device answered the request */
5200 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5201 if (!setFl) *val_ptr = req.val;
5202 if (!okFl) mutex_lock(&hdw->i2c_list_lock); do {
e77e2c2f 5203 list_for_each_entry(cp, &hdw->i2c_clients, list) {
8481a750
MI		 5204 if (!v4l2_chip_match_i2c_client(
5205 cp->client,
aecde8b5 5206 &req.match)) {
f3d092b8
HV		 5207 continue;
5208 }
32ffa9ae 5209 stat = pvr2_i2c_client_cmd(
52ebc763
TP		 5210 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
5211 VIDIOC_DBG_G_REGISTER),&req);
32ffa9ae 5212 if (!setFl) *val_ptr = req.val;
6d98816f
MI		 5213 okFl = !0;
5214 break;
32ffa9ae
MI		 5215 }
5216 } while (0); mutex_unlock(&hdw->i2c_list_lock);
6d98816f
MI		 5217 if (okFl) {
5218 return stat;
5219 }
32ffa9ae
MI		 5220 return -EINVAL;
5221#else
5222 return -ENOSYS;
5223#endif
5224}
5225
5226
d855497e
MI		 5227/*
5228 Stuff for Emacs to see, in order to encourage consistent editing style:
5229 *** Local Variables: ***
5230 *** mode: c ***
5231 *** fill-column: 75 ***
5232 *** tab-width: 8 ***
5233 *** c-basic-offset: 8 ***
5234 *** End: ***
5235 */
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