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V4L/DVB (11187): pvrusb2: Allow sub-devices to insert correctly
[mirror_ubuntu-artful-kernel.git] / drivers / media / video / pvrusb2 / pvrusb2-hdw.c
CommitLineData
d855497e
MI		 1/*
2 *
d855497e
MI		 3 *
4 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 *
19 */
20
21#include <linux/errno.h>
22#include <linux/string.h>
23#include <linux/slab.h>
24#include <linux/firmware.h>
d855497e 25#include <linux/videodev2.h>
32ffa9ae 26#include <media/v4l2-common.h>
d855497e
MI		 27#include "pvrusb2.h"
28#include "pvrusb2-std.h"
29#include "pvrusb2-util.h"
30#include "pvrusb2-hdw.h"
31#include "pvrusb2-i2c-core.h"
59af3367 32#include "pvrusb2-i2c-track.h"
d855497e
MI		 33#include "pvrusb2-tuner.h"
34#include "pvrusb2-eeprom.h"
35#include "pvrusb2-hdw-internal.h"
36#include "pvrusb2-encoder.h"
37#include "pvrusb2-debug.h"
8d364363 38#include "pvrusb2-fx2-cmd.h"
5f6dae80 39#include "pvrusb2-wm8775.h"
6f956512 40#include "pvrusb2-video-v4l.h"
634ba268 41#include "pvrusb2-cx2584x-v4l.h"
76891d65 42#include "pvrusb2-audio.h"
d855497e 43
1bde0289
MI		 44#define TV_MIN_FREQ 55250000L
45#define TV_MAX_FREQ 850000000L
25d8527a 46
83ce57aa
MI		 47/* This defines a minimum interval that the decoder must remain quiet
48 before we are allowed to start it running. */
49#define TIME_MSEC_DECODER_WAIT 50
50
51/* This defines a minimum interval that the encoder must remain quiet
fa98e594
MI		 52 before we are allowed to configure it. I had this originally set to
53 50msec, but Martin Dauskardt <martin.dauskardt@gmx.de> reports that
54 things work better when it's set to 100msec. */
55#define TIME_MSEC_ENCODER_WAIT 100
83ce57aa
MI		 56
57/* This defines the minimum interval that the encoder must successfully run
58 before we consider that the encoder has run at least once since its
59 firmware has been loaded. This measurement is in important for cases
60 where we can't do something until we know that the encoder has been run
61 at least once. */
62#define TIME_MSEC_ENCODER_OK 250
63
a0fd1cb1 64static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
8df0c87c 65static DEFINE_MUTEX(pvr2_unit_mtx);
d855497e 66
ff699e6b 67static int ctlchg;
ff699e6b 68static int procreload;
d855497e
MI		 69static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
70static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
71static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
ff699e6b 72static int init_pause_msec;
d855497e
MI		 73
74module_param(ctlchg, int, S_IRUGO|S_IWUSR);
75MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
76module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
77MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
d855497e
MI		 78module_param(procreload, int, S_IRUGO|S_IWUSR);
79MODULE_PARM_DESC(procreload,
80 "Attempt init failure recovery with firmware reload");
81module_param_array(tuner, int, NULL, 0444);
82MODULE_PARM_DESC(tuner,"specify installed tuner type");
83module_param_array(video_std, int, NULL, 0444);
84MODULE_PARM_DESC(video_std,"specify initial video standard");
85module_param_array(tolerance, int, NULL, 0444);
86MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
87
5a4f5da6
MK		 88/* US Broadcast channel 7 (175.25 MHz) */
89static int default_tv_freq = 175250000L;
90/* 104.3 MHz, a usable FM station for my area */
91static int default_radio_freq = 104300000L;
92
93module_param_named(tv_freq, default_tv_freq, int, 0444);
94MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
95module_param_named(radio_freq, default_radio_freq, int, 0444);
96MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
97
d855497e
MI		 98#define PVR2_CTL_WRITE_ENDPOINT 0x01
99#define PVR2_CTL_READ_ENDPOINT 0x81
100
101#define PVR2_GPIO_IN 0x9008
102#define PVR2_GPIO_OUT 0x900c
103#define PVR2_GPIO_DIR 0x9020
104
105#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
106
107#define PVR2_FIRMWARE_ENDPOINT 0x02
108
109/* size of a firmware chunk */
110#define FIRMWARE_CHUNK_SIZE 0x2000
111
edb9dcb8
MI		 112typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
113 struct v4l2_subdev *);
114
115static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
4ecbc28d 116 [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
6f956512 117 [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
76891d65 118 [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
634ba268 119 [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
edb9dcb8
MI		 120};
121
e9c64a78
MI		 122static const char *module_names[] = {
123 [PVR2_CLIENT_ID_MSP3400] = "msp3400",
124 [PVR2_CLIENT_ID_CX25840] = "cx25840",
125 [PVR2_CLIENT_ID_SAA7115] = "saa7115",
126 [PVR2_CLIENT_ID_TUNER] = "tuner",
127 [PVR2_CLIENT_ID_CS53132A] = "cs53132a",
5f6dae80 128 [PVR2_CLIENT_ID_WM8775] = "wm8775",
e9c64a78
MI		 129};
130
131
132static const unsigned char *module_i2c_addresses[] = {
133 [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
ae111f76 134 [PVR2_CLIENT_ID_WM8775] = "\x1b",
e9c64a78
MI		 135};
136
137
b30d2441
MI		 138/* Define the list of additional controls we'll dynamically construct based
139 on query of the cx2341x module. */
140struct pvr2_mpeg_ids {
141 const char *strid;
142 int id;
143};
144static const struct pvr2_mpeg_ids mpeg_ids[] = {
145 {
146 .strid = "audio_layer",
147 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
148 },{
149 .strid = "audio_bitrate",
150 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
151 },{
152 /* Already using audio_mode elsewhere :-( */
153 .strid = "mpeg_audio_mode",
154 .id = V4L2_CID_MPEG_AUDIO_MODE,
155 },{
156 .strid = "mpeg_audio_mode_extension",
157 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
158 },{
159 .strid = "audio_emphasis",
160 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
161 },{
162 .strid = "audio_crc",
163 .id = V4L2_CID_MPEG_AUDIO_CRC,
164 },{
165 .strid = "video_aspect",
166 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
167 },{
168 .strid = "video_b_frames",
169 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
170 },{
171 .strid = "video_gop_size",
172 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
173 },{
174 .strid = "video_gop_closure",
175 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
b30d2441
MI		 176 },{
177 .strid = "video_bitrate_mode",
178 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
179 },{
180 .strid = "video_bitrate",
181 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
182 },{
183 .strid = "video_bitrate_peak",
184 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
185 },{
186 .strid = "video_temporal_decimation",
187 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
188 },{
189 .strid = "stream_type",
190 .id = V4L2_CID_MPEG_STREAM_TYPE,
191 },{
192 .strid = "video_spatial_filter_mode",
193 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
194 },{
195 .strid = "video_spatial_filter",
196 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
197 },{
198 .strid = "video_luma_spatial_filter_type",
199 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
200 },{
201 .strid = "video_chroma_spatial_filter_type",
202 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
203 },{
204 .strid = "video_temporal_filter_mode",
205 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
206 },{
207 .strid = "video_temporal_filter",
208 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
209 },{
210 .strid = "video_median_filter_type",
211 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
212 },{
213 .strid = "video_luma_median_filter_top",
214 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
215 },{
216 .strid = "video_luma_median_filter_bottom",
217 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
218 },{
219 .strid = "video_chroma_median_filter_top",
220 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
221 },{
222 .strid = "video_chroma_median_filter_bottom",
223 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
224 }
225};
eca8ebfc 226#define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
c05c0462 227
434449f4 228
d855497e 229static const char *control_values_srate[] = {
434449f4
MI		 230 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
231 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
232 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
d855497e
MI		 233};
234
235
d855497e 236
d855497e
MI		 237static const char *control_values_input[] = {
238 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
29bf5b1d 239 [PVR2_CVAL_INPUT_DTV] = "dtv",
d855497e
MI		 240 [PVR2_CVAL_INPUT_RADIO] = "radio",
241 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
242 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
243};
244
245
246static const char *control_values_audiomode[] = {
247 [V4L2_TUNER_MODE_MONO] = "Mono",
248 [V4L2_TUNER_MODE_STEREO] = "Stereo",
249 [V4L2_TUNER_MODE_LANG1] = "Lang1",
250 [V4L2_TUNER_MODE_LANG2] = "Lang2",
251 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
252};
253
254
255static const char *control_values_hsm[] = {
256 [PVR2_CVAL_HSM_FAIL] = "Fail",
257 [PVR2_CVAL_HSM_HIGH] = "High",
258 [PVR2_CVAL_HSM_FULL] = "Full",
259};
260
261
681c7399
MI		 262static const char *pvr2_state_names[] = {
263 [PVR2_STATE_NONE] = "none",
264 [PVR2_STATE_DEAD] = "dead",
265 [PVR2_STATE_COLD] = "cold",
266 [PVR2_STATE_WARM] = "warm",
267 [PVR2_STATE_ERROR] = "error",
268 [PVR2_STATE_READY] = "ready",
269 [PVR2_STATE_RUN] = "run",
d855497e
MI		 270};
271
681c7399 272
694dca2b 273struct pvr2_fx2cmd_descdef {
1c9d10d4
MI		 274 unsigned char id;
275 unsigned char *desc;
276};
277
694dca2b 278static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
1c9d10d4
MI		 279 {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
280 {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
31335b13 281 {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
1c9d10d4
MI		 282 {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
283 {FX2CMD_REG_WRITE, "write encoder register"},
284 {FX2CMD_REG_READ, "read encoder register"},
285 {FX2CMD_MEMSEL, "encoder memsel"},
286 {FX2CMD_I2C_WRITE, "i2c write"},
287 {FX2CMD_I2C_READ, "i2c read"},
288 {FX2CMD_GET_USB_SPEED, "get USB speed"},
289 {FX2CMD_STREAMING_ON, "stream on"},
290 {FX2CMD_STREAMING_OFF, "stream off"},
291 {FX2CMD_FWPOST1, "fwpost1"},
292 {FX2CMD_POWER_OFF, "power off"},
293 {FX2CMD_POWER_ON, "power on"},
294 {FX2CMD_DEEP_RESET, "deep reset"},
295 {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
296 {FX2CMD_GET_IR_CODE, "get IR code"},
297 {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
298 {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
299 {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
300 {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
301 {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
302 {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
303 {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
304};
305
306
1cb03b76 307static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
681c7399
MI		 308static void pvr2_hdw_state_sched(struct pvr2_hdw *);
309static int pvr2_hdw_state_eval(struct pvr2_hdw *);
1bde0289 310static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
681c7399
MI		 311static void pvr2_hdw_worker_i2c(struct work_struct *work);
312static void pvr2_hdw_worker_poll(struct work_struct *work);
681c7399
MI		 313static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
314static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
315static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
07e337ee 316static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
681c7399 317static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
07e337ee 318static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
07e337ee
AB		 319static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
320static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
681c7399
MI		 321static void pvr2_hdw_quiescent_timeout(unsigned long);
322static void pvr2_hdw_encoder_wait_timeout(unsigned long);
d913d630 323static void pvr2_hdw_encoder_run_timeout(unsigned long);
1c9d10d4 324static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
07e337ee
AB		 325static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
326 unsigned int timeout,int probe_fl,
327 void *write_data,unsigned int write_len,
328 void *read_data,unsigned int read_len);
432907f7 329static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
d855497e 330
681c7399
MI		 331
332static void trace_stbit(const char *name,int val)
333{
334 pvr2_trace(PVR2_TRACE_STBITS,
335 "State bit %s <-- %s",
336 name,(val ? "true" : "false"));
337}
338
d855497e
MI		 339static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
340{
341 struct pvr2_hdw *hdw = cptr->hdw;
342 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
343 *vp = hdw->freqTable[hdw->freqProgSlot-1];
344 } else {
345 *vp = 0;
346 }
347 return 0;
348}
349
350static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
351{
352 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 353 unsigned int slotId = hdw->freqProgSlot;
354 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
355 hdw->freqTable[slotId-1] = v;
356 /* Handle side effects correctly - if we're tuned to this
357 slot, then forgot the slot id relation since the stored
358 frequency has been changed. */
359 if (hdw->freqSelector) {
360 if (hdw->freqSlotRadio == slotId) {
361 hdw->freqSlotRadio = 0;
362 }
363 } else {
364 if (hdw->freqSlotTelevision == slotId) {
365 hdw->freqSlotTelevision = 0;
366 }
367 }
d855497e
MI		 368 }
369 return 0;
370}
371
372static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
373{
374 *vp = cptr->hdw->freqProgSlot;
375 return 0;
376}
377
378static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
379{
380 struct pvr2_hdw *hdw = cptr->hdw;
381 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
382 hdw->freqProgSlot = v;
383 }
384 return 0;
385}
386
387static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
388{
1bde0289
MI		 389 struct pvr2_hdw *hdw = cptr->hdw;
390 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
d855497e
MI		 391 return 0;
392}
393
1bde0289 394static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
d855497e
MI		 395{
396 unsigned freq = 0;
397 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 398 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
399 if (slotId > 0) {
400 freq = hdw->freqTable[slotId-1];
401 if (!freq) return 0;
402 pvr2_hdw_set_cur_freq(hdw,freq);
d855497e 403 }
1bde0289
MI		 404 if (hdw->freqSelector) {
405 hdw->freqSlotRadio = slotId;
406 } else {
407 hdw->freqSlotTelevision = slotId;
d855497e
MI		 408 }
409 return 0;
410}
411
412static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
413{
1bde0289 414 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
d855497e
MI		 415 return 0;
416}
417
418static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
419{
420 return cptr->hdw->freqDirty != 0;
421}
422
423static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
424{
425 cptr->hdw->freqDirty = 0;
426}
427
428static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
429{
1bde0289 430 pvr2_hdw_set_cur_freq(cptr->hdw,v);
d855497e
MI		 431 return 0;
432}
433
e784bfb9 434static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
435{
432907f7
MI		 436 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
437 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
438 if (stat != 0) {
432907f7 439 return stat;
e784bfb9 440 }
432907f7 441 *left = cap->bounds.left;
e784bfb9 442 return 0;
443}
444
445static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
446{
432907f7
MI		 447 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
448 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
449 if (stat != 0) {
432907f7
MI		 450 return stat;
451 }
452 *left = cap->bounds.left;
453 if (cap->bounds.width > cptr->hdw->cropw_val) {
432907f7 454 *left += cap->bounds.width - cptr->hdw->cropw_val;
e784bfb9 455 }
456 return 0;
457}
458
459static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
460{
432907f7
MI		 461 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
462 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
463 if (stat != 0) {
432907f7 464 return stat;
e784bfb9 465 }
432907f7 466 *top = cap->bounds.top;
e784bfb9 467 return 0;
468}
469
432907f7 470static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
3ad9fc37 471{
432907f7
MI		 472 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
473 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
474 if (stat != 0) {
432907f7
MI		 475 return stat;
476 }
477 *top = cap->bounds.top;
478 if (cap->bounds.height > cptr->hdw->croph_val) {
432907f7 479 *top += cap->bounds.height - cptr->hdw->croph_val;
3ad9fc37
MI		 480 }
481 return 0;
482}
483
432907f7
MI		 484static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
485{
486 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
487 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
488 if (stat != 0) {
432907f7
MI		 489 return stat;
490 }
491 *val = 0;
492 if (cap->bounds.width > cptr->hdw->cropl_val) {
432907f7
MI		 493 *val = cap->bounds.width - cptr->hdw->cropl_val;
494 }
495 return 0;
496}
497
498static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
499{
500 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
501 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
502 if (stat != 0) {
432907f7
MI		 503 return stat;
504 }
505 *val = 0;
506 if (cap->bounds.height > cptr->hdw->cropt_val) {
432907f7
MI		 507 *val = cap->bounds.height - cptr->hdw->cropt_val;
508 }
509 return 0;
510}
511
512static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
513{
514 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
515 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
516 if (stat != 0) {
432907f7
MI		 517 return stat;
518 }
519 *val = cap->bounds.left;
520 return 0;
521}
522
523static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
524{
525 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
526 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
527 if (stat != 0) {
432907f7
MI		 528 return stat;
529 }
530 *val = cap->bounds.top;
531 return 0;
532}
533
534static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
535{
536 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
537 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
538 if (stat != 0) {
432907f7
MI		 539 return stat;
540 }
541 *val = cap->bounds.width;
542 return 0;
543}
544
545static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
546{
547 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
548 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
549 if (stat != 0) {
432907f7
MI		 550 return stat;
551 }
552 *val = cap->bounds.height;
553 return 0;
554}
555
556static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
557{
558 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
559 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
560 if (stat != 0) {
432907f7
MI		 561 return stat;
562 }
563 *val = cap->defrect.left;
564 return 0;
565}
566
567static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
568{
569 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
570 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
571 if (stat != 0) {
432907f7
MI		 572 return stat;
573 }
574 *val = cap->defrect.top;
575 return 0;
576}
577
578static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
579{
580 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
581 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
582 if (stat != 0) {
432907f7
MI		 583 return stat;
584 }
585 *val = cap->defrect.width;
586 return 0;
587}
588
589static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
590{
591 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
592 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
593 if (stat != 0) {
432907f7
MI		 594 return stat;
595 }
596 *val = cap->defrect.height;
597 return 0;
598}
599
600static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
601{
602 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
603 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
604 if (stat != 0) {
432907f7
MI		 605 return stat;
606 }
607 *val = cap->pixelaspect.numerator;
608 return 0;
609}
610
611static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
612{
613 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
614 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
615 if (stat != 0) {
432907f7
MI		 616 return stat;
617 }
618 *val = cap->pixelaspect.denominator;
619 return 0;
620}
621
622static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
e784bfb9 623{
432907f7
MI		 624 /* Actual maximum depends on the video standard in effect. */
625 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
626 *vp = 480;
e784bfb9 627 } else {
432907f7 628 *vp = 576;
e784bfb9 629 }
630 return 0;
631}
632
3ad9fc37
MI		 633static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
634{
989eb154
MI		 635 /* Actual minimum depends on device digitizer type. */
636 if (cptr->hdw->hdw_desc->flag_has_cx25840) {
3ad9fc37
MI		 637 *vp = 75;
638 } else {
639 *vp = 17;
640 }
641 return 0;
642}
643
1bde0289 644static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
5549f54f 645{
1bde0289
MI		 646 *vp = cptr->hdw->input_val;
647 return 0;
648}
649
29bf5b1d
MI		 650static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
651{
1cb03b76 652 return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
29bf5b1d
MI		 653}
654
1bde0289
MI		 655static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
656{
1cb03b76 657 return pvr2_hdw_set_input(cptr->hdw,v);
1bde0289
MI		 658}
659
660static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
661{
662 return cptr->hdw->input_dirty != 0;
663}
664
665static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
666{
667 cptr->hdw->input_dirty = 0;
668}
669
5549f54f 670
25d8527a
PK		 671static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
672{
644afdb9
MI		 673 unsigned long fv;
674 struct pvr2_hdw *hdw = cptr->hdw;
675 if (hdw->tuner_signal_stale) {
a51f5000 676 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 677 }
678 fv = hdw->tuner_signal_info.rangehigh;
679 if (!fv) {
680 /* Safety fallback */
25d8527a 681 *vp = TV_MAX_FREQ;
644afdb9 682 return 0;
25d8527a 683 }
644afdb9
MI		 684 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
685 fv = (fv * 125) / 2;
686 } else {
687 fv = fv * 62500;
688 }
689 *vp = fv;
25d8527a
PK		 690 return 0;
691}
692
693static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
694{
644afdb9
MI		 695 unsigned long fv;
696 struct pvr2_hdw *hdw = cptr->hdw;
697 if (hdw->tuner_signal_stale) {
a51f5000 698 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 699 }
700 fv = hdw->tuner_signal_info.rangelow;
701 if (!fv) {
702 /* Safety fallback */
25d8527a 703 *vp = TV_MIN_FREQ;
644afdb9
MI		 704 return 0;
705 }
706 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
707 fv = (fv * 125) / 2;
708 } else {
709 fv = fv * 62500;
25d8527a 710 }
644afdb9 711 *vp = fv;
25d8527a
PK		 712 return 0;
713}
714
b30d2441
MI		 715static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
716{
717 return cptr->hdw->enc_stale != 0;
718}
719
720static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
721{
722 cptr->hdw->enc_stale = 0;
681c7399 723 cptr->hdw->enc_unsafe_stale = 0;
b30d2441
MI		 724}
725
726static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
727{
728 int ret;
729 struct v4l2_ext_controls cs;
730 struct v4l2_ext_control c1;
731 memset(&cs,0,sizeof(cs));
732 memset(&c1,0,sizeof(c1));
733 cs.controls = &c1;
734 cs.count = 1;
735 c1.id = cptr->info->v4l_id;
01f1e44f 736 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
b30d2441
MI		 737 VIDIOC_G_EXT_CTRLS);
738 if (ret) return ret;
739 *vp = c1.value;
740 return 0;
741}
742
743static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
744{
745 int ret;
681c7399 746 struct pvr2_hdw *hdw = cptr->hdw;
b30d2441
MI		 747 struct v4l2_ext_controls cs;
748 struct v4l2_ext_control c1;
749 memset(&cs,0,sizeof(cs));
750 memset(&c1,0,sizeof(c1));
751 cs.controls = &c1;
752 cs.count = 1;
753 c1.id = cptr->info->v4l_id;
754 c1.value = v;
681c7399
MI		 755 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
756 hdw->state_encoder_run, &cs,
b30d2441 757 VIDIOC_S_EXT_CTRLS);
681c7399
MI		 758 if (ret == -EBUSY) {
759 /* Oops. cx2341x is telling us it's not safe to change
760 this control while we're capturing. Make a note of this
761 fact so that the pipeline will be stopped the next time
762 controls are committed. Then go on ahead and store this
763 change anyway. */
764 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
765 0, &cs,
766 VIDIOC_S_EXT_CTRLS);
767 if (!ret) hdw->enc_unsafe_stale = !0;
768 }
b30d2441 769 if (ret) return ret;
681c7399 770 hdw->enc_stale = !0;
b30d2441
MI		 771 return 0;
772}
773
774static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
775{
776 struct v4l2_queryctrl qctrl;
777 struct pvr2_ctl_info *info;
778 qctrl.id = cptr->info->v4l_id;
779 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
780 /* Strip out the const so we can adjust a function pointer. It's
781 OK to do this here because we know this is a dynamically created
782 control, so the underlying storage for the info pointer is (a)
783 private to us, and (b) not in read-only storage. Either we do
784 this or we significantly complicate the underlying control
785 implementation. */
786 info = (struct pvr2_ctl_info *)(cptr->info);
787 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
788 if (info->set_value) {
a0fd1cb1 789 info->set_value = NULL;
b30d2441
MI		 790 }
791 } else {
792 if (!(info->set_value)) {
793 info->set_value = ctrl_cx2341x_set;
794 }
795 }
796 return qctrl.flags;
797}
798
d855497e
MI		 799static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
800{
681c7399
MI		 801 *vp = cptr->hdw->state_pipeline_req;
802 return 0;
803}
804
805static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
806{
807 *vp = cptr->hdw->master_state;
d855497e
MI		 808 return 0;
809}
810
811static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
812{
813 int result = pvr2_hdw_is_hsm(cptr->hdw);
814 *vp = PVR2_CVAL_HSM_FULL;
815 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
816 if (result) *vp = PVR2_CVAL_HSM_HIGH;
817 return 0;
818}
819
820static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
821{
822 *vp = cptr->hdw->std_mask_avail;
823 return 0;
824}
825
826static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
827{
828 struct pvr2_hdw *hdw = cptr->hdw;
829 v4l2_std_id ns;
830 ns = hdw->std_mask_avail;
831 ns = (ns & ~m) | (v & m);
832 if (ns == hdw->std_mask_avail) return 0;
833 hdw->std_mask_avail = ns;
834 pvr2_hdw_internal_set_std_avail(hdw);
835 pvr2_hdw_internal_find_stdenum(hdw);
836 return 0;
837}
838
839static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
840 char *bufPtr,unsigned int bufSize,
841 unsigned int *len)
842{
843 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
844 return 0;
845}
846
847static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
848 const char *bufPtr,unsigned int bufSize,
849 int *mskp,int *valp)
850{
851 int ret;
852 v4l2_std_id id;
853 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
854 if (ret < 0) return ret;
855 if (mskp) *mskp = id;
856 if (valp) *valp = id;
857 return 0;
858}
859
860static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
861{
862 *vp = cptr->hdw->std_mask_cur;
863 return 0;
864}
865
866static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
867{
868 struct pvr2_hdw *hdw = cptr->hdw;
869 v4l2_std_id ns;
870 ns = hdw->std_mask_cur;
871 ns = (ns & ~m) | (v & m);
872 if (ns == hdw->std_mask_cur) return 0;
873 hdw->std_mask_cur = ns;
874 hdw->std_dirty = !0;
875 pvr2_hdw_internal_find_stdenum(hdw);
876 return 0;
877}
878
879static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
880{
881 return cptr->hdw->std_dirty != 0;
882}
883
884static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
885{
886 cptr->hdw->std_dirty = 0;
887}
888
889static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
890{
18103c57 891 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 892 pvr2_hdw_status_poll(hdw);
18103c57
MI		 893 *vp = hdw->tuner_signal_info.signal;
894 return 0;
895}
896
897static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
898{
899 int val = 0;
900 unsigned int subchan;
901 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 902 pvr2_hdw_status_poll(hdw);
18103c57
MI		 903 subchan = hdw->tuner_signal_info.rxsubchans;
904 if (subchan & V4L2_TUNER_SUB_MONO) {
905 val |= (1 << V4L2_TUNER_MODE_MONO);
906 }
907 if (subchan & V4L2_TUNER_SUB_STEREO) {
908 val |= (1 << V4L2_TUNER_MODE_STEREO);
909 }
910 if (subchan & V4L2_TUNER_SUB_LANG1) {
911 val |= (1 << V4L2_TUNER_MODE_LANG1);
912 }
913 if (subchan & V4L2_TUNER_SUB_LANG2) {
914 val |= (1 << V4L2_TUNER_MODE_LANG2);
915 }
916 *vp = val;
d855497e
MI		 917 return 0;
918}
919
d855497e
MI		 920
921static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
922{
923 struct pvr2_hdw *hdw = cptr->hdw;
924 if (v < 0) return -EINVAL;
925 if (v > hdw->std_enum_cnt) return -EINVAL;
926 hdw->std_enum_cur = v;
927 if (!v) return 0;
928 v--;
929 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
930 hdw->std_mask_cur = hdw->std_defs[v].id;
931 hdw->std_dirty = !0;
932 return 0;
933}
934
935
936static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
937{
938 *vp = cptr->hdw->std_enum_cur;
939 return 0;
940}
941
942
943static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
944{
945 return cptr->hdw->std_dirty != 0;
946}
947
948
949static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
950{
951 cptr->hdw->std_dirty = 0;
952}
953
954
955#define DEFINT(vmin,vmax) \
956 .type = pvr2_ctl_int, \
957 .def.type_int.min_value = vmin, \
958 .def.type_int.max_value = vmax
959
960#define DEFENUM(tab) \
961 .type = pvr2_ctl_enum, \
27c7b710 962 .def.type_enum.count = ARRAY_SIZE(tab), \
d855497e
MI		 963 .def.type_enum.value_names = tab
964
33213963
MI		 965#define DEFBOOL \
966 .type = pvr2_ctl_bool
967
d855497e
MI		 968#define DEFMASK(msk,tab) \
969 .type = pvr2_ctl_bitmask, \
970 .def.type_bitmask.valid_bits = msk, \
971 .def.type_bitmask.bit_names = tab
972
973#define DEFREF(vname) \
974 .set_value = ctrl_set_##vname, \
975 .get_value = ctrl_get_##vname, \
976 .is_dirty = ctrl_isdirty_##vname, \
977 .clear_dirty = ctrl_cleardirty_##vname
978
979
980#define VCREATE_FUNCS(vname) \
981static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
982{*vp = cptr->hdw->vname##_val; return 0;} \
983static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
984{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
985static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
986{return cptr->hdw->vname##_dirty != 0;} \
987static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
988{cptr->hdw->vname##_dirty = 0;}
989
990VCREATE_FUNCS(brightness)
991VCREATE_FUNCS(contrast)
992VCREATE_FUNCS(saturation)
993VCREATE_FUNCS(hue)
994VCREATE_FUNCS(volume)
995VCREATE_FUNCS(balance)
996VCREATE_FUNCS(bass)
997VCREATE_FUNCS(treble)
998VCREATE_FUNCS(mute)
e784bfb9 999VCREATE_FUNCS(cropl)
1000VCREATE_FUNCS(cropt)
1001VCREATE_FUNCS(cropw)
1002VCREATE_FUNCS(croph)
c05c0462
MI		 1003VCREATE_FUNCS(audiomode)
1004VCREATE_FUNCS(res_hor)
1005VCREATE_FUNCS(res_ver)
d855497e 1006VCREATE_FUNCS(srate)
d855497e 1007
d855497e
MI		 1008/* Table definition of all controls which can be manipulated */
1009static const struct pvr2_ctl_info control_defs[] = {
1010 {
1011 .v4l_id = V4L2_CID_BRIGHTNESS,
1012 .desc = "Brightness",
1013 .name = "brightness",
1014 .default_value = 128,
1015 DEFREF(brightness),
1016 DEFINT(0,255),
1017 },{
1018 .v4l_id = V4L2_CID_CONTRAST,
1019 .desc = "Contrast",
1020 .name = "contrast",
1021 .default_value = 68,
1022 DEFREF(contrast),
1023 DEFINT(0,127),
1024 },{
1025 .v4l_id = V4L2_CID_SATURATION,
1026 .desc = "Saturation",
1027 .name = "saturation",
1028 .default_value = 64,
1029 DEFREF(saturation),
1030 DEFINT(0,127),
1031 },{
1032 .v4l_id = V4L2_CID_HUE,
1033 .desc = "Hue",
1034 .name = "hue",
1035 .default_value = 0,
1036 DEFREF(hue),
1037 DEFINT(-128,127),
1038 },{
1039 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1040 .desc = "Volume",
1041 .name = "volume",
139eecf9 1042 .default_value = 62000,
d855497e
MI		 1043 DEFREF(volume),
1044 DEFINT(0,65535),
1045 },{
1046 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1047 .desc = "Balance",
1048 .name = "balance",
1049 .default_value = 0,
1050 DEFREF(balance),
1051 DEFINT(-32768,32767),
1052 },{
1053 .v4l_id = V4L2_CID_AUDIO_BASS,
1054 .desc = "Bass",
1055 .name = "bass",
1056 .default_value = 0,
1057 DEFREF(bass),
1058 DEFINT(-32768,32767),
1059 },{
1060 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1061 .desc = "Treble",
1062 .name = "treble",
1063 .default_value = 0,
1064 DEFREF(treble),
1065 DEFINT(-32768,32767),
1066 },{
1067 .v4l_id = V4L2_CID_AUDIO_MUTE,
1068 .desc = "Mute",
1069 .name = "mute",
1070 .default_value = 0,
1071 DEFREF(mute),
33213963 1072 DEFBOOL,
e784bfb9 1073 }, {
432907f7 1074 .desc = "Capture crop left margin",
e784bfb9 1075 .name = "crop_left",
1076 .internal_id = PVR2_CID_CROPL,
1077 .default_value = 0,
1078 DEFREF(cropl),
1079 DEFINT(-129, 340),
1080 .get_min_value = ctrl_cropl_min_get,
1081 .get_max_value = ctrl_cropl_max_get,
432907f7 1082 .get_def_value = ctrl_get_cropcapdl,
e784bfb9 1083 }, {
432907f7 1084 .desc = "Capture crop top margin",
e784bfb9 1085 .name = "crop_top",
1086 .internal_id = PVR2_CID_CROPT,
1087 .default_value = 0,
1088 DEFREF(cropt),
1089 DEFINT(-35, 544),
1090 .get_min_value = ctrl_cropt_min_get,
1091 .get_max_value = ctrl_cropt_max_get,
432907f7 1092 .get_def_value = ctrl_get_cropcapdt,
e784bfb9 1093 }, {
432907f7 1094 .desc = "Capture crop width",
e784bfb9 1095 .name = "crop_width",
1096 .internal_id = PVR2_CID_CROPW,
1097 .default_value = 720,
1098 DEFREF(cropw),
432907f7
MI		 1099 .get_max_value = ctrl_cropw_max_get,
1100 .get_def_value = ctrl_get_cropcapdw,
e784bfb9 1101 }, {
432907f7 1102 .desc = "Capture crop height",
e784bfb9 1103 .name = "crop_height",
1104 .internal_id = PVR2_CID_CROPH,
1105 .default_value = 480,
1106 DEFREF(croph),
432907f7
MI		 1107 .get_max_value = ctrl_croph_max_get,
1108 .get_def_value = ctrl_get_cropcapdh,
1109 }, {
1110 .desc = "Capture capability pixel aspect numerator",
1111 .name = "cropcap_pixel_numerator",
1112 .internal_id = PVR2_CID_CROPCAPPAN,
1113 .get_value = ctrl_get_cropcappan,
1114 }, {
1115 .desc = "Capture capability pixel aspect denominator",
1116 .name = "cropcap_pixel_denominator",
1117 .internal_id = PVR2_CID_CROPCAPPAD,
1118 .get_value = ctrl_get_cropcappad,
1119 }, {
1120 .desc = "Capture capability bounds top",
1121 .name = "cropcap_bounds_top",
1122 .internal_id = PVR2_CID_CROPCAPBT,
1123 .get_value = ctrl_get_cropcapbt,
1124 }, {
1125 .desc = "Capture capability bounds left",
1126 .name = "cropcap_bounds_left",
1127 .internal_id = PVR2_CID_CROPCAPBL,
1128 .get_value = ctrl_get_cropcapbl,
1129 }, {
1130 .desc = "Capture capability bounds width",
1131 .name = "cropcap_bounds_width",
1132 .internal_id = PVR2_CID_CROPCAPBW,
1133 .get_value = ctrl_get_cropcapbw,
1134 }, {
1135 .desc = "Capture capability bounds height",
1136 .name = "cropcap_bounds_height",
1137 .internal_id = PVR2_CID_CROPCAPBH,
1138 .get_value = ctrl_get_cropcapbh,
c05c0462
MI		 1139 },{
1140 .desc = "Video Source",
1141 .name = "input",
1142 .internal_id = PVR2_CID_INPUT,
1143 .default_value = PVR2_CVAL_INPUT_TV,
29bf5b1d 1144 .check_value = ctrl_check_input,
c05c0462
MI		 1145 DEFREF(input),
1146 DEFENUM(control_values_input),
1147 },{
1148 .desc = "Audio Mode",
1149 .name = "audio_mode",
1150 .internal_id = PVR2_CID_AUDIOMODE,
1151 .default_value = V4L2_TUNER_MODE_STEREO,
1152 DEFREF(audiomode),
1153 DEFENUM(control_values_audiomode),
1154 },{
1155 .desc = "Horizontal capture resolution",
1156 .name = "resolution_hor",
1157 .internal_id = PVR2_CID_HRES,
1158 .default_value = 720,
1159 DEFREF(res_hor),
3ad9fc37 1160 DEFINT(19,720),
c05c0462
MI		 1161 },{
1162 .desc = "Vertical capture resolution",
1163 .name = "resolution_ver",
1164 .internal_id = PVR2_CID_VRES,
1165 .default_value = 480,
1166 DEFREF(res_ver),
3ad9fc37
MI		 1167 DEFINT(17,576),
1168 /* Hook in check for video standard and adjust maximum
1169 depending on the standard. */
1170 .get_max_value = ctrl_vres_max_get,
1171 .get_min_value = ctrl_vres_min_get,
d855497e 1172 },{
b30d2441 1173 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
434449f4
MI		 1174 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1175 .desc = "Audio Sampling Frequency",
d855497e 1176 .name = "srate",
d855497e
MI		 1177 DEFREF(srate),
1178 DEFENUM(control_values_srate),
d855497e
MI		 1179 },{
1180 .desc = "Tuner Frequency (Hz)",
1181 .name = "frequency",
1182 .internal_id = PVR2_CID_FREQUENCY,
1bde0289 1183 .default_value = 0,
d855497e
MI		 1184 .set_value = ctrl_freq_set,
1185 .get_value = ctrl_freq_get,
1186 .is_dirty = ctrl_freq_is_dirty,
1187 .clear_dirty = ctrl_freq_clear_dirty,
644afdb9 1188 DEFINT(0,0),
25d8527a
PK		 1189 /* Hook in check for input value (tv/radio) and adjust
1190 max/min values accordingly */
1191 .get_max_value = ctrl_freq_max_get,
1192 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1193 },{
1194 .desc = "Channel",
1195 .name = "channel",
1196 .set_value = ctrl_channel_set,
1197 .get_value = ctrl_channel_get,
1198 DEFINT(0,FREQTABLE_SIZE),
1199 },{
1200 .desc = "Channel Program Frequency",
1201 .name = "freq_table_value",
1202 .set_value = ctrl_channelfreq_set,
1203 .get_value = ctrl_channelfreq_get,
644afdb9 1204 DEFINT(0,0),
1bde0289
MI		 1205 /* Hook in check for input value (tv/radio) and adjust
1206 max/min values accordingly */
1bde0289
MI		 1207 .get_max_value = ctrl_freq_max_get,
1208 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1209 },{
1210 .desc = "Channel Program ID",
1211 .name = "freq_table_channel",
1212 .set_value = ctrl_channelprog_set,
1213 .get_value = ctrl_channelprog_get,
1214 DEFINT(0,FREQTABLE_SIZE),
d855497e
MI		 1215 },{
1216 .desc = "Streaming Enabled",
1217 .name = "streaming_enabled",
1218 .get_value = ctrl_streamingenabled_get,
33213963 1219 DEFBOOL,
d855497e
MI		 1220 },{
1221 .desc = "USB Speed",
1222 .name = "usb_speed",
1223 .get_value = ctrl_hsm_get,
1224 DEFENUM(control_values_hsm),
681c7399
MI		 1225 },{
1226 .desc = "Master State",
1227 .name = "master_state",
1228 .get_value = ctrl_masterstate_get,
1229 DEFENUM(pvr2_state_names),
d855497e
MI		 1230 },{
1231 .desc = "Signal Present",
1232 .name = "signal_present",
1233 .get_value = ctrl_signal_get,
18103c57
MI		 1234 DEFINT(0,65535),
1235 },{
1236 .desc = "Audio Modes Present",
1237 .name = "audio_modes_present",
1238 .get_value = ctrl_audio_modes_present_get,
1239 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1240 v4l. Nothing outside of this module cares about this,
1241 but I reuse it in order to also reuse the
1242 control_values_audiomode string table. */
1243 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1244 (1 << V4L2_TUNER_MODE_STEREO)|
1245 (1 << V4L2_TUNER_MODE_LANG1)|
1246 (1 << V4L2_TUNER_MODE_LANG2)),
1247 control_values_audiomode),
d855497e
MI		 1248 },{
1249 .desc = "Video Standards Available Mask",
1250 .name = "video_standard_mask_available",
1251 .internal_id = PVR2_CID_STDAVAIL,
1252 .skip_init = !0,
1253 .get_value = ctrl_stdavail_get,
1254 .set_value = ctrl_stdavail_set,
1255 .val_to_sym = ctrl_std_val_to_sym,
1256 .sym_to_val = ctrl_std_sym_to_val,
1257 .type = pvr2_ctl_bitmask,
1258 },{
1259 .desc = "Video Standards In Use Mask",
1260 .name = "video_standard_mask_active",
1261 .internal_id = PVR2_CID_STDCUR,
1262 .skip_init = !0,
1263 .get_value = ctrl_stdcur_get,
1264 .set_value = ctrl_stdcur_set,
1265 .is_dirty = ctrl_stdcur_is_dirty,
1266 .clear_dirty = ctrl_stdcur_clear_dirty,
1267 .val_to_sym = ctrl_std_val_to_sym,
1268 .sym_to_val = ctrl_std_sym_to_val,
1269 .type = pvr2_ctl_bitmask,
d855497e
MI		 1270 },{
1271 .desc = "Video Standard Name",
1272 .name = "video_standard",
1273 .internal_id = PVR2_CID_STDENUM,
1274 .skip_init = !0,
1275 .get_value = ctrl_stdenumcur_get,
1276 .set_value = ctrl_stdenumcur_set,
1277 .is_dirty = ctrl_stdenumcur_is_dirty,
1278 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1279 .type = pvr2_ctl_enum,
1280 }
1281};
1282
eca8ebfc 1283#define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
d855497e
MI		 1284
1285
1286const char *pvr2_config_get_name(enum pvr2_config cfg)
1287{
1288 switch (cfg) {
1289 case pvr2_config_empty: return "empty";
1290 case pvr2_config_mpeg: return "mpeg";
1291 case pvr2_config_vbi: return "vbi";
16eb40d3
MI		 1292 case pvr2_config_pcm: return "pcm";
1293 case pvr2_config_rawvideo: return "raw video";
d855497e
MI		 1294 }
1295 return "<unknown>";
1296}
1297
1298
1299struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1300{
1301 return hdw->usb_dev;
1302}
1303
1304
1305unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1306{
1307 return hdw->serial_number;
1308}
1309
31a18547
MI		 1310
1311const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1312{
1313 return hdw->bus_info;
1314}
1315
1316
13a88797
MI		 1317const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1318{
1319 return hdw->identifier;
1320}
1321
1322
1bde0289
MI		 1323unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1324{
1325 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1326}
1327
1328/* Set the currently tuned frequency and account for all possible
1329 driver-core side effects of this action. */
f55a8712 1330static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1bde0289 1331{
7c74e57e 1332 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1bde0289
MI		 1333 if (hdw->freqSelector) {
1334 /* Swing over to radio frequency selection */
1335 hdw->freqSelector = 0;
1336 hdw->freqDirty = !0;
1337 }
1bde0289
MI		 1338 if (hdw->freqValRadio != val) {
1339 hdw->freqValRadio = val;
1340 hdw->freqSlotRadio = 0;
7c74e57e 1341 hdw->freqDirty = !0;
1bde0289 1342 }
7c74e57e 1343 } else {
1bde0289
MI		 1344 if (!(hdw->freqSelector)) {
1345 /* Swing over to television frequency selection */
1346 hdw->freqSelector = 1;
1347 hdw->freqDirty = !0;
1348 }
1bde0289
MI		 1349 if (hdw->freqValTelevision != val) {
1350 hdw->freqValTelevision = val;
1351 hdw->freqSlotTelevision = 0;
7c74e57e 1352 hdw->freqDirty = !0;
1bde0289 1353 }
1bde0289
MI		 1354 }
1355}
1356
d855497e
MI		 1357int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1358{
1359 return hdw->unit_number;
1360}
1361
1362
1363/* Attempt to locate one of the given set of files. Messages are logged
1364 appropriate to what has been found. The return value will be 0 or
1365 greater on success (it will be the index of the file name found) and
1366 fw_entry will be filled in. Otherwise a negative error is returned on
1367 failure. If the return value is -ENOENT then no viable firmware file
1368 could be located. */
1369static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1370 const struct firmware **fw_entry,
1371 const char *fwtypename,
1372 unsigned int fwcount,
1373 const char *fwnames[])
1374{
1375 unsigned int idx;
1376 int ret = -EINVAL;
1377 for (idx = 0; idx < fwcount; idx++) {
1378 ret = request_firmware(fw_entry,
1379 fwnames[idx],
1380 &hdw->usb_dev->dev);
1381 if (!ret) {
1382 trace_firmware("Located %s firmware: %s;"
1383 " uploading...",
1384 fwtypename,
1385 fwnames[idx]);
1386 return idx;
1387 }
1388 if (ret == -ENOENT) continue;
1389 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1390 "request_firmware fatal error with code=%d",ret);
1391 return ret;
1392 }
1393 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1394 "***WARNING***"
1395 " Device %s firmware"
1396 " seems to be missing.",
1397 fwtypename);
1398 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1399 "Did you install the pvrusb2 firmware files"
1400 " in their proper location?");
1401 if (fwcount == 1) {
1402 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1403 "request_firmware unable to locate %s file %s",
1404 fwtypename,fwnames[0]);
1405 } else {
1406 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1407 "request_firmware unable to locate"
1408 " one of the following %s files:",
1409 fwtypename);
1410 for (idx = 0; idx < fwcount; idx++) {
1411 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1412 "request_firmware: Failed to find %s",
1413 fwnames[idx]);
1414 }
1415 }
1416 return ret;
1417}
1418
1419
1420/*
1421 * pvr2_upload_firmware1().
1422 *
1423 * Send the 8051 firmware to the device. After the upload, arrange for
1424 * device to re-enumerate.
1425 *
1426 * NOTE : the pointer to the firmware data given by request_firmware()
1427 * is not suitable for an usb transaction.
1428 *
1429 */
07e337ee 1430static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
d855497e 1431{
a0fd1cb1 1432 const struct firmware *fw_entry = NULL;
d855497e
MI		 1433 void *fw_ptr;
1434 unsigned int pipe;
1435 int ret;
1436 u16 address;
1d643a37 1437
989eb154 1438 if (!hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37 1439 hdw->fw1_state = FW1_STATE_OK;
56dcbfa0
MI		 1440 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1441 "Connected device type defines"
1442 " no firmware to upload; ignoring firmware");
1443 return -ENOTTY;
1d643a37
MI		 1444 }
1445
d855497e
MI		 1446 hdw->fw1_state = FW1_STATE_FAILED; // default result
1447
1448 trace_firmware("pvr2_upload_firmware1");
1449
1450 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
989eb154
MI		 1451 hdw->hdw_desc->fx2_firmware.cnt,
1452 hdw->hdw_desc->fx2_firmware.lst);
d855497e
MI		 1453 if (ret < 0) {
1454 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1455 return ret;
1456 }
1457
1458 usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1459 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1460
1461 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1462
1463 if (fw_entry->size != 0x2000){
1464 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1465 release_firmware(fw_entry);
1466 return -ENOMEM;
1467 }
1468
1469 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1470 if (fw_ptr == NULL){
1471 release_firmware(fw_entry);
1472 return -ENOMEM;
1473 }
1474
1475 /* We have to hold the CPU during firmware upload. */
1476 pvr2_hdw_cpureset_assert(hdw,1);
1477
1478 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1479 chunk. */
1480
1481 ret = 0;
1482 for(address = 0; address < fw_entry->size; address += 0x800) {
1483 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1484 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1485 0, fw_ptr, 0x800, HZ);
1486 }
1487
1488 trace_firmware("Upload done, releasing device's CPU");
1489
1490 /* Now release the CPU. It will disconnect and reconnect later. */
1491 pvr2_hdw_cpureset_assert(hdw,0);
1492
1493 kfree(fw_ptr);
1494 release_firmware(fw_entry);
1495
1496 trace_firmware("Upload done (%d bytes sent)",ret);
1497
1498 /* We should have written 8192 bytes */
1499 if (ret == 8192) {
1500 hdw->fw1_state = FW1_STATE_RELOAD;
1501 return 0;
1502 }
1503
1504 return -EIO;
1505}
1506
1507
1508/*
1509 * pvr2_upload_firmware2()
1510 *
1511 * This uploads encoder firmware on endpoint 2.
1512 *
1513 */
1514
1515int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1516{
a0fd1cb1 1517 const struct firmware *fw_entry = NULL;
d855497e 1518 void *fw_ptr;
90060d32 1519 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
d855497e
MI		 1520 int actual_length;
1521 int ret = 0;
1522 int fwidx;
1523 static const char *fw_files[] = {
1524 CX2341X_FIRM_ENC_FILENAME,
1525 };
1526
989eb154 1527 if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1d643a37
MI		 1528 return 0;
1529 }
1530
d855497e
MI		 1531 trace_firmware("pvr2_upload_firmware2");
1532
1533 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
eca8ebfc 1534 ARRAY_SIZE(fw_files), fw_files);
d855497e
MI		 1535 if (ret < 0) return ret;
1536 fwidx = ret;
1537 ret = 0;
b30d2441
MI		 1538 /* Since we're about to completely reinitialize the encoder,
1539 invalidate our cached copy of its configuration state. Next
1540 time we configure the encoder, then we'll fully configure it. */
1541 hdw->enc_cur_valid = 0;
d855497e 1542
d913d630
MI		 1543 /* Encoder is about to be reset so note that as far as we're
1544 concerned now, the encoder has never been run. */
1545 del_timer_sync(&hdw->encoder_run_timer);
1546 if (hdw->state_encoder_runok) {
1547 hdw->state_encoder_runok = 0;
1548 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1549 }
1550
d855497e
MI		 1551 /* First prepare firmware loading */
1552 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1553 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1554 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1555 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1556 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1557 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1558 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1559 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1560 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1561 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1562 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1563 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1564 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1565 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1566 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1567 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1c9d10d4
MI		 1568 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1569 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1570
1571 if (ret) {
1572 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1573 "firmware2 upload prep failed, ret=%d",ret);
1574 release_firmware(fw_entry);
21684ba9 1575 goto done;
d855497e
MI		 1576 }
1577
1578 /* Now send firmware */
1579
1580 fw_len = fw_entry->size;
1581
90060d32 1582 if (fw_len % sizeof(u32)) {
d855497e
MI		 1583 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1584 "size of %s firmware"
48dc30a1 1585 " must be a multiple of %zu bytes",
90060d32 1586 fw_files[fwidx],sizeof(u32));
d855497e 1587 release_firmware(fw_entry);
21684ba9
MI		 1588 ret = -EINVAL;
1589 goto done;
d855497e
MI		 1590 }
1591
1592 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1593 if (fw_ptr == NULL){
1594 release_firmware(fw_entry);
1595 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1596 "failed to allocate memory for firmware2 upload");
21684ba9
MI		 1597 ret = -ENOMEM;
1598 goto done;
d855497e
MI		 1599 }
1600
1601 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1602
90060d32
MI		 1603 fw_done = 0;
1604 for (fw_done = 0; fw_done < fw_len;) {
1605 bcnt = fw_len - fw_done;
1606 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1607 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1608 /* Usbsnoop log shows that we must swap bytes... */
5f33df14
MI		 1609 /* Some background info: The data being swapped here is a
1610 firmware image destined for the mpeg encoder chip that
1611 lives at the other end of a USB endpoint. The encoder
1612 chip always talks in 32 bit chunks and its storage is
1613 organized into 32 bit words. However from the file
1614 system to the encoder chip everything is purely a byte
1615 stream. The firmware file's contents are always 32 bit
1616 swapped from what the encoder expects. Thus the need
1617 always exists to swap the bytes regardless of the endian
1618 type of the host processor and therefore swab32() makes
1619 the most sense. */
90060d32 1620 for (icnt = 0; icnt < bcnt/4 ; icnt++)
513edce6 1621 ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
90060d32
MI		 1622
1623 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
d855497e 1624 &actual_length, HZ);
90060d32
MI		 1625 ret |= (actual_length != bcnt);
1626 if (ret) break;
1627 fw_done += bcnt;
d855497e
MI		 1628 }
1629
1630 trace_firmware("upload of %s : %i / %i ",
1631 fw_files[fwidx],fw_done,fw_len);
1632
1633 kfree(fw_ptr);
1634 release_firmware(fw_entry);
1635
1636 if (ret) {
1637 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1638 "firmware2 upload transfer failure");
21684ba9 1639 goto done;
d855497e
MI		 1640 }
1641
1642 /* Finish upload */
1643
1644 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1645 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1c9d10d4 1646 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1647
1648 if (ret) {
1649 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1650 "firmware2 upload post-proc failure");
d855497e 1651 }
21684ba9
MI		 1652
1653 done:
1df59f0b
MI		 1654 if (hdw->hdw_desc->signal_routing_scheme ==
1655 PVR2_ROUTING_SCHEME_GOTVIEW) {
1656 /* Ensure that GPIO 11 is set to output for GOTVIEW
1657 hardware. */
1658 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1659 }
d855497e
MI		 1660 return ret;
1661}
1662
1663
681c7399
MI		 1664static const char *pvr2_get_state_name(unsigned int st)
1665{
1666 if (st < ARRAY_SIZE(pvr2_state_names)) {
1667 return pvr2_state_names[st];
d855497e 1668 }
681c7399 1669 return "???";
d855497e
MI		 1670}
1671
681c7399 1672static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
d855497e 1673{
af78e16b
MI		 1674 if (hdw->decoder_ctrl) {
1675 hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt, enablefl);
1676 return 0;
681c7399 1677 }
af78e16b
MI		 1678 /* Even though we really only care about the video decoder chip at
1679 this point, we'll broadcast stream on/off to all sub-devices
1680 anyway, just in case somebody else wants to hear the
1681 command... */
1682 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1683 if (hdw->decoder_client_id) {
1684 /* We get here if the encoder has been noticed. Otherwise
1685 we'll issue a warning to the user (which should
1686 normally never happen). */
1687 return 0;
1688 }
1689 if (!hdw->flag_decoder_missed) {
1690 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1691 "WARNING: No decoder present");
1692 hdw->flag_decoder_missed = !0;
1693 trace_stbit("flag_decoder_missed",
1694 hdw->flag_decoder_missed);
1695 }
1696 return -EIO;
d855497e
MI		 1697}
1698
1699
681c7399 1700void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
d855497e 1701{
681c7399
MI		 1702 if (hdw->decoder_ctrl == ptr) return;
1703 hdw->decoder_ctrl = ptr;
1704 if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1705 hdw->flag_decoder_missed = 0;
1706 trace_stbit("flag_decoder_missed",
1707 hdw->flag_decoder_missed);
1708 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1709 "Decoder has appeared");
1710 pvr2_hdw_state_sched(hdw);
1711 }
d855497e
MI		 1712}
1713
1714
681c7399 1715int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
d855497e 1716{
681c7399 1717 return hdw->master_state;
d855497e
MI		 1718}
1719
1720
681c7399 1721static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
d855497e 1722{
681c7399
MI		 1723 if (!hdw->flag_tripped) return 0;
1724 hdw->flag_tripped = 0;
1725 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1726 "Clearing driver error statuss");
1727 return !0;
d855497e
MI		 1728}
1729
1730
681c7399 1731int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
d855497e 1732{
681c7399 1733 int fl;
d855497e 1734 LOCK_TAKE(hdw->big_lock); do {
681c7399 1735 fl = pvr2_hdw_untrip_unlocked(hdw);
d855497e 1736 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1737 if (fl) pvr2_hdw_state_sched(hdw);
1738 return 0;
d855497e
MI		 1739}
1740
1741
d855497e
MI		 1742
1743
1744int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1745{
681c7399 1746 return hdw->state_pipeline_req != 0;
d855497e
MI		 1747}
1748
1749
1750int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1751{
681c7399 1752 int ret,st;
d855497e 1753 LOCK_TAKE(hdw->big_lock); do {
681c7399
MI		 1754 pvr2_hdw_untrip_unlocked(hdw);
1755 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1756 hdw->state_pipeline_req = enable_flag != 0;
1757 pvr2_trace(PVR2_TRACE_START_STOP,
1758 "/*--TRACE_STREAM--*/ %s",
1759 enable_flag ? "enable" : "disable");
1760 }
1761 pvr2_hdw_state_sched(hdw);
d855497e 1762 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1763 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1764 if (enable_flag) {
1765 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1766 if (st != PVR2_STATE_READY) return -EIO;
1767 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1768 }
1769 }
d855497e
MI		 1770 return 0;
1771}
1772
1773
1774int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1775{
681c7399 1776 int fl;
d855497e 1777 LOCK_TAKE(hdw->big_lock);
681c7399
MI		 1778 if ((fl = (hdw->desired_stream_type != config)) != 0) {
1779 hdw->desired_stream_type = config;
1780 hdw->state_pipeline_config = 0;
1781 trace_stbit("state_pipeline_config",
1782 hdw->state_pipeline_config);
1783 pvr2_hdw_state_sched(hdw);
1784 }
d855497e 1785 LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1786 if (fl) return 0;
1787 return pvr2_hdw_wait(hdw,0);
d855497e
MI		 1788}
1789
1790
1791static int get_default_tuner_type(struct pvr2_hdw *hdw)
1792{
1793 int unit_number = hdw->unit_number;
1794 int tp = -1;
1795 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1796 tp = tuner[unit_number];
1797 }
1798 if (tp < 0) return -EINVAL;
1799 hdw->tuner_type = tp;
aaf7884d 1800 hdw->tuner_updated = !0;
d855497e
MI		 1801 return 0;
1802}
1803
1804
1805static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1806{
1807 int unit_number = hdw->unit_number;
1808 int tp = 0;
1809 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1810 tp = video_std[unit_number];
6a540254 1811 if (tp) return tp;
d855497e 1812 }
6a540254 1813 return 0;
d855497e
MI		 1814}
1815
1816
1817static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1818{
1819 int unit_number = hdw->unit_number;
1820 int tp = 0;
1821 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1822 tp = tolerance[unit_number];
1823 }
1824 return tp;
1825}
1826
1827
1828static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1829{
1830 /* Try a harmless request to fetch the eeprom's address over
1831 endpoint 1. See what happens. Only the full FX2 image can
1832 respond to this. If this probe fails then likely the FX2
1833 firmware needs be loaded. */
1834 int result;
1835 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 1836 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 1837 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1838 hdw->cmd_buffer,1,
1839 hdw->cmd_buffer,1);
1840 if (result < 0) break;
1841 } while(0); LOCK_GIVE(hdw->ctl_lock);
1842 if (result) {
1843 pvr2_trace(PVR2_TRACE_INIT,
1844 "Probe of device endpoint 1 result status %d",
1845 result);
1846 } else {
1847 pvr2_trace(PVR2_TRACE_INIT,
1848 "Probe of device endpoint 1 succeeded");
1849 }
1850 return result == 0;
1851}
1852
9f66d4ea
MI		 1853struct pvr2_std_hack {
1854 v4l2_std_id pat; /* Pattern to match */
1855 v4l2_std_id msk; /* Which bits we care about */
1856 v4l2_std_id std; /* What additional standards or default to set */
1857};
1858
1859/* This data structure labels specific combinations of standards from
1860 tveeprom that we'll try to recognize. If we recognize one, then assume
1861 a specified default standard to use. This is here because tveeprom only
1862 tells us about available standards not the intended default standard (if
1863 any) for the device in question. We guess the default based on what has
1864 been reported as available. Note that this is only for guessing a
1865 default - which can always be overridden explicitly - and if the user
1866 has otherwise named a default then that default will always be used in
1867 place of this table. */
ebff0330 1868static const struct pvr2_std_hack std_eeprom_maps[] = {
9f66d4ea
MI		 1869 { /* PAL(B/G) */
1870 .pat = V4L2_STD_B|V4L2_STD_GH,
1871 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1872 },
1873 { /* NTSC(M) */
1874 .pat = V4L2_STD_MN,
1875 .std = V4L2_STD_NTSC_M,
1876 },
1877 { /* PAL(I) */
1878 .pat = V4L2_STD_PAL_I,
1879 .std = V4L2_STD_PAL_I,
1880 },
1881 { /* SECAM(L/L') */
1882 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1883 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1884 },
1885 { /* PAL(D/D1/K) */
1886 .pat = V4L2_STD_DK,
ea2562d9 1887 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
9f66d4ea
MI		 1888 },
1889};
1890
d855497e
MI		 1891static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1892{
1893 char buf[40];
1894 unsigned int bcnt;
3d290bdb 1895 v4l2_std_id std1,std2,std3;
d855497e
MI		 1896
1897 std1 = get_default_standard(hdw);
3d290bdb 1898 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
d855497e
MI		 1899
1900 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
56585386 1901 pvr2_trace(PVR2_TRACE_STD,
56dcbfa0
MI		 1902 "Supported video standard(s) reported available"
1903 " in hardware: %.*s",
d855497e
MI		 1904 bcnt,buf);
1905
1906 hdw->std_mask_avail = hdw->std_mask_eeprom;
1907
3d290bdb 1908 std2 = (std1|std3) & ~hdw->std_mask_avail;
d855497e
MI		 1909 if (std2) {
1910 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
56585386 1911 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1912 "Expanding supported video standards"
1913 " to include: %.*s",
1914 bcnt,buf);
1915 hdw->std_mask_avail |= std2;
1916 }
1917
1918 pvr2_hdw_internal_set_std_avail(hdw);
1919
1920 if (std1) {
1921 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
56585386 1922 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1923 "Initial video standard forced to %.*s",
1924 bcnt,buf);
1925 hdw->std_mask_cur = std1;
1926 hdw->std_dirty = !0;
1927 pvr2_hdw_internal_find_stdenum(hdw);
1928 return;
1929 }
3d290bdb
MI		 1930 if (std3) {
1931 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1932 pvr2_trace(PVR2_TRACE_STD,
1933 "Initial video standard"
1934 " (determined by device type): %.*s",bcnt,buf);
1935 hdw->std_mask_cur = std3;
1936 hdw->std_dirty = !0;
1937 pvr2_hdw_internal_find_stdenum(hdw);
1938 return;
1939 }
d855497e 1940
9f66d4ea
MI		 1941 {
1942 unsigned int idx;
1943 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1944 if (std_eeprom_maps[idx].msk ?
1945 ((std_eeprom_maps[idx].pat ^
1946 hdw->std_mask_eeprom) &
1947 std_eeprom_maps[idx].msk) :
1948 (std_eeprom_maps[idx].pat !=
1949 hdw->std_mask_eeprom)) continue;
1950 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1951 std_eeprom_maps[idx].std);
56585386 1952 pvr2_trace(PVR2_TRACE_STD,
9f66d4ea
MI		 1953 "Initial video standard guessed as %.*s",
1954 bcnt,buf);
1955 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1956 hdw->std_dirty = !0;
1957 pvr2_hdw_internal_find_stdenum(hdw);
1958 return;
1959 }
1960 }
1961
d855497e
MI		 1962 if (hdw->std_enum_cnt > 1) {
1963 // Autoselect the first listed standard
1964 hdw->std_enum_cur = 1;
1965 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1966 hdw->std_dirty = !0;
56585386 1967 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1968 "Initial video standard auto-selected to %s",
1969 hdw->std_defs[hdw->std_enum_cur-1].name);
1970 return;
1971 }
1972
0885ba1d 1973 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
d855497e
MI		 1974 "Unable to select a viable initial video standard");
1975}
1976
1977
e9c64a78
MI		 1978static unsigned int pvr2_copy_i2c_addr_list(
1979 unsigned short *dst, const unsigned char *src,
1980 unsigned int dst_max)
1981{
3ab8d295 1982 unsigned int cnt = 0;
e9c64a78
MI		 1983 if (!src) return 0;
1984 while (src[cnt] && (cnt + 1) < dst_max) {
1985 dst[cnt] = src[cnt];
1986 cnt++;
1987 }
1988 dst[cnt] = I2C_CLIENT_END;
1989 return cnt;
1990}
1991
1992
1ab5e74f
MI		 1993static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
1994 const struct pvr2_device_client_desc *cd)
e9c64a78
MI		 1995{
1996 const char *fname;
1997 unsigned char mid;
1998 struct v4l2_subdev *sd;
1999 unsigned int i2ccnt;
2000 const unsigned char *p;
2001 /* Arbitrary count - max # i2c addresses we will probe */
2002 unsigned short i2caddr[25];
2003
2004 mid = cd->module_id;
2005 fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
2006 if (!fname) {
2007 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1ab5e74f 2008 "Module ID %u for device %s has no name",
e9c64a78
MI		 2009 mid,
2010 hdw->hdw_desc->description);
1ab5e74f 2011 return -EINVAL;
e9c64a78 2012 }
bd14d4f8
MI		 2013 pvr2_trace(PVR2_TRACE_INIT,
2014 "Module ID %u (%s) for device %s being loaded...",
2015 mid, fname,
2016 hdw->hdw_desc->description);
e9c64a78
MI		 2017
2018 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2019 ARRAY_SIZE(i2caddr));
2020 if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2021 module_i2c_addresses[mid] : NULL) != NULL)) {
2022 /* Second chance: Try default i2c address list */
2023 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2024 ARRAY_SIZE(i2caddr));
bd14d4f8
MI		 2025 if (i2ccnt) {
2026 pvr2_trace(PVR2_TRACE_INIT,
2027 "Module ID %u:"
2028 " Using default i2c address list",
2029 mid);
2030 }
e9c64a78
MI		 2031 }
2032
2033 if (!i2ccnt) {
2034 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1ab5e74f
MI		 2035 "Module ID %u (%s) for device %s:"
2036 " No i2c addresses",
2037 mid, fname, hdw->hdw_desc->description);
2038 return -EINVAL;
e9c64a78
MI		 2039 }
2040
2041 /* Note how the 2nd and 3rd arguments are the same for both
2042 * v4l2_i2c_new_subdev() and v4l2_i2c_new_probed_subdev(). Why?
2043 * Well the 2nd argument is the module name to load, while the 3rd
2044 * argument is documented in the framework as being the "chipid" -
2045 * and every other place where I can find examples of this, the
2046 * "chipid" appears to just be the module name again. So here we
2047 * just do the same thing. */
0db85568 2048 hdw->i2c_adap.class = 0;
e9c64a78 2049 if (i2ccnt == 1) {
bd14d4f8
MI		 2050 pvr2_trace(PVR2_TRACE_INIT,
2051 "Module ID %u:"
2052 " Setting up with specified i2c address 0x%x",
2053 mid, i2caddr[0]);
e9c64a78
MI		 2054 sd = v4l2_i2c_new_subdev(&hdw->i2c_adap,
2055 fname, fname,
2056 i2caddr[0]);
2057 } else {
bd14d4f8
MI		 2058 pvr2_trace(PVR2_TRACE_INIT,
2059 "Module ID %u:"
2060 " Setting up with address probe list",
2061 mid);
e9c64a78
MI		 2062 sd = v4l2_i2c_new_probed_subdev(&hdw->i2c_adap,
2063 fname, fname,
2064 i2caddr);
2065 }
0db85568 2066 hdw->i2c_adap.class = I2C_CLASS_TV_ANALOG;
e9c64a78 2067
446dfdc6
MI		 2068 if (!sd) {
2069 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1ab5e74f
MI		 2070 "Module ID %u (%s) for device %s failed to load",
2071 mid, fname, hdw->hdw_desc->description);
2072 return -EIO;
446dfdc6
MI		 2073 }
2074
2075 /* Tag this sub-device instance with the module ID we know about.
2076 In other places we'll use that tag to determine if the instance
2077 requires special handling. */
2078 sd->grp_id = mid;
2079
a932f507
MI		 2080 /* If we have both old and new i2c layers enabled, make sure that
2081 old layer isn't also tracking this module. This is a debugging
2082 aid, in normal situations there's no reason for both mechanisms
2083 to be enabled. */
2084 pvr2_i2c_untrack_subdev(hdw, sd);
bd14d4f8 2085 pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
a932f507 2086
e9c64a78 2087
00e5f736
MI		 2088 /* client-specific setup... */
2089 switch (mid) {
2090 case PVR2_CLIENT_ID_CX25840:
2091 hdw->decoder_client_id = mid;
2092 {
2093 /*
2094 Mike Isely <isely@pobox.com> 19-Nov-2006 - This
2095 bit of nuttiness for cx25840 causes that module
2096 to correctly set up its video scaling. This is
2097 really a problem in the cx25840 module itself,
2098 but we work around it here. The problem has not
2099 been seen in ivtv because there VBI is supported
2100 and set up. We don't do VBI here (at least not
2101 yet) and thus we never attempted to even set it
2102 up.
2103 */
2104 struct v4l2_format fmt;
bd14d4f8
MI		 2105 pvr2_trace(PVR2_TRACE_INIT,
2106 "Module ID %u:"
2107 " Executing cx25840 VBI hack",
2108 mid);
00e5f736
MI		 2109 memset(&fmt, 0, sizeof(fmt));
2110 fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
2111 v4l2_device_call_all(&hdw->v4l2_dev, mid,
2112 video, s_fmt, &fmt);
2113 }
2114 break;
2115 case PVR2_CLIENT_ID_SAA7115:
2116 hdw->decoder_client_id = mid;
2117 break;
2118 default: break;
2119 }
1ab5e74f
MI		 2120
2121 return 0;
e9c64a78
MI		 2122}
2123
2124
2125static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2126{
2127 unsigned int idx;
2128 const struct pvr2_string_table *cm;
2129 const struct pvr2_device_client_table *ct;
1ab5e74f 2130 int okFl = !0;
e9c64a78
MI		 2131
2132 cm = &hdw->hdw_desc->client_modules;
2133 for (idx = 0; idx < cm->cnt; idx++) {
2134 request_module(cm->lst[idx]);
2135 }
2136
2137 ct = &hdw->hdw_desc->client_table;
2138 for (idx = 0; idx < ct->cnt; idx++) {
bd14d4f8 2139 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
e9c64a78 2140 }
1ab5e74f 2141 if (!okFl) pvr2_hdw_render_useless(hdw);
e9c64a78
MI		 2142}
2143
2144
d855497e
MI		 2145static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2146{
2147 int ret;
2148 unsigned int idx;
2149 struct pvr2_ctrl *cptr;
2150 int reloadFl = 0;
989eb154 2151 if (hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37
MI		 2152 if (!reloadFl) {
2153 reloadFl =
2154 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2155 == 0);
2156 if (reloadFl) {
2157 pvr2_trace(PVR2_TRACE_INIT,
2158 "USB endpoint config looks strange"
2159 "; possibly firmware needs to be"
2160 " loaded");
2161 }
d855497e 2162 }
1d643a37
MI		 2163 if (!reloadFl) {
2164 reloadFl = !pvr2_hdw_check_firmware(hdw);
2165 if (reloadFl) {
2166 pvr2_trace(PVR2_TRACE_INIT,
2167 "Check for FX2 firmware failed"
2168 "; possibly firmware needs to be"
2169 " loaded");
2170 }
d855497e 2171 }
1d643a37
MI		 2172 if (reloadFl) {
2173 if (pvr2_upload_firmware1(hdw) != 0) {
2174 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2175 "Failure uploading firmware1");
2176 }
2177 return;
d855497e 2178 }
d855497e
MI		 2179 }
2180 hdw->fw1_state = FW1_STATE_OK;
2181
d855497e
MI		 2182 if (!pvr2_hdw_dev_ok(hdw)) return;
2183
989eb154 2184 if (!hdw->hdw_desc->flag_no_powerup) {
1d643a37
MI		 2185 pvr2_hdw_cmd_powerup(hdw);
2186 if (!pvr2_hdw_dev_ok(hdw)) return;
d855497e
MI		 2187 }
2188
31335b13
MI		 2189 /* Take the IR chip out of reset, if appropriate */
2190 if (hdw->hdw_desc->ir_scheme == PVR2_IR_SCHEME_ZILOG) {
2191 pvr2_issue_simple_cmd(hdw,
2192 FX2CMD_HCW_ZILOG_RESET |
2193 (1 << 8) |
2194 ((0) << 16));
2195 }
2196
d855497e 2197 // This step MUST happen after the earlier powerup step.
59af3367 2198 pvr2_i2c_track_init(hdw);
d855497e
MI		 2199 pvr2_i2c_core_init(hdw);
2200 if (!pvr2_hdw_dev_ok(hdw)) return;
2201
e9c64a78 2202 pvr2_hdw_load_modules(hdw);
1ab5e74f 2203 if (!pvr2_hdw_dev_ok(hdw)) return;
e9c64a78 2204
c05c0462 2205 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e
MI		 2206 cptr = hdw->controls + idx;
2207 if (cptr->info->skip_init) continue;
2208 if (!cptr->info->set_value) continue;
2209 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2210 }
2211
1bde0289
MI		 2212 /* Set up special default values for the television and radio
2213 frequencies here. It's not really important what these defaults
2214 are, but I set them to something usable in the Chicago area just
2215 to make driver testing a little easier. */
2216
5a4f5da6
MK		 2217 hdw->freqValTelevision = default_tv_freq;
2218 hdw->freqValRadio = default_radio_freq;
1bde0289 2219
d855497e
MI		 2220 // Do not use pvr2_reset_ctl_endpoints() here. It is not
2221 // thread-safe against the normal pvr2_send_request() mechanism.
2222 // (We should make it thread safe).
2223
aaf7884d
MI		 2224 if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2225 ret = pvr2_hdw_get_eeprom_addr(hdw);
d855497e 2226 if (!pvr2_hdw_dev_ok(hdw)) return;
aaf7884d
MI		 2227 if (ret < 0) {
2228 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2229 "Unable to determine location of eeprom,"
2230 " skipping");
2231 } else {
2232 hdw->eeprom_addr = ret;
2233 pvr2_eeprom_analyze(hdw);
2234 if (!pvr2_hdw_dev_ok(hdw)) return;
2235 }
2236 } else {
2237 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2238 hdw->tuner_updated = !0;
2239 hdw->std_mask_eeprom = V4L2_STD_ALL;
d855497e
MI		 2240 }
2241
13a88797
MI		 2242 if (hdw->serial_number) {
2243 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2244 "sn-%lu", hdw->serial_number);
2245 } else if (hdw->unit_number >= 0) {
2246 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2247 "unit-%c",
2248 hdw->unit_number + 'a');
2249 } else {
2250 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2251 "unit-??");
2252 }
2253 hdw->identifier[idx] = 0;
2254
d855497e
MI		 2255 pvr2_hdw_setup_std(hdw);
2256
2257 if (!get_default_tuner_type(hdw)) {
2258 pvr2_trace(PVR2_TRACE_INIT,
2259 "pvr2_hdw_setup: Tuner type overridden to %d",
2260 hdw->tuner_type);
2261 }
2262
d855497e
MI		 2263 pvr2_i2c_core_check_stale(hdw);
2264 hdw->tuner_updated = 0;
2265
2266 if (!pvr2_hdw_dev_ok(hdw)) return;
2267
1df59f0b
MI		 2268 if (hdw->hdw_desc->signal_routing_scheme ==
2269 PVR2_ROUTING_SCHEME_GOTVIEW) {
2270 /* Ensure that GPIO 11 is set to output for GOTVIEW
2271 hardware. */
2272 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2273 }
2274
681c7399 2275 pvr2_hdw_commit_setup(hdw);
d855497e
MI		 2276
2277 hdw->vid_stream = pvr2_stream_create();
2278 if (!pvr2_hdw_dev_ok(hdw)) return;
2279 pvr2_trace(PVR2_TRACE_INIT,
2280 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2281 if (hdw->vid_stream) {
2282 idx = get_default_error_tolerance(hdw);
2283 if (idx) {
2284 pvr2_trace(PVR2_TRACE_INIT,
2285 "pvr2_hdw_setup: video stream %p"
2286 " setting tolerance %u",
2287 hdw->vid_stream,idx);
2288 }
2289 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2290 PVR2_VID_ENDPOINT,idx);
2291 }
2292
2293 if (!pvr2_hdw_dev_ok(hdw)) return;
2294
d855497e 2295 hdw->flag_init_ok = !0;
681c7399
MI		 2296
2297 pvr2_hdw_state_sched(hdw);
d855497e
MI		 2298}
2299
2300
681c7399
MI		 2301/* Set up the structure and attempt to put the device into a usable state.
2302 This can be a time-consuming operation, which is why it is not done
2303 internally as part of the create() step. */
2304static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
d855497e
MI		 2305{
2306 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
681c7399 2307 do {
d855497e
MI		 2308 pvr2_hdw_setup_low(hdw);
2309 pvr2_trace(PVR2_TRACE_INIT,
2310 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
681c7399 2311 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
d855497e 2312 if (pvr2_hdw_dev_ok(hdw)) {
681c7399 2313 if (hdw->flag_init_ok) {
d855497e
MI		 2314 pvr2_trace(
2315 PVR2_TRACE_INFO,
2316 "Device initialization"
2317 " completed successfully.");
2318 break;
2319 }
2320 if (hdw->fw1_state == FW1_STATE_RELOAD) {
2321 pvr2_trace(
2322 PVR2_TRACE_INFO,
2323 "Device microcontroller firmware"
2324 " (re)loaded; it should now reset"
2325 " and reconnect.");
2326 break;
2327 }
2328 pvr2_trace(
2329 PVR2_TRACE_ERROR_LEGS,
2330 "Device initialization was not successful.");
2331 if (hdw->fw1_state == FW1_STATE_MISSING) {
2332 pvr2_trace(
2333 PVR2_TRACE_ERROR_LEGS,
2334 "Giving up since device"
2335 " microcontroller firmware"
2336 " appears to be missing.");
2337 break;
2338 }
2339 }
2340 if (procreload) {
2341 pvr2_trace(
2342 PVR2_TRACE_ERROR_LEGS,
2343 "Attempting pvrusb2 recovery by reloading"
2344 " primary firmware.");
2345 pvr2_trace(
2346 PVR2_TRACE_ERROR_LEGS,
2347 "If this works, device should disconnect"
2348 " and reconnect in a sane state.");
2349 hdw->fw1_state = FW1_STATE_UNKNOWN;
2350 pvr2_upload_firmware1(hdw);
2351 } else {
2352 pvr2_trace(
2353 PVR2_TRACE_ERROR_LEGS,
2354 "***WARNING*** pvrusb2 device hardware"
2355 " appears to be jammed"
2356 " and I can't clear it.");
2357 pvr2_trace(
2358 PVR2_TRACE_ERROR_LEGS,
2359 "You might need to power cycle"
2360 " the pvrusb2 device"
2361 " in order to recover.");
2362 }
681c7399 2363 } while (0);
d855497e 2364 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
d855497e
MI		 2365}
2366
2367
c4a8828d
MI		 2368/* Perform second stage initialization. Set callback pointer first so that
2369 we can avoid a possible initialization race (if the kernel thread runs
2370 before the callback has been set). */
794b1607
MI		 2371int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2372 void (*callback_func)(void *),
2373 void *callback_data)
c4a8828d
MI		 2374{
2375 LOCK_TAKE(hdw->big_lock); do {
97f26ff6
MI		 2376 if (hdw->flag_disconnected) {
2377 /* Handle a race here: If we're already
2378 disconnected by this point, then give up. If we
2379 get past this then we'll remain connected for
2380 the duration of initialization since the entire
2381 initialization sequence is now protected by the
2382 big_lock. */
2383 break;
2384 }
c4a8828d
MI		 2385 hdw->state_data = callback_data;
2386 hdw->state_func = callback_func;
97f26ff6 2387 pvr2_hdw_setup(hdw);
c4a8828d 2388 } while (0); LOCK_GIVE(hdw->big_lock);
794b1607 2389 return hdw->flag_init_ok;
c4a8828d
MI		 2390}
2391
2392
2393/* Create, set up, and return a structure for interacting with the
2394 underlying hardware. */
d855497e
MI		 2395struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2396 const struct usb_device_id *devid)
2397{
7fb20fa3 2398 unsigned int idx,cnt1,cnt2,m;
fe15f136 2399 struct pvr2_hdw *hdw = NULL;
d855497e
MI		 2400 int valid_std_mask;
2401 struct pvr2_ctrl *cptr;
b72b7bf5 2402 struct usb_device *usb_dev;
989eb154 2403 const struct pvr2_device_desc *hdw_desc;
d855497e 2404 __u8 ifnum;
b30d2441
MI		 2405 struct v4l2_queryctrl qctrl;
2406 struct pvr2_ctl_info *ciptr;
d855497e 2407
b72b7bf5
MI		 2408 usb_dev = interface_to_usbdev(intf);
2409
d130fa8a 2410 hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
d855497e 2411
fe15f136
MI		 2412 if (hdw_desc == NULL) {
2413 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2414 " No device description pointer,"
2415 " unable to continue.");
2416 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2417 " please contact Mike Isely <isely@pobox.com>"
2418 " to get it included in the driver\n");
2419 goto fail;
2420 }
2421
ca545f7c 2422 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
d855497e 2423 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
989eb154 2424 hdw,hdw_desc->description);
d855497e 2425 if (!hdw) goto fail;
681c7399
MI		 2426
2427 init_timer(&hdw->quiescent_timer);
2428 hdw->quiescent_timer.data = (unsigned long)hdw;
2429 hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2430
2431 init_timer(&hdw->encoder_wait_timer);
2432 hdw->encoder_wait_timer.data = (unsigned long)hdw;
2433 hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2434
d913d630
MI		 2435 init_timer(&hdw->encoder_run_timer);
2436 hdw->encoder_run_timer.data = (unsigned long)hdw;
2437 hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2438
681c7399
MI		 2439 hdw->master_state = PVR2_STATE_DEAD;
2440
2441 init_waitqueue_head(&hdw->state_wait_data);
2442
18103c57 2443 hdw->tuner_signal_stale = !0;
b30d2441 2444 cx2341x_fill_defaults(&hdw->enc_ctl_state);
d855497e 2445
7fb20fa3
MI		 2446 /* Calculate which inputs are OK */
2447 m = 0;
2448 if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
e8f5bacf
MI		 2449 if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2450 m |= 1 << PVR2_CVAL_INPUT_DTV;
2451 }
7fb20fa3
MI		 2452 if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2453 if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2454 if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2455 hdw->input_avail_mask = m;
1cb03b76 2456 hdw->input_allowed_mask = hdw->input_avail_mask;
7fb20fa3 2457
62433e31
MI		 2458 /* If not a hybrid device, pathway_state never changes. So
2459 initialize it here to what it should forever be. */
2460 if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2461 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2462 } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2463 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2464 }
2465
c05c0462 2466 hdw->control_cnt = CTRLDEF_COUNT;
b30d2441 2467 hdw->control_cnt += MPEGDEF_COUNT;
ca545f7c 2468 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
d855497e
MI		 2469 GFP_KERNEL);
2470 if (!hdw->controls) goto fail;
989eb154 2471 hdw->hdw_desc = hdw_desc;
c05c0462
MI		 2472 for (idx = 0; idx < hdw->control_cnt; idx++) {
2473 cptr = hdw->controls + idx;
2474 cptr->hdw = hdw;
2475 }
d855497e
MI		 2476 for (idx = 0; idx < 32; idx++) {
2477 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2478 }
c05c0462 2479 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e 2480 cptr = hdw->controls + idx;
d855497e
MI		 2481 cptr->info = control_defs+idx;
2482 }
dbc40a0e
MI		 2483
2484 /* Ensure that default input choice is a valid one. */
2485 m = hdw->input_avail_mask;
2486 if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2487 if (!((1 << idx) & m)) continue;
2488 hdw->input_val = idx;
2489 break;
2490 }
2491
b30d2441 2492 /* Define and configure additional controls from cx2341x module. */
ca545f7c 2493 hdw->mpeg_ctrl_info = kzalloc(
b30d2441
MI		 2494 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2495 if (!hdw->mpeg_ctrl_info) goto fail;
b30d2441
MI		 2496 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2497 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2498 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2499 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2500 ciptr->name = mpeg_ids[idx].strid;
2501 ciptr->v4l_id = mpeg_ids[idx].id;
2502 ciptr->skip_init = !0;
2503 ciptr->get_value = ctrl_cx2341x_get;
2504 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2505 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2506 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2507 qctrl.id = ciptr->v4l_id;
2508 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2509 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2510 ciptr->set_value = ctrl_cx2341x_set;
2511 }
2512 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2513 PVR2_CTLD_INFO_DESC_SIZE);
2514 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2515 ciptr->default_value = qctrl.default_value;
2516 switch (qctrl.type) {
2517 default:
2518 case V4L2_CTRL_TYPE_INTEGER:
2519 ciptr->type = pvr2_ctl_int;
2520 ciptr->def.type_int.min_value = qctrl.minimum;
2521 ciptr->def.type_int.max_value = qctrl.maximum;
2522 break;
2523 case V4L2_CTRL_TYPE_BOOLEAN:
2524 ciptr->type = pvr2_ctl_bool;
2525 break;
2526 case V4L2_CTRL_TYPE_MENU:
2527 ciptr->type = pvr2_ctl_enum;
2528 ciptr->def.type_enum.value_names =
e0e31cdb
HV		 2529 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2530 ciptr->v4l_id);
b30d2441
MI		 2531 for (cnt1 = 0;
2532 ciptr->def.type_enum.value_names[cnt1] != NULL;
2533 cnt1++) { }
2534 ciptr->def.type_enum.count = cnt1;
2535 break;
2536 }
2537 cptr->info = ciptr;
2538 }
d855497e
MI		 2539
2540 // Initialize video standard enum dynamic control
2541 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2542 if (cptr) {
2543 memcpy(&hdw->std_info_enum,cptr->info,
2544 sizeof(hdw->std_info_enum));
2545 cptr->info = &hdw->std_info_enum;
2546
2547 }
2548 // Initialize control data regarding video standard masks
2549 valid_std_mask = pvr2_std_get_usable();
2550 for (idx = 0; idx < 32; idx++) {
2551 if (!(valid_std_mask & (1 << idx))) continue;
2552 cnt1 = pvr2_std_id_to_str(
2553 hdw->std_mask_names[idx],
2554 sizeof(hdw->std_mask_names[idx])-1,
2555 1 << idx);
2556 hdw->std_mask_names[idx][cnt1] = 0;
2557 }
2558 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2559 if (cptr) {
2560 memcpy(&hdw->std_info_avail,cptr->info,
2561 sizeof(hdw->std_info_avail));
2562 cptr->info = &hdw->std_info_avail;
2563 hdw->std_info_avail.def.type_bitmask.bit_names =
2564 hdw->std_mask_ptrs;
2565 hdw->std_info_avail.def.type_bitmask.valid_bits =
2566 valid_std_mask;
2567 }
2568 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2569 if (cptr) {
2570 memcpy(&hdw->std_info_cur,cptr->info,
2571 sizeof(hdw->std_info_cur));
2572 cptr->info = &hdw->std_info_cur;
2573 hdw->std_info_cur.def.type_bitmask.bit_names =
2574 hdw->std_mask_ptrs;
2575 hdw->std_info_avail.def.type_bitmask.valid_bits =
2576 valid_std_mask;
2577 }
2578
432907f7 2579 hdw->cropcap_stale = !0;
d855497e
MI		 2580 hdw->eeprom_addr = -1;
2581 hdw->unit_number = -1;
8079384e
MI		 2582 hdw->v4l_minor_number_video = -1;
2583 hdw->v4l_minor_number_vbi = -1;
fd5a75fe 2584 hdw->v4l_minor_number_radio = -1;
d855497e
MI		 2585 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2586 if (!hdw->ctl_write_buffer) goto fail;
2587 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2588 if (!hdw->ctl_read_buffer) goto fail;
2589 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2590 if (!hdw->ctl_write_urb) goto fail;
2591 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2592 if (!hdw->ctl_read_urb) goto fail;
2593
b72b7bf5
MI		 2594 if (v4l2_device_register(&usb_dev->dev, &hdw->v4l2_dev) != 0) {
2595 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2596 "Error registering with v4l core, giving up");
2597 goto fail;
2598 }
8df0c87c 2599 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2600 for (idx = 0; idx < PVR_NUM; idx++) {
2601 if (unit_pointers[idx]) continue;
2602 hdw->unit_number = idx;
2603 unit_pointers[idx] = hdw;
2604 break;
2605 }
8df0c87c 2606 } while (0); mutex_unlock(&pvr2_unit_mtx);
d855497e
MI		 2607
2608 cnt1 = 0;
2609 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2610 cnt1 += cnt2;
2611 if (hdw->unit_number >= 0) {
2612 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2613 ('a' + hdw->unit_number));
2614 cnt1 += cnt2;
2615 }
2616 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2617 hdw->name[cnt1] = 0;
2618
681c7399
MI		 2619 hdw->workqueue = create_singlethread_workqueue(hdw->name);
2620 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2621 INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
681c7399 2622
d855497e
MI		 2623 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2624 hdw->unit_number,hdw->name);
2625
2626 hdw->tuner_type = -1;
2627 hdw->flag_ok = !0;
d855497e
MI		 2628
2629 hdw->usb_intf = intf;
b72b7bf5 2630 hdw->usb_dev = usb_dev;
d855497e 2631
87e3495c 2632 usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
31a18547 2633
d855497e
MI		 2634 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2635 usb_set_interface(hdw->usb_dev,ifnum,0);
2636
2637 mutex_init(&hdw->ctl_lock_mutex);
2638 mutex_init(&hdw->big_lock_mutex);
2639
2640 return hdw;
2641 fail:
2642 if (hdw) {
681c7399 2643 del_timer_sync(&hdw->quiescent_timer);
d913d630 2644 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 2645 del_timer_sync(&hdw->encoder_wait_timer);
2646 if (hdw->workqueue) {
2647 flush_workqueue(hdw->workqueue);
2648 destroy_workqueue(hdw->workqueue);
2649 hdw->workqueue = NULL;
2650 }
5e55d2ce
MK		 2651 usb_free_urb(hdw->ctl_read_urb);
2652 usb_free_urb(hdw->ctl_write_urb);
22071a42
MK		 2653 kfree(hdw->ctl_read_buffer);
2654 kfree(hdw->ctl_write_buffer);
2655 kfree(hdw->controls);
2656 kfree(hdw->mpeg_ctrl_info);
681c7399
MI		 2657 kfree(hdw->std_defs);
2658 kfree(hdw->std_enum_names);
d855497e
MI		 2659 kfree(hdw);
2660 }
a0fd1cb1 2661 return NULL;
d855497e
MI		 2662}
2663
2664
2665/* Remove _all_ associations between this driver and the underlying USB
2666 layer. */
07e337ee 2667static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
d855497e
MI		 2668{
2669 if (hdw->flag_disconnected) return;
2670 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2671 if (hdw->ctl_read_urb) {
2672 usb_kill_urb(hdw->ctl_read_urb);
2673 usb_free_urb(hdw->ctl_read_urb);
a0fd1cb1 2674 hdw->ctl_read_urb = NULL;
d855497e
MI		 2675 }
2676 if (hdw->ctl_write_urb) {
2677 usb_kill_urb(hdw->ctl_write_urb);
2678 usb_free_urb(hdw->ctl_write_urb);
a0fd1cb1 2679 hdw->ctl_write_urb = NULL;
d855497e
MI		 2680 }
2681 if (hdw->ctl_read_buffer) {
2682 kfree(hdw->ctl_read_buffer);
a0fd1cb1 2683 hdw->ctl_read_buffer = NULL;
d855497e
MI		 2684 }
2685 if (hdw->ctl_write_buffer) {
2686 kfree(hdw->ctl_write_buffer);
a0fd1cb1 2687 hdw->ctl_write_buffer = NULL;
d855497e 2688 }
d855497e 2689 hdw->flag_disconnected = !0;
b72b7bf5
MI		 2690 /* If we don't do this, then there will be a dangling struct device
2691 reference to our disappearing device persisting inside the V4L
2692 core... */
2693 if (hdw->v4l2_dev.dev) {
2694 dev_set_drvdata(hdw->v4l2_dev.dev, NULL);
2695 hdw->v4l2_dev.dev = NULL;
2696 }
a0fd1cb1
MI		 2697 hdw->usb_dev = NULL;
2698 hdw->usb_intf = NULL;
681c7399 2699 pvr2_hdw_render_useless(hdw);
d855497e
MI		 2700}
2701
2702
2703/* Destroy hardware interaction structure */
2704void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2705{
401c27ce 2706 if (!hdw) return;
d855497e 2707 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
681c7399
MI		 2708 if (hdw->workqueue) {
2709 flush_workqueue(hdw->workqueue);
2710 destroy_workqueue(hdw->workqueue);
2711 hdw->workqueue = NULL;
2712 }
8f59100a 2713 del_timer_sync(&hdw->quiescent_timer);
d913d630 2714 del_timer_sync(&hdw->encoder_run_timer);
8f59100a 2715 del_timer_sync(&hdw->encoder_wait_timer);
d855497e
MI		 2716 if (hdw->fw_buffer) {
2717 kfree(hdw->fw_buffer);
a0fd1cb1 2718 hdw->fw_buffer = NULL;
d855497e
MI		 2719 }
2720 if (hdw->vid_stream) {
2721 pvr2_stream_destroy(hdw->vid_stream);
a0fd1cb1 2722 hdw->vid_stream = NULL;
d855497e 2723 }
d855497e
MI		 2724 if (hdw->decoder_ctrl) {
2725 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2726 }
2727 pvr2_i2c_core_done(hdw);
59af3367 2728 pvr2_i2c_track_done(hdw);
b72b7bf5 2729 v4l2_device_unregister(&hdw->v4l2_dev);
d855497e 2730 pvr2_hdw_remove_usb_stuff(hdw);
8df0c87c 2731 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2732 if ((hdw->unit_number >= 0) &&
2733 (hdw->unit_number < PVR_NUM) &&
2734 (unit_pointers[hdw->unit_number] == hdw)) {
a0fd1cb1 2735 unit_pointers[hdw->unit_number] = NULL;
d855497e 2736 }
8df0c87c 2737 } while (0); mutex_unlock(&pvr2_unit_mtx);
22071a42
MK		 2738 kfree(hdw->controls);
2739 kfree(hdw->mpeg_ctrl_info);
2740 kfree(hdw->std_defs);
2741 kfree(hdw->std_enum_names);
d855497e
MI		 2742 kfree(hdw);
2743}
2744
2745
d855497e
MI		 2746int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2747{
2748 return (hdw && hdw->flag_ok);
2749}
2750
2751
2752/* Called when hardware has been unplugged */
2753void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2754{
2755 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2756 LOCK_TAKE(hdw->big_lock);
2757 LOCK_TAKE(hdw->ctl_lock);
2758 pvr2_hdw_remove_usb_stuff(hdw);
2759 LOCK_GIVE(hdw->ctl_lock);
2760 LOCK_GIVE(hdw->big_lock);
2761}
2762
2763
2764// Attempt to autoselect an appropriate value for std_enum_cur given
2765// whatever is currently in std_mask_cur
07e337ee 2766static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
d855497e
MI		 2767{
2768 unsigned int idx;
2769 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2770 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2771 hdw->std_enum_cur = idx;
2772 return;
2773 }
2774 }
2775 hdw->std_enum_cur = 0;
2776}
2777
2778
2779// Calculate correct set of enumerated standards based on currently known
2780// set of available standards bits.
07e337ee 2781static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
d855497e
MI		 2782{
2783 struct v4l2_standard *newstd;
2784 unsigned int std_cnt;
2785 unsigned int idx;
2786
2787 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2788
2789 if (hdw->std_defs) {
2790 kfree(hdw->std_defs);
a0fd1cb1 2791 hdw->std_defs = NULL;
d855497e
MI		 2792 }
2793 hdw->std_enum_cnt = 0;
2794 if (hdw->std_enum_names) {
2795 kfree(hdw->std_enum_names);
a0fd1cb1 2796 hdw->std_enum_names = NULL;
d855497e
MI		 2797 }
2798
2799 if (!std_cnt) {
2800 pvr2_trace(
2801 PVR2_TRACE_ERROR_LEGS,
2802 "WARNING: Failed to identify any viable standards");
2803 }
2804 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2805 hdw->std_enum_names[0] = "none";
2806 for (idx = 0; idx < std_cnt; idx++) {
2807 hdw->std_enum_names[idx+1] =
2808 newstd[idx].name;
2809 }
2810 // Set up the dynamic control for this standard
2811 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2812 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2813 hdw->std_defs = newstd;
2814 hdw->std_enum_cnt = std_cnt+1;
2815 hdw->std_enum_cur = 0;
2816 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2817}
2818
2819
2820int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2821 struct v4l2_standard *std,
2822 unsigned int idx)
2823{
2824 int ret = -EINVAL;
2825 if (!idx) return ret;
2826 LOCK_TAKE(hdw->big_lock); do {
2827 if (idx >= hdw->std_enum_cnt) break;
2828 idx--;
2829 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2830 ret = 0;
2831 } while (0); LOCK_GIVE(hdw->big_lock);
2832 return ret;
2833}
2834
2835
2836/* Get the number of defined controls */
2837unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2838{
c05c0462 2839 return hdw->control_cnt;
d855497e
MI		 2840}
2841
2842
2843/* Retrieve a control handle given its index (0..count-1) */
2844struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2845 unsigned int idx)
2846{
a0fd1cb1 2847 if (idx >= hdw->control_cnt) return NULL;
d855497e
MI		 2848 return hdw->controls + idx;
2849}
2850
2851
2852/* Retrieve a control handle given its index (0..count-1) */
2853struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2854 unsigned int ctl_id)
2855{
2856 struct pvr2_ctrl *cptr;
2857 unsigned int idx;
2858 int i;
2859
2860 /* This could be made a lot more efficient, but for now... */
c05c0462 2861 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2862 cptr = hdw->controls + idx;
2863 i = cptr->info->internal_id;
2864 if (i && (i == ctl_id)) return cptr;
2865 }
a0fd1cb1 2866 return NULL;
d855497e
MI		 2867}
2868
2869
a761f431 2870/* Given a V4L ID, retrieve the control structure associated with it. */
d855497e
MI		 2871struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2872{
2873 struct pvr2_ctrl *cptr;
2874 unsigned int idx;
2875 int i;
2876
2877 /* This could be made a lot more efficient, but for now... */
c05c0462 2878 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2879 cptr = hdw->controls + idx;
2880 i = cptr->info->v4l_id;
2881 if (i && (i == ctl_id)) return cptr;
2882 }
a0fd1cb1 2883 return NULL;
d855497e
MI		 2884}
2885
2886
a761f431
MI		 2887/* Given a V4L ID for its immediate predecessor, retrieve the control
2888 structure associated with it. */
2889struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2890 unsigned int ctl_id)
2891{
2892 struct pvr2_ctrl *cptr,*cp2;
2893 unsigned int idx;
2894 int i;
2895
2896 /* This could be made a lot more efficient, but for now... */
a0fd1cb1 2897 cp2 = NULL;
a761f431
MI		 2898 for (idx = 0; idx < hdw->control_cnt; idx++) {
2899 cptr = hdw->controls + idx;
2900 i = cptr->info->v4l_id;
2901 if (!i) continue;
2902 if (i <= ctl_id) continue;
2903 if (cp2 && (cp2->info->v4l_id < i)) continue;
2904 cp2 = cptr;
2905 }
2906 return cp2;
a0fd1cb1 2907 return NULL;
a761f431
MI		 2908}
2909
2910
d855497e
MI		 2911static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2912{
2913 switch (tp) {
2914 case pvr2_ctl_int: return "integer";
2915 case pvr2_ctl_enum: return "enum";
33213963 2916 case pvr2_ctl_bool: return "boolean";
d855497e
MI		 2917 case pvr2_ctl_bitmask: return "bitmask";
2918 }
2919 return "";
2920}
2921
2922
2641df36
MI		 2923static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2924 const char *name, int val)
2925{
2926 struct v4l2_control ctrl;
2927 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2928 memset(&ctrl, 0, sizeof(ctrl));
2929 ctrl.id = id;
2930 ctrl.value = val;
2931 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2932}
2933
2934#define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
2935 if ((hdw)->lab##_dirty) { \
2936 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2937 }
2938
5ceaad14 2939/* Execute whatever commands are required to update the state of all the
2641df36 2940 sub-devices so that they match our current control values. */
5ceaad14
MI		 2941static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2942{
edb9dcb8
MI		 2943 struct v4l2_subdev *sd;
2944 unsigned int id;
2945 pvr2_subdev_update_func fp;
2946
2641df36
MI		 2947 if (hdw->input_dirty || hdw->std_dirty) {
2948 pvr2_trace(PVR2_TRACE_CHIPS,"subdev v4l2 set_standard");
2949 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2950 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2951 tuner, s_radio);
2952 } else {
2953 v4l2_std_id vs;
2954 vs = hdw->std_mask_cur;
2955 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2956 tuner, s_std, vs);
2957 }
2958 hdw->tuner_signal_stale = !0;
2959 hdw->cropcap_stale = !0;
2960 }
2961
2962 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2963 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2964 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2965 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2966 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2967 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2968 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2969 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2970 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2971
2972 if (hdw->input_dirty || hdw->audiomode_dirty) {
2973 struct v4l2_tuner vt;
2974 memset(&vt, 0, sizeof(vt));
2975 vt.audmode = hdw->audiomode_val;
2976 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
2977 }
2978
2979 if (hdw->freqDirty) {
2980 unsigned long fv;
2981 struct v4l2_frequency freq;
2982 fv = pvr2_hdw_get_cur_freq(hdw);
2983 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
2984 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
2985 memset(&freq, 0, sizeof(freq));
2986 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
2987 /* ((fv * 1000) / 62500) */
2988 freq.frequency = (fv * 2) / 125;
2989 } else {
2990 freq.frequency = fv / 62500;
2991 }
2992 /* tuner-core currently doesn't seem to care about this, but
2993 let's set it anyway for completeness. */
2994 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2995 freq.type = V4L2_TUNER_RADIO;
2996 } else {
2997 freq.type = V4L2_TUNER_ANALOG_TV;
2998 }
2999 freq.tuner = 0;
3000 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
3001 s_frequency, &freq);
3002 }
3003
3004 if (hdw->res_hor_dirty || hdw->res_ver_dirty) {
3005 struct v4l2_format fmt;
3006 memset(&fmt, 0, sizeof(fmt));
3007 fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
3008 fmt.fmt.pix.width = hdw->res_hor_val;
3009 fmt.fmt.pix.height = hdw->res_ver_val;
3010 pvr2_trace(PVR2_TRACE_CHIPS,"subdev v4l2 set_size(%dx%d)",
3011 fmt.fmt.pix.width, fmt.fmt.pix.height);
3012 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_fmt, &fmt);
3013 }
3014
01c59df8
MI		 3015 if (hdw->srate_dirty) {
3016 u32 val;
3017 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
3018 hdw->srate_val);
3019 switch (hdw->srate_val) {
3020 default:
3021 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
3022 val = 48000;
3023 break;
3024 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
3025 val = 44100;
3026 break;
3027 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
3028 val = 32000;
3029 break;
3030 }
3031 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3032 audio, s_clock_freq, val);
3033 }
3034
2641df36
MI		 3035 /* Unable to set crop parameters; there is apparently no equivalent
3036 for VIDIOC_S_CROP */
3037
edb9dcb8
MI		 3038 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
3039 id = sd->grp_id;
3040 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
3041 fp = pvr2_module_update_functions[id];
3042 if (!fp) continue;
3043 (*fp)(hdw, sd);
3044 }
2641df36
MI		 3045
3046 if (hdw->tuner_signal_stale && hdw->cropcap_stale) {
3047 pvr2_hdw_status_poll(hdw);
3048 }
5ceaad14
MI		 3049}
3050
3051
681c7399
MI		 3052/* Figure out if we need to commit control changes. If so, mark internal
3053 state flags to indicate this fact and return true. Otherwise do nothing
3054 else and return false. */
3055static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
d855497e 3056{
d855497e
MI		 3057 unsigned int idx;
3058 struct pvr2_ctrl *cptr;
3059 int value;
3060 int commit_flag = 0;
3061 char buf[100];
3062 unsigned int bcnt,ccnt;
3063
c05c0462 3064 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e 3065 cptr = hdw->controls + idx;
5fa1247a 3066 if (!cptr->info->is_dirty) continue;
d855497e 3067 if (!cptr->info->is_dirty(cptr)) continue;
fe23a280 3068 commit_flag = !0;
d855497e 3069
fe23a280 3070 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
d855497e
MI		 3071 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3072 cptr->info->name);
3073 value = 0;
3074 cptr->info->get_value(cptr,&value);
3075 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3076 buf+bcnt,
3077 sizeof(buf)-bcnt,&ccnt);
3078 bcnt += ccnt;
3079 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3080 get_ctrl_typename(cptr->info->type));
3081 pvr2_trace(PVR2_TRACE_CTL,
3082 "/*--TRACE_COMMIT--*/ %.*s",
3083 bcnt,buf);
3084 }
3085
3086 if (!commit_flag) {
3087 /* Nothing has changed */
3088 return 0;
3089 }
3090
681c7399
MI		 3091 hdw->state_pipeline_config = 0;
3092 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3093 pvr2_hdw_state_sched(hdw);
3094
3095 return !0;
3096}
3097
3098
3099/* Perform all operations needed to commit all control changes. This must
3100 be performed in synchronization with the pipeline state and is thus
3101 expected to be called as part of the driver's worker thread. Return
3102 true if commit successful, otherwise return false to indicate that
3103 commit isn't possible at this time. */
3104static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3105{
3106 unsigned int idx;
3107 struct pvr2_ctrl *cptr;
3108 int disruptive_change;
3109
ab062fe3
MI		 3110 /* Handle some required side effects when the video standard is
3111 changed.... */
d855497e 3112 if (hdw->std_dirty) {
d855497e 3113 int nvres;
00528d9c 3114 int gop_size;
d855497e
MI		 3115 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3116 nvres = 480;
00528d9c 3117 gop_size = 15;
d855497e
MI		 3118 } else {
3119 nvres = 576;
00528d9c 3120 gop_size = 12;
d855497e 3121 }
00528d9c
MI		 3122 /* Rewrite the vertical resolution to be appropriate to the
3123 video standard that has been selected. */
d855497e
MI		 3124 if (nvres != hdw->res_ver_val) {
3125 hdw->res_ver_val = nvres;
3126 hdw->res_ver_dirty = !0;
3127 }
00528d9c
MI		 3128 /* Rewrite the GOP size to be appropriate to the video
3129 standard that has been selected. */
3130 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3131 struct v4l2_ext_controls cs;
3132 struct v4l2_ext_control c1;
3133 memset(&cs, 0, sizeof(cs));
3134 memset(&c1, 0, sizeof(c1));
3135 cs.controls = &c1;
3136 cs.count = 1;
3137 c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3138 c1.value = gop_size;
3139 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3140 VIDIOC_S_EXT_CTRLS);
3141 }
d855497e
MI		 3142 }
3143
38d9a2cf 3144 if (hdw->input_dirty && hdw->state_pathway_ok &&
62433e31
MI		 3145 (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3146 PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3147 hdw->pathway_state)) {
3148 /* Change of mode being asked for... */
3149 hdw->state_pathway_ok = 0;
e9db1ff2 3150 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 3151 }
3152 if (!hdw->state_pathway_ok) {
3153 /* Can't commit anything until pathway is ok. */
3154 return 0;
3155 }
e784bfb9 3156 /* The broadcast decoder can only scale down, so if
3157 * res_*_dirty && crop window < output format ==> enlarge crop.
3158 *
3159 * The mpeg encoder receives fields of res_hor_val dots and
3160 * res_ver_val halflines. Limits: hor<=720, ver<=576.
3161 */
3162 if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3163 hdw->cropw_val = hdw->res_hor_val;
3164 hdw->cropw_dirty = !0;
3165 } else if (hdw->cropw_dirty) {
3166 hdw->res_hor_dirty = !0; /* must rescale */
3167 hdw->res_hor_val = min(720, hdw->cropw_val);
3168 }
3169 if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3170 hdw->croph_val = hdw->res_ver_val;
3171 hdw->croph_dirty = !0;
3172 } else if (hdw->croph_dirty) {
3173 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3174 hdw->res_ver_dirty = !0;
3175 hdw->res_ver_val = min(nvres, hdw->croph_val);
3176 }
3177
681c7399
MI		 3178 /* If any of the below has changed, then we can't do the update
3179 while the pipeline is running. Pipeline must be paused first
3180 and decoder -> encoder connection be made quiescent before we
3181 can proceed. */
3182 disruptive_change =
3183 (hdw->std_dirty ||
3184 hdw->enc_unsafe_stale ||
3185 hdw->srate_dirty ||
3186 hdw->res_ver_dirty ||
3187 hdw->res_hor_dirty ||
755879c6
MI		 3188 hdw->cropw_dirty ||
3189 hdw->croph_dirty ||
681c7399
MI		 3190 hdw->input_dirty ||
3191 (hdw->active_stream_type != hdw->desired_stream_type));
3192 if (disruptive_change && !hdw->state_pipeline_idle) {
3193 /* Pipeline is not idle; we can't proceed. Arrange to
3194 cause pipeline to stop so that we can try this again
3195 later.... */
3196 hdw->state_pipeline_pause = !0;
3197 return 0;
275b2e28
PK		 3198 }
3199
b30d2441
MI		 3200 if (hdw->srate_dirty) {
3201 /* Write new sample rate into control structure since
3202 * the master copy is stale. We must track srate
3203 * separate from the mpeg control structure because
3204 * other logic also uses this value. */
3205 struct v4l2_ext_controls cs;
3206 struct v4l2_ext_control c1;
3207 memset(&cs,0,sizeof(cs));
3208 memset(&c1,0,sizeof(c1));
3209 cs.controls = &c1;
3210 cs.count = 1;
3211 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3212 c1.value = hdw->srate_val;
01f1e44f 3213 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
b30d2441 3214 }
c05c0462 3215
d855497e
MI		 3216 /* Scan i2c core at this point - before we clear all the dirty
3217 bits. Various parts of the i2c core will notice dirty bits as
3218 appropriate and arrange to broadcast or directly send updates to
3219 the client drivers in order to keep everything in sync */
3220 pvr2_i2c_core_check_stale(hdw);
3221
681c7399
MI		 3222 if (hdw->active_stream_type != hdw->desired_stream_type) {
3223 /* Handle any side effects of stream config here */
3224 hdw->active_stream_type = hdw->desired_stream_type;
3225 }
3226
1df59f0b
MI		 3227 if (hdw->hdw_desc->signal_routing_scheme ==
3228 PVR2_ROUTING_SCHEME_GOTVIEW) {
3229 u32 b;
3230 /* Handle GOTVIEW audio switching */
3231 pvr2_hdw_gpio_get_out(hdw,&b);
3232 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3233 /* Set GPIO 11 */
3234 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3235 } else {
3236 /* Clear GPIO 11 */
3237 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3238 }
3239 }
3240
5ceaad14
MI		 3241 for (idx = 0; idx < hdw->control_cnt; idx++) {
3242 cptr = hdw->controls + idx;
3243 if (!cptr->info->clear_dirty) continue;
3244 cptr->info->clear_dirty(cptr);
3245 }
3246
3247 /* Check and update state for all sub-devices. */
3248 pvr2_subdev_update(hdw);
3249
d855497e
MI		 3250 /* Now execute i2c core update */
3251 pvr2_i2c_core_sync(hdw);
3252
62433e31
MI		 3253 if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3254 hdw->state_encoder_run) {
3255 /* If encoder isn't running or it can't be touched, then
3256 this will get worked out later when we start the
3257 encoder. */
681c7399
MI		 3258 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3259 }
d855497e 3260
681c7399 3261 hdw->state_pipeline_config = !0;
432907f7
MI		 3262 /* Hardware state may have changed in a way to cause the cropping
3263 capabilities to have changed. So mark it stale, which will
3264 cause a later re-fetch. */
681c7399
MI		 3265 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3266 return !0;
d855497e
MI		 3267}
3268
3269
3270int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3271{
681c7399
MI		 3272 int fl;
3273 LOCK_TAKE(hdw->big_lock);
3274 fl = pvr2_hdw_commit_setup(hdw);
3275 LOCK_GIVE(hdw->big_lock);
3276 if (!fl) return 0;
3277 return pvr2_hdw_wait(hdw,0);
3278}
3279
3280
3281static void pvr2_hdw_worker_i2c(struct work_struct *work)
3282{
3283 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
d855497e 3284 LOCK_TAKE(hdw->big_lock); do {
681c7399 3285 pvr2_i2c_core_sync(hdw);
d855497e 3286 } while (0); LOCK_GIVE(hdw->big_lock);
d855497e
MI		 3287}
3288
3289
681c7399 3290static void pvr2_hdw_worker_poll(struct work_struct *work)
d855497e 3291{
681c7399
MI		 3292 int fl = 0;
3293 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
d855497e 3294 LOCK_TAKE(hdw->big_lock); do {
681c7399 3295 fl = pvr2_hdw_state_eval(hdw);
d855497e 3296 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 3297 if (fl && hdw->state_func) {
3298 hdw->state_func(hdw->state_data);
3299 }
d855497e
MI		 3300}
3301
3302
681c7399 3303static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
d855497e 3304{
681c7399
MI		 3305 return wait_event_interruptible(
3306 hdw->state_wait_data,
3307 (hdw->state_stale == 0) &&
3308 (!state || (hdw->master_state != state)));
3309}
3310
3311
d855497e
MI		 3312/* Return name for this driver instance */
3313const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3314{
3315 return hdw->name;
3316}
3317
3318
78a47101
MI		 3319const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3320{
3321 return hdw->hdw_desc->description;
3322}
3323
3324
3325const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3326{
3327 return hdw->hdw_desc->shortname;
3328}
3329
3330
d855497e
MI		 3331int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3332{
3333 int result;
3334 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 3335 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
d855497e
MI		 3336 result = pvr2_send_request(hdw,
3337 hdw->cmd_buffer,1,
3338 hdw->cmd_buffer,1);
3339 if (result < 0) break;
3340 result = (hdw->cmd_buffer[0] != 0);
3341 } while(0); LOCK_GIVE(hdw->ctl_lock);
3342 return result;
3343}
3344
3345
18103c57
MI		 3346/* Execute poll of tuner status */
3347void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
d855497e 3348{
d855497e 3349 LOCK_TAKE(hdw->big_lock); do {
a51f5000 3350 pvr2_hdw_status_poll(hdw);
d855497e 3351 } while (0); LOCK_GIVE(hdw->big_lock);
18103c57
MI		 3352}
3353
3354
432907f7
MI		 3355static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3356{
3357 if (!hdw->cropcap_stale) {
432907f7
MI		 3358 return 0;
3359 }
a51f5000 3360 pvr2_hdw_status_poll(hdw);
432907f7 3361 if (hdw->cropcap_stale) {
432907f7
MI		 3362 return -EIO;
3363 }
3364 return 0;
3365}
3366
3367
3368/* Return information about cropping capabilities */
3369int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3370{
3371 int stat = 0;
3372 LOCK_TAKE(hdw->big_lock);
3373 stat = pvr2_hdw_check_cropcap(hdw);
3374 if (!stat) {
432907f7
MI		 3375 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3376 }
3377 LOCK_GIVE(hdw->big_lock);
3378 return stat;
3379}
3380
3381
18103c57
MI		 3382/* Return information about the tuner */
3383int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3384{
3385 LOCK_TAKE(hdw->big_lock); do {
3386 if (hdw->tuner_signal_stale) {
a51f5000 3387 pvr2_hdw_status_poll(hdw);
18103c57
MI		 3388 }
3389 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3390 } while (0); LOCK_GIVE(hdw->big_lock);
3391 return 0;
d855497e
MI		 3392}
3393
3394
3395/* Get handle to video output stream */
3396struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3397{
3398 return hp->vid_stream;
3399}
3400
3401
3402void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3403{
4f1a3e5b 3404 int nr = pvr2_hdw_get_unit_number(hdw);
d855497e 3405 LOCK_TAKE(hdw->big_lock); do {
4f1a3e5b 3406 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
5ceaad14 3407 hdw->log_requested = !0;
d855497e 3408 pvr2_i2c_core_check_stale(hdw);
d855497e 3409 pvr2_i2c_core_sync(hdw);
a51f5000 3410 hdw->log_requested = 0;
ed3261a8 3411 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
b30d2441 3412 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
99eb44fe 3413 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
681c7399 3414 pvr2_hdw_state_log_state(hdw);
4f1a3e5b 3415 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
d855497e
MI		 3416 } while (0); LOCK_GIVE(hdw->big_lock);
3417}
3418
4db666cc
MI		 3419
3420/* Grab EEPROM contents, needed for direct method. */
3421#define EEPROM_SIZE 8192
3422#define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3423static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3424{
3425 struct i2c_msg msg[2];
3426 u8 *eeprom;
3427 u8 iadd[2];
3428 u8 addr;
3429 u16 eepromSize;
3430 unsigned int offs;
3431 int ret;
3432 int mode16 = 0;
3433 unsigned pcnt,tcnt;
3434 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3435 if (!eeprom) {
3436 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3437 "Failed to allocate memory"
3438 " required to read eeprom");
3439 return NULL;
3440 }
3441
3442 trace_eeprom("Value for eeprom addr from controller was 0x%x",
3443 hdw->eeprom_addr);
3444 addr = hdw->eeprom_addr;
3445 /* Seems that if the high bit is set, then the *real* eeprom
3446 address is shifted right now bit position (noticed this in
3447 newer PVR USB2 hardware) */
3448 if (addr & 0x80) addr >>= 1;
3449
3450 /* FX2 documentation states that a 16bit-addressed eeprom is
3451 expected if the I2C address is an odd number (yeah, this is
3452 strange but it's what they do) */
3453 mode16 = (addr & 1);
3454 eepromSize = (mode16 ? EEPROM_SIZE : 256);
3455 trace_eeprom("Examining %d byte eeprom at location 0x%x"
3456 " using %d bit addressing",eepromSize,addr,
3457 mode16 ? 16 : 8);
3458
3459 msg[0].addr = addr;
3460 msg[0].flags = 0;
3461 msg[0].len = mode16 ? 2 : 1;
3462 msg[0].buf = iadd;
3463 msg[1].addr = addr;
3464 msg[1].flags = I2C_M_RD;
3465
3466 /* We have to do the actual eeprom data fetch ourselves, because
3467 (1) we're only fetching part of the eeprom, and (2) if we were
3468 getting the whole thing our I2C driver can't grab it in one
3469 pass - which is what tveeprom is otherwise going to attempt */
3470 memset(eeprom,0,EEPROM_SIZE);
3471 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3472 pcnt = 16;
3473 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3474 offs = tcnt + (eepromSize - EEPROM_SIZE);
3475 if (mode16) {
3476 iadd[0] = offs >> 8;
3477 iadd[1] = offs;
3478 } else {
3479 iadd[0] = offs;
3480 }
3481 msg[1].len = pcnt;
3482 msg[1].buf = eeprom+tcnt;
3483 if ((ret = i2c_transfer(&hdw->i2c_adap,
3484 msg,ARRAY_SIZE(msg))) != 2) {
3485 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3486 "eeprom fetch set offs err=%d",ret);
3487 kfree(eeprom);
3488 return NULL;
3489 }
3490 }
3491 return eeprom;
3492}
3493
3494
3495void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3496 int prom_flag,
3497 int enable_flag)
d855497e
MI		 3498{
3499 int ret;
3500 u16 address;
3501 unsigned int pipe;
3502 LOCK_TAKE(hdw->big_lock); do {
5fa1247a 3503 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
d855497e
MI		 3504
3505 if (!enable_flag) {
3506 pvr2_trace(PVR2_TRACE_FIRMWARE,
3507 "Cleaning up after CPU firmware fetch");
3508 kfree(hdw->fw_buffer);
a0fd1cb1 3509 hdw->fw_buffer = NULL;
d855497e 3510 hdw->fw_size = 0;
4db666cc
MI		 3511 if (hdw->fw_cpu_flag) {
3512 /* Now release the CPU. It will disconnect
3513 and reconnect later. */
3514 pvr2_hdw_cpureset_assert(hdw,0);
3515 }
d855497e
MI		 3516 break;
3517 }
3518
4db666cc
MI		 3519 hdw->fw_cpu_flag = (prom_flag == 0);
3520 if (hdw->fw_cpu_flag) {
3521 pvr2_trace(PVR2_TRACE_FIRMWARE,
3522 "Preparing to suck out CPU firmware");
3523 hdw->fw_size = 0x2000;
3524 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3525 if (!hdw->fw_buffer) {
3526 hdw->fw_size = 0;
3527 break;
3528 }
d855497e 3529
4db666cc
MI		 3530 /* We have to hold the CPU during firmware upload. */
3531 pvr2_hdw_cpureset_assert(hdw,1);
d855497e 3532
4db666cc
MI		 3533 /* download the firmware from address 0000-1fff in 2048
3534 (=0x800) bytes chunk. */
d855497e 3535
4db666cc
MI		 3536 pvr2_trace(PVR2_TRACE_FIRMWARE,
3537 "Grabbing CPU firmware");
3538 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3539 for(address = 0; address < hdw->fw_size;
3540 address += 0x800) {
3541 ret = usb_control_msg(hdw->usb_dev,pipe,
3542 0xa0,0xc0,
3543 address,0,
3544 hdw->fw_buffer+address,
3545 0x800,HZ);
3546 if (ret < 0) break;
3547 }
d855497e 3548
4db666cc
MI		 3549 pvr2_trace(PVR2_TRACE_FIRMWARE,
3550 "Done grabbing CPU firmware");
3551 } else {
3552 pvr2_trace(PVR2_TRACE_FIRMWARE,
3553 "Sucking down EEPROM contents");
3554 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3555 if (!hdw->fw_buffer) {
3556 pvr2_trace(PVR2_TRACE_FIRMWARE,
3557 "EEPROM content suck failed.");
3558 break;
3559 }
3560 hdw->fw_size = EEPROM_SIZE;
3561 pvr2_trace(PVR2_TRACE_FIRMWARE,
3562 "Done sucking down EEPROM contents");
3563 }
d855497e
MI		 3564
3565 } while (0); LOCK_GIVE(hdw->big_lock);
3566}
3567
3568
3569/* Return true if we're in a mode for retrieval CPU firmware */
3570int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3571{
5fa1247a 3572 return hdw->fw_buffer != NULL;
d855497e
MI		 3573}
3574
3575
3576int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3577 char *buf,unsigned int cnt)
3578{
3579 int ret = -EINVAL;
3580 LOCK_TAKE(hdw->big_lock); do {
3581 if (!buf) break;
3582 if (!cnt) break;
3583
3584 if (!hdw->fw_buffer) {
3585 ret = -EIO;
3586 break;
3587 }
3588
3589 if (offs >= hdw->fw_size) {
3590 pvr2_trace(PVR2_TRACE_FIRMWARE,
3591 "Read firmware data offs=%d EOF",
3592 offs);
3593 ret = 0;
3594 break;
3595 }
3596
3597 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3598
3599 memcpy(buf,hdw->fw_buffer+offs,cnt);
3600
3601 pvr2_trace(PVR2_TRACE_FIRMWARE,
3602 "Read firmware data offs=%d cnt=%d",
3603 offs,cnt);
3604 ret = cnt;
3605 } while (0); LOCK_GIVE(hdw->big_lock);
3606
3607 return ret;
3608}
3609
3610
fd5a75fe 3611int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
8079384e 3612 enum pvr2_v4l_type index)
d855497e 3613{
fd5a75fe 3614 switch (index) {
8079384e
MI		 3615 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3616 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3617 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
fd5a75fe
MI		 3618 default: return -1;
3619 }
d855497e
MI		 3620}
3621
3622
2fdf3d9c 3623/* Store a v4l minor device number */
fd5a75fe 3624void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
8079384e 3625 enum pvr2_v4l_type index,int v)
d855497e 3626{
fd5a75fe 3627 switch (index) {
8079384e
MI		 3628 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3629 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3630 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
fd5a75fe
MI		 3631 default: break;
3632 }
d855497e
MI		 3633}
3634
3635
7d12e780 3636static void pvr2_ctl_write_complete(struct urb *urb)
d855497e
MI		 3637{
3638 struct pvr2_hdw *hdw = urb->context;
3639 hdw->ctl_write_pend_flag = 0;
3640 if (hdw->ctl_read_pend_flag) return;
3641 complete(&hdw->ctl_done);
3642}
3643
3644
7d12e780 3645static void pvr2_ctl_read_complete(struct urb *urb)
d855497e
MI		 3646{
3647 struct pvr2_hdw *hdw = urb->context;
3648 hdw->ctl_read_pend_flag = 0;
3649 if (hdw->ctl_write_pend_flag) return;
3650 complete(&hdw->ctl_done);
3651}
3652
3653
3654static void pvr2_ctl_timeout(unsigned long data)
3655{
3656 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3657 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3658 hdw->ctl_timeout_flag = !0;
5e55d2ce 3659 if (hdw->ctl_write_pend_flag)
d855497e 3660 usb_unlink_urb(hdw->ctl_write_urb);
5e55d2ce 3661 if (hdw->ctl_read_pend_flag)
d855497e 3662 usb_unlink_urb(hdw->ctl_read_urb);
d855497e
MI		 3663 }
3664}
3665
3666
e61b6fc5
MI		 3667/* Issue a command and get a response from the device. This extended
3668 version includes a probe flag (which if set means that device errors
3669 should not be logged or treated as fatal) and a timeout in jiffies.
3670 This can be used to non-lethally probe the health of endpoint 1. */
07e337ee
AB		 3671static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3672 unsigned int timeout,int probe_fl,
3673 void *write_data,unsigned int write_len,
3674 void *read_data,unsigned int read_len)
d855497e
MI		 3675{
3676 unsigned int idx;
3677 int status = 0;
3678 struct timer_list timer;
3679 if (!hdw->ctl_lock_held) {
3680 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3681 "Attempted to execute control transfer"
3682 " without lock!!");
3683 return -EDEADLK;
3684 }
681c7399 3685 if (!hdw->flag_ok && !probe_fl) {
d855497e
MI		 3686 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3687 "Attempted to execute control transfer"
3688 " when device not ok");
3689 return -EIO;
3690 }
3691 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3692 if (!probe_fl) {
3693 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3694 "Attempted to execute control transfer"
3695 " when USB is disconnected");
3696 }
3697 return -ENOTTY;
3698 }
3699
3700 /* Ensure that we have sane parameters */
3701 if (!write_data) write_len = 0;
3702 if (!read_data) read_len = 0;
3703 if (write_len > PVR2_CTL_BUFFSIZE) {
3704 pvr2_trace(
3705 PVR2_TRACE_ERROR_LEGS,
3706 "Attempted to execute %d byte"
3707 " control-write transfer (limit=%d)",
3708 write_len,PVR2_CTL_BUFFSIZE);
3709 return -EINVAL;
3710 }
3711 if (read_len > PVR2_CTL_BUFFSIZE) {
3712 pvr2_trace(
3713 PVR2_TRACE_ERROR_LEGS,
3714 "Attempted to execute %d byte"
3715 " control-read transfer (limit=%d)",
3716 write_len,PVR2_CTL_BUFFSIZE);
3717 return -EINVAL;
3718 }
3719 if ((!write_len) && (!read_len)) {
3720 pvr2_trace(
3721 PVR2_TRACE_ERROR_LEGS,
3722 "Attempted to execute null control transfer?");
3723 return -EINVAL;
3724 }
3725
3726
3727 hdw->cmd_debug_state = 1;
3728 if (write_len) {
3729 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3730 } else {
3731 hdw->cmd_debug_code = 0;
3732 }
3733 hdw->cmd_debug_write_len = write_len;
3734 hdw->cmd_debug_read_len = read_len;
3735
3736 /* Initialize common stuff */
3737 init_completion(&hdw->ctl_done);
3738 hdw->ctl_timeout_flag = 0;
3739 hdw->ctl_write_pend_flag = 0;
3740 hdw->ctl_read_pend_flag = 0;
3741 init_timer(&timer);
3742 timer.expires = jiffies + timeout;
3743 timer.data = (unsigned long)hdw;
3744 timer.function = pvr2_ctl_timeout;
3745
3746 if (write_len) {
3747 hdw->cmd_debug_state = 2;
3748 /* Transfer write data to internal buffer */
3749 for (idx = 0; idx < write_len; idx++) {
3750 hdw->ctl_write_buffer[idx] =
3751 ((unsigned char *)write_data)[idx];
3752 }
3753 /* Initiate a write request */
3754 usb_fill_bulk_urb(hdw->ctl_write_urb,
3755 hdw->usb_dev,
3756 usb_sndbulkpipe(hdw->usb_dev,
3757 PVR2_CTL_WRITE_ENDPOINT),
3758 hdw->ctl_write_buffer,
3759 write_len,
3760 pvr2_ctl_write_complete,
3761 hdw);
3762 hdw->ctl_write_urb->actual_length = 0;
3763 hdw->ctl_write_pend_flag = !0;
3764 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3765 if (status < 0) {
3766 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3767 "Failed to submit write-control"
3768 " URB status=%d",status);
3769 hdw->ctl_write_pend_flag = 0;
3770 goto done;
3771 }
3772 }
3773
3774 if (read_len) {
3775 hdw->cmd_debug_state = 3;
3776 memset(hdw->ctl_read_buffer,0x43,read_len);
3777 /* Initiate a read request */
3778 usb_fill_bulk_urb(hdw->ctl_read_urb,
3779 hdw->usb_dev,
3780 usb_rcvbulkpipe(hdw->usb_dev,
3781 PVR2_CTL_READ_ENDPOINT),
3782 hdw->ctl_read_buffer,
3783 read_len,
3784 pvr2_ctl_read_complete,
3785 hdw);
3786 hdw->ctl_read_urb->actual_length = 0;
3787 hdw->ctl_read_pend_flag = !0;
3788 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3789 if (status < 0) {
3790 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3791 "Failed to submit read-control"
3792 " URB status=%d",status);
3793 hdw->ctl_read_pend_flag = 0;
3794 goto done;
3795 }
3796 }
3797
3798 /* Start timer */
3799 add_timer(&timer);
3800
3801 /* Now wait for all I/O to complete */
3802 hdw->cmd_debug_state = 4;
3803 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3804 wait_for_completion(&hdw->ctl_done);
3805 }
3806 hdw->cmd_debug_state = 5;
3807
3808 /* Stop timer */
3809 del_timer_sync(&timer);
3810
3811 hdw->cmd_debug_state = 6;
3812 status = 0;
3813
3814 if (hdw->ctl_timeout_flag) {
3815 status = -ETIMEDOUT;
3816 if (!probe_fl) {
3817 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3818 "Timed out control-write");
3819 }
3820 goto done;
3821 }
3822
3823 if (write_len) {
3824 /* Validate results of write request */
3825 if ((hdw->ctl_write_urb->status != 0) &&
3826 (hdw->ctl_write_urb->status != -ENOENT) &&
3827 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3828 (hdw->ctl_write_urb->status != -ECONNRESET)) {
3829 /* USB subsystem is reporting some kind of failure
3830 on the write */
3831 status = hdw->ctl_write_urb->status;
3832 if (!probe_fl) {
3833 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3834 "control-write URB failure,"
3835 " status=%d",
3836 status);
3837 }
3838 goto done;
3839 }
3840 if (hdw->ctl_write_urb->actual_length < write_len) {
3841 /* Failed to write enough data */
3842 status = -EIO;
3843 if (!probe_fl) {
3844 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3845 "control-write URB short,"
3846 " expected=%d got=%d",
3847 write_len,
3848 hdw->ctl_write_urb->actual_length);
3849 }
3850 goto done;
3851 }
3852 }
3853 if (read_len) {
3854 /* Validate results of read request */
3855 if ((hdw->ctl_read_urb->status != 0) &&
3856 (hdw->ctl_read_urb->status != -ENOENT) &&
3857 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3858 (hdw->ctl_read_urb->status != -ECONNRESET)) {
3859 /* USB subsystem is reporting some kind of failure
3860 on the read */
3861 status = hdw->ctl_read_urb->status;
3862 if (!probe_fl) {
3863 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3864 "control-read URB failure,"
3865 " status=%d",
3866 status);
3867 }
3868 goto done;
3869 }
3870 if (hdw->ctl_read_urb->actual_length < read_len) {
3871 /* Failed to read enough data */
3872 status = -EIO;
3873 if (!probe_fl) {
3874 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3875 "control-read URB short,"
3876 " expected=%d got=%d",
3877 read_len,
3878 hdw->ctl_read_urb->actual_length);
3879 }
3880 goto done;
3881 }
3882 /* Transfer retrieved data out from internal buffer */
3883 for (idx = 0; idx < read_len; idx++) {
3884 ((unsigned char *)read_data)[idx] =
3885 hdw->ctl_read_buffer[idx];
3886 }
3887 }
3888
3889 done:
3890
3891 hdw->cmd_debug_state = 0;
3892 if ((status < 0) && (!probe_fl)) {
681c7399 3893 pvr2_hdw_render_useless(hdw);
d855497e
MI		 3894 }
3895 return status;
3896}
3897
3898
3899int pvr2_send_request(struct pvr2_hdw *hdw,
3900 void *write_data,unsigned int write_len,
3901 void *read_data,unsigned int read_len)
3902{
3903 return pvr2_send_request_ex(hdw,HZ*4,0,
3904 write_data,write_len,
3905 read_data,read_len);
3906}
3907
1c9d10d4
MI		 3908
3909static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3910{
3911 int ret;
3912 unsigned int cnt = 1;
3913 unsigned int args = 0;
3914 LOCK_TAKE(hdw->ctl_lock);
3915 hdw->cmd_buffer[0] = cmdcode & 0xffu;
3916 args = (cmdcode >> 8) & 0xffu;
3917 args = (args > 2) ? 2 : args;
3918 if (args) {
3919 cnt += args;
3920 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3921 if (args > 1) {
3922 hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3923 }
3924 }
3925 if (pvrusb2_debug & PVR2_TRACE_INIT) {
3926 unsigned int idx;
3927 unsigned int ccnt,bcnt;
3928 char tbuf[50];
3929 cmdcode &= 0xffu;
3930 bcnt = 0;
3931 ccnt = scnprintf(tbuf+bcnt,
3932 sizeof(tbuf)-bcnt,
3933 "Sending FX2 command 0x%x",cmdcode);
3934 bcnt += ccnt;
3935 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3936 if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3937 ccnt = scnprintf(tbuf+bcnt,
3938 sizeof(tbuf)-bcnt,
3939 " \"%s\"",
3940 pvr2_fx2cmd_desc[idx].desc);
3941 bcnt += ccnt;
3942 break;
3943 }
3944 }
3945 if (args) {
3946 ccnt = scnprintf(tbuf+bcnt,
3947 sizeof(tbuf)-bcnt,
3948 " (%u",hdw->cmd_buffer[1]);
3949 bcnt += ccnt;
3950 if (args > 1) {
3951 ccnt = scnprintf(tbuf+bcnt,
3952 sizeof(tbuf)-bcnt,
3953 ",%u",hdw->cmd_buffer[2]);
3954 bcnt += ccnt;
3955 }
3956 ccnt = scnprintf(tbuf+bcnt,
3957 sizeof(tbuf)-bcnt,
3958 ")");
3959 bcnt += ccnt;
3960 }
3961 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3962 }
3963 ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3964 LOCK_GIVE(hdw->ctl_lock);
3965 return ret;
3966}
3967
3968
d855497e
MI		 3969int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3970{
3971 int ret;
3972
3973 LOCK_TAKE(hdw->ctl_lock);
3974
8d364363 3975 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
d855497e
MI		 3976 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3977 hdw->cmd_buffer[5] = 0;
3978 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3979 hdw->cmd_buffer[7] = reg & 0xff;
3980
3981
3982 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3983
3984 LOCK_GIVE(hdw->ctl_lock);
3985
3986 return ret;
3987}
3988
3989
07e337ee 3990static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
d855497e
MI		 3991{
3992 int ret = 0;
3993
3994 LOCK_TAKE(hdw->ctl_lock);
3995
8d364363 3996 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
d855497e
MI		 3997 hdw->cmd_buffer[1] = 0;
3998 hdw->cmd_buffer[2] = 0;
3999 hdw->cmd_buffer[3] = 0;
4000 hdw->cmd_buffer[4] = 0;
4001 hdw->cmd_buffer[5] = 0;
4002 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4003 hdw->cmd_buffer[7] = reg & 0xff;
4004
4005 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
4006 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
4007
4008 LOCK_GIVE(hdw->ctl_lock);
4009
4010 return ret;
4011}
4012
4013
681c7399 4014void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
d855497e
MI		 4015{
4016 if (!hdw->flag_ok) return;
681c7399
MI		 4017 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4018 "Device being rendered inoperable");
d855497e 4019 if (hdw->vid_stream) {
a0fd1cb1 4020 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
d855497e 4021 }
681c7399
MI		 4022 hdw->flag_ok = 0;
4023 trace_stbit("flag_ok",hdw->flag_ok);
4024 pvr2_hdw_state_sched(hdw);
d855497e
MI		 4025}
4026
4027
4028void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
4029{
4030 int ret;
4031 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
a0fd1cb1 4032 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
011b15df 4033 if (ret == 0) {
d855497e
MI		 4034 ret = usb_reset_device(hdw->usb_dev);
4035 usb_unlock_device(hdw->usb_dev);
4036 } else {
4037 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4038 "Failed to lock USB device ret=%d",ret);
4039 }
4040 if (init_pause_msec) {
4041 pvr2_trace(PVR2_TRACE_INFO,
4042 "Waiting %u msec for hardware to settle",
4043 init_pause_msec);
4044 msleep(init_pause_msec);
4045 }
4046
4047}
4048
4049
4050void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
4051{
4052 char da[1];
4053 unsigned int pipe;
4054 int ret;
4055
4056 if (!hdw->usb_dev) return;
4057
4058 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4059
4060 da[0] = val ? 0x01 : 0x00;
4061
4062 /* Write the CPUCS register on the 8051. The lsb of the register
4063 is the reset bit; a 1 asserts reset while a 0 clears it. */
4064 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4065 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4066 if (ret < 0) {
4067 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4068 "cpureset_assert(%d) error=%d",val,ret);
4069 pvr2_hdw_render_useless(hdw);
4070 }
4071}
4072
4073
4074int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4075{
1c9d10d4 4076 return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
d855497e
MI		 4077}
4078
4079
e1edb19a
MK		 4080int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4081{
1c9d10d4 4082 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
e1edb19a
MK		 4083}
4084
1c9d10d4 4085
e1edb19a
MK		 4086int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4087{
1c9d10d4 4088 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
e1edb19a
MK		 4089}
4090
d855497e
MI		 4091
4092int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4093{
af78e16b
MI		 4094 pvr2_trace(PVR2_TRACE_INIT,
4095 "Requesting decoder reset");
4096 if (hdw->decoder_ctrl) {
4097 if (!hdw->decoder_ctrl->force_reset) {
4098 pvr2_trace(PVR2_TRACE_INIT,
4099 "Unable to reset decoder: not implemented");
4100 return -ENOTTY;
4101 }
4102 hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
4103 return 0;
4104 } else {
d855497e 4105 }
af78e16b
MI		 4106 if (hdw->decoder_client_id) {
4107 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4108 core, reset, 0);
4109 return 0;
d855497e 4110 }
d855497e 4111 pvr2_trace(PVR2_TRACE_INIT,
af78e16b
MI		 4112 "Unable to reset decoder: nothing attached");
4113 return -ENOTTY;
d855497e
MI		 4114}
4115
4116
62433e31 4117static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
84147f3d 4118{
1c9d10d4
MI		 4119 hdw->flag_ok = !0;
4120 return pvr2_issue_simple_cmd(hdw,
4121 FX2CMD_HCW_DEMOD_RESETIN |
4122 (1 << 8) |
4123 ((onoff ? 1 : 0) << 16));
84147f3d
MI		 4124}
4125
84147f3d 4126
62433e31 4127static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
84147f3d 4128{
1c9d10d4
MI		 4129 hdw->flag_ok = !0;
4130 return pvr2_issue_simple_cmd(hdw,(onoff ?
4131 FX2CMD_ONAIR_DTV_POWER_ON :
4132 FX2CMD_ONAIR_DTV_POWER_OFF));
84147f3d
MI		 4133}
4134
62433e31
MI		 4135
4136static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4137 int onoff)
84147f3d 4138{
1c9d10d4
MI		 4139 return pvr2_issue_simple_cmd(hdw,(onoff ?
4140 FX2CMD_ONAIR_DTV_STREAMING_ON :
4141 FX2CMD_ONAIR_DTV_STREAMING_OFF));
84147f3d
MI		 4142}
4143
62433e31
MI		 4144
4145static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4146{
4147 int cmode;
4148 /* Compare digital/analog desired setting with current setting. If
4149 they don't match, fix it... */
4150 cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4151 if (cmode == hdw->pathway_state) {
4152 /* They match; nothing to do */
4153 return;
4154 }
4155
4156 switch (hdw->hdw_desc->digital_control_scheme) {
4157 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4158 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4159 if (cmode == PVR2_PATHWAY_ANALOG) {
4160 /* If moving to analog mode, also force the decoder
4161 to reset. If no decoder is attached, then it's
4162 ok to ignore this because if/when the decoder
4163 attaches, it will reset itself at that time. */
4164 pvr2_hdw_cmd_decoder_reset(hdw);
4165 }
4166 break;
4167 case PVR2_DIGITAL_SCHEME_ONAIR:
4168 /* Supposedly we should always have the power on whether in
4169 digital or analog mode. But for now do what appears to
4170 work... */
bb0c2fe0 4171 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
62433e31
MI		 4172 break;
4173 default: break;
4174 }
4175
1b9c18c5 4176 pvr2_hdw_untrip_unlocked(hdw);
62433e31
MI		 4177 hdw->pathway_state = cmode;
4178}
4179
4180
e9b59f6e 4181static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
c55a97d7
MI		 4182{
4183 /* change some GPIO data
4184 *
4185 * note: bit d7 of dir appears to control the LED,
4186 * so we shut it off here.
4187 *
c55a97d7 4188 */
40381cb0 4189 if (onoff) {
c55a97d7 4190 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
40381cb0 4191 } else {
c55a97d7 4192 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
40381cb0 4193 }
c55a97d7 4194 pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
40381cb0 4195}
c55a97d7 4196
40381cb0
MI		 4197
4198typedef void (*led_method_func)(struct pvr2_hdw *,int);
4199
4200static led_method_func led_methods[] = {
4201 [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4202};
4203
4204
4205/* Toggle LED */
4206static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4207{
4208 unsigned int scheme_id;
4209 led_method_func fp;
4210
4211 if ((!onoff) == (!hdw->led_on)) return;
4212
4213 hdw->led_on = onoff != 0;
4214
4215 scheme_id = hdw->hdw_desc->led_scheme;
4216 if (scheme_id < ARRAY_SIZE(led_methods)) {
4217 fp = led_methods[scheme_id];
4218 } else {
4219 fp = NULL;
4220 }
4221
4222 if (fp) (*fp)(hdw,onoff);
c55a97d7
MI		 4223}
4224
4225
e61b6fc5 4226/* Stop / start video stream transport */
07e337ee 4227static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
d855497e 4228{
bb0c2fe0
MI		 4229 int ret;
4230
4231 /* If we're in analog mode, then just issue the usual analog
4232 command. */
4233 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4234 return pvr2_issue_simple_cmd(hdw,
4235 (runFl ?
4236 FX2CMD_STREAMING_ON :
4237 FX2CMD_STREAMING_OFF));
4238 /*Note: Not reached */
4239 }
4240
4241 if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4242 /* Whoops, we don't know what mode we're in... */
4243 return -EINVAL;
4244 }
4245
4246 /* To get here we have to be in digital mode. The mechanism here
4247 is unfortunately different for different vendors. So we switch
4248 on the device's digital scheme attribute in order to figure out
4249 what to do. */
4250 switch (hdw->hdw_desc->digital_control_scheme) {
4251 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4252 return pvr2_issue_simple_cmd(hdw,
4253 (runFl ?
4254 FX2CMD_HCW_DTV_STREAMING_ON :
4255 FX2CMD_HCW_DTV_STREAMING_OFF));
4256 case PVR2_DIGITAL_SCHEME_ONAIR:
4257 ret = pvr2_issue_simple_cmd(hdw,
4258 (runFl ?
4259 FX2CMD_STREAMING_ON :
4260 FX2CMD_STREAMING_OFF));
4261 if (ret) return ret;
4262 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4263 default:
4264 return -EINVAL;
62433e31 4265 }
d855497e
MI		 4266}
4267
4268
62433e31
MI		 4269/* Evaluate whether or not state_pathway_ok can change */
4270static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4271{
4272 if (hdw->state_pathway_ok) {
4273 /* Nothing to do if pathway is already ok */
4274 return 0;
4275 }
4276 if (!hdw->state_pipeline_idle) {
4277 /* Not allowed to change anything if pipeline is not idle */
4278 return 0;
4279 }
4280 pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4281 hdw->state_pathway_ok = !0;
e9db1ff2 4282 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 4283 return !0;
4284}
4285
4286
681c7399
MI		 4287/* Evaluate whether or not state_encoder_ok can change */
4288static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4289{
4290 if (hdw->state_encoder_ok) return 0;
4291 if (hdw->flag_tripped) return 0;
4292 if (hdw->state_encoder_run) return 0;
4293 if (hdw->state_encoder_config) return 0;
4294 if (hdw->state_decoder_run) return 0;
4295 if (hdw->state_usbstream_run) return 0;
72998b71
MI		 4296 if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4297 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4298 } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4299 return 0;
4300 }
4301
681c7399
MI		 4302 if (pvr2_upload_firmware2(hdw) < 0) {
4303 hdw->flag_tripped = !0;
4304 trace_stbit("flag_tripped",hdw->flag_tripped);
4305 return !0;
4306 }
4307 hdw->state_encoder_ok = !0;
4308 trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4309 return !0;
4310}
4311
4312
4313/* Evaluate whether or not state_encoder_config can change */
4314static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4315{
4316 if (hdw->state_encoder_config) {
4317 if (hdw->state_encoder_ok) {
4318 if (hdw->state_pipeline_req &&
4319 !hdw->state_pipeline_pause) return 0;
4320 }
4321 hdw->state_encoder_config = 0;
4322 hdw->state_encoder_waitok = 0;
4323 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4324 /* paranoia - solve race if timer just completed */
4325 del_timer_sync(&hdw->encoder_wait_timer);
4326 } else {
62433e31
MI		 4327 if (!hdw->state_pathway_ok ||
4328 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4329 !hdw->state_encoder_ok ||
681c7399
MI		 4330 !hdw->state_pipeline_idle ||
4331 hdw->state_pipeline_pause ||
4332 !hdw->state_pipeline_req ||
4333 !hdw->state_pipeline_config) {
4334 /* We must reset the enforced wait interval if
4335 anything has happened that might have disturbed
4336 the encoder. This should be a rare case. */
4337 if (timer_pending(&hdw->encoder_wait_timer)) {
4338 del_timer_sync(&hdw->encoder_wait_timer);
4339 }
4340 if (hdw->state_encoder_waitok) {
4341 /* Must clear the state - therefore we did
4342 something to a state bit and must also
4343 return true. */
4344 hdw->state_encoder_waitok = 0;
4345 trace_stbit("state_encoder_waitok",
4346 hdw->state_encoder_waitok);
4347 return !0;
4348 }
4349 return 0;
4350 }
4351 if (!hdw->state_encoder_waitok) {
4352 if (!timer_pending(&hdw->encoder_wait_timer)) {
4353 /* waitok flag wasn't set and timer isn't
4354 running. Check flag once more to avoid
4355 a race then start the timer. This is
4356 the point when we measure out a minimal
4357 quiet interval before doing something to
4358 the encoder. */
4359 if (!hdw->state_encoder_waitok) {
4360 hdw->encoder_wait_timer.expires =
83ce57aa
MI		 4361 jiffies +
4362 (HZ * TIME_MSEC_ENCODER_WAIT
4363 / 1000);
681c7399
MI		 4364 add_timer(&hdw->encoder_wait_timer);
4365 }
4366 }
4367 /* We can't continue until we know we have been
4368 quiet for the interval measured by this
4369 timer. */
4370 return 0;
4371 }
4372 pvr2_encoder_configure(hdw);
4373 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4374 }
4375 trace_stbit("state_encoder_config",hdw->state_encoder_config);
4376 return !0;
4377}
4378
4379
d913d630
MI		 4380/* Return true if the encoder should not be running. */
4381static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4382{
4383 if (!hdw->state_encoder_ok) {
4384 /* Encoder isn't healthy at the moment, so stop it. */
4385 return !0;
4386 }
4387 if (!hdw->state_pathway_ok) {
4388 /* Mode is not understood at the moment (i.e. it wants to
4389 change), so encoder must be stopped. */
4390 return !0;
4391 }
4392
4393 switch (hdw->pathway_state) {
4394 case PVR2_PATHWAY_ANALOG:
4395 if (!hdw->state_decoder_run) {
4396 /* We're in analog mode and the decoder is not
4397 running; thus the encoder should be stopped as
4398 well. */
4399 return !0;
4400 }
4401 break;
4402 case PVR2_PATHWAY_DIGITAL:
4403 if (hdw->state_encoder_runok) {
4404 /* This is a funny case. We're in digital mode so
4405 really the encoder should be stopped. However
4406 if it really is running, only kill it after
4407 runok has been set. This gives a chance for the
4408 onair quirk to function (encoder must run
4409 briefly first, at least once, before onair
4410 digital streaming can work). */
4411 return !0;
4412 }
4413 break;
4414 default:
4415 /* Unknown mode; so encoder should be stopped. */
4416 return !0;
4417 }
4418
4419 /* If we get here, we haven't found a reason to stop the
4420 encoder. */
4421 return 0;
4422}
4423
4424
4425/* Return true if the encoder should be running. */
4426static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4427{
4428 if (!hdw->state_encoder_ok) {
4429 /* Don't run the encoder if it isn't healthy... */
4430 return 0;
4431 }
4432 if (!hdw->state_pathway_ok) {
4433 /* Don't run the encoder if we don't (yet) know what mode
4434 we need to be in... */
4435 return 0;
4436 }
4437
4438 switch (hdw->pathway_state) {
4439 case PVR2_PATHWAY_ANALOG:
4440 if (hdw->state_decoder_run) {
4441 /* In analog mode, if the decoder is running, then
4442 run the encoder. */
4443 return !0;
4444 }
4445 break;
4446 case PVR2_PATHWAY_DIGITAL:
4447 if ((hdw->hdw_desc->digital_control_scheme ==
4448 PVR2_DIGITAL_SCHEME_ONAIR) &&
4449 !hdw->state_encoder_runok) {
4450 /* This is a quirk. OnAir hardware won't stream
4451 digital until the encoder has been run at least
4452 once, for a minimal period of time (empiricially
4453 measured to be 1/4 second). So if we're on
4454 OnAir hardware and the encoder has never been
4455 run at all, then start the encoder. Normal
4456 state machine logic in the driver will
4457 automatically handle the remaining bits. */
4458 return !0;
4459 }
4460 break;
4461 default:
4462 /* For completeness (unknown mode; encoder won't run ever) */
4463 break;
4464 }
4465 /* If we get here, then we haven't found any reason to run the
4466 encoder, so don't run it. */
4467 return 0;
4468}
4469
4470
681c7399
MI		 4471/* Evaluate whether or not state_encoder_run can change */
4472static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4473{
4474 if (hdw->state_encoder_run) {
d913d630 4475 if (!state_check_disable_encoder_run(hdw)) return 0;
681c7399 4476 if (hdw->state_encoder_ok) {
d913d630 4477 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 4478 if (pvr2_encoder_stop(hdw) < 0) return !0;
4479 }
4480 hdw->state_encoder_run = 0;
4481 } else {
d913d630 4482 if (!state_check_enable_encoder_run(hdw)) return 0;
681c7399
MI		 4483 if (pvr2_encoder_start(hdw) < 0) return !0;
4484 hdw->state_encoder_run = !0;
d913d630
MI		 4485 if (!hdw->state_encoder_runok) {
4486 hdw->encoder_run_timer.expires =
83ce57aa 4487 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
d913d630
MI		 4488 add_timer(&hdw->encoder_run_timer);
4489 }
681c7399
MI		 4490 }
4491 trace_stbit("state_encoder_run",hdw->state_encoder_run);
4492 return !0;
4493}
4494
4495
4496/* Timeout function for quiescent timer. */
4497static void pvr2_hdw_quiescent_timeout(unsigned long data)
4498{
4499 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4500 hdw->state_decoder_quiescent = !0;
4501 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4502 hdw->state_stale = !0;
4503 queue_work(hdw->workqueue,&hdw->workpoll);
4504}
4505
4506
4507/* Timeout function for encoder wait timer. */
4508static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4509{
4510 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4511 hdw->state_encoder_waitok = !0;
4512 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4513 hdw->state_stale = !0;
4514 queue_work(hdw->workqueue,&hdw->workpoll);
4515}
4516
4517
d913d630
MI		 4518/* Timeout function for encoder run timer. */
4519static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4520{
4521 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4522 if (!hdw->state_encoder_runok) {
4523 hdw->state_encoder_runok = !0;
4524 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4525 hdw->state_stale = !0;
4526 queue_work(hdw->workqueue,&hdw->workpoll);
4527 }
4528}
4529
4530
681c7399
MI		 4531/* Evaluate whether or not state_decoder_run can change */
4532static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4533{
4534 if (hdw->state_decoder_run) {
4535 if (hdw->state_encoder_ok) {
4536 if (hdw->state_pipeline_req &&
62433e31
MI		 4537 !hdw->state_pipeline_pause &&
4538 hdw->state_pathway_ok) return 0;
681c7399
MI		 4539 }
4540 if (!hdw->flag_decoder_missed) {
4541 pvr2_decoder_enable(hdw,0);
4542 }
4543 hdw->state_decoder_quiescent = 0;
4544 hdw->state_decoder_run = 0;
4545 /* paranoia - solve race if timer just completed */
4546 del_timer_sync(&hdw->quiescent_timer);
4547 } else {
4548 if (!hdw->state_decoder_quiescent) {
4549 if (!timer_pending(&hdw->quiescent_timer)) {
4550 /* We don't do something about the
4551 quiescent timer until right here because
4552 we also want to catch cases where the
4553 decoder was already not running (like
4554 after initialization) as opposed to
4555 knowing that we had just stopped it.
4556 The second flag check is here to cover a
4557 race - the timer could have run and set
4558 this flag just after the previous check
4559 but before we did the pending check. */
4560 if (!hdw->state_decoder_quiescent) {
4561 hdw->quiescent_timer.expires =
83ce57aa
MI		 4562 jiffies +
4563 (HZ * TIME_MSEC_DECODER_WAIT
4564 / 1000);
681c7399
MI		 4565 add_timer(&hdw->quiescent_timer);
4566 }
4567 }
4568 /* Don't allow decoder to start again until it has
4569 been quiesced first. This little detail should
4570 hopefully further stabilize the encoder. */
4571 return 0;
4572 }
62433e31
MI		 4573 if (!hdw->state_pathway_ok ||
4574 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4575 !hdw->state_pipeline_req ||
681c7399
MI		 4576 hdw->state_pipeline_pause ||
4577 !hdw->state_pipeline_config ||
4578 !hdw->state_encoder_config ||
4579 !hdw->state_encoder_ok) return 0;
4580 del_timer_sync(&hdw->quiescent_timer);
4581 if (hdw->flag_decoder_missed) return 0;
4582 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4583 hdw->state_decoder_quiescent = 0;
4584 hdw->state_decoder_run = !0;
4585 }
4586 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4587 trace_stbit("state_decoder_run",hdw->state_decoder_run);
4588 return !0;
4589}
4590
4591
4592/* Evaluate whether or not state_usbstream_run can change */
4593static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4594{
4595 if (hdw->state_usbstream_run) {
72998b71 4596 int fl = !0;
62433e31 4597 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
72998b71
MI		 4598 fl = (hdw->state_encoder_ok &&
4599 hdw->state_encoder_run);
4600 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4601 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4602 fl = hdw->state_encoder_ok;
4603 }
4604 if (fl &&
4605 hdw->state_pipeline_req &&
4606 !hdw->state_pipeline_pause &&
4607 hdw->state_pathway_ok) {
4608 return 0;
681c7399
MI		 4609 }
4610 pvr2_hdw_cmd_usbstream(hdw,0);
4611 hdw->state_usbstream_run = 0;
4612 } else {
62433e31
MI		 4613 if (!hdw->state_pipeline_req ||
4614 hdw->state_pipeline_pause ||
4615 !hdw->state_pathway_ok) return 0;
4616 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4617 if (!hdw->state_encoder_ok ||
4618 !hdw->state_encoder_run) return 0;
72998b71
MI		 4619 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4620 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4621 if (!hdw->state_encoder_ok) return 0;
d913d630
MI		 4622 if (hdw->state_encoder_run) return 0;
4623 if (hdw->hdw_desc->digital_control_scheme ==
4624 PVR2_DIGITAL_SCHEME_ONAIR) {
4625 /* OnAir digital receivers won't stream
4626 unless the analog encoder has run first.
4627 Why? I have no idea. But don't even
4628 try until we know the analog side is
4629 known to have run. */
4630 if (!hdw->state_encoder_runok) return 0;
4631 }
62433e31 4632 }
681c7399
MI		 4633 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4634 hdw->state_usbstream_run = !0;
4635 }
4636 trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4637 return !0;
4638}
4639
4640
4641/* Attempt to configure pipeline, if needed */
4642static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4643{
4644 if (hdw->state_pipeline_config ||
4645 hdw->state_pipeline_pause) return 0;
4646 pvr2_hdw_commit_execute(hdw);
4647 return !0;
4648}
4649
4650
4651/* Update pipeline idle and pipeline pause tracking states based on other
4652 inputs. This must be called whenever the other relevant inputs have
4653 changed. */
4654static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4655{
4656 unsigned int st;
4657 int updatedFl = 0;
4658 /* Update pipeline state */
4659 st = !(hdw->state_encoder_run ||
4660 hdw->state_decoder_run ||
4661 hdw->state_usbstream_run ||
4662 (!hdw->state_decoder_quiescent));
4663 if (!st != !hdw->state_pipeline_idle) {
4664 hdw->state_pipeline_idle = st;
4665 updatedFl = !0;
4666 }
4667 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4668 hdw->state_pipeline_pause = 0;
4669 updatedFl = !0;
4670 }
4671 return updatedFl;
4672}
4673
4674
4675typedef int (*state_eval_func)(struct pvr2_hdw *);
4676
4677/* Set of functions to be run to evaluate various states in the driver. */
ebff0330 4678static const state_eval_func eval_funcs[] = {
62433e31 4679 state_eval_pathway_ok,
681c7399
MI		 4680 state_eval_pipeline_config,
4681 state_eval_encoder_ok,
4682 state_eval_encoder_config,
4683 state_eval_decoder_run,
4684 state_eval_encoder_run,
4685 state_eval_usbstream_run,
4686};
4687
4688
4689/* Process various states and return true if we did anything interesting. */
4690static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4691{
4692 unsigned int i;
4693 int state_updated = 0;
4694 int check_flag;
4695
4696 if (!hdw->state_stale) return 0;
4697 if ((hdw->fw1_state != FW1_STATE_OK) ||
4698 !hdw->flag_ok) {
4699 hdw->state_stale = 0;
4700 return !0;
4701 }
4702 /* This loop is the heart of the entire driver. It keeps trying to
4703 evaluate various bits of driver state until nothing changes for
4704 one full iteration. Each "bit of state" tracks some global
4705 aspect of the driver, e.g. whether decoder should run, if
4706 pipeline is configured, usb streaming is on, etc. We separately
4707 evaluate each of those questions based on other driver state to
4708 arrive at the correct running configuration. */
4709 do {
4710 check_flag = 0;
4711 state_update_pipeline_state(hdw);
4712 /* Iterate over each bit of state */
4713 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4714 if ((*eval_funcs[i])(hdw)) {
4715 check_flag = !0;
4716 state_updated = !0;
4717 state_update_pipeline_state(hdw);
4718 }
4719 }
4720 } while (check_flag && hdw->flag_ok);
4721 hdw->state_stale = 0;
4722 trace_stbit("state_stale",hdw->state_stale);
4723 return state_updated;
4724}
4725
4726
1cb03b76
MI		 4727static unsigned int print_input_mask(unsigned int msk,
4728 char *buf,unsigned int acnt)
4729{
4730 unsigned int idx,ccnt;
4731 unsigned int tcnt = 0;
4732 for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4733 if (!((1 << idx) & msk)) continue;
4734 ccnt = scnprintf(buf+tcnt,
4735 acnt-tcnt,
4736 "%s%s",
4737 (tcnt ? ", " : ""),
4738 control_values_input[idx]);
4739 tcnt += ccnt;
4740 }
4741 return tcnt;
4742}
4743
4744
62433e31
MI		 4745static const char *pvr2_pathway_state_name(int id)
4746{
4747 switch (id) {
4748 case PVR2_PATHWAY_ANALOG: return "analog";
4749 case PVR2_PATHWAY_DIGITAL: return "digital";
4750 default: return "unknown";
4751 }
4752}
4753
4754
681c7399
MI		 4755static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4756 char *buf,unsigned int acnt)
4757{
4758 switch (which) {
4759 case 0:
4760 return scnprintf(
4761 buf,acnt,
e9db1ff2 4762 "driver:%s%s%s%s%s <mode=%s>",
681c7399
MI		 4763 (hdw->flag_ok ? " <ok>" : " <fail>"),
4764 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4765 (hdw->flag_disconnected ? " <disconnected>" :
4766 " <connected>"),
4767 (hdw->flag_tripped ? " <tripped>" : ""),
62433e31
MI		 4768 (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4769 pvr2_pathway_state_name(hdw->pathway_state));
4770
681c7399
MI		 4771 case 1:
4772 return scnprintf(
4773 buf,acnt,
4774 "pipeline:%s%s%s%s",
4775 (hdw->state_pipeline_idle ? " <idle>" : ""),
4776 (hdw->state_pipeline_config ?
4777 " <configok>" : " <stale>"),
4778 (hdw->state_pipeline_req ? " <req>" : ""),
4779 (hdw->state_pipeline_pause ? " <pause>" : ""));
4780 case 2:
4781 return scnprintf(
4782 buf,acnt,
62433e31 4783 "worker:%s%s%s%s%s%s%s",
681c7399
MI		 4784 (hdw->state_decoder_run ?
4785 " <decode:run>" :
4786 (hdw->state_decoder_quiescent ?
4787 "" : " <decode:stop>")),
4788 (hdw->state_decoder_quiescent ?
4789 " <decode:quiescent>" : ""),
4790 (hdw->state_encoder_ok ?
4791 "" : " <encode:init>"),
4792 (hdw->state_encoder_run ?
d913d630
MI		 4793 (hdw->state_encoder_runok ?
4794 " <encode:run>" :
4795 " <encode:firstrun>") :
4796 (hdw->state_encoder_runok ?
4797 " <encode:stop>" :
4798 " <encode:virgin>")),
681c7399
MI		 4799 (hdw->state_encoder_config ?
4800 " <encode:configok>" :
4801 (hdw->state_encoder_waitok ?
b9a37d91 4802 "" : " <encode:waitok>")),
681c7399 4803 (hdw->state_usbstream_run ?
62433e31
MI		 4804 " <usb:run>" : " <usb:stop>"),
4805 (hdw->state_pathway_ok ?
e9db1ff2 4806 " <pathway:ok>" : ""));
681c7399
MI		 4807 case 3:
4808 return scnprintf(
4809 buf,acnt,
4810 "state: %s",
4811 pvr2_get_state_name(hdw->master_state));
ad0992e9 4812 case 4: {
1cb03b76
MI		 4813 unsigned int tcnt = 0;
4814 unsigned int ccnt;
4815
4816 ccnt = scnprintf(buf,
4817 acnt,
4818 "Hardware supported inputs: ");
4819 tcnt += ccnt;
4820 tcnt += print_input_mask(hdw->input_avail_mask,
4821 buf+tcnt,
4822 acnt-tcnt);
4823 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4824 ccnt = scnprintf(buf+tcnt,
4825 acnt-tcnt,
4826 "; allowed inputs: ");
4827 tcnt += ccnt;
4828 tcnt += print_input_mask(hdw->input_allowed_mask,
4829 buf+tcnt,
4830 acnt-tcnt);
4831 }
4832 return tcnt;
4833 }
4834 case 5: {
ad0992e9
MI		 4835 struct pvr2_stream_stats stats;
4836 if (!hdw->vid_stream) break;
4837 pvr2_stream_get_stats(hdw->vid_stream,
4838 &stats,
4839 0);
4840 return scnprintf(
4841 buf,acnt,
4842 "Bytes streamed=%u"
4843 " URBs: queued=%u idle=%u ready=%u"
4844 " processed=%u failed=%u",
4845 stats.bytes_processed,
4846 stats.buffers_in_queue,
4847 stats.buffers_in_idle,
4848 stats.buffers_in_ready,
4849 stats.buffers_processed,
4850 stats.buffers_failed);
4851 }
858f910e
MI		 4852 case 6: {
4853 struct v4l2_subdev *sd;
4854 unsigned int tcnt = 0;
4855 unsigned int ccnt;
4856 const char *p;
4857 unsigned int id;
4858 ccnt = scnprintf(buf,
4859 acnt,
5f757ddd 4860 "Associated v4l2_subdev drivers:");
858f910e
MI		 4861 tcnt += ccnt;
4862 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4863 id = sd->grp_id;
4864 p = NULL;
4865 if (id < ARRAY_SIZE(module_names)) {
4866 p = module_names[id];
4867 }
5f757ddd
MI		 4868 if (p) {
4869 ccnt = scnprintf(buf + tcnt,
4870 acnt - tcnt,
4871 " %s", p);
4872 } else {
4873 ccnt = scnprintf(buf + tcnt,
4874 acnt - tcnt,
4875 " (unknown id=%u)", id);
4876 }
4877 tcnt += ccnt;
858f910e
MI		 4878 }
4879 return tcnt;
4880 }
681c7399
MI		 4881 default: break;
4882 }
4883 return 0;
4884}
4885
4886
4887unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4888 char *buf,unsigned int acnt)
4889{
4890 unsigned int bcnt,ccnt,idx;
4891 bcnt = 0;
4892 LOCK_TAKE(hdw->big_lock);
4893 for (idx = 0; ; idx++) {
4894 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4895 if (!ccnt) break;
4896 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4897 if (!acnt) break;
4898 buf[0] = '\n'; ccnt = 1;
4899 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4900 }
4901 LOCK_GIVE(hdw->big_lock);
4902 return bcnt;
4903}
4904
4905
4906static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4907{
4908 char buf[128];
4909 unsigned int idx,ccnt;
4910
4911 for (idx = 0; ; idx++) {
4912 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4913 if (!ccnt) break;
4914 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4915 }
4916}
4917
4918
4919/* Evaluate and update the driver's current state, taking various actions
4920 as appropriate for the update. */
4921static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4922{
4923 unsigned int st;
4924 int state_updated = 0;
4925 int callback_flag = 0;
1b9c18c5 4926 int analog_mode;
681c7399
MI		 4927
4928 pvr2_trace(PVR2_TRACE_STBITS,
4929 "Drive state check START");
4930 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4931 pvr2_hdw_state_log_state(hdw);
4932 }
4933
4934 /* Process all state and get back over disposition */
4935 state_updated = pvr2_hdw_state_update(hdw);
4936
1b9c18c5
MI		 4937 analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4938
681c7399
MI		 4939 /* Update master state based upon all other states. */
4940 if (!hdw->flag_ok) {
4941 st = PVR2_STATE_DEAD;
4942 } else if (hdw->fw1_state != FW1_STATE_OK) {
4943 st = PVR2_STATE_COLD;
72998b71
MI		 4944 } else if ((analog_mode ||
4945 hdw->hdw_desc->flag_digital_requires_cx23416) &&
4946 !hdw->state_encoder_ok) {
681c7399 4947 st = PVR2_STATE_WARM;
1b9c18c5
MI		 4948 } else if (hdw->flag_tripped ||
4949 (analog_mode && hdw->flag_decoder_missed)) {
681c7399 4950 st = PVR2_STATE_ERROR;
62433e31 4951 } else if (hdw->state_usbstream_run &&
1b9c18c5 4952 (!analog_mode ||
62433e31 4953 (hdw->state_encoder_run && hdw->state_decoder_run))) {
681c7399
MI		 4954 st = PVR2_STATE_RUN;
4955 } else {
4956 st = PVR2_STATE_READY;
4957 }
4958 if (hdw->master_state != st) {
4959 pvr2_trace(PVR2_TRACE_STATE,
4960 "Device state change from %s to %s",
4961 pvr2_get_state_name(hdw->master_state),
4962 pvr2_get_state_name(st));
40381cb0 4963 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
681c7399
MI		 4964 hdw->master_state = st;
4965 state_updated = !0;
4966 callback_flag = !0;
4967 }
4968 if (state_updated) {
4969 /* Trigger anyone waiting on any state changes here. */
4970 wake_up(&hdw->state_wait_data);
4971 }
4972
4973 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4974 pvr2_hdw_state_log_state(hdw);
4975 }
4976 pvr2_trace(PVR2_TRACE_STBITS,
4977 "Drive state check DONE callback=%d",callback_flag);
4978
4979 return callback_flag;
4980}
4981
4982
4983/* Cause kernel thread to check / update driver state */
4984static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4985{
4986 if (hdw->state_stale) return;
4987 hdw->state_stale = !0;
4988 trace_stbit("state_stale",hdw->state_stale);
4989 queue_work(hdw->workqueue,&hdw->workpoll);
4990}
4991
4992
d855497e
MI		 4993int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4994{
4995 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
4996}
4997
4998
4999int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
5000{
5001 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
5002}
5003
5004
5005int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
5006{
5007 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
5008}
5009
5010
5011int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
5012{
5013 u32 cval,nval;
5014 int ret;
5015 if (~msk) {
5016 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
5017 if (ret) return ret;
5018 nval = (cval & ~msk) | (val & msk);
5019 pvr2_trace(PVR2_TRACE_GPIO,
5020 "GPIO direction changing 0x%x:0x%x"
5021 " from 0x%x to 0x%x",
5022 msk,val,cval,nval);
5023 } else {
5024 nval = val;
5025 pvr2_trace(PVR2_TRACE_GPIO,
5026 "GPIO direction changing to 0x%x",nval);
5027 }
5028 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5029}
5030
5031
5032int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5033{
5034 u32 cval,nval;
5035 int ret;
5036 if (~msk) {
5037 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5038 if (ret) return ret;
5039 nval = (cval & ~msk) | (val & msk);
5040 pvr2_trace(PVR2_TRACE_GPIO,
5041 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5042 msk,val,cval,nval);
5043 } else {
5044 nval = val;
5045 pvr2_trace(PVR2_TRACE_GPIO,
5046 "GPIO output changing to 0x%x",nval);
5047 }
5048 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5049}
5050
5051
a51f5000
MI		 5052void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5053{
40f07111
MI		 5054 struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5055 memset(vtp, 0, sizeof(*vtp));
2641df36 5056 hdw->tuner_signal_stale = 0;
a51f5000 5057 pvr2_i2c_core_status_poll(hdw);
40f07111
MI		 5058 /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5059 using v4l2-subdev - therefore we can't support that AT ALL right
5060 now. (Of course, no sub-drivers seem to implement it either.
5061 But now it's a a chicken and egg problem...) */
5062 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner,
5063 &hdw->tuner_signal_info);
2641df36 5064 pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
40f07111
MI		 5065 " type=%u strength=%u audio=0x%x cap=0x%x"
5066 " low=%u hi=%u",
5067 vtp->type,
5068 vtp->signal, vtp->rxsubchans, vtp->capability,
5069 vtp->rangelow, vtp->rangehigh);
2641df36
MI		 5070
5071 /* We have to do this to avoid getting into constant polling if
5072 there's nobody to answer a poll of cropcap info. */
5073 hdw->cropcap_stale = 0;
a51f5000
MI		 5074}
5075
5076
7fb20fa3
MI		 5077unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5078{
5079 return hdw->input_avail_mask;
5080}
5081
5082
1cb03b76
MI		 5083unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5084{
5085 return hdw->input_allowed_mask;
5086}
5087
5088
5089static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5090{
5091 if (hdw->input_val != v) {
5092 hdw->input_val = v;
5093 hdw->input_dirty = !0;
5094 }
5095
5096 /* Handle side effects - if we switch to a mode that needs the RF
5097 tuner, then select the right frequency choice as well and mark
5098 it dirty. */
5099 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5100 hdw->freqSelector = 0;
5101 hdw->freqDirty = !0;
5102 } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5103 (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5104 hdw->freqSelector = 1;
5105 hdw->freqDirty = !0;
5106 }
5107 return 0;
5108}
5109
5110
5111int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5112 unsigned int change_mask,
5113 unsigned int change_val)
5114{
5115 int ret = 0;
5116 unsigned int nv,m,idx;
5117 LOCK_TAKE(hdw->big_lock);
5118 do {
5119 nv = hdw->input_allowed_mask & ~change_mask;
5120 nv |= (change_val & change_mask);
5121 nv &= hdw->input_avail_mask;
5122 if (!nv) {
5123 /* No legal modes left; return error instead. */
5124 ret = -EPERM;
5125 break;
5126 }
5127 hdw->input_allowed_mask = nv;
5128 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5129 /* Current mode is still in the allowed mask, so
5130 we're done. */
5131 break;
5132 }
5133 /* Select and switch to a mode that is still in the allowed
5134 mask */
5135 if (!hdw->input_allowed_mask) {
5136 /* Nothing legal; give up */
5137 break;
5138 }
5139 m = hdw->input_allowed_mask;
5140 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5141 if (!((1 << idx) & m)) continue;
5142 pvr2_hdw_set_input(hdw,idx);
5143 break;
5144 }
5145 } while (0);
5146 LOCK_GIVE(hdw->big_lock);
5147 return ret;
5148}
5149
5150
e61b6fc5 5151/* Find I2C address of eeprom */
07e337ee 5152static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
d855497e
MI		 5153{
5154 int result;
5155 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 5156 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 5157 result = pvr2_send_request(hdw,
5158 hdw->cmd_buffer,1,
5159 hdw->cmd_buffer,1);
5160 if (result < 0) break;
5161 result = hdw->cmd_buffer[0];
5162 } while(0); LOCK_GIVE(hdw->ctl_lock);
5163 return result;
5164}
5165
5166
32ffa9ae 5167int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
aecde8b5
HV		 5168 struct v4l2_dbg_match *match, u64 reg_id,
5169 int setFl, u64 *val_ptr)
32ffa9ae
MI		 5170{
5171#ifdef CONFIG_VIDEO_ADV_DEBUG
32ffa9ae 5172 struct pvr2_i2c_client *cp;
aecde8b5 5173 struct v4l2_dbg_register req;
6d98816f
MI		 5174 int stat = 0;
5175 int okFl = 0;
32ffa9ae 5176
201f5c9c
MI		 5177 if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5178
aecde8b5 5179 req.match = *match;
32ffa9ae
MI		 5180 req.reg = reg_id;
5181 if (setFl) req.val = *val_ptr;
d8f5b9ba
MI		 5182 /* It would be nice to know if a sub-device answered the request */
5183 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5184 if (!setFl) *val_ptr = req.val;
5185 if (!okFl) mutex_lock(&hdw->i2c_list_lock); do {
e77e2c2f 5186 list_for_each_entry(cp, &hdw->i2c_clients, list) {
8481a750
MI		 5187 if (!v4l2_chip_match_i2c_client(
5188 cp->client,
aecde8b5 5189 &req.match)) {
f3d092b8
HV		 5190 continue;
5191 }
32ffa9ae 5192 stat = pvr2_i2c_client_cmd(
52ebc763
TP		 5193 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
5194 VIDIOC_DBG_G_REGISTER),&req);
32ffa9ae 5195 if (!setFl) *val_ptr = req.val;
6d98816f
MI		 5196 okFl = !0;
5197 break;
32ffa9ae
MI		 5198 }
5199 } while (0); mutex_unlock(&hdw->i2c_list_lock);
6d98816f
MI		 5200 if (okFl) {
5201 return stat;
5202 }
32ffa9ae
MI		 5203 return -EINVAL;
5204#else
5205 return -ENOSYS;
5206#endif
5207}
5208
5209
d855497e
MI		 5210/*
5211 Stuff for Emacs to see, in order to encourage consistent editing style:
5212 *** Local Variables: ***
5213 *** mode: c ***
5214 *** fill-column: 75 ***
5215 *** tab-width: 8 ***
5216 *** c-basic-offset: 8 ***
5217 *** End: ***
5218 */
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