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d855497e MI |
1 | /* |
2 | * | |
3 | * $Id$ | |
4 | * | |
5 | * Copyright (C) 2005 Mike Isely <isely@pobox.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | * | |
20 | */ | |
21 | ||
22 | #include <linux/errno.h> | |
23 | #include <linux/string.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/firmware.h> | |
d855497e | 26 | #include <linux/videodev2.h> |
32ffa9ae | 27 | #include <media/v4l2-common.h> |
b2bbaa93 | 28 | #include <asm/semaphore.h> |
d855497e MI |
29 | #include "pvrusb2.h" |
30 | #include "pvrusb2-std.h" | |
31 | #include "pvrusb2-util.h" | |
32 | #include "pvrusb2-hdw.h" | |
33 | #include "pvrusb2-i2c-core.h" | |
34 | #include "pvrusb2-tuner.h" | |
35 | #include "pvrusb2-eeprom.h" | |
36 | #include "pvrusb2-hdw-internal.h" | |
37 | #include "pvrusb2-encoder.h" | |
38 | #include "pvrusb2-debug.h" | |
39 | ||
1bde0289 MI |
40 | #define TV_MIN_FREQ 55250000L |
41 | #define TV_MAX_FREQ 850000000L | |
42 | #define RADIO_MIN_FREQ 87000000L | |
98752102 | 43 | #define RADIO_MAX_FREQ 108000000L |
25d8527a | 44 | |
d855497e MI |
45 | struct usb_device_id pvr2_device_table[] = { |
46 | [PVR2_HDW_TYPE_29XXX] = { USB_DEVICE(0x2040, 0x2900) }, | |
d855497e | 47 | [PVR2_HDW_TYPE_24XXX] = { USB_DEVICE(0x2040, 0x2400) }, |
d855497e MI |
48 | { } |
49 | }; | |
50 | ||
51 | MODULE_DEVICE_TABLE(usb, pvr2_device_table); | |
52 | ||
53 | static const char *pvr2_device_names[] = { | |
54 | [PVR2_HDW_TYPE_29XXX] = "WinTV PVR USB2 Model Category 29xxxx", | |
d855497e | 55 | [PVR2_HDW_TYPE_24XXX] = "WinTV PVR USB2 Model Category 24xxxx", |
d855497e MI |
56 | }; |
57 | ||
58 | struct pvr2_string_table { | |
59 | const char **lst; | |
60 | unsigned int cnt; | |
61 | }; | |
62 | ||
d855497e MI |
63 | // Names of other client modules to request for 24xxx model hardware |
64 | static const char *pvr2_client_24xxx[] = { | |
65 | "cx25840", | |
66 | "tuner", | |
d855497e MI |
67 | "wm8775", |
68 | }; | |
d855497e MI |
69 | |
70 | // Names of other client modules to request for 29xxx model hardware | |
71 | static const char *pvr2_client_29xxx[] = { | |
72 | "msp3400", | |
73 | "saa7115", | |
74 | "tuner", | |
d855497e MI |
75 | }; |
76 | ||
77 | static struct pvr2_string_table pvr2_client_lists[] = { | |
78 | [PVR2_HDW_TYPE_29XXX] = { | |
79 | pvr2_client_29xxx, | |
80 | sizeof(pvr2_client_29xxx)/sizeof(pvr2_client_29xxx[0]), | |
81 | }, | |
d855497e MI |
82 | [PVR2_HDW_TYPE_24XXX] = { |
83 | pvr2_client_24xxx, | |
84 | sizeof(pvr2_client_24xxx)/sizeof(pvr2_client_24xxx[0]), | |
85 | }, | |
d855497e MI |
86 | }; |
87 | ||
a0fd1cb1 | 88 | static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL}; |
07e337ee | 89 | static DECLARE_MUTEX(pvr2_unit_sem); |
d855497e MI |
90 | |
91 | static int ctlchg = 0; | |
92 | static int initusbreset = 1; | |
93 | static int procreload = 0; | |
94 | static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 }; | |
95 | static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 }; | |
96 | static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 }; | |
1bde0289 | 97 | static int auto_mode_switch[PVR_NUM]; |
d855497e MI |
98 | static int init_pause_msec = 0; |
99 | ||
100 | module_param(ctlchg, int, S_IRUGO|S_IWUSR); | |
101 | MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value"); | |
102 | module_param(init_pause_msec, int, S_IRUGO|S_IWUSR); | |
103 | MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay"); | |
104 | module_param(initusbreset, int, S_IRUGO|S_IWUSR); | |
105 | MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe"); | |
106 | module_param(procreload, int, S_IRUGO|S_IWUSR); | |
107 | MODULE_PARM_DESC(procreload, | |
108 | "Attempt init failure recovery with firmware reload"); | |
109 | module_param_array(tuner, int, NULL, 0444); | |
110 | MODULE_PARM_DESC(tuner,"specify installed tuner type"); | |
111 | module_param_array(video_std, int, NULL, 0444); | |
112 | MODULE_PARM_DESC(video_std,"specify initial video standard"); | |
113 | module_param_array(tolerance, int, NULL, 0444); | |
114 | MODULE_PARM_DESC(tolerance,"specify stream error tolerance"); | |
1bde0289 MI |
115 | module_param_array(auto_mode_switch, int, NULL, 0444); |
116 | MODULE_PARM_DESC(auto_mode_switch,"Enable TV/Radio automatic mode switch based on freq"); | |
d855497e MI |
117 | |
118 | #define PVR2_CTL_WRITE_ENDPOINT 0x01 | |
119 | #define PVR2_CTL_READ_ENDPOINT 0x81 | |
120 | ||
121 | #define PVR2_GPIO_IN 0x9008 | |
122 | #define PVR2_GPIO_OUT 0x900c | |
123 | #define PVR2_GPIO_DIR 0x9020 | |
124 | ||
125 | #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__) | |
126 | ||
127 | #define PVR2_FIRMWARE_ENDPOINT 0x02 | |
128 | ||
129 | /* size of a firmware chunk */ | |
130 | #define FIRMWARE_CHUNK_SIZE 0x2000 | |
131 | ||
b30d2441 MI |
132 | /* Define the list of additional controls we'll dynamically construct based |
133 | on query of the cx2341x module. */ | |
134 | struct pvr2_mpeg_ids { | |
135 | const char *strid; | |
136 | int id; | |
137 | }; | |
138 | static const struct pvr2_mpeg_ids mpeg_ids[] = { | |
139 | { | |
140 | .strid = "audio_layer", | |
141 | .id = V4L2_CID_MPEG_AUDIO_ENCODING, | |
142 | },{ | |
143 | .strid = "audio_bitrate", | |
144 | .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE, | |
145 | },{ | |
146 | /* Already using audio_mode elsewhere :-( */ | |
147 | .strid = "mpeg_audio_mode", | |
148 | .id = V4L2_CID_MPEG_AUDIO_MODE, | |
149 | },{ | |
150 | .strid = "mpeg_audio_mode_extension", | |
151 | .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION, | |
152 | },{ | |
153 | .strid = "audio_emphasis", | |
154 | .id = V4L2_CID_MPEG_AUDIO_EMPHASIS, | |
155 | },{ | |
156 | .strid = "audio_crc", | |
157 | .id = V4L2_CID_MPEG_AUDIO_CRC, | |
158 | },{ | |
159 | .strid = "video_aspect", | |
160 | .id = V4L2_CID_MPEG_VIDEO_ASPECT, | |
161 | },{ | |
162 | .strid = "video_b_frames", | |
163 | .id = V4L2_CID_MPEG_VIDEO_B_FRAMES, | |
164 | },{ | |
165 | .strid = "video_gop_size", | |
166 | .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE, | |
167 | },{ | |
168 | .strid = "video_gop_closure", | |
169 | .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE, | |
b30d2441 MI |
170 | },{ |
171 | .strid = "video_bitrate_mode", | |
172 | .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE, | |
173 | },{ | |
174 | .strid = "video_bitrate", | |
175 | .id = V4L2_CID_MPEG_VIDEO_BITRATE, | |
176 | },{ | |
177 | .strid = "video_bitrate_peak", | |
178 | .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK, | |
179 | },{ | |
180 | .strid = "video_temporal_decimation", | |
181 | .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION, | |
182 | },{ | |
183 | .strid = "stream_type", | |
184 | .id = V4L2_CID_MPEG_STREAM_TYPE, | |
185 | },{ | |
186 | .strid = "video_spatial_filter_mode", | |
187 | .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE, | |
188 | },{ | |
189 | .strid = "video_spatial_filter", | |
190 | .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER, | |
191 | },{ | |
192 | .strid = "video_luma_spatial_filter_type", | |
193 | .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE, | |
194 | },{ | |
195 | .strid = "video_chroma_spatial_filter_type", | |
196 | .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE, | |
197 | },{ | |
198 | .strid = "video_temporal_filter_mode", | |
199 | .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE, | |
200 | },{ | |
201 | .strid = "video_temporal_filter", | |
202 | .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER, | |
203 | },{ | |
204 | .strid = "video_median_filter_type", | |
205 | .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE, | |
206 | },{ | |
207 | .strid = "video_luma_median_filter_top", | |
208 | .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP, | |
209 | },{ | |
210 | .strid = "video_luma_median_filter_bottom", | |
211 | .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM, | |
212 | },{ | |
213 | .strid = "video_chroma_median_filter_top", | |
214 | .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP, | |
215 | },{ | |
216 | .strid = "video_chroma_median_filter_bottom", | |
217 | .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM, | |
218 | } | |
219 | }; | |
220 | #define MPEGDEF_COUNT (sizeof(mpeg_ids)/sizeof(mpeg_ids[0])) | |
c05c0462 | 221 | |
434449f4 | 222 | |
d855497e | 223 | static const char *control_values_srate[] = { |
434449f4 MI |
224 | [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz", |
225 | [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz", | |
226 | [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz", | |
d855497e MI |
227 | }; |
228 | ||
229 | ||
d855497e | 230 | |
d855497e MI |
231 | static const char *control_values_input[] = { |
232 | [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/ | |
233 | [PVR2_CVAL_INPUT_RADIO] = "radio", | |
234 | [PVR2_CVAL_INPUT_SVIDEO] = "s-video", | |
235 | [PVR2_CVAL_INPUT_COMPOSITE] = "composite", | |
236 | }; | |
237 | ||
238 | ||
239 | static const char *control_values_audiomode[] = { | |
240 | [V4L2_TUNER_MODE_MONO] = "Mono", | |
241 | [V4L2_TUNER_MODE_STEREO] = "Stereo", | |
242 | [V4L2_TUNER_MODE_LANG1] = "Lang1", | |
243 | [V4L2_TUNER_MODE_LANG2] = "Lang2", | |
244 | [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2", | |
245 | }; | |
246 | ||
247 | ||
248 | static const char *control_values_hsm[] = { | |
249 | [PVR2_CVAL_HSM_FAIL] = "Fail", | |
250 | [PVR2_CVAL_HSM_HIGH] = "High", | |
251 | [PVR2_CVAL_HSM_FULL] = "Full", | |
252 | }; | |
253 | ||
254 | ||
255 | static const char *control_values_subsystem[] = { | |
256 | [PVR2_SUBSYS_B_ENC_FIRMWARE] = "enc_firmware", | |
257 | [PVR2_SUBSYS_B_ENC_CFG] = "enc_config", | |
258 | [PVR2_SUBSYS_B_DIGITIZER_RUN] = "digitizer_run", | |
259 | [PVR2_SUBSYS_B_USBSTREAM_RUN] = "usbstream_run", | |
260 | [PVR2_SUBSYS_B_ENC_RUN] = "enc_run", | |
261 | }; | |
262 | ||
1bde0289 | 263 | static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long); |
07e337ee AB |
264 | static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl); |
265 | static int pvr2_hdw_commit_ctl_internal(struct pvr2_hdw *hdw); | |
266 | static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw); | |
07e337ee AB |
267 | static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw); |
268 | static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw); | |
269 | static void pvr2_hdw_render_useless_unlocked(struct pvr2_hdw *hdw); | |
270 | static void pvr2_hdw_subsys_bit_chg_no_lock(struct pvr2_hdw *hdw, | |
271 | unsigned long msk, | |
272 | unsigned long val); | |
273 | static void pvr2_hdw_subsys_stream_bit_chg_no_lock(struct pvr2_hdw *hdw, | |
274 | unsigned long msk, | |
275 | unsigned long val); | |
276 | static int pvr2_send_request_ex(struct pvr2_hdw *hdw, | |
277 | unsigned int timeout,int probe_fl, | |
278 | void *write_data,unsigned int write_len, | |
279 | void *read_data,unsigned int read_len); | |
280 | static int pvr2_write_u16(struct pvr2_hdw *hdw, u16 data, int res); | |
281 | static int pvr2_write_u8(struct pvr2_hdw *hdw, u8 data, int res); | |
d855497e MI |
282 | |
283 | static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp) | |
284 | { | |
285 | struct pvr2_hdw *hdw = cptr->hdw; | |
286 | if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) { | |
287 | *vp = hdw->freqTable[hdw->freqProgSlot-1]; | |
288 | } else { | |
289 | *vp = 0; | |
290 | } | |
291 | return 0; | |
292 | } | |
293 | ||
294 | static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v) | |
295 | { | |
296 | struct pvr2_hdw *hdw = cptr->hdw; | |
1bde0289 MI |
297 | unsigned int slotId = hdw->freqProgSlot; |
298 | if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) { | |
299 | hdw->freqTable[slotId-1] = v; | |
300 | /* Handle side effects correctly - if we're tuned to this | |
301 | slot, then forgot the slot id relation since the stored | |
302 | frequency has been changed. */ | |
303 | if (hdw->freqSelector) { | |
304 | if (hdw->freqSlotRadio == slotId) { | |
305 | hdw->freqSlotRadio = 0; | |
306 | } | |
307 | } else { | |
308 | if (hdw->freqSlotTelevision == slotId) { | |
309 | hdw->freqSlotTelevision = 0; | |
310 | } | |
311 | } | |
d855497e MI |
312 | } |
313 | return 0; | |
314 | } | |
315 | ||
316 | static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp) | |
317 | { | |
318 | *vp = cptr->hdw->freqProgSlot; | |
319 | return 0; | |
320 | } | |
321 | ||
322 | static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v) | |
323 | { | |
324 | struct pvr2_hdw *hdw = cptr->hdw; | |
325 | if ((v >= 0) && (v <= FREQTABLE_SIZE)) { | |
326 | hdw->freqProgSlot = v; | |
327 | } | |
328 | return 0; | |
329 | } | |
330 | ||
331 | static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp) | |
332 | { | |
1bde0289 MI |
333 | struct pvr2_hdw *hdw = cptr->hdw; |
334 | *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision; | |
d855497e MI |
335 | return 0; |
336 | } | |
337 | ||
1bde0289 | 338 | static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId) |
d855497e MI |
339 | { |
340 | unsigned freq = 0; | |
341 | struct pvr2_hdw *hdw = cptr->hdw; | |
1bde0289 MI |
342 | if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0; |
343 | if (slotId > 0) { | |
344 | freq = hdw->freqTable[slotId-1]; | |
345 | if (!freq) return 0; | |
346 | pvr2_hdw_set_cur_freq(hdw,freq); | |
d855497e | 347 | } |
1bde0289 MI |
348 | if (hdw->freqSelector) { |
349 | hdw->freqSlotRadio = slotId; | |
350 | } else { | |
351 | hdw->freqSlotTelevision = slotId; | |
d855497e MI |
352 | } |
353 | return 0; | |
354 | } | |
355 | ||
356 | static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp) | |
357 | { | |
1bde0289 | 358 | *vp = pvr2_hdw_get_cur_freq(cptr->hdw); |
d855497e MI |
359 | return 0; |
360 | } | |
361 | ||
362 | static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr) | |
363 | { | |
364 | return cptr->hdw->freqDirty != 0; | |
365 | } | |
366 | ||
367 | static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr) | |
368 | { | |
369 | cptr->hdw->freqDirty = 0; | |
370 | } | |
371 | ||
372 | static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v) | |
373 | { | |
1bde0289 | 374 | pvr2_hdw_set_cur_freq(cptr->hdw,v); |
d855497e MI |
375 | return 0; |
376 | } | |
377 | ||
3ad9fc37 MI |
378 | static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp) |
379 | { | |
380 | /* Actual maximum depends on the video standard in effect. */ | |
381 | if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) { | |
382 | *vp = 480; | |
383 | } else { | |
384 | *vp = 576; | |
385 | } | |
386 | return 0; | |
387 | } | |
388 | ||
389 | static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp) | |
390 | { | |
391 | /* Actual minimum depends on device type. */ | |
392 | if (cptr->hdw->hdw_type == PVR2_HDW_TYPE_24XXX) { | |
393 | *vp = 75; | |
394 | } else { | |
395 | *vp = 17; | |
396 | } | |
397 | return 0; | |
398 | } | |
399 | ||
1bde0289 | 400 | static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp) |
5549f54f | 401 | { |
1bde0289 MI |
402 | *vp = cptr->hdw->input_val; |
403 | return 0; | |
404 | } | |
405 | ||
406 | static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v) | |
407 | { | |
408 | struct pvr2_hdw *hdw = cptr->hdw; | |
409 | ||
410 | if (hdw->input_val != v) { | |
411 | hdw->input_val = v; | |
412 | hdw->input_dirty = !0; | |
413 | } | |
414 | ||
415 | /* Handle side effects - if we switch to a mode that needs the RF | |
416 | tuner, then select the right frequency choice as well and mark | |
417 | it dirty. */ | |
418 | if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) { | |
419 | hdw->freqSelector = 0; | |
420 | hdw->freqDirty = !0; | |
421 | } else if (hdw->input_val == PVR2_CVAL_INPUT_TV) { | |
422 | hdw->freqSelector = 1; | |
423 | hdw->freqDirty = !0; | |
5549f54f | 424 | } |
1bde0289 MI |
425 | return 0; |
426 | } | |
427 | ||
428 | static int ctrl_isdirty_input(struct pvr2_ctrl *cptr) | |
429 | { | |
430 | return cptr->hdw->input_dirty != 0; | |
431 | } | |
432 | ||
433 | static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr) | |
434 | { | |
435 | cptr->hdw->input_dirty = 0; | |
436 | } | |
437 | ||
438 | static int ctrl_freq_check(struct pvr2_ctrl *cptr,int v) | |
439 | { | |
440 | /* Both ranges are simultaneously considered legal, in order to | |
441 | permit implicit mode switching, i.e. set a frequency in the | |
442 | other range and the mode will switch */ | |
443 | return (((v >= RADIO_MIN_FREQ) && (v <= RADIO_MAX_FREQ)) || | |
444 | ((v >= TV_MIN_FREQ) && (v <= TV_MAX_FREQ))); | |
5549f54f MI |
445 | } |
446 | ||
25d8527a PK |
447 | static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp) |
448 | { | |
449 | /* Actual maximum depends on radio/tv mode */ | |
450 | if (cptr->hdw->input_val == PVR2_CVAL_INPUT_RADIO) { | |
451 | *vp = RADIO_MAX_FREQ; | |
452 | } else { | |
453 | *vp = TV_MAX_FREQ; | |
454 | } | |
455 | return 0; | |
456 | } | |
457 | ||
458 | static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp) | |
459 | { | |
460 | /* Actual minimum depends on radio/tv mode */ | |
461 | if (cptr->hdw->input_val == PVR2_CVAL_INPUT_RADIO) { | |
462 | *vp = RADIO_MIN_FREQ; | |
463 | } else { | |
464 | *vp = TV_MIN_FREQ; | |
465 | } | |
466 | return 0; | |
467 | } | |
468 | ||
b30d2441 MI |
469 | static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr) |
470 | { | |
471 | return cptr->hdw->enc_stale != 0; | |
472 | } | |
473 | ||
474 | static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr) | |
475 | { | |
476 | cptr->hdw->enc_stale = 0; | |
477 | } | |
478 | ||
479 | static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp) | |
480 | { | |
481 | int ret; | |
482 | struct v4l2_ext_controls cs; | |
483 | struct v4l2_ext_control c1; | |
484 | memset(&cs,0,sizeof(cs)); | |
485 | memset(&c1,0,sizeof(c1)); | |
486 | cs.controls = &c1; | |
487 | cs.count = 1; | |
488 | c1.id = cptr->info->v4l_id; | |
489 | ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state,&cs, | |
490 | VIDIOC_G_EXT_CTRLS); | |
491 | if (ret) return ret; | |
492 | *vp = c1.value; | |
493 | return 0; | |
494 | } | |
495 | ||
496 | static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v) | |
497 | { | |
498 | int ret; | |
499 | struct v4l2_ext_controls cs; | |
500 | struct v4l2_ext_control c1; | |
501 | memset(&cs,0,sizeof(cs)); | |
502 | memset(&c1,0,sizeof(c1)); | |
503 | cs.controls = &c1; | |
504 | cs.count = 1; | |
505 | c1.id = cptr->info->v4l_id; | |
506 | c1.value = v; | |
507 | ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state,&cs, | |
508 | VIDIOC_S_EXT_CTRLS); | |
509 | if (ret) return ret; | |
510 | cptr->hdw->enc_stale = !0; | |
511 | return 0; | |
512 | } | |
513 | ||
514 | static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr) | |
515 | { | |
516 | struct v4l2_queryctrl qctrl; | |
517 | struct pvr2_ctl_info *info; | |
518 | qctrl.id = cptr->info->v4l_id; | |
519 | cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl); | |
520 | /* Strip out the const so we can adjust a function pointer. It's | |
521 | OK to do this here because we know this is a dynamically created | |
522 | control, so the underlying storage for the info pointer is (a) | |
523 | private to us, and (b) not in read-only storage. Either we do | |
524 | this or we significantly complicate the underlying control | |
525 | implementation. */ | |
526 | info = (struct pvr2_ctl_info *)(cptr->info); | |
527 | if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) { | |
528 | if (info->set_value) { | |
a0fd1cb1 | 529 | info->set_value = NULL; |
b30d2441 MI |
530 | } |
531 | } else { | |
532 | if (!(info->set_value)) { | |
533 | info->set_value = ctrl_cx2341x_set; | |
534 | } | |
535 | } | |
536 | return qctrl.flags; | |
537 | } | |
538 | ||
d855497e MI |
539 | static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp) |
540 | { | |
541 | *vp = cptr->hdw->flag_streaming_enabled; | |
542 | return 0; | |
543 | } | |
544 | ||
545 | static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp) | |
546 | { | |
547 | int result = pvr2_hdw_is_hsm(cptr->hdw); | |
548 | *vp = PVR2_CVAL_HSM_FULL; | |
549 | if (result < 0) *vp = PVR2_CVAL_HSM_FAIL; | |
550 | if (result) *vp = PVR2_CVAL_HSM_HIGH; | |
551 | return 0; | |
552 | } | |
553 | ||
554 | static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp) | |
555 | { | |
556 | *vp = cptr->hdw->std_mask_avail; | |
557 | return 0; | |
558 | } | |
559 | ||
560 | static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v) | |
561 | { | |
562 | struct pvr2_hdw *hdw = cptr->hdw; | |
563 | v4l2_std_id ns; | |
564 | ns = hdw->std_mask_avail; | |
565 | ns = (ns & ~m) | (v & m); | |
566 | if (ns == hdw->std_mask_avail) return 0; | |
567 | hdw->std_mask_avail = ns; | |
568 | pvr2_hdw_internal_set_std_avail(hdw); | |
569 | pvr2_hdw_internal_find_stdenum(hdw); | |
570 | return 0; | |
571 | } | |
572 | ||
573 | static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val, | |
574 | char *bufPtr,unsigned int bufSize, | |
575 | unsigned int *len) | |
576 | { | |
577 | *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val); | |
578 | return 0; | |
579 | } | |
580 | ||
581 | static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr, | |
582 | const char *bufPtr,unsigned int bufSize, | |
583 | int *mskp,int *valp) | |
584 | { | |
585 | int ret; | |
586 | v4l2_std_id id; | |
587 | ret = pvr2_std_str_to_id(&id,bufPtr,bufSize); | |
588 | if (ret < 0) return ret; | |
589 | if (mskp) *mskp = id; | |
590 | if (valp) *valp = id; | |
591 | return 0; | |
592 | } | |
593 | ||
594 | static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp) | |
595 | { | |
596 | *vp = cptr->hdw->std_mask_cur; | |
597 | return 0; | |
598 | } | |
599 | ||
600 | static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v) | |
601 | { | |
602 | struct pvr2_hdw *hdw = cptr->hdw; | |
603 | v4l2_std_id ns; | |
604 | ns = hdw->std_mask_cur; | |
605 | ns = (ns & ~m) | (v & m); | |
606 | if (ns == hdw->std_mask_cur) return 0; | |
607 | hdw->std_mask_cur = ns; | |
608 | hdw->std_dirty = !0; | |
609 | pvr2_hdw_internal_find_stdenum(hdw); | |
610 | return 0; | |
611 | } | |
612 | ||
613 | static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr) | |
614 | { | |
615 | return cptr->hdw->std_dirty != 0; | |
616 | } | |
617 | ||
618 | static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr) | |
619 | { | |
620 | cptr->hdw->std_dirty = 0; | |
621 | } | |
622 | ||
623 | static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp) | |
624 | { | |
18103c57 MI |
625 | struct pvr2_hdw *hdw = cptr->hdw; |
626 | pvr2_i2c_core_status_poll(hdw); | |
627 | *vp = hdw->tuner_signal_info.signal; | |
628 | return 0; | |
629 | } | |
630 | ||
631 | static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp) | |
632 | { | |
633 | int val = 0; | |
634 | unsigned int subchan; | |
635 | struct pvr2_hdw *hdw = cptr->hdw; | |
636 | if (hdw->tuner_signal_stale) { | |
637 | pvr2_i2c_core_status_poll(hdw); | |
638 | } | |
639 | subchan = hdw->tuner_signal_info.rxsubchans; | |
640 | if (subchan & V4L2_TUNER_SUB_MONO) { | |
641 | val |= (1 << V4L2_TUNER_MODE_MONO); | |
642 | } | |
643 | if (subchan & V4L2_TUNER_SUB_STEREO) { | |
644 | val |= (1 << V4L2_TUNER_MODE_STEREO); | |
645 | } | |
646 | if (subchan & V4L2_TUNER_SUB_LANG1) { | |
647 | val |= (1 << V4L2_TUNER_MODE_LANG1); | |
648 | } | |
649 | if (subchan & V4L2_TUNER_SUB_LANG2) { | |
650 | val |= (1 << V4L2_TUNER_MODE_LANG2); | |
651 | } | |
652 | *vp = val; | |
d855497e MI |
653 | return 0; |
654 | } | |
655 | ||
656 | static int ctrl_subsys_get(struct pvr2_ctrl *cptr,int *vp) | |
657 | { | |
658 | *vp = cptr->hdw->subsys_enabled_mask; | |
659 | return 0; | |
660 | } | |
661 | ||
662 | static int ctrl_subsys_set(struct pvr2_ctrl *cptr,int m,int v) | |
663 | { | |
664 | pvr2_hdw_subsys_bit_chg_no_lock(cptr->hdw,m,v); | |
665 | return 0; | |
666 | } | |
667 | ||
668 | static int ctrl_subsys_stream_get(struct pvr2_ctrl *cptr,int *vp) | |
669 | { | |
670 | *vp = cptr->hdw->subsys_stream_mask; | |
671 | return 0; | |
672 | } | |
673 | ||
674 | static int ctrl_subsys_stream_set(struct pvr2_ctrl *cptr,int m,int v) | |
675 | { | |
676 | pvr2_hdw_subsys_stream_bit_chg_no_lock(cptr->hdw,m,v); | |
677 | return 0; | |
678 | } | |
679 | ||
680 | static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v) | |
681 | { | |
682 | struct pvr2_hdw *hdw = cptr->hdw; | |
683 | if (v < 0) return -EINVAL; | |
684 | if (v > hdw->std_enum_cnt) return -EINVAL; | |
685 | hdw->std_enum_cur = v; | |
686 | if (!v) return 0; | |
687 | v--; | |
688 | if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0; | |
689 | hdw->std_mask_cur = hdw->std_defs[v].id; | |
690 | hdw->std_dirty = !0; | |
691 | return 0; | |
692 | } | |
693 | ||
694 | ||
695 | static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp) | |
696 | { | |
697 | *vp = cptr->hdw->std_enum_cur; | |
698 | return 0; | |
699 | } | |
700 | ||
701 | ||
702 | static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr) | |
703 | { | |
704 | return cptr->hdw->std_dirty != 0; | |
705 | } | |
706 | ||
707 | ||
708 | static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr) | |
709 | { | |
710 | cptr->hdw->std_dirty = 0; | |
711 | } | |
712 | ||
713 | ||
714 | #define DEFINT(vmin,vmax) \ | |
715 | .type = pvr2_ctl_int, \ | |
716 | .def.type_int.min_value = vmin, \ | |
717 | .def.type_int.max_value = vmax | |
718 | ||
719 | #define DEFENUM(tab) \ | |
720 | .type = pvr2_ctl_enum, \ | |
721 | .def.type_enum.count = (sizeof(tab)/sizeof((tab)[0])), \ | |
722 | .def.type_enum.value_names = tab | |
723 | ||
33213963 MI |
724 | #define DEFBOOL \ |
725 | .type = pvr2_ctl_bool | |
726 | ||
d855497e MI |
727 | #define DEFMASK(msk,tab) \ |
728 | .type = pvr2_ctl_bitmask, \ | |
729 | .def.type_bitmask.valid_bits = msk, \ | |
730 | .def.type_bitmask.bit_names = tab | |
731 | ||
732 | #define DEFREF(vname) \ | |
733 | .set_value = ctrl_set_##vname, \ | |
734 | .get_value = ctrl_get_##vname, \ | |
735 | .is_dirty = ctrl_isdirty_##vname, \ | |
736 | .clear_dirty = ctrl_cleardirty_##vname | |
737 | ||
738 | ||
739 | #define VCREATE_FUNCS(vname) \ | |
740 | static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \ | |
741 | {*vp = cptr->hdw->vname##_val; return 0;} \ | |
742 | static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \ | |
743 | {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \ | |
744 | static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \ | |
745 | {return cptr->hdw->vname##_dirty != 0;} \ | |
746 | static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \ | |
747 | {cptr->hdw->vname##_dirty = 0;} | |
748 | ||
749 | VCREATE_FUNCS(brightness) | |
750 | VCREATE_FUNCS(contrast) | |
751 | VCREATE_FUNCS(saturation) | |
752 | VCREATE_FUNCS(hue) | |
753 | VCREATE_FUNCS(volume) | |
754 | VCREATE_FUNCS(balance) | |
755 | VCREATE_FUNCS(bass) | |
756 | VCREATE_FUNCS(treble) | |
757 | VCREATE_FUNCS(mute) | |
c05c0462 MI |
758 | VCREATE_FUNCS(audiomode) |
759 | VCREATE_FUNCS(res_hor) | |
760 | VCREATE_FUNCS(res_ver) | |
d855497e | 761 | VCREATE_FUNCS(srate) |
1bde0289 | 762 | VCREATE_FUNCS(automodeswitch) |
d855497e | 763 | |
d855497e MI |
764 | /* Table definition of all controls which can be manipulated */ |
765 | static const struct pvr2_ctl_info control_defs[] = { | |
766 | { | |
767 | .v4l_id = V4L2_CID_BRIGHTNESS, | |
768 | .desc = "Brightness", | |
769 | .name = "brightness", | |
770 | .default_value = 128, | |
771 | DEFREF(brightness), | |
772 | DEFINT(0,255), | |
773 | },{ | |
774 | .v4l_id = V4L2_CID_CONTRAST, | |
775 | .desc = "Contrast", | |
776 | .name = "contrast", | |
777 | .default_value = 68, | |
778 | DEFREF(contrast), | |
779 | DEFINT(0,127), | |
780 | },{ | |
781 | .v4l_id = V4L2_CID_SATURATION, | |
782 | .desc = "Saturation", | |
783 | .name = "saturation", | |
784 | .default_value = 64, | |
785 | DEFREF(saturation), | |
786 | DEFINT(0,127), | |
787 | },{ | |
788 | .v4l_id = V4L2_CID_HUE, | |
789 | .desc = "Hue", | |
790 | .name = "hue", | |
791 | .default_value = 0, | |
792 | DEFREF(hue), | |
793 | DEFINT(-128,127), | |
794 | },{ | |
795 | .v4l_id = V4L2_CID_AUDIO_VOLUME, | |
796 | .desc = "Volume", | |
797 | .name = "volume", | |
139eecf9 | 798 | .default_value = 62000, |
d855497e MI |
799 | DEFREF(volume), |
800 | DEFINT(0,65535), | |
801 | },{ | |
802 | .v4l_id = V4L2_CID_AUDIO_BALANCE, | |
803 | .desc = "Balance", | |
804 | .name = "balance", | |
805 | .default_value = 0, | |
806 | DEFREF(balance), | |
807 | DEFINT(-32768,32767), | |
808 | },{ | |
809 | .v4l_id = V4L2_CID_AUDIO_BASS, | |
810 | .desc = "Bass", | |
811 | .name = "bass", | |
812 | .default_value = 0, | |
813 | DEFREF(bass), | |
814 | DEFINT(-32768,32767), | |
815 | },{ | |
816 | .v4l_id = V4L2_CID_AUDIO_TREBLE, | |
817 | .desc = "Treble", | |
818 | .name = "treble", | |
819 | .default_value = 0, | |
820 | DEFREF(treble), | |
821 | DEFINT(-32768,32767), | |
822 | },{ | |
823 | .v4l_id = V4L2_CID_AUDIO_MUTE, | |
824 | .desc = "Mute", | |
825 | .name = "mute", | |
826 | .default_value = 0, | |
827 | DEFREF(mute), | |
33213963 | 828 | DEFBOOL, |
c05c0462 MI |
829 | },{ |
830 | .desc = "Video Source", | |
831 | .name = "input", | |
832 | .internal_id = PVR2_CID_INPUT, | |
833 | .default_value = PVR2_CVAL_INPUT_TV, | |
834 | DEFREF(input), | |
835 | DEFENUM(control_values_input), | |
836 | },{ | |
837 | .desc = "Audio Mode", | |
838 | .name = "audio_mode", | |
839 | .internal_id = PVR2_CID_AUDIOMODE, | |
840 | .default_value = V4L2_TUNER_MODE_STEREO, | |
841 | DEFREF(audiomode), | |
842 | DEFENUM(control_values_audiomode), | |
843 | },{ | |
844 | .desc = "Horizontal capture resolution", | |
845 | .name = "resolution_hor", | |
846 | .internal_id = PVR2_CID_HRES, | |
847 | .default_value = 720, | |
848 | DEFREF(res_hor), | |
3ad9fc37 | 849 | DEFINT(19,720), |
c05c0462 MI |
850 | },{ |
851 | .desc = "Vertical capture resolution", | |
852 | .name = "resolution_ver", | |
853 | .internal_id = PVR2_CID_VRES, | |
854 | .default_value = 480, | |
855 | DEFREF(res_ver), | |
3ad9fc37 MI |
856 | DEFINT(17,576), |
857 | /* Hook in check for video standard and adjust maximum | |
858 | depending on the standard. */ | |
859 | .get_max_value = ctrl_vres_max_get, | |
860 | .get_min_value = ctrl_vres_min_get, | |
1bde0289 | 861 | },{ |
1bde0289 MI |
862 | .desc = "Automatic TV / Radio mode switch based on frequency", |
863 | .name = "auto_mode_switch", | |
864 | .default_value = 0, | |
865 | DEFREF(automodeswitch), | |
866 | DEFBOOL, | |
d855497e | 867 | },{ |
b30d2441 | 868 | .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ, |
434449f4 MI |
869 | .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000, |
870 | .desc = "Audio Sampling Frequency", | |
d855497e | 871 | .name = "srate", |
d855497e MI |
872 | DEFREF(srate), |
873 | DEFENUM(control_values_srate), | |
d855497e MI |
874 | },{ |
875 | .desc = "Tuner Frequency (Hz)", | |
876 | .name = "frequency", | |
877 | .internal_id = PVR2_CID_FREQUENCY, | |
1bde0289 | 878 | .default_value = 0, |
d855497e MI |
879 | .set_value = ctrl_freq_set, |
880 | .get_value = ctrl_freq_get, | |
881 | .is_dirty = ctrl_freq_is_dirty, | |
882 | .clear_dirty = ctrl_freq_clear_dirty, | |
25d8527a PK |
883 | DEFINT(TV_MIN_FREQ,TV_MAX_FREQ), |
884 | /* Hook in check for input value (tv/radio) and adjust | |
885 | max/min values accordingly */ | |
5549f54f | 886 | .check_value = ctrl_freq_check, |
25d8527a PK |
887 | .get_max_value = ctrl_freq_max_get, |
888 | .get_min_value = ctrl_freq_min_get, | |
d855497e MI |
889 | },{ |
890 | .desc = "Channel", | |
891 | .name = "channel", | |
892 | .set_value = ctrl_channel_set, | |
893 | .get_value = ctrl_channel_get, | |
894 | DEFINT(0,FREQTABLE_SIZE), | |
895 | },{ | |
896 | .desc = "Channel Program Frequency", | |
897 | .name = "freq_table_value", | |
898 | .set_value = ctrl_channelfreq_set, | |
899 | .get_value = ctrl_channelfreq_get, | |
25d8527a | 900 | DEFINT(TV_MIN_FREQ,TV_MAX_FREQ), |
1bde0289 MI |
901 | /* Hook in check for input value (tv/radio) and adjust |
902 | max/min values accordingly */ | |
903 | .check_value = ctrl_freq_check, | |
904 | .get_max_value = ctrl_freq_max_get, | |
905 | .get_min_value = ctrl_freq_min_get, | |
d855497e MI |
906 | },{ |
907 | .desc = "Channel Program ID", | |
908 | .name = "freq_table_channel", | |
909 | .set_value = ctrl_channelprog_set, | |
910 | .get_value = ctrl_channelprog_get, | |
911 | DEFINT(0,FREQTABLE_SIZE), | |
d855497e MI |
912 | },{ |
913 | .desc = "Streaming Enabled", | |
914 | .name = "streaming_enabled", | |
915 | .get_value = ctrl_streamingenabled_get, | |
33213963 | 916 | DEFBOOL, |
d855497e MI |
917 | },{ |
918 | .desc = "USB Speed", | |
919 | .name = "usb_speed", | |
920 | .get_value = ctrl_hsm_get, | |
921 | DEFENUM(control_values_hsm), | |
922 | },{ | |
923 | .desc = "Signal Present", | |
924 | .name = "signal_present", | |
925 | .get_value = ctrl_signal_get, | |
18103c57 MI |
926 | DEFINT(0,65535), |
927 | },{ | |
928 | .desc = "Audio Modes Present", | |
929 | .name = "audio_modes_present", | |
930 | .get_value = ctrl_audio_modes_present_get, | |
931 | /* For this type we "borrow" the V4L2_TUNER_MODE enum from | |
932 | v4l. Nothing outside of this module cares about this, | |
933 | but I reuse it in order to also reuse the | |
934 | control_values_audiomode string table. */ | |
935 | DEFMASK(((1 << V4L2_TUNER_MODE_MONO)| | |
936 | (1 << V4L2_TUNER_MODE_STEREO)| | |
937 | (1 << V4L2_TUNER_MODE_LANG1)| | |
938 | (1 << V4L2_TUNER_MODE_LANG2)), | |
939 | control_values_audiomode), | |
d855497e MI |
940 | },{ |
941 | .desc = "Video Standards Available Mask", | |
942 | .name = "video_standard_mask_available", | |
943 | .internal_id = PVR2_CID_STDAVAIL, | |
944 | .skip_init = !0, | |
945 | .get_value = ctrl_stdavail_get, | |
946 | .set_value = ctrl_stdavail_set, | |
947 | .val_to_sym = ctrl_std_val_to_sym, | |
948 | .sym_to_val = ctrl_std_sym_to_val, | |
949 | .type = pvr2_ctl_bitmask, | |
950 | },{ | |
951 | .desc = "Video Standards In Use Mask", | |
952 | .name = "video_standard_mask_active", | |
953 | .internal_id = PVR2_CID_STDCUR, | |
954 | .skip_init = !0, | |
955 | .get_value = ctrl_stdcur_get, | |
956 | .set_value = ctrl_stdcur_set, | |
957 | .is_dirty = ctrl_stdcur_is_dirty, | |
958 | .clear_dirty = ctrl_stdcur_clear_dirty, | |
959 | .val_to_sym = ctrl_std_val_to_sym, | |
960 | .sym_to_val = ctrl_std_sym_to_val, | |
961 | .type = pvr2_ctl_bitmask, | |
962 | },{ | |
963 | .desc = "Subsystem enabled mask", | |
964 | .name = "debug_subsys_mask", | |
965 | .skip_init = !0, | |
966 | .get_value = ctrl_subsys_get, | |
967 | .set_value = ctrl_subsys_set, | |
968 | DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem), | |
969 | },{ | |
970 | .desc = "Subsystem stream mask", | |
971 | .name = "debug_subsys_stream_mask", | |
972 | .skip_init = !0, | |
973 | .get_value = ctrl_subsys_stream_get, | |
974 | .set_value = ctrl_subsys_stream_set, | |
975 | DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem), | |
976 | },{ | |
977 | .desc = "Video Standard Name", | |
978 | .name = "video_standard", | |
979 | .internal_id = PVR2_CID_STDENUM, | |
980 | .skip_init = !0, | |
981 | .get_value = ctrl_stdenumcur_get, | |
982 | .set_value = ctrl_stdenumcur_set, | |
983 | .is_dirty = ctrl_stdenumcur_is_dirty, | |
984 | .clear_dirty = ctrl_stdenumcur_clear_dirty, | |
985 | .type = pvr2_ctl_enum, | |
986 | } | |
987 | }; | |
988 | ||
c05c0462 | 989 | #define CTRLDEF_COUNT (sizeof(control_defs)/sizeof(control_defs[0])) |
d855497e MI |
990 | |
991 | ||
992 | const char *pvr2_config_get_name(enum pvr2_config cfg) | |
993 | { | |
994 | switch (cfg) { | |
995 | case pvr2_config_empty: return "empty"; | |
996 | case pvr2_config_mpeg: return "mpeg"; | |
997 | case pvr2_config_vbi: return "vbi"; | |
16eb40d3 MI |
998 | case pvr2_config_pcm: return "pcm"; |
999 | case pvr2_config_rawvideo: return "raw video"; | |
d855497e MI |
1000 | } |
1001 | return "<unknown>"; | |
1002 | } | |
1003 | ||
1004 | ||
1005 | struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw) | |
1006 | { | |
1007 | return hdw->usb_dev; | |
1008 | } | |
1009 | ||
1010 | ||
1011 | unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw) | |
1012 | { | |
1013 | return hdw->serial_number; | |
1014 | } | |
1015 | ||
1bde0289 MI |
1016 | unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw) |
1017 | { | |
1018 | return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio; | |
1019 | } | |
1020 | ||
1021 | /* Set the currently tuned frequency and account for all possible | |
1022 | driver-core side effects of this action. */ | |
1023 | void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val) | |
1024 | { | |
1025 | int mode = 0; | |
1026 | ||
1027 | /* If hdw->automodeswitch_val is set, then we do something clever: | |
1028 | Look at the desired frequency and see if it looks like FM or TV. | |
1029 | Execute a possible mode switch based on this result. Otherwise | |
1030 | we use the current input setting to determine which frequency | |
1031 | register we need to adjust. */ | |
1032 | if (hdw->automodeswitch_val) { | |
1033 | /* Note that since FM RADIO frequency range sits *inside* | |
1034 | the TV spectrum that we must therefore check the radio | |
1035 | range first... */ | |
1036 | if ((val >= RADIO_MIN_FREQ) && (val <= RADIO_MAX_FREQ)) { | |
1037 | mode = 1; | |
1038 | } else if ((val >= TV_MIN_FREQ) && (val <= TV_MAX_FREQ)) { | |
1039 | mode = 2; | |
1040 | } | |
1041 | } else { | |
1042 | if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) { | |
1043 | mode = 1; | |
1044 | } else { | |
1045 | mode = 2; | |
1046 | } | |
1047 | } | |
1048 | ||
1049 | switch (mode) { | |
1050 | case 1: | |
1051 | if (hdw->freqSelector) { | |
1052 | /* Swing over to radio frequency selection */ | |
1053 | hdw->freqSelector = 0; | |
1054 | hdw->freqDirty = !0; | |
1055 | } | |
1056 | if (hdw->input_val == PVR2_CVAL_INPUT_TV) { | |
1057 | /* Force switch to radio mode */ | |
1058 | hdw->input_val = PVR2_CVAL_INPUT_RADIO; | |
1059 | hdw->input_dirty = !0; | |
1060 | } | |
1061 | if (hdw->freqValRadio != val) { | |
1062 | hdw->freqValRadio = val; | |
1063 | hdw->freqSlotRadio = 0; | |
1064 | if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) { | |
1065 | hdw->freqDirty = !0; | |
1066 | } | |
1067 | } | |
1068 | break; | |
1069 | case 2: | |
1070 | if (!(hdw->freqSelector)) { | |
1071 | /* Swing over to television frequency selection */ | |
1072 | hdw->freqSelector = 1; | |
1073 | hdw->freqDirty = !0; | |
1074 | } | |
1075 | if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) { | |
1076 | /* Force switch to television mode */ | |
1077 | hdw->input_val = PVR2_CVAL_INPUT_TV; | |
1078 | hdw->input_dirty = !0; | |
1079 | } | |
1080 | if (hdw->freqValTelevision != val) { | |
1081 | hdw->freqValTelevision = val; | |
1082 | hdw->freqSlotTelevision = 0; | |
1083 | if (hdw->input_val == PVR2_CVAL_INPUT_TV) { | |
1084 | hdw->freqDirty = !0; | |
1085 | } | |
1086 | } | |
1087 | break; | |
1088 | default: | |
1089 | break; | |
1090 | } | |
1091 | } | |
1092 | ||
d855497e MI |
1093 | int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw) |
1094 | { | |
1095 | return hdw->unit_number; | |
1096 | } | |
1097 | ||
1098 | ||
1099 | /* Attempt to locate one of the given set of files. Messages are logged | |
1100 | appropriate to what has been found. The return value will be 0 or | |
1101 | greater on success (it will be the index of the file name found) and | |
1102 | fw_entry will be filled in. Otherwise a negative error is returned on | |
1103 | failure. If the return value is -ENOENT then no viable firmware file | |
1104 | could be located. */ | |
1105 | static int pvr2_locate_firmware(struct pvr2_hdw *hdw, | |
1106 | const struct firmware **fw_entry, | |
1107 | const char *fwtypename, | |
1108 | unsigned int fwcount, | |
1109 | const char *fwnames[]) | |
1110 | { | |
1111 | unsigned int idx; | |
1112 | int ret = -EINVAL; | |
1113 | for (idx = 0; idx < fwcount; idx++) { | |
1114 | ret = request_firmware(fw_entry, | |
1115 | fwnames[idx], | |
1116 | &hdw->usb_dev->dev); | |
1117 | if (!ret) { | |
1118 | trace_firmware("Located %s firmware: %s;" | |
1119 | " uploading...", | |
1120 | fwtypename, | |
1121 | fwnames[idx]); | |
1122 | return idx; | |
1123 | } | |
1124 | if (ret == -ENOENT) continue; | |
1125 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1126 | "request_firmware fatal error with code=%d",ret); | |
1127 | return ret; | |
1128 | } | |
1129 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1130 | "***WARNING***" | |
1131 | " Device %s firmware" | |
1132 | " seems to be missing.", | |
1133 | fwtypename); | |
1134 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1135 | "Did you install the pvrusb2 firmware files" | |
1136 | " in their proper location?"); | |
1137 | if (fwcount == 1) { | |
1138 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1139 | "request_firmware unable to locate %s file %s", | |
1140 | fwtypename,fwnames[0]); | |
1141 | } else { | |
1142 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1143 | "request_firmware unable to locate" | |
1144 | " one of the following %s files:", | |
1145 | fwtypename); | |
1146 | for (idx = 0; idx < fwcount; idx++) { | |
1147 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1148 | "request_firmware: Failed to find %s", | |
1149 | fwnames[idx]); | |
1150 | } | |
1151 | } | |
1152 | return ret; | |
1153 | } | |
1154 | ||
1155 | ||
1156 | /* | |
1157 | * pvr2_upload_firmware1(). | |
1158 | * | |
1159 | * Send the 8051 firmware to the device. After the upload, arrange for | |
1160 | * device to re-enumerate. | |
1161 | * | |
1162 | * NOTE : the pointer to the firmware data given by request_firmware() | |
1163 | * is not suitable for an usb transaction. | |
1164 | * | |
1165 | */ | |
07e337ee | 1166 | static int pvr2_upload_firmware1(struct pvr2_hdw *hdw) |
d855497e | 1167 | { |
a0fd1cb1 | 1168 | const struct firmware *fw_entry = NULL; |
d855497e MI |
1169 | void *fw_ptr; |
1170 | unsigned int pipe; | |
1171 | int ret; | |
1172 | u16 address; | |
1173 | static const char *fw_files_29xxx[] = { | |
1174 | "v4l-pvrusb2-29xxx-01.fw", | |
1175 | }; | |
d855497e MI |
1176 | static const char *fw_files_24xxx[] = { |
1177 | "v4l-pvrusb2-24xxx-01.fw", | |
1178 | }; | |
d855497e MI |
1179 | static const struct pvr2_string_table fw_file_defs[] = { |
1180 | [PVR2_HDW_TYPE_29XXX] = { | |
1181 | fw_files_29xxx, | |
1182 | sizeof(fw_files_29xxx)/sizeof(fw_files_29xxx[0]), | |
1183 | }, | |
d855497e MI |
1184 | [PVR2_HDW_TYPE_24XXX] = { |
1185 | fw_files_24xxx, | |
1186 | sizeof(fw_files_24xxx)/sizeof(fw_files_24xxx[0]), | |
1187 | }, | |
d855497e MI |
1188 | }; |
1189 | hdw->fw1_state = FW1_STATE_FAILED; // default result | |
1190 | ||
1191 | trace_firmware("pvr2_upload_firmware1"); | |
1192 | ||
1193 | ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller", | |
1194 | fw_file_defs[hdw->hdw_type].cnt, | |
1195 | fw_file_defs[hdw->hdw_type].lst); | |
1196 | if (ret < 0) { | |
1197 | if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING; | |
1198 | return ret; | |
1199 | } | |
1200 | ||
1201 | usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0); | |
1202 | usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f)); | |
1203 | ||
1204 | pipe = usb_sndctrlpipe(hdw->usb_dev, 0); | |
1205 | ||
1206 | if (fw_entry->size != 0x2000){ | |
1207 | pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size"); | |
1208 | release_firmware(fw_entry); | |
1209 | return -ENOMEM; | |
1210 | } | |
1211 | ||
1212 | fw_ptr = kmalloc(0x800, GFP_KERNEL); | |
1213 | if (fw_ptr == NULL){ | |
1214 | release_firmware(fw_entry); | |
1215 | return -ENOMEM; | |
1216 | } | |
1217 | ||
1218 | /* We have to hold the CPU during firmware upload. */ | |
1219 | pvr2_hdw_cpureset_assert(hdw,1); | |
1220 | ||
1221 | /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes | |
1222 | chunk. */ | |
1223 | ||
1224 | ret = 0; | |
1225 | for(address = 0; address < fw_entry->size; address += 0x800) { | |
1226 | memcpy(fw_ptr, fw_entry->data + address, 0x800); | |
1227 | ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address, | |
1228 | 0, fw_ptr, 0x800, HZ); | |
1229 | } | |
1230 | ||
1231 | trace_firmware("Upload done, releasing device's CPU"); | |
1232 | ||
1233 | /* Now release the CPU. It will disconnect and reconnect later. */ | |
1234 | pvr2_hdw_cpureset_assert(hdw,0); | |
1235 | ||
1236 | kfree(fw_ptr); | |
1237 | release_firmware(fw_entry); | |
1238 | ||
1239 | trace_firmware("Upload done (%d bytes sent)",ret); | |
1240 | ||
1241 | /* We should have written 8192 bytes */ | |
1242 | if (ret == 8192) { | |
1243 | hdw->fw1_state = FW1_STATE_RELOAD; | |
1244 | return 0; | |
1245 | } | |
1246 | ||
1247 | return -EIO; | |
1248 | } | |
1249 | ||
1250 | ||
1251 | /* | |
1252 | * pvr2_upload_firmware2() | |
1253 | * | |
1254 | * This uploads encoder firmware on endpoint 2. | |
1255 | * | |
1256 | */ | |
1257 | ||
1258 | int pvr2_upload_firmware2(struct pvr2_hdw *hdw) | |
1259 | { | |
a0fd1cb1 | 1260 | const struct firmware *fw_entry = NULL; |
d855497e MI |
1261 | void *fw_ptr; |
1262 | unsigned int pipe, fw_len, fw_done; | |
1263 | int actual_length; | |
1264 | int ret = 0; | |
1265 | int fwidx; | |
1266 | static const char *fw_files[] = { | |
1267 | CX2341X_FIRM_ENC_FILENAME, | |
1268 | }; | |
1269 | ||
1270 | trace_firmware("pvr2_upload_firmware2"); | |
1271 | ||
1272 | ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder", | |
1273 | sizeof(fw_files)/sizeof(fw_files[0]), | |
1274 | fw_files); | |
1275 | if (ret < 0) return ret; | |
1276 | fwidx = ret; | |
1277 | ret = 0; | |
b30d2441 MI |
1278 | /* Since we're about to completely reinitialize the encoder, |
1279 | invalidate our cached copy of its configuration state. Next | |
1280 | time we configure the encoder, then we'll fully configure it. */ | |
1281 | hdw->enc_cur_valid = 0; | |
d855497e MI |
1282 | |
1283 | /* First prepare firmware loading */ | |
1284 | ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/ | |
1285 | ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/ | |
1286 | ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/ | |
1287 | ret |= pvr2_hdw_cmd_deep_reset(hdw); | |
1288 | ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/ | |
1289 | ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/ | |
1290 | ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/ | |
1291 | ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/ | |
1292 | ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/ | |
1293 | ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/ | |
1294 | ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/ | |
1295 | ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/ | |
1296 | ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/ | |
1297 | ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/ | |
1298 | ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/ | |
1299 | ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/ | |
1300 | ret |= pvr2_write_u8(hdw, 0x52, 0); | |
1301 | ret |= pvr2_write_u16(hdw, 0x0600, 0); | |
1302 | ||
1303 | if (ret) { | |
1304 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1305 | "firmware2 upload prep failed, ret=%d",ret); | |
1306 | release_firmware(fw_entry); | |
1307 | return ret; | |
1308 | } | |
1309 | ||
1310 | /* Now send firmware */ | |
1311 | ||
1312 | fw_len = fw_entry->size; | |
1313 | ||
1314 | if (fw_len % FIRMWARE_CHUNK_SIZE) { | |
1315 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1316 | "size of %s firmware" | |
1317 | " must be a multiple of 8192B", | |
1318 | fw_files[fwidx]); | |
1319 | release_firmware(fw_entry); | |
1320 | return -1; | |
1321 | } | |
1322 | ||
1323 | fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL); | |
1324 | if (fw_ptr == NULL){ | |
1325 | release_firmware(fw_entry); | |
1326 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1327 | "failed to allocate memory for firmware2 upload"); | |
1328 | return -ENOMEM; | |
1329 | } | |
1330 | ||
1331 | pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT); | |
1332 | ||
1333 | for (fw_done = 0 ; (fw_done < fw_len) && !ret ; | |
1334 | fw_done += FIRMWARE_CHUNK_SIZE ) { | |
1335 | int i; | |
1336 | memcpy(fw_ptr, fw_entry->data + fw_done, FIRMWARE_CHUNK_SIZE); | |
1337 | /* Usbsnoop log shows that we must swap bytes... */ | |
1338 | for (i = 0; i < FIRMWARE_CHUNK_SIZE/4 ; i++) | |
1339 | ((u32 *)fw_ptr)[i] = ___swab32(((u32 *)fw_ptr)[i]); | |
1340 | ||
1341 | ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr, | |
1342 | FIRMWARE_CHUNK_SIZE, | |
1343 | &actual_length, HZ); | |
1344 | ret |= (actual_length != FIRMWARE_CHUNK_SIZE); | |
1345 | } | |
1346 | ||
1347 | trace_firmware("upload of %s : %i / %i ", | |
1348 | fw_files[fwidx],fw_done,fw_len); | |
1349 | ||
1350 | kfree(fw_ptr); | |
1351 | release_firmware(fw_entry); | |
1352 | ||
1353 | if (ret) { | |
1354 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1355 | "firmware2 upload transfer failure"); | |
1356 | return ret; | |
1357 | } | |
1358 | ||
1359 | /* Finish upload */ | |
1360 | ||
1361 | ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/ | |
1362 | ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/ | |
1363 | ret |= pvr2_write_u16(hdw, 0x0600, 0); | |
1364 | ||
1365 | if (ret) { | |
1366 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1367 | "firmware2 upload post-proc failure"); | |
1368 | } else { | |
1369 | hdw->subsys_enabled_mask |= (1<<PVR2_SUBSYS_B_ENC_FIRMWARE); | |
1370 | } | |
1371 | return ret; | |
1372 | } | |
1373 | ||
1374 | ||
1375 | #define FIRMWARE_RECOVERY_BITS \ | |
1376 | ((1<<PVR2_SUBSYS_B_ENC_CFG) | \ | |
1377 | (1<<PVR2_SUBSYS_B_ENC_RUN) | \ | |
1378 | (1<<PVR2_SUBSYS_B_ENC_FIRMWARE) | \ | |
1379 | (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) | |
1380 | ||
1381 | /* | |
1382 | ||
1383 | This single function is key to pretty much everything. The pvrusb2 | |
1384 | device can logically be viewed as a series of subsystems which can be | |
1385 | stopped / started or unconfigured / configured. To get things streaming, | |
1386 | one must configure everything and start everything, but there may be | |
1387 | various reasons over time to deconfigure something or stop something. | |
1388 | This function handles all of this activity. Everything EVERYWHERE that | |
1389 | must affect a subsystem eventually comes here to do the work. | |
1390 | ||
1391 | The current state of all subsystems is represented by a single bit mask, | |
1392 | known as subsys_enabled_mask. The bit positions are defined by the | |
1393 | PVR2_SUBSYS_xxxx macros, with one subsystem per bit position. At any | |
1394 | time the set of configured or active subsystems can be queried just by | |
1395 | looking at that mask. To change bits in that mask, this function here | |
1396 | must be called. The "msk" argument indicates which bit positions to | |
1397 | change, and the "val" argument defines the new values for the positions | |
1398 | defined by "msk". | |
1399 | ||
1400 | There is a priority ordering of starting / stopping things, and for | |
1401 | multiple requested changes, this function implements that ordering. | |
1402 | (Thus we will act on a request to load encoder firmware before we | |
1403 | configure the encoder.) In addition to priority ordering, there is a | |
1404 | recovery strategy implemented here. If a particular step fails and we | |
1405 | detect that failure, this function will clear the affected subsystem bits | |
1406 | and restart. Thus we have a means for recovering from a dead encoder: | |
1407 | Clear all bits that correspond to subsystems that we need to restart / | |
1408 | reconfigure and start over. | |
1409 | ||
1410 | */ | |
07e337ee AB |
1411 | static void pvr2_hdw_subsys_bit_chg_no_lock(struct pvr2_hdw *hdw, |
1412 | unsigned long msk, | |
1413 | unsigned long val) | |
d855497e MI |
1414 | { |
1415 | unsigned long nmsk; | |
1416 | unsigned long vmsk; | |
1417 | int ret; | |
1418 | unsigned int tryCount = 0; | |
1419 | ||
1420 | if (!hdw->flag_ok) return; | |
1421 | ||
1422 | msk &= PVR2_SUBSYS_ALL; | |
eb8e0ee4 MI |
1423 | nmsk = (hdw->subsys_enabled_mask & ~msk) | (val & msk); |
1424 | nmsk &= PVR2_SUBSYS_ALL; | |
d855497e MI |
1425 | |
1426 | for (;;) { | |
1427 | tryCount++; | |
eb8e0ee4 MI |
1428 | if (!((nmsk ^ hdw->subsys_enabled_mask) & |
1429 | PVR2_SUBSYS_ALL)) break; | |
d855497e MI |
1430 | if (tryCount > 4) { |
1431 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1432 | "Too many retries when configuring device;" | |
1433 | " giving up"); | |
1434 | pvr2_hdw_render_useless(hdw); | |
1435 | break; | |
1436 | } | |
1437 | if (tryCount > 1) { | |
1438 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1439 | "Retrying device reconfiguration"); | |
1440 | } | |
1441 | pvr2_trace(PVR2_TRACE_INIT, | |
1442 | "subsys mask changing 0x%lx:0x%lx" | |
1443 | " from 0x%lx to 0x%lx", | |
1444 | msk,val,hdw->subsys_enabled_mask,nmsk); | |
1445 | ||
1446 | vmsk = (nmsk ^ hdw->subsys_enabled_mask) & | |
1447 | hdw->subsys_enabled_mask; | |
1448 | if (vmsk) { | |
1449 | if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) { | |
1450 | pvr2_trace(PVR2_TRACE_CTL, | |
1451 | "/*---TRACE_CTL----*/" | |
1452 | " pvr2_encoder_stop"); | |
1453 | ret = pvr2_encoder_stop(hdw); | |
1454 | if (ret) { | |
1455 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1456 | "Error recovery initiated"); | |
1457 | hdw->subsys_enabled_mask &= | |
1458 | ~FIRMWARE_RECOVERY_BITS; | |
1459 | continue; | |
1460 | } | |
1461 | } | |
1462 | if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) { | |
1463 | pvr2_trace(PVR2_TRACE_CTL, | |
1464 | "/*---TRACE_CTL----*/" | |
1465 | " pvr2_hdw_cmd_usbstream(0)"); | |
1466 | pvr2_hdw_cmd_usbstream(hdw,0); | |
1467 | } | |
1468 | if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) { | |
1469 | pvr2_trace(PVR2_TRACE_CTL, | |
1470 | "/*---TRACE_CTL----*/" | |
1471 | " decoder disable"); | |
1472 | if (hdw->decoder_ctrl) { | |
1473 | hdw->decoder_ctrl->enable( | |
1474 | hdw->decoder_ctrl->ctxt,0); | |
1475 | } else { | |
1476 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1477 | "WARNING:" | |
1478 | " No decoder present"); | |
1479 | } | |
1480 | hdw->subsys_enabled_mask &= | |
1481 | ~(1<<PVR2_SUBSYS_B_DIGITIZER_RUN); | |
1482 | } | |
1483 | if (vmsk & PVR2_SUBSYS_CFG_ALL) { | |
1484 | hdw->subsys_enabled_mask &= | |
1485 | ~(vmsk & PVR2_SUBSYS_CFG_ALL); | |
1486 | } | |
1487 | } | |
1488 | vmsk = (nmsk ^ hdw->subsys_enabled_mask) & nmsk; | |
1489 | if (vmsk) { | |
1490 | if (vmsk & (1<<PVR2_SUBSYS_B_ENC_FIRMWARE)) { | |
1491 | pvr2_trace(PVR2_TRACE_CTL, | |
1492 | "/*---TRACE_CTL----*/" | |
1493 | " pvr2_upload_firmware2"); | |
1494 | ret = pvr2_upload_firmware2(hdw); | |
1495 | if (ret) { | |
1496 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1497 | "Failure uploading encoder" | |
1498 | " firmware"); | |
1499 | pvr2_hdw_render_useless(hdw); | |
1500 | break; | |
1501 | } | |
1502 | } | |
1503 | if (vmsk & (1<<PVR2_SUBSYS_B_ENC_CFG)) { | |
1504 | pvr2_trace(PVR2_TRACE_CTL, | |
1505 | "/*---TRACE_CTL----*/" | |
1506 | " pvr2_encoder_configure"); | |
1507 | ret = pvr2_encoder_configure(hdw); | |
1508 | if (ret) { | |
1509 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1510 | "Error recovery initiated"); | |
1511 | hdw->subsys_enabled_mask &= | |
1512 | ~FIRMWARE_RECOVERY_BITS; | |
1513 | continue; | |
1514 | } | |
1515 | } | |
1516 | if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) { | |
1517 | pvr2_trace(PVR2_TRACE_CTL, | |
1518 | "/*---TRACE_CTL----*/" | |
1519 | " decoder enable"); | |
1520 | if (hdw->decoder_ctrl) { | |
1521 | hdw->decoder_ctrl->enable( | |
1522 | hdw->decoder_ctrl->ctxt,!0); | |
1523 | } else { | |
1524 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1525 | "WARNING:" | |
1526 | " No decoder present"); | |
1527 | } | |
1528 | hdw->subsys_enabled_mask |= | |
1529 | (1<<PVR2_SUBSYS_B_DIGITIZER_RUN); | |
1530 | } | |
1531 | if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) { | |
1532 | pvr2_trace(PVR2_TRACE_CTL, | |
1533 | "/*---TRACE_CTL----*/" | |
1534 | " pvr2_hdw_cmd_usbstream(1)"); | |
1535 | pvr2_hdw_cmd_usbstream(hdw,!0); | |
1536 | } | |
1537 | if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) { | |
1538 | pvr2_trace(PVR2_TRACE_CTL, | |
1539 | "/*---TRACE_CTL----*/" | |
1540 | " pvr2_encoder_start"); | |
1541 | ret = pvr2_encoder_start(hdw); | |
1542 | if (ret) { | |
1543 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1544 | "Error recovery initiated"); | |
1545 | hdw->subsys_enabled_mask &= | |
1546 | ~FIRMWARE_RECOVERY_BITS; | |
1547 | continue; | |
1548 | } | |
1549 | } | |
1550 | } | |
1551 | } | |
1552 | } | |
1553 | ||
1554 | ||
1555 | void pvr2_hdw_subsys_bit_chg(struct pvr2_hdw *hdw, | |
1556 | unsigned long msk,unsigned long val) | |
1557 | { | |
1558 | LOCK_TAKE(hdw->big_lock); do { | |
1559 | pvr2_hdw_subsys_bit_chg_no_lock(hdw,msk,val); | |
1560 | } while (0); LOCK_GIVE(hdw->big_lock); | |
1561 | } | |
1562 | ||
1563 | ||
d855497e MI |
1564 | unsigned long pvr2_hdw_subsys_get(struct pvr2_hdw *hdw) |
1565 | { | |
1566 | return hdw->subsys_enabled_mask; | |
1567 | } | |
1568 | ||
1569 | ||
1570 | unsigned long pvr2_hdw_subsys_stream_get(struct pvr2_hdw *hdw) | |
1571 | { | |
1572 | return hdw->subsys_stream_mask; | |
1573 | } | |
1574 | ||
1575 | ||
07e337ee AB |
1576 | static void pvr2_hdw_subsys_stream_bit_chg_no_lock(struct pvr2_hdw *hdw, |
1577 | unsigned long msk, | |
1578 | unsigned long val) | |
d855497e MI |
1579 | { |
1580 | unsigned long val2; | |
1581 | msk &= PVR2_SUBSYS_ALL; | |
1582 | val2 = ((hdw->subsys_stream_mask & ~msk) | (val & msk)); | |
1583 | pvr2_trace(PVR2_TRACE_INIT, | |
1584 | "stream mask changing 0x%lx:0x%lx from 0x%lx to 0x%lx", | |
1585 | msk,val,hdw->subsys_stream_mask,val2); | |
1586 | hdw->subsys_stream_mask = val2; | |
1587 | } | |
1588 | ||
1589 | ||
1590 | void pvr2_hdw_subsys_stream_bit_chg(struct pvr2_hdw *hdw, | |
1591 | unsigned long msk, | |
1592 | unsigned long val) | |
1593 | { | |
1594 | LOCK_TAKE(hdw->big_lock); do { | |
1595 | pvr2_hdw_subsys_stream_bit_chg_no_lock(hdw,msk,val); | |
1596 | } while (0); LOCK_GIVE(hdw->big_lock); | |
1597 | } | |
1598 | ||
1599 | ||
07e337ee | 1600 | static int pvr2_hdw_set_streaming_no_lock(struct pvr2_hdw *hdw,int enableFl) |
d855497e MI |
1601 | { |
1602 | if ((!enableFl) == !(hdw->flag_streaming_enabled)) return 0; | |
1603 | if (enableFl) { | |
1604 | pvr2_trace(PVR2_TRACE_START_STOP, | |
1605 | "/*--TRACE_STREAM--*/ enable"); | |
1606 | pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,~0); | |
1607 | } else { | |
1608 | pvr2_trace(PVR2_TRACE_START_STOP, | |
1609 | "/*--TRACE_STREAM--*/ disable"); | |
1610 | pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0); | |
1611 | } | |
1612 | if (!hdw->flag_ok) return -EIO; | |
1613 | hdw->flag_streaming_enabled = enableFl != 0; | |
1614 | return 0; | |
1615 | } | |
1616 | ||
1617 | ||
1618 | int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw) | |
1619 | { | |
1620 | return hdw->flag_streaming_enabled != 0; | |
1621 | } | |
1622 | ||
1623 | ||
1624 | int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag) | |
1625 | { | |
1626 | int ret; | |
1627 | LOCK_TAKE(hdw->big_lock); do { | |
1628 | ret = pvr2_hdw_set_streaming_no_lock(hdw,enable_flag); | |
1629 | } while (0); LOCK_GIVE(hdw->big_lock); | |
1630 | return ret; | |
1631 | } | |
1632 | ||
1633 | ||
07e337ee AB |
1634 | static int pvr2_hdw_set_stream_type_no_lock(struct pvr2_hdw *hdw, |
1635 | enum pvr2_config config) | |
d855497e MI |
1636 | { |
1637 | unsigned long sm = hdw->subsys_enabled_mask; | |
1638 | if (!hdw->flag_ok) return -EIO; | |
1639 | pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0); | |
1640 | hdw->config = config; | |
1641 | pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,sm); | |
1642 | return 0; | |
1643 | } | |
1644 | ||
1645 | ||
1646 | int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config) | |
1647 | { | |
1648 | int ret; | |
1649 | if (!hdw->flag_ok) return -EIO; | |
1650 | LOCK_TAKE(hdw->big_lock); | |
1651 | ret = pvr2_hdw_set_stream_type_no_lock(hdw,config); | |
1652 | LOCK_GIVE(hdw->big_lock); | |
1653 | return ret; | |
1654 | } | |
1655 | ||
1656 | ||
1657 | static int get_default_tuner_type(struct pvr2_hdw *hdw) | |
1658 | { | |
1659 | int unit_number = hdw->unit_number; | |
1660 | int tp = -1; | |
1661 | if ((unit_number >= 0) && (unit_number < PVR_NUM)) { | |
1662 | tp = tuner[unit_number]; | |
1663 | } | |
1664 | if (tp < 0) return -EINVAL; | |
1665 | hdw->tuner_type = tp; | |
1666 | return 0; | |
1667 | } | |
1668 | ||
1669 | ||
1670 | static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw) | |
1671 | { | |
1672 | int unit_number = hdw->unit_number; | |
1673 | int tp = 0; | |
1674 | if ((unit_number >= 0) && (unit_number < PVR_NUM)) { | |
1675 | tp = video_std[unit_number]; | |
1676 | } | |
1677 | return tp; | |
1678 | } | |
1679 | ||
1680 | ||
1681 | static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw) | |
1682 | { | |
1683 | int unit_number = hdw->unit_number; | |
1684 | int tp = 0; | |
1685 | if ((unit_number >= 0) && (unit_number < PVR_NUM)) { | |
1686 | tp = tolerance[unit_number]; | |
1687 | } | |
1688 | return tp; | |
1689 | } | |
1690 | ||
1691 | ||
1692 | static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw) | |
1693 | { | |
1694 | /* Try a harmless request to fetch the eeprom's address over | |
1695 | endpoint 1. See what happens. Only the full FX2 image can | |
1696 | respond to this. If this probe fails then likely the FX2 | |
1697 | firmware needs be loaded. */ | |
1698 | int result; | |
1699 | LOCK_TAKE(hdw->ctl_lock); do { | |
1700 | hdw->cmd_buffer[0] = 0xeb; | |
1701 | result = pvr2_send_request_ex(hdw,HZ*1,!0, | |
1702 | hdw->cmd_buffer,1, | |
1703 | hdw->cmd_buffer,1); | |
1704 | if (result < 0) break; | |
1705 | } while(0); LOCK_GIVE(hdw->ctl_lock); | |
1706 | if (result) { | |
1707 | pvr2_trace(PVR2_TRACE_INIT, | |
1708 | "Probe of device endpoint 1 result status %d", | |
1709 | result); | |
1710 | } else { | |
1711 | pvr2_trace(PVR2_TRACE_INIT, | |
1712 | "Probe of device endpoint 1 succeeded"); | |
1713 | } | |
1714 | return result == 0; | |
1715 | } | |
1716 | ||
1717 | static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw) | |
1718 | { | |
1719 | char buf[40]; | |
1720 | unsigned int bcnt; | |
1721 | v4l2_std_id std1,std2; | |
1722 | ||
1723 | std1 = get_default_standard(hdw); | |
1724 | ||
1725 | bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom); | |
1726 | pvr2_trace(PVR2_TRACE_INIT, | |
1727 | "Supported video standard(s) reported by eeprom: %.*s", | |
1728 | bcnt,buf); | |
1729 | ||
1730 | hdw->std_mask_avail = hdw->std_mask_eeprom; | |
1731 | ||
1732 | std2 = std1 & ~hdw->std_mask_avail; | |
1733 | if (std2) { | |
1734 | bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2); | |
1735 | pvr2_trace(PVR2_TRACE_INIT, | |
1736 | "Expanding supported video standards" | |
1737 | " to include: %.*s", | |
1738 | bcnt,buf); | |
1739 | hdw->std_mask_avail |= std2; | |
1740 | } | |
1741 | ||
1742 | pvr2_hdw_internal_set_std_avail(hdw); | |
1743 | ||
1744 | if (std1) { | |
1745 | bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1); | |
1746 | pvr2_trace(PVR2_TRACE_INIT, | |
1747 | "Initial video standard forced to %.*s", | |
1748 | bcnt,buf); | |
1749 | hdw->std_mask_cur = std1; | |
1750 | hdw->std_dirty = !0; | |
1751 | pvr2_hdw_internal_find_stdenum(hdw); | |
1752 | return; | |
1753 | } | |
1754 | ||
1755 | if (hdw->std_enum_cnt > 1) { | |
1756 | // Autoselect the first listed standard | |
1757 | hdw->std_enum_cur = 1; | |
1758 | hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id; | |
1759 | hdw->std_dirty = !0; | |
1760 | pvr2_trace(PVR2_TRACE_INIT, | |
1761 | "Initial video standard auto-selected to %s", | |
1762 | hdw->std_defs[hdw->std_enum_cur-1].name); | |
1763 | return; | |
1764 | } | |
1765 | ||
0885ba1d | 1766 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, |
d855497e MI |
1767 | "Unable to select a viable initial video standard"); |
1768 | } | |
1769 | ||
1770 | ||
1771 | static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw) | |
1772 | { | |
1773 | int ret; | |
1774 | unsigned int idx; | |
1775 | struct pvr2_ctrl *cptr; | |
1776 | int reloadFl = 0; | |
1777 | if (!reloadFl) { | |
1778 | reloadFl = (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints | |
1779 | == 0); | |
1780 | if (reloadFl) { | |
1781 | pvr2_trace(PVR2_TRACE_INIT, | |
1782 | "USB endpoint config looks strange" | |
1783 | "; possibly firmware needs to be loaded"); | |
1784 | } | |
1785 | } | |
1786 | if (!reloadFl) { | |
1787 | reloadFl = !pvr2_hdw_check_firmware(hdw); | |
1788 | if (reloadFl) { | |
1789 | pvr2_trace(PVR2_TRACE_INIT, | |
1790 | "Check for FX2 firmware failed" | |
1791 | "; possibly firmware needs to be loaded"); | |
1792 | } | |
1793 | } | |
1794 | if (reloadFl) { | |
1795 | if (pvr2_upload_firmware1(hdw) != 0) { | |
1796 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1797 | "Failure uploading firmware1"); | |
1798 | } | |
1799 | return; | |
1800 | } | |
1801 | hdw->fw1_state = FW1_STATE_OK; | |
1802 | ||
1803 | if (initusbreset) { | |
1804 | pvr2_hdw_device_reset(hdw); | |
1805 | } | |
1806 | if (!pvr2_hdw_dev_ok(hdw)) return; | |
1807 | ||
1808 | for (idx = 0; idx < pvr2_client_lists[hdw->hdw_type].cnt; idx++) { | |
1809 | request_module(pvr2_client_lists[hdw->hdw_type].lst[idx]); | |
1810 | } | |
1811 | ||
1812 | pvr2_hdw_cmd_powerup(hdw); | |
1813 | if (!pvr2_hdw_dev_ok(hdw)) return; | |
1814 | ||
1815 | if (pvr2_upload_firmware2(hdw)){ | |
1816 | pvr2_trace(PVR2_TRACE_ERROR_LEGS,"device unstable!!"); | |
1817 | pvr2_hdw_render_useless(hdw); | |
1818 | return; | |
1819 | } | |
1820 | ||
1821 | // This step MUST happen after the earlier powerup step. | |
1822 | pvr2_i2c_core_init(hdw); | |
1823 | if (!pvr2_hdw_dev_ok(hdw)) return; | |
1824 | ||
c05c0462 | 1825 | for (idx = 0; idx < CTRLDEF_COUNT; idx++) { |
d855497e MI |
1826 | cptr = hdw->controls + idx; |
1827 | if (cptr->info->skip_init) continue; | |
1828 | if (!cptr->info->set_value) continue; | |
1829 | cptr->info->set_value(cptr,~0,cptr->info->default_value); | |
1830 | } | |
1831 | ||
1bde0289 MI |
1832 | /* Set up special default values for the television and radio |
1833 | frequencies here. It's not really important what these defaults | |
1834 | are, but I set them to something usable in the Chicago area just | |
1835 | to make driver testing a little easier. */ | |
1836 | ||
1837 | /* US Broadcast channel 7 (175.25 MHz) */ | |
1838 | hdw->freqValTelevision = 175250000L; | |
1839 | /* 104.3 MHz, a usable FM station for my area */ | |
1840 | hdw->freqValRadio = 104300000L; | |
1841 | ||
1842 | /* Default value for auto mode switch based on module option */ | |
1843 | if ((hdw->unit_number >= 0) && (hdw->unit_number < PVR_NUM)) { | |
1844 | hdw->automodeswitch_val = auto_mode_switch[hdw->unit_number]; | |
1845 | } | |
1846 | ||
d855497e MI |
1847 | // Do not use pvr2_reset_ctl_endpoints() here. It is not |
1848 | // thread-safe against the normal pvr2_send_request() mechanism. | |
1849 | // (We should make it thread safe). | |
1850 | ||
1851 | ret = pvr2_hdw_get_eeprom_addr(hdw); | |
1852 | if (!pvr2_hdw_dev_ok(hdw)) return; | |
1853 | if (ret < 0) { | |
1854 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1855 | "Unable to determine location of eeprom, skipping"); | |
1856 | } else { | |
1857 | hdw->eeprom_addr = ret; | |
1858 | pvr2_eeprom_analyze(hdw); | |
1859 | if (!pvr2_hdw_dev_ok(hdw)) return; | |
1860 | } | |
1861 | ||
1862 | pvr2_hdw_setup_std(hdw); | |
1863 | ||
1864 | if (!get_default_tuner_type(hdw)) { | |
1865 | pvr2_trace(PVR2_TRACE_INIT, | |
1866 | "pvr2_hdw_setup: Tuner type overridden to %d", | |
1867 | hdw->tuner_type); | |
1868 | } | |
1869 | ||
1870 | hdw->tuner_updated = !0; | |
1871 | pvr2_i2c_core_check_stale(hdw); | |
1872 | hdw->tuner_updated = 0; | |
1873 | ||
1874 | if (!pvr2_hdw_dev_ok(hdw)) return; | |
1875 | ||
1876 | pvr2_hdw_commit_ctl_internal(hdw); | |
1877 | if (!pvr2_hdw_dev_ok(hdw)) return; | |
1878 | ||
1879 | hdw->vid_stream = pvr2_stream_create(); | |
1880 | if (!pvr2_hdw_dev_ok(hdw)) return; | |
1881 | pvr2_trace(PVR2_TRACE_INIT, | |
1882 | "pvr2_hdw_setup: video stream is %p",hdw->vid_stream); | |
1883 | if (hdw->vid_stream) { | |
1884 | idx = get_default_error_tolerance(hdw); | |
1885 | if (idx) { | |
1886 | pvr2_trace(PVR2_TRACE_INIT, | |
1887 | "pvr2_hdw_setup: video stream %p" | |
1888 | " setting tolerance %u", | |
1889 | hdw->vid_stream,idx); | |
1890 | } | |
1891 | pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev, | |
1892 | PVR2_VID_ENDPOINT,idx); | |
1893 | } | |
1894 | ||
1895 | if (!pvr2_hdw_dev_ok(hdw)) return; | |
1896 | ||
1897 | /* Make sure everything is up to date */ | |
1898 | pvr2_i2c_core_sync(hdw); | |
1899 | ||
1900 | if (!pvr2_hdw_dev_ok(hdw)) return; | |
1901 | ||
1902 | hdw->flag_init_ok = !0; | |
1903 | } | |
1904 | ||
1905 | ||
1906 | int pvr2_hdw_setup(struct pvr2_hdw *hdw) | |
1907 | { | |
1908 | pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw); | |
1909 | LOCK_TAKE(hdw->big_lock); do { | |
1910 | pvr2_hdw_setup_low(hdw); | |
1911 | pvr2_trace(PVR2_TRACE_INIT, | |
1912 | "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d", | |
1913 | hdw,hdw->flag_ok,hdw->flag_init_ok); | |
1914 | if (pvr2_hdw_dev_ok(hdw)) { | |
1915 | if (pvr2_hdw_init_ok(hdw)) { | |
1916 | pvr2_trace( | |
1917 | PVR2_TRACE_INFO, | |
1918 | "Device initialization" | |
1919 | " completed successfully."); | |
1920 | break; | |
1921 | } | |
1922 | if (hdw->fw1_state == FW1_STATE_RELOAD) { | |
1923 | pvr2_trace( | |
1924 | PVR2_TRACE_INFO, | |
1925 | "Device microcontroller firmware" | |
1926 | " (re)loaded; it should now reset" | |
1927 | " and reconnect."); | |
1928 | break; | |
1929 | } | |
1930 | pvr2_trace( | |
1931 | PVR2_TRACE_ERROR_LEGS, | |
1932 | "Device initialization was not successful."); | |
1933 | if (hdw->fw1_state == FW1_STATE_MISSING) { | |
1934 | pvr2_trace( | |
1935 | PVR2_TRACE_ERROR_LEGS, | |
1936 | "Giving up since device" | |
1937 | " microcontroller firmware" | |
1938 | " appears to be missing."); | |
1939 | break; | |
1940 | } | |
1941 | } | |
1942 | if (procreload) { | |
1943 | pvr2_trace( | |
1944 | PVR2_TRACE_ERROR_LEGS, | |
1945 | "Attempting pvrusb2 recovery by reloading" | |
1946 | " primary firmware."); | |
1947 | pvr2_trace( | |
1948 | PVR2_TRACE_ERROR_LEGS, | |
1949 | "If this works, device should disconnect" | |
1950 | " and reconnect in a sane state."); | |
1951 | hdw->fw1_state = FW1_STATE_UNKNOWN; | |
1952 | pvr2_upload_firmware1(hdw); | |
1953 | } else { | |
1954 | pvr2_trace( | |
1955 | PVR2_TRACE_ERROR_LEGS, | |
1956 | "***WARNING*** pvrusb2 device hardware" | |
1957 | " appears to be jammed" | |
1958 | " and I can't clear it."); | |
1959 | pvr2_trace( | |
1960 | PVR2_TRACE_ERROR_LEGS, | |
1961 | "You might need to power cycle" | |
1962 | " the pvrusb2 device" | |
1963 | " in order to recover."); | |
1964 | } | |
1965 | } while (0); LOCK_GIVE(hdw->big_lock); | |
1966 | pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw); | |
1967 | return hdw->flag_init_ok; | |
1968 | } | |
1969 | ||
1970 | ||
1971 | /* Create and return a structure for interacting with the underlying | |
1972 | hardware */ | |
1973 | struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf, | |
1974 | const struct usb_device_id *devid) | |
1975 | { | |
1976 | unsigned int idx,cnt1,cnt2; | |
1977 | struct pvr2_hdw *hdw; | |
1978 | unsigned int hdw_type; | |
1979 | int valid_std_mask; | |
1980 | struct pvr2_ctrl *cptr; | |
1981 | __u8 ifnum; | |
b30d2441 MI |
1982 | struct v4l2_queryctrl qctrl; |
1983 | struct pvr2_ctl_info *ciptr; | |
d855497e MI |
1984 | |
1985 | hdw_type = devid - pvr2_device_table; | |
1986 | if (hdw_type >= | |
1987 | sizeof(pvr2_device_names)/sizeof(pvr2_device_names[0])) { | |
1988 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
1989 | "Bogus device type of %u reported",hdw_type); | |
a0fd1cb1 | 1990 | return NULL; |
d855497e MI |
1991 | } |
1992 | ||
1993 | hdw = kmalloc(sizeof(*hdw),GFP_KERNEL); | |
1994 | pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"", | |
1995 | hdw,pvr2_device_names[hdw_type]); | |
1996 | if (!hdw) goto fail; | |
1997 | memset(hdw,0,sizeof(*hdw)); | |
18103c57 | 1998 | hdw->tuner_signal_stale = !0; |
b30d2441 | 1999 | cx2341x_fill_defaults(&hdw->enc_ctl_state); |
d855497e | 2000 | |
c05c0462 | 2001 | hdw->control_cnt = CTRLDEF_COUNT; |
b30d2441 | 2002 | hdw->control_cnt += MPEGDEF_COUNT; |
c05c0462 | 2003 | hdw->controls = kmalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt, |
d855497e MI |
2004 | GFP_KERNEL); |
2005 | if (!hdw->controls) goto fail; | |
c05c0462 | 2006 | memset(hdw->controls,0,sizeof(struct pvr2_ctrl) * hdw->control_cnt); |
d855497e | 2007 | hdw->hdw_type = hdw_type; |
c05c0462 MI |
2008 | for (idx = 0; idx < hdw->control_cnt; idx++) { |
2009 | cptr = hdw->controls + idx; | |
2010 | cptr->hdw = hdw; | |
2011 | } | |
d855497e MI |
2012 | for (idx = 0; idx < 32; idx++) { |
2013 | hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx]; | |
2014 | } | |
c05c0462 | 2015 | for (idx = 0; idx < CTRLDEF_COUNT; idx++) { |
d855497e | 2016 | cptr = hdw->controls + idx; |
d855497e MI |
2017 | cptr->info = control_defs+idx; |
2018 | } | |
b30d2441 MI |
2019 | /* Define and configure additional controls from cx2341x module. */ |
2020 | hdw->mpeg_ctrl_info = kmalloc( | |
2021 | sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL); | |
2022 | if (!hdw->mpeg_ctrl_info) goto fail; | |
2023 | memset(hdw->mpeg_ctrl_info,0, | |
2024 | sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT); | |
2025 | for (idx = 0; idx < MPEGDEF_COUNT; idx++) { | |
2026 | cptr = hdw->controls + idx + CTRLDEF_COUNT; | |
2027 | ciptr = &(hdw->mpeg_ctrl_info[idx].info); | |
2028 | ciptr->desc = hdw->mpeg_ctrl_info[idx].desc; | |
2029 | ciptr->name = mpeg_ids[idx].strid; | |
2030 | ciptr->v4l_id = mpeg_ids[idx].id; | |
2031 | ciptr->skip_init = !0; | |
2032 | ciptr->get_value = ctrl_cx2341x_get; | |
2033 | ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags; | |
2034 | ciptr->is_dirty = ctrl_cx2341x_is_dirty; | |
2035 | if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty; | |
2036 | qctrl.id = ciptr->v4l_id; | |
2037 | cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl); | |
2038 | if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) { | |
2039 | ciptr->set_value = ctrl_cx2341x_set; | |
2040 | } | |
2041 | strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name, | |
2042 | PVR2_CTLD_INFO_DESC_SIZE); | |
2043 | hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0; | |
2044 | ciptr->default_value = qctrl.default_value; | |
2045 | switch (qctrl.type) { | |
2046 | default: | |
2047 | case V4L2_CTRL_TYPE_INTEGER: | |
2048 | ciptr->type = pvr2_ctl_int; | |
2049 | ciptr->def.type_int.min_value = qctrl.minimum; | |
2050 | ciptr->def.type_int.max_value = qctrl.maximum; | |
2051 | break; | |
2052 | case V4L2_CTRL_TYPE_BOOLEAN: | |
2053 | ciptr->type = pvr2_ctl_bool; | |
2054 | break; | |
2055 | case V4L2_CTRL_TYPE_MENU: | |
2056 | ciptr->type = pvr2_ctl_enum; | |
2057 | ciptr->def.type_enum.value_names = | |
2058 | cx2341x_ctrl_get_menu(ciptr->v4l_id); | |
2059 | for (cnt1 = 0; | |
2060 | ciptr->def.type_enum.value_names[cnt1] != NULL; | |
2061 | cnt1++) { } | |
2062 | ciptr->def.type_enum.count = cnt1; | |
2063 | break; | |
2064 | } | |
2065 | cptr->info = ciptr; | |
2066 | } | |
d855497e MI |
2067 | |
2068 | // Initialize video standard enum dynamic control | |
2069 | cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM); | |
2070 | if (cptr) { | |
2071 | memcpy(&hdw->std_info_enum,cptr->info, | |
2072 | sizeof(hdw->std_info_enum)); | |
2073 | cptr->info = &hdw->std_info_enum; | |
2074 | ||
2075 | } | |
2076 | // Initialize control data regarding video standard masks | |
2077 | valid_std_mask = pvr2_std_get_usable(); | |
2078 | for (idx = 0; idx < 32; idx++) { | |
2079 | if (!(valid_std_mask & (1 << idx))) continue; | |
2080 | cnt1 = pvr2_std_id_to_str( | |
2081 | hdw->std_mask_names[idx], | |
2082 | sizeof(hdw->std_mask_names[idx])-1, | |
2083 | 1 << idx); | |
2084 | hdw->std_mask_names[idx][cnt1] = 0; | |
2085 | } | |
2086 | cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL); | |
2087 | if (cptr) { | |
2088 | memcpy(&hdw->std_info_avail,cptr->info, | |
2089 | sizeof(hdw->std_info_avail)); | |
2090 | cptr->info = &hdw->std_info_avail; | |
2091 | hdw->std_info_avail.def.type_bitmask.bit_names = | |
2092 | hdw->std_mask_ptrs; | |
2093 | hdw->std_info_avail.def.type_bitmask.valid_bits = | |
2094 | valid_std_mask; | |
2095 | } | |
2096 | cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR); | |
2097 | if (cptr) { | |
2098 | memcpy(&hdw->std_info_cur,cptr->info, | |
2099 | sizeof(hdw->std_info_cur)); | |
2100 | cptr->info = &hdw->std_info_cur; | |
2101 | hdw->std_info_cur.def.type_bitmask.bit_names = | |
2102 | hdw->std_mask_ptrs; | |
2103 | hdw->std_info_avail.def.type_bitmask.valid_bits = | |
2104 | valid_std_mask; | |
2105 | } | |
2106 | ||
2107 | hdw->eeprom_addr = -1; | |
2108 | hdw->unit_number = -1; | |
8079384e MI |
2109 | hdw->v4l_minor_number_video = -1; |
2110 | hdw->v4l_minor_number_vbi = -1; | |
fd5a75fe | 2111 | hdw->v4l_minor_number_radio = -1; |
d855497e MI |
2112 | hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL); |
2113 | if (!hdw->ctl_write_buffer) goto fail; | |
2114 | hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL); | |
2115 | if (!hdw->ctl_read_buffer) goto fail; | |
2116 | hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL); | |
2117 | if (!hdw->ctl_write_urb) goto fail; | |
2118 | hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL); | |
2119 | if (!hdw->ctl_read_urb) goto fail; | |
2120 | ||
2121 | down(&pvr2_unit_sem); do { | |
2122 | for (idx = 0; idx < PVR_NUM; idx++) { | |
2123 | if (unit_pointers[idx]) continue; | |
2124 | hdw->unit_number = idx; | |
2125 | unit_pointers[idx] = hdw; | |
2126 | break; | |
2127 | } | |
2128 | } while (0); up(&pvr2_unit_sem); | |
2129 | ||
2130 | cnt1 = 0; | |
2131 | cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2"); | |
2132 | cnt1 += cnt2; | |
2133 | if (hdw->unit_number >= 0) { | |
2134 | cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c", | |
2135 | ('a' + hdw->unit_number)); | |
2136 | cnt1 += cnt2; | |
2137 | } | |
2138 | if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1; | |
2139 | hdw->name[cnt1] = 0; | |
2140 | ||
2141 | pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s", | |
2142 | hdw->unit_number,hdw->name); | |
2143 | ||
2144 | hdw->tuner_type = -1; | |
2145 | hdw->flag_ok = !0; | |
2146 | /* Initialize the mask of subsystems that we will shut down when we | |
2147 | stop streaming. */ | |
2148 | hdw->subsys_stream_mask = PVR2_SUBSYS_RUN_ALL; | |
2149 | hdw->subsys_stream_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG); | |
2150 | ||
2151 | pvr2_trace(PVR2_TRACE_INIT,"subsys_stream_mask: 0x%lx", | |
2152 | hdw->subsys_stream_mask); | |
2153 | ||
2154 | hdw->usb_intf = intf; | |
2155 | hdw->usb_dev = interface_to_usbdev(intf); | |
2156 | ||
2157 | ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber; | |
2158 | usb_set_interface(hdw->usb_dev,ifnum,0); | |
2159 | ||
2160 | mutex_init(&hdw->ctl_lock_mutex); | |
2161 | mutex_init(&hdw->big_lock_mutex); | |
2162 | ||
2163 | return hdw; | |
2164 | fail: | |
2165 | if (hdw) { | |
5e55d2ce MK |
2166 | usb_free_urb(hdw->ctl_read_urb); |
2167 | usb_free_urb(hdw->ctl_write_urb); | |
22071a42 MK |
2168 | kfree(hdw->ctl_read_buffer); |
2169 | kfree(hdw->ctl_write_buffer); | |
2170 | kfree(hdw->controls); | |
2171 | kfree(hdw->mpeg_ctrl_info); | |
d855497e MI |
2172 | kfree(hdw); |
2173 | } | |
a0fd1cb1 | 2174 | return NULL; |
d855497e MI |
2175 | } |
2176 | ||
2177 | ||
2178 | /* Remove _all_ associations between this driver and the underlying USB | |
2179 | layer. */ | |
07e337ee | 2180 | static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw) |
d855497e MI |
2181 | { |
2182 | if (hdw->flag_disconnected) return; | |
2183 | pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw); | |
2184 | if (hdw->ctl_read_urb) { | |
2185 | usb_kill_urb(hdw->ctl_read_urb); | |
2186 | usb_free_urb(hdw->ctl_read_urb); | |
a0fd1cb1 | 2187 | hdw->ctl_read_urb = NULL; |
d855497e MI |
2188 | } |
2189 | if (hdw->ctl_write_urb) { | |
2190 | usb_kill_urb(hdw->ctl_write_urb); | |
2191 | usb_free_urb(hdw->ctl_write_urb); | |
a0fd1cb1 | 2192 | hdw->ctl_write_urb = NULL; |
d855497e MI |
2193 | } |
2194 | if (hdw->ctl_read_buffer) { | |
2195 | kfree(hdw->ctl_read_buffer); | |
a0fd1cb1 | 2196 | hdw->ctl_read_buffer = NULL; |
d855497e MI |
2197 | } |
2198 | if (hdw->ctl_write_buffer) { | |
2199 | kfree(hdw->ctl_write_buffer); | |
a0fd1cb1 | 2200 | hdw->ctl_write_buffer = NULL; |
d855497e MI |
2201 | } |
2202 | pvr2_hdw_render_useless_unlocked(hdw); | |
2203 | hdw->flag_disconnected = !0; | |
a0fd1cb1 MI |
2204 | hdw->usb_dev = NULL; |
2205 | hdw->usb_intf = NULL; | |
d855497e MI |
2206 | } |
2207 | ||
2208 | ||
2209 | /* Destroy hardware interaction structure */ | |
2210 | void pvr2_hdw_destroy(struct pvr2_hdw *hdw) | |
2211 | { | |
2212 | pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw); | |
2213 | if (hdw->fw_buffer) { | |
2214 | kfree(hdw->fw_buffer); | |
a0fd1cb1 | 2215 | hdw->fw_buffer = NULL; |
d855497e MI |
2216 | } |
2217 | if (hdw->vid_stream) { | |
2218 | pvr2_stream_destroy(hdw->vid_stream); | |
a0fd1cb1 | 2219 | hdw->vid_stream = NULL; |
d855497e | 2220 | } |
d855497e MI |
2221 | if (hdw->decoder_ctrl) { |
2222 | hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt); | |
2223 | } | |
2224 | pvr2_i2c_core_done(hdw); | |
2225 | pvr2_hdw_remove_usb_stuff(hdw); | |
2226 | down(&pvr2_unit_sem); do { | |
2227 | if ((hdw->unit_number >= 0) && | |
2228 | (hdw->unit_number < PVR_NUM) && | |
2229 | (unit_pointers[hdw->unit_number] == hdw)) { | |
a0fd1cb1 | 2230 | unit_pointers[hdw->unit_number] = NULL; |
d855497e MI |
2231 | } |
2232 | } while (0); up(&pvr2_unit_sem); | |
22071a42 MK |
2233 | kfree(hdw->controls); |
2234 | kfree(hdw->mpeg_ctrl_info); | |
2235 | kfree(hdw->std_defs); | |
2236 | kfree(hdw->std_enum_names); | |
d855497e MI |
2237 | kfree(hdw); |
2238 | } | |
2239 | ||
2240 | ||
2241 | int pvr2_hdw_init_ok(struct pvr2_hdw *hdw) | |
2242 | { | |
2243 | return hdw->flag_init_ok; | |
2244 | } | |
2245 | ||
2246 | ||
2247 | int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw) | |
2248 | { | |
2249 | return (hdw && hdw->flag_ok); | |
2250 | } | |
2251 | ||
2252 | ||
2253 | /* Called when hardware has been unplugged */ | |
2254 | void pvr2_hdw_disconnect(struct pvr2_hdw *hdw) | |
2255 | { | |
2256 | pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw); | |
2257 | LOCK_TAKE(hdw->big_lock); | |
2258 | LOCK_TAKE(hdw->ctl_lock); | |
2259 | pvr2_hdw_remove_usb_stuff(hdw); | |
2260 | LOCK_GIVE(hdw->ctl_lock); | |
2261 | LOCK_GIVE(hdw->big_lock); | |
2262 | } | |
2263 | ||
2264 | ||
2265 | // Attempt to autoselect an appropriate value for std_enum_cur given | |
2266 | // whatever is currently in std_mask_cur | |
07e337ee | 2267 | static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw) |
d855497e MI |
2268 | { |
2269 | unsigned int idx; | |
2270 | for (idx = 1; idx < hdw->std_enum_cnt; idx++) { | |
2271 | if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) { | |
2272 | hdw->std_enum_cur = idx; | |
2273 | return; | |
2274 | } | |
2275 | } | |
2276 | hdw->std_enum_cur = 0; | |
2277 | } | |
2278 | ||
2279 | ||
2280 | // Calculate correct set of enumerated standards based on currently known | |
2281 | // set of available standards bits. | |
07e337ee | 2282 | static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw) |
d855497e MI |
2283 | { |
2284 | struct v4l2_standard *newstd; | |
2285 | unsigned int std_cnt; | |
2286 | unsigned int idx; | |
2287 | ||
2288 | newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail); | |
2289 | ||
2290 | if (hdw->std_defs) { | |
2291 | kfree(hdw->std_defs); | |
a0fd1cb1 | 2292 | hdw->std_defs = NULL; |
d855497e MI |
2293 | } |
2294 | hdw->std_enum_cnt = 0; | |
2295 | if (hdw->std_enum_names) { | |
2296 | kfree(hdw->std_enum_names); | |
a0fd1cb1 | 2297 | hdw->std_enum_names = NULL; |
d855497e MI |
2298 | } |
2299 | ||
2300 | if (!std_cnt) { | |
2301 | pvr2_trace( | |
2302 | PVR2_TRACE_ERROR_LEGS, | |
2303 | "WARNING: Failed to identify any viable standards"); | |
2304 | } | |
2305 | hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL); | |
2306 | hdw->std_enum_names[0] = "none"; | |
2307 | for (idx = 0; idx < std_cnt; idx++) { | |
2308 | hdw->std_enum_names[idx+1] = | |
2309 | newstd[idx].name; | |
2310 | } | |
2311 | // Set up the dynamic control for this standard | |
2312 | hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names; | |
2313 | hdw->std_info_enum.def.type_enum.count = std_cnt+1; | |
2314 | hdw->std_defs = newstd; | |
2315 | hdw->std_enum_cnt = std_cnt+1; | |
2316 | hdw->std_enum_cur = 0; | |
2317 | hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail; | |
2318 | } | |
2319 | ||
2320 | ||
2321 | int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw, | |
2322 | struct v4l2_standard *std, | |
2323 | unsigned int idx) | |
2324 | { | |
2325 | int ret = -EINVAL; | |
2326 | if (!idx) return ret; | |
2327 | LOCK_TAKE(hdw->big_lock); do { | |
2328 | if (idx >= hdw->std_enum_cnt) break; | |
2329 | idx--; | |
2330 | memcpy(std,hdw->std_defs+idx,sizeof(*std)); | |
2331 | ret = 0; | |
2332 | } while (0); LOCK_GIVE(hdw->big_lock); | |
2333 | return ret; | |
2334 | } | |
2335 | ||
2336 | ||
2337 | /* Get the number of defined controls */ | |
2338 | unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw) | |
2339 | { | |
c05c0462 | 2340 | return hdw->control_cnt; |
d855497e MI |
2341 | } |
2342 | ||
2343 | ||
2344 | /* Retrieve a control handle given its index (0..count-1) */ | |
2345 | struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw, | |
2346 | unsigned int idx) | |
2347 | { | |
a0fd1cb1 | 2348 | if (idx >= hdw->control_cnt) return NULL; |
d855497e MI |
2349 | return hdw->controls + idx; |
2350 | } | |
2351 | ||
2352 | ||
2353 | /* Retrieve a control handle given its index (0..count-1) */ | |
2354 | struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw, | |
2355 | unsigned int ctl_id) | |
2356 | { | |
2357 | struct pvr2_ctrl *cptr; | |
2358 | unsigned int idx; | |
2359 | int i; | |
2360 | ||
2361 | /* This could be made a lot more efficient, but for now... */ | |
c05c0462 | 2362 | for (idx = 0; idx < hdw->control_cnt; idx++) { |
d855497e MI |
2363 | cptr = hdw->controls + idx; |
2364 | i = cptr->info->internal_id; | |
2365 | if (i && (i == ctl_id)) return cptr; | |
2366 | } | |
a0fd1cb1 | 2367 | return NULL; |
d855497e MI |
2368 | } |
2369 | ||
2370 | ||
a761f431 | 2371 | /* Given a V4L ID, retrieve the control structure associated with it. */ |
d855497e MI |
2372 | struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id) |
2373 | { | |
2374 | struct pvr2_ctrl *cptr; | |
2375 | unsigned int idx; | |
2376 | int i; | |
2377 | ||
2378 | /* This could be made a lot more efficient, but for now... */ | |
c05c0462 | 2379 | for (idx = 0; idx < hdw->control_cnt; idx++) { |
d855497e MI |
2380 | cptr = hdw->controls + idx; |
2381 | i = cptr->info->v4l_id; | |
2382 | if (i && (i == ctl_id)) return cptr; | |
2383 | } | |
a0fd1cb1 | 2384 | return NULL; |
d855497e MI |
2385 | } |
2386 | ||
2387 | ||
a761f431 MI |
2388 | /* Given a V4L ID for its immediate predecessor, retrieve the control |
2389 | structure associated with it. */ | |
2390 | struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw, | |
2391 | unsigned int ctl_id) | |
2392 | { | |
2393 | struct pvr2_ctrl *cptr,*cp2; | |
2394 | unsigned int idx; | |
2395 | int i; | |
2396 | ||
2397 | /* This could be made a lot more efficient, but for now... */ | |
a0fd1cb1 | 2398 | cp2 = NULL; |
a761f431 MI |
2399 | for (idx = 0; idx < hdw->control_cnt; idx++) { |
2400 | cptr = hdw->controls + idx; | |
2401 | i = cptr->info->v4l_id; | |
2402 | if (!i) continue; | |
2403 | if (i <= ctl_id) continue; | |
2404 | if (cp2 && (cp2->info->v4l_id < i)) continue; | |
2405 | cp2 = cptr; | |
2406 | } | |
2407 | return cp2; | |
a0fd1cb1 | 2408 | return NULL; |
a761f431 MI |
2409 | } |
2410 | ||
2411 | ||
d855497e MI |
2412 | static const char *get_ctrl_typename(enum pvr2_ctl_type tp) |
2413 | { | |
2414 | switch (tp) { | |
2415 | case pvr2_ctl_int: return "integer"; | |
2416 | case pvr2_ctl_enum: return "enum"; | |
33213963 | 2417 | case pvr2_ctl_bool: return "boolean"; |
d855497e MI |
2418 | case pvr2_ctl_bitmask: return "bitmask"; |
2419 | } | |
2420 | return ""; | |
2421 | } | |
2422 | ||
2423 | ||
2424 | /* Commit all control changes made up to this point. Subsystems can be | |
2425 | indirectly affected by these changes. For a given set of things being | |
2426 | committed, we'll clear the affected subsystem bits and then once we're | |
2427 | done committing everything we'll make a request to restore the subsystem | |
2428 | state(s) back to their previous value before this function was called. | |
2429 | Thus we can automatically reconfigure affected pieces of the driver as | |
2430 | controls are changed. */ | |
07e337ee | 2431 | static int pvr2_hdw_commit_ctl_internal(struct pvr2_hdw *hdw) |
d855497e MI |
2432 | { |
2433 | unsigned long saved_subsys_mask = hdw->subsys_enabled_mask; | |
2434 | unsigned long stale_subsys_mask = 0; | |
2435 | unsigned int idx; | |
2436 | struct pvr2_ctrl *cptr; | |
2437 | int value; | |
2438 | int commit_flag = 0; | |
2439 | char buf[100]; | |
2440 | unsigned int bcnt,ccnt; | |
2441 | ||
c05c0462 | 2442 | for (idx = 0; idx < hdw->control_cnt; idx++) { |
d855497e MI |
2443 | cptr = hdw->controls + idx; |
2444 | if (cptr->info->is_dirty == 0) continue; | |
2445 | if (!cptr->info->is_dirty(cptr)) continue; | |
2446 | if (!commit_flag) { | |
2447 | commit_flag = !0; | |
2448 | } | |
2449 | ||
2450 | bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ", | |
2451 | cptr->info->name); | |
2452 | value = 0; | |
2453 | cptr->info->get_value(cptr,&value); | |
2454 | pvr2_ctrl_value_to_sym_internal(cptr,~0,value, | |
2455 | buf+bcnt, | |
2456 | sizeof(buf)-bcnt,&ccnt); | |
2457 | bcnt += ccnt; | |
2458 | bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>", | |
2459 | get_ctrl_typename(cptr->info->type)); | |
2460 | pvr2_trace(PVR2_TRACE_CTL, | |
2461 | "/*--TRACE_COMMIT--*/ %.*s", | |
2462 | bcnt,buf); | |
2463 | } | |
2464 | ||
2465 | if (!commit_flag) { | |
2466 | /* Nothing has changed */ | |
2467 | return 0; | |
2468 | } | |
2469 | ||
2470 | /* When video standard changes, reset the hres and vres values - | |
2471 | but if the user has pending changes there, then let the changes | |
2472 | take priority. */ | |
2473 | if (hdw->std_dirty) { | |
2474 | /* Rewrite the vertical resolution to be appropriate to the | |
2475 | video standard that has been selected. */ | |
2476 | int nvres; | |
2477 | if (hdw->std_mask_cur & V4L2_STD_525_60) { | |
2478 | nvres = 480; | |
2479 | } else { | |
2480 | nvres = 576; | |
2481 | } | |
2482 | if (nvres != hdw->res_ver_val) { | |
2483 | hdw->res_ver_val = nvres; | |
2484 | hdw->res_ver_dirty = !0; | |
2485 | } | |
d855497e MI |
2486 | } |
2487 | ||
2488 | if (hdw->std_dirty || | |
434449f4 MI |
2489 | hdw->enc_stale || |
2490 | hdw->srate_dirty || | |
2491 | hdw->res_ver_dirty || | |
2492 | hdw->res_hor_dirty || | |
b46cfa80 | 2493 | 0) { |
d855497e MI |
2494 | /* If any of this changes, then the encoder needs to be |
2495 | reconfigured, and we need to reset the stream. */ | |
2496 | stale_subsys_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG); | |
d855497e MI |
2497 | } |
2498 | ||
275b2e28 PK |
2499 | if (hdw->input_dirty) { |
2500 | /* pk: If input changes to or from radio, then the encoder | |
2501 | needs to be restarted (for ENC_MUTE_VIDEO to work) */ | |
2502 | stale_subsys_mask |= (1<<PVR2_SUBSYS_B_ENC_RUN); | |
2503 | } | |
2504 | ||
2505 | ||
b30d2441 MI |
2506 | if (hdw->srate_dirty) { |
2507 | /* Write new sample rate into control structure since | |
2508 | * the master copy is stale. We must track srate | |
2509 | * separate from the mpeg control structure because | |
2510 | * other logic also uses this value. */ | |
2511 | struct v4l2_ext_controls cs; | |
2512 | struct v4l2_ext_control c1; | |
2513 | memset(&cs,0,sizeof(cs)); | |
2514 | memset(&c1,0,sizeof(c1)); | |
2515 | cs.controls = &c1; | |
2516 | cs.count = 1; | |
2517 | c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ; | |
2518 | c1.value = hdw->srate_val; | |
2519 | cx2341x_ext_ctrls(&hdw->enc_ctl_state,&cs,VIDIOC_S_EXT_CTRLS); | |
2520 | } | |
c05c0462 | 2521 | |
d855497e MI |
2522 | /* Scan i2c core at this point - before we clear all the dirty |
2523 | bits. Various parts of the i2c core will notice dirty bits as | |
2524 | appropriate and arrange to broadcast or directly send updates to | |
2525 | the client drivers in order to keep everything in sync */ | |
2526 | pvr2_i2c_core_check_stale(hdw); | |
2527 | ||
c05c0462 | 2528 | for (idx = 0; idx < hdw->control_cnt; idx++) { |
d855497e MI |
2529 | cptr = hdw->controls + idx; |
2530 | if (!cptr->info->clear_dirty) continue; | |
2531 | cptr->info->clear_dirty(cptr); | |
2532 | } | |
2533 | ||
2534 | /* Now execute i2c core update */ | |
2535 | pvr2_i2c_core_sync(hdw); | |
2536 | ||
2537 | pvr2_hdw_subsys_bit_chg_no_lock(hdw,stale_subsys_mask,0); | |
2538 | pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,saved_subsys_mask); | |
2539 | ||
2540 | return 0; | |
2541 | } | |
2542 | ||
2543 | ||
2544 | int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw) | |
2545 | { | |
2546 | LOCK_TAKE(hdw->big_lock); do { | |
2547 | pvr2_hdw_commit_ctl_internal(hdw); | |
2548 | } while (0); LOCK_GIVE(hdw->big_lock); | |
2549 | return 0; | |
2550 | } | |
2551 | ||
2552 | ||
2553 | void pvr2_hdw_poll(struct pvr2_hdw *hdw) | |
2554 | { | |
2555 | LOCK_TAKE(hdw->big_lock); do { | |
2556 | pvr2_i2c_core_sync(hdw); | |
2557 | } while (0); LOCK_GIVE(hdw->big_lock); | |
2558 | } | |
2559 | ||
2560 | ||
2561 | void pvr2_hdw_setup_poll_trigger(struct pvr2_hdw *hdw, | |
2562 | void (*func)(void *), | |
2563 | void *data) | |
2564 | { | |
2565 | LOCK_TAKE(hdw->big_lock); do { | |
2566 | hdw->poll_trigger_func = func; | |
2567 | hdw->poll_trigger_data = data; | |
2568 | } while (0); LOCK_GIVE(hdw->big_lock); | |
2569 | } | |
2570 | ||
2571 | ||
2572 | void pvr2_hdw_poll_trigger_unlocked(struct pvr2_hdw *hdw) | |
2573 | { | |
2574 | if (hdw->poll_trigger_func) { | |
2575 | hdw->poll_trigger_func(hdw->poll_trigger_data); | |
2576 | } | |
2577 | } | |
2578 | ||
d855497e MI |
2579 | /* Return name for this driver instance */ |
2580 | const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw) | |
2581 | { | |
2582 | return hdw->name; | |
2583 | } | |
2584 | ||
2585 | ||
d855497e MI |
2586 | int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw) |
2587 | { | |
2588 | int result; | |
2589 | LOCK_TAKE(hdw->ctl_lock); do { | |
2590 | hdw->cmd_buffer[0] = 0x0b; | |
2591 | result = pvr2_send_request(hdw, | |
2592 | hdw->cmd_buffer,1, | |
2593 | hdw->cmd_buffer,1); | |
2594 | if (result < 0) break; | |
2595 | result = (hdw->cmd_buffer[0] != 0); | |
2596 | } while(0); LOCK_GIVE(hdw->ctl_lock); | |
2597 | return result; | |
2598 | } | |
2599 | ||
2600 | ||
18103c57 MI |
2601 | /* Execute poll of tuner status */ |
2602 | void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw) | |
d855497e | 2603 | { |
d855497e | 2604 | LOCK_TAKE(hdw->big_lock); do { |
18103c57 | 2605 | pvr2_i2c_core_status_poll(hdw); |
d855497e | 2606 | } while (0); LOCK_GIVE(hdw->big_lock); |
18103c57 MI |
2607 | } |
2608 | ||
2609 | ||
2610 | /* Return information about the tuner */ | |
2611 | int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp) | |
2612 | { | |
2613 | LOCK_TAKE(hdw->big_lock); do { | |
2614 | if (hdw->tuner_signal_stale) { | |
2615 | pvr2_i2c_core_status_poll(hdw); | |
2616 | } | |
2617 | memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner)); | |
2618 | } while (0); LOCK_GIVE(hdw->big_lock); | |
2619 | return 0; | |
d855497e MI |
2620 | } |
2621 | ||
2622 | ||
2623 | /* Get handle to video output stream */ | |
2624 | struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp) | |
2625 | { | |
2626 | return hp->vid_stream; | |
2627 | } | |
2628 | ||
2629 | ||
2630 | void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw) | |
2631 | { | |
4f1a3e5b | 2632 | int nr = pvr2_hdw_get_unit_number(hdw); |
d855497e MI |
2633 | LOCK_TAKE(hdw->big_lock); do { |
2634 | hdw->log_requested = !0; | |
4f1a3e5b | 2635 | printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr); |
d855497e MI |
2636 | pvr2_i2c_core_check_stale(hdw); |
2637 | hdw->log_requested = 0; | |
2638 | pvr2_i2c_core_sync(hdw); | |
b30d2441 | 2639 | pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:"); |
99eb44fe | 2640 | cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2"); |
4f1a3e5b | 2641 | printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr); |
d855497e MI |
2642 | } while (0); LOCK_GIVE(hdw->big_lock); |
2643 | } | |
2644 | ||
2645 | void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw, int enable_flag) | |
2646 | { | |
2647 | int ret; | |
2648 | u16 address; | |
2649 | unsigned int pipe; | |
2650 | LOCK_TAKE(hdw->big_lock); do { | |
2651 | if ((hdw->fw_buffer == 0) == !enable_flag) break; | |
2652 | ||
2653 | if (!enable_flag) { | |
2654 | pvr2_trace(PVR2_TRACE_FIRMWARE, | |
2655 | "Cleaning up after CPU firmware fetch"); | |
2656 | kfree(hdw->fw_buffer); | |
a0fd1cb1 | 2657 | hdw->fw_buffer = NULL; |
d855497e MI |
2658 | hdw->fw_size = 0; |
2659 | /* Now release the CPU. It will disconnect and | |
2660 | reconnect later. */ | |
2661 | pvr2_hdw_cpureset_assert(hdw,0); | |
2662 | break; | |
2663 | } | |
2664 | ||
2665 | pvr2_trace(PVR2_TRACE_FIRMWARE, | |
2666 | "Preparing to suck out CPU firmware"); | |
2667 | hdw->fw_size = 0x2000; | |
2668 | hdw->fw_buffer = kmalloc(hdw->fw_size,GFP_KERNEL); | |
2669 | if (!hdw->fw_buffer) { | |
2670 | hdw->fw_size = 0; | |
2671 | break; | |
2672 | } | |
2673 | ||
2674 | memset(hdw->fw_buffer,0,hdw->fw_size); | |
2675 | ||
2676 | /* We have to hold the CPU during firmware upload. */ | |
2677 | pvr2_hdw_cpureset_assert(hdw,1); | |
2678 | ||
2679 | /* download the firmware from address 0000-1fff in 2048 | |
2680 | (=0x800) bytes chunk. */ | |
2681 | ||
2682 | pvr2_trace(PVR2_TRACE_FIRMWARE,"Grabbing CPU firmware"); | |
2683 | pipe = usb_rcvctrlpipe(hdw->usb_dev, 0); | |
2684 | for(address = 0; address < hdw->fw_size; address += 0x800) { | |
2685 | ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0xc0, | |
2686 | address,0, | |
2687 | hdw->fw_buffer+address,0x800,HZ); | |
2688 | if (ret < 0) break; | |
2689 | } | |
2690 | ||
2691 | pvr2_trace(PVR2_TRACE_FIRMWARE,"Done grabbing CPU firmware"); | |
2692 | ||
2693 | } while (0); LOCK_GIVE(hdw->big_lock); | |
2694 | } | |
2695 | ||
2696 | ||
2697 | /* Return true if we're in a mode for retrieval CPU firmware */ | |
2698 | int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw) | |
2699 | { | |
2700 | return hdw->fw_buffer != 0; | |
2701 | } | |
2702 | ||
2703 | ||
2704 | int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs, | |
2705 | char *buf,unsigned int cnt) | |
2706 | { | |
2707 | int ret = -EINVAL; | |
2708 | LOCK_TAKE(hdw->big_lock); do { | |
2709 | if (!buf) break; | |
2710 | if (!cnt) break; | |
2711 | ||
2712 | if (!hdw->fw_buffer) { | |
2713 | ret = -EIO; | |
2714 | break; | |
2715 | } | |
2716 | ||
2717 | if (offs >= hdw->fw_size) { | |
2718 | pvr2_trace(PVR2_TRACE_FIRMWARE, | |
2719 | "Read firmware data offs=%d EOF", | |
2720 | offs); | |
2721 | ret = 0; | |
2722 | break; | |
2723 | } | |
2724 | ||
2725 | if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs; | |
2726 | ||
2727 | memcpy(buf,hdw->fw_buffer+offs,cnt); | |
2728 | ||
2729 | pvr2_trace(PVR2_TRACE_FIRMWARE, | |
2730 | "Read firmware data offs=%d cnt=%d", | |
2731 | offs,cnt); | |
2732 | ret = cnt; | |
2733 | } while (0); LOCK_GIVE(hdw->big_lock); | |
2734 | ||
2735 | return ret; | |
2736 | } | |
2737 | ||
2738 | ||
fd5a75fe | 2739 | int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw, |
8079384e | 2740 | enum pvr2_v4l_type index) |
d855497e | 2741 | { |
fd5a75fe | 2742 | switch (index) { |
8079384e MI |
2743 | case pvr2_v4l_type_video: return hdw->v4l_minor_number_video; |
2744 | case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi; | |
2745 | case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio; | |
fd5a75fe MI |
2746 | default: return -1; |
2747 | } | |
d855497e MI |
2748 | } |
2749 | ||
2750 | ||
2fdf3d9c | 2751 | /* Store a v4l minor device number */ |
fd5a75fe | 2752 | void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw, |
8079384e | 2753 | enum pvr2_v4l_type index,int v) |
d855497e | 2754 | { |
fd5a75fe | 2755 | switch (index) { |
8079384e MI |
2756 | case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v; |
2757 | case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v; | |
2758 | case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v; | |
fd5a75fe MI |
2759 | default: break; |
2760 | } | |
d855497e MI |
2761 | } |
2762 | ||
2763 | ||
7d12e780 | 2764 | static void pvr2_ctl_write_complete(struct urb *urb) |
d855497e MI |
2765 | { |
2766 | struct pvr2_hdw *hdw = urb->context; | |
2767 | hdw->ctl_write_pend_flag = 0; | |
2768 | if (hdw->ctl_read_pend_flag) return; | |
2769 | complete(&hdw->ctl_done); | |
2770 | } | |
2771 | ||
2772 | ||
7d12e780 | 2773 | static void pvr2_ctl_read_complete(struct urb *urb) |
d855497e MI |
2774 | { |
2775 | struct pvr2_hdw *hdw = urb->context; | |
2776 | hdw->ctl_read_pend_flag = 0; | |
2777 | if (hdw->ctl_write_pend_flag) return; | |
2778 | complete(&hdw->ctl_done); | |
2779 | } | |
2780 | ||
2781 | ||
2782 | static void pvr2_ctl_timeout(unsigned long data) | |
2783 | { | |
2784 | struct pvr2_hdw *hdw = (struct pvr2_hdw *)data; | |
2785 | if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) { | |
2786 | hdw->ctl_timeout_flag = !0; | |
5e55d2ce | 2787 | if (hdw->ctl_write_pend_flag) |
d855497e | 2788 | usb_unlink_urb(hdw->ctl_write_urb); |
5e55d2ce | 2789 | if (hdw->ctl_read_pend_flag) |
d855497e | 2790 | usb_unlink_urb(hdw->ctl_read_urb); |
d855497e MI |
2791 | } |
2792 | } | |
2793 | ||
2794 | ||
e61b6fc5 MI |
2795 | /* Issue a command and get a response from the device. This extended |
2796 | version includes a probe flag (which if set means that device errors | |
2797 | should not be logged or treated as fatal) and a timeout in jiffies. | |
2798 | This can be used to non-lethally probe the health of endpoint 1. */ | |
07e337ee AB |
2799 | static int pvr2_send_request_ex(struct pvr2_hdw *hdw, |
2800 | unsigned int timeout,int probe_fl, | |
2801 | void *write_data,unsigned int write_len, | |
2802 | void *read_data,unsigned int read_len) | |
d855497e MI |
2803 | { |
2804 | unsigned int idx; | |
2805 | int status = 0; | |
2806 | struct timer_list timer; | |
2807 | if (!hdw->ctl_lock_held) { | |
2808 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
2809 | "Attempted to execute control transfer" | |
2810 | " without lock!!"); | |
2811 | return -EDEADLK; | |
2812 | } | |
2813 | if ((!hdw->flag_ok) && !probe_fl) { | |
2814 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
2815 | "Attempted to execute control transfer" | |
2816 | " when device not ok"); | |
2817 | return -EIO; | |
2818 | } | |
2819 | if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) { | |
2820 | if (!probe_fl) { | |
2821 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
2822 | "Attempted to execute control transfer" | |
2823 | " when USB is disconnected"); | |
2824 | } | |
2825 | return -ENOTTY; | |
2826 | } | |
2827 | ||
2828 | /* Ensure that we have sane parameters */ | |
2829 | if (!write_data) write_len = 0; | |
2830 | if (!read_data) read_len = 0; | |
2831 | if (write_len > PVR2_CTL_BUFFSIZE) { | |
2832 | pvr2_trace( | |
2833 | PVR2_TRACE_ERROR_LEGS, | |
2834 | "Attempted to execute %d byte" | |
2835 | " control-write transfer (limit=%d)", | |
2836 | write_len,PVR2_CTL_BUFFSIZE); | |
2837 | return -EINVAL; | |
2838 | } | |
2839 | if (read_len > PVR2_CTL_BUFFSIZE) { | |
2840 | pvr2_trace( | |
2841 | PVR2_TRACE_ERROR_LEGS, | |
2842 | "Attempted to execute %d byte" | |
2843 | " control-read transfer (limit=%d)", | |
2844 | write_len,PVR2_CTL_BUFFSIZE); | |
2845 | return -EINVAL; | |
2846 | } | |
2847 | if ((!write_len) && (!read_len)) { | |
2848 | pvr2_trace( | |
2849 | PVR2_TRACE_ERROR_LEGS, | |
2850 | "Attempted to execute null control transfer?"); | |
2851 | return -EINVAL; | |
2852 | } | |
2853 | ||
2854 | ||
2855 | hdw->cmd_debug_state = 1; | |
2856 | if (write_len) { | |
2857 | hdw->cmd_debug_code = ((unsigned char *)write_data)[0]; | |
2858 | } else { | |
2859 | hdw->cmd_debug_code = 0; | |
2860 | } | |
2861 | hdw->cmd_debug_write_len = write_len; | |
2862 | hdw->cmd_debug_read_len = read_len; | |
2863 | ||
2864 | /* Initialize common stuff */ | |
2865 | init_completion(&hdw->ctl_done); | |
2866 | hdw->ctl_timeout_flag = 0; | |
2867 | hdw->ctl_write_pend_flag = 0; | |
2868 | hdw->ctl_read_pend_flag = 0; | |
2869 | init_timer(&timer); | |
2870 | timer.expires = jiffies + timeout; | |
2871 | timer.data = (unsigned long)hdw; | |
2872 | timer.function = pvr2_ctl_timeout; | |
2873 | ||
2874 | if (write_len) { | |
2875 | hdw->cmd_debug_state = 2; | |
2876 | /* Transfer write data to internal buffer */ | |
2877 | for (idx = 0; idx < write_len; idx++) { | |
2878 | hdw->ctl_write_buffer[idx] = | |
2879 | ((unsigned char *)write_data)[idx]; | |
2880 | } | |
2881 | /* Initiate a write request */ | |
2882 | usb_fill_bulk_urb(hdw->ctl_write_urb, | |
2883 | hdw->usb_dev, | |
2884 | usb_sndbulkpipe(hdw->usb_dev, | |
2885 | PVR2_CTL_WRITE_ENDPOINT), | |
2886 | hdw->ctl_write_buffer, | |
2887 | write_len, | |
2888 | pvr2_ctl_write_complete, | |
2889 | hdw); | |
2890 | hdw->ctl_write_urb->actual_length = 0; | |
2891 | hdw->ctl_write_pend_flag = !0; | |
2892 | status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL); | |
2893 | if (status < 0) { | |
2894 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
2895 | "Failed to submit write-control" | |
2896 | " URB status=%d",status); | |
2897 | hdw->ctl_write_pend_flag = 0; | |
2898 | goto done; | |
2899 | } | |
2900 | } | |
2901 | ||
2902 | if (read_len) { | |
2903 | hdw->cmd_debug_state = 3; | |
2904 | memset(hdw->ctl_read_buffer,0x43,read_len); | |
2905 | /* Initiate a read request */ | |
2906 | usb_fill_bulk_urb(hdw->ctl_read_urb, | |
2907 | hdw->usb_dev, | |
2908 | usb_rcvbulkpipe(hdw->usb_dev, | |
2909 | PVR2_CTL_READ_ENDPOINT), | |
2910 | hdw->ctl_read_buffer, | |
2911 | read_len, | |
2912 | pvr2_ctl_read_complete, | |
2913 | hdw); | |
2914 | hdw->ctl_read_urb->actual_length = 0; | |
2915 | hdw->ctl_read_pend_flag = !0; | |
2916 | status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL); | |
2917 | if (status < 0) { | |
2918 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
2919 | "Failed to submit read-control" | |
2920 | " URB status=%d",status); | |
2921 | hdw->ctl_read_pend_flag = 0; | |
2922 | goto done; | |
2923 | } | |
2924 | } | |
2925 | ||
2926 | /* Start timer */ | |
2927 | add_timer(&timer); | |
2928 | ||
2929 | /* Now wait for all I/O to complete */ | |
2930 | hdw->cmd_debug_state = 4; | |
2931 | while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) { | |
2932 | wait_for_completion(&hdw->ctl_done); | |
2933 | } | |
2934 | hdw->cmd_debug_state = 5; | |
2935 | ||
2936 | /* Stop timer */ | |
2937 | del_timer_sync(&timer); | |
2938 | ||
2939 | hdw->cmd_debug_state = 6; | |
2940 | status = 0; | |
2941 | ||
2942 | if (hdw->ctl_timeout_flag) { | |
2943 | status = -ETIMEDOUT; | |
2944 | if (!probe_fl) { | |
2945 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
2946 | "Timed out control-write"); | |
2947 | } | |
2948 | goto done; | |
2949 | } | |
2950 | ||
2951 | if (write_len) { | |
2952 | /* Validate results of write request */ | |
2953 | if ((hdw->ctl_write_urb->status != 0) && | |
2954 | (hdw->ctl_write_urb->status != -ENOENT) && | |
2955 | (hdw->ctl_write_urb->status != -ESHUTDOWN) && | |
2956 | (hdw->ctl_write_urb->status != -ECONNRESET)) { | |
2957 | /* USB subsystem is reporting some kind of failure | |
2958 | on the write */ | |
2959 | status = hdw->ctl_write_urb->status; | |
2960 | if (!probe_fl) { | |
2961 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
2962 | "control-write URB failure," | |
2963 | " status=%d", | |
2964 | status); | |
2965 | } | |
2966 | goto done; | |
2967 | } | |
2968 | if (hdw->ctl_write_urb->actual_length < write_len) { | |
2969 | /* Failed to write enough data */ | |
2970 | status = -EIO; | |
2971 | if (!probe_fl) { | |
2972 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
2973 | "control-write URB short," | |
2974 | " expected=%d got=%d", | |
2975 | write_len, | |
2976 | hdw->ctl_write_urb->actual_length); | |
2977 | } | |
2978 | goto done; | |
2979 | } | |
2980 | } | |
2981 | if (read_len) { | |
2982 | /* Validate results of read request */ | |
2983 | if ((hdw->ctl_read_urb->status != 0) && | |
2984 | (hdw->ctl_read_urb->status != -ENOENT) && | |
2985 | (hdw->ctl_read_urb->status != -ESHUTDOWN) && | |
2986 | (hdw->ctl_read_urb->status != -ECONNRESET)) { | |
2987 | /* USB subsystem is reporting some kind of failure | |
2988 | on the read */ | |
2989 | status = hdw->ctl_read_urb->status; | |
2990 | if (!probe_fl) { | |
2991 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
2992 | "control-read URB failure," | |
2993 | " status=%d", | |
2994 | status); | |
2995 | } | |
2996 | goto done; | |
2997 | } | |
2998 | if (hdw->ctl_read_urb->actual_length < read_len) { | |
2999 | /* Failed to read enough data */ | |
3000 | status = -EIO; | |
3001 | if (!probe_fl) { | |
3002 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
3003 | "control-read URB short," | |
3004 | " expected=%d got=%d", | |
3005 | read_len, | |
3006 | hdw->ctl_read_urb->actual_length); | |
3007 | } | |
3008 | goto done; | |
3009 | } | |
3010 | /* Transfer retrieved data out from internal buffer */ | |
3011 | for (idx = 0; idx < read_len; idx++) { | |
3012 | ((unsigned char *)read_data)[idx] = | |
3013 | hdw->ctl_read_buffer[idx]; | |
3014 | } | |
3015 | } | |
3016 | ||
3017 | done: | |
3018 | ||
3019 | hdw->cmd_debug_state = 0; | |
3020 | if ((status < 0) && (!probe_fl)) { | |
3021 | pvr2_hdw_render_useless_unlocked(hdw); | |
3022 | } | |
3023 | return status; | |
3024 | } | |
3025 | ||
3026 | ||
3027 | int pvr2_send_request(struct pvr2_hdw *hdw, | |
3028 | void *write_data,unsigned int write_len, | |
3029 | void *read_data,unsigned int read_len) | |
3030 | { | |
3031 | return pvr2_send_request_ex(hdw,HZ*4,0, | |
3032 | write_data,write_len, | |
3033 | read_data,read_len); | |
3034 | } | |
3035 | ||
3036 | int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data) | |
3037 | { | |
3038 | int ret; | |
3039 | ||
3040 | LOCK_TAKE(hdw->ctl_lock); | |
3041 | ||
3042 | hdw->cmd_buffer[0] = 0x04; /* write register prefix */ | |
3043 | PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data); | |
3044 | hdw->cmd_buffer[5] = 0; | |
3045 | hdw->cmd_buffer[6] = (reg >> 8) & 0xff; | |
3046 | hdw->cmd_buffer[7] = reg & 0xff; | |
3047 | ||
3048 | ||
3049 | ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0); | |
3050 | ||
3051 | LOCK_GIVE(hdw->ctl_lock); | |
3052 | ||
3053 | return ret; | |
3054 | } | |
3055 | ||
3056 | ||
07e337ee | 3057 | static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data) |
d855497e MI |
3058 | { |
3059 | int ret = 0; | |
3060 | ||
3061 | LOCK_TAKE(hdw->ctl_lock); | |
3062 | ||
3063 | hdw->cmd_buffer[0] = 0x05; /* read register prefix */ | |
3064 | hdw->cmd_buffer[1] = 0; | |
3065 | hdw->cmd_buffer[2] = 0; | |
3066 | hdw->cmd_buffer[3] = 0; | |
3067 | hdw->cmd_buffer[4] = 0; | |
3068 | hdw->cmd_buffer[5] = 0; | |
3069 | hdw->cmd_buffer[6] = (reg >> 8) & 0xff; | |
3070 | hdw->cmd_buffer[7] = reg & 0xff; | |
3071 | ||
3072 | ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4); | |
3073 | *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0); | |
3074 | ||
3075 | LOCK_GIVE(hdw->ctl_lock); | |
3076 | ||
3077 | return ret; | |
3078 | } | |
3079 | ||
3080 | ||
07e337ee | 3081 | static int pvr2_write_u16(struct pvr2_hdw *hdw, u16 data, int res) |
d855497e MI |
3082 | { |
3083 | int ret; | |
3084 | ||
3085 | LOCK_TAKE(hdw->ctl_lock); | |
3086 | ||
3087 | hdw->cmd_buffer[0] = (data >> 8) & 0xff; | |
3088 | hdw->cmd_buffer[1] = data & 0xff; | |
3089 | ||
3090 | ret = pvr2_send_request(hdw, hdw->cmd_buffer, 2, hdw->cmd_buffer, res); | |
3091 | ||
3092 | LOCK_GIVE(hdw->ctl_lock); | |
3093 | ||
3094 | return ret; | |
3095 | } | |
3096 | ||
3097 | ||
07e337ee | 3098 | static int pvr2_write_u8(struct pvr2_hdw *hdw, u8 data, int res) |
d855497e MI |
3099 | { |
3100 | int ret; | |
3101 | ||
3102 | LOCK_TAKE(hdw->ctl_lock); | |
3103 | ||
3104 | hdw->cmd_buffer[0] = data; | |
3105 | ||
3106 | ret = pvr2_send_request(hdw, hdw->cmd_buffer, 1, hdw->cmd_buffer, res); | |
3107 | ||
3108 | LOCK_GIVE(hdw->ctl_lock); | |
3109 | ||
3110 | return ret; | |
3111 | } | |
3112 | ||
3113 | ||
07e337ee | 3114 | static void pvr2_hdw_render_useless_unlocked(struct pvr2_hdw *hdw) |
d855497e MI |
3115 | { |
3116 | if (!hdw->flag_ok) return; | |
3117 | pvr2_trace(PVR2_TRACE_INIT,"render_useless"); | |
3118 | hdw->flag_ok = 0; | |
3119 | if (hdw->vid_stream) { | |
a0fd1cb1 | 3120 | pvr2_stream_setup(hdw->vid_stream,NULL,0,0); |
d855497e MI |
3121 | } |
3122 | hdw->flag_streaming_enabled = 0; | |
3123 | hdw->subsys_enabled_mask = 0; | |
3124 | } | |
3125 | ||
3126 | ||
3127 | void pvr2_hdw_render_useless(struct pvr2_hdw *hdw) | |
3128 | { | |
3129 | LOCK_TAKE(hdw->ctl_lock); | |
3130 | pvr2_hdw_render_useless_unlocked(hdw); | |
3131 | LOCK_GIVE(hdw->ctl_lock); | |
3132 | } | |
3133 | ||
3134 | ||
3135 | void pvr2_hdw_device_reset(struct pvr2_hdw *hdw) | |
3136 | { | |
3137 | int ret; | |
3138 | pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset..."); | |
a0fd1cb1 | 3139 | ret = usb_lock_device_for_reset(hdw->usb_dev,NULL); |
d855497e MI |
3140 | if (ret == 1) { |
3141 | ret = usb_reset_device(hdw->usb_dev); | |
3142 | usb_unlock_device(hdw->usb_dev); | |
3143 | } else { | |
3144 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
3145 | "Failed to lock USB device ret=%d",ret); | |
3146 | } | |
3147 | if (init_pause_msec) { | |
3148 | pvr2_trace(PVR2_TRACE_INFO, | |
3149 | "Waiting %u msec for hardware to settle", | |
3150 | init_pause_msec); | |
3151 | msleep(init_pause_msec); | |
3152 | } | |
3153 | ||
3154 | } | |
3155 | ||
3156 | ||
3157 | void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val) | |
3158 | { | |
3159 | char da[1]; | |
3160 | unsigned int pipe; | |
3161 | int ret; | |
3162 | ||
3163 | if (!hdw->usb_dev) return; | |
3164 | ||
3165 | pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val); | |
3166 | ||
3167 | da[0] = val ? 0x01 : 0x00; | |
3168 | ||
3169 | /* Write the CPUCS register on the 8051. The lsb of the register | |
3170 | is the reset bit; a 1 asserts reset while a 0 clears it. */ | |
3171 | pipe = usb_sndctrlpipe(hdw->usb_dev, 0); | |
3172 | ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ); | |
3173 | if (ret < 0) { | |
3174 | pvr2_trace(PVR2_TRACE_ERROR_LEGS, | |
3175 | "cpureset_assert(%d) error=%d",val,ret); | |
3176 | pvr2_hdw_render_useless(hdw); | |
3177 | } | |
3178 | } | |
3179 | ||
3180 | ||
3181 | int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw) | |
3182 | { | |
3183 | int status; | |
3184 | LOCK_TAKE(hdw->ctl_lock); do { | |
3185 | pvr2_trace(PVR2_TRACE_INIT,"Requesting uproc hard reset"); | |
3186 | hdw->flag_ok = !0; | |
3187 | hdw->cmd_buffer[0] = 0xdd; | |
a0fd1cb1 | 3188 | status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0); |
d855497e MI |
3189 | } while (0); LOCK_GIVE(hdw->ctl_lock); |
3190 | return status; | |
3191 | } | |
3192 | ||
3193 | ||
3194 | int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw) | |
3195 | { | |
3196 | int status; | |
3197 | LOCK_TAKE(hdw->ctl_lock); do { | |
3198 | pvr2_trace(PVR2_TRACE_INIT,"Requesting powerup"); | |
3199 | hdw->cmd_buffer[0] = 0xde; | |
a0fd1cb1 | 3200 | status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0); |
d855497e MI |
3201 | } while (0); LOCK_GIVE(hdw->ctl_lock); |
3202 | return status; | |
3203 | } | |
3204 | ||
3205 | ||
3206 | int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw) | |
3207 | { | |
3208 | if (!hdw->decoder_ctrl) { | |
3209 | pvr2_trace(PVR2_TRACE_INIT, | |
3210 | "Unable to reset decoder: nothing attached"); | |
3211 | return -ENOTTY; | |
3212 | } | |
3213 | ||
3214 | if (!hdw->decoder_ctrl->force_reset) { | |
3215 | pvr2_trace(PVR2_TRACE_INIT, | |
3216 | "Unable to reset decoder: not implemented"); | |
3217 | return -ENOTTY; | |
3218 | } | |
3219 | ||
3220 | pvr2_trace(PVR2_TRACE_INIT, | |
3221 | "Requesting decoder reset"); | |
3222 | hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt); | |
3223 | return 0; | |
3224 | } | |
3225 | ||
3226 | ||
e61b6fc5 | 3227 | /* Stop / start video stream transport */ |
07e337ee | 3228 | static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl) |
d855497e MI |
3229 | { |
3230 | int status; | |
3231 | LOCK_TAKE(hdw->ctl_lock); do { | |
3232 | hdw->cmd_buffer[0] = (runFl ? 0x36 : 0x37); | |
a0fd1cb1 | 3233 | status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0); |
d855497e MI |
3234 | } while (0); LOCK_GIVE(hdw->ctl_lock); |
3235 | if (!status) { | |
3236 | hdw->subsys_enabled_mask = | |
3237 | ((hdw->subsys_enabled_mask & | |
3238 | ~(1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) | | |
3239 | (runFl ? (1<<PVR2_SUBSYS_B_USBSTREAM_RUN) : 0)); | |
3240 | } | |
3241 | return status; | |
3242 | } | |
3243 | ||
3244 | ||
3245 | void pvr2_hdw_get_debug_info(const struct pvr2_hdw *hdw, | |
3246 | struct pvr2_hdw_debug_info *ptr) | |
3247 | { | |
3248 | ptr->big_lock_held = hdw->big_lock_held; | |
3249 | ptr->ctl_lock_held = hdw->ctl_lock_held; | |
3250 | ptr->flag_ok = hdw->flag_ok; | |
3251 | ptr->flag_disconnected = hdw->flag_disconnected; | |
3252 | ptr->flag_init_ok = hdw->flag_init_ok; | |
3253 | ptr->flag_streaming_enabled = hdw->flag_streaming_enabled; | |
3254 | ptr->subsys_flags = hdw->subsys_enabled_mask; | |
3255 | ptr->cmd_debug_state = hdw->cmd_debug_state; | |
3256 | ptr->cmd_code = hdw->cmd_debug_code; | |
3257 | ptr->cmd_debug_write_len = hdw->cmd_debug_write_len; | |
3258 | ptr->cmd_debug_read_len = hdw->cmd_debug_read_len; | |
3259 | ptr->cmd_debug_timeout = hdw->ctl_timeout_flag; | |
3260 | ptr->cmd_debug_write_pend = hdw->ctl_write_pend_flag; | |
3261 | ptr->cmd_debug_read_pend = hdw->ctl_read_pend_flag; | |
3262 | ptr->cmd_debug_rstatus = hdw->ctl_read_urb->status; | |
3263 | ptr->cmd_debug_wstatus = hdw->ctl_read_urb->status; | |
3264 | } | |
3265 | ||
3266 | ||
3267 | int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp) | |
3268 | { | |
3269 | return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp); | |
3270 | } | |
3271 | ||
3272 | ||
3273 | int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp) | |
3274 | { | |
3275 | return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp); | |
3276 | } | |
3277 | ||
3278 | ||
3279 | int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp) | |
3280 | { | |
3281 | return pvr2_read_register(hdw,PVR2_GPIO_IN,dp); | |
3282 | } | |
3283 | ||
3284 | ||
3285 | int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val) | |
3286 | { | |
3287 | u32 cval,nval; | |
3288 | int ret; | |
3289 | if (~msk) { | |
3290 | ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval); | |
3291 | if (ret) return ret; | |
3292 | nval = (cval & ~msk) | (val & msk); | |
3293 | pvr2_trace(PVR2_TRACE_GPIO, | |
3294 | "GPIO direction changing 0x%x:0x%x" | |
3295 | " from 0x%x to 0x%x", | |
3296 | msk,val,cval,nval); | |
3297 | } else { | |
3298 | nval = val; | |
3299 | pvr2_trace(PVR2_TRACE_GPIO, | |
3300 | "GPIO direction changing to 0x%x",nval); | |
3301 | } | |
3302 | return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval); | |
3303 | } | |
3304 | ||
3305 | ||
3306 | int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val) | |
3307 | { | |
3308 | u32 cval,nval; | |
3309 | int ret; | |
3310 | if (~msk) { | |
3311 | ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval); | |
3312 | if (ret) return ret; | |
3313 | nval = (cval & ~msk) | (val & msk); | |
3314 | pvr2_trace(PVR2_TRACE_GPIO, | |
3315 | "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x", | |
3316 | msk,val,cval,nval); | |
3317 | } else { | |
3318 | nval = val; | |
3319 | pvr2_trace(PVR2_TRACE_GPIO, | |
3320 | "GPIO output changing to 0x%x",nval); | |
3321 | } | |
3322 | return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval); | |
3323 | } | |
3324 | ||
3325 | ||
e61b6fc5 | 3326 | /* Find I2C address of eeprom */ |
07e337ee | 3327 | static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw) |
d855497e MI |
3328 | { |
3329 | int result; | |
3330 | LOCK_TAKE(hdw->ctl_lock); do { | |
3331 | hdw->cmd_buffer[0] = 0xeb; | |
3332 | result = pvr2_send_request(hdw, | |
3333 | hdw->cmd_buffer,1, | |
3334 | hdw->cmd_buffer,1); | |
3335 | if (result < 0) break; | |
3336 | result = hdw->cmd_buffer[0]; | |
3337 | } while(0); LOCK_GIVE(hdw->ctl_lock); | |
3338 | return result; | |
3339 | } | |
3340 | ||
3341 | ||
32ffa9ae MI |
3342 | int pvr2_hdw_register_access(struct pvr2_hdw *hdw, |
3343 | u32 chip_id,unsigned long reg_id, | |
3344 | int setFl,u32 *val_ptr) | |
3345 | { | |
3346 | #ifdef CONFIG_VIDEO_ADV_DEBUG | |
3347 | struct list_head *item; | |
3348 | struct pvr2_i2c_client *cp; | |
3349 | struct v4l2_register req; | |
6d98816f MI |
3350 | int stat = 0; |
3351 | int okFl = 0; | |
32ffa9ae MI |
3352 | |
3353 | req.i2c_id = chip_id; | |
3354 | req.reg = reg_id; | |
3355 | if (setFl) req.val = *val_ptr; | |
3356 | mutex_lock(&hdw->i2c_list_lock); do { | |
3357 | list_for_each(item,&hdw->i2c_clients) { | |
3358 | cp = list_entry(item,struct pvr2_i2c_client,list); | |
3359 | if (cp->client->driver->id != chip_id) continue; | |
3360 | stat = pvr2_i2c_client_cmd( | |
3361 | cp,(setFl ? VIDIOC_INT_S_REGISTER : | |
3362 | VIDIOC_INT_G_REGISTER),&req); | |
3363 | if (!setFl) *val_ptr = req.val; | |
6d98816f MI |
3364 | okFl = !0; |
3365 | break; | |
32ffa9ae MI |
3366 | } |
3367 | } while (0); mutex_unlock(&hdw->i2c_list_lock); | |
6d98816f MI |
3368 | if (okFl) { |
3369 | return stat; | |
3370 | } | |
32ffa9ae MI |
3371 | return -EINVAL; |
3372 | #else | |
3373 | return -ENOSYS; | |
3374 | #endif | |
3375 | } | |
3376 | ||
3377 | ||
d855497e MI |
3378 | /* |
3379 | Stuff for Emacs to see, in order to encourage consistent editing style: | |
3380 | *** Local Variables: *** | |
3381 | *** mode: c *** | |
3382 | *** fill-column: 75 *** | |
3383 | *** tab-width: 8 *** | |
3384 | *** c-basic-offset: 8 *** | |
3385 | *** End: *** | |
3386 | */ |