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V4L/DVB (5210): Pvrusb2: Fix printk format typo
[mirror_ubuntu-artful-kernel.git] / drivers / media / video / pvrusb2 / pvrusb2-hdw.c
CommitLineData
d855497e
MI		 1/*
2 *
3 * $Id$
4 *
5 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22#include <linux/errno.h>
23#include <linux/string.h>
24#include <linux/slab.h>
25#include <linux/firmware.h>
d855497e 26#include <linux/videodev2.h>
32ffa9ae 27#include <media/v4l2-common.h>
b2bbaa93 28#include <asm/semaphore.h>
d855497e
MI		 29#include "pvrusb2.h"
30#include "pvrusb2-std.h"
31#include "pvrusb2-util.h"
32#include "pvrusb2-hdw.h"
33#include "pvrusb2-i2c-core.h"
34#include "pvrusb2-tuner.h"
35#include "pvrusb2-eeprom.h"
36#include "pvrusb2-hdw-internal.h"
37#include "pvrusb2-encoder.h"
38#include "pvrusb2-debug.h"
8d364363 39#include "pvrusb2-fx2-cmd.h"
d855497e 40
1bde0289
MI		 41#define TV_MIN_FREQ 55250000L
42#define TV_MAX_FREQ 850000000L
25d8527a 43
d855497e
MI		 44struct usb_device_id pvr2_device_table[] = {
45 [PVR2_HDW_TYPE_29XXX] = { USB_DEVICE(0x2040, 0x2900) },
d855497e 46 [PVR2_HDW_TYPE_24XXX] = { USB_DEVICE(0x2040, 0x2400) },
d855497e
MI		 47 { }
48};
49
50MODULE_DEVICE_TABLE(usb, pvr2_device_table);
51
52static const char *pvr2_device_names[] = {
53 [PVR2_HDW_TYPE_29XXX] = "WinTV PVR USB2 Model Category 29xxxx",
d855497e 54 [PVR2_HDW_TYPE_24XXX] = "WinTV PVR USB2 Model Category 24xxxx",
d855497e
MI		 55};
56
57struct pvr2_string_table {
58 const char **lst;
59 unsigned int cnt;
60};
61
d855497e
MI		 62// Names of other client modules to request for 24xxx model hardware
63static const char *pvr2_client_24xxx[] = {
64 "cx25840",
65 "tuner",
d855497e
MI		 66 "wm8775",
67};
d855497e
MI		 68
69// Names of other client modules to request for 29xxx model hardware
70static const char *pvr2_client_29xxx[] = {
71 "msp3400",
72 "saa7115",
73 "tuner",
d855497e
MI		 74};
75
76static struct pvr2_string_table pvr2_client_lists[] = {
77 [PVR2_HDW_TYPE_29XXX] = {
eca8ebfc 78 pvr2_client_29xxx, ARRAY_SIZE(pvr2_client_29xxx)
d855497e 79 },
d855497e 80 [PVR2_HDW_TYPE_24XXX] = {
eca8ebfc 81 pvr2_client_24xxx, ARRAY_SIZE(pvr2_client_24xxx)
d855497e 82 },
d855497e
MI		 83};
84
a0fd1cb1 85static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
07e337ee 86static DECLARE_MUTEX(pvr2_unit_sem);
d855497e
MI		 87
88static int ctlchg = 0;
89static int initusbreset = 1;
90static int procreload = 0;
91static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
92static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
93static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
94static int init_pause_msec = 0;
95
96module_param(ctlchg, int, S_IRUGO|S_IWUSR);
97MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
98module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
99MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
100module_param(initusbreset, int, S_IRUGO|S_IWUSR);
101MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
102module_param(procreload, int, S_IRUGO|S_IWUSR);
103MODULE_PARM_DESC(procreload,
104 "Attempt init failure recovery with firmware reload");
105module_param_array(tuner, int, NULL, 0444);
106MODULE_PARM_DESC(tuner,"specify installed tuner type");
107module_param_array(video_std, int, NULL, 0444);
108MODULE_PARM_DESC(video_std,"specify initial video standard");
109module_param_array(tolerance, int, NULL, 0444);
110MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
111
112#define PVR2_CTL_WRITE_ENDPOINT 0x01
113#define PVR2_CTL_READ_ENDPOINT 0x81
114
115#define PVR2_GPIO_IN 0x9008
116#define PVR2_GPIO_OUT 0x900c
117#define PVR2_GPIO_DIR 0x9020
118
119#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
120
121#define PVR2_FIRMWARE_ENDPOINT 0x02
122
123/* size of a firmware chunk */
124#define FIRMWARE_CHUNK_SIZE 0x2000
125
b30d2441
MI		 126/* Define the list of additional controls we'll dynamically construct based
127 on query of the cx2341x module. */
128struct pvr2_mpeg_ids {
129 const char *strid;
130 int id;
131};
132static const struct pvr2_mpeg_ids mpeg_ids[] = {
133 {
134 .strid = "audio_layer",
135 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
136 },{
137 .strid = "audio_bitrate",
138 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
139 },{
140 /* Already using audio_mode elsewhere :-( */
141 .strid = "mpeg_audio_mode",
142 .id = V4L2_CID_MPEG_AUDIO_MODE,
143 },{
144 .strid = "mpeg_audio_mode_extension",
145 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
146 },{
147 .strid = "audio_emphasis",
148 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
149 },{
150 .strid = "audio_crc",
151 .id = V4L2_CID_MPEG_AUDIO_CRC,
152 },{
153 .strid = "video_aspect",
154 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
155 },{
156 .strid = "video_b_frames",
157 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
158 },{
159 .strid = "video_gop_size",
160 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
161 },{
162 .strid = "video_gop_closure",
163 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
b30d2441
MI		 164 },{
165 .strid = "video_bitrate_mode",
166 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
167 },{
168 .strid = "video_bitrate",
169 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
170 },{
171 .strid = "video_bitrate_peak",
172 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
173 },{
174 .strid = "video_temporal_decimation",
175 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
176 },{
177 .strid = "stream_type",
178 .id = V4L2_CID_MPEG_STREAM_TYPE,
179 },{
180 .strid = "video_spatial_filter_mode",
181 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
182 },{
183 .strid = "video_spatial_filter",
184 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
185 },{
186 .strid = "video_luma_spatial_filter_type",
187 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
188 },{
189 .strid = "video_chroma_spatial_filter_type",
190 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
191 },{
192 .strid = "video_temporal_filter_mode",
193 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
194 },{
195 .strid = "video_temporal_filter",
196 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
197 },{
198 .strid = "video_median_filter_type",
199 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
200 },{
201 .strid = "video_luma_median_filter_top",
202 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
203 },{
204 .strid = "video_luma_median_filter_bottom",
205 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
206 },{
207 .strid = "video_chroma_median_filter_top",
208 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
209 },{
210 .strid = "video_chroma_median_filter_bottom",
211 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
212 }
213};
eca8ebfc 214#define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
c05c0462 215
434449f4 216
d855497e 217static const char *control_values_srate[] = {
434449f4
MI		 218 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
219 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
220 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
d855497e
MI		 221};
222
223
d855497e 224
d855497e
MI		 225static const char *control_values_input[] = {
226 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
227 [PVR2_CVAL_INPUT_RADIO] = "radio",
228 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
229 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
230};
231
232
233static const char *control_values_audiomode[] = {
234 [V4L2_TUNER_MODE_MONO] = "Mono",
235 [V4L2_TUNER_MODE_STEREO] = "Stereo",
236 [V4L2_TUNER_MODE_LANG1] = "Lang1",
237 [V4L2_TUNER_MODE_LANG2] = "Lang2",
238 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
239};
240
241
242static const char *control_values_hsm[] = {
243 [PVR2_CVAL_HSM_FAIL] = "Fail",
244 [PVR2_CVAL_HSM_HIGH] = "High",
245 [PVR2_CVAL_HSM_FULL] = "Full",
246};
247
248
249static const char *control_values_subsystem[] = {
250 [PVR2_SUBSYS_B_ENC_FIRMWARE] = "enc_firmware",
251 [PVR2_SUBSYS_B_ENC_CFG] = "enc_config",
252 [PVR2_SUBSYS_B_DIGITIZER_RUN] = "digitizer_run",
253 [PVR2_SUBSYS_B_USBSTREAM_RUN] = "usbstream_run",
254 [PVR2_SUBSYS_B_ENC_RUN] = "enc_run",
255};
256
1bde0289 257static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
07e337ee
AB		 258static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
259static int pvr2_hdw_commit_ctl_internal(struct pvr2_hdw *hdw);
260static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
07e337ee
AB		 261static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
262static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
263static void pvr2_hdw_render_useless_unlocked(struct pvr2_hdw *hdw);
264static void pvr2_hdw_subsys_bit_chg_no_lock(struct pvr2_hdw *hdw,
265 unsigned long msk,
266 unsigned long val);
267static void pvr2_hdw_subsys_stream_bit_chg_no_lock(struct pvr2_hdw *hdw,
268 unsigned long msk,
269 unsigned long val);
270static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
271 unsigned int timeout,int probe_fl,
272 void *write_data,unsigned int write_len,
273 void *read_data,unsigned int read_len);
d855497e
MI		 274
275static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
276{
277 struct pvr2_hdw *hdw = cptr->hdw;
278 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
279 *vp = hdw->freqTable[hdw->freqProgSlot-1];
280 } else {
281 *vp = 0;
282 }
283 return 0;
284}
285
286static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
287{
288 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 289 unsigned int slotId = hdw->freqProgSlot;
290 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
291 hdw->freqTable[slotId-1] = v;
292 /* Handle side effects correctly - if we're tuned to this
293 slot, then forgot the slot id relation since the stored
294 frequency has been changed. */
295 if (hdw->freqSelector) {
296 if (hdw->freqSlotRadio == slotId) {
297 hdw->freqSlotRadio = 0;
298 }
299 } else {
300 if (hdw->freqSlotTelevision == slotId) {
301 hdw->freqSlotTelevision = 0;
302 }
303 }
d855497e
MI		 304 }
305 return 0;
306}
307
308static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
309{
310 *vp = cptr->hdw->freqProgSlot;
311 return 0;
312}
313
314static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
315{
316 struct pvr2_hdw *hdw = cptr->hdw;
317 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
318 hdw->freqProgSlot = v;
319 }
320 return 0;
321}
322
323static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
324{
1bde0289
MI		 325 struct pvr2_hdw *hdw = cptr->hdw;
326 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
d855497e
MI		 327 return 0;
328}
329
1bde0289 330static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
d855497e
MI		 331{
332 unsigned freq = 0;
333 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 334 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
335 if (slotId > 0) {
336 freq = hdw->freqTable[slotId-1];
337 if (!freq) return 0;
338 pvr2_hdw_set_cur_freq(hdw,freq);
d855497e 339 }
1bde0289
MI		 340 if (hdw->freqSelector) {
341 hdw->freqSlotRadio = slotId;
342 } else {
343 hdw->freqSlotTelevision = slotId;
d855497e
MI		 344 }
345 return 0;
346}
347
348static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
349{
1bde0289 350 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
d855497e
MI		 351 return 0;
352}
353
354static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
355{
356 return cptr->hdw->freqDirty != 0;
357}
358
359static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
360{
361 cptr->hdw->freqDirty = 0;
362}
363
364static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
365{
1bde0289 366 pvr2_hdw_set_cur_freq(cptr->hdw,v);
d855497e
MI		 367 return 0;
368}
369
3ad9fc37
MI		 370static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
371{
372 /* Actual maximum depends on the video standard in effect. */
373 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
374 *vp = 480;
375 } else {
376 *vp = 576;
377 }
378 return 0;
379}
380
381static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
382{
383 /* Actual minimum depends on device type. */
384 if (cptr->hdw->hdw_type == PVR2_HDW_TYPE_24XXX) {
385 *vp = 75;
386 } else {
387 *vp = 17;
388 }
389 return 0;
390}
391
1bde0289 392static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
5549f54f 393{
1bde0289
MI		 394 *vp = cptr->hdw->input_val;
395 return 0;
396}
397
398static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
399{
400 struct pvr2_hdw *hdw = cptr->hdw;
401
402 if (hdw->input_val != v) {
403 hdw->input_val = v;
404 hdw->input_dirty = !0;
405 }
406
407 /* Handle side effects - if we switch to a mode that needs the RF
408 tuner, then select the right frequency choice as well and mark
409 it dirty. */
410 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
411 hdw->freqSelector = 0;
412 hdw->freqDirty = !0;
413 } else if (hdw->input_val == PVR2_CVAL_INPUT_TV) {
414 hdw->freqSelector = 1;
415 hdw->freqDirty = !0;
5549f54f 416 }
1bde0289
MI		 417 return 0;
418}
419
420static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
421{
422 return cptr->hdw->input_dirty != 0;
423}
424
425static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
426{
427 cptr->hdw->input_dirty = 0;
428}
429
5549f54f 430
25d8527a
PK		 431static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
432{
644afdb9
MI		 433 unsigned long fv;
434 struct pvr2_hdw *hdw = cptr->hdw;
435 if (hdw->tuner_signal_stale) {
436 pvr2_i2c_core_status_poll(hdw);
437 }
438 fv = hdw->tuner_signal_info.rangehigh;
439 if (!fv) {
440 /* Safety fallback */
25d8527a 441 *vp = TV_MAX_FREQ;
644afdb9 442 return 0;
25d8527a 443 }
644afdb9
MI		 444 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
445 fv = (fv * 125) / 2;
446 } else {
447 fv = fv * 62500;
448 }
449 *vp = fv;
25d8527a
PK		 450 return 0;
451}
452
453static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
454{
644afdb9
MI		 455 unsigned long fv;
456 struct pvr2_hdw *hdw = cptr->hdw;
457 if (hdw->tuner_signal_stale) {
458 pvr2_i2c_core_status_poll(hdw);
459 }
460 fv = hdw->tuner_signal_info.rangelow;
461 if (!fv) {
462 /* Safety fallback */
25d8527a 463 *vp = TV_MIN_FREQ;
644afdb9
MI		 464 return 0;
465 }
466 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
467 fv = (fv * 125) / 2;
468 } else {
469 fv = fv * 62500;
25d8527a 470 }
644afdb9 471 *vp = fv;
25d8527a
PK		 472 return 0;
473}
474
b30d2441
MI		 475static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
476{
477 return cptr->hdw->enc_stale != 0;
478}
479
480static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
481{
482 cptr->hdw->enc_stale = 0;
483}
484
485static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
486{
487 int ret;
488 struct v4l2_ext_controls cs;
489 struct v4l2_ext_control c1;
490 memset(&cs,0,sizeof(cs));
491 memset(&c1,0,sizeof(c1));
492 cs.controls = &c1;
493 cs.count = 1;
494 c1.id = cptr->info->v4l_id;
495 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state,&cs,
496 VIDIOC_G_EXT_CTRLS);
497 if (ret) return ret;
498 *vp = c1.value;
499 return 0;
500}
501
502static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
503{
504 int ret;
505 struct v4l2_ext_controls cs;
506 struct v4l2_ext_control c1;
507 memset(&cs,0,sizeof(cs));
508 memset(&c1,0,sizeof(c1));
509 cs.controls = &c1;
510 cs.count = 1;
511 c1.id = cptr->info->v4l_id;
512 c1.value = v;
513 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state,&cs,
514 VIDIOC_S_EXT_CTRLS);
515 if (ret) return ret;
516 cptr->hdw->enc_stale = !0;
517 return 0;
518}
519
520static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
521{
522 struct v4l2_queryctrl qctrl;
523 struct pvr2_ctl_info *info;
524 qctrl.id = cptr->info->v4l_id;
525 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
526 /* Strip out the const so we can adjust a function pointer. It's
527 OK to do this here because we know this is a dynamically created
528 control, so the underlying storage for the info pointer is (a)
529 private to us, and (b) not in read-only storage. Either we do
530 this or we significantly complicate the underlying control
531 implementation. */
532 info = (struct pvr2_ctl_info *)(cptr->info);
533 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
534 if (info->set_value) {
a0fd1cb1 535 info->set_value = NULL;
b30d2441
MI		 536 }
537 } else {
538 if (!(info->set_value)) {
539 info->set_value = ctrl_cx2341x_set;
540 }
541 }
542 return qctrl.flags;
543}
544
d855497e
MI		 545static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
546{
547 *vp = cptr->hdw->flag_streaming_enabled;
548 return 0;
549}
550
551static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
552{
553 int result = pvr2_hdw_is_hsm(cptr->hdw);
554 *vp = PVR2_CVAL_HSM_FULL;
555 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
556 if (result) *vp = PVR2_CVAL_HSM_HIGH;
557 return 0;
558}
559
560static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
561{
562 *vp = cptr->hdw->std_mask_avail;
563 return 0;
564}
565
566static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
567{
568 struct pvr2_hdw *hdw = cptr->hdw;
569 v4l2_std_id ns;
570 ns = hdw->std_mask_avail;
571 ns = (ns & ~m) | (v & m);
572 if (ns == hdw->std_mask_avail) return 0;
573 hdw->std_mask_avail = ns;
574 pvr2_hdw_internal_set_std_avail(hdw);
575 pvr2_hdw_internal_find_stdenum(hdw);
576 return 0;
577}
578
579static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
580 char *bufPtr,unsigned int bufSize,
581 unsigned int *len)
582{
583 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
584 return 0;
585}
586
587static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
588 const char *bufPtr,unsigned int bufSize,
589 int *mskp,int *valp)
590{
591 int ret;
592 v4l2_std_id id;
593 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
594 if (ret < 0) return ret;
595 if (mskp) *mskp = id;
596 if (valp) *valp = id;
597 return 0;
598}
599
600static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
601{
602 *vp = cptr->hdw->std_mask_cur;
603 return 0;
604}
605
606static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
607{
608 struct pvr2_hdw *hdw = cptr->hdw;
609 v4l2_std_id ns;
610 ns = hdw->std_mask_cur;
611 ns = (ns & ~m) | (v & m);
612 if (ns == hdw->std_mask_cur) return 0;
613 hdw->std_mask_cur = ns;
614 hdw->std_dirty = !0;
615 pvr2_hdw_internal_find_stdenum(hdw);
616 return 0;
617}
618
619static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
620{
621 return cptr->hdw->std_dirty != 0;
622}
623
624static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
625{
626 cptr->hdw->std_dirty = 0;
627}
628
629static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
630{
18103c57
MI		 631 struct pvr2_hdw *hdw = cptr->hdw;
632 pvr2_i2c_core_status_poll(hdw);
633 *vp = hdw->tuner_signal_info.signal;
634 return 0;
635}
636
637static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
638{
639 int val = 0;
640 unsigned int subchan;
641 struct pvr2_hdw *hdw = cptr->hdw;
644afdb9 642 pvr2_i2c_core_status_poll(hdw);
18103c57
MI		 643 subchan = hdw->tuner_signal_info.rxsubchans;
644 if (subchan & V4L2_TUNER_SUB_MONO) {
645 val |= (1 << V4L2_TUNER_MODE_MONO);
646 }
647 if (subchan & V4L2_TUNER_SUB_STEREO) {
648 val |= (1 << V4L2_TUNER_MODE_STEREO);
649 }
650 if (subchan & V4L2_TUNER_SUB_LANG1) {
651 val |= (1 << V4L2_TUNER_MODE_LANG1);
652 }
653 if (subchan & V4L2_TUNER_SUB_LANG2) {
654 val |= (1 << V4L2_TUNER_MODE_LANG2);
655 }
656 *vp = val;
d855497e
MI		 657 return 0;
658}
659
660static int ctrl_subsys_get(struct pvr2_ctrl *cptr,int *vp)
661{
662 *vp = cptr->hdw->subsys_enabled_mask;
663 return 0;
664}
665
666static int ctrl_subsys_set(struct pvr2_ctrl *cptr,int m,int v)
667{
668 pvr2_hdw_subsys_bit_chg_no_lock(cptr->hdw,m,v);
669 return 0;
670}
671
672static int ctrl_subsys_stream_get(struct pvr2_ctrl *cptr,int *vp)
673{
674 *vp = cptr->hdw->subsys_stream_mask;
675 return 0;
676}
677
678static int ctrl_subsys_stream_set(struct pvr2_ctrl *cptr,int m,int v)
679{
680 pvr2_hdw_subsys_stream_bit_chg_no_lock(cptr->hdw,m,v);
681 return 0;
682}
683
684static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
685{
686 struct pvr2_hdw *hdw = cptr->hdw;
687 if (v < 0) return -EINVAL;
688 if (v > hdw->std_enum_cnt) return -EINVAL;
689 hdw->std_enum_cur = v;
690 if (!v) return 0;
691 v--;
692 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
693 hdw->std_mask_cur = hdw->std_defs[v].id;
694 hdw->std_dirty = !0;
695 return 0;
696}
697
698
699static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
700{
701 *vp = cptr->hdw->std_enum_cur;
702 return 0;
703}
704
705
706static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
707{
708 return cptr->hdw->std_dirty != 0;
709}
710
711
712static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
713{
714 cptr->hdw->std_dirty = 0;
715}
716
717
718#define DEFINT(vmin,vmax) \
719 .type = pvr2_ctl_int, \
720 .def.type_int.min_value = vmin, \
721 .def.type_int.max_value = vmax
722
723#define DEFENUM(tab) \
724 .type = pvr2_ctl_enum, \
27c7b710 725 .def.type_enum.count = ARRAY_SIZE(tab), \
d855497e
MI		 726 .def.type_enum.value_names = tab
727
33213963
MI		 728#define DEFBOOL \
729 .type = pvr2_ctl_bool
730
d855497e
MI		 731#define DEFMASK(msk,tab) \
732 .type = pvr2_ctl_bitmask, \
733 .def.type_bitmask.valid_bits = msk, \
734 .def.type_bitmask.bit_names = tab
735
736#define DEFREF(vname) \
737 .set_value = ctrl_set_##vname, \
738 .get_value = ctrl_get_##vname, \
739 .is_dirty = ctrl_isdirty_##vname, \
740 .clear_dirty = ctrl_cleardirty_##vname
741
742
743#define VCREATE_FUNCS(vname) \
744static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
745{*vp = cptr->hdw->vname##_val; return 0;} \
746static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
747{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
748static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
749{return cptr->hdw->vname##_dirty != 0;} \
750static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
751{cptr->hdw->vname##_dirty = 0;}
752
753VCREATE_FUNCS(brightness)
754VCREATE_FUNCS(contrast)
755VCREATE_FUNCS(saturation)
756VCREATE_FUNCS(hue)
757VCREATE_FUNCS(volume)
758VCREATE_FUNCS(balance)
759VCREATE_FUNCS(bass)
760VCREATE_FUNCS(treble)
761VCREATE_FUNCS(mute)
c05c0462
MI		 762VCREATE_FUNCS(audiomode)
763VCREATE_FUNCS(res_hor)
764VCREATE_FUNCS(res_ver)
d855497e 765VCREATE_FUNCS(srate)
d855497e 766
d855497e
MI		 767/* Table definition of all controls which can be manipulated */
768static const struct pvr2_ctl_info control_defs[] = {
769 {
770 .v4l_id = V4L2_CID_BRIGHTNESS,
771 .desc = "Brightness",
772 .name = "brightness",
773 .default_value = 128,
774 DEFREF(brightness),
775 DEFINT(0,255),
776 },{
777 .v4l_id = V4L2_CID_CONTRAST,
778 .desc = "Contrast",
779 .name = "contrast",
780 .default_value = 68,
781 DEFREF(contrast),
782 DEFINT(0,127),
783 },{
784 .v4l_id = V4L2_CID_SATURATION,
785 .desc = "Saturation",
786 .name = "saturation",
787 .default_value = 64,
788 DEFREF(saturation),
789 DEFINT(0,127),
790 },{
791 .v4l_id = V4L2_CID_HUE,
792 .desc = "Hue",
793 .name = "hue",
794 .default_value = 0,
795 DEFREF(hue),
796 DEFINT(-128,127),
797 },{
798 .v4l_id = V4L2_CID_AUDIO_VOLUME,
799 .desc = "Volume",
800 .name = "volume",
139eecf9 801 .default_value = 62000,
d855497e
MI		 802 DEFREF(volume),
803 DEFINT(0,65535),
804 },{
805 .v4l_id = V4L2_CID_AUDIO_BALANCE,
806 .desc = "Balance",
807 .name = "balance",
808 .default_value = 0,
809 DEFREF(balance),
810 DEFINT(-32768,32767),
811 },{
812 .v4l_id = V4L2_CID_AUDIO_BASS,
813 .desc = "Bass",
814 .name = "bass",
815 .default_value = 0,
816 DEFREF(bass),
817 DEFINT(-32768,32767),
818 },{
819 .v4l_id = V4L2_CID_AUDIO_TREBLE,
820 .desc = "Treble",
821 .name = "treble",
822 .default_value = 0,
823 DEFREF(treble),
824 DEFINT(-32768,32767),
825 },{
826 .v4l_id = V4L2_CID_AUDIO_MUTE,
827 .desc = "Mute",
828 .name = "mute",
829 .default_value = 0,
830 DEFREF(mute),
33213963 831 DEFBOOL,
c05c0462
MI		 832 },{
833 .desc = "Video Source",
834 .name = "input",
835 .internal_id = PVR2_CID_INPUT,
836 .default_value = PVR2_CVAL_INPUT_TV,
837 DEFREF(input),
838 DEFENUM(control_values_input),
839 },{
840 .desc = "Audio Mode",
841 .name = "audio_mode",
842 .internal_id = PVR2_CID_AUDIOMODE,
843 .default_value = V4L2_TUNER_MODE_STEREO,
844 DEFREF(audiomode),
845 DEFENUM(control_values_audiomode),
846 },{
847 .desc = "Horizontal capture resolution",
848 .name = "resolution_hor",
849 .internal_id = PVR2_CID_HRES,
850 .default_value = 720,
851 DEFREF(res_hor),
3ad9fc37 852 DEFINT(19,720),
c05c0462
MI		 853 },{
854 .desc = "Vertical capture resolution",
855 .name = "resolution_ver",
856 .internal_id = PVR2_CID_VRES,
857 .default_value = 480,
858 DEFREF(res_ver),
3ad9fc37
MI		 859 DEFINT(17,576),
860 /* Hook in check for video standard and adjust maximum
861 depending on the standard. */
862 .get_max_value = ctrl_vres_max_get,
863 .get_min_value = ctrl_vres_min_get,
d855497e 864 },{
b30d2441 865 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
434449f4
MI		 866 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
867 .desc = "Audio Sampling Frequency",
d855497e 868 .name = "srate",
d855497e
MI		 869 DEFREF(srate),
870 DEFENUM(control_values_srate),
d855497e
MI		 871 },{
872 .desc = "Tuner Frequency (Hz)",
873 .name = "frequency",
874 .internal_id = PVR2_CID_FREQUENCY,
1bde0289 875 .default_value = 0,
d855497e
MI		 876 .set_value = ctrl_freq_set,
877 .get_value = ctrl_freq_get,
878 .is_dirty = ctrl_freq_is_dirty,
879 .clear_dirty = ctrl_freq_clear_dirty,
644afdb9 880 DEFINT(0,0),
25d8527a
PK		 881 /* Hook in check for input value (tv/radio) and adjust
882 max/min values accordingly */
883 .get_max_value = ctrl_freq_max_get,
884 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 885 },{
886 .desc = "Channel",
887 .name = "channel",
888 .set_value = ctrl_channel_set,
889 .get_value = ctrl_channel_get,
890 DEFINT(0,FREQTABLE_SIZE),
891 },{
892 .desc = "Channel Program Frequency",
893 .name = "freq_table_value",
894 .set_value = ctrl_channelfreq_set,
895 .get_value = ctrl_channelfreq_get,
644afdb9 896 DEFINT(0,0),
1bde0289
MI		 897 /* Hook in check for input value (tv/radio) and adjust
898 max/min values accordingly */
1bde0289
MI		 899 .get_max_value = ctrl_freq_max_get,
900 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 901 },{
902 .desc = "Channel Program ID",
903 .name = "freq_table_channel",
904 .set_value = ctrl_channelprog_set,
905 .get_value = ctrl_channelprog_get,
906 DEFINT(0,FREQTABLE_SIZE),
d855497e
MI		 907 },{
908 .desc = "Streaming Enabled",
909 .name = "streaming_enabled",
910 .get_value = ctrl_streamingenabled_get,
33213963 911 DEFBOOL,
d855497e
MI		 912 },{
913 .desc = "USB Speed",
914 .name = "usb_speed",
915 .get_value = ctrl_hsm_get,
916 DEFENUM(control_values_hsm),
917 },{
918 .desc = "Signal Present",
919 .name = "signal_present",
920 .get_value = ctrl_signal_get,
18103c57
MI		 921 DEFINT(0,65535),
922 },{
923 .desc = "Audio Modes Present",
924 .name = "audio_modes_present",
925 .get_value = ctrl_audio_modes_present_get,
926 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
927 v4l. Nothing outside of this module cares about this,
928 but I reuse it in order to also reuse the
929 control_values_audiomode string table. */
930 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
931 (1 << V4L2_TUNER_MODE_STEREO)|
932 (1 << V4L2_TUNER_MODE_LANG1)|
933 (1 << V4L2_TUNER_MODE_LANG2)),
934 control_values_audiomode),
d855497e
MI		 935 },{
936 .desc = "Video Standards Available Mask",
937 .name = "video_standard_mask_available",
938 .internal_id = PVR2_CID_STDAVAIL,
939 .skip_init = !0,
940 .get_value = ctrl_stdavail_get,
941 .set_value = ctrl_stdavail_set,
942 .val_to_sym = ctrl_std_val_to_sym,
943 .sym_to_val = ctrl_std_sym_to_val,
944 .type = pvr2_ctl_bitmask,
945 },{
946 .desc = "Video Standards In Use Mask",
947 .name = "video_standard_mask_active",
948 .internal_id = PVR2_CID_STDCUR,
949 .skip_init = !0,
950 .get_value = ctrl_stdcur_get,
951 .set_value = ctrl_stdcur_set,
952 .is_dirty = ctrl_stdcur_is_dirty,
953 .clear_dirty = ctrl_stdcur_clear_dirty,
954 .val_to_sym = ctrl_std_val_to_sym,
955 .sym_to_val = ctrl_std_sym_to_val,
956 .type = pvr2_ctl_bitmask,
957 },{
958 .desc = "Subsystem enabled mask",
959 .name = "debug_subsys_mask",
960 .skip_init = !0,
961 .get_value = ctrl_subsys_get,
962 .set_value = ctrl_subsys_set,
963 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
964 },{
965 .desc = "Subsystem stream mask",
966 .name = "debug_subsys_stream_mask",
967 .skip_init = !0,
968 .get_value = ctrl_subsys_stream_get,
969 .set_value = ctrl_subsys_stream_set,
970 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
971 },{
972 .desc = "Video Standard Name",
973 .name = "video_standard",
974 .internal_id = PVR2_CID_STDENUM,
975 .skip_init = !0,
976 .get_value = ctrl_stdenumcur_get,
977 .set_value = ctrl_stdenumcur_set,
978 .is_dirty = ctrl_stdenumcur_is_dirty,
979 .clear_dirty = ctrl_stdenumcur_clear_dirty,
980 .type = pvr2_ctl_enum,
981 }
982};
983
eca8ebfc 984#define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
d855497e
MI		 985
986
987const char *pvr2_config_get_name(enum pvr2_config cfg)
988{
989 switch (cfg) {
990 case pvr2_config_empty: return "empty";
991 case pvr2_config_mpeg: return "mpeg";
992 case pvr2_config_vbi: return "vbi";
16eb40d3
MI		 993 case pvr2_config_pcm: return "pcm";
994 case pvr2_config_rawvideo: return "raw video";
d855497e
MI		 995 }
996 return "<unknown>";
997}
998
999
1000struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1001{
1002 return hdw->usb_dev;
1003}
1004
1005
1006unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1007{
1008 return hdw->serial_number;
1009}
1010
1bde0289
MI		 1011unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1012{
1013 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1014}
1015
1016/* Set the currently tuned frequency and account for all possible
1017 driver-core side effects of this action. */
1018void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1019{
7c74e57e 1020 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1bde0289
MI		 1021 if (hdw->freqSelector) {
1022 /* Swing over to radio frequency selection */
1023 hdw->freqSelector = 0;
1024 hdw->freqDirty = !0;
1025 }
1bde0289
MI		 1026 if (hdw->freqValRadio != val) {
1027 hdw->freqValRadio = val;
1028 hdw->freqSlotRadio = 0;
7c74e57e 1029 hdw->freqDirty = !0;
1bde0289 1030 }
7c74e57e 1031 } else {
1bde0289
MI		 1032 if (!(hdw->freqSelector)) {
1033 /* Swing over to television frequency selection */
1034 hdw->freqSelector = 1;
1035 hdw->freqDirty = !0;
1036 }
1bde0289
MI		 1037 if (hdw->freqValTelevision != val) {
1038 hdw->freqValTelevision = val;
1039 hdw->freqSlotTelevision = 0;
7c74e57e 1040 hdw->freqDirty = !0;
1bde0289 1041 }
1bde0289
MI		 1042 }
1043}
1044
d855497e
MI		 1045int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1046{
1047 return hdw->unit_number;
1048}
1049
1050
1051/* Attempt to locate one of the given set of files. Messages are logged
1052 appropriate to what has been found. The return value will be 0 or
1053 greater on success (it will be the index of the file name found) and
1054 fw_entry will be filled in. Otherwise a negative error is returned on
1055 failure. If the return value is -ENOENT then no viable firmware file
1056 could be located. */
1057static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1058 const struct firmware **fw_entry,
1059 const char *fwtypename,
1060 unsigned int fwcount,
1061 const char *fwnames[])
1062{
1063 unsigned int idx;
1064 int ret = -EINVAL;
1065 for (idx = 0; idx < fwcount; idx++) {
1066 ret = request_firmware(fw_entry,
1067 fwnames[idx],
1068 &hdw->usb_dev->dev);
1069 if (!ret) {
1070 trace_firmware("Located %s firmware: %s;"
1071 " uploading...",
1072 fwtypename,
1073 fwnames[idx]);
1074 return idx;
1075 }
1076 if (ret == -ENOENT) continue;
1077 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1078 "request_firmware fatal error with code=%d",ret);
1079 return ret;
1080 }
1081 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1082 "***WARNING***"
1083 " Device %s firmware"
1084 " seems to be missing.",
1085 fwtypename);
1086 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1087 "Did you install the pvrusb2 firmware files"
1088 " in their proper location?");
1089 if (fwcount == 1) {
1090 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1091 "request_firmware unable to locate %s file %s",
1092 fwtypename,fwnames[0]);
1093 } else {
1094 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1095 "request_firmware unable to locate"
1096 " one of the following %s files:",
1097 fwtypename);
1098 for (idx = 0; idx < fwcount; idx++) {
1099 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1100 "request_firmware: Failed to find %s",
1101 fwnames[idx]);
1102 }
1103 }
1104 return ret;
1105}
1106
1107
1108/*
1109 * pvr2_upload_firmware1().
1110 *
1111 * Send the 8051 firmware to the device. After the upload, arrange for
1112 * device to re-enumerate.
1113 *
1114 * NOTE : the pointer to the firmware data given by request_firmware()
1115 * is not suitable for an usb transaction.
1116 *
1117 */
07e337ee 1118static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
d855497e 1119{
a0fd1cb1 1120 const struct firmware *fw_entry = NULL;
d855497e
MI		 1121 void *fw_ptr;
1122 unsigned int pipe;
1123 int ret;
1124 u16 address;
1125 static const char *fw_files_29xxx[] = {
1126 "v4l-pvrusb2-29xxx-01.fw",
1127 };
d855497e
MI		 1128 static const char *fw_files_24xxx[] = {
1129 "v4l-pvrusb2-24xxx-01.fw",
1130 };
d855497e
MI		 1131 static const struct pvr2_string_table fw_file_defs[] = {
1132 [PVR2_HDW_TYPE_29XXX] = {
eca8ebfc 1133 fw_files_29xxx, ARRAY_SIZE(fw_files_29xxx)
d855497e 1134 },
d855497e 1135 [PVR2_HDW_TYPE_24XXX] = {
eca8ebfc 1136 fw_files_24xxx, ARRAY_SIZE(fw_files_24xxx)
d855497e 1137 },
d855497e
MI		 1138 };
1139 hdw->fw1_state = FW1_STATE_FAILED; // default result
1140
1141 trace_firmware("pvr2_upload_firmware1");
1142
1143 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1144 fw_file_defs[hdw->hdw_type].cnt,
1145 fw_file_defs[hdw->hdw_type].lst);
1146 if (ret < 0) {
1147 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1148 return ret;
1149 }
1150
1151 usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1152 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1153
1154 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1155
1156 if (fw_entry->size != 0x2000){
1157 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1158 release_firmware(fw_entry);
1159 return -ENOMEM;
1160 }
1161
1162 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1163 if (fw_ptr == NULL){
1164 release_firmware(fw_entry);
1165 return -ENOMEM;
1166 }
1167
1168 /* We have to hold the CPU during firmware upload. */
1169 pvr2_hdw_cpureset_assert(hdw,1);
1170
1171 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1172 chunk. */
1173
1174 ret = 0;
1175 for(address = 0; address < fw_entry->size; address += 0x800) {
1176 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1177 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1178 0, fw_ptr, 0x800, HZ);
1179 }
1180
1181 trace_firmware("Upload done, releasing device's CPU");
1182
1183 /* Now release the CPU. It will disconnect and reconnect later. */
1184 pvr2_hdw_cpureset_assert(hdw,0);
1185
1186 kfree(fw_ptr);
1187 release_firmware(fw_entry);
1188
1189 trace_firmware("Upload done (%d bytes sent)",ret);
1190
1191 /* We should have written 8192 bytes */
1192 if (ret == 8192) {
1193 hdw->fw1_state = FW1_STATE_RELOAD;
1194 return 0;
1195 }
1196
1197 return -EIO;
1198}
1199
1200
1201/*
1202 * pvr2_upload_firmware2()
1203 *
1204 * This uploads encoder firmware on endpoint 2.
1205 *
1206 */
1207
1208int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1209{
a0fd1cb1 1210 const struct firmware *fw_entry = NULL;
d855497e
MI		 1211 void *fw_ptr;
1212 unsigned int pipe, fw_len, fw_done;
1213 int actual_length;
1214 int ret = 0;
1215 int fwidx;
1216 static const char *fw_files[] = {
1217 CX2341X_FIRM_ENC_FILENAME,
1218 };
1219
1220 trace_firmware("pvr2_upload_firmware2");
1221
1222 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
eca8ebfc 1223 ARRAY_SIZE(fw_files), fw_files);
d855497e
MI		 1224 if (ret < 0) return ret;
1225 fwidx = ret;
1226 ret = 0;
b30d2441
MI		 1227 /* Since we're about to completely reinitialize the encoder,
1228 invalidate our cached copy of its configuration state. Next
1229 time we configure the encoder, then we'll fully configure it. */
1230 hdw->enc_cur_valid = 0;
d855497e
MI		 1231
1232 /* First prepare firmware loading */
1233 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1234 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1235 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1236 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1237 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1238 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1239 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1240 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1241 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1242 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1243 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1244 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1245 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1246 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1247 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1248 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
567d7115
MI		 1249 LOCK_TAKE(hdw->ctl_lock); do {
1250 hdw->cmd_buffer[0] = FX2CMD_FWPOST1;
1251 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,1,0,0);
1252 hdw->cmd_buffer[0] = FX2CMD_MEMSEL;
1253 hdw->cmd_buffer[1] = 0;
1254 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,2,0,0);
1255 } while (0); LOCK_GIVE(hdw->ctl_lock);
d855497e
MI		 1256
1257 if (ret) {
1258 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1259 "firmware2 upload prep failed, ret=%d",ret);
1260 release_firmware(fw_entry);
1261 return ret;
1262 }
1263
1264 /* Now send firmware */
1265
1266 fw_len = fw_entry->size;
1267
1268 if (fw_len % FIRMWARE_CHUNK_SIZE) {
1269 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1270 "size of %s firmware"
1271 " must be a multiple of 8192B",
1272 fw_files[fwidx]);
1273 release_firmware(fw_entry);
1274 return -1;
1275 }
1276
1277 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1278 if (fw_ptr == NULL){
1279 release_firmware(fw_entry);
1280 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1281 "failed to allocate memory for firmware2 upload");
1282 return -ENOMEM;
1283 }
1284
1285 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1286
1287 for (fw_done = 0 ; (fw_done < fw_len) && !ret ;
1288 fw_done += FIRMWARE_CHUNK_SIZE ) {
1289 int i;
1290 memcpy(fw_ptr, fw_entry->data + fw_done, FIRMWARE_CHUNK_SIZE);
1291 /* Usbsnoop log shows that we must swap bytes... */
1292 for (i = 0; i < FIRMWARE_CHUNK_SIZE/4 ; i++)
1293 ((u32 *)fw_ptr)[i] = ___swab32(((u32 *)fw_ptr)[i]);
1294
1295 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,
1296 FIRMWARE_CHUNK_SIZE,
1297 &actual_length, HZ);
1298 ret |= (actual_length != FIRMWARE_CHUNK_SIZE);
1299 }
1300
1301 trace_firmware("upload of %s : %i / %i ",
1302 fw_files[fwidx],fw_done,fw_len);
1303
1304 kfree(fw_ptr);
1305 release_firmware(fw_entry);
1306
1307 if (ret) {
1308 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1309 "firmware2 upload transfer failure");
1310 return ret;
1311 }
1312
1313 /* Finish upload */
1314
1315 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1316 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
567d7115
MI		 1317 LOCK_TAKE(hdw->ctl_lock); do {
1318 hdw->cmd_buffer[0] = FX2CMD_MEMSEL;
1319 hdw->cmd_buffer[1] = 0;
1320 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,2,0,0);
1321 } while (0); LOCK_GIVE(hdw->ctl_lock);
d855497e
MI		 1322
1323 if (ret) {
1324 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1325 "firmware2 upload post-proc failure");
1326 } else {
1327 hdw->subsys_enabled_mask |= (1<<PVR2_SUBSYS_B_ENC_FIRMWARE);
1328 }
1329 return ret;
1330}
1331
1332
1333#define FIRMWARE_RECOVERY_BITS \
1334 ((1<<PVR2_SUBSYS_B_ENC_CFG) | \
1335 (1<<PVR2_SUBSYS_B_ENC_RUN) | \
1336 (1<<PVR2_SUBSYS_B_ENC_FIRMWARE) | \
1337 (1<<PVR2_SUBSYS_B_USBSTREAM_RUN))
1338
1339/*
1340
1341 This single function is key to pretty much everything. The pvrusb2
1342 device can logically be viewed as a series of subsystems which can be
1343 stopped / started or unconfigured / configured. To get things streaming,
1344 one must configure everything and start everything, but there may be
1345 various reasons over time to deconfigure something or stop something.
1346 This function handles all of this activity. Everything EVERYWHERE that
1347 must affect a subsystem eventually comes here to do the work.
1348
1349 The current state of all subsystems is represented by a single bit mask,
1350 known as subsys_enabled_mask. The bit positions are defined by the
1351 PVR2_SUBSYS_xxxx macros, with one subsystem per bit position. At any
1352 time the set of configured or active subsystems can be queried just by
1353 looking at that mask. To change bits in that mask, this function here
1354 must be called. The "msk" argument indicates which bit positions to
1355 change, and the "val" argument defines the new values for the positions
1356 defined by "msk".
1357
1358 There is a priority ordering of starting / stopping things, and for
1359 multiple requested changes, this function implements that ordering.
1360 (Thus we will act on a request to load encoder firmware before we
1361 configure the encoder.) In addition to priority ordering, there is a
1362 recovery strategy implemented here. If a particular step fails and we
1363 detect that failure, this function will clear the affected subsystem bits
1364 and restart. Thus we have a means for recovering from a dead encoder:
1365 Clear all bits that correspond to subsystems that we need to restart /
1366 reconfigure and start over.
1367
1368*/
07e337ee
AB		 1369static void pvr2_hdw_subsys_bit_chg_no_lock(struct pvr2_hdw *hdw,
1370 unsigned long msk,
1371 unsigned long val)
d855497e
MI		 1372{
1373 unsigned long nmsk;
1374 unsigned long vmsk;
1375 int ret;
1376 unsigned int tryCount = 0;
1377
1378 if (!hdw->flag_ok) return;
1379
1380 msk &= PVR2_SUBSYS_ALL;
eb8e0ee4
MI		 1381 nmsk = (hdw->subsys_enabled_mask & ~msk) | (val & msk);
1382 nmsk &= PVR2_SUBSYS_ALL;
d855497e
MI		 1383
1384 for (;;) {
1385 tryCount++;
eb8e0ee4
MI		 1386 if (!((nmsk ^ hdw->subsys_enabled_mask) &
1387 PVR2_SUBSYS_ALL)) break;
d855497e
MI		 1388 if (tryCount > 4) {
1389 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1390 "Too many retries when configuring device;"
1391 " giving up");
1392 pvr2_hdw_render_useless(hdw);
1393 break;
1394 }
1395 if (tryCount > 1) {
1396 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1397 "Retrying device reconfiguration");
1398 }
1399 pvr2_trace(PVR2_TRACE_INIT,
1400 "subsys mask changing 0x%lx:0x%lx"
1401 " from 0x%lx to 0x%lx",
1402 msk,val,hdw->subsys_enabled_mask,nmsk);
1403
1404 vmsk = (nmsk ^ hdw->subsys_enabled_mask) &
1405 hdw->subsys_enabled_mask;
1406 if (vmsk) {
1407 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1408 pvr2_trace(PVR2_TRACE_CTL,
1409 "/*---TRACE_CTL----*/"
1410 " pvr2_encoder_stop");
1411 ret = pvr2_encoder_stop(hdw);
1412 if (ret) {
1413 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1414 "Error recovery initiated");
1415 hdw->subsys_enabled_mask &=
1416 ~FIRMWARE_RECOVERY_BITS;
1417 continue;
1418 }
1419 }
1420 if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1421 pvr2_trace(PVR2_TRACE_CTL,
1422 "/*---TRACE_CTL----*/"
1423 " pvr2_hdw_cmd_usbstream(0)");
1424 pvr2_hdw_cmd_usbstream(hdw,0);
1425 }
1426 if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1427 pvr2_trace(PVR2_TRACE_CTL,
1428 "/*---TRACE_CTL----*/"
1429 " decoder disable");
1430 if (hdw->decoder_ctrl) {
1431 hdw->decoder_ctrl->enable(
1432 hdw->decoder_ctrl->ctxt,0);
1433 } else {
1434 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1435 "WARNING:"
1436 " No decoder present");
1437 }
1438 hdw->subsys_enabled_mask &=
1439 ~(1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1440 }
1441 if (vmsk & PVR2_SUBSYS_CFG_ALL) {
1442 hdw->subsys_enabled_mask &=
1443 ~(vmsk & PVR2_SUBSYS_CFG_ALL);
1444 }
1445 }
1446 vmsk = (nmsk ^ hdw->subsys_enabled_mask) & nmsk;
1447 if (vmsk) {
1448 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_FIRMWARE)) {
1449 pvr2_trace(PVR2_TRACE_CTL,
1450 "/*---TRACE_CTL----*/"
1451 " pvr2_upload_firmware2");
1452 ret = pvr2_upload_firmware2(hdw);
1453 if (ret) {
1454 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1455 "Failure uploading encoder"
1456 " firmware");
1457 pvr2_hdw_render_useless(hdw);
1458 break;
1459 }
1460 }
1461 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_CFG)) {
1462 pvr2_trace(PVR2_TRACE_CTL,
1463 "/*---TRACE_CTL----*/"
1464 " pvr2_encoder_configure");
1465 ret = pvr2_encoder_configure(hdw);
1466 if (ret) {
1467 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1468 "Error recovery initiated");
1469 hdw->subsys_enabled_mask &=
1470 ~FIRMWARE_RECOVERY_BITS;
1471 continue;
1472 }
1473 }
1474 if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1475 pvr2_trace(PVR2_TRACE_CTL,
1476 "/*---TRACE_CTL----*/"
1477 " decoder enable");
1478 if (hdw->decoder_ctrl) {
1479 hdw->decoder_ctrl->enable(
1480 hdw->decoder_ctrl->ctxt,!0);
1481 } else {
1482 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1483 "WARNING:"
1484 " No decoder present");
1485 }
1486 hdw->subsys_enabled_mask |=
1487 (1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1488 }
1489 if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1490 pvr2_trace(PVR2_TRACE_CTL,
1491 "/*---TRACE_CTL----*/"
1492 " pvr2_hdw_cmd_usbstream(1)");
1493 pvr2_hdw_cmd_usbstream(hdw,!0);
1494 }
1495 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1496 pvr2_trace(PVR2_TRACE_CTL,
1497 "/*---TRACE_CTL----*/"
1498 " pvr2_encoder_start");
1499 ret = pvr2_encoder_start(hdw);
1500 if (ret) {
1501 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1502 "Error recovery initiated");
1503 hdw->subsys_enabled_mask &=
1504 ~FIRMWARE_RECOVERY_BITS;
1505 continue;
1506 }
1507 }
1508 }
1509 }
1510}
1511
1512
1513void pvr2_hdw_subsys_bit_chg(struct pvr2_hdw *hdw,
1514 unsigned long msk,unsigned long val)
1515{
1516 LOCK_TAKE(hdw->big_lock); do {
1517 pvr2_hdw_subsys_bit_chg_no_lock(hdw,msk,val);
1518 } while (0); LOCK_GIVE(hdw->big_lock);
1519}
1520
1521
d855497e
MI		 1522unsigned long pvr2_hdw_subsys_get(struct pvr2_hdw *hdw)
1523{
1524 return hdw->subsys_enabled_mask;
1525}
1526
1527
1528unsigned long pvr2_hdw_subsys_stream_get(struct pvr2_hdw *hdw)
1529{
1530 return hdw->subsys_stream_mask;
1531}
1532
1533
07e337ee
AB		 1534static void pvr2_hdw_subsys_stream_bit_chg_no_lock(struct pvr2_hdw *hdw,
1535 unsigned long msk,
1536 unsigned long val)
d855497e
MI		 1537{
1538 unsigned long val2;
1539 msk &= PVR2_SUBSYS_ALL;
1540 val2 = ((hdw->subsys_stream_mask & ~msk) | (val & msk));
1541 pvr2_trace(PVR2_TRACE_INIT,
1542 "stream mask changing 0x%lx:0x%lx from 0x%lx to 0x%lx",
1543 msk,val,hdw->subsys_stream_mask,val2);
1544 hdw->subsys_stream_mask = val2;
1545}
1546
1547
1548void pvr2_hdw_subsys_stream_bit_chg(struct pvr2_hdw *hdw,
1549 unsigned long msk,
1550 unsigned long val)
1551{
1552 LOCK_TAKE(hdw->big_lock); do {
1553 pvr2_hdw_subsys_stream_bit_chg_no_lock(hdw,msk,val);
1554 } while (0); LOCK_GIVE(hdw->big_lock);
1555}
1556
1557
07e337ee 1558static int pvr2_hdw_set_streaming_no_lock(struct pvr2_hdw *hdw,int enableFl)
d855497e
MI		 1559{
1560 if ((!enableFl) == !(hdw->flag_streaming_enabled)) return 0;
1561 if (enableFl) {
1562 pvr2_trace(PVR2_TRACE_START_STOP,
1563 "/*--TRACE_STREAM--*/ enable");
1564 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,~0);
1565 } else {
1566 pvr2_trace(PVR2_TRACE_START_STOP,
1567 "/*--TRACE_STREAM--*/ disable");
1568 pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1569 }
1570 if (!hdw->flag_ok) return -EIO;
1571 hdw->flag_streaming_enabled = enableFl != 0;
1572 return 0;
1573}
1574
1575
1576int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1577{
1578 return hdw->flag_streaming_enabled != 0;
1579}
1580
1581
1582int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1583{
1584 int ret;
1585 LOCK_TAKE(hdw->big_lock); do {
1586 ret = pvr2_hdw_set_streaming_no_lock(hdw,enable_flag);
1587 } while (0); LOCK_GIVE(hdw->big_lock);
1588 return ret;
1589}
1590
1591
07e337ee
AB		 1592static int pvr2_hdw_set_stream_type_no_lock(struct pvr2_hdw *hdw,
1593 enum pvr2_config config)
d855497e
MI		 1594{
1595 unsigned long sm = hdw->subsys_enabled_mask;
1596 if (!hdw->flag_ok) return -EIO;
1597 pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1598 hdw->config = config;
1599 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,sm);
1600 return 0;
1601}
1602
1603
1604int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1605{
1606 int ret;
1607 if (!hdw->flag_ok) return -EIO;
1608 LOCK_TAKE(hdw->big_lock);
1609 ret = pvr2_hdw_set_stream_type_no_lock(hdw,config);
1610 LOCK_GIVE(hdw->big_lock);
1611 return ret;
1612}
1613
1614
1615static int get_default_tuner_type(struct pvr2_hdw *hdw)
1616{
1617 int unit_number = hdw->unit_number;
1618 int tp = -1;
1619 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1620 tp = tuner[unit_number];
1621 }
1622 if (tp < 0) return -EINVAL;
1623 hdw->tuner_type = tp;
1624 return 0;
1625}
1626
1627
1628static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1629{
1630 int unit_number = hdw->unit_number;
1631 int tp = 0;
1632 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1633 tp = video_std[unit_number];
1634 }
1635 return tp;
1636}
1637
1638
1639static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1640{
1641 int unit_number = hdw->unit_number;
1642 int tp = 0;
1643 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1644 tp = tolerance[unit_number];
1645 }
1646 return tp;
1647}
1648
1649
1650static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1651{
1652 /* Try a harmless request to fetch the eeprom's address over
1653 endpoint 1. See what happens. Only the full FX2 image can
1654 respond to this. If this probe fails then likely the FX2
1655 firmware needs be loaded. */
1656 int result;
1657 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 1658 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 1659 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1660 hdw->cmd_buffer,1,
1661 hdw->cmd_buffer,1);
1662 if (result < 0) break;
1663 } while(0); LOCK_GIVE(hdw->ctl_lock);
1664 if (result) {
1665 pvr2_trace(PVR2_TRACE_INIT,
1666 "Probe of device endpoint 1 result status %d",
1667 result);
1668 } else {
1669 pvr2_trace(PVR2_TRACE_INIT,
1670 "Probe of device endpoint 1 succeeded");
1671 }
1672 return result == 0;
1673}
1674
1675static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1676{
1677 char buf[40];
1678 unsigned int bcnt;
1679 v4l2_std_id std1,std2;
1680
1681 std1 = get_default_standard(hdw);
1682
1683 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1684 pvr2_trace(PVR2_TRACE_INIT,
1685 "Supported video standard(s) reported by eeprom: %.*s",
1686 bcnt,buf);
1687
1688 hdw->std_mask_avail = hdw->std_mask_eeprom;
1689
1690 std2 = std1 & ~hdw->std_mask_avail;
1691 if (std2) {
1692 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1693 pvr2_trace(PVR2_TRACE_INIT,
1694 "Expanding supported video standards"
1695 " to include: %.*s",
1696 bcnt,buf);
1697 hdw->std_mask_avail |= std2;
1698 }
1699
1700 pvr2_hdw_internal_set_std_avail(hdw);
1701
1702 if (std1) {
1703 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1704 pvr2_trace(PVR2_TRACE_INIT,
1705 "Initial video standard forced to %.*s",
1706 bcnt,buf);
1707 hdw->std_mask_cur = std1;
1708 hdw->std_dirty = !0;
1709 pvr2_hdw_internal_find_stdenum(hdw);
1710 return;
1711 }
1712
1713 if (hdw->std_enum_cnt > 1) {
1714 // Autoselect the first listed standard
1715 hdw->std_enum_cur = 1;
1716 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1717 hdw->std_dirty = !0;
1718 pvr2_trace(PVR2_TRACE_INIT,
1719 "Initial video standard auto-selected to %s",
1720 hdw->std_defs[hdw->std_enum_cur-1].name);
1721 return;
1722 }
1723
0885ba1d 1724 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
d855497e
MI		 1725 "Unable to select a viable initial video standard");
1726}
1727
1728
1729static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1730{
1731 int ret;
1732 unsigned int idx;
1733 struct pvr2_ctrl *cptr;
1734 int reloadFl = 0;
1735 if (!reloadFl) {
1736 reloadFl = (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1737 == 0);
1738 if (reloadFl) {
1739 pvr2_trace(PVR2_TRACE_INIT,
1740 "USB endpoint config looks strange"
1741 "; possibly firmware needs to be loaded");
1742 }
1743 }
1744 if (!reloadFl) {
1745 reloadFl = !pvr2_hdw_check_firmware(hdw);
1746 if (reloadFl) {
1747 pvr2_trace(PVR2_TRACE_INIT,
1748 "Check for FX2 firmware failed"
1749 "; possibly firmware needs to be loaded");
1750 }
1751 }
1752 if (reloadFl) {
1753 if (pvr2_upload_firmware1(hdw) != 0) {
1754 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1755 "Failure uploading firmware1");
1756 }
1757 return;
1758 }
1759 hdw->fw1_state = FW1_STATE_OK;
1760
1761 if (initusbreset) {
1762 pvr2_hdw_device_reset(hdw);
1763 }
1764 if (!pvr2_hdw_dev_ok(hdw)) return;
1765
1766 for (idx = 0; idx < pvr2_client_lists[hdw->hdw_type].cnt; idx++) {
1767 request_module(pvr2_client_lists[hdw->hdw_type].lst[idx]);
1768 }
1769
1770 pvr2_hdw_cmd_powerup(hdw);
1771 if (!pvr2_hdw_dev_ok(hdw)) return;
1772
1773 if (pvr2_upload_firmware2(hdw)){
1774 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"device unstable!!");
1775 pvr2_hdw_render_useless(hdw);
1776 return;
1777 }
1778
1779 // This step MUST happen after the earlier powerup step.
1780 pvr2_i2c_core_init(hdw);
1781 if (!pvr2_hdw_dev_ok(hdw)) return;
1782
c05c0462 1783 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e
MI		 1784 cptr = hdw->controls + idx;
1785 if (cptr->info->skip_init) continue;
1786 if (!cptr->info->set_value) continue;
1787 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1788 }
1789
1bde0289
MI		 1790 /* Set up special default values for the television and radio
1791 frequencies here. It's not really important what these defaults
1792 are, but I set them to something usable in the Chicago area just
1793 to make driver testing a little easier. */
1794
1795 /* US Broadcast channel 7 (175.25 MHz) */
1796 hdw->freqValTelevision = 175250000L;
1797 /* 104.3 MHz, a usable FM station for my area */
1798 hdw->freqValRadio = 104300000L;
1799
d855497e
MI		 1800 // Do not use pvr2_reset_ctl_endpoints() here. It is not
1801 // thread-safe against the normal pvr2_send_request() mechanism.
1802 // (We should make it thread safe).
1803
1804 ret = pvr2_hdw_get_eeprom_addr(hdw);
1805 if (!pvr2_hdw_dev_ok(hdw)) return;
1806 if (ret < 0) {
1807 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1808 "Unable to determine location of eeprom, skipping");
1809 } else {
1810 hdw->eeprom_addr = ret;
1811 pvr2_eeprom_analyze(hdw);
1812 if (!pvr2_hdw_dev_ok(hdw)) return;
1813 }
1814
1815 pvr2_hdw_setup_std(hdw);
1816
1817 if (!get_default_tuner_type(hdw)) {
1818 pvr2_trace(PVR2_TRACE_INIT,
1819 "pvr2_hdw_setup: Tuner type overridden to %d",
1820 hdw->tuner_type);
1821 }
1822
1823 hdw->tuner_updated = !0;
1824 pvr2_i2c_core_check_stale(hdw);
1825 hdw->tuner_updated = 0;
1826
1827 if (!pvr2_hdw_dev_ok(hdw)) return;
1828
1829 pvr2_hdw_commit_ctl_internal(hdw);
1830 if (!pvr2_hdw_dev_ok(hdw)) return;
1831
1832 hdw->vid_stream = pvr2_stream_create();
1833 if (!pvr2_hdw_dev_ok(hdw)) return;
1834 pvr2_trace(PVR2_TRACE_INIT,
1835 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1836 if (hdw->vid_stream) {
1837 idx = get_default_error_tolerance(hdw);
1838 if (idx) {
1839 pvr2_trace(PVR2_TRACE_INIT,
1840 "pvr2_hdw_setup: video stream %p"
1841 " setting tolerance %u",
1842 hdw->vid_stream,idx);
1843 }
1844 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1845 PVR2_VID_ENDPOINT,idx);
1846 }
1847
1848 if (!pvr2_hdw_dev_ok(hdw)) return;
1849
1850 /* Make sure everything is up to date */
1851 pvr2_i2c_core_sync(hdw);
1852
1853 if (!pvr2_hdw_dev_ok(hdw)) return;
1854
1855 hdw->flag_init_ok = !0;
1856}
1857
1858
1859int pvr2_hdw_setup(struct pvr2_hdw *hdw)
1860{
1861 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
1862 LOCK_TAKE(hdw->big_lock); do {
1863 pvr2_hdw_setup_low(hdw);
1864 pvr2_trace(PVR2_TRACE_INIT,
1865 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
1866 hdw,hdw->flag_ok,hdw->flag_init_ok);
1867 if (pvr2_hdw_dev_ok(hdw)) {
1868 if (pvr2_hdw_init_ok(hdw)) {
1869 pvr2_trace(
1870 PVR2_TRACE_INFO,
1871 "Device initialization"
1872 " completed successfully.");
1873 break;
1874 }
1875 if (hdw->fw1_state == FW1_STATE_RELOAD) {
1876 pvr2_trace(
1877 PVR2_TRACE_INFO,
1878 "Device microcontroller firmware"
1879 " (re)loaded; it should now reset"
1880 " and reconnect.");
1881 break;
1882 }
1883 pvr2_trace(
1884 PVR2_TRACE_ERROR_LEGS,
1885 "Device initialization was not successful.");
1886 if (hdw->fw1_state == FW1_STATE_MISSING) {
1887 pvr2_trace(
1888 PVR2_TRACE_ERROR_LEGS,
1889 "Giving up since device"
1890 " microcontroller firmware"
1891 " appears to be missing.");
1892 break;
1893 }
1894 }
1895 if (procreload) {
1896 pvr2_trace(
1897 PVR2_TRACE_ERROR_LEGS,
1898 "Attempting pvrusb2 recovery by reloading"
1899 " primary firmware.");
1900 pvr2_trace(
1901 PVR2_TRACE_ERROR_LEGS,
1902 "If this works, device should disconnect"
1903 " and reconnect in a sane state.");
1904 hdw->fw1_state = FW1_STATE_UNKNOWN;
1905 pvr2_upload_firmware1(hdw);
1906 } else {
1907 pvr2_trace(
1908 PVR2_TRACE_ERROR_LEGS,
1909 "***WARNING*** pvrusb2 device hardware"
1910 " appears to be jammed"
1911 " and I can't clear it.");
1912 pvr2_trace(
1913 PVR2_TRACE_ERROR_LEGS,
1914 "You might need to power cycle"
1915 " the pvrusb2 device"
1916 " in order to recover.");
1917 }
1918 } while (0); LOCK_GIVE(hdw->big_lock);
1919 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
1920 return hdw->flag_init_ok;
1921}
1922
1923
1924/* Create and return a structure for interacting with the underlying
1925 hardware */
1926struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1927 const struct usb_device_id *devid)
1928{
1929 unsigned int idx,cnt1,cnt2;
1930 struct pvr2_hdw *hdw;
1931 unsigned int hdw_type;
1932 int valid_std_mask;
1933 struct pvr2_ctrl *cptr;
1934 __u8 ifnum;
b30d2441
MI		 1935 struct v4l2_queryctrl qctrl;
1936 struct pvr2_ctl_info *ciptr;
d855497e
MI		 1937
1938 hdw_type = devid - pvr2_device_table;
eca8ebfc 1939 if (hdw_type >= ARRAY_SIZE(pvr2_device_names)) {
d855497e
MI		 1940 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1941 "Bogus device type of %u reported",hdw_type);
a0fd1cb1 1942 return NULL;
d855497e
MI		 1943 }
1944
ca545f7c 1945 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
d855497e
MI		 1946 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
1947 hdw,pvr2_device_names[hdw_type]);
1948 if (!hdw) goto fail;
18103c57 1949 hdw->tuner_signal_stale = !0;
b30d2441 1950 cx2341x_fill_defaults(&hdw->enc_ctl_state);
d855497e 1951
c05c0462 1952 hdw->control_cnt = CTRLDEF_COUNT;
b30d2441 1953 hdw->control_cnt += MPEGDEF_COUNT;
ca545f7c 1954 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
d855497e
MI		 1955 GFP_KERNEL);
1956 if (!hdw->controls) goto fail;
d855497e 1957 hdw->hdw_type = hdw_type;
c05c0462
MI		 1958 for (idx = 0; idx < hdw->control_cnt; idx++) {
1959 cptr = hdw->controls + idx;
1960 cptr->hdw = hdw;
1961 }
d855497e
MI		 1962 for (idx = 0; idx < 32; idx++) {
1963 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
1964 }
c05c0462 1965 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e 1966 cptr = hdw->controls + idx;
d855497e
MI		 1967 cptr->info = control_defs+idx;
1968 }
b30d2441 1969 /* Define and configure additional controls from cx2341x module. */
ca545f7c 1970 hdw->mpeg_ctrl_info = kzalloc(
b30d2441
MI		 1971 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
1972 if (!hdw->mpeg_ctrl_info) goto fail;
b30d2441
MI		 1973 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
1974 cptr = hdw->controls + idx + CTRLDEF_COUNT;
1975 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
1976 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
1977 ciptr->name = mpeg_ids[idx].strid;
1978 ciptr->v4l_id = mpeg_ids[idx].id;
1979 ciptr->skip_init = !0;
1980 ciptr->get_value = ctrl_cx2341x_get;
1981 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
1982 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
1983 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
1984 qctrl.id = ciptr->v4l_id;
1985 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
1986 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
1987 ciptr->set_value = ctrl_cx2341x_set;
1988 }
1989 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
1990 PVR2_CTLD_INFO_DESC_SIZE);
1991 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
1992 ciptr->default_value = qctrl.default_value;
1993 switch (qctrl.type) {
1994 default:
1995 case V4L2_CTRL_TYPE_INTEGER:
1996 ciptr->type = pvr2_ctl_int;
1997 ciptr->def.type_int.min_value = qctrl.minimum;
1998 ciptr->def.type_int.max_value = qctrl.maximum;
1999 break;
2000 case V4L2_CTRL_TYPE_BOOLEAN:
2001 ciptr->type = pvr2_ctl_bool;
2002 break;
2003 case V4L2_CTRL_TYPE_MENU:
2004 ciptr->type = pvr2_ctl_enum;
2005 ciptr->def.type_enum.value_names =
2006 cx2341x_ctrl_get_menu(ciptr->v4l_id);
2007 for (cnt1 = 0;
2008 ciptr->def.type_enum.value_names[cnt1] != NULL;
2009 cnt1++) { }
2010 ciptr->def.type_enum.count = cnt1;
2011 break;
2012 }
2013 cptr->info = ciptr;
2014 }
d855497e
MI		 2015
2016 // Initialize video standard enum dynamic control
2017 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2018 if (cptr) {
2019 memcpy(&hdw->std_info_enum,cptr->info,
2020 sizeof(hdw->std_info_enum));
2021 cptr->info = &hdw->std_info_enum;
2022
2023 }
2024 // Initialize control data regarding video standard masks
2025 valid_std_mask = pvr2_std_get_usable();
2026 for (idx = 0; idx < 32; idx++) {
2027 if (!(valid_std_mask & (1 << idx))) continue;
2028 cnt1 = pvr2_std_id_to_str(
2029 hdw->std_mask_names[idx],
2030 sizeof(hdw->std_mask_names[idx])-1,
2031 1 << idx);
2032 hdw->std_mask_names[idx][cnt1] = 0;
2033 }
2034 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2035 if (cptr) {
2036 memcpy(&hdw->std_info_avail,cptr->info,
2037 sizeof(hdw->std_info_avail));
2038 cptr->info = &hdw->std_info_avail;
2039 hdw->std_info_avail.def.type_bitmask.bit_names =
2040 hdw->std_mask_ptrs;
2041 hdw->std_info_avail.def.type_bitmask.valid_bits =
2042 valid_std_mask;
2043 }
2044 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2045 if (cptr) {
2046 memcpy(&hdw->std_info_cur,cptr->info,
2047 sizeof(hdw->std_info_cur));
2048 cptr->info = &hdw->std_info_cur;
2049 hdw->std_info_cur.def.type_bitmask.bit_names =
2050 hdw->std_mask_ptrs;
2051 hdw->std_info_avail.def.type_bitmask.valid_bits =
2052 valid_std_mask;
2053 }
2054
2055 hdw->eeprom_addr = -1;
2056 hdw->unit_number = -1;
8079384e
MI		 2057 hdw->v4l_minor_number_video = -1;
2058 hdw->v4l_minor_number_vbi = -1;
fd5a75fe 2059 hdw->v4l_minor_number_radio = -1;
d855497e
MI		 2060 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2061 if (!hdw->ctl_write_buffer) goto fail;
2062 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2063 if (!hdw->ctl_read_buffer) goto fail;
2064 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2065 if (!hdw->ctl_write_urb) goto fail;
2066 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2067 if (!hdw->ctl_read_urb) goto fail;
2068
2069 down(&pvr2_unit_sem); do {
2070 for (idx = 0; idx < PVR_NUM; idx++) {
2071 if (unit_pointers[idx]) continue;
2072 hdw->unit_number = idx;
2073 unit_pointers[idx] = hdw;
2074 break;
2075 }
2076 } while (0); up(&pvr2_unit_sem);
2077
2078 cnt1 = 0;
2079 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2080 cnt1 += cnt2;
2081 if (hdw->unit_number >= 0) {
2082 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2083 ('a' + hdw->unit_number));
2084 cnt1 += cnt2;
2085 }
2086 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2087 hdw->name[cnt1] = 0;
2088
2089 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2090 hdw->unit_number,hdw->name);
2091
2092 hdw->tuner_type = -1;
2093 hdw->flag_ok = !0;
2094 /* Initialize the mask of subsystems that we will shut down when we
2095 stop streaming. */
2096 hdw->subsys_stream_mask = PVR2_SUBSYS_RUN_ALL;
2097 hdw->subsys_stream_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
2098
2099 pvr2_trace(PVR2_TRACE_INIT,"subsys_stream_mask: 0x%lx",
2100 hdw->subsys_stream_mask);
2101
2102 hdw->usb_intf = intf;
2103 hdw->usb_dev = interface_to_usbdev(intf);
2104
2105 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2106 usb_set_interface(hdw->usb_dev,ifnum,0);
2107
2108 mutex_init(&hdw->ctl_lock_mutex);
2109 mutex_init(&hdw->big_lock_mutex);
2110
2111 return hdw;
2112 fail:
2113 if (hdw) {
5e55d2ce
MK		 2114 usb_free_urb(hdw->ctl_read_urb);
2115 usb_free_urb(hdw->ctl_write_urb);
22071a42
MK		 2116 kfree(hdw->ctl_read_buffer);
2117 kfree(hdw->ctl_write_buffer);
2118 kfree(hdw->controls);
2119 kfree(hdw->mpeg_ctrl_info);
d855497e
MI		 2120 kfree(hdw);
2121 }
a0fd1cb1 2122 return NULL;
d855497e
MI		 2123}
2124
2125
2126/* Remove _all_ associations between this driver and the underlying USB
2127 layer. */
07e337ee 2128static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
d855497e
MI		 2129{
2130 if (hdw->flag_disconnected) return;
2131 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2132 if (hdw->ctl_read_urb) {
2133 usb_kill_urb(hdw->ctl_read_urb);
2134 usb_free_urb(hdw->ctl_read_urb);
a0fd1cb1 2135 hdw->ctl_read_urb = NULL;
d855497e
MI		 2136 }
2137 if (hdw->ctl_write_urb) {
2138 usb_kill_urb(hdw->ctl_write_urb);
2139 usb_free_urb(hdw->ctl_write_urb);
a0fd1cb1 2140 hdw->ctl_write_urb = NULL;
d855497e
MI		 2141 }
2142 if (hdw->ctl_read_buffer) {
2143 kfree(hdw->ctl_read_buffer);
a0fd1cb1 2144 hdw->ctl_read_buffer = NULL;
d855497e
MI		 2145 }
2146 if (hdw->ctl_write_buffer) {
2147 kfree(hdw->ctl_write_buffer);
a0fd1cb1 2148 hdw->ctl_write_buffer = NULL;
d855497e
MI		 2149 }
2150 pvr2_hdw_render_useless_unlocked(hdw);
2151 hdw->flag_disconnected = !0;
a0fd1cb1
MI		 2152 hdw->usb_dev = NULL;
2153 hdw->usb_intf = NULL;
d855497e
MI		 2154}
2155
2156
2157/* Destroy hardware interaction structure */
2158void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2159{
2160 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2161 if (hdw->fw_buffer) {
2162 kfree(hdw->fw_buffer);
a0fd1cb1 2163 hdw->fw_buffer = NULL;
d855497e
MI		 2164 }
2165 if (hdw->vid_stream) {
2166 pvr2_stream_destroy(hdw->vid_stream);
a0fd1cb1 2167 hdw->vid_stream = NULL;
d855497e 2168 }
d855497e
MI		 2169 if (hdw->decoder_ctrl) {
2170 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2171 }
2172 pvr2_i2c_core_done(hdw);
2173 pvr2_hdw_remove_usb_stuff(hdw);
2174 down(&pvr2_unit_sem); do {
2175 if ((hdw->unit_number >= 0) &&
2176 (hdw->unit_number < PVR_NUM) &&
2177 (unit_pointers[hdw->unit_number] == hdw)) {
a0fd1cb1 2178 unit_pointers[hdw->unit_number] = NULL;
d855497e
MI		 2179 }
2180 } while (0); up(&pvr2_unit_sem);
22071a42
MK		 2181 kfree(hdw->controls);
2182 kfree(hdw->mpeg_ctrl_info);
2183 kfree(hdw->std_defs);
2184 kfree(hdw->std_enum_names);
d855497e
MI		 2185 kfree(hdw);
2186}
2187
2188
2189int pvr2_hdw_init_ok(struct pvr2_hdw *hdw)
2190{
2191 return hdw->flag_init_ok;
2192}
2193
2194
2195int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2196{
2197 return (hdw && hdw->flag_ok);
2198}
2199
2200
2201/* Called when hardware has been unplugged */
2202void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2203{
2204 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2205 LOCK_TAKE(hdw->big_lock);
2206 LOCK_TAKE(hdw->ctl_lock);
2207 pvr2_hdw_remove_usb_stuff(hdw);
2208 LOCK_GIVE(hdw->ctl_lock);
2209 LOCK_GIVE(hdw->big_lock);
2210}
2211
2212
2213// Attempt to autoselect an appropriate value for std_enum_cur given
2214// whatever is currently in std_mask_cur
07e337ee 2215static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
d855497e
MI		 2216{
2217 unsigned int idx;
2218 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2219 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2220 hdw->std_enum_cur = idx;
2221 return;
2222 }
2223 }
2224 hdw->std_enum_cur = 0;
2225}
2226
2227
2228// Calculate correct set of enumerated standards based on currently known
2229// set of available standards bits.
07e337ee 2230static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
d855497e
MI		 2231{
2232 struct v4l2_standard *newstd;
2233 unsigned int std_cnt;
2234 unsigned int idx;
2235
2236 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2237
2238 if (hdw->std_defs) {
2239 kfree(hdw->std_defs);
a0fd1cb1 2240 hdw->std_defs = NULL;
d855497e
MI		 2241 }
2242 hdw->std_enum_cnt = 0;
2243 if (hdw->std_enum_names) {
2244 kfree(hdw->std_enum_names);
a0fd1cb1 2245 hdw->std_enum_names = NULL;
d855497e
MI		 2246 }
2247
2248 if (!std_cnt) {
2249 pvr2_trace(
2250 PVR2_TRACE_ERROR_LEGS,
2251 "WARNING: Failed to identify any viable standards");
2252 }
2253 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2254 hdw->std_enum_names[0] = "none";
2255 for (idx = 0; idx < std_cnt; idx++) {
2256 hdw->std_enum_names[idx+1] =
2257 newstd[idx].name;
2258 }
2259 // Set up the dynamic control for this standard
2260 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2261 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2262 hdw->std_defs = newstd;
2263 hdw->std_enum_cnt = std_cnt+1;
2264 hdw->std_enum_cur = 0;
2265 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2266}
2267
2268
2269int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2270 struct v4l2_standard *std,
2271 unsigned int idx)
2272{
2273 int ret = -EINVAL;
2274 if (!idx) return ret;
2275 LOCK_TAKE(hdw->big_lock); do {
2276 if (idx >= hdw->std_enum_cnt) break;
2277 idx--;
2278 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2279 ret = 0;
2280 } while (0); LOCK_GIVE(hdw->big_lock);
2281 return ret;
2282}
2283
2284
2285/* Get the number of defined controls */
2286unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2287{
c05c0462 2288 return hdw->control_cnt;
d855497e
MI		 2289}
2290
2291
2292/* Retrieve a control handle given its index (0..count-1) */
2293struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2294 unsigned int idx)
2295{
a0fd1cb1 2296 if (idx >= hdw->control_cnt) return NULL;
d855497e
MI		 2297 return hdw->controls + idx;
2298}
2299
2300
2301/* Retrieve a control handle given its index (0..count-1) */
2302struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2303 unsigned int ctl_id)
2304{
2305 struct pvr2_ctrl *cptr;
2306 unsigned int idx;
2307 int i;
2308
2309 /* This could be made a lot more efficient, but for now... */
c05c0462 2310 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2311 cptr = hdw->controls + idx;
2312 i = cptr->info->internal_id;
2313 if (i && (i == ctl_id)) return cptr;
2314 }
a0fd1cb1 2315 return NULL;
d855497e
MI		 2316}
2317
2318
a761f431 2319/* Given a V4L ID, retrieve the control structure associated with it. */
d855497e
MI		 2320struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2321{
2322 struct pvr2_ctrl *cptr;
2323 unsigned int idx;
2324 int i;
2325
2326 /* This could be made a lot more efficient, but for now... */
c05c0462 2327 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2328 cptr = hdw->controls + idx;
2329 i = cptr->info->v4l_id;
2330 if (i && (i == ctl_id)) return cptr;
2331 }
a0fd1cb1 2332 return NULL;
d855497e
MI		 2333}
2334
2335
a761f431
MI		 2336/* Given a V4L ID for its immediate predecessor, retrieve the control
2337 structure associated with it. */
2338struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2339 unsigned int ctl_id)
2340{
2341 struct pvr2_ctrl *cptr,*cp2;
2342 unsigned int idx;
2343 int i;
2344
2345 /* This could be made a lot more efficient, but for now... */
a0fd1cb1 2346 cp2 = NULL;
a761f431
MI		 2347 for (idx = 0; idx < hdw->control_cnt; idx++) {
2348 cptr = hdw->controls + idx;
2349 i = cptr->info->v4l_id;
2350 if (!i) continue;
2351 if (i <= ctl_id) continue;
2352 if (cp2 && (cp2->info->v4l_id < i)) continue;
2353 cp2 = cptr;
2354 }
2355 return cp2;
a0fd1cb1 2356 return NULL;
a761f431
MI		 2357}
2358
2359
d855497e
MI		 2360static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2361{
2362 switch (tp) {
2363 case pvr2_ctl_int: return "integer";
2364 case pvr2_ctl_enum: return "enum";
33213963 2365 case pvr2_ctl_bool: return "boolean";
d855497e
MI		 2366 case pvr2_ctl_bitmask: return "bitmask";
2367 }
2368 return "";
2369}
2370
2371
2372/* Commit all control changes made up to this point. Subsystems can be
2373 indirectly affected by these changes. For a given set of things being
2374 committed, we'll clear the affected subsystem bits and then once we're
2375 done committing everything we'll make a request to restore the subsystem
2376 state(s) back to their previous value before this function was called.
2377 Thus we can automatically reconfigure affected pieces of the driver as
2378 controls are changed. */
07e337ee 2379static int pvr2_hdw_commit_ctl_internal(struct pvr2_hdw *hdw)
d855497e
MI		 2380{
2381 unsigned long saved_subsys_mask = hdw->subsys_enabled_mask;
2382 unsigned long stale_subsys_mask = 0;
2383 unsigned int idx;
2384 struct pvr2_ctrl *cptr;
2385 int value;
2386 int commit_flag = 0;
2387 char buf[100];
2388 unsigned int bcnt,ccnt;
2389
c05c0462 2390 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2391 cptr = hdw->controls + idx;
2392 if (cptr->info->is_dirty == 0) continue;
2393 if (!cptr->info->is_dirty(cptr)) continue;
fe23a280 2394 commit_flag = !0;
d855497e 2395
fe23a280 2396 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
d855497e
MI		 2397 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2398 cptr->info->name);
2399 value = 0;
2400 cptr->info->get_value(cptr,&value);
2401 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2402 buf+bcnt,
2403 sizeof(buf)-bcnt,&ccnt);
2404 bcnt += ccnt;
2405 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2406 get_ctrl_typename(cptr->info->type));
2407 pvr2_trace(PVR2_TRACE_CTL,
2408 "/*--TRACE_COMMIT--*/ %.*s",
2409 bcnt,buf);
2410 }
2411
2412 if (!commit_flag) {
2413 /* Nothing has changed */
2414 return 0;
2415 }
2416
2417 /* When video standard changes, reset the hres and vres values -
2418 but if the user has pending changes there, then let the changes
2419 take priority. */
2420 if (hdw->std_dirty) {
2421 /* Rewrite the vertical resolution to be appropriate to the
2422 video standard that has been selected. */
2423 int nvres;
2424 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2425 nvres = 480;
2426 } else {
2427 nvres = 576;
2428 }
2429 if (nvres != hdw->res_ver_val) {
2430 hdw->res_ver_val = nvres;
2431 hdw->res_ver_dirty = !0;
2432 }
d855497e
MI		 2433 }
2434
2435 if (hdw->std_dirty ||
434449f4
MI		 2436 hdw->enc_stale ||
2437 hdw->srate_dirty ||
2438 hdw->res_ver_dirty ||
2439 hdw->res_hor_dirty ||
b46cfa80 2440 0) {
d855497e
MI		 2441 /* If any of this changes, then the encoder needs to be
2442 reconfigured, and we need to reset the stream. */
2443 stale_subsys_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
d855497e
MI		 2444 }
2445
275b2e28
PK		 2446 if (hdw->input_dirty) {
2447 /* pk: If input changes to or from radio, then the encoder
2448 needs to be restarted (for ENC_MUTE_VIDEO to work) */
2449 stale_subsys_mask |= (1<<PVR2_SUBSYS_B_ENC_RUN);
2450 }
2451
2452
b30d2441
MI		 2453 if (hdw->srate_dirty) {
2454 /* Write new sample rate into control structure since
2455 * the master copy is stale. We must track srate
2456 * separate from the mpeg control structure because
2457 * other logic also uses this value. */
2458 struct v4l2_ext_controls cs;
2459 struct v4l2_ext_control c1;
2460 memset(&cs,0,sizeof(cs));
2461 memset(&c1,0,sizeof(c1));
2462 cs.controls = &c1;
2463 cs.count = 1;
2464 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
2465 c1.value = hdw->srate_val;
2466 cx2341x_ext_ctrls(&hdw->enc_ctl_state,&cs,VIDIOC_S_EXT_CTRLS);
2467 }
c05c0462 2468
d855497e
MI		 2469 /* Scan i2c core at this point - before we clear all the dirty
2470 bits. Various parts of the i2c core will notice dirty bits as
2471 appropriate and arrange to broadcast or directly send updates to
2472 the client drivers in order to keep everything in sync */
2473 pvr2_i2c_core_check_stale(hdw);
2474
c05c0462 2475 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2476 cptr = hdw->controls + idx;
2477 if (!cptr->info->clear_dirty) continue;
2478 cptr->info->clear_dirty(cptr);
2479 }
2480
2481 /* Now execute i2c core update */
2482 pvr2_i2c_core_sync(hdw);
2483
2484 pvr2_hdw_subsys_bit_chg_no_lock(hdw,stale_subsys_mask,0);
2485 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,saved_subsys_mask);
2486
2487 return 0;
2488}
2489
2490
2491int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2492{
2493 LOCK_TAKE(hdw->big_lock); do {
2494 pvr2_hdw_commit_ctl_internal(hdw);
2495 } while (0); LOCK_GIVE(hdw->big_lock);
2496 return 0;
2497}
2498
2499
2500void pvr2_hdw_poll(struct pvr2_hdw *hdw)
2501{
2502 LOCK_TAKE(hdw->big_lock); do {
2503 pvr2_i2c_core_sync(hdw);
2504 } while (0); LOCK_GIVE(hdw->big_lock);
2505}
2506
2507
2508void pvr2_hdw_setup_poll_trigger(struct pvr2_hdw *hdw,
2509 void (*func)(void *),
2510 void *data)
2511{
2512 LOCK_TAKE(hdw->big_lock); do {
2513 hdw->poll_trigger_func = func;
2514 hdw->poll_trigger_data = data;
2515 } while (0); LOCK_GIVE(hdw->big_lock);
2516}
2517
2518
2519void pvr2_hdw_poll_trigger_unlocked(struct pvr2_hdw *hdw)
2520{
2521 if (hdw->poll_trigger_func) {
2522 hdw->poll_trigger_func(hdw->poll_trigger_data);
2523 }
2524}
2525
d855497e
MI		 2526/* Return name for this driver instance */
2527const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2528{
2529 return hdw->name;
2530}
2531
2532
d855497e
MI		 2533int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2534{
2535 int result;
2536 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 2537 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
d855497e
MI		 2538 result = pvr2_send_request(hdw,
2539 hdw->cmd_buffer,1,
2540 hdw->cmd_buffer,1);
2541 if (result < 0) break;
2542 result = (hdw->cmd_buffer[0] != 0);
2543 } while(0); LOCK_GIVE(hdw->ctl_lock);
2544 return result;
2545}
2546
2547
18103c57
MI		 2548/* Execute poll of tuner status */
2549void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
d855497e 2550{
d855497e 2551 LOCK_TAKE(hdw->big_lock); do {
18103c57 2552 pvr2_i2c_core_status_poll(hdw);
d855497e 2553 } while (0); LOCK_GIVE(hdw->big_lock);
18103c57
MI		 2554}
2555
2556
2557/* Return information about the tuner */
2558int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
2559{
2560 LOCK_TAKE(hdw->big_lock); do {
2561 if (hdw->tuner_signal_stale) {
2562 pvr2_i2c_core_status_poll(hdw);
2563 }
2564 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
2565 } while (0); LOCK_GIVE(hdw->big_lock);
2566 return 0;
d855497e
MI		 2567}
2568
2569
2570/* Get handle to video output stream */
2571struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2572{
2573 return hp->vid_stream;
2574}
2575
2576
2577void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2578{
4f1a3e5b 2579 int nr = pvr2_hdw_get_unit_number(hdw);
d855497e
MI		 2580 LOCK_TAKE(hdw->big_lock); do {
2581 hdw->log_requested = !0;
4f1a3e5b 2582 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
d855497e
MI		 2583 pvr2_i2c_core_check_stale(hdw);
2584 hdw->log_requested = 0;
2585 pvr2_i2c_core_sync(hdw);
b30d2441 2586 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
99eb44fe 2587 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
4f1a3e5b 2588 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
d855497e
MI		 2589 } while (0); LOCK_GIVE(hdw->big_lock);
2590}
2591
2592void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw, int enable_flag)
2593{
2594 int ret;
2595 u16 address;
2596 unsigned int pipe;
2597 LOCK_TAKE(hdw->big_lock); do {
2598 if ((hdw->fw_buffer == 0) == !enable_flag) break;
2599
2600 if (!enable_flag) {
2601 pvr2_trace(PVR2_TRACE_FIRMWARE,
2602 "Cleaning up after CPU firmware fetch");
2603 kfree(hdw->fw_buffer);
a0fd1cb1 2604 hdw->fw_buffer = NULL;
d855497e
MI		 2605 hdw->fw_size = 0;
2606 /* Now release the CPU. It will disconnect and
2607 reconnect later. */
2608 pvr2_hdw_cpureset_assert(hdw,0);
2609 break;
2610 }
2611
2612 pvr2_trace(PVR2_TRACE_FIRMWARE,
2613 "Preparing to suck out CPU firmware");
2614 hdw->fw_size = 0x2000;
ca545f7c 2615 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
d855497e
MI		 2616 if (!hdw->fw_buffer) {
2617 hdw->fw_size = 0;
2618 break;
2619 }
2620
d855497e
MI		 2621 /* We have to hold the CPU during firmware upload. */
2622 pvr2_hdw_cpureset_assert(hdw,1);
2623
2624 /* download the firmware from address 0000-1fff in 2048
2625 (=0x800) bytes chunk. */
2626
2627 pvr2_trace(PVR2_TRACE_FIRMWARE,"Grabbing CPU firmware");
2628 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2629 for(address = 0; address < hdw->fw_size; address += 0x800) {
2630 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0xc0,
2631 address,0,
2632 hdw->fw_buffer+address,0x800,HZ);
2633 if (ret < 0) break;
2634 }
2635
2636 pvr2_trace(PVR2_TRACE_FIRMWARE,"Done grabbing CPU firmware");
2637
2638 } while (0); LOCK_GIVE(hdw->big_lock);
2639}
2640
2641
2642/* Return true if we're in a mode for retrieval CPU firmware */
2643int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2644{
2645 return hdw->fw_buffer != 0;
2646}
2647
2648
2649int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2650 char *buf,unsigned int cnt)
2651{
2652 int ret = -EINVAL;
2653 LOCK_TAKE(hdw->big_lock); do {
2654 if (!buf) break;
2655 if (!cnt) break;
2656
2657 if (!hdw->fw_buffer) {
2658 ret = -EIO;
2659 break;
2660 }
2661
2662 if (offs >= hdw->fw_size) {
2663 pvr2_trace(PVR2_TRACE_FIRMWARE,
2664 "Read firmware data offs=%d EOF",
2665 offs);
2666 ret = 0;
2667 break;
2668 }
2669
2670 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2671
2672 memcpy(buf,hdw->fw_buffer+offs,cnt);
2673
2674 pvr2_trace(PVR2_TRACE_FIRMWARE,
2675 "Read firmware data offs=%d cnt=%d",
2676 offs,cnt);
2677 ret = cnt;
2678 } while (0); LOCK_GIVE(hdw->big_lock);
2679
2680 return ret;
2681}
2682
2683
fd5a75fe 2684int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
8079384e 2685 enum pvr2_v4l_type index)
d855497e 2686{
fd5a75fe 2687 switch (index) {
8079384e
MI		 2688 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
2689 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
2690 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
fd5a75fe
MI		 2691 default: return -1;
2692 }
d855497e
MI		 2693}
2694
2695
2fdf3d9c 2696/* Store a v4l minor device number */
fd5a75fe 2697void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
8079384e 2698 enum pvr2_v4l_type index,int v)
d855497e 2699{
fd5a75fe 2700 switch (index) {
8079384e
MI		 2701 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
2702 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
2703 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
fd5a75fe
MI		 2704 default: break;
2705 }
d855497e
MI		 2706}
2707
2708
7d12e780 2709static void pvr2_ctl_write_complete(struct urb *urb)
d855497e
MI		 2710{
2711 struct pvr2_hdw *hdw = urb->context;
2712 hdw->ctl_write_pend_flag = 0;
2713 if (hdw->ctl_read_pend_flag) return;
2714 complete(&hdw->ctl_done);
2715}
2716
2717
7d12e780 2718static void pvr2_ctl_read_complete(struct urb *urb)
d855497e
MI		 2719{
2720 struct pvr2_hdw *hdw = urb->context;
2721 hdw->ctl_read_pend_flag = 0;
2722 if (hdw->ctl_write_pend_flag) return;
2723 complete(&hdw->ctl_done);
2724}
2725
2726
2727static void pvr2_ctl_timeout(unsigned long data)
2728{
2729 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2730 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2731 hdw->ctl_timeout_flag = !0;
5e55d2ce 2732 if (hdw->ctl_write_pend_flag)
d855497e 2733 usb_unlink_urb(hdw->ctl_write_urb);
5e55d2ce 2734 if (hdw->ctl_read_pend_flag)
d855497e 2735 usb_unlink_urb(hdw->ctl_read_urb);
d855497e
MI		 2736 }
2737}
2738
2739
e61b6fc5
MI		 2740/* Issue a command and get a response from the device. This extended
2741 version includes a probe flag (which if set means that device errors
2742 should not be logged or treated as fatal) and a timeout in jiffies.
2743 This can be used to non-lethally probe the health of endpoint 1. */
07e337ee
AB		 2744static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2745 unsigned int timeout,int probe_fl,
2746 void *write_data,unsigned int write_len,
2747 void *read_data,unsigned int read_len)
d855497e
MI		 2748{
2749 unsigned int idx;
2750 int status = 0;
2751 struct timer_list timer;
2752 if (!hdw->ctl_lock_held) {
2753 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2754 "Attempted to execute control transfer"
2755 " without lock!!");
2756 return -EDEADLK;
2757 }
2758 if ((!hdw->flag_ok) && !probe_fl) {
2759 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2760 "Attempted to execute control transfer"
2761 " when device not ok");
2762 return -EIO;
2763 }
2764 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2765 if (!probe_fl) {
2766 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2767 "Attempted to execute control transfer"
2768 " when USB is disconnected");
2769 }
2770 return -ENOTTY;
2771 }
2772
2773 /* Ensure that we have sane parameters */
2774 if (!write_data) write_len = 0;
2775 if (!read_data) read_len = 0;
2776 if (write_len > PVR2_CTL_BUFFSIZE) {
2777 pvr2_trace(
2778 PVR2_TRACE_ERROR_LEGS,
2779 "Attempted to execute %d byte"
2780 " control-write transfer (limit=%d)",
2781 write_len,PVR2_CTL_BUFFSIZE);
2782 return -EINVAL;
2783 }
2784 if (read_len > PVR2_CTL_BUFFSIZE) {
2785 pvr2_trace(
2786 PVR2_TRACE_ERROR_LEGS,
2787 "Attempted to execute %d byte"
2788 " control-read transfer (limit=%d)",
2789 write_len,PVR2_CTL_BUFFSIZE);
2790 return -EINVAL;
2791 }
2792 if ((!write_len) && (!read_len)) {
2793 pvr2_trace(
2794 PVR2_TRACE_ERROR_LEGS,
2795 "Attempted to execute null control transfer?");
2796 return -EINVAL;
2797 }
2798
2799
2800 hdw->cmd_debug_state = 1;
2801 if (write_len) {
2802 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
2803 } else {
2804 hdw->cmd_debug_code = 0;
2805 }
2806 hdw->cmd_debug_write_len = write_len;
2807 hdw->cmd_debug_read_len = read_len;
2808
2809 /* Initialize common stuff */
2810 init_completion(&hdw->ctl_done);
2811 hdw->ctl_timeout_flag = 0;
2812 hdw->ctl_write_pend_flag = 0;
2813 hdw->ctl_read_pend_flag = 0;
2814 init_timer(&timer);
2815 timer.expires = jiffies + timeout;
2816 timer.data = (unsigned long)hdw;
2817 timer.function = pvr2_ctl_timeout;
2818
2819 if (write_len) {
2820 hdw->cmd_debug_state = 2;
2821 /* Transfer write data to internal buffer */
2822 for (idx = 0; idx < write_len; idx++) {
2823 hdw->ctl_write_buffer[idx] =
2824 ((unsigned char *)write_data)[idx];
2825 }
2826 /* Initiate a write request */
2827 usb_fill_bulk_urb(hdw->ctl_write_urb,
2828 hdw->usb_dev,
2829 usb_sndbulkpipe(hdw->usb_dev,
2830 PVR2_CTL_WRITE_ENDPOINT),
2831 hdw->ctl_write_buffer,
2832 write_len,
2833 pvr2_ctl_write_complete,
2834 hdw);
2835 hdw->ctl_write_urb->actual_length = 0;
2836 hdw->ctl_write_pend_flag = !0;
2837 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
2838 if (status < 0) {
2839 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2840 "Failed to submit write-control"
2841 " URB status=%d",status);
2842 hdw->ctl_write_pend_flag = 0;
2843 goto done;
2844 }
2845 }
2846
2847 if (read_len) {
2848 hdw->cmd_debug_state = 3;
2849 memset(hdw->ctl_read_buffer,0x43,read_len);
2850 /* Initiate a read request */
2851 usb_fill_bulk_urb(hdw->ctl_read_urb,
2852 hdw->usb_dev,
2853 usb_rcvbulkpipe(hdw->usb_dev,
2854 PVR2_CTL_READ_ENDPOINT),
2855 hdw->ctl_read_buffer,
2856 read_len,
2857 pvr2_ctl_read_complete,
2858 hdw);
2859 hdw->ctl_read_urb->actual_length = 0;
2860 hdw->ctl_read_pend_flag = !0;
2861 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
2862 if (status < 0) {
2863 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2864 "Failed to submit read-control"
2865 " URB status=%d",status);
2866 hdw->ctl_read_pend_flag = 0;
2867 goto done;
2868 }
2869 }
2870
2871 /* Start timer */
2872 add_timer(&timer);
2873
2874 /* Now wait for all I/O to complete */
2875 hdw->cmd_debug_state = 4;
2876 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2877 wait_for_completion(&hdw->ctl_done);
2878 }
2879 hdw->cmd_debug_state = 5;
2880
2881 /* Stop timer */
2882 del_timer_sync(&timer);
2883
2884 hdw->cmd_debug_state = 6;
2885 status = 0;
2886
2887 if (hdw->ctl_timeout_flag) {
2888 status = -ETIMEDOUT;
2889 if (!probe_fl) {
2890 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2891 "Timed out control-write");
2892 }
2893 goto done;
2894 }
2895
2896 if (write_len) {
2897 /* Validate results of write request */
2898 if ((hdw->ctl_write_urb->status != 0) &&
2899 (hdw->ctl_write_urb->status != -ENOENT) &&
2900 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
2901 (hdw->ctl_write_urb->status != -ECONNRESET)) {
2902 /* USB subsystem is reporting some kind of failure
2903 on the write */
2904 status = hdw->ctl_write_urb->status;
2905 if (!probe_fl) {
2906 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2907 "control-write URB failure,"
2908 " status=%d",
2909 status);
2910 }
2911 goto done;
2912 }
2913 if (hdw->ctl_write_urb->actual_length < write_len) {
2914 /* Failed to write enough data */
2915 status = -EIO;
2916 if (!probe_fl) {
2917 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2918 "control-write URB short,"
2919 " expected=%d got=%d",
2920 write_len,
2921 hdw->ctl_write_urb->actual_length);
2922 }
2923 goto done;
2924 }
2925 }
2926 if (read_len) {
2927 /* Validate results of read request */
2928 if ((hdw->ctl_read_urb->status != 0) &&
2929 (hdw->ctl_read_urb->status != -ENOENT) &&
2930 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
2931 (hdw->ctl_read_urb->status != -ECONNRESET)) {
2932 /* USB subsystem is reporting some kind of failure
2933 on the read */
2934 status = hdw->ctl_read_urb->status;
2935 if (!probe_fl) {
2936 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2937 "control-read URB failure,"
2938 " status=%d",
2939 status);
2940 }
2941 goto done;
2942 }
2943 if (hdw->ctl_read_urb->actual_length < read_len) {
2944 /* Failed to read enough data */
2945 status = -EIO;
2946 if (!probe_fl) {
2947 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2948 "control-read URB short,"
2949 " expected=%d got=%d",
2950 read_len,
2951 hdw->ctl_read_urb->actual_length);
2952 }
2953 goto done;
2954 }
2955 /* Transfer retrieved data out from internal buffer */
2956 for (idx = 0; idx < read_len; idx++) {
2957 ((unsigned char *)read_data)[idx] =
2958 hdw->ctl_read_buffer[idx];
2959 }
2960 }
2961
2962 done:
2963
2964 hdw->cmd_debug_state = 0;
2965 if ((status < 0) && (!probe_fl)) {
2966 pvr2_hdw_render_useless_unlocked(hdw);
2967 }
2968 return status;
2969}
2970
2971
2972int pvr2_send_request(struct pvr2_hdw *hdw,
2973 void *write_data,unsigned int write_len,
2974 void *read_data,unsigned int read_len)
2975{
2976 return pvr2_send_request_ex(hdw,HZ*4,0,
2977 write_data,write_len,
2978 read_data,read_len);
2979}
2980
2981int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
2982{
2983 int ret;
2984
2985 LOCK_TAKE(hdw->ctl_lock);
2986
8d364363 2987 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
d855497e
MI		 2988 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
2989 hdw->cmd_buffer[5] = 0;
2990 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
2991 hdw->cmd_buffer[7] = reg & 0xff;
2992
2993
2994 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
2995
2996 LOCK_GIVE(hdw->ctl_lock);
2997
2998 return ret;
2999}
3000
3001
07e337ee 3002static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
d855497e
MI		 3003{
3004 int ret = 0;
3005
3006 LOCK_TAKE(hdw->ctl_lock);
3007
8d364363 3008 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
d855497e
MI		 3009 hdw->cmd_buffer[1] = 0;
3010 hdw->cmd_buffer[2] = 0;
3011 hdw->cmd_buffer[3] = 0;
3012 hdw->cmd_buffer[4] = 0;
3013 hdw->cmd_buffer[5] = 0;
3014 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3015 hdw->cmd_buffer[7] = reg & 0xff;
3016
3017 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3018 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3019
3020 LOCK_GIVE(hdw->ctl_lock);
3021
3022 return ret;
3023}
3024
3025
07e337ee 3026static void pvr2_hdw_render_useless_unlocked(struct pvr2_hdw *hdw)
d855497e
MI		 3027{
3028 if (!hdw->flag_ok) return;
3029 pvr2_trace(PVR2_TRACE_INIT,"render_useless");
3030 hdw->flag_ok = 0;
3031 if (hdw->vid_stream) {
a0fd1cb1 3032 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
d855497e
MI		 3033 }
3034 hdw->flag_streaming_enabled = 0;
3035 hdw->subsys_enabled_mask = 0;
3036}
3037
3038
3039void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3040{
3041 LOCK_TAKE(hdw->ctl_lock);
3042 pvr2_hdw_render_useless_unlocked(hdw);
3043 LOCK_GIVE(hdw->ctl_lock);
3044}
3045
3046
3047void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3048{
3049 int ret;
3050 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
a0fd1cb1 3051 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
d855497e
MI		 3052 if (ret == 1) {
3053 ret = usb_reset_device(hdw->usb_dev);
3054 usb_unlock_device(hdw->usb_dev);
3055 } else {
3056 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3057 "Failed to lock USB device ret=%d",ret);
3058 }
3059 if (init_pause_msec) {
3060 pvr2_trace(PVR2_TRACE_INFO,
3061 "Waiting %u msec for hardware to settle",
3062 init_pause_msec);
3063 msleep(init_pause_msec);
3064 }
3065
3066}
3067
3068
3069void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3070{
3071 char da[1];
3072 unsigned int pipe;
3073 int ret;
3074
3075 if (!hdw->usb_dev) return;
3076
3077 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3078
3079 da[0] = val ? 0x01 : 0x00;
3080
3081 /* Write the CPUCS register on the 8051. The lsb of the register
3082 is the reset bit; a 1 asserts reset while a 0 clears it. */
3083 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3084 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3085 if (ret < 0) {
3086 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3087 "cpureset_assert(%d) error=%d",val,ret);
3088 pvr2_hdw_render_useless(hdw);
3089 }
3090}
3091
3092
3093int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
3094{
3095 int status;
3096 LOCK_TAKE(hdw->ctl_lock); do {
3097 pvr2_trace(PVR2_TRACE_INIT,"Requesting uproc hard reset");
3098 hdw->flag_ok = !0;
8d364363 3099 hdw->cmd_buffer[0] = FX2CMD_DEEP_RESET;
a0fd1cb1 3100 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
d855497e
MI		 3101 } while (0); LOCK_GIVE(hdw->ctl_lock);
3102 return status;
3103}
3104
3105
3106int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
3107{
3108 int status;
3109 LOCK_TAKE(hdw->ctl_lock); do {
3110 pvr2_trace(PVR2_TRACE_INIT,"Requesting powerup");
8d364363 3111 hdw->cmd_buffer[0] = FX2CMD_POWER_ON;
a0fd1cb1 3112 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
d855497e
MI		 3113 } while (0); LOCK_GIVE(hdw->ctl_lock);
3114 return status;
3115}
3116
3117
3118int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
3119{
3120 if (!hdw->decoder_ctrl) {
3121 pvr2_trace(PVR2_TRACE_INIT,
3122 "Unable to reset decoder: nothing attached");
3123 return -ENOTTY;
3124 }
3125
3126 if (!hdw->decoder_ctrl->force_reset) {
3127 pvr2_trace(PVR2_TRACE_INIT,
3128 "Unable to reset decoder: not implemented");
3129 return -ENOTTY;
3130 }
3131
3132 pvr2_trace(PVR2_TRACE_INIT,
3133 "Requesting decoder reset");
3134 hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
3135 return 0;
3136}
3137
3138
e61b6fc5 3139/* Stop / start video stream transport */
07e337ee 3140static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
d855497e
MI		 3141{
3142 int status;
3143 LOCK_TAKE(hdw->ctl_lock); do {
8d364363
MK		 3144 hdw->cmd_buffer[0] =
3145 (runFl ? FX2CMD_STREAMING_ON : FX2CMD_STREAMING_OFF);
a0fd1cb1 3146 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
d855497e
MI		 3147 } while (0); LOCK_GIVE(hdw->ctl_lock);
3148 if (!status) {
3149 hdw->subsys_enabled_mask =
3150 ((hdw->subsys_enabled_mask &
3151 ~(1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) |
3152 (runFl ? (1<<PVR2_SUBSYS_B_USBSTREAM_RUN) : 0));
3153 }
3154 return status;
3155}
3156
3157
3158void pvr2_hdw_get_debug_info(const struct pvr2_hdw *hdw,
3159 struct pvr2_hdw_debug_info *ptr)
3160{
3161 ptr->big_lock_held = hdw->big_lock_held;
3162 ptr->ctl_lock_held = hdw->ctl_lock_held;
3163 ptr->flag_ok = hdw->flag_ok;
3164 ptr->flag_disconnected = hdw->flag_disconnected;
3165 ptr->flag_init_ok = hdw->flag_init_ok;
3166 ptr->flag_streaming_enabled = hdw->flag_streaming_enabled;
3167 ptr->subsys_flags = hdw->subsys_enabled_mask;
3168 ptr->cmd_debug_state = hdw->cmd_debug_state;
3169 ptr->cmd_code = hdw->cmd_debug_code;
3170 ptr->cmd_debug_write_len = hdw->cmd_debug_write_len;
3171 ptr->cmd_debug_read_len = hdw->cmd_debug_read_len;
3172 ptr->cmd_debug_timeout = hdw->ctl_timeout_flag;
3173 ptr->cmd_debug_write_pend = hdw->ctl_write_pend_flag;
3174 ptr->cmd_debug_read_pend = hdw->ctl_read_pend_flag;
3175 ptr->cmd_debug_rstatus = hdw->ctl_read_urb->status;
3176 ptr->cmd_debug_wstatus = hdw->ctl_read_urb->status;
3177}
3178
3179
3180int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
3181{
3182 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
3183}
3184
3185
3186int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
3187{
3188 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
3189}
3190
3191
3192int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
3193{
3194 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
3195}
3196
3197
3198int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
3199{
3200 u32 cval,nval;
3201 int ret;
3202 if (~msk) {
3203 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
3204 if (ret) return ret;
3205 nval = (cval & ~msk) | (val & msk);
3206 pvr2_trace(PVR2_TRACE_GPIO,
3207 "GPIO direction changing 0x%x:0x%x"
3208 " from 0x%x to 0x%x",
3209 msk,val,cval,nval);
3210 } else {
3211 nval = val;
3212 pvr2_trace(PVR2_TRACE_GPIO,
3213 "GPIO direction changing to 0x%x",nval);
3214 }
3215 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
3216}
3217
3218
3219int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
3220{
3221 u32 cval,nval;
3222 int ret;
3223 if (~msk) {
3224 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
3225 if (ret) return ret;
3226 nval = (cval & ~msk) | (val & msk);
3227 pvr2_trace(PVR2_TRACE_GPIO,
3228 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
3229 msk,val,cval,nval);
3230 } else {
3231 nval = val;
3232 pvr2_trace(PVR2_TRACE_GPIO,
3233 "GPIO output changing to 0x%x",nval);
3234 }
3235 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
3236}
3237
3238
e61b6fc5 3239/* Find I2C address of eeprom */
07e337ee 3240static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
d855497e
MI		 3241{
3242 int result;
3243 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 3244 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 3245 result = pvr2_send_request(hdw,
3246 hdw->cmd_buffer,1,
3247 hdw->cmd_buffer,1);
3248 if (result < 0) break;
3249 result = hdw->cmd_buffer[0];
3250 } while(0); LOCK_GIVE(hdw->ctl_lock);
3251 return result;
3252}
3253
3254
32ffa9ae 3255int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
201f5c9c 3256 u32 chip_id, u64 reg_id,
32ffa9ae
MI		 3257 int setFl,u32 *val_ptr)
3258{
3259#ifdef CONFIG_VIDEO_ADV_DEBUG
3260 struct list_head *item;
3261 struct pvr2_i2c_client *cp;
3262 struct v4l2_register req;
6d98816f
MI		 3263 int stat = 0;
3264 int okFl = 0;
32ffa9ae 3265
201f5c9c
MI		 3266 if (!capable(CAP_SYS_ADMIN)) return -EPERM;
3267
32ffa9ae
MI		 3268 req.i2c_id = chip_id;
3269 req.reg = reg_id;
3270 if (setFl) req.val = *val_ptr;
3271 mutex_lock(&hdw->i2c_list_lock); do {
3272 list_for_each(item,&hdw->i2c_clients) {
3273 cp = list_entry(item,struct pvr2_i2c_client,list);
3274 if (cp->client->driver->id != chip_id) continue;
3275 stat = pvr2_i2c_client_cmd(
52ebc763
TP		 3276 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
3277 VIDIOC_DBG_G_REGISTER),&req);
32ffa9ae 3278 if (!setFl) *val_ptr = req.val;
6d98816f
MI		 3279 okFl = !0;
3280 break;
32ffa9ae
MI		 3281 }
3282 } while (0); mutex_unlock(&hdw->i2c_list_lock);
6d98816f
MI		 3283 if (okFl) {
3284 return stat;
3285 }
32ffa9ae
MI		 3286 return -EINVAL;
3287#else
3288 return -ENOSYS;
3289#endif
3290}
3291
3292
d855497e
MI		 3293/*
3294 Stuff for Emacs to see, in order to encourage consistent editing style:
3295 *** Local Variables: ***
3296 *** mode: c ***
3297 *** fill-column: 75 ***
3298 *** tab-width: 8 ***
3299 *** c-basic-offset: 8 ***
3300 *** End: ***
3301 */
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